takashi kadono / Mbed OS Nucleo446_SSD1331

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Dependencies:   ssd1331

mbed-os/targets/TARGET_ARM_SSG/TARGET_BEETLE/spi_def.h@3:f3764f852aa8, 2018-10-11 (annotated)

Committer:
kadonotakashi
Date:
Thu Oct 11 02:27:46 2018 +0000
Revision:
3:f3764f852aa8
Parent:
0:8fdf9a60065b 
Nucreo 446 + SSD1331 test version;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kadonotakashi 0:8fdf9a60065b 1 /* mbed Microcontroller Library
kadonotakashi 0:8fdf9a60065b 2 * Copyright (c) 2015 ARM Limited
kadonotakashi 0:8fdf9a60065b 3 *
kadonotakashi 0:8fdf9a60065b 4 * Licensed under the Apache License, Version 2.0 (the "License");
kadonotakashi 0:8fdf9a60065b 5 * you may not use this file except in compliance with the License.
kadonotakashi 0:8fdf9a60065b 6 * You may obtain a copy of the License at
kadonotakashi 0:8fdf9a60065b 7 *
kadonotakashi 0:8fdf9a60065b 8 * http://www.apache.org/licenses/LICENSE-2.0
kadonotakashi 0:8fdf9a60065b 9 *
kadonotakashi 0:8fdf9a60065b 10 * Unless required by applicable law or agreed to in writing, software
kadonotakashi 0:8fdf9a60065b 11 * distributed under the License is distributed on an "AS IS" BASIS,
kadonotakashi 0:8fdf9a60065b 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
kadonotakashi 0:8fdf9a60065b 13 * See the License for the specific language governing permissions and
kadonotakashi 0:8fdf9a60065b 14 * limitations under the License.
kadonotakashi 0:8fdf9a60065b 15 */
kadonotakashi 0:8fdf9a60065b 16 /*
kadonotakashi 0:8fdf9a60065b 17 * SSP interface Support
kadonotakashi 0:8fdf9a60065b 18 * =====================
kadonotakashi 0:8fdf9a60065b 19 */
kadonotakashi 0:8fdf9a60065b 20
kadonotakashi 0:8fdf9a60065b 21 #ifndef MBED_SPI_DEF_H
kadonotakashi 0:8fdf9a60065b 22 #define MBED_SPI_DEF_H
kadonotakashi 0:8fdf9a60065b 23
kadonotakashi 0:8fdf9a60065b 24 #include <stdint.h> /* standard types definitions */
kadonotakashi 0:8fdf9a60065b 25
kadonotakashi 0:8fdf9a60065b 26 #define Module_ID 0x00090108
kadonotakashi 0:8fdf9a60065b 27
kadonotakashi 0:8fdf9a60065b 28 typedef struct beetle_spi
kadonotakashi 0:8fdf9a60065b 29 {
kadonotakashi 0:8fdf9a60065b 30 __IO uint32_t CONFIG; /* 0x00 RW Configuration Register */
kadonotakashi 0:8fdf9a60065b 31 __I uint32_t IRQ_STATUS; /* 0x04 RO Interrupt Status Register*/
kadonotakashi 0:8fdf9a60065b 32 __O uint32_t IRQ_ENABLE; /* 0x08 WO Interrupt Enable Register*/
kadonotakashi 0:8fdf9a60065b 33 __O uint32_t IRQ_DISABLE; /* 0x0C WO Interrupt Disable Register */
kadonotakashi 0:8fdf9a60065b 34 __I uint32_t IRQ_MASK; /* 0x10 RO Interrupt Mask Register */
kadonotakashi 0:8fdf9a60065b 35 __IO uint32_t SPI_ENABLE; /* 0x14 RW SPI Enable Register */
kadonotakashi 0:8fdf9a60065b 36 __IO uint32_t DELAY; /* 0x18 RW Delay Register */
kadonotakashi 0:8fdf9a60065b 37 __O uint32_t TX_DATA; /* 0x1C WO Transmit Data Register */
kadonotakashi 0:8fdf9a60065b 38 __I uint32_t RX_DATA; /* 0x20 RO Receive Data Register */
kadonotakashi 0:8fdf9a60065b 39 __IO uint32_t SLAVE_IDLE_COUNT; /* 0x24 RW Slave Idle Count Register */
kadonotakashi 0:8fdf9a60065b 40 __IO uint32_t TX_THRESHOLD; /* 0x28 RW TX Threshold Register */
kadonotakashi 0:8fdf9a60065b 41 __IO uint32_t RX_THRESHOLD; /* 0x2C RW RX Threshold Register */
kadonotakashi 0:8fdf9a60065b 42 uint32_t reserved[208];
kadonotakashi 0:8fdf9a60065b 43 __I uint32_t MID; /* 0xFC RO Module ID Register */
kadonotakashi 0:8fdf9a60065b 44 }SPI_TypeDef;
kadonotakashi 0:8fdf9a60065b 45
kadonotakashi 0:8fdf9a60065b 46
kadonotakashi 0:8fdf9a60065b 47 #define SPI0_BASE (0x4000C000ul) /* Shield Header SPI Base Address */
kadonotakashi 0:8fdf9a60065b 48 #define SPI1_BASE (0x4000D000ul) /* ADC SPI Base Address */
kadonotakashi 0:8fdf9a60065b 49
kadonotakashi 0:8fdf9a60065b 50 #define SHIELD_SPI ((SPI_TypeDef *) SPI0_BASE )
kadonotakashi 0:8fdf9a60065b 51 #define ADC_SPI ((SPI_TypeDef *) SPI1_BASE )
kadonotakashi 0:8fdf9a60065b 52
kadonotakashi 0:8fdf9a60065b 53 /* Configuration Register Bit Masks */
kadonotakashi 0:8fdf9a60065b 54 #define CONFIG_MSEL 0x00001 // Bit [00] MSEL Mode Select
kadonotakashi 0:8fdf9a60065b 55 #define CONFIG_CPOL 0x00002 // Bit [01] CPOL External Clock Edge
kadonotakashi 0:8fdf9a60065b 56 #define CONFIG_CPHA 0x00004 // Bit [02] CPHA Clock Phase
kadonotakashi 0:8fdf9a60065b 57 #define CONFIG_MBRD 0x00038 // Bits [05:03] MBRD Master Baud Rate Divisor (2 to 256)
kadonotakashi 0:8fdf9a60065b 58 #define CONFIG_MBRD_0 0x00008
kadonotakashi 0:8fdf9a60065b 59 #define CONFIG_MBRD_1 0x00010
kadonotakashi 0:8fdf9a60065b 60 #define CONFIG_MBRD_2 0x00020
kadonotakashi 0:8fdf9a60065b 61 #define CONFIG_MBRD_SHIFT 3
kadonotakashi 0:8fdf9a60065b 62 #define CONFIG_TWS 0x000C0 // Bits [07:06] TWS Transfer Word Size
kadonotakashi 0:8fdf9a60065b 63 #define CONFIG_TWS_0 0x00000
kadonotakashi 0:8fdf9a60065b 64 #define CONFIG_TWS_1 0x00040
kadonotakashi 0:8fdf9a60065b 65 #define CONFIG_MRCS 0x00100 // Bit [08] MRCS Reference Clock Select
kadonotakashi 0:8fdf9a60065b 66 #define CONFIG_PSD 0x00200 // Bit [09] PSD Peripheral Select Decode
kadonotakashi 0:8fdf9a60065b 67 #define CONFIG_PCSL 0x03C00 // Bits [13:10] PCSL Peripheral Chip Select Lines (master mode only)
kadonotakashi 0:8fdf9a60065b 68 #define CONFIG_MCSE 0x04000 // Bit [14] MCSE Manual Chip Select Enable
kadonotakashi 0:8fdf9a60065b 69 #define CONFIG_MSE 0x08000 // Bit [15] MSE Manual Start Enable
kadonotakashi 0:8fdf9a60065b 70 #define CONFIG_MSC 0x10000 // Bit [16] MSC Manual Start Command
kadonotakashi 0:8fdf9a60065b 71 #define CONFIG_MFGE 0x20000 // Bit [17] MFGE Mode Fail Generation Enable
kadonotakashi 0:8fdf9a60065b 72 #define CONFIG_SPSE 0x40000 // Bit [18] SPSE Sample Point Shift Enable
kadonotakashi 0:8fdf9a60065b 73
kadonotakashi 0:8fdf9a60065b 74 /* Interrupt Status Register Bit Masks */
kadonotakashi 0:8fdf9a60065b 75 #define IRQ_STATUS_ROF 0x01 // Bit [00] ROF RX FIFO Overflow
kadonotakashi 0:8fdf9a60065b 76 #define IRQ_STATUS_MF 0x02 // Bit [01] MF Mode Fail
kadonotakashi 0:8fdf9a60065b 77 #define IRQ_STATUS_TNF 0x04 // Bit [02] TNF TX FIFO Not Full (current FIFO status)
kadonotakashi 0:8fdf9a60065b 78 #define IRQ_STATUS_TF 0x08 // Bit [03] TF TX FIFO Full (current FIFO status)
kadonotakashi 0:8fdf9a60065b 79 #define IRQ_STATUS_RNE 0x10 // Bit [04] RNE RX FIFO Not Empty (current FIFO status)
kadonotakashi 0:8fdf9a60065b 80 #define IRQ_STATUS_RF 0x20 // Bit [05] RF RX FIFO Full (current FIFO status)
kadonotakashi 0:8fdf9a60065b 81 #define IRQ_STATUS_TUF 0x40 // Bit [06] TUF TX FIFO Underflow
kadonotakashi 0:8fdf9a60065b 82
kadonotakashi 0:8fdf9a60065b 83 /* Interrupt Enable Register Bit Masks */
kadonotakashi 0:8fdf9a60065b 84 #define IRQ_ENABLE_ROFE 0x01 // Bit [00] ROFE RX FIFO Overflow Enable
kadonotakashi 0:8fdf9a60065b 85 #define IRQ_ENABLE_MFE 0x02 // Bit [01] MFE Mode Fail Enable
kadonotakashi 0:8fdf9a60065b 86 #define IRQ_ENABLE_TNFE 0x04 // Bit [02] TNFE TX FIFO Not Full Enable
kadonotakashi 0:8fdf9a60065b 87 #define IRQ_ENABLE_TFE 0x08 // Bit [03] TFE TX FIFO Full Enable
kadonotakashi 0:8fdf9a60065b 88 #define IRQ_ENABLE_RNEE 0x10 // Bit [04] RNEE RX FIFO Not Empty Enable
kadonotakashi 0:8fdf9a60065b 89 #define IRQ_ENABLE_RFE 0x20 // Bit [05] RFE RX FIFO Full Enable
kadonotakashi 0:8fdf9a60065b 90 #define IRQ_ENABLE_TUFE 0x40 // Bit [06] TUFE TX FIFO Underflow Enable
kadonotakashi 0:8fdf9a60065b 91
kadonotakashi 0:8fdf9a60065b 92 /* Interrupt Disable Register Bit Masks */
kadonotakashi 0:8fdf9a60065b 93 #define IRQ_DISABLE_ROFD 0x01 // Bit [00] ROFD RX FIFO Overflow Disable
kadonotakashi 0:8fdf9a60065b 94 #define IRQ_DISABLE_MFD 0x02 // Bit [01] MFD Mode Fail Disable
kadonotakashi 0:8fdf9a60065b 95 #define IRQ_DISABLE_TNFD 0x04 // Bit [02] TNFD TX FIFO Not Full Disable
kadonotakashi 0:8fdf9a60065b 96 #define IRQ_DISABLE_TFD 0x08 // Bit [03] TFD TX FIFO Full Disable
kadonotakashi 0:8fdf9a60065b 97 #define IRQ_DISABLE_RNED 0x10 // Bit [04] RNED RX FIFO Not Empty Disable
kadonotakashi 0:8fdf9a60065b 98 #define IRQ_DISABLE_RFD 0x20 // Bit [05] RFD RX FIFO Full Disable
kadonotakashi 0:8fdf9a60065b 99 #define IRQ_DISABLE_TUFD 0x40 // Bit [06] TUFD TX FIFO Underflow Disable
kadonotakashi 0:8fdf9a60065b 100
kadonotakashi 0:8fdf9a60065b 101 /* Interrupt Mask Register Bit Masks */
kadonotakashi 0:8fdf9a60065b 102 #define IRQ_MASK_ROFM 0x01 // Bit [00] ROFM RX FIFO Overflow Mask
kadonotakashi 0:8fdf9a60065b 103 #define IRQ_MASK_MFM 0x02 // Bit [01] MFM Mode Fail Mask
kadonotakashi 0:8fdf9a60065b 104 #define IRQ_MASK_TNFM 0x04 // Bit [02] TNFM TX FIFO Not Full Mask
kadonotakashi 0:8fdf9a60065b 105 #define IRQ_MASK_TFM 0x08 // Bit [03] TFM TX FIFO Full Mask
kadonotakashi 0:8fdf9a60065b 106 #define IRQ_MASK_RNEM 0x10 // Bit [04] RNEM RX FIFO Not Empty Mask
kadonotakashi 0:8fdf9a60065b 107 #define IRQ_MASK_RFM 0x20 // Bit [05] RFM RX FIFO Full Mask
kadonotakashi 0:8fdf9a60065b 108 #define IRQ_MASK_TUFM 0x40 // Bit [06] TUFM TX FIFO Underflow Mask
kadonotakashi 0:8fdf9a60065b 109
kadonotakashi 0:8fdf9a60065b 110 /* SPI Enable Register Bit Masks */
kadonotakashi 0:8fdf9a60065b 111 #define SPI_ENABLE_SPIE 0x01 // Bit [00] SPIE SPI Enable
kadonotakashi 0:8fdf9a60065b 112
kadonotakashi 0:8fdf9a60065b 113 /* Delay Register Bit Masks */
kadonotakashi 0:8fdf9a60065b 114 #define DELAY_D_INIT 0x000000FF // Bits [07:00] D_INIT Delay Init
kadonotakashi 0:8fdf9a60065b 115 #define DELAY_D_AFTER 0x0000FF00 // Bits [15:08] D_AFTER Delay After
kadonotakashi 0:8fdf9a60065b 116 #define DELAY_D_BTWN 0x00FF0000 // Bits [23:16] D_BTWN Delay Between
kadonotakashi 0:8fdf9a60065b 117 #define DELAY_D_NSS 0xFF000000 // Bits [31:24] D_NSS Delay NSS
kadonotakashi 0:8fdf9a60065b 118
kadonotakashi 0:8fdf9a60065b 119 /* Transmit Data Register Bit Masks */
kadonotakashi 0:8fdf9a60065b 120 #define TX_DATA_TDATA 0xFF
kadonotakashi 0:8fdf9a60065b 121
kadonotakashi 0:8fdf9a60065b 122 /* Receive Data Register Bit Masks */
kadonotakashi 0:8fdf9a60065b 123 #define RX_DATA_RDATA 0xFF
kadonotakashi 0:8fdf9a60065b 124
kadonotakashi 0:8fdf9a60065b 125 /* Slave Idle Count Register Bit Masks */
kadonotakashi 0:8fdf9a60065b 126 #define SLAVE_IDLE_COUNT_SICNT 0xFF // Bits [07:00] SICNT Slave Idle Count
kadonotakashi 0:8fdf9a60065b 127
kadonotakashi 0:8fdf9a60065b 128 /* TX Threshold Register Bit Masks */
kadonotakashi 0:8fdf9a60065b 129 #define TX_THRESHOLD_TTRSH 0x07 // Bits [N:00] TTRSH TX Threshold
kadonotakashi 0:8fdf9a60065b 130
kadonotakashi 0:8fdf9a60065b 131 /* RX Threshold Register Bit Masks */
kadonotakashi 0:8fdf9a60065b 132 #define RX_THRESHOLD_RTRSH 0x07 // Bits [N:00] RTRSH RX Threshold
kadonotakashi 0:8fdf9a60065b 133
kadonotakashi 0:8fdf9a60065b 134 #endif