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targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_dac.h@563:9f26fcd0c9ce, 2015-06-09 (annotated)

Committer:
mbed_official
Date:
Tue Jun 09 15:30:08 2015 +0100
Revision:
563:9f26fcd0c9ce
Parent:
525:c320967f86b9 
Synchronized with git revision a140fc60a6f74003a3d46c4ce8bf8c742148b9fd



Full URL: https://github.com/mbedmicro/mbed/commit/a140fc60a6f74003a3d46c4ce8bf8c742148b9fd/

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 525:c320967f86b9 1 /**************************************************************************//**
mbed_official 525:c320967f86b9 2 * @file efm32lg_dac.h
mbed_official 525:c320967f86b9 3 * @brief EFM32LG_DAC register and bit field definitions
mbed_official 525:c320967f86b9 4 * @version 3.20.6
mbed_official 525:c320967f86b9 5 ******************************************************************************
mbed_official 525:c320967f86b9 6 * @section License
mbed_official 525:c320967f86b9 7 * <b>(C) Copyright 2014 Silicon Laboratories, Inc. http://www.silabs.com</b>
mbed_official 525:c320967f86b9 8 ******************************************************************************
mbed_official 525:c320967f86b9 9 *
mbed_official 525:c320967f86b9 10 * Permission is granted to anyone to use this software for any purpose,
mbed_official 525:c320967f86b9 11 * including commercial applications, and to alter it and redistribute it
mbed_official 525:c320967f86b9 12 * freely, subject to the following restrictions:
mbed_official 525:c320967f86b9 13 *
mbed_official 525:c320967f86b9 14 * 1. The origin of this software must not be misrepresented; you must not
mbed_official 525:c320967f86b9 15 * claim that you wrote the original software.@n
mbed_official 525:c320967f86b9 16 * 2. Altered source versions must be plainly marked as such, and must not be
mbed_official 525:c320967f86b9 17 * misrepresented as being the original software.@n
mbed_official 525:c320967f86b9 18 * 3. This notice may not be removed or altered from any source distribution.
mbed_official 525:c320967f86b9 19 *
mbed_official 525:c320967f86b9 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
mbed_official 525:c320967f86b9 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
mbed_official 525:c320967f86b9 22 * providing the Software "AS IS", with no express or implied warranties of any
mbed_official 525:c320967f86b9 23 * kind, including, but not limited to, any implied warranties of
mbed_official 525:c320967f86b9 24 * merchantability or fitness for any particular purpose or warranties against
mbed_official 525:c320967f86b9 25 * infringement of any proprietary rights of a third party.
mbed_official 525:c320967f86b9 26 *
mbed_official 525:c320967f86b9 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
mbed_official 525:c320967f86b9 28 * incidental, or special damages, or any other relief, or for any claim by
mbed_official 525:c320967f86b9 29 * any third party, arising from your use of this Software.
mbed_official 525:c320967f86b9 30 *
mbed_official 525:c320967f86b9 31 *****************************************************************************/
mbed_official 525:c320967f86b9 32 /**************************************************************************//**
mbed_official 525:c320967f86b9 33 * @defgroup EFM32LG_DAC
mbed_official 525:c320967f86b9 34 * @{
mbed_official 525:c320967f86b9 35 * @brief EFM32LG_DAC Register Declaration
mbed_official 525:c320967f86b9 36 *****************************************************************************/
mbed_official 525:c320967f86b9 37 typedef struct
mbed_official 525:c320967f86b9 38 {
mbed_official 525:c320967f86b9 39 __IO uint32_t CTRL; /**< Control Register */
mbed_official 525:c320967f86b9 40 __I uint32_t STATUS; /**< Status Register */
mbed_official 525:c320967f86b9 41 __IO uint32_t CH0CTRL; /**< Channel 0 Control Register */
mbed_official 525:c320967f86b9 42 __IO uint32_t CH1CTRL; /**< Channel 1 Control Register */
mbed_official 525:c320967f86b9 43 __IO uint32_t IEN; /**< Interrupt Enable Register */
mbed_official 525:c320967f86b9 44 __I uint32_t IF; /**< Interrupt Flag Register */
mbed_official 525:c320967f86b9 45 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
mbed_official 525:c320967f86b9 46 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
mbed_official 525:c320967f86b9 47 __IO uint32_t CH0DATA; /**< Channel 0 Data Register */
mbed_official 525:c320967f86b9 48 __IO uint32_t CH1DATA; /**< Channel 1 Data Register */
mbed_official 525:c320967f86b9 49 __IO uint32_t COMBDATA; /**< Combined Data Register */
mbed_official 525:c320967f86b9 50 __IO uint32_t CAL; /**< Calibration Register */
mbed_official 525:c320967f86b9 51 __IO uint32_t BIASPROG; /**< Bias Programming Register */
mbed_official 525:c320967f86b9 52 uint32_t RESERVED0[8]; /**< Reserved for future use **/
mbed_official 525:c320967f86b9 53 __IO uint32_t OPACTRL; /**< Operational Amplifier Control Register */
mbed_official 525:c320967f86b9 54 __IO uint32_t OPAOFFSET; /**< Operational Amplifier Offset Register */
mbed_official 525:c320967f86b9 55 __IO uint32_t OPA0MUX; /**< Operational Amplifier Mux Configuration Register */
mbed_official 525:c320967f86b9 56 __IO uint32_t OPA1MUX; /**< Operational Amplifier Mux Configuration Register */
mbed_official 525:c320967f86b9 57 __IO uint32_t OPA2MUX; /**< Operational Amplifier Mux Configuration Register */
mbed_official 525:c320967f86b9 58 } DAC_TypeDef; /** @} */
mbed_official 525:c320967f86b9 59
mbed_official 525:c320967f86b9 60 /**************************************************************************//**
mbed_official 525:c320967f86b9 61 * @defgroup EFM32LG_DAC_BitFields
mbed_official 525:c320967f86b9 62 * @{
mbed_official 525:c320967f86b9 63 *****************************************************************************/
mbed_official 525:c320967f86b9 64
mbed_official 525:c320967f86b9 65 /* Bit fields for DAC CTRL */
mbed_official 525:c320967f86b9 66 #define _DAC_CTRL_RESETVALUE 0x00000010UL /**< Default value for DAC_CTRL */
mbed_official 525:c320967f86b9 67 #define _DAC_CTRL_MASK 0x003703FFUL /**< Mask for DAC_CTRL */
mbed_official 525:c320967f86b9 68 #define DAC_CTRL_DIFF (0x1UL << 0) /**< Differential Mode */
mbed_official 525:c320967f86b9 69 #define _DAC_CTRL_DIFF_SHIFT 0 /**< Shift value for DAC_DIFF */
mbed_official 525:c320967f86b9 70 #define _DAC_CTRL_DIFF_MASK 0x1UL /**< Bit mask for DAC_DIFF */
mbed_official 525:c320967f86b9 71 #define _DAC_CTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
mbed_official 525:c320967f86b9 72 #define DAC_CTRL_DIFF_DEFAULT (_DAC_CTRL_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CTRL */
mbed_official 525:c320967f86b9 73 #define DAC_CTRL_SINEMODE (0x1UL << 1) /**< Sine Mode */
mbed_official 525:c320967f86b9 74 #define _DAC_CTRL_SINEMODE_SHIFT 1 /**< Shift value for DAC_SINEMODE */
mbed_official 525:c320967f86b9 75 #define _DAC_CTRL_SINEMODE_MASK 0x2UL /**< Bit mask for DAC_SINEMODE */
mbed_official 525:c320967f86b9 76 #define _DAC_CTRL_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
mbed_official 525:c320967f86b9 77 #define DAC_CTRL_SINEMODE_DEFAULT (_DAC_CTRL_SINEMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_CTRL */
mbed_official 525:c320967f86b9 78 #define _DAC_CTRL_CONVMODE_SHIFT 2 /**< Shift value for DAC_CONVMODE */
mbed_official 525:c320967f86b9 79 #define _DAC_CTRL_CONVMODE_MASK 0xCUL /**< Bit mask for DAC_CONVMODE */
mbed_official 525:c320967f86b9 80 #define _DAC_CTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
mbed_official 525:c320967f86b9 81 #define _DAC_CTRL_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for DAC_CTRL */
mbed_official 525:c320967f86b9 82 #define _DAC_CTRL_CONVMODE_SAMPLEHOLD 0x00000001UL /**< Mode SAMPLEHOLD for DAC_CTRL */
mbed_official 525:c320967f86b9 83 #define _DAC_CTRL_CONVMODE_SAMPLEOFF 0x00000002UL /**< Mode SAMPLEOFF for DAC_CTRL */
mbed_official 525:c320967f86b9 84 #define DAC_CTRL_CONVMODE_DEFAULT (_DAC_CTRL_CONVMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for DAC_CTRL */
mbed_official 525:c320967f86b9 85 #define DAC_CTRL_CONVMODE_CONTINUOUS (_DAC_CTRL_CONVMODE_CONTINUOUS << 2) /**< Shifted mode CONTINUOUS for DAC_CTRL */
mbed_official 525:c320967f86b9 86 #define DAC_CTRL_CONVMODE_SAMPLEHOLD (_DAC_CTRL_CONVMODE_SAMPLEHOLD << 2) /**< Shifted mode SAMPLEHOLD for DAC_CTRL */
mbed_official 525:c320967f86b9 87 #define DAC_CTRL_CONVMODE_SAMPLEOFF (_DAC_CTRL_CONVMODE_SAMPLEOFF << 2) /**< Shifted mode SAMPLEOFF for DAC_CTRL */
mbed_official 525:c320967f86b9 88 #define _DAC_CTRL_OUTMODE_SHIFT 4 /**< Shift value for DAC_OUTMODE */
mbed_official 525:c320967f86b9 89 #define _DAC_CTRL_OUTMODE_MASK 0x30UL /**< Bit mask for DAC_OUTMODE */
mbed_official 525:c320967f86b9 90 #define _DAC_CTRL_OUTMODE_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_CTRL */
mbed_official 525:c320967f86b9 91 #define _DAC_CTRL_OUTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for DAC_CTRL */
mbed_official 525:c320967f86b9 92 #define _DAC_CTRL_OUTMODE_PIN 0x00000001UL /**< Mode PIN for DAC_CTRL */
mbed_official 525:c320967f86b9 93 #define _DAC_CTRL_OUTMODE_ADC 0x00000002UL /**< Mode ADC for DAC_CTRL */
mbed_official 525:c320967f86b9 94 #define _DAC_CTRL_OUTMODE_PINADC 0x00000003UL /**< Mode PINADC for DAC_CTRL */
mbed_official 525:c320967f86b9 95 #define DAC_CTRL_OUTMODE_DISABLE (_DAC_CTRL_OUTMODE_DISABLE << 4) /**< Shifted mode DISABLE for DAC_CTRL */
mbed_official 525:c320967f86b9 96 #define DAC_CTRL_OUTMODE_DEFAULT (_DAC_CTRL_OUTMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_CTRL */
mbed_official 525:c320967f86b9 97 #define DAC_CTRL_OUTMODE_PIN (_DAC_CTRL_OUTMODE_PIN << 4) /**< Shifted mode PIN for DAC_CTRL */
mbed_official 525:c320967f86b9 98 #define DAC_CTRL_OUTMODE_ADC (_DAC_CTRL_OUTMODE_ADC << 4) /**< Shifted mode ADC for DAC_CTRL */
mbed_official 525:c320967f86b9 99 #define DAC_CTRL_OUTMODE_PINADC (_DAC_CTRL_OUTMODE_PINADC << 4) /**< Shifted mode PINADC for DAC_CTRL */
mbed_official 525:c320967f86b9 100 #define DAC_CTRL_OUTENPRS (0x1UL << 6) /**< PRS Controlled Output Enable */
mbed_official 525:c320967f86b9 101 #define _DAC_CTRL_OUTENPRS_SHIFT 6 /**< Shift value for DAC_OUTENPRS */
mbed_official 525:c320967f86b9 102 #define _DAC_CTRL_OUTENPRS_MASK 0x40UL /**< Bit mask for DAC_OUTENPRS */
mbed_official 525:c320967f86b9 103 #define _DAC_CTRL_OUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
mbed_official 525:c320967f86b9 104 #define DAC_CTRL_OUTENPRS_DEFAULT (_DAC_CTRL_OUTENPRS_DEFAULT << 6) /**< Shifted mode DEFAULT for DAC_CTRL */
mbed_official 525:c320967f86b9 105 #define DAC_CTRL_CH0PRESCRST (0x1UL << 7) /**< Channel 0 Start Reset Prescaler */
mbed_official 525:c320967f86b9 106 #define _DAC_CTRL_CH0PRESCRST_SHIFT 7 /**< Shift value for DAC_CH0PRESCRST */
mbed_official 525:c320967f86b9 107 #define _DAC_CTRL_CH0PRESCRST_MASK 0x80UL /**< Bit mask for DAC_CH0PRESCRST */
mbed_official 525:c320967f86b9 108 #define _DAC_CTRL_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
mbed_official 525:c320967f86b9 109 #define DAC_CTRL_CH0PRESCRST_DEFAULT (_DAC_CTRL_CH0PRESCRST_DEFAULT << 7) /**< Shifted mode DEFAULT for DAC_CTRL */
mbed_official 525:c320967f86b9 110 #define _DAC_CTRL_REFSEL_SHIFT 8 /**< Shift value for DAC_REFSEL */
mbed_official 525:c320967f86b9 111 #define _DAC_CTRL_REFSEL_MASK 0x300UL /**< Bit mask for DAC_REFSEL */
mbed_official 525:c320967f86b9 112 #define _DAC_CTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
mbed_official 525:c320967f86b9 113 #define _DAC_CTRL_REFSEL_1V25 0x00000000UL /**< Mode 1V25 for DAC_CTRL */
mbed_official 525:c320967f86b9 114 #define _DAC_CTRL_REFSEL_2V5 0x00000001UL /**< Mode 2V5 for DAC_CTRL */
mbed_official 525:c320967f86b9 115 #define _DAC_CTRL_REFSEL_VDD 0x00000002UL /**< Mode VDD for DAC_CTRL */
mbed_official 525:c320967f86b9 116 #define DAC_CTRL_REFSEL_DEFAULT (_DAC_CTRL_REFSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_CTRL */
mbed_official 525:c320967f86b9 117 #define DAC_CTRL_REFSEL_1V25 (_DAC_CTRL_REFSEL_1V25 << 8) /**< Shifted mode 1V25 for DAC_CTRL */
mbed_official 525:c320967f86b9 118 #define DAC_CTRL_REFSEL_2V5 (_DAC_CTRL_REFSEL_2V5 << 8) /**< Shifted mode 2V5 for DAC_CTRL */
mbed_official 525:c320967f86b9 119 #define DAC_CTRL_REFSEL_VDD (_DAC_CTRL_REFSEL_VDD << 8) /**< Shifted mode VDD for DAC_CTRL */
mbed_official 525:c320967f86b9 120 #define _DAC_CTRL_PRESC_SHIFT 16 /**< Shift value for DAC_PRESC */
mbed_official 525:c320967f86b9 121 #define _DAC_CTRL_PRESC_MASK 0x70000UL /**< Bit mask for DAC_PRESC */
mbed_official 525:c320967f86b9 122 #define _DAC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
mbed_official 525:c320967f86b9 123 #define _DAC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for DAC_CTRL */
mbed_official 525:c320967f86b9 124 #define DAC_CTRL_PRESC_DEFAULT (_DAC_CTRL_PRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for DAC_CTRL */
mbed_official 525:c320967f86b9 125 #define DAC_CTRL_PRESC_NODIVISION (_DAC_CTRL_PRESC_NODIVISION << 16) /**< Shifted mode NODIVISION for DAC_CTRL */
mbed_official 525:c320967f86b9 126 #define _DAC_CTRL_REFRSEL_SHIFT 20 /**< Shift value for DAC_REFRSEL */
mbed_official 525:c320967f86b9 127 #define _DAC_CTRL_REFRSEL_MASK 0x300000UL /**< Bit mask for DAC_REFRSEL */
mbed_official 525:c320967f86b9 128 #define _DAC_CTRL_REFRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
mbed_official 525:c320967f86b9 129 #define _DAC_CTRL_REFRSEL_8CYCLES 0x00000000UL /**< Mode 8CYCLES for DAC_CTRL */
mbed_official 525:c320967f86b9 130 #define _DAC_CTRL_REFRSEL_16CYCLES 0x00000001UL /**< Mode 16CYCLES for DAC_CTRL */
mbed_official 525:c320967f86b9 131 #define _DAC_CTRL_REFRSEL_32CYCLES 0x00000002UL /**< Mode 32CYCLES for DAC_CTRL */
mbed_official 525:c320967f86b9 132 #define _DAC_CTRL_REFRSEL_64CYCLES 0x00000003UL /**< Mode 64CYCLES for DAC_CTRL */
mbed_official 525:c320967f86b9 133 #define DAC_CTRL_REFRSEL_DEFAULT (_DAC_CTRL_REFRSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for DAC_CTRL */
mbed_official 525:c320967f86b9 134 #define DAC_CTRL_REFRSEL_8CYCLES (_DAC_CTRL_REFRSEL_8CYCLES << 20) /**< Shifted mode 8CYCLES for DAC_CTRL */
mbed_official 525:c320967f86b9 135 #define DAC_CTRL_REFRSEL_16CYCLES (_DAC_CTRL_REFRSEL_16CYCLES << 20) /**< Shifted mode 16CYCLES for DAC_CTRL */
mbed_official 525:c320967f86b9 136 #define DAC_CTRL_REFRSEL_32CYCLES (_DAC_CTRL_REFRSEL_32CYCLES << 20) /**< Shifted mode 32CYCLES for DAC_CTRL */
mbed_official 525:c320967f86b9 137 #define DAC_CTRL_REFRSEL_64CYCLES (_DAC_CTRL_REFRSEL_64CYCLES << 20) /**< Shifted mode 64CYCLES for DAC_CTRL */
mbed_official 525:c320967f86b9 138
mbed_official 525:c320967f86b9 139 /* Bit fields for DAC STATUS */
mbed_official 525:c320967f86b9 140 #define _DAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for DAC_STATUS */
mbed_official 525:c320967f86b9 141 #define _DAC_STATUS_MASK 0x00000003UL /**< Mask for DAC_STATUS */
mbed_official 525:c320967f86b9 142 #define DAC_STATUS_CH0DV (0x1UL << 0) /**< Channel 0 Data Valid */
mbed_official 525:c320967f86b9 143 #define _DAC_STATUS_CH0DV_SHIFT 0 /**< Shift value for DAC_CH0DV */
mbed_official 525:c320967f86b9 144 #define _DAC_STATUS_CH0DV_MASK 0x1UL /**< Bit mask for DAC_CH0DV */
mbed_official 525:c320967f86b9 145 #define _DAC_STATUS_CH0DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_STATUS */
mbed_official 525:c320967f86b9 146 #define DAC_STATUS_CH0DV_DEFAULT (_DAC_STATUS_CH0DV_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_STATUS */
mbed_official 525:c320967f86b9 147 #define DAC_STATUS_CH1DV (0x1UL << 1) /**< Channel 1 Data Valid */
mbed_official 525:c320967f86b9 148 #define _DAC_STATUS_CH1DV_SHIFT 1 /**< Shift value for DAC_CH1DV */
mbed_official 525:c320967f86b9 149 #define _DAC_STATUS_CH1DV_MASK 0x2UL /**< Bit mask for DAC_CH1DV */
mbed_official 525:c320967f86b9 150 #define _DAC_STATUS_CH1DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_STATUS */
mbed_official 525:c320967f86b9 151 #define DAC_STATUS_CH1DV_DEFAULT (_DAC_STATUS_CH1DV_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_STATUS */
mbed_official 525:c320967f86b9 152
mbed_official 525:c320967f86b9 153 /* Bit fields for DAC CH0CTRL */
mbed_official 525:c320967f86b9 154 #define _DAC_CH0CTRL_RESETVALUE 0x00000000UL /**< Default value for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 155 #define _DAC_CH0CTRL_MASK 0x000000F7UL /**< Mask for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 156 #define DAC_CH0CTRL_EN (0x1UL << 0) /**< Channel 0 Enable */
mbed_official 525:c320967f86b9 157 #define _DAC_CH0CTRL_EN_SHIFT 0 /**< Shift value for DAC_EN */
mbed_official 525:c320967f86b9 158 #define _DAC_CH0CTRL_EN_MASK 0x1UL /**< Bit mask for DAC_EN */
mbed_official 525:c320967f86b9 159 #define _DAC_CH0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 160 #define DAC_CH0CTRL_EN_DEFAULT (_DAC_CH0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 161 #define DAC_CH0CTRL_REFREN (0x1UL << 1) /**< Channel 0 Automatic Refresh Enable */
mbed_official 525:c320967f86b9 162 #define _DAC_CH0CTRL_REFREN_SHIFT 1 /**< Shift value for DAC_REFREN */
mbed_official 525:c320967f86b9 163 #define _DAC_CH0CTRL_REFREN_MASK 0x2UL /**< Bit mask for DAC_REFREN */
mbed_official 525:c320967f86b9 164 #define _DAC_CH0CTRL_REFREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 165 #define DAC_CH0CTRL_REFREN_DEFAULT (_DAC_CH0CTRL_REFREN_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 166 #define DAC_CH0CTRL_PRSEN (0x1UL << 2) /**< Channel 0 PRS Trigger Enable */
mbed_official 525:c320967f86b9 167 #define _DAC_CH0CTRL_PRSEN_SHIFT 2 /**< Shift value for DAC_PRSEN */
mbed_official 525:c320967f86b9 168 #define _DAC_CH0CTRL_PRSEN_MASK 0x4UL /**< Bit mask for DAC_PRSEN */
mbed_official 525:c320967f86b9 169 #define _DAC_CH0CTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 170 #define DAC_CH0CTRL_PRSEN_DEFAULT (_DAC_CH0CTRL_PRSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 171 #define _DAC_CH0CTRL_PRSSEL_SHIFT 4 /**< Shift value for DAC_PRSSEL */
mbed_official 525:c320967f86b9 172 #define _DAC_CH0CTRL_PRSSEL_MASK 0xF0UL /**< Bit mask for DAC_PRSSEL */
mbed_official 525:c320967f86b9 173 #define _DAC_CH0CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 174 #define _DAC_CH0CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 175 #define _DAC_CH0CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 176 #define _DAC_CH0CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 177 #define _DAC_CH0CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 178 #define _DAC_CH0CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 179 #define _DAC_CH0CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 180 #define _DAC_CH0CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 181 #define _DAC_CH0CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 182 #define _DAC_CH0CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 183 #define _DAC_CH0CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 184 #define _DAC_CH0CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 185 #define _DAC_CH0CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 186 #define DAC_CH0CTRL_PRSSEL_DEFAULT (_DAC_CH0CTRL_PRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 187 #define DAC_CH0CTRL_PRSSEL_PRSCH0 (_DAC_CH0CTRL_PRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 188 #define DAC_CH0CTRL_PRSSEL_PRSCH1 (_DAC_CH0CTRL_PRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 189 #define DAC_CH0CTRL_PRSSEL_PRSCH2 (_DAC_CH0CTRL_PRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 190 #define DAC_CH0CTRL_PRSSEL_PRSCH3 (_DAC_CH0CTRL_PRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 191 #define DAC_CH0CTRL_PRSSEL_PRSCH4 (_DAC_CH0CTRL_PRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 192 #define DAC_CH0CTRL_PRSSEL_PRSCH5 (_DAC_CH0CTRL_PRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 193 #define DAC_CH0CTRL_PRSSEL_PRSCH6 (_DAC_CH0CTRL_PRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 194 #define DAC_CH0CTRL_PRSSEL_PRSCH7 (_DAC_CH0CTRL_PRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 195 #define DAC_CH0CTRL_PRSSEL_PRSCH8 (_DAC_CH0CTRL_PRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 196 #define DAC_CH0CTRL_PRSSEL_PRSCH9 (_DAC_CH0CTRL_PRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 197 #define DAC_CH0CTRL_PRSSEL_PRSCH10 (_DAC_CH0CTRL_PRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 198 #define DAC_CH0CTRL_PRSSEL_PRSCH11 (_DAC_CH0CTRL_PRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for DAC_CH0CTRL */
mbed_official 525:c320967f86b9 199
mbed_official 525:c320967f86b9 200 /* Bit fields for DAC CH1CTRL */
mbed_official 525:c320967f86b9 201 #define _DAC_CH1CTRL_RESETVALUE 0x00000000UL /**< Default value for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 202 #define _DAC_CH1CTRL_MASK 0x000000F7UL /**< Mask for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 203 #define DAC_CH1CTRL_EN (0x1UL << 0) /**< Channel 1 Enable */
mbed_official 525:c320967f86b9 204 #define _DAC_CH1CTRL_EN_SHIFT 0 /**< Shift value for DAC_EN */
mbed_official 525:c320967f86b9 205 #define _DAC_CH1CTRL_EN_MASK 0x1UL /**< Bit mask for DAC_EN */
mbed_official 525:c320967f86b9 206 #define _DAC_CH1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 207 #define DAC_CH1CTRL_EN_DEFAULT (_DAC_CH1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 208 #define DAC_CH1CTRL_REFREN (0x1UL << 1) /**< Channel 1 Automatic Refresh Enable */
mbed_official 525:c320967f86b9 209 #define _DAC_CH1CTRL_REFREN_SHIFT 1 /**< Shift value for DAC_REFREN */
mbed_official 525:c320967f86b9 210 #define _DAC_CH1CTRL_REFREN_MASK 0x2UL /**< Bit mask for DAC_REFREN */
mbed_official 525:c320967f86b9 211 #define _DAC_CH1CTRL_REFREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 212 #define DAC_CH1CTRL_REFREN_DEFAULT (_DAC_CH1CTRL_REFREN_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 213 #define DAC_CH1CTRL_PRSEN (0x1UL << 2) /**< Channel 1 PRS Trigger Enable */
mbed_official 525:c320967f86b9 214 #define _DAC_CH1CTRL_PRSEN_SHIFT 2 /**< Shift value for DAC_PRSEN */
mbed_official 525:c320967f86b9 215 #define _DAC_CH1CTRL_PRSEN_MASK 0x4UL /**< Bit mask for DAC_PRSEN */
mbed_official 525:c320967f86b9 216 #define _DAC_CH1CTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 217 #define DAC_CH1CTRL_PRSEN_DEFAULT (_DAC_CH1CTRL_PRSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 218 #define _DAC_CH1CTRL_PRSSEL_SHIFT 4 /**< Shift value for DAC_PRSSEL */
mbed_official 525:c320967f86b9 219 #define _DAC_CH1CTRL_PRSSEL_MASK 0xF0UL /**< Bit mask for DAC_PRSSEL */
mbed_official 525:c320967f86b9 220 #define _DAC_CH1CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 221 #define _DAC_CH1CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 222 #define _DAC_CH1CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 223 #define _DAC_CH1CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 224 #define _DAC_CH1CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 225 #define _DAC_CH1CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 226 #define _DAC_CH1CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 227 #define _DAC_CH1CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 228 #define _DAC_CH1CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 229 #define _DAC_CH1CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 230 #define _DAC_CH1CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 231 #define _DAC_CH1CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 232 #define _DAC_CH1CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 233 #define DAC_CH1CTRL_PRSSEL_DEFAULT (_DAC_CH1CTRL_PRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 234 #define DAC_CH1CTRL_PRSSEL_PRSCH0 (_DAC_CH1CTRL_PRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 235 #define DAC_CH1CTRL_PRSSEL_PRSCH1 (_DAC_CH1CTRL_PRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 236 #define DAC_CH1CTRL_PRSSEL_PRSCH2 (_DAC_CH1CTRL_PRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 237 #define DAC_CH1CTRL_PRSSEL_PRSCH3 (_DAC_CH1CTRL_PRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 238 #define DAC_CH1CTRL_PRSSEL_PRSCH4 (_DAC_CH1CTRL_PRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 239 #define DAC_CH1CTRL_PRSSEL_PRSCH5 (_DAC_CH1CTRL_PRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 240 #define DAC_CH1CTRL_PRSSEL_PRSCH6 (_DAC_CH1CTRL_PRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 241 #define DAC_CH1CTRL_PRSSEL_PRSCH7 (_DAC_CH1CTRL_PRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 242 #define DAC_CH1CTRL_PRSSEL_PRSCH8 (_DAC_CH1CTRL_PRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 243 #define DAC_CH1CTRL_PRSSEL_PRSCH9 (_DAC_CH1CTRL_PRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 244 #define DAC_CH1CTRL_PRSSEL_PRSCH10 (_DAC_CH1CTRL_PRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 245 #define DAC_CH1CTRL_PRSSEL_PRSCH11 (_DAC_CH1CTRL_PRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for DAC_CH1CTRL */
mbed_official 525:c320967f86b9 246
mbed_official 525:c320967f86b9 247 /* Bit fields for DAC IEN */
mbed_official 525:c320967f86b9 248 #define _DAC_IEN_RESETVALUE 0x00000000UL /**< Default value for DAC_IEN */
mbed_official 525:c320967f86b9 249 #define _DAC_IEN_MASK 0x00000033UL /**< Mask for DAC_IEN */
mbed_official 525:c320967f86b9 250 #define DAC_IEN_CH0 (0x1UL << 0) /**< Channel 0 Conversion Complete Interrupt Enable */
mbed_official 525:c320967f86b9 251 #define _DAC_IEN_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */
mbed_official 525:c320967f86b9 252 #define _DAC_IEN_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */
mbed_official 525:c320967f86b9 253 #define _DAC_IEN_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */
mbed_official 525:c320967f86b9 254 #define DAC_IEN_CH0_DEFAULT (_DAC_IEN_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_IEN */
mbed_official 525:c320967f86b9 255 #define DAC_IEN_CH1 (0x1UL << 1) /**< Channel 1 Conversion Complete Interrupt Enable */
mbed_official 525:c320967f86b9 256 #define _DAC_IEN_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */
mbed_official 525:c320967f86b9 257 #define _DAC_IEN_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */
mbed_official 525:c320967f86b9 258 #define _DAC_IEN_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */
mbed_official 525:c320967f86b9 259 #define DAC_IEN_CH1_DEFAULT (_DAC_IEN_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_IEN */
mbed_official 525:c320967f86b9 260 #define DAC_IEN_CH0UF (0x1UL << 4) /**< Channel 0 Conversion Data Underflow Interrupt Enable */
mbed_official 525:c320967f86b9 261 #define _DAC_IEN_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */
mbed_official 525:c320967f86b9 262 #define _DAC_IEN_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */
mbed_official 525:c320967f86b9 263 #define _DAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */
mbed_official 525:c320967f86b9 264 #define DAC_IEN_CH0UF_DEFAULT (_DAC_IEN_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IEN */
mbed_official 525:c320967f86b9 265 #define DAC_IEN_CH1UF (0x1UL << 5) /**< Channel 1 Conversion Data Underflow Interrupt Enable */
mbed_official 525:c320967f86b9 266 #define _DAC_IEN_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */
mbed_official 525:c320967f86b9 267 #define _DAC_IEN_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */
mbed_official 525:c320967f86b9 268 #define _DAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */
mbed_official 525:c320967f86b9 269 #define DAC_IEN_CH1UF_DEFAULT (_DAC_IEN_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IEN */
mbed_official 525:c320967f86b9 270
mbed_official 525:c320967f86b9 271 /* Bit fields for DAC IF */
mbed_official 525:c320967f86b9 272 #define _DAC_IF_RESETVALUE 0x00000000UL /**< Default value for DAC_IF */
mbed_official 525:c320967f86b9 273 #define _DAC_IF_MASK 0x00000033UL /**< Mask for DAC_IF */
mbed_official 525:c320967f86b9 274 #define DAC_IF_CH0 (0x1UL << 0) /**< Channel 0 Conversion Complete Interrupt Flag */
mbed_official 525:c320967f86b9 275 #define _DAC_IF_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */
mbed_official 525:c320967f86b9 276 #define _DAC_IF_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */
mbed_official 525:c320967f86b9 277 #define _DAC_IF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */
mbed_official 525:c320967f86b9 278 #define DAC_IF_CH0_DEFAULT (_DAC_IF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_IF */
mbed_official 525:c320967f86b9 279 #define DAC_IF_CH1 (0x1UL << 1) /**< Channel 1 Conversion Complete Interrupt Flag */
mbed_official 525:c320967f86b9 280 #define _DAC_IF_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */
mbed_official 525:c320967f86b9 281 #define _DAC_IF_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */
mbed_official 525:c320967f86b9 282 #define _DAC_IF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */
mbed_official 525:c320967f86b9 283 #define DAC_IF_CH1_DEFAULT (_DAC_IF_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_IF */
mbed_official 525:c320967f86b9 284 #define DAC_IF_CH0UF (0x1UL << 4) /**< Channel 0 Data Underflow Interrupt Flag */
mbed_official 525:c320967f86b9 285 #define _DAC_IF_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */
mbed_official 525:c320967f86b9 286 #define _DAC_IF_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */
mbed_official 525:c320967f86b9 287 #define _DAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */
mbed_official 525:c320967f86b9 288 #define DAC_IF_CH0UF_DEFAULT (_DAC_IF_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IF */
mbed_official 525:c320967f86b9 289 #define DAC_IF_CH1UF (0x1UL << 5) /**< Channel 1 Data Underflow Interrupt Flag */
mbed_official 525:c320967f86b9 290 #define _DAC_IF_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */
mbed_official 525:c320967f86b9 291 #define _DAC_IF_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */
mbed_official 525:c320967f86b9 292 #define _DAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */
mbed_official 525:c320967f86b9 293 #define DAC_IF_CH1UF_DEFAULT (_DAC_IF_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IF */
mbed_official 525:c320967f86b9 294
mbed_official 525:c320967f86b9 295 /* Bit fields for DAC IFS */
mbed_official 525:c320967f86b9 296 #define _DAC_IFS_RESETVALUE 0x00000000UL /**< Default value for DAC_IFS */
mbed_official 525:c320967f86b9 297 #define _DAC_IFS_MASK 0x00000033UL /**< Mask for DAC_IFS */
mbed_official 525:c320967f86b9 298 #define DAC_IFS_CH0 (0x1UL << 0) /**< Channel 0 Conversion Complete Interrupt Flag Set */
mbed_official 525:c320967f86b9 299 #define _DAC_IFS_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */
mbed_official 525:c320967f86b9 300 #define _DAC_IFS_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */
mbed_official 525:c320967f86b9 301 #define _DAC_IFS_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */
mbed_official 525:c320967f86b9 302 #define DAC_IFS_CH0_DEFAULT (_DAC_IFS_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_IFS */
mbed_official 525:c320967f86b9 303 #define DAC_IFS_CH1 (0x1UL << 1) /**< Channel 1 Conversion Complete Interrupt Flag Set */
mbed_official 525:c320967f86b9 304 #define _DAC_IFS_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */
mbed_official 525:c320967f86b9 305 #define _DAC_IFS_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */
mbed_official 525:c320967f86b9 306 #define _DAC_IFS_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */
mbed_official 525:c320967f86b9 307 #define DAC_IFS_CH1_DEFAULT (_DAC_IFS_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_IFS */
mbed_official 525:c320967f86b9 308 #define DAC_IFS_CH0UF (0x1UL << 4) /**< Channel 0 Data Underflow Interrupt Flag Set */
mbed_official 525:c320967f86b9 309 #define _DAC_IFS_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */
mbed_official 525:c320967f86b9 310 #define _DAC_IFS_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */
mbed_official 525:c320967f86b9 311 #define _DAC_IFS_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */
mbed_official 525:c320967f86b9 312 #define DAC_IFS_CH0UF_DEFAULT (_DAC_IFS_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IFS */
mbed_official 525:c320967f86b9 313 #define DAC_IFS_CH1UF (0x1UL << 5) /**< Channel 1 Data Underflow Interrupt Flag Set */
mbed_official 525:c320967f86b9 314 #define _DAC_IFS_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */
mbed_official 525:c320967f86b9 315 #define _DAC_IFS_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */
mbed_official 525:c320967f86b9 316 #define _DAC_IFS_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */
mbed_official 525:c320967f86b9 317 #define DAC_IFS_CH1UF_DEFAULT (_DAC_IFS_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IFS */
mbed_official 525:c320967f86b9 318
mbed_official 525:c320967f86b9 319 /* Bit fields for DAC IFC */
mbed_official 525:c320967f86b9 320 #define _DAC_IFC_RESETVALUE 0x00000000UL /**< Default value for DAC_IFC */
mbed_official 525:c320967f86b9 321 #define _DAC_IFC_MASK 0x00000033UL /**< Mask for DAC_IFC */
mbed_official 525:c320967f86b9 322 #define DAC_IFC_CH0 (0x1UL << 0) /**< Channel 0 Conversion Complete Interrupt Flag Clear */
mbed_official 525:c320967f86b9 323 #define _DAC_IFC_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */
mbed_official 525:c320967f86b9 324 #define _DAC_IFC_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */
mbed_official 525:c320967f86b9 325 #define _DAC_IFC_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */
mbed_official 525:c320967f86b9 326 #define DAC_IFC_CH0_DEFAULT (_DAC_IFC_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_IFC */
mbed_official 525:c320967f86b9 327 #define DAC_IFC_CH1 (0x1UL << 1) /**< Channel 1 Conversion Complete Interrupt Flag Clear */
mbed_official 525:c320967f86b9 328 #define _DAC_IFC_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */
mbed_official 525:c320967f86b9 329 #define _DAC_IFC_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */
mbed_official 525:c320967f86b9 330 #define _DAC_IFC_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */
mbed_official 525:c320967f86b9 331 #define DAC_IFC_CH1_DEFAULT (_DAC_IFC_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_IFC */
mbed_official 525:c320967f86b9 332 #define DAC_IFC_CH0UF (0x1UL << 4) /**< Channel 0 Data Underflow Interrupt Flag Clear */
mbed_official 525:c320967f86b9 333 #define _DAC_IFC_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */
mbed_official 525:c320967f86b9 334 #define _DAC_IFC_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */
mbed_official 525:c320967f86b9 335 #define _DAC_IFC_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */
mbed_official 525:c320967f86b9 336 #define DAC_IFC_CH0UF_DEFAULT (_DAC_IFC_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IFC */
mbed_official 525:c320967f86b9 337 #define DAC_IFC_CH1UF (0x1UL << 5) /**< Channel 1 Data Underflow Interrupt Flag Clear */
mbed_official 525:c320967f86b9 338 #define _DAC_IFC_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */
mbed_official 525:c320967f86b9 339 #define _DAC_IFC_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */
mbed_official 525:c320967f86b9 340 #define _DAC_IFC_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */
mbed_official 525:c320967f86b9 341 #define DAC_IFC_CH1UF_DEFAULT (_DAC_IFC_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IFC */
mbed_official 525:c320967f86b9 342
mbed_official 525:c320967f86b9 343 /* Bit fields for DAC CH0DATA */
mbed_official 525:c320967f86b9 344 #define _DAC_CH0DATA_RESETVALUE 0x00000000UL /**< Default value for DAC_CH0DATA */
mbed_official 525:c320967f86b9 345 #define _DAC_CH0DATA_MASK 0x00000FFFUL /**< Mask for DAC_CH0DATA */
mbed_official 525:c320967f86b9 346 #define _DAC_CH0DATA_DATA_SHIFT 0 /**< Shift value for DAC_DATA */
mbed_official 525:c320967f86b9 347 #define _DAC_CH0DATA_DATA_MASK 0xFFFUL /**< Bit mask for DAC_DATA */
mbed_official 525:c320967f86b9 348 #define _DAC_CH0DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0DATA */
mbed_official 525:c320967f86b9 349 #define DAC_CH0DATA_DATA_DEFAULT (_DAC_CH0DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CH0DATA */
mbed_official 525:c320967f86b9 350
mbed_official 525:c320967f86b9 351 /* Bit fields for DAC CH1DATA */
mbed_official 525:c320967f86b9 352 #define _DAC_CH1DATA_RESETVALUE 0x00000000UL /**< Default value for DAC_CH1DATA */
mbed_official 525:c320967f86b9 353 #define _DAC_CH1DATA_MASK 0x00000FFFUL /**< Mask for DAC_CH1DATA */
mbed_official 525:c320967f86b9 354 #define _DAC_CH1DATA_DATA_SHIFT 0 /**< Shift value for DAC_DATA */
mbed_official 525:c320967f86b9 355 #define _DAC_CH1DATA_DATA_MASK 0xFFFUL /**< Bit mask for DAC_DATA */
mbed_official 525:c320967f86b9 356 #define _DAC_CH1DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1DATA */
mbed_official 525:c320967f86b9 357 #define DAC_CH1DATA_DATA_DEFAULT (_DAC_CH1DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CH1DATA */
mbed_official 525:c320967f86b9 358
mbed_official 525:c320967f86b9 359 /* Bit fields for DAC COMBDATA */
mbed_official 525:c320967f86b9 360 #define _DAC_COMBDATA_RESETVALUE 0x00000000UL /**< Default value for DAC_COMBDATA */
mbed_official 525:c320967f86b9 361 #define _DAC_COMBDATA_MASK 0x0FFF0FFFUL /**< Mask for DAC_COMBDATA */
mbed_official 525:c320967f86b9 362 #define _DAC_COMBDATA_CH0DATA_SHIFT 0 /**< Shift value for DAC_CH0DATA */
mbed_official 525:c320967f86b9 363 #define _DAC_COMBDATA_CH0DATA_MASK 0xFFFUL /**< Bit mask for DAC_CH0DATA */
mbed_official 525:c320967f86b9 364 #define _DAC_COMBDATA_CH0DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_COMBDATA */
mbed_official 525:c320967f86b9 365 #define DAC_COMBDATA_CH0DATA_DEFAULT (_DAC_COMBDATA_CH0DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_COMBDATA */
mbed_official 525:c320967f86b9 366 #define _DAC_COMBDATA_CH1DATA_SHIFT 16 /**< Shift value for DAC_CH1DATA */
mbed_official 525:c320967f86b9 367 #define _DAC_COMBDATA_CH1DATA_MASK 0xFFF0000UL /**< Bit mask for DAC_CH1DATA */
mbed_official 525:c320967f86b9 368 #define _DAC_COMBDATA_CH1DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_COMBDATA */
mbed_official 525:c320967f86b9 369 #define DAC_COMBDATA_CH1DATA_DEFAULT (_DAC_COMBDATA_CH1DATA_DEFAULT << 16) /**< Shifted mode DEFAULT for DAC_COMBDATA */
mbed_official 525:c320967f86b9 370
mbed_official 525:c320967f86b9 371 /* Bit fields for DAC CAL */
mbed_official 525:c320967f86b9 372 #define _DAC_CAL_RESETVALUE 0x00400000UL /**< Default value for DAC_CAL */
mbed_official 525:c320967f86b9 373 #define _DAC_CAL_MASK 0x007F3F3FUL /**< Mask for DAC_CAL */
mbed_official 525:c320967f86b9 374 #define _DAC_CAL_CH0OFFSET_SHIFT 0 /**< Shift value for DAC_CH0OFFSET */
mbed_official 525:c320967f86b9 375 #define _DAC_CAL_CH0OFFSET_MASK 0x3FUL /**< Bit mask for DAC_CH0OFFSET */
mbed_official 525:c320967f86b9 376 #define _DAC_CAL_CH0OFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CAL */
mbed_official 525:c320967f86b9 377 #define DAC_CAL_CH0OFFSET_DEFAULT (_DAC_CAL_CH0OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CAL */
mbed_official 525:c320967f86b9 378 #define _DAC_CAL_CH1OFFSET_SHIFT 8 /**< Shift value for DAC_CH1OFFSET */
mbed_official 525:c320967f86b9 379 #define _DAC_CAL_CH1OFFSET_MASK 0x3F00UL /**< Bit mask for DAC_CH1OFFSET */
mbed_official 525:c320967f86b9 380 #define _DAC_CAL_CH1OFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CAL */
mbed_official 525:c320967f86b9 381 #define DAC_CAL_CH1OFFSET_DEFAULT (_DAC_CAL_CH1OFFSET_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_CAL */
mbed_official 525:c320967f86b9 382 #define _DAC_CAL_GAIN_SHIFT 16 /**< Shift value for DAC_GAIN */
mbed_official 525:c320967f86b9 383 #define _DAC_CAL_GAIN_MASK 0x7F0000UL /**< Bit mask for DAC_GAIN */
mbed_official 525:c320967f86b9 384 #define _DAC_CAL_GAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for DAC_CAL */
mbed_official 525:c320967f86b9 385 #define DAC_CAL_GAIN_DEFAULT (_DAC_CAL_GAIN_DEFAULT << 16) /**< Shifted mode DEFAULT for DAC_CAL */
mbed_official 525:c320967f86b9 386
mbed_official 525:c320967f86b9 387 /* Bit fields for DAC BIASPROG */
mbed_official 525:c320967f86b9 388 #define _DAC_BIASPROG_RESETVALUE 0x00004747UL /**< Default value for DAC_BIASPROG */
mbed_official 525:c320967f86b9 389 #define _DAC_BIASPROG_MASK 0x00004F4FUL /**< Mask for DAC_BIASPROG */
mbed_official 525:c320967f86b9 390 #define _DAC_BIASPROG_BIASPROG_SHIFT 0 /**< Shift value for DAC_BIASPROG */
mbed_official 525:c320967f86b9 391 #define _DAC_BIASPROG_BIASPROG_MASK 0xFUL /**< Bit mask for DAC_BIASPROG */
mbed_official 525:c320967f86b9 392 #define _DAC_BIASPROG_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for DAC_BIASPROG */
mbed_official 525:c320967f86b9 393 #define DAC_BIASPROG_BIASPROG_DEFAULT (_DAC_BIASPROG_BIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_BIASPROG */
mbed_official 525:c320967f86b9 394 #define DAC_BIASPROG_HALFBIAS (0x1UL << 6) /**< Half Bias Current */
mbed_official 525:c320967f86b9 395 #define _DAC_BIASPROG_HALFBIAS_SHIFT 6 /**< Shift value for DAC_HALFBIAS */
mbed_official 525:c320967f86b9 396 #define _DAC_BIASPROG_HALFBIAS_MASK 0x40UL /**< Bit mask for DAC_HALFBIAS */
mbed_official 525:c320967f86b9 397 #define _DAC_BIASPROG_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DAC_BIASPROG */
mbed_official 525:c320967f86b9 398 #define DAC_BIASPROG_HALFBIAS_DEFAULT (_DAC_BIASPROG_HALFBIAS_DEFAULT << 6) /**< Shifted mode DEFAULT for DAC_BIASPROG */
mbed_official 525:c320967f86b9 399 #define _DAC_BIASPROG_OPA2BIASPROG_SHIFT 8 /**< Shift value for DAC_OPA2BIASPROG */
mbed_official 525:c320967f86b9 400 #define _DAC_BIASPROG_OPA2BIASPROG_MASK 0xF00UL /**< Bit mask for DAC_OPA2BIASPROG */
mbed_official 525:c320967f86b9 401 #define _DAC_BIASPROG_OPA2BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for DAC_BIASPROG */
mbed_official 525:c320967f86b9 402 #define DAC_BIASPROG_OPA2BIASPROG_DEFAULT (_DAC_BIASPROG_OPA2BIASPROG_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_BIASPROG */
mbed_official 525:c320967f86b9 403 #define DAC_BIASPROG_OPA2HALFBIAS (0x1UL << 14) /**< Half Bias Current */
mbed_official 525:c320967f86b9 404 #define _DAC_BIASPROG_OPA2HALFBIAS_SHIFT 14 /**< Shift value for DAC_OPA2HALFBIAS */
mbed_official 525:c320967f86b9 405 #define _DAC_BIASPROG_OPA2HALFBIAS_MASK 0x4000UL /**< Bit mask for DAC_OPA2HALFBIAS */
mbed_official 525:c320967f86b9 406 #define _DAC_BIASPROG_OPA2HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DAC_BIASPROG */
mbed_official 525:c320967f86b9 407 #define DAC_BIASPROG_OPA2HALFBIAS_DEFAULT (_DAC_BIASPROG_OPA2HALFBIAS_DEFAULT << 14) /**< Shifted mode DEFAULT for DAC_BIASPROG */
mbed_official 525:c320967f86b9 408
mbed_official 525:c320967f86b9 409 /* Bit fields for DAC OPACTRL */
mbed_official 525:c320967f86b9 410 #define _DAC_OPACTRL_RESETVALUE 0x00000000UL /**< Default value for DAC_OPACTRL */
mbed_official 525:c320967f86b9 411 #define _DAC_OPACTRL_MASK 0x01C3F1C7UL /**< Mask for DAC_OPACTRL */
mbed_official 525:c320967f86b9 412 #define DAC_OPACTRL_OPA0EN (0x1UL << 0) /**< OPA0 Enable */
mbed_official 525:c320967f86b9 413 #define _DAC_OPACTRL_OPA0EN_SHIFT 0 /**< Shift value for DAC_OPA0EN */
mbed_official 525:c320967f86b9 414 #define _DAC_OPACTRL_OPA0EN_MASK 0x1UL /**< Bit mask for DAC_OPA0EN */
mbed_official 525:c320967f86b9 415 #define _DAC_OPACTRL_OPA0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 416 #define DAC_OPACTRL_OPA0EN_DEFAULT (_DAC_OPACTRL_OPA0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 417 #define DAC_OPACTRL_OPA1EN (0x1UL << 1) /**< OPA1 Enable */
mbed_official 525:c320967f86b9 418 #define _DAC_OPACTRL_OPA1EN_SHIFT 1 /**< Shift value for DAC_OPA1EN */
mbed_official 525:c320967f86b9 419 #define _DAC_OPACTRL_OPA1EN_MASK 0x2UL /**< Bit mask for DAC_OPA1EN */
mbed_official 525:c320967f86b9 420 #define _DAC_OPACTRL_OPA1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 421 #define DAC_OPACTRL_OPA1EN_DEFAULT (_DAC_OPACTRL_OPA1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 422 #define DAC_OPACTRL_OPA2EN (0x1UL << 2) /**< OPA2 Enable */
mbed_official 525:c320967f86b9 423 #define _DAC_OPACTRL_OPA2EN_SHIFT 2 /**< Shift value for DAC_OPA2EN */
mbed_official 525:c320967f86b9 424 #define _DAC_OPACTRL_OPA2EN_MASK 0x4UL /**< Bit mask for DAC_OPA2EN */
mbed_official 525:c320967f86b9 425 #define _DAC_OPACTRL_OPA2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 426 #define DAC_OPACTRL_OPA2EN_DEFAULT (_DAC_OPACTRL_OPA2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 427 #define DAC_OPACTRL_OPA0HCMDIS (0x1UL << 6) /**< High Common Mode Disable. */
mbed_official 525:c320967f86b9 428 #define _DAC_OPACTRL_OPA0HCMDIS_SHIFT 6 /**< Shift value for DAC_OPA0HCMDIS */
mbed_official 525:c320967f86b9 429 #define _DAC_OPACTRL_OPA0HCMDIS_MASK 0x40UL /**< Bit mask for DAC_OPA0HCMDIS */
mbed_official 525:c320967f86b9 430 #define _DAC_OPACTRL_OPA0HCMDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 431 #define DAC_OPACTRL_OPA0HCMDIS_DEFAULT (_DAC_OPACTRL_OPA0HCMDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 432 #define DAC_OPACTRL_OPA1HCMDIS (0x1UL << 7) /**< High Common Mode Disable. */
mbed_official 525:c320967f86b9 433 #define _DAC_OPACTRL_OPA1HCMDIS_SHIFT 7 /**< Shift value for DAC_OPA1HCMDIS */
mbed_official 525:c320967f86b9 434 #define _DAC_OPACTRL_OPA1HCMDIS_MASK 0x80UL /**< Bit mask for DAC_OPA1HCMDIS */
mbed_official 525:c320967f86b9 435 #define _DAC_OPACTRL_OPA1HCMDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 436 #define DAC_OPACTRL_OPA1HCMDIS_DEFAULT (_DAC_OPACTRL_OPA1HCMDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 437 #define DAC_OPACTRL_OPA2HCMDIS (0x1UL << 8) /**< High Common Mode Disable. */
mbed_official 525:c320967f86b9 438 #define _DAC_OPACTRL_OPA2HCMDIS_SHIFT 8 /**< Shift value for DAC_OPA2HCMDIS */
mbed_official 525:c320967f86b9 439 #define _DAC_OPACTRL_OPA2HCMDIS_MASK 0x100UL /**< Bit mask for DAC_OPA2HCMDIS */
mbed_official 525:c320967f86b9 440 #define _DAC_OPACTRL_OPA2HCMDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 441 #define DAC_OPACTRL_OPA2HCMDIS_DEFAULT (_DAC_OPACTRL_OPA2HCMDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 442 #define _DAC_OPACTRL_OPA0LPFDIS_SHIFT 12 /**< Shift value for DAC_OPA0LPFDIS */
mbed_official 525:c320967f86b9 443 #define _DAC_OPACTRL_OPA0LPFDIS_MASK 0x3000UL /**< Bit mask for DAC_OPA0LPFDIS */
mbed_official 525:c320967f86b9 444 #define _DAC_OPACTRL_OPA0LPFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 445 #define _DAC_OPACTRL_OPA0LPFDIS_PLPFDIS 0x00000001UL /**< Mode PLPFDIS for DAC_OPACTRL */
mbed_official 525:c320967f86b9 446 #define _DAC_OPACTRL_OPA0LPFDIS_NLPFDIS 0x00000002UL /**< Mode NLPFDIS for DAC_OPACTRL */
mbed_official 525:c320967f86b9 447 #define DAC_OPACTRL_OPA0LPFDIS_DEFAULT (_DAC_OPACTRL_OPA0LPFDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 448 #define DAC_OPACTRL_OPA0LPFDIS_PLPFDIS (_DAC_OPACTRL_OPA0LPFDIS_PLPFDIS << 12) /**< Shifted mode PLPFDIS for DAC_OPACTRL */
mbed_official 525:c320967f86b9 449 #define DAC_OPACTRL_OPA0LPFDIS_NLPFDIS (_DAC_OPACTRL_OPA0LPFDIS_NLPFDIS << 12) /**< Shifted mode NLPFDIS for DAC_OPACTRL */
mbed_official 525:c320967f86b9 450 #define _DAC_OPACTRL_OPA1LPFDIS_SHIFT 14 /**< Shift value for DAC_OPA1LPFDIS */
mbed_official 525:c320967f86b9 451 #define _DAC_OPACTRL_OPA1LPFDIS_MASK 0xC000UL /**< Bit mask for DAC_OPA1LPFDIS */
mbed_official 525:c320967f86b9 452 #define _DAC_OPACTRL_OPA1LPFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 453 #define _DAC_OPACTRL_OPA1LPFDIS_PLPFDIS 0x00000001UL /**< Mode PLPFDIS for DAC_OPACTRL */
mbed_official 525:c320967f86b9 454 #define _DAC_OPACTRL_OPA1LPFDIS_NLPFDIS 0x00000002UL /**< Mode NLPFDIS for DAC_OPACTRL */
mbed_official 525:c320967f86b9 455 #define DAC_OPACTRL_OPA1LPFDIS_DEFAULT (_DAC_OPACTRL_OPA1LPFDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 456 #define DAC_OPACTRL_OPA1LPFDIS_PLPFDIS (_DAC_OPACTRL_OPA1LPFDIS_PLPFDIS << 14) /**< Shifted mode PLPFDIS for DAC_OPACTRL */
mbed_official 525:c320967f86b9 457 #define DAC_OPACTRL_OPA1LPFDIS_NLPFDIS (_DAC_OPACTRL_OPA1LPFDIS_NLPFDIS << 14) /**< Shifted mode NLPFDIS for DAC_OPACTRL */
mbed_official 525:c320967f86b9 458 #define _DAC_OPACTRL_OPA2LPFDIS_SHIFT 16 /**< Shift value for DAC_OPA2LPFDIS */
mbed_official 525:c320967f86b9 459 #define _DAC_OPACTRL_OPA2LPFDIS_MASK 0x30000UL /**< Bit mask for DAC_OPA2LPFDIS */
mbed_official 525:c320967f86b9 460 #define _DAC_OPACTRL_OPA2LPFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 461 #define _DAC_OPACTRL_OPA2LPFDIS_PLPFDIS 0x00000001UL /**< Mode PLPFDIS for DAC_OPACTRL */
mbed_official 525:c320967f86b9 462 #define _DAC_OPACTRL_OPA2LPFDIS_NLPFDIS 0x00000002UL /**< Mode NLPFDIS for DAC_OPACTRL */
mbed_official 525:c320967f86b9 463 #define DAC_OPACTRL_OPA2LPFDIS_DEFAULT (_DAC_OPACTRL_OPA2LPFDIS_DEFAULT << 16) /**< Shifted mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 464 #define DAC_OPACTRL_OPA2LPFDIS_PLPFDIS (_DAC_OPACTRL_OPA2LPFDIS_PLPFDIS << 16) /**< Shifted mode PLPFDIS for DAC_OPACTRL */
mbed_official 525:c320967f86b9 465 #define DAC_OPACTRL_OPA2LPFDIS_NLPFDIS (_DAC_OPACTRL_OPA2LPFDIS_NLPFDIS << 16) /**< Shifted mode NLPFDIS for DAC_OPACTRL */
mbed_official 525:c320967f86b9 466 #define DAC_OPACTRL_OPA0SHORT (0x1UL << 22) /**< Short the non-inverting and inverting input. */
mbed_official 525:c320967f86b9 467 #define _DAC_OPACTRL_OPA0SHORT_SHIFT 22 /**< Shift value for DAC_OPA0SHORT */
mbed_official 525:c320967f86b9 468 #define _DAC_OPACTRL_OPA0SHORT_MASK 0x400000UL /**< Bit mask for DAC_OPA0SHORT */
mbed_official 525:c320967f86b9 469 #define _DAC_OPACTRL_OPA0SHORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 470 #define DAC_OPACTRL_OPA0SHORT_DEFAULT (_DAC_OPACTRL_OPA0SHORT_DEFAULT << 22) /**< Shifted mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 471 #define DAC_OPACTRL_OPA1SHORT (0x1UL << 23) /**< Short the non-inverting and inverting input. */
mbed_official 525:c320967f86b9 472 #define _DAC_OPACTRL_OPA1SHORT_SHIFT 23 /**< Shift value for DAC_OPA1SHORT */
mbed_official 525:c320967f86b9 473 #define _DAC_OPACTRL_OPA1SHORT_MASK 0x800000UL /**< Bit mask for DAC_OPA1SHORT */
mbed_official 525:c320967f86b9 474 #define _DAC_OPACTRL_OPA1SHORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 475 #define DAC_OPACTRL_OPA1SHORT_DEFAULT (_DAC_OPACTRL_OPA1SHORT_DEFAULT << 23) /**< Shifted mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 476 #define DAC_OPACTRL_OPA2SHORT (0x1UL << 24) /**< Short the non-inverting and inverting input. */
mbed_official 525:c320967f86b9 477 #define _DAC_OPACTRL_OPA2SHORT_SHIFT 24 /**< Shift value for DAC_OPA2SHORT */
mbed_official 525:c320967f86b9 478 #define _DAC_OPACTRL_OPA2SHORT_MASK 0x1000000UL /**< Bit mask for DAC_OPA2SHORT */
mbed_official 525:c320967f86b9 479 #define _DAC_OPACTRL_OPA2SHORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 480 #define DAC_OPACTRL_OPA2SHORT_DEFAULT (_DAC_OPACTRL_OPA2SHORT_DEFAULT << 24) /**< Shifted mode DEFAULT for DAC_OPACTRL */
mbed_official 525:c320967f86b9 481
mbed_official 525:c320967f86b9 482 /* Bit fields for DAC OPAOFFSET */
mbed_official 525:c320967f86b9 483 #define _DAC_OPAOFFSET_RESETVALUE 0x00000020UL /**< Default value for DAC_OPAOFFSET */
mbed_official 525:c320967f86b9 484 #define _DAC_OPAOFFSET_MASK 0x0000003FUL /**< Mask for DAC_OPAOFFSET */
mbed_official 525:c320967f86b9 485 #define _DAC_OPAOFFSET_OPA2OFFSET_SHIFT 0 /**< Shift value for DAC_OPA2OFFSET */
mbed_official 525:c320967f86b9 486 #define _DAC_OPAOFFSET_OPA2OFFSET_MASK 0x3FUL /**< Bit mask for DAC_OPA2OFFSET */
mbed_official 525:c320967f86b9 487 #define _DAC_OPAOFFSET_OPA2OFFSET_DEFAULT 0x00000020UL /**< Mode DEFAULT for DAC_OPAOFFSET */
mbed_official 525:c320967f86b9 488 #define DAC_OPAOFFSET_OPA2OFFSET_DEFAULT (_DAC_OPAOFFSET_OPA2OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_OPAOFFSET */
mbed_official 525:c320967f86b9 489
mbed_official 525:c320967f86b9 490 /* Bit fields for DAC OPA0MUX */
mbed_official 525:c320967f86b9 491 #define _DAC_OPA0MUX_RESETVALUE 0x00400000UL /**< Default value for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 492 #define _DAC_OPA0MUX_MASK 0x74C7F737UL /**< Mask for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 493 #define _DAC_OPA0MUX_POSSEL_SHIFT 0 /**< Shift value for DAC_POSSEL */
mbed_official 525:c320967f86b9 494 #define _DAC_OPA0MUX_POSSEL_MASK 0x7UL /**< Bit mask for DAC_POSSEL */
mbed_official 525:c320967f86b9 495 #define _DAC_OPA0MUX_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 496 #define _DAC_OPA0MUX_POSSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 497 #define _DAC_OPA0MUX_POSSEL_DAC 0x00000001UL /**< Mode DAC for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 498 #define _DAC_OPA0MUX_POSSEL_POSPAD 0x00000002UL /**< Mode POSPAD for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 499 #define _DAC_OPA0MUX_POSSEL_OPA0INP 0x00000003UL /**< Mode OPA0INP for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 500 #define _DAC_OPA0MUX_POSSEL_OPATAP 0x00000004UL /**< Mode OPATAP for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 501 #define DAC_OPA0MUX_POSSEL_DEFAULT (_DAC_OPA0MUX_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 502 #define DAC_OPA0MUX_POSSEL_DISABLE (_DAC_OPA0MUX_POSSEL_DISABLE << 0) /**< Shifted mode DISABLE for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 503 #define DAC_OPA0MUX_POSSEL_DAC (_DAC_OPA0MUX_POSSEL_DAC << 0) /**< Shifted mode DAC for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 504 #define DAC_OPA0MUX_POSSEL_POSPAD (_DAC_OPA0MUX_POSSEL_POSPAD << 0) /**< Shifted mode POSPAD for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 505 #define DAC_OPA0MUX_POSSEL_OPA0INP (_DAC_OPA0MUX_POSSEL_OPA0INP << 0) /**< Shifted mode OPA0INP for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 506 #define DAC_OPA0MUX_POSSEL_OPATAP (_DAC_OPA0MUX_POSSEL_OPATAP << 0) /**< Shifted mode OPATAP for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 507 #define _DAC_OPA0MUX_NEGSEL_SHIFT 4 /**< Shift value for DAC_NEGSEL */
mbed_official 525:c320967f86b9 508 #define _DAC_OPA0MUX_NEGSEL_MASK 0x30UL /**< Bit mask for DAC_NEGSEL */
mbed_official 525:c320967f86b9 509 #define _DAC_OPA0MUX_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 510 #define _DAC_OPA0MUX_NEGSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 511 #define _DAC_OPA0MUX_NEGSEL_UG 0x00000001UL /**< Mode UG for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 512 #define _DAC_OPA0MUX_NEGSEL_OPATAP 0x00000002UL /**< Mode OPATAP for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 513 #define _DAC_OPA0MUX_NEGSEL_NEGPAD 0x00000003UL /**< Mode NEGPAD for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 514 #define DAC_OPA0MUX_NEGSEL_DEFAULT (_DAC_OPA0MUX_NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 515 #define DAC_OPA0MUX_NEGSEL_DISABLE (_DAC_OPA0MUX_NEGSEL_DISABLE << 4) /**< Shifted mode DISABLE for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 516 #define DAC_OPA0MUX_NEGSEL_UG (_DAC_OPA0MUX_NEGSEL_UG << 4) /**< Shifted mode UG for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 517 #define DAC_OPA0MUX_NEGSEL_OPATAP (_DAC_OPA0MUX_NEGSEL_OPATAP << 4) /**< Shifted mode OPATAP for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 518 #define DAC_OPA0MUX_NEGSEL_NEGPAD (_DAC_OPA0MUX_NEGSEL_NEGPAD << 4) /**< Shifted mode NEGPAD for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 519 #define _DAC_OPA0MUX_RESINMUX_SHIFT 8 /**< Shift value for DAC_RESINMUX */
mbed_official 525:c320967f86b9 520 #define _DAC_OPA0MUX_RESINMUX_MASK 0x700UL /**< Bit mask for DAC_RESINMUX */
mbed_official 525:c320967f86b9 521 #define _DAC_OPA0MUX_RESINMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 522 #define _DAC_OPA0MUX_RESINMUX_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 523 #define _DAC_OPA0MUX_RESINMUX_OPA0INP 0x00000001UL /**< Mode OPA0INP for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 524 #define _DAC_OPA0MUX_RESINMUX_NEGPAD 0x00000002UL /**< Mode NEGPAD for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 525 #define _DAC_OPA0MUX_RESINMUX_POSPAD 0x00000003UL /**< Mode POSPAD for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 526 #define _DAC_OPA0MUX_RESINMUX_VSS 0x00000004UL /**< Mode VSS for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 527 #define DAC_OPA0MUX_RESINMUX_DEFAULT (_DAC_OPA0MUX_RESINMUX_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 528 #define DAC_OPA0MUX_RESINMUX_DISABLE (_DAC_OPA0MUX_RESINMUX_DISABLE << 8) /**< Shifted mode DISABLE for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 529 #define DAC_OPA0MUX_RESINMUX_OPA0INP (_DAC_OPA0MUX_RESINMUX_OPA0INP << 8) /**< Shifted mode OPA0INP for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 530 #define DAC_OPA0MUX_RESINMUX_NEGPAD (_DAC_OPA0MUX_RESINMUX_NEGPAD << 8) /**< Shifted mode NEGPAD for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 531 #define DAC_OPA0MUX_RESINMUX_POSPAD (_DAC_OPA0MUX_RESINMUX_POSPAD << 8) /**< Shifted mode POSPAD for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 532 #define DAC_OPA0MUX_RESINMUX_VSS (_DAC_OPA0MUX_RESINMUX_VSS << 8) /**< Shifted mode VSS for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 533 #define DAC_OPA0MUX_PPEN (0x1UL << 12) /**< OPA0 Positive Pad Input Enable */
mbed_official 525:c320967f86b9 534 #define _DAC_OPA0MUX_PPEN_SHIFT 12 /**< Shift value for DAC_PPEN */
mbed_official 525:c320967f86b9 535 #define _DAC_OPA0MUX_PPEN_MASK 0x1000UL /**< Bit mask for DAC_PPEN */
mbed_official 525:c320967f86b9 536 #define _DAC_OPA0MUX_PPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 537 #define DAC_OPA0MUX_PPEN_DEFAULT (_DAC_OPA0MUX_PPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 538 #define DAC_OPA0MUX_NPEN (0x1UL << 13) /**< OPA0 Negative Pad Input Enable */
mbed_official 525:c320967f86b9 539 #define _DAC_OPA0MUX_NPEN_SHIFT 13 /**< Shift value for DAC_NPEN */
mbed_official 525:c320967f86b9 540 #define _DAC_OPA0MUX_NPEN_MASK 0x2000UL /**< Bit mask for DAC_NPEN */
mbed_official 525:c320967f86b9 541 #define _DAC_OPA0MUX_NPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 542 #define DAC_OPA0MUX_NPEN_DEFAULT (_DAC_OPA0MUX_NPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 543 #define _DAC_OPA0MUX_OUTPEN_SHIFT 14 /**< Shift value for DAC_OUTPEN */
mbed_official 525:c320967f86b9 544 #define _DAC_OPA0MUX_OUTPEN_MASK 0x7C000UL /**< Bit mask for DAC_OUTPEN */
mbed_official 525:c320967f86b9 545 #define _DAC_OPA0MUX_OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 546 #define _DAC_OPA0MUX_OUTPEN_OUT0 0x00000001UL /**< Mode OUT0 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 547 #define _DAC_OPA0MUX_OUTPEN_OUT1 0x00000002UL /**< Mode OUT1 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 548 #define _DAC_OPA0MUX_OUTPEN_OUT2 0x00000004UL /**< Mode OUT2 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 549 #define _DAC_OPA0MUX_OUTPEN_OUT3 0x00000008UL /**< Mode OUT3 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 550 #define _DAC_OPA0MUX_OUTPEN_OUT4 0x00000010UL /**< Mode OUT4 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 551 #define DAC_OPA0MUX_OUTPEN_DEFAULT (_DAC_OPA0MUX_OUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 552 #define DAC_OPA0MUX_OUTPEN_OUT0 (_DAC_OPA0MUX_OUTPEN_OUT0 << 14) /**< Shifted mode OUT0 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 553 #define DAC_OPA0MUX_OUTPEN_OUT1 (_DAC_OPA0MUX_OUTPEN_OUT1 << 14) /**< Shifted mode OUT1 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 554 #define DAC_OPA0MUX_OUTPEN_OUT2 (_DAC_OPA0MUX_OUTPEN_OUT2 << 14) /**< Shifted mode OUT2 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 555 #define DAC_OPA0MUX_OUTPEN_OUT3 (_DAC_OPA0MUX_OUTPEN_OUT3 << 14) /**< Shifted mode OUT3 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 556 #define DAC_OPA0MUX_OUTPEN_OUT4 (_DAC_OPA0MUX_OUTPEN_OUT4 << 14) /**< Shifted mode OUT4 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 557 #define _DAC_OPA0MUX_OUTMODE_SHIFT 22 /**< Shift value for DAC_OUTMODE */
mbed_official 525:c320967f86b9 558 #define _DAC_OPA0MUX_OUTMODE_MASK 0xC00000UL /**< Bit mask for DAC_OUTMODE */
mbed_official 525:c320967f86b9 559 #define _DAC_OPA0MUX_OUTMODE_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 560 #define _DAC_OPA0MUX_OUTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 561 #define _DAC_OPA0MUX_OUTMODE_MAIN 0x00000001UL /**< Mode MAIN for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 562 #define _DAC_OPA0MUX_OUTMODE_ALT 0x00000002UL /**< Mode ALT for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 563 #define _DAC_OPA0MUX_OUTMODE_ALL 0x00000003UL /**< Mode ALL for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 564 #define DAC_OPA0MUX_OUTMODE_DISABLE (_DAC_OPA0MUX_OUTMODE_DISABLE << 22) /**< Shifted mode DISABLE for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 565 #define DAC_OPA0MUX_OUTMODE_DEFAULT (_DAC_OPA0MUX_OUTMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 566 #define DAC_OPA0MUX_OUTMODE_MAIN (_DAC_OPA0MUX_OUTMODE_MAIN << 22) /**< Shifted mode MAIN for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 567 #define DAC_OPA0MUX_OUTMODE_ALT (_DAC_OPA0MUX_OUTMODE_ALT << 22) /**< Shifted mode ALT for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 568 #define DAC_OPA0MUX_OUTMODE_ALL (_DAC_OPA0MUX_OUTMODE_ALL << 22) /**< Shifted mode ALL for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 569 #define DAC_OPA0MUX_NEXTOUT (0x1UL << 26) /**< OPA0 Next Enable */
mbed_official 525:c320967f86b9 570 #define _DAC_OPA0MUX_NEXTOUT_SHIFT 26 /**< Shift value for DAC_NEXTOUT */
mbed_official 525:c320967f86b9 571 #define _DAC_OPA0MUX_NEXTOUT_MASK 0x4000000UL /**< Bit mask for DAC_NEXTOUT */
mbed_official 525:c320967f86b9 572 #define _DAC_OPA0MUX_NEXTOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 573 #define DAC_OPA0MUX_NEXTOUT_DEFAULT (_DAC_OPA0MUX_NEXTOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 574 #define _DAC_OPA0MUX_RESSEL_SHIFT 28 /**< Shift value for DAC_RESSEL */
mbed_official 525:c320967f86b9 575 #define _DAC_OPA0MUX_RESSEL_MASK 0x70000000UL /**< Bit mask for DAC_RESSEL */
mbed_official 525:c320967f86b9 576 #define _DAC_OPA0MUX_RESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 577 #define _DAC_OPA0MUX_RESSEL_RES0 0x00000000UL /**< Mode RES0 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 578 #define _DAC_OPA0MUX_RESSEL_RES1 0x00000001UL /**< Mode RES1 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 579 #define _DAC_OPA0MUX_RESSEL_RES2 0x00000002UL /**< Mode RES2 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 580 #define _DAC_OPA0MUX_RESSEL_RES3 0x00000003UL /**< Mode RES3 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 581 #define _DAC_OPA0MUX_RESSEL_RES4 0x00000004UL /**< Mode RES4 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 582 #define _DAC_OPA0MUX_RESSEL_RES5 0x00000005UL /**< Mode RES5 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 583 #define _DAC_OPA0MUX_RESSEL_RES6 0x00000006UL /**< Mode RES6 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 584 #define _DAC_OPA0MUX_RESSEL_RES7 0x00000007UL /**< Mode RES7 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 585 #define DAC_OPA0MUX_RESSEL_DEFAULT (_DAC_OPA0MUX_RESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 586 #define DAC_OPA0MUX_RESSEL_RES0 (_DAC_OPA0MUX_RESSEL_RES0 << 28) /**< Shifted mode RES0 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 587 #define DAC_OPA0MUX_RESSEL_RES1 (_DAC_OPA0MUX_RESSEL_RES1 << 28) /**< Shifted mode RES1 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 588 #define DAC_OPA0MUX_RESSEL_RES2 (_DAC_OPA0MUX_RESSEL_RES2 << 28) /**< Shifted mode RES2 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 589 #define DAC_OPA0MUX_RESSEL_RES3 (_DAC_OPA0MUX_RESSEL_RES3 << 28) /**< Shifted mode RES3 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 590 #define DAC_OPA0MUX_RESSEL_RES4 (_DAC_OPA0MUX_RESSEL_RES4 << 28) /**< Shifted mode RES4 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 591 #define DAC_OPA0MUX_RESSEL_RES5 (_DAC_OPA0MUX_RESSEL_RES5 << 28) /**< Shifted mode RES5 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 592 #define DAC_OPA0MUX_RESSEL_RES6 (_DAC_OPA0MUX_RESSEL_RES6 << 28) /**< Shifted mode RES6 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 593 #define DAC_OPA0MUX_RESSEL_RES7 (_DAC_OPA0MUX_RESSEL_RES7 << 28) /**< Shifted mode RES7 for DAC_OPA0MUX */
mbed_official 525:c320967f86b9 594
mbed_official 525:c320967f86b9 595 /* Bit fields for DAC OPA1MUX */
mbed_official 525:c320967f86b9 596 #define _DAC_OPA1MUX_RESETVALUE 0x00000000UL /**< Default value for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 597 #define _DAC_OPA1MUX_MASK 0x74C7F737UL /**< Mask for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 598 #define _DAC_OPA1MUX_POSSEL_SHIFT 0 /**< Shift value for DAC_POSSEL */
mbed_official 525:c320967f86b9 599 #define _DAC_OPA1MUX_POSSEL_MASK 0x7UL /**< Bit mask for DAC_POSSEL */
mbed_official 525:c320967f86b9 600 #define _DAC_OPA1MUX_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 601 #define _DAC_OPA1MUX_POSSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 602 #define _DAC_OPA1MUX_POSSEL_DAC 0x00000001UL /**< Mode DAC for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 603 #define _DAC_OPA1MUX_POSSEL_POSPAD 0x00000002UL /**< Mode POSPAD for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 604 #define _DAC_OPA1MUX_POSSEL_OPA0INP 0x00000003UL /**< Mode OPA0INP for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 605 #define _DAC_OPA1MUX_POSSEL_OPATAP 0x00000004UL /**< Mode OPATAP for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 606 #define DAC_OPA1MUX_POSSEL_DEFAULT (_DAC_OPA1MUX_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 607 #define DAC_OPA1MUX_POSSEL_DISABLE (_DAC_OPA1MUX_POSSEL_DISABLE << 0) /**< Shifted mode DISABLE for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 608 #define DAC_OPA1MUX_POSSEL_DAC (_DAC_OPA1MUX_POSSEL_DAC << 0) /**< Shifted mode DAC for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 609 #define DAC_OPA1MUX_POSSEL_POSPAD (_DAC_OPA1MUX_POSSEL_POSPAD << 0) /**< Shifted mode POSPAD for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 610 #define DAC_OPA1MUX_POSSEL_OPA0INP (_DAC_OPA1MUX_POSSEL_OPA0INP << 0) /**< Shifted mode OPA0INP for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 611 #define DAC_OPA1MUX_POSSEL_OPATAP (_DAC_OPA1MUX_POSSEL_OPATAP << 0) /**< Shifted mode OPATAP for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 612 #define _DAC_OPA1MUX_NEGSEL_SHIFT 4 /**< Shift value for DAC_NEGSEL */
mbed_official 525:c320967f86b9 613 #define _DAC_OPA1MUX_NEGSEL_MASK 0x30UL /**< Bit mask for DAC_NEGSEL */
mbed_official 525:c320967f86b9 614 #define _DAC_OPA1MUX_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 615 #define _DAC_OPA1MUX_NEGSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 616 #define _DAC_OPA1MUX_NEGSEL_UG 0x00000001UL /**< Mode UG for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 617 #define _DAC_OPA1MUX_NEGSEL_OPATAP 0x00000002UL /**< Mode OPATAP for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 618 #define _DAC_OPA1MUX_NEGSEL_NEGPAD 0x00000003UL /**< Mode NEGPAD for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 619 #define DAC_OPA1MUX_NEGSEL_DEFAULT (_DAC_OPA1MUX_NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 620 #define DAC_OPA1MUX_NEGSEL_DISABLE (_DAC_OPA1MUX_NEGSEL_DISABLE << 4) /**< Shifted mode DISABLE for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 621 #define DAC_OPA1MUX_NEGSEL_UG (_DAC_OPA1MUX_NEGSEL_UG << 4) /**< Shifted mode UG for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 622 #define DAC_OPA1MUX_NEGSEL_OPATAP (_DAC_OPA1MUX_NEGSEL_OPATAP << 4) /**< Shifted mode OPATAP for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 623 #define DAC_OPA1MUX_NEGSEL_NEGPAD (_DAC_OPA1MUX_NEGSEL_NEGPAD << 4) /**< Shifted mode NEGPAD for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 624 #define _DAC_OPA1MUX_RESINMUX_SHIFT 8 /**< Shift value for DAC_RESINMUX */
mbed_official 525:c320967f86b9 625 #define _DAC_OPA1MUX_RESINMUX_MASK 0x700UL /**< Bit mask for DAC_RESINMUX */
mbed_official 525:c320967f86b9 626 #define _DAC_OPA1MUX_RESINMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 627 #define _DAC_OPA1MUX_RESINMUX_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 628 #define _DAC_OPA1MUX_RESINMUX_OPA0INP 0x00000001UL /**< Mode OPA0INP for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 629 #define _DAC_OPA1MUX_RESINMUX_NEGPAD 0x00000002UL /**< Mode NEGPAD for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 630 #define _DAC_OPA1MUX_RESINMUX_POSPAD 0x00000003UL /**< Mode POSPAD for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 631 #define _DAC_OPA1MUX_RESINMUX_VSS 0x00000004UL /**< Mode VSS for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 632 #define DAC_OPA1MUX_RESINMUX_DEFAULT (_DAC_OPA1MUX_RESINMUX_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 633 #define DAC_OPA1MUX_RESINMUX_DISABLE (_DAC_OPA1MUX_RESINMUX_DISABLE << 8) /**< Shifted mode DISABLE for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 634 #define DAC_OPA1MUX_RESINMUX_OPA0INP (_DAC_OPA1MUX_RESINMUX_OPA0INP << 8) /**< Shifted mode OPA0INP for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 635 #define DAC_OPA1MUX_RESINMUX_NEGPAD (_DAC_OPA1MUX_RESINMUX_NEGPAD << 8) /**< Shifted mode NEGPAD for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 636 #define DAC_OPA1MUX_RESINMUX_POSPAD (_DAC_OPA1MUX_RESINMUX_POSPAD << 8) /**< Shifted mode POSPAD for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 637 #define DAC_OPA1MUX_RESINMUX_VSS (_DAC_OPA1MUX_RESINMUX_VSS << 8) /**< Shifted mode VSS for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 638 #define DAC_OPA1MUX_PPEN (0x1UL << 12) /**< OPA1 Positive Pad Input Enable */
mbed_official 525:c320967f86b9 639 #define _DAC_OPA1MUX_PPEN_SHIFT 12 /**< Shift value for DAC_PPEN */
mbed_official 525:c320967f86b9 640 #define _DAC_OPA1MUX_PPEN_MASK 0x1000UL /**< Bit mask for DAC_PPEN */
mbed_official 525:c320967f86b9 641 #define _DAC_OPA1MUX_PPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 642 #define DAC_OPA1MUX_PPEN_DEFAULT (_DAC_OPA1MUX_PPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 643 #define DAC_OPA1MUX_NPEN (0x1UL << 13) /**< OPA1 Negative Pad Input Enable */
mbed_official 525:c320967f86b9 644 #define _DAC_OPA1MUX_NPEN_SHIFT 13 /**< Shift value for DAC_NPEN */
mbed_official 525:c320967f86b9 645 #define _DAC_OPA1MUX_NPEN_MASK 0x2000UL /**< Bit mask for DAC_NPEN */
mbed_official 525:c320967f86b9 646 #define _DAC_OPA1MUX_NPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 647 #define DAC_OPA1MUX_NPEN_DEFAULT (_DAC_OPA1MUX_NPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 648 #define _DAC_OPA1MUX_OUTPEN_SHIFT 14 /**< Shift value for DAC_OUTPEN */
mbed_official 525:c320967f86b9 649 #define _DAC_OPA1MUX_OUTPEN_MASK 0x7C000UL /**< Bit mask for DAC_OUTPEN */
mbed_official 525:c320967f86b9 650 #define _DAC_OPA1MUX_OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 651 #define _DAC_OPA1MUX_OUTPEN_OUT0 0x00000001UL /**< Mode OUT0 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 652 #define _DAC_OPA1MUX_OUTPEN_OUT1 0x00000002UL /**< Mode OUT1 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 653 #define _DAC_OPA1MUX_OUTPEN_OUT2 0x00000004UL /**< Mode OUT2 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 654 #define _DAC_OPA1MUX_OUTPEN_OUT3 0x00000008UL /**< Mode OUT3 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 655 #define _DAC_OPA1MUX_OUTPEN_OUT4 0x00000010UL /**< Mode OUT4 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 656 #define DAC_OPA1MUX_OUTPEN_DEFAULT (_DAC_OPA1MUX_OUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 657 #define DAC_OPA1MUX_OUTPEN_OUT0 (_DAC_OPA1MUX_OUTPEN_OUT0 << 14) /**< Shifted mode OUT0 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 658 #define DAC_OPA1MUX_OUTPEN_OUT1 (_DAC_OPA1MUX_OUTPEN_OUT1 << 14) /**< Shifted mode OUT1 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 659 #define DAC_OPA1MUX_OUTPEN_OUT2 (_DAC_OPA1MUX_OUTPEN_OUT2 << 14) /**< Shifted mode OUT2 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 660 #define DAC_OPA1MUX_OUTPEN_OUT3 (_DAC_OPA1MUX_OUTPEN_OUT3 << 14) /**< Shifted mode OUT3 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 661 #define DAC_OPA1MUX_OUTPEN_OUT4 (_DAC_OPA1MUX_OUTPEN_OUT4 << 14) /**< Shifted mode OUT4 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 662 #define _DAC_OPA1MUX_OUTMODE_SHIFT 22 /**< Shift value for DAC_OUTMODE */
mbed_official 525:c320967f86b9 663 #define _DAC_OPA1MUX_OUTMODE_MASK 0xC00000UL /**< Bit mask for DAC_OUTMODE */
mbed_official 525:c320967f86b9 664 #define _DAC_OPA1MUX_OUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 665 #define _DAC_OPA1MUX_OUTMODE_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 666 #define _DAC_OPA1MUX_OUTMODE_MAIN 0x00000001UL /**< Mode MAIN for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 667 #define _DAC_OPA1MUX_OUTMODE_ALT 0x00000002UL /**< Mode ALT for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 668 #define _DAC_OPA1MUX_OUTMODE_ALL 0x00000003UL /**< Mode ALL for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 669 #define DAC_OPA1MUX_OUTMODE_DEFAULT (_DAC_OPA1MUX_OUTMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 670 #define DAC_OPA1MUX_OUTMODE_DISABLE (_DAC_OPA1MUX_OUTMODE_DISABLE << 22) /**< Shifted mode DISABLE for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 671 #define DAC_OPA1MUX_OUTMODE_MAIN (_DAC_OPA1MUX_OUTMODE_MAIN << 22) /**< Shifted mode MAIN for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 672 #define DAC_OPA1MUX_OUTMODE_ALT (_DAC_OPA1MUX_OUTMODE_ALT << 22) /**< Shifted mode ALT for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 673 #define DAC_OPA1MUX_OUTMODE_ALL (_DAC_OPA1MUX_OUTMODE_ALL << 22) /**< Shifted mode ALL for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 674 #define DAC_OPA1MUX_NEXTOUT (0x1UL << 26) /**< OPA1 Next Enable */
mbed_official 525:c320967f86b9 675 #define _DAC_OPA1MUX_NEXTOUT_SHIFT 26 /**< Shift value for DAC_NEXTOUT */
mbed_official 525:c320967f86b9 676 #define _DAC_OPA1MUX_NEXTOUT_MASK 0x4000000UL /**< Bit mask for DAC_NEXTOUT */
mbed_official 525:c320967f86b9 677 #define _DAC_OPA1MUX_NEXTOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 678 #define DAC_OPA1MUX_NEXTOUT_DEFAULT (_DAC_OPA1MUX_NEXTOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 679 #define _DAC_OPA1MUX_RESSEL_SHIFT 28 /**< Shift value for DAC_RESSEL */
mbed_official 525:c320967f86b9 680 #define _DAC_OPA1MUX_RESSEL_MASK 0x70000000UL /**< Bit mask for DAC_RESSEL */
mbed_official 525:c320967f86b9 681 #define _DAC_OPA1MUX_RESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 682 #define _DAC_OPA1MUX_RESSEL_RES0 0x00000000UL /**< Mode RES0 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 683 #define _DAC_OPA1MUX_RESSEL_RES1 0x00000001UL /**< Mode RES1 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 684 #define _DAC_OPA1MUX_RESSEL_RES2 0x00000002UL /**< Mode RES2 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 685 #define _DAC_OPA1MUX_RESSEL_RES3 0x00000003UL /**< Mode RES3 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 686 #define _DAC_OPA1MUX_RESSEL_RES4 0x00000004UL /**< Mode RES4 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 687 #define _DAC_OPA1MUX_RESSEL_RES5 0x00000005UL /**< Mode RES5 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 688 #define _DAC_OPA1MUX_RESSEL_RES6 0x00000006UL /**< Mode RES6 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 689 #define _DAC_OPA1MUX_RESSEL_RES7 0x00000007UL /**< Mode RES7 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 690 #define DAC_OPA1MUX_RESSEL_DEFAULT (_DAC_OPA1MUX_RESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 691 #define DAC_OPA1MUX_RESSEL_RES0 (_DAC_OPA1MUX_RESSEL_RES0 << 28) /**< Shifted mode RES0 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 692 #define DAC_OPA1MUX_RESSEL_RES1 (_DAC_OPA1MUX_RESSEL_RES1 << 28) /**< Shifted mode RES1 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 693 #define DAC_OPA1MUX_RESSEL_RES2 (_DAC_OPA1MUX_RESSEL_RES2 << 28) /**< Shifted mode RES2 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 694 #define DAC_OPA1MUX_RESSEL_RES3 (_DAC_OPA1MUX_RESSEL_RES3 << 28) /**< Shifted mode RES3 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 695 #define DAC_OPA1MUX_RESSEL_RES4 (_DAC_OPA1MUX_RESSEL_RES4 << 28) /**< Shifted mode RES4 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 696 #define DAC_OPA1MUX_RESSEL_RES5 (_DAC_OPA1MUX_RESSEL_RES5 << 28) /**< Shifted mode RES5 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 697 #define DAC_OPA1MUX_RESSEL_RES6 (_DAC_OPA1MUX_RESSEL_RES6 << 28) /**< Shifted mode RES6 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 698 #define DAC_OPA1MUX_RESSEL_RES7 (_DAC_OPA1MUX_RESSEL_RES7 << 28) /**< Shifted mode RES7 for DAC_OPA1MUX */
mbed_official 525:c320967f86b9 699
mbed_official 525:c320967f86b9 700 /* Bit fields for DAC OPA2MUX */
mbed_official 525:c320967f86b9 701 #define _DAC_OPA2MUX_RESETVALUE 0x00000000UL /**< Default value for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 702 #define _DAC_OPA2MUX_MASK 0x7440F737UL /**< Mask for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 703 #define _DAC_OPA2MUX_POSSEL_SHIFT 0 /**< Shift value for DAC_POSSEL */
mbed_official 525:c320967f86b9 704 #define _DAC_OPA2MUX_POSSEL_MASK 0x7UL /**< Bit mask for DAC_POSSEL */
mbed_official 525:c320967f86b9 705 #define _DAC_OPA2MUX_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 706 #define _DAC_OPA2MUX_POSSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 707 #define _DAC_OPA2MUX_POSSEL_POSPAD 0x00000002UL /**< Mode POSPAD for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 708 #define _DAC_OPA2MUX_POSSEL_OPA1INP 0x00000003UL /**< Mode OPA1INP for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 709 #define _DAC_OPA2MUX_POSSEL_OPATAP 0x00000004UL /**< Mode OPATAP for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 710 #define DAC_OPA2MUX_POSSEL_DEFAULT (_DAC_OPA2MUX_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 711 #define DAC_OPA2MUX_POSSEL_DISABLE (_DAC_OPA2MUX_POSSEL_DISABLE << 0) /**< Shifted mode DISABLE for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 712 #define DAC_OPA2MUX_POSSEL_POSPAD (_DAC_OPA2MUX_POSSEL_POSPAD << 0) /**< Shifted mode POSPAD for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 713 #define DAC_OPA2MUX_POSSEL_OPA1INP (_DAC_OPA2MUX_POSSEL_OPA1INP << 0) /**< Shifted mode OPA1INP for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 714 #define DAC_OPA2MUX_POSSEL_OPATAP (_DAC_OPA2MUX_POSSEL_OPATAP << 0) /**< Shifted mode OPATAP for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 715 #define _DAC_OPA2MUX_NEGSEL_SHIFT 4 /**< Shift value for DAC_NEGSEL */
mbed_official 525:c320967f86b9 716 #define _DAC_OPA2MUX_NEGSEL_MASK 0x30UL /**< Bit mask for DAC_NEGSEL */
mbed_official 525:c320967f86b9 717 #define _DAC_OPA2MUX_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 718 #define _DAC_OPA2MUX_NEGSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 719 #define _DAC_OPA2MUX_NEGSEL_UG 0x00000001UL /**< Mode UG for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 720 #define _DAC_OPA2MUX_NEGSEL_OPATAP 0x00000002UL /**< Mode OPATAP for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 721 #define _DAC_OPA2MUX_NEGSEL_NEGPAD 0x00000003UL /**< Mode NEGPAD for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 722 #define DAC_OPA2MUX_NEGSEL_DEFAULT (_DAC_OPA2MUX_NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 723 #define DAC_OPA2MUX_NEGSEL_DISABLE (_DAC_OPA2MUX_NEGSEL_DISABLE << 4) /**< Shifted mode DISABLE for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 724 #define DAC_OPA2MUX_NEGSEL_UG (_DAC_OPA2MUX_NEGSEL_UG << 4) /**< Shifted mode UG for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 725 #define DAC_OPA2MUX_NEGSEL_OPATAP (_DAC_OPA2MUX_NEGSEL_OPATAP << 4) /**< Shifted mode OPATAP for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 726 #define DAC_OPA2MUX_NEGSEL_NEGPAD (_DAC_OPA2MUX_NEGSEL_NEGPAD << 4) /**< Shifted mode NEGPAD for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 727 #define _DAC_OPA2MUX_RESINMUX_SHIFT 8 /**< Shift value for DAC_RESINMUX */
mbed_official 525:c320967f86b9 728 #define _DAC_OPA2MUX_RESINMUX_MASK 0x700UL /**< Bit mask for DAC_RESINMUX */
mbed_official 525:c320967f86b9 729 #define _DAC_OPA2MUX_RESINMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 730 #define _DAC_OPA2MUX_RESINMUX_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 731 #define _DAC_OPA2MUX_RESINMUX_OPA1INP 0x00000001UL /**< Mode OPA1INP for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 732 #define _DAC_OPA2MUX_RESINMUX_NEGPAD 0x00000002UL /**< Mode NEGPAD for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 733 #define _DAC_OPA2MUX_RESINMUX_POSPAD 0x00000003UL /**< Mode POSPAD for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 734 #define _DAC_OPA2MUX_RESINMUX_VSS 0x00000004UL /**< Mode VSS for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 735 #define DAC_OPA2MUX_RESINMUX_DEFAULT (_DAC_OPA2MUX_RESINMUX_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 736 #define DAC_OPA2MUX_RESINMUX_DISABLE (_DAC_OPA2MUX_RESINMUX_DISABLE << 8) /**< Shifted mode DISABLE for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 737 #define DAC_OPA2MUX_RESINMUX_OPA1INP (_DAC_OPA2MUX_RESINMUX_OPA1INP << 8) /**< Shifted mode OPA1INP for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 738 #define DAC_OPA2MUX_RESINMUX_NEGPAD (_DAC_OPA2MUX_RESINMUX_NEGPAD << 8) /**< Shifted mode NEGPAD for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 739 #define DAC_OPA2MUX_RESINMUX_POSPAD (_DAC_OPA2MUX_RESINMUX_POSPAD << 8) /**< Shifted mode POSPAD for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 740 #define DAC_OPA2MUX_RESINMUX_VSS (_DAC_OPA2MUX_RESINMUX_VSS << 8) /**< Shifted mode VSS for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 741 #define DAC_OPA2MUX_PPEN (0x1UL << 12) /**< OPA2 Positive Pad Input Enable */
mbed_official 525:c320967f86b9 742 #define _DAC_OPA2MUX_PPEN_SHIFT 12 /**< Shift value for DAC_PPEN */
mbed_official 525:c320967f86b9 743 #define _DAC_OPA2MUX_PPEN_MASK 0x1000UL /**< Bit mask for DAC_PPEN */
mbed_official 525:c320967f86b9 744 #define _DAC_OPA2MUX_PPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 745 #define DAC_OPA2MUX_PPEN_DEFAULT (_DAC_OPA2MUX_PPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 746 #define DAC_OPA2MUX_NPEN (0x1UL << 13) /**< OPA2 Negative Pad Input Enable */
mbed_official 525:c320967f86b9 747 #define _DAC_OPA2MUX_NPEN_SHIFT 13 /**< Shift value for DAC_NPEN */
mbed_official 525:c320967f86b9 748 #define _DAC_OPA2MUX_NPEN_MASK 0x2000UL /**< Bit mask for DAC_NPEN */
mbed_official 525:c320967f86b9 749 #define _DAC_OPA2MUX_NPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 750 #define DAC_OPA2MUX_NPEN_DEFAULT (_DAC_OPA2MUX_NPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 751 #define _DAC_OPA2MUX_OUTPEN_SHIFT 14 /**< Shift value for DAC_OUTPEN */
mbed_official 525:c320967f86b9 752 #define _DAC_OPA2MUX_OUTPEN_MASK 0xC000UL /**< Bit mask for DAC_OUTPEN */
mbed_official 525:c320967f86b9 753 #define _DAC_OPA2MUX_OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 754 #define _DAC_OPA2MUX_OUTPEN_OUT0 0x00000001UL /**< Mode OUT0 for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 755 #define _DAC_OPA2MUX_OUTPEN_OUT1 0x00000002UL /**< Mode OUT1 for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 756 #define DAC_OPA2MUX_OUTPEN_DEFAULT (_DAC_OPA2MUX_OUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 757 #define DAC_OPA2MUX_OUTPEN_OUT0 (_DAC_OPA2MUX_OUTPEN_OUT0 << 14) /**< Shifted mode OUT0 for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 758 #define DAC_OPA2MUX_OUTPEN_OUT1 (_DAC_OPA2MUX_OUTPEN_OUT1 << 14) /**< Shifted mode OUT1 for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 759 #define DAC_OPA2MUX_OUTMODE (0x1UL << 22) /**< Output Select */
mbed_official 525:c320967f86b9 760 #define _DAC_OPA2MUX_OUTMODE_SHIFT 22 /**< Shift value for DAC_OUTMODE */
mbed_official 525:c320967f86b9 761 #define _DAC_OPA2MUX_OUTMODE_MASK 0x400000UL /**< Bit mask for DAC_OUTMODE */
mbed_official 525:c320967f86b9 762 #define _DAC_OPA2MUX_OUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 763 #define DAC_OPA2MUX_OUTMODE_DEFAULT (_DAC_OPA2MUX_OUTMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 764 #define DAC_OPA2MUX_NEXTOUT (0x1UL << 26) /**< OPA2 Next Enable */
mbed_official 525:c320967f86b9 765 #define _DAC_OPA2MUX_NEXTOUT_SHIFT 26 /**< Shift value for DAC_NEXTOUT */
mbed_official 525:c320967f86b9 766 #define _DAC_OPA2MUX_NEXTOUT_MASK 0x4000000UL /**< Bit mask for DAC_NEXTOUT */
mbed_official 525:c320967f86b9 767 #define _DAC_OPA2MUX_NEXTOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 768 #define DAC_OPA2MUX_NEXTOUT_DEFAULT (_DAC_OPA2MUX_NEXTOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 769 #define _DAC_OPA2MUX_RESSEL_SHIFT 28 /**< Shift value for DAC_RESSEL */
mbed_official 525:c320967f86b9 770 #define _DAC_OPA2MUX_RESSEL_MASK 0x70000000UL /**< Bit mask for DAC_RESSEL */
mbed_official 525:c320967f86b9 771 #define _DAC_OPA2MUX_RESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 772 #define _DAC_OPA2MUX_RESSEL_RES0 0x00000000UL /**< Mode RES0 for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 773 #define _DAC_OPA2MUX_RESSEL_RES1 0x00000001UL /**< Mode RES1 for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 774 #define _DAC_OPA2MUX_RESSEL_RES2 0x00000002UL /**< Mode RES2 for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 775 #define _DAC_OPA2MUX_RESSEL_RES3 0x00000003UL /**< Mode RES3 for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 776 #define _DAC_OPA2MUX_RESSEL_RES4 0x00000004UL /**< Mode RES4 for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 777 #define _DAC_OPA2MUX_RESSEL_RES5 0x00000005UL /**< Mode RES5 for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 778 #define _DAC_OPA2MUX_RESSEL_RES6 0x00000006UL /**< Mode RES6 for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 779 #define _DAC_OPA2MUX_RESSEL_RES7 0x00000007UL /**< Mode RES7 for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 780 #define DAC_OPA2MUX_RESSEL_DEFAULT (_DAC_OPA2MUX_RESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 781 #define DAC_OPA2MUX_RESSEL_RES0 (_DAC_OPA2MUX_RESSEL_RES0 << 28) /**< Shifted mode RES0 for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 782 #define DAC_OPA2MUX_RESSEL_RES1 (_DAC_OPA2MUX_RESSEL_RES1 << 28) /**< Shifted mode RES1 for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 783 #define DAC_OPA2MUX_RESSEL_RES2 (_DAC_OPA2MUX_RESSEL_RES2 << 28) /**< Shifted mode RES2 for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 784 #define DAC_OPA2MUX_RESSEL_RES3 (_DAC_OPA2MUX_RESSEL_RES3 << 28) /**< Shifted mode RES3 for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 785 #define DAC_OPA2MUX_RESSEL_RES4 (_DAC_OPA2MUX_RESSEL_RES4 << 28) /**< Shifted mode RES4 for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 786 #define DAC_OPA2MUX_RESSEL_RES5 (_DAC_OPA2MUX_RESSEL_RES5 << 28) /**< Shifted mode RES5 for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 787 #define DAC_OPA2MUX_RESSEL_RES6 (_DAC_OPA2MUX_RESSEL_RES6 << 28) /**< Shifted mode RES6 for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 788 #define DAC_OPA2MUX_RESSEL_RES7 (_DAC_OPA2MUX_RESSEL_RES7 << 28) /**< Shifted mode RES7 for DAC_OPA2MUX */
mbed_official 525:c320967f86b9 789
mbed_official 525:c320967f86b9 790 /** @} End of group EFM32LG_DAC */
mbed_official 525:c320967f86b9 791
mbed_official 525:c320967f86b9 792