rf24_config.h

00001 /* Memory Map */
00002 #define CONFIG      0x00
00003 #define EN_AA       0x01
00004 #define EN_RXADDR   0x02
00005 #define SETUP_AW    0x03
00006 #define SETUP_RETR  0x04
00007 #define RF_CH       0x05
00008 #define RF_SETUP    0x06
00009 #define STATUS      0x07
00010 #define OBSERVE_TX  0x08
00011 #define CD          0x09
00012 #define RX_ADDR_P0  0x0A
00013 #define RX_ADDR_P1  0x0B
00014 #define RX_ADDR_P2  0x0C
00015 #define RX_ADDR_P3  0x0D
00016 #define RX_ADDR_P4  0x0E
00017 #define RX_ADDR_P5  0x0F
00018 #define TX_ADDR     0x10
00019 #define RX_PW_P0    0x11
00020 #define RX_PW_P1    0x12
00021 #define RX_PW_P2    0x13
00022 #define RX_PW_P3    0x14
00023 #define RX_PW_P4    0x15
00024 #define RX_PW_P5    0x16
00025 #define FIFO_STATUS 0x17
00026 #define DYNPD       0x1C
00027 #define FEATURE     0x1D
00028 
00029 /* Bit Mnemonics */
00030 #define MASK_RX_DR  6
00031 #define MASK_TX_DS  5
00032 #define MASK_MAX_RT 4
00033 #define EN_CRC      3
00034 #define CRCO        2
00035 #define PWR_UP      1
00036 #define PRIM_RX     0
00037 #define ENAA_P5     5
00038 #define ENAA_P4     4
00039 #define ENAA_P3     3
00040 #define ENAA_P2     2
00041 #define ENAA_P1     1
00042 #define ENAA_P0     0
00043 #define ERX_P5      5
00044 #define ERX_P4      4
00045 #define ERX_P3      3
00046 #define ERX_P2      2
00047 #define ERX_P1      1
00048 #define ERX_P0      0
00049 #define AW          0
00050 #define ARD         4
00051 #define ARC         0
00052 #define PLL_LOCK    4
00053 #define RF_DR       3
00054 #define RF_PWR      6
00055 #define RX_DR       6
00056 #define TX_DS       5
00057 #define MAX_RT      4
00058 #define RX_P_NO     1
00059 #define TX_FULL     0
00060 #define PLOS_CNT    4
00061 #define ARC_CNT     0
00062 #define TX_REUSE    6
00063 #define FIFO_FULL   5
00064 #define TX_EMPTY    4
00065 #define RX_FULL     1
00066 #define RX_EMPTY    0
00067 #define DPL_P5      5
00068 #define DPL_P4      4
00069 #define DPL_P3      3
00070 #define DPL_P2      2
00071 #define DPL_P1      1
00072 #define DPL_P0      0
00073 #define EN_DPL      2
00074 #define EN_ACK_PAY  1
00075 #define EN_DYN_ACK  0
00076 
00077 /* Instruction Mnemonics */
00078 #define R_REGISTER    0x00
00079 #define W_REGISTER    0x20
00080 #define REGISTER_MASK 0x1F
00081 #define ACTIVATE      0x50
00082 #define R_RX_PL_WID   0x60
00083 #define R_RX_PAYLOAD  0x61
00084 #define W_TX_PAYLOAD  0xA0
00085 #define W_ACK_PAYLOAD 0xA8
00086 #define FLUSH_TX      0xE1
00087 #define FLUSH_RX      0xE2
00088 #define REUSE_TX_PL   0xE3
00089 #define NOP           0xFF
00090 
00091 /* Non-P omissions */
00092 #define LNA_HCURR   0
00093 
00094 /* P model memory Map */
00095 #define RPD         0x09
00096 
00097 /* P model bit Mnemonics */
00098 #define RF_DR_LOW   5
00099 #define RF_DR_HIGH  3
00100 #define RF_PWR_LOW  1
00101 #define RF_PWR_HIGH 2
00102 
00103 #define HIGH        1
00104 #define LOW         0
00105 #define _BV(n) (1 << n)