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mbed-dev
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mbed official
targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_etm.h@50:a417edff4437, 2016-01-15 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Jan 15 07:45:16 2016 +0000
- Revision:
- 50:a417edff4437
- Parent:
- 0:9b334a45a8ff
- Child:
- 144:ef7eb2e8f9f7
Synchronized with git revision 6010f32619bfcbb01cc73747d4ff9040863482d9
Full URL: https://github.com/mbedmicro/mbed/commit/6010f32619bfcbb01cc73747d4ff9040863482d9/
Remove doubling of buffer size in realiseEndpoint()
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /**************************************************************************//** |
| bogdanm | 0:9b334a45a8ff | 2 | * @file efm32lg_etm.h |
| bogdanm | 0:9b334a45a8ff | 3 | * @brief EFM32LG_ETM register and bit field definitions |
| mbed_official | 50:a417edff4437 | 4 | * @version 4.2.0 |
| bogdanm | 0:9b334a45a8ff | 5 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 6 | * @section License |
| mbed_official | 50:a417edff4437 | 7 | * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| bogdanm | 0:9b334a45a8ff | 8 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 9 | * |
| bogdanm | 0:9b334a45a8ff | 10 | * Permission is granted to anyone to use this software for any purpose, |
| bogdanm | 0:9b334a45a8ff | 11 | * including commercial applications, and to alter it and redistribute it |
| bogdanm | 0:9b334a45a8ff | 12 | * freely, subject to the following restrictions: |
| bogdanm | 0:9b334a45a8ff | 13 | * |
| bogdanm | 0:9b334a45a8ff | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| bogdanm | 0:9b334a45a8ff | 15 | * claim that you wrote the original software.@n |
| bogdanm | 0:9b334a45a8ff | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| bogdanm | 0:9b334a45a8ff | 17 | * misrepresented as being the original software.@n |
| bogdanm | 0:9b334a45a8ff | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| bogdanm | 0:9b334a45a8ff | 19 | * |
| bogdanm | 0:9b334a45a8ff | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| bogdanm | 0:9b334a45a8ff | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| bogdanm | 0:9b334a45a8ff | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| bogdanm | 0:9b334a45a8ff | 23 | * kind, including, but not limited to, any implied warranties of |
| bogdanm | 0:9b334a45a8ff | 24 | * merchantability or fitness for any particular purpose or warranties against |
| bogdanm | 0:9b334a45a8ff | 25 | * infringement of any proprietary rights of a third party. |
| bogdanm | 0:9b334a45a8ff | 26 | * |
| bogdanm | 0:9b334a45a8ff | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| bogdanm | 0:9b334a45a8ff | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| bogdanm | 0:9b334a45a8ff | 29 | * any third party, arising from your use of this Software. |
| bogdanm | 0:9b334a45a8ff | 30 | * |
| bogdanm | 0:9b334a45a8ff | 31 | *****************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 32 | /**************************************************************************//** |
| mbed_official | 50:a417edff4437 | 33 | * @addtogroup Parts |
| mbed_official | 50:a417edff4437 | 34 | * @{ |
| mbed_official | 50:a417edff4437 | 35 | ******************************************************************************/ |
| mbed_official | 50:a417edff4437 | 36 | /**************************************************************************//** |
| bogdanm | 0:9b334a45a8ff | 37 | * @defgroup EFM32LG_ETM |
| bogdanm | 0:9b334a45a8ff | 38 | * @{ |
| bogdanm | 0:9b334a45a8ff | 39 | * @brief EFM32LG_ETM Register Declaration |
| bogdanm | 0:9b334a45a8ff | 40 | *****************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 41 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 42 | { |
| bogdanm | 0:9b334a45a8ff | 43 | __IO uint32_t ETMCR; /**< Main Control Register */ |
| bogdanm | 0:9b334a45a8ff | 44 | __I uint32_t ETMCCR; /**< Configuration Code Register */ |
| bogdanm | 0:9b334a45a8ff | 45 | __IO uint32_t ETMTRIGGER; /**< ETM Trigger Event Register */ |
| bogdanm | 0:9b334a45a8ff | 46 | uint32_t RESERVED0[1]; /**< Reserved for future use **/ |
| bogdanm | 0:9b334a45a8ff | 47 | __IO uint32_t ETMSR; /**< ETM Status Register */ |
| bogdanm | 0:9b334a45a8ff | 48 | __I uint32_t ETMSCR; /**< ETM System Configuration Register */ |
| bogdanm | 0:9b334a45a8ff | 49 | uint32_t RESERVED1[2]; /**< Reserved for future use **/ |
| bogdanm | 0:9b334a45a8ff | 50 | __IO uint32_t ETMTEEVR; /**< ETM TraceEnable Event Register */ |
| bogdanm | 0:9b334a45a8ff | 51 | __IO uint32_t ETMTECR1; /**< ETM Trace control Register */ |
| bogdanm | 0:9b334a45a8ff | 52 | uint32_t RESERVED2[1]; /**< Reserved for future use **/ |
| bogdanm | 0:9b334a45a8ff | 53 | __IO uint32_t ETMFFLR; /**< ETM Fifo Full Level Register */ |
| bogdanm | 0:9b334a45a8ff | 54 | uint32_t RESERVED3[68]; /**< Reserved for future use **/ |
| bogdanm | 0:9b334a45a8ff | 55 | __IO uint32_t ETMCNTRLDVR1; /**< Counter Reload Value */ |
| bogdanm | 0:9b334a45a8ff | 56 | uint32_t RESERVED4[39]; /**< Reserved for future use **/ |
| bogdanm | 0:9b334a45a8ff | 57 | __IO uint32_t ETMSYNCFR; /**< Synchronisation Frequency Register */ |
| bogdanm | 0:9b334a45a8ff | 58 | __I uint32_t ETMIDR; /**< ID Register */ |
| bogdanm | 0:9b334a45a8ff | 59 | __I uint32_t ETMCCER; /**< Configuration Code Extension Register */ |
| bogdanm | 0:9b334a45a8ff | 60 | uint32_t RESERVED5[1]; /**< Reserved for future use **/ |
| bogdanm | 0:9b334a45a8ff | 61 | __IO uint32_t ETMTESSEICR; /**< TraceEnable Start/Stop EmbeddedICE Control Register */ |
| bogdanm | 0:9b334a45a8ff | 62 | uint32_t RESERVED6[1]; /**< Reserved for future use **/ |
| bogdanm | 0:9b334a45a8ff | 63 | __IO uint32_t ETMTSEVR; /**< Timestamp Event Register */ |
| bogdanm | 0:9b334a45a8ff | 64 | uint32_t RESERVED7[1]; /**< Reserved for future use **/ |
| bogdanm | 0:9b334a45a8ff | 65 | __IO uint32_t ETMTRACEIDR; /**< CoreSight Trace ID Register */ |
| bogdanm | 0:9b334a45a8ff | 66 | uint32_t RESERVED8[1]; /**< Reserved for future use **/ |
| bogdanm | 0:9b334a45a8ff | 67 | __I uint32_t ETMIDR2; /**< ETM ID Register 2 */ |
| bogdanm | 0:9b334a45a8ff | 68 | uint32_t RESERVED9[66]; /**< Reserved for future use **/ |
| bogdanm | 0:9b334a45a8ff | 69 | __I uint32_t ETMPDSR; /**< Device Power-down Status Register */ |
| bogdanm | 0:9b334a45a8ff | 70 | uint32_t RESERVED10[754]; /**< Reserved for future use **/ |
| bogdanm | 0:9b334a45a8ff | 71 | __IO uint32_t ETMISCIN; /**< Integration Test Miscellaneous Inputs Register */ |
| bogdanm | 0:9b334a45a8ff | 72 | uint32_t RESERVED11[1]; /**< Reserved for future use **/ |
| bogdanm | 0:9b334a45a8ff | 73 | __O uint32_t ITTRIGOUT; /**< Integration Test Trigger Out Register */ |
| bogdanm | 0:9b334a45a8ff | 74 | uint32_t RESERVED12[1]; /**< Reserved for future use **/ |
| bogdanm | 0:9b334a45a8ff | 75 | __I uint32_t ETMITATBCTR2; /**< ETM Integration Test ATB Control 2 Register */ |
| bogdanm | 0:9b334a45a8ff | 76 | uint32_t RESERVED13[1]; /**< Reserved for future use **/ |
| bogdanm | 0:9b334a45a8ff | 77 | __O uint32_t ETMITATBCTR0; /**< ETM Integration Test ATB Control 0 Register */ |
| bogdanm | 0:9b334a45a8ff | 78 | uint32_t RESERVED14[1]; /**< Reserved for future use **/ |
| bogdanm | 0:9b334a45a8ff | 79 | __IO uint32_t ETMITCTRL; /**< ETM Integration Control Register */ |
| bogdanm | 0:9b334a45a8ff | 80 | uint32_t RESERVED15[39]; /**< Reserved for future use **/ |
| bogdanm | 0:9b334a45a8ff | 81 | __IO uint32_t ETMCLAIMSET; /**< ETM Claim Tag Set Register */ |
| bogdanm | 0:9b334a45a8ff | 82 | __IO uint32_t ETMCLAIMCLR; /**< ETM Claim Tag Clear Register */ |
| bogdanm | 0:9b334a45a8ff | 83 | uint32_t RESERVED16[2]; /**< Reserved for future use **/ |
| bogdanm | 0:9b334a45a8ff | 84 | __IO uint32_t ETMLAR; /**< ETM Lock Access Register */ |
| bogdanm | 0:9b334a45a8ff | 85 | __I uint32_t ETMLSR; /**< Lock Status Register */ |
| bogdanm | 0:9b334a45a8ff | 86 | __I uint32_t ETMAUTHSTATUS; /**< ETM Authentication Status Register */ |
| bogdanm | 0:9b334a45a8ff | 87 | uint32_t RESERVED17[4]; /**< Reserved for future use **/ |
| bogdanm | 0:9b334a45a8ff | 88 | __I uint32_t ETMDEVTYPE; /**< CoreSight Device Type Register */ |
| bogdanm | 0:9b334a45a8ff | 89 | __I uint32_t ETMPIDR4; /**< Peripheral ID4 Register */ |
| bogdanm | 0:9b334a45a8ff | 90 | __O uint32_t ETMPIDR5; /**< Peripheral ID5 Register */ |
| bogdanm | 0:9b334a45a8ff | 91 | __O uint32_t ETMPIDR6; /**< Peripheral ID6 Register */ |
| bogdanm | 0:9b334a45a8ff | 92 | __O uint32_t ETMPIDR7; /**< Peripheral ID7 Register */ |
| bogdanm | 0:9b334a45a8ff | 93 | __I uint32_t ETMPIDR0; /**< Peripheral ID0 Register */ |
| bogdanm | 0:9b334a45a8ff | 94 | __I uint32_t ETMPIDR1; /**< Peripheral ID1 Register */ |
| bogdanm | 0:9b334a45a8ff | 95 | __I uint32_t ETMPIDR2; /**< Peripheral ID2 Register */ |
| bogdanm | 0:9b334a45a8ff | 96 | __I uint32_t ETMPIDR3; /**< Peripheral ID3 Register */ |
| bogdanm | 0:9b334a45a8ff | 97 | __I uint32_t ETMCIDR0; /**< Component ID0 Register */ |
| bogdanm | 0:9b334a45a8ff | 98 | __I uint32_t ETMCIDR1; /**< Component ID1 Register */ |
| bogdanm | 0:9b334a45a8ff | 99 | __I uint32_t ETMCIDR2; /**< Component ID2 Register */ |
| bogdanm | 0:9b334a45a8ff | 100 | __I uint32_t ETMCIDR3; /**< Component ID3 Register */ |
| bogdanm | 0:9b334a45a8ff | 101 | } ETM_TypeDef; /** @} */ |
| bogdanm | 0:9b334a45a8ff | 102 | |
| bogdanm | 0:9b334a45a8ff | 103 | /**************************************************************************//** |
| bogdanm | 0:9b334a45a8ff | 104 | * @defgroup EFM32LG_ETM_BitFields |
| bogdanm | 0:9b334a45a8ff | 105 | * @{ |
| bogdanm | 0:9b334a45a8ff | 106 | *****************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 107 | |
| bogdanm | 0:9b334a45a8ff | 108 | /* Bit fields for ETM ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 109 | #define _ETM_ETMCR_RESETVALUE 0x00000411UL /**< Default value for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 110 | #define _ETM_ETMCR_MASK 0x10632FF1UL /**< Mask for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 111 | #define ETM_ETMCR_POWERDWN (0x1UL << 0) /**< ETM Control in low power mode */ |
| bogdanm | 0:9b334a45a8ff | 112 | #define _ETM_ETMCR_POWERDWN_SHIFT 0 /**< Shift value for ETM_POWERDWN */ |
| bogdanm | 0:9b334a45a8ff | 113 | #define _ETM_ETMCR_POWERDWN_MASK 0x1UL /**< Bit mask for ETM_POWERDWN */ |
| bogdanm | 0:9b334a45a8ff | 114 | #define _ETM_ETMCR_POWERDWN_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 115 | #define ETM_ETMCR_POWERDWN_DEFAULT (_ETM_ETMCR_POWERDWN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 116 | #define _ETM_ETMCR_PORTSIZE_SHIFT 4 /**< Shift value for ETM_PORTSIZE */ |
| bogdanm | 0:9b334a45a8ff | 117 | #define _ETM_ETMCR_PORTSIZE_MASK 0x70UL /**< Bit mask for ETM_PORTSIZE */ |
| bogdanm | 0:9b334a45a8ff | 118 | #define _ETM_ETMCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 119 | #define ETM_ETMCR_PORTSIZE_DEFAULT (_ETM_ETMCR_PORTSIZE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 120 | #define ETM_ETMCR_STALL (0x1UL << 7) /**< Stall Processor */ |
| bogdanm | 0:9b334a45a8ff | 121 | #define _ETM_ETMCR_STALL_SHIFT 7 /**< Shift value for ETM_STALL */ |
| bogdanm | 0:9b334a45a8ff | 122 | #define _ETM_ETMCR_STALL_MASK 0x80UL /**< Bit mask for ETM_STALL */ |
| bogdanm | 0:9b334a45a8ff | 123 | #define _ETM_ETMCR_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 124 | #define ETM_ETMCR_STALL_DEFAULT (_ETM_ETMCR_STALL_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 125 | #define ETM_ETMCR_BRANCHOUTPUT (0x1UL << 8) /**< Branch Output */ |
| bogdanm | 0:9b334a45a8ff | 126 | #define _ETM_ETMCR_BRANCHOUTPUT_SHIFT 8 /**< Shift value for ETM_BRANCHOUTPUT */ |
| bogdanm | 0:9b334a45a8ff | 127 | #define _ETM_ETMCR_BRANCHOUTPUT_MASK 0x100UL /**< Bit mask for ETM_BRANCHOUTPUT */ |
| bogdanm | 0:9b334a45a8ff | 128 | #define _ETM_ETMCR_BRANCHOUTPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 129 | #define ETM_ETMCR_BRANCHOUTPUT_DEFAULT (_ETM_ETMCR_BRANCHOUTPUT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 130 | #define ETM_ETMCR_DBGREQCTRL (0x1UL << 9) /**< Debug Request Control */ |
| bogdanm | 0:9b334a45a8ff | 131 | #define _ETM_ETMCR_DBGREQCTRL_SHIFT 9 /**< Shift value for ETM_DBGREQCTRL */ |
| bogdanm | 0:9b334a45a8ff | 132 | #define _ETM_ETMCR_DBGREQCTRL_MASK 0x200UL /**< Bit mask for ETM_DBGREQCTRL */ |
| bogdanm | 0:9b334a45a8ff | 133 | #define _ETM_ETMCR_DBGREQCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 134 | #define ETM_ETMCR_DBGREQCTRL_DEFAULT (_ETM_ETMCR_DBGREQCTRL_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 135 | #define ETM_ETMCR_ETMPROG (0x1UL << 10) /**< ETM Programming */ |
| bogdanm | 0:9b334a45a8ff | 136 | #define _ETM_ETMCR_ETMPROG_SHIFT 10 /**< Shift value for ETM_ETMPROG */ |
| bogdanm | 0:9b334a45a8ff | 137 | #define _ETM_ETMCR_ETMPROG_MASK 0x400UL /**< Bit mask for ETM_ETMPROG */ |
| bogdanm | 0:9b334a45a8ff | 138 | #define _ETM_ETMCR_ETMPROG_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 139 | #define ETM_ETMCR_ETMPROG_DEFAULT (_ETM_ETMCR_ETMPROG_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 140 | #define ETM_ETMCR_ETMPORTSEL (0x1UL << 11) /**< ETM Port Selection */ |
| bogdanm | 0:9b334a45a8ff | 141 | #define _ETM_ETMCR_ETMPORTSEL_SHIFT 11 /**< Shift value for ETM_ETMPORTSEL */ |
| bogdanm | 0:9b334a45a8ff | 142 | #define _ETM_ETMCR_ETMPORTSEL_MASK 0x800UL /**< Bit mask for ETM_ETMPORTSEL */ |
| bogdanm | 0:9b334a45a8ff | 143 | #define _ETM_ETMCR_ETMPORTSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 144 | #define _ETM_ETMCR_ETMPORTSEL_ETMLOW 0x00000000UL /**< Mode ETMLOW for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 145 | #define _ETM_ETMCR_ETMPORTSEL_ETMHIGH 0x00000001UL /**< Mode ETMHIGH for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 146 | #define ETM_ETMCR_ETMPORTSEL_DEFAULT (_ETM_ETMCR_ETMPORTSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 147 | #define ETM_ETMCR_ETMPORTSEL_ETMLOW (_ETM_ETMCR_ETMPORTSEL_ETMLOW << 11) /**< Shifted mode ETMLOW for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 148 | #define ETM_ETMCR_ETMPORTSEL_ETMHIGH (_ETM_ETMCR_ETMPORTSEL_ETMHIGH << 11) /**< Shifted mode ETMHIGH for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 149 | #define ETM_ETMCR_PORTMODE2 (0x1UL << 13) /**< Port Mode[2] */ |
| bogdanm | 0:9b334a45a8ff | 150 | #define _ETM_ETMCR_PORTMODE2_SHIFT 13 /**< Shift value for ETM_PORTMODE2 */ |
| bogdanm | 0:9b334a45a8ff | 151 | #define _ETM_ETMCR_PORTMODE2_MASK 0x2000UL /**< Bit mask for ETM_PORTMODE2 */ |
| bogdanm | 0:9b334a45a8ff | 152 | #define _ETM_ETMCR_PORTMODE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 153 | #define ETM_ETMCR_PORTMODE2_DEFAULT (_ETM_ETMCR_PORTMODE2_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 154 | #define _ETM_ETMCR_PORTMODE_SHIFT 16 /**< Shift value for ETM_PORTMODE */ |
| bogdanm | 0:9b334a45a8ff | 155 | #define _ETM_ETMCR_PORTMODE_MASK 0x30000UL /**< Bit mask for ETM_PORTMODE */ |
| bogdanm | 0:9b334a45a8ff | 156 | #define _ETM_ETMCR_PORTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 157 | #define ETM_ETMCR_PORTMODE_DEFAULT (_ETM_ETMCR_PORTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 158 | #define _ETM_ETMCR_EPORTSIZE_SHIFT 21 /**< Shift value for ETM_EPORTSIZE */ |
| bogdanm | 0:9b334a45a8ff | 159 | #define _ETM_ETMCR_EPORTSIZE_MASK 0x600000UL /**< Bit mask for ETM_EPORTSIZE */ |
| bogdanm | 0:9b334a45a8ff | 160 | #define _ETM_ETMCR_EPORTSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 161 | #define ETM_ETMCR_EPORTSIZE_DEFAULT (_ETM_ETMCR_EPORTSIZE_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 162 | #define ETM_ETMCR_TSTAMPEN (0x1UL << 28) /**< Time Stamp Enable */ |
| bogdanm | 0:9b334a45a8ff | 163 | #define _ETM_ETMCR_TSTAMPEN_SHIFT 28 /**< Shift value for ETM_TSTAMPEN */ |
| bogdanm | 0:9b334a45a8ff | 164 | #define _ETM_ETMCR_TSTAMPEN_MASK 0x10000000UL /**< Bit mask for ETM_TSTAMPEN */ |
| bogdanm | 0:9b334a45a8ff | 165 | #define _ETM_ETMCR_TSTAMPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 166 | #define ETM_ETMCR_TSTAMPEN_DEFAULT (_ETM_ETMCR_TSTAMPEN_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCR */ |
| bogdanm | 0:9b334a45a8ff | 167 | |
| bogdanm | 0:9b334a45a8ff | 168 | /* Bit fields for ETM ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 169 | #define _ETM_ETMCCR_RESETVALUE 0x8C802000UL /**< Default value for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 170 | #define _ETM_ETMCCR_MASK 0x8FFFFFFFUL /**< Mask for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 171 | #define _ETM_ETMCCR_ADRCMPPAIR_SHIFT 0 /**< Shift value for ETM_ADRCMPPAIR */ |
| bogdanm | 0:9b334a45a8ff | 172 | #define _ETM_ETMCCR_ADRCMPPAIR_MASK 0xFUL /**< Bit mask for ETM_ADRCMPPAIR */ |
| bogdanm | 0:9b334a45a8ff | 173 | #define _ETM_ETMCCR_ADRCMPPAIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 174 | #define ETM_ETMCCR_ADRCMPPAIR_DEFAULT (_ETM_ETMCCR_ADRCMPPAIR_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 175 | #define _ETM_ETMCCR_DATACMPNUM_SHIFT 4 /**< Shift value for ETM_DATACMPNUM */ |
| bogdanm | 0:9b334a45a8ff | 176 | #define _ETM_ETMCCR_DATACMPNUM_MASK 0xF0UL /**< Bit mask for ETM_DATACMPNUM */ |
| bogdanm | 0:9b334a45a8ff | 177 | #define _ETM_ETMCCR_DATACMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 178 | #define ETM_ETMCCR_DATACMPNUM_DEFAULT (_ETM_ETMCCR_DATACMPNUM_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 179 | #define _ETM_ETMCCR_MMDECCNT_SHIFT 8 /**< Shift value for ETM_MMDECCNT */ |
| bogdanm | 0:9b334a45a8ff | 180 | #define _ETM_ETMCCR_MMDECCNT_MASK 0x1F00UL /**< Bit mask for ETM_MMDECCNT */ |
| bogdanm | 0:9b334a45a8ff | 181 | #define _ETM_ETMCCR_MMDECCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 182 | #define ETM_ETMCCR_MMDECCNT_DEFAULT (_ETM_ETMCCR_MMDECCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 183 | #define _ETM_ETMCCR_COUNTNUM_SHIFT 13 /**< Shift value for ETM_COUNTNUM */ |
| bogdanm | 0:9b334a45a8ff | 184 | #define _ETM_ETMCCR_COUNTNUM_MASK 0xE000UL /**< Bit mask for ETM_COUNTNUM */ |
| bogdanm | 0:9b334a45a8ff | 185 | #define _ETM_ETMCCR_COUNTNUM_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 186 | #define ETM_ETMCCR_COUNTNUM_DEFAULT (_ETM_ETMCCR_COUNTNUM_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 187 | #define ETM_ETMCCR_SEQPRES (0x1UL << 16) /**< Sequencer Present */ |
| bogdanm | 0:9b334a45a8ff | 188 | #define _ETM_ETMCCR_SEQPRES_SHIFT 16 /**< Shift value for ETM_SEQPRES */ |
| bogdanm | 0:9b334a45a8ff | 189 | #define _ETM_ETMCCR_SEQPRES_MASK 0x10000UL /**< Bit mask for ETM_SEQPRES */ |
| bogdanm | 0:9b334a45a8ff | 190 | #define _ETM_ETMCCR_SEQPRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 191 | #define ETM_ETMCCR_SEQPRES_DEFAULT (_ETM_ETMCCR_SEQPRES_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 192 | #define _ETM_ETMCCR_EXTINPNUM_SHIFT 17 /**< Shift value for ETM_EXTINPNUM */ |
| bogdanm | 0:9b334a45a8ff | 193 | #define _ETM_ETMCCR_EXTINPNUM_MASK 0xE0000UL /**< Bit mask for ETM_EXTINPNUM */ |
| bogdanm | 0:9b334a45a8ff | 194 | #define _ETM_ETMCCR_EXTINPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 195 | #define _ETM_ETMCCR_EXTINPNUM_ZERO 0x00000000UL /**< Mode ZERO for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 196 | #define _ETM_ETMCCR_EXTINPNUM_ONE 0x00000001UL /**< Mode ONE for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 197 | #define _ETM_ETMCCR_EXTINPNUM_TWO 0x00000002UL /**< Mode TWO for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 198 | #define ETM_ETMCCR_EXTINPNUM_DEFAULT (_ETM_ETMCCR_EXTINPNUM_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 199 | #define ETM_ETMCCR_EXTINPNUM_ZERO (_ETM_ETMCCR_EXTINPNUM_ZERO << 17) /**< Shifted mode ZERO for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 200 | #define ETM_ETMCCR_EXTINPNUM_ONE (_ETM_ETMCCR_EXTINPNUM_ONE << 17) /**< Shifted mode ONE for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 201 | #define ETM_ETMCCR_EXTINPNUM_TWO (_ETM_ETMCCR_EXTINPNUM_TWO << 17) /**< Shifted mode TWO for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 202 | #define _ETM_ETMCCR_EXTOUTNUM_SHIFT 20 /**< Shift value for ETM_EXTOUTNUM */ |
| bogdanm | 0:9b334a45a8ff | 203 | #define _ETM_ETMCCR_EXTOUTNUM_MASK 0x700000UL /**< Bit mask for ETM_EXTOUTNUM */ |
| bogdanm | 0:9b334a45a8ff | 204 | #define _ETM_ETMCCR_EXTOUTNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 205 | #define ETM_ETMCCR_EXTOUTNUM_DEFAULT (_ETM_ETMCCR_EXTOUTNUM_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 206 | #define ETM_ETMCCR_FIFOFULLPRES (0x1UL << 23) /**< FIFIO FULL present */ |
| bogdanm | 0:9b334a45a8ff | 207 | #define _ETM_ETMCCR_FIFOFULLPRES_SHIFT 23 /**< Shift value for ETM_FIFOFULLPRES */ |
| bogdanm | 0:9b334a45a8ff | 208 | #define _ETM_ETMCCR_FIFOFULLPRES_MASK 0x800000UL /**< Bit mask for ETM_FIFOFULLPRES */ |
| bogdanm | 0:9b334a45a8ff | 209 | #define _ETM_ETMCCR_FIFOFULLPRES_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 210 | #define ETM_ETMCCR_FIFOFULLPRES_DEFAULT (_ETM_ETMCCR_FIFOFULLPRES_DEFAULT << 23) /**< Shifted mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 211 | #define _ETM_ETMCCR_IDCOMPNUM_SHIFT 24 /**< Shift value for ETM_IDCOMPNUM */ |
| bogdanm | 0:9b334a45a8ff | 212 | #define _ETM_ETMCCR_IDCOMPNUM_MASK 0x3000000UL /**< Bit mask for ETM_IDCOMPNUM */ |
| bogdanm | 0:9b334a45a8ff | 213 | #define _ETM_ETMCCR_IDCOMPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 214 | #define ETM_ETMCCR_IDCOMPNUM_DEFAULT (_ETM_ETMCCR_IDCOMPNUM_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 215 | #define ETM_ETMCCR_TRACESS (0x1UL << 26) /**< Trace Start/Stop Block Present */ |
| bogdanm | 0:9b334a45a8ff | 216 | #define _ETM_ETMCCR_TRACESS_SHIFT 26 /**< Shift value for ETM_TRACESS */ |
| bogdanm | 0:9b334a45a8ff | 217 | #define _ETM_ETMCCR_TRACESS_MASK 0x4000000UL /**< Bit mask for ETM_TRACESS */ |
| bogdanm | 0:9b334a45a8ff | 218 | #define _ETM_ETMCCR_TRACESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 219 | #define ETM_ETMCCR_TRACESS_DEFAULT (_ETM_ETMCCR_TRACESS_DEFAULT << 26) /**< Shifted mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 220 | #define ETM_ETMCCR_MMACCESS (0x1UL << 27) /**< Coprocessor and Memeory Access */ |
| bogdanm | 0:9b334a45a8ff | 221 | #define _ETM_ETMCCR_MMACCESS_SHIFT 27 /**< Shift value for ETM_MMACCESS */ |
| bogdanm | 0:9b334a45a8ff | 222 | #define _ETM_ETMCCR_MMACCESS_MASK 0x8000000UL /**< Bit mask for ETM_MMACCESS */ |
| bogdanm | 0:9b334a45a8ff | 223 | #define _ETM_ETMCCR_MMACCESS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 224 | #define ETM_ETMCCR_MMACCESS_DEFAULT (_ETM_ETMCCR_MMACCESS_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 225 | #define ETM_ETMCCR_ETMID (0x1UL << 31) /**< ETM ID Register Present */ |
| bogdanm | 0:9b334a45a8ff | 226 | #define _ETM_ETMCCR_ETMID_SHIFT 31 /**< Shift value for ETM_ETMID */ |
| bogdanm | 0:9b334a45a8ff | 227 | #define _ETM_ETMCCR_ETMID_MASK 0x80000000UL /**< Bit mask for ETM_ETMID */ |
| bogdanm | 0:9b334a45a8ff | 228 | #define _ETM_ETMCCR_ETMID_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 229 | #define ETM_ETMCCR_ETMID_DEFAULT (_ETM_ETMCCR_ETMID_DEFAULT << 31) /**< Shifted mode DEFAULT for ETM_ETMCCR */ |
| bogdanm | 0:9b334a45a8ff | 230 | |
| bogdanm | 0:9b334a45a8ff | 231 | /* Bit fields for ETM ETMTRIGGER */ |
| bogdanm | 0:9b334a45a8ff | 232 | #define _ETM_ETMTRIGGER_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRIGGER */ |
| bogdanm | 0:9b334a45a8ff | 233 | #define _ETM_ETMTRIGGER_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTRIGGER */ |
| bogdanm | 0:9b334a45a8ff | 234 | #define _ETM_ETMTRIGGER_RESA_SHIFT 0 /**< Shift value for ETM_RESA */ |
| bogdanm | 0:9b334a45a8ff | 235 | #define _ETM_ETMTRIGGER_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */ |
| bogdanm | 0:9b334a45a8ff | 236 | #define _ETM_ETMTRIGGER_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */ |
| bogdanm | 0:9b334a45a8ff | 237 | #define ETM_ETMTRIGGER_RESA_DEFAULT (_ETM_ETMTRIGGER_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */ |
| bogdanm | 0:9b334a45a8ff | 238 | #define _ETM_ETMTRIGGER_RESB_SHIFT 7 /**< Shift value for ETM_RESB */ |
| bogdanm | 0:9b334a45a8ff | 239 | #define _ETM_ETMTRIGGER_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */ |
| bogdanm | 0:9b334a45a8ff | 240 | #define _ETM_ETMTRIGGER_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */ |
| bogdanm | 0:9b334a45a8ff | 241 | #define ETM_ETMTRIGGER_RESB_DEFAULT (_ETM_ETMTRIGGER_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */ |
| bogdanm | 0:9b334a45a8ff | 242 | #define _ETM_ETMTRIGGER_ETMFCN_SHIFT 14 /**< Shift value for ETM_ETMFCN */ |
| bogdanm | 0:9b334a45a8ff | 243 | #define _ETM_ETMTRIGGER_ETMFCN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCN */ |
| bogdanm | 0:9b334a45a8ff | 244 | #define _ETM_ETMTRIGGER_ETMFCN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRIGGER */ |
| bogdanm | 0:9b334a45a8ff | 245 | #define ETM_ETMTRIGGER_ETMFCN_DEFAULT (_ETM_ETMTRIGGER_ETMFCN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTRIGGER */ |
| bogdanm | 0:9b334a45a8ff | 246 | |
| bogdanm | 0:9b334a45a8ff | 247 | /* Bit fields for ETM ETMSR */ |
| bogdanm | 0:9b334a45a8ff | 248 | #define _ETM_ETMSR_RESETVALUE 0x00000002UL /**< Default value for ETM_ETMSR */ |
| bogdanm | 0:9b334a45a8ff | 249 | #define _ETM_ETMSR_MASK 0x0000000FUL /**< Mask for ETM_ETMSR */ |
| bogdanm | 0:9b334a45a8ff | 250 | #define ETM_ETMSR_ETHOF (0x1UL << 0) /**< ETM Overflow */ |
| bogdanm | 0:9b334a45a8ff | 251 | #define _ETM_ETMSR_ETHOF_SHIFT 0 /**< Shift value for ETM_ETHOF */ |
| bogdanm | 0:9b334a45a8ff | 252 | #define _ETM_ETMSR_ETHOF_MASK 0x1UL /**< Bit mask for ETM_ETHOF */ |
| bogdanm | 0:9b334a45a8ff | 253 | #define _ETM_ETMSR_ETHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */ |
| bogdanm | 0:9b334a45a8ff | 254 | #define ETM_ETMSR_ETHOF_DEFAULT (_ETM_ETMSR_ETHOF_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSR */ |
| bogdanm | 0:9b334a45a8ff | 255 | #define ETM_ETMSR_ETMPROGBIT (0x1UL << 1) /**< ETM Programming Bit Status */ |
| bogdanm | 0:9b334a45a8ff | 256 | #define _ETM_ETMSR_ETMPROGBIT_SHIFT 1 /**< Shift value for ETM_ETMPROGBIT */ |
| bogdanm | 0:9b334a45a8ff | 257 | #define _ETM_ETMSR_ETMPROGBIT_MASK 0x2UL /**< Bit mask for ETM_ETMPROGBIT */ |
| bogdanm | 0:9b334a45a8ff | 258 | #define _ETM_ETMSR_ETMPROGBIT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSR */ |
| bogdanm | 0:9b334a45a8ff | 259 | #define ETM_ETMSR_ETMPROGBIT_DEFAULT (_ETM_ETMSR_ETMPROGBIT_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMSR */ |
| bogdanm | 0:9b334a45a8ff | 260 | #define ETM_ETMSR_TRACESTAT (0x1UL << 2) /**< Trace Start/Stop Status */ |
| bogdanm | 0:9b334a45a8ff | 261 | #define _ETM_ETMSR_TRACESTAT_SHIFT 2 /**< Shift value for ETM_TRACESTAT */ |
| bogdanm | 0:9b334a45a8ff | 262 | #define _ETM_ETMSR_TRACESTAT_MASK 0x4UL /**< Bit mask for ETM_TRACESTAT */ |
| bogdanm | 0:9b334a45a8ff | 263 | #define _ETM_ETMSR_TRACESTAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */ |
| bogdanm | 0:9b334a45a8ff | 264 | #define ETM_ETMSR_TRACESTAT_DEFAULT (_ETM_ETMSR_TRACESTAT_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMSR */ |
| bogdanm | 0:9b334a45a8ff | 265 | #define ETM_ETMSR_TRIGBIT (0x1UL << 3) /**< Trigger Bit */ |
| bogdanm | 0:9b334a45a8ff | 266 | #define _ETM_ETMSR_TRIGBIT_SHIFT 3 /**< Shift value for ETM_TRIGBIT */ |
| bogdanm | 0:9b334a45a8ff | 267 | #define _ETM_ETMSR_TRIGBIT_MASK 0x8UL /**< Bit mask for ETM_TRIGBIT */ |
| bogdanm | 0:9b334a45a8ff | 268 | #define _ETM_ETMSR_TRIGBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSR */ |
| bogdanm | 0:9b334a45a8ff | 269 | #define ETM_ETMSR_TRIGBIT_DEFAULT (_ETM_ETMSR_TRIGBIT_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMSR */ |
| bogdanm | 0:9b334a45a8ff | 270 | |
| bogdanm | 0:9b334a45a8ff | 271 | /* Bit fields for ETM ETMSCR */ |
| bogdanm | 0:9b334a45a8ff | 272 | #define _ETM_ETMSCR_RESETVALUE 0x00020D09UL /**< Default value for ETM_ETMSCR */ |
| bogdanm | 0:9b334a45a8ff | 273 | #define _ETM_ETMSCR_MASK 0x00027F0FUL /**< Mask for ETM_ETMSCR */ |
| bogdanm | 0:9b334a45a8ff | 274 | #define _ETM_ETMSCR_MAXPORTSIZE_SHIFT 0 /**< Shift value for ETM_MAXPORTSIZE */ |
| bogdanm | 0:9b334a45a8ff | 275 | #define _ETM_ETMSCR_MAXPORTSIZE_MASK 0x7UL /**< Bit mask for ETM_MAXPORTSIZE */ |
| bogdanm | 0:9b334a45a8ff | 276 | #define _ETM_ETMSCR_MAXPORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ |
| bogdanm | 0:9b334a45a8ff | 277 | #define ETM_ETMSCR_MAXPORTSIZE_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSCR */ |
| bogdanm | 0:9b334a45a8ff | 278 | #define ETM_ETMSCR_Reserved (0x1UL << 3) /**< Reserved */ |
| bogdanm | 0:9b334a45a8ff | 279 | #define _ETM_ETMSCR_Reserved_SHIFT 3 /**< Shift value for ETM_Reserved */ |
| bogdanm | 0:9b334a45a8ff | 280 | #define _ETM_ETMSCR_Reserved_MASK 0x8UL /**< Bit mask for ETM_Reserved */ |
| bogdanm | 0:9b334a45a8ff | 281 | #define _ETM_ETMSCR_Reserved_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ |
| bogdanm | 0:9b334a45a8ff | 282 | #define ETM_ETMSCR_Reserved_DEFAULT (_ETM_ETMSCR_Reserved_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMSCR */ |
| bogdanm | 0:9b334a45a8ff | 283 | #define ETM_ETMSCR_FIFOFULL (0x1UL << 8) /**< FIFO FULL Supported */ |
| bogdanm | 0:9b334a45a8ff | 284 | #define _ETM_ETMSCR_FIFOFULL_SHIFT 8 /**< Shift value for ETM_FIFOFULL */ |
| bogdanm | 0:9b334a45a8ff | 285 | #define _ETM_ETMSCR_FIFOFULL_MASK 0x100UL /**< Bit mask for ETM_FIFOFULL */ |
| bogdanm | 0:9b334a45a8ff | 286 | #define _ETM_ETMSCR_FIFOFULL_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ |
| bogdanm | 0:9b334a45a8ff | 287 | #define ETM_ETMSCR_FIFOFULL_DEFAULT (_ETM_ETMSCR_FIFOFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMSCR */ |
| bogdanm | 0:9b334a45a8ff | 288 | #define ETM_ETMSCR_MAXPORTSIZE3 (0x1UL << 9) /**< Max Port Size[3] */ |
| bogdanm | 0:9b334a45a8ff | 289 | #define _ETM_ETMSCR_MAXPORTSIZE3_SHIFT 9 /**< Shift value for ETM_MAXPORTSIZE3 */ |
| bogdanm | 0:9b334a45a8ff | 290 | #define _ETM_ETMSCR_MAXPORTSIZE3_MASK 0x200UL /**< Bit mask for ETM_MAXPORTSIZE3 */ |
| bogdanm | 0:9b334a45a8ff | 291 | #define _ETM_ETMSCR_MAXPORTSIZE3_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */ |
| bogdanm | 0:9b334a45a8ff | 292 | #define ETM_ETMSCR_MAXPORTSIZE3_DEFAULT (_ETM_ETMSCR_MAXPORTSIZE3_DEFAULT << 9) /**< Shifted mode DEFAULT for ETM_ETMSCR */ |
| bogdanm | 0:9b334a45a8ff | 293 | #define ETM_ETMSCR_PORTSIZE (0x1UL << 10) /**< Port Size Supported */ |
| bogdanm | 0:9b334a45a8ff | 294 | #define _ETM_ETMSCR_PORTSIZE_SHIFT 10 /**< Shift value for ETM_PORTSIZE */ |
| bogdanm | 0:9b334a45a8ff | 295 | #define _ETM_ETMSCR_PORTSIZE_MASK 0x400UL /**< Bit mask for ETM_PORTSIZE */ |
| bogdanm | 0:9b334a45a8ff | 296 | #define _ETM_ETMSCR_PORTSIZE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ |
| bogdanm | 0:9b334a45a8ff | 297 | #define ETM_ETMSCR_PORTSIZE_DEFAULT (_ETM_ETMSCR_PORTSIZE_DEFAULT << 10) /**< Shifted mode DEFAULT for ETM_ETMSCR */ |
| bogdanm | 0:9b334a45a8ff | 298 | #define ETM_ETMSCR_PORTMODE (0x1UL << 11) /**< Port Mode Supported */ |
| bogdanm | 0:9b334a45a8ff | 299 | #define _ETM_ETMSCR_PORTMODE_SHIFT 11 /**< Shift value for ETM_PORTMODE */ |
| bogdanm | 0:9b334a45a8ff | 300 | #define _ETM_ETMSCR_PORTMODE_MASK 0x800UL /**< Bit mask for ETM_PORTMODE */ |
| bogdanm | 0:9b334a45a8ff | 301 | #define _ETM_ETMSCR_PORTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ |
| bogdanm | 0:9b334a45a8ff | 302 | #define ETM_ETMSCR_PORTMODE_DEFAULT (_ETM_ETMSCR_PORTMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMSCR */ |
| bogdanm | 0:9b334a45a8ff | 303 | #define _ETM_ETMSCR_PROCNUM_SHIFT 12 /**< Shift value for ETM_PROCNUM */ |
| bogdanm | 0:9b334a45a8ff | 304 | #define _ETM_ETMSCR_PROCNUM_MASK 0x7000UL /**< Bit mask for ETM_PROCNUM */ |
| bogdanm | 0:9b334a45a8ff | 305 | #define _ETM_ETMSCR_PROCNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMSCR */ |
| bogdanm | 0:9b334a45a8ff | 306 | #define ETM_ETMSCR_PROCNUM_DEFAULT (_ETM_ETMSCR_PROCNUM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMSCR */ |
| bogdanm | 0:9b334a45a8ff | 307 | #define ETM_ETMSCR_NOFETCHCOMP (0x1UL << 17) /**< No Fetch Comparison */ |
| bogdanm | 0:9b334a45a8ff | 308 | #define _ETM_ETMSCR_NOFETCHCOMP_SHIFT 17 /**< Shift value for ETM_NOFETCHCOMP */ |
| bogdanm | 0:9b334a45a8ff | 309 | #define _ETM_ETMSCR_NOFETCHCOMP_MASK 0x20000UL /**< Bit mask for ETM_NOFETCHCOMP */ |
| bogdanm | 0:9b334a45a8ff | 310 | #define _ETM_ETMSCR_NOFETCHCOMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMSCR */ |
| bogdanm | 0:9b334a45a8ff | 311 | #define ETM_ETMSCR_NOFETCHCOMP_DEFAULT (_ETM_ETMSCR_NOFETCHCOMP_DEFAULT << 17) /**< Shifted mode DEFAULT for ETM_ETMSCR */ |
| bogdanm | 0:9b334a45a8ff | 312 | |
| bogdanm | 0:9b334a45a8ff | 313 | /* Bit fields for ETM ETMTEEVR */ |
| bogdanm | 0:9b334a45a8ff | 314 | #define _ETM_ETMTEEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTEEVR */ |
| bogdanm | 0:9b334a45a8ff | 315 | #define _ETM_ETMTEEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTEEVR */ |
| bogdanm | 0:9b334a45a8ff | 316 | #define _ETM_ETMTEEVR_RESA_SHIFT 0 /**< Shift value for ETM_RESA */ |
| bogdanm | 0:9b334a45a8ff | 317 | #define _ETM_ETMTEEVR_RESA_MASK 0x7FUL /**< Bit mask for ETM_RESA */ |
| bogdanm | 0:9b334a45a8ff | 318 | #define _ETM_ETMTEEVR_RESA_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */ |
| bogdanm | 0:9b334a45a8ff | 319 | #define ETM_ETMTEEVR_RESA_DEFAULT (_ETM_ETMTEEVR_RESA_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */ |
| bogdanm | 0:9b334a45a8ff | 320 | #define _ETM_ETMTEEVR_RESB_SHIFT 7 /**< Shift value for ETM_RESB */ |
| bogdanm | 0:9b334a45a8ff | 321 | #define _ETM_ETMTEEVR_RESB_MASK 0x3F80UL /**< Bit mask for ETM_RESB */ |
| bogdanm | 0:9b334a45a8ff | 322 | #define _ETM_ETMTEEVR_RESB_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */ |
| bogdanm | 0:9b334a45a8ff | 323 | #define ETM_ETMTEEVR_RESB_DEFAULT (_ETM_ETMTEEVR_RESB_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */ |
| bogdanm | 0:9b334a45a8ff | 324 | #define _ETM_ETMTEEVR_ETMFCNEN_SHIFT 14 /**< Shift value for ETM_ETMFCNEN */ |
| bogdanm | 0:9b334a45a8ff | 325 | #define _ETM_ETMTEEVR_ETMFCNEN_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEN */ |
| bogdanm | 0:9b334a45a8ff | 326 | #define _ETM_ETMTEEVR_ETMFCNEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTEEVR */ |
| bogdanm | 0:9b334a45a8ff | 327 | #define ETM_ETMTEEVR_ETMFCNEN_DEFAULT (_ETM_ETMTEEVR_ETMFCNEN_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTEEVR */ |
| bogdanm | 0:9b334a45a8ff | 328 | |
| bogdanm | 0:9b334a45a8ff | 329 | /* Bit fields for ETM ETMTECR1 */ |
| bogdanm | 0:9b334a45a8ff | 330 | #define _ETM_ETMTECR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTECR1 */ |
| bogdanm | 0:9b334a45a8ff | 331 | #define _ETM_ETMTECR1_MASK 0x03FFFFFFUL /**< Mask for ETM_ETMTECR1 */ |
| bogdanm | 0:9b334a45a8ff | 332 | #define _ETM_ETMTECR1_ADRCMP_SHIFT 0 /**< Shift value for ETM_ADRCMP */ |
| bogdanm | 0:9b334a45a8ff | 333 | #define _ETM_ETMTECR1_ADRCMP_MASK 0xFFUL /**< Bit mask for ETM_ADRCMP */ |
| bogdanm | 0:9b334a45a8ff | 334 | #define _ETM_ETMTECR1_ADRCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ |
| bogdanm | 0:9b334a45a8ff | 335 | #define ETM_ETMTECR1_ADRCMP_DEFAULT (_ETM_ETMTECR1_ADRCMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ |
| bogdanm | 0:9b334a45a8ff | 336 | #define _ETM_ETMTECR1_MEMMAP_SHIFT 8 /**< Shift value for ETM_MEMMAP */ |
| bogdanm | 0:9b334a45a8ff | 337 | #define _ETM_ETMTECR1_MEMMAP_MASK 0xFFFF00UL /**< Bit mask for ETM_MEMMAP */ |
| bogdanm | 0:9b334a45a8ff | 338 | #define _ETM_ETMTECR1_MEMMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ |
| bogdanm | 0:9b334a45a8ff | 339 | #define ETM_ETMTECR1_MEMMAP_DEFAULT (_ETM_ETMTECR1_MEMMAP_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ |
| bogdanm | 0:9b334a45a8ff | 340 | #define ETM_ETMTECR1_INCEXCTL (0x1UL << 24) /**< Trace Include/Exclude Flag */ |
| bogdanm | 0:9b334a45a8ff | 341 | #define _ETM_ETMTECR1_INCEXCTL_SHIFT 24 /**< Shift value for ETM_INCEXCTL */ |
| bogdanm | 0:9b334a45a8ff | 342 | #define _ETM_ETMTECR1_INCEXCTL_MASK 0x1000000UL /**< Bit mask for ETM_INCEXCTL */ |
| bogdanm | 0:9b334a45a8ff | 343 | #define _ETM_ETMTECR1_INCEXCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ |
| bogdanm | 0:9b334a45a8ff | 344 | #define _ETM_ETMTECR1_INCEXCTL_INC 0x00000000UL /**< Mode INC for ETM_ETMTECR1 */ |
| bogdanm | 0:9b334a45a8ff | 345 | #define _ETM_ETMTECR1_INCEXCTL_EXC 0x00000001UL /**< Mode EXC for ETM_ETMTECR1 */ |
| bogdanm | 0:9b334a45a8ff | 346 | #define ETM_ETMTECR1_INCEXCTL_DEFAULT (_ETM_ETMTECR1_INCEXCTL_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ |
| bogdanm | 0:9b334a45a8ff | 347 | #define ETM_ETMTECR1_INCEXCTL_INC (_ETM_ETMTECR1_INCEXCTL_INC << 24) /**< Shifted mode INC for ETM_ETMTECR1 */ |
| bogdanm | 0:9b334a45a8ff | 348 | #define ETM_ETMTECR1_INCEXCTL_EXC (_ETM_ETMTECR1_INCEXCTL_EXC << 24) /**< Shifted mode EXC for ETM_ETMTECR1 */ |
| bogdanm | 0:9b334a45a8ff | 349 | #define ETM_ETMTECR1_TCE (0x1UL << 25) /**< Trace Control Enable */ |
| bogdanm | 0:9b334a45a8ff | 350 | #define _ETM_ETMTECR1_TCE_SHIFT 25 /**< Shift value for ETM_TCE */ |
| bogdanm | 0:9b334a45a8ff | 351 | #define _ETM_ETMTECR1_TCE_MASK 0x2000000UL /**< Bit mask for ETM_TCE */ |
| bogdanm | 0:9b334a45a8ff | 352 | #define _ETM_ETMTECR1_TCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTECR1 */ |
| bogdanm | 0:9b334a45a8ff | 353 | #define _ETM_ETMTECR1_TCE_EN 0x00000000UL /**< Mode EN for ETM_ETMTECR1 */ |
| bogdanm | 0:9b334a45a8ff | 354 | #define _ETM_ETMTECR1_TCE_DIS 0x00000001UL /**< Mode DIS for ETM_ETMTECR1 */ |
| bogdanm | 0:9b334a45a8ff | 355 | #define ETM_ETMTECR1_TCE_DEFAULT (_ETM_ETMTECR1_TCE_DEFAULT << 25) /**< Shifted mode DEFAULT for ETM_ETMTECR1 */ |
| bogdanm | 0:9b334a45a8ff | 356 | #define ETM_ETMTECR1_TCE_EN (_ETM_ETMTECR1_TCE_EN << 25) /**< Shifted mode EN for ETM_ETMTECR1 */ |
| bogdanm | 0:9b334a45a8ff | 357 | #define ETM_ETMTECR1_TCE_DIS (_ETM_ETMTECR1_TCE_DIS << 25) /**< Shifted mode DIS for ETM_ETMTECR1 */ |
| bogdanm | 0:9b334a45a8ff | 358 | |
| bogdanm | 0:9b334a45a8ff | 359 | /* Bit fields for ETM ETMFFLR */ |
| bogdanm | 0:9b334a45a8ff | 360 | #define _ETM_ETMFFLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMFFLR */ |
| bogdanm | 0:9b334a45a8ff | 361 | #define _ETM_ETMFFLR_MASK 0x000000FFUL /**< Mask for ETM_ETMFFLR */ |
| bogdanm | 0:9b334a45a8ff | 362 | #define _ETM_ETMFFLR_BYTENUM_SHIFT 0 /**< Shift value for ETM_BYTENUM */ |
| bogdanm | 0:9b334a45a8ff | 363 | #define _ETM_ETMFFLR_BYTENUM_MASK 0xFFUL /**< Bit mask for ETM_BYTENUM */ |
| bogdanm | 0:9b334a45a8ff | 364 | #define _ETM_ETMFFLR_BYTENUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMFFLR */ |
| bogdanm | 0:9b334a45a8ff | 365 | #define ETM_ETMFFLR_BYTENUM_DEFAULT (_ETM_ETMFFLR_BYTENUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMFFLR */ |
| bogdanm | 0:9b334a45a8ff | 366 | |
| bogdanm | 0:9b334a45a8ff | 367 | /* Bit fields for ETM ETMCNTRLDVR1 */ |
| bogdanm | 0:9b334a45a8ff | 368 | #define _ETM_ETMCNTRLDVR1_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCNTRLDVR1 */ |
| bogdanm | 0:9b334a45a8ff | 369 | #define _ETM_ETMCNTRLDVR1_MASK 0x0000FFFFUL /**< Mask for ETM_ETMCNTRLDVR1 */ |
| bogdanm | 0:9b334a45a8ff | 370 | #define _ETM_ETMCNTRLDVR1_COUNT_SHIFT 0 /**< Shift value for ETM_COUNT */ |
| bogdanm | 0:9b334a45a8ff | 371 | #define _ETM_ETMCNTRLDVR1_COUNT_MASK 0xFFFFUL /**< Bit mask for ETM_COUNT */ |
| bogdanm | 0:9b334a45a8ff | 372 | #define _ETM_ETMCNTRLDVR1_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCNTRLDVR1 */ |
| bogdanm | 0:9b334a45a8ff | 373 | #define ETM_ETMCNTRLDVR1_COUNT_DEFAULT (_ETM_ETMCNTRLDVR1_COUNT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCNTRLDVR1 */ |
| bogdanm | 0:9b334a45a8ff | 374 | |
| bogdanm | 0:9b334a45a8ff | 375 | /* Bit fields for ETM ETMSYNCFR */ |
| bogdanm | 0:9b334a45a8ff | 376 | #define _ETM_ETMSYNCFR_RESETVALUE 0x00000400UL /**< Default value for ETM_ETMSYNCFR */ |
| bogdanm | 0:9b334a45a8ff | 377 | #define _ETM_ETMSYNCFR_MASK 0x00000FFFUL /**< Mask for ETM_ETMSYNCFR */ |
| bogdanm | 0:9b334a45a8ff | 378 | #define _ETM_ETMSYNCFR_FREQ_SHIFT 0 /**< Shift value for ETM_FREQ */ |
| bogdanm | 0:9b334a45a8ff | 379 | #define _ETM_ETMSYNCFR_FREQ_MASK 0xFFFUL /**< Bit mask for ETM_FREQ */ |
| bogdanm | 0:9b334a45a8ff | 380 | #define _ETM_ETMSYNCFR_FREQ_DEFAULT 0x00000400UL /**< Mode DEFAULT for ETM_ETMSYNCFR */ |
| bogdanm | 0:9b334a45a8ff | 381 | #define ETM_ETMSYNCFR_FREQ_DEFAULT (_ETM_ETMSYNCFR_FREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMSYNCFR */ |
| bogdanm | 0:9b334a45a8ff | 382 | |
| bogdanm | 0:9b334a45a8ff | 383 | /* Bit fields for ETM ETMIDR */ |
| bogdanm | 0:9b334a45a8ff | 384 | #define _ETM_ETMIDR_RESETVALUE 0x4114F253UL /**< Default value for ETM_ETMIDR */ |
| bogdanm | 0:9b334a45a8ff | 385 | #define _ETM_ETMIDR_MASK 0xFF1DFFFFUL /**< Mask for ETM_ETMIDR */ |
| bogdanm | 0:9b334a45a8ff | 386 | #define _ETM_ETMIDR_IMPVER_SHIFT 0 /**< Shift value for ETM_IMPVER */ |
| bogdanm | 0:9b334a45a8ff | 387 | #define _ETM_ETMIDR_IMPVER_MASK 0xFUL /**< Bit mask for ETM_IMPVER */ |
| bogdanm | 0:9b334a45a8ff | 388 | #define _ETM_ETMIDR_IMPVER_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMIDR */ |
| bogdanm | 0:9b334a45a8ff | 389 | #define ETM_ETMIDR_IMPVER_DEFAULT (_ETM_ETMIDR_IMPVER_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR */ |
| bogdanm | 0:9b334a45a8ff | 390 | #define _ETM_ETMIDR_ETMMINVER_SHIFT 4 /**< Shift value for ETM_ETMMINVER */ |
| bogdanm | 0:9b334a45a8ff | 391 | #define _ETM_ETMIDR_ETMMINVER_MASK 0xF0UL /**< Bit mask for ETM_ETMMINVER */ |
| bogdanm | 0:9b334a45a8ff | 392 | #define _ETM_ETMIDR_ETMMINVER_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMIDR */ |
| bogdanm | 0:9b334a45a8ff | 393 | #define ETM_ETMIDR_ETMMINVER_DEFAULT (_ETM_ETMIDR_ETMMINVER_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMIDR */ |
| bogdanm | 0:9b334a45a8ff | 394 | #define _ETM_ETMIDR_ETMMAJVER_SHIFT 8 /**< Shift value for ETM_ETMMAJVER */ |
| bogdanm | 0:9b334a45a8ff | 395 | #define _ETM_ETMIDR_ETMMAJVER_MASK 0xF00UL /**< Bit mask for ETM_ETMMAJVER */ |
| bogdanm | 0:9b334a45a8ff | 396 | #define _ETM_ETMIDR_ETMMAJVER_DEFAULT 0x00000002UL /**< Mode DEFAULT for ETM_ETMIDR */ |
| bogdanm | 0:9b334a45a8ff | 397 | #define ETM_ETMIDR_ETMMAJVER_DEFAULT (_ETM_ETMIDR_ETMMAJVER_DEFAULT << 8) /**< Shifted mode DEFAULT for ETM_ETMIDR */ |
| bogdanm | 0:9b334a45a8ff | 398 | #define _ETM_ETMIDR_PROCFAM_SHIFT 12 /**< Shift value for ETM_PROCFAM */ |
| bogdanm | 0:9b334a45a8ff | 399 | #define _ETM_ETMIDR_PROCFAM_MASK 0xF000UL /**< Bit mask for ETM_PROCFAM */ |
| bogdanm | 0:9b334a45a8ff | 400 | #define _ETM_ETMIDR_PROCFAM_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMIDR */ |
| bogdanm | 0:9b334a45a8ff | 401 | #define ETM_ETMIDR_PROCFAM_DEFAULT (_ETM_ETMIDR_PROCFAM_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMIDR */ |
| bogdanm | 0:9b334a45a8ff | 402 | #define ETM_ETMIDR_LPCF (0x1UL << 16) /**< Load PC First */ |
| bogdanm | 0:9b334a45a8ff | 403 | #define _ETM_ETMIDR_LPCF_SHIFT 16 /**< Shift value for ETM_LPCF */ |
| bogdanm | 0:9b334a45a8ff | 404 | #define _ETM_ETMIDR_LPCF_MASK 0x10000UL /**< Bit mask for ETM_LPCF */ |
| bogdanm | 0:9b334a45a8ff | 405 | #define _ETM_ETMIDR_LPCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */ |
| bogdanm | 0:9b334a45a8ff | 406 | #define ETM_ETMIDR_LPCF_DEFAULT (_ETM_ETMIDR_LPCF_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMIDR */ |
| bogdanm | 0:9b334a45a8ff | 407 | #define ETM_ETMIDR_THUMBT (0x1UL << 18) /**< 32-bit Thumb Instruction Tracing */ |
| bogdanm | 0:9b334a45a8ff | 408 | #define _ETM_ETMIDR_THUMBT_SHIFT 18 /**< Shift value for ETM_THUMBT */ |
| bogdanm | 0:9b334a45a8ff | 409 | #define _ETM_ETMIDR_THUMBT_MASK 0x40000UL /**< Bit mask for ETM_THUMBT */ |
| bogdanm | 0:9b334a45a8ff | 410 | #define _ETM_ETMIDR_THUMBT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */ |
| bogdanm | 0:9b334a45a8ff | 411 | #define ETM_ETMIDR_THUMBT_DEFAULT (_ETM_ETMIDR_THUMBT_DEFAULT << 18) /**< Shifted mode DEFAULT for ETM_ETMIDR */ |
| bogdanm | 0:9b334a45a8ff | 412 | #define ETM_ETMIDR_SECEXT (0x1UL << 19) /**< Security Extension Support */ |
| bogdanm | 0:9b334a45a8ff | 413 | #define _ETM_ETMIDR_SECEXT_SHIFT 19 /**< Shift value for ETM_SECEXT */ |
| bogdanm | 0:9b334a45a8ff | 414 | #define _ETM_ETMIDR_SECEXT_MASK 0x80000UL /**< Bit mask for ETM_SECEXT */ |
| bogdanm | 0:9b334a45a8ff | 415 | #define _ETM_ETMIDR_SECEXT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR */ |
| bogdanm | 0:9b334a45a8ff | 416 | #define ETM_ETMIDR_SECEXT_DEFAULT (_ETM_ETMIDR_SECEXT_DEFAULT << 19) /**< Shifted mode DEFAULT for ETM_ETMIDR */ |
| bogdanm | 0:9b334a45a8ff | 417 | #define ETM_ETMIDR_BPE (0x1UL << 20) /**< Branch Packet Encoding */ |
| bogdanm | 0:9b334a45a8ff | 418 | #define _ETM_ETMIDR_BPE_SHIFT 20 /**< Shift value for ETM_BPE */ |
| bogdanm | 0:9b334a45a8ff | 419 | #define _ETM_ETMIDR_BPE_MASK 0x100000UL /**< Bit mask for ETM_BPE */ |
| bogdanm | 0:9b334a45a8ff | 420 | #define _ETM_ETMIDR_BPE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMIDR */ |
| bogdanm | 0:9b334a45a8ff | 421 | #define ETM_ETMIDR_BPE_DEFAULT (_ETM_ETMIDR_BPE_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMIDR */ |
| bogdanm | 0:9b334a45a8ff | 422 | #define _ETM_ETMIDR_IMPCODE_SHIFT 24 /**< Shift value for ETM_IMPCODE */ |
| bogdanm | 0:9b334a45a8ff | 423 | #define _ETM_ETMIDR_IMPCODE_MASK 0xFF000000UL /**< Bit mask for ETM_IMPCODE */ |
| bogdanm | 0:9b334a45a8ff | 424 | #define _ETM_ETMIDR_IMPCODE_DEFAULT 0x00000041UL /**< Mode DEFAULT for ETM_ETMIDR */ |
| bogdanm | 0:9b334a45a8ff | 425 | #define ETM_ETMIDR_IMPCODE_DEFAULT (_ETM_ETMIDR_IMPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for ETM_ETMIDR */ |
| bogdanm | 0:9b334a45a8ff | 426 | |
| bogdanm | 0:9b334a45a8ff | 427 | /* Bit fields for ETM ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 428 | #define _ETM_ETMCCER_RESETVALUE 0x18541800UL /**< Default value for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 429 | #define _ETM_ETMCCER_MASK 0x387FFFFBUL /**< Mask for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 430 | #define _ETM_ETMCCER_EXTINPSEL_SHIFT 0 /**< Shift value for ETM_EXTINPSEL */ |
| bogdanm | 0:9b334a45a8ff | 431 | #define _ETM_ETMCCER_EXTINPSEL_MASK 0x3UL /**< Bit mask for ETM_EXTINPSEL */ |
| bogdanm | 0:9b334a45a8ff | 432 | #define _ETM_ETMCCER_EXTINPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 433 | #define ETM_ETMCCER_EXTINPSEL_DEFAULT (_ETM_ETMCCER_EXTINPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 434 | #define _ETM_ETMCCER_EXTINPBUS_SHIFT 3 /**< Shift value for ETM_EXTINPBUS */ |
| bogdanm | 0:9b334a45a8ff | 435 | #define _ETM_ETMCCER_EXTINPBUS_MASK 0x7F8UL /**< Bit mask for ETM_EXTINPBUS */ |
| bogdanm | 0:9b334a45a8ff | 436 | #define _ETM_ETMCCER_EXTINPBUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 437 | #define ETM_ETMCCER_EXTINPBUS_DEFAULT (_ETM_ETMCCER_EXTINPBUS_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 438 | #define ETM_ETMCCER_READREGS (0x1UL << 11) /**< Readable Registers */ |
| bogdanm | 0:9b334a45a8ff | 439 | #define _ETM_ETMCCER_READREGS_SHIFT 11 /**< Shift value for ETM_READREGS */ |
| bogdanm | 0:9b334a45a8ff | 440 | #define _ETM_ETMCCER_READREGS_MASK 0x800UL /**< Bit mask for ETM_READREGS */ |
| bogdanm | 0:9b334a45a8ff | 441 | #define _ETM_ETMCCER_READREGS_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 442 | #define ETM_ETMCCER_READREGS_DEFAULT (_ETM_ETMCCER_READREGS_DEFAULT << 11) /**< Shifted mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 443 | #define ETM_ETMCCER_DADDRCMP (0x1UL << 12) /**< Data Address comparisons */ |
| bogdanm | 0:9b334a45a8ff | 444 | #define _ETM_ETMCCER_DADDRCMP_SHIFT 12 /**< Shift value for ETM_DADDRCMP */ |
| bogdanm | 0:9b334a45a8ff | 445 | #define _ETM_ETMCCER_DADDRCMP_MASK 0x1000UL /**< Bit mask for ETM_DADDRCMP */ |
| bogdanm | 0:9b334a45a8ff | 446 | #define _ETM_ETMCCER_DADDRCMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 447 | #define ETM_ETMCCER_DADDRCMP_DEFAULT (_ETM_ETMCCER_DADDRCMP_DEFAULT << 12) /**< Shifted mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 448 | #define _ETM_ETMCCER_INSTRES_SHIFT 13 /**< Shift value for ETM_INSTRES */ |
| bogdanm | 0:9b334a45a8ff | 449 | #define _ETM_ETMCCER_INSTRES_MASK 0xE000UL /**< Bit mask for ETM_INSTRES */ |
| bogdanm | 0:9b334a45a8ff | 450 | #define _ETM_ETMCCER_INSTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 451 | #define ETM_ETMCCER_INSTRES_DEFAULT (_ETM_ETMCCER_INSTRES_DEFAULT << 13) /**< Shifted mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 452 | #define _ETM_ETMCCER_EICEWPNT_SHIFT 16 /**< Shift value for ETM_EICEWPNT */ |
| bogdanm | 0:9b334a45a8ff | 453 | #define _ETM_ETMCCER_EICEWPNT_MASK 0xF0000UL /**< Bit mask for ETM_EICEWPNT */ |
| bogdanm | 0:9b334a45a8ff | 454 | #define _ETM_ETMCCER_EICEWPNT_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 455 | #define ETM_ETMCCER_EICEWPNT_DEFAULT (_ETM_ETMCCER_EICEWPNT_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 456 | #define ETM_ETMCCER_TEICEWPNT (0x1UL << 20) /**< Trace Sart/Stop Block Uses EmbeddedICE watchpoint inputs */ |
| bogdanm | 0:9b334a45a8ff | 457 | #define _ETM_ETMCCER_TEICEWPNT_SHIFT 20 /**< Shift value for ETM_TEICEWPNT */ |
| bogdanm | 0:9b334a45a8ff | 458 | #define _ETM_ETMCCER_TEICEWPNT_MASK 0x100000UL /**< Bit mask for ETM_TEICEWPNT */ |
| bogdanm | 0:9b334a45a8ff | 459 | #define _ETM_ETMCCER_TEICEWPNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 460 | #define ETM_ETMCCER_TEICEWPNT_DEFAULT (_ETM_ETMCCER_TEICEWPNT_DEFAULT << 20) /**< Shifted mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 461 | #define ETM_ETMCCER_EICEIMP (0x1UL << 21) /**< EmbeddedICE Behavior control Implemented */ |
| bogdanm | 0:9b334a45a8ff | 462 | #define _ETM_ETMCCER_EICEIMP_SHIFT 21 /**< Shift value for ETM_EICEIMP */ |
| bogdanm | 0:9b334a45a8ff | 463 | #define _ETM_ETMCCER_EICEIMP_MASK 0x200000UL /**< Bit mask for ETM_EICEIMP */ |
| bogdanm | 0:9b334a45a8ff | 464 | #define _ETM_ETMCCER_EICEIMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 465 | #define ETM_ETMCCER_EICEIMP_DEFAULT (_ETM_ETMCCER_EICEIMP_DEFAULT << 21) /**< Shifted mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 466 | #define ETM_ETMCCER_TIMP (0x1UL << 22) /**< Timestamping Implemented */ |
| bogdanm | 0:9b334a45a8ff | 467 | #define _ETM_ETMCCER_TIMP_SHIFT 22 /**< Shift value for ETM_TIMP */ |
| bogdanm | 0:9b334a45a8ff | 468 | #define _ETM_ETMCCER_TIMP_MASK 0x400000UL /**< Bit mask for ETM_TIMP */ |
| bogdanm | 0:9b334a45a8ff | 469 | #define _ETM_ETMCCER_TIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 470 | #define ETM_ETMCCER_TIMP_DEFAULT (_ETM_ETMCCER_TIMP_DEFAULT << 22) /**< Shifted mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 471 | #define ETM_ETMCCER_RFCNT (0x1UL << 27) /**< Reduced Function Counter */ |
| bogdanm | 0:9b334a45a8ff | 472 | #define _ETM_ETMCCER_RFCNT_SHIFT 27 /**< Shift value for ETM_RFCNT */ |
| bogdanm | 0:9b334a45a8ff | 473 | #define _ETM_ETMCCER_RFCNT_MASK 0x8000000UL /**< Bit mask for ETM_RFCNT */ |
| bogdanm | 0:9b334a45a8ff | 474 | #define _ETM_ETMCCER_RFCNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 475 | #define ETM_ETMCCER_RFCNT_DEFAULT (_ETM_ETMCCER_RFCNT_DEFAULT << 27) /**< Shifted mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 476 | #define ETM_ETMCCER_TENC (0x1UL << 28) /**< Timestamp Encoding */ |
| bogdanm | 0:9b334a45a8ff | 477 | #define _ETM_ETMCCER_TENC_SHIFT 28 /**< Shift value for ETM_TENC */ |
| bogdanm | 0:9b334a45a8ff | 478 | #define _ETM_ETMCCER_TENC_MASK 0x10000000UL /**< Bit mask for ETM_TENC */ |
| bogdanm | 0:9b334a45a8ff | 479 | #define _ETM_ETMCCER_TENC_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 480 | #define ETM_ETMCCER_TENC_DEFAULT (_ETM_ETMCCER_TENC_DEFAULT << 28) /**< Shifted mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 481 | #define ETM_ETMCCER_TSIZE (0x1UL << 29) /**< Timestamp Size */ |
| bogdanm | 0:9b334a45a8ff | 482 | #define _ETM_ETMCCER_TSIZE_SHIFT 29 /**< Shift value for ETM_TSIZE */ |
| bogdanm | 0:9b334a45a8ff | 483 | #define _ETM_ETMCCER_TSIZE_MASK 0x20000000UL /**< Bit mask for ETM_TSIZE */ |
| bogdanm | 0:9b334a45a8ff | 484 | #define _ETM_ETMCCER_TSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 485 | #define ETM_ETMCCER_TSIZE_DEFAULT (_ETM_ETMCCER_TSIZE_DEFAULT << 29) /**< Shifted mode DEFAULT for ETM_ETMCCER */ |
| bogdanm | 0:9b334a45a8ff | 486 | |
| bogdanm | 0:9b334a45a8ff | 487 | /* Bit fields for ETM ETMTESSEICR */ |
| bogdanm | 0:9b334a45a8ff | 488 | #define _ETM_ETMTESSEICR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTESSEICR */ |
| bogdanm | 0:9b334a45a8ff | 489 | #define _ETM_ETMTESSEICR_MASK 0x000F000FUL /**< Mask for ETM_ETMTESSEICR */ |
| bogdanm | 0:9b334a45a8ff | 490 | #define _ETM_ETMTESSEICR_STARTRSEL_SHIFT 0 /**< Shift value for ETM_STARTRSEL */ |
| bogdanm | 0:9b334a45a8ff | 491 | #define _ETM_ETMTESSEICR_STARTRSEL_MASK 0xFUL /**< Bit mask for ETM_STARTRSEL */ |
| bogdanm | 0:9b334a45a8ff | 492 | #define _ETM_ETMTESSEICR_STARTRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */ |
| bogdanm | 0:9b334a45a8ff | 493 | #define ETM_ETMTESSEICR_STARTRSEL_DEFAULT (_ETM_ETMTESSEICR_STARTRSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */ |
| bogdanm | 0:9b334a45a8ff | 494 | #define _ETM_ETMTESSEICR_STOPRSEL_SHIFT 16 /**< Shift value for ETM_STOPRSEL */ |
| bogdanm | 0:9b334a45a8ff | 495 | #define _ETM_ETMTESSEICR_STOPRSEL_MASK 0xF0000UL /**< Bit mask for ETM_STOPRSEL */ |
| bogdanm | 0:9b334a45a8ff | 496 | #define _ETM_ETMTESSEICR_STOPRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTESSEICR */ |
| bogdanm | 0:9b334a45a8ff | 497 | #define ETM_ETMTESSEICR_STOPRSEL_DEFAULT (_ETM_ETMTESSEICR_STOPRSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for ETM_ETMTESSEICR */ |
| bogdanm | 0:9b334a45a8ff | 498 | |
| bogdanm | 0:9b334a45a8ff | 499 | /* Bit fields for ETM ETMTSEVR */ |
| bogdanm | 0:9b334a45a8ff | 500 | #define _ETM_ETMTSEVR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTSEVR */ |
| bogdanm | 0:9b334a45a8ff | 501 | #define _ETM_ETMTSEVR_MASK 0x0001FFFFUL /**< Mask for ETM_ETMTSEVR */ |
| bogdanm | 0:9b334a45a8ff | 502 | #define _ETM_ETMTSEVR_RESAEVT_SHIFT 0 /**< Shift value for ETM_RESAEVT */ |
| bogdanm | 0:9b334a45a8ff | 503 | #define _ETM_ETMTSEVR_RESAEVT_MASK 0x7FUL /**< Bit mask for ETM_RESAEVT */ |
| bogdanm | 0:9b334a45a8ff | 504 | #define _ETM_ETMTSEVR_RESAEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */ |
| bogdanm | 0:9b334a45a8ff | 505 | #define ETM_ETMTSEVR_RESAEVT_DEFAULT (_ETM_ETMTSEVR_RESAEVT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */ |
| bogdanm | 0:9b334a45a8ff | 506 | #define _ETM_ETMTSEVR_RESBEVT_SHIFT 7 /**< Shift value for ETM_RESBEVT */ |
| bogdanm | 0:9b334a45a8ff | 507 | #define _ETM_ETMTSEVR_RESBEVT_MASK 0x3F80UL /**< Bit mask for ETM_RESBEVT */ |
| bogdanm | 0:9b334a45a8ff | 508 | #define _ETM_ETMTSEVR_RESBEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */ |
| bogdanm | 0:9b334a45a8ff | 509 | #define ETM_ETMTSEVR_RESBEVT_DEFAULT (_ETM_ETMTSEVR_RESBEVT_DEFAULT << 7) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */ |
| bogdanm | 0:9b334a45a8ff | 510 | #define _ETM_ETMTSEVR_ETMFCNEVT_SHIFT 14 /**< Shift value for ETM_ETMFCNEVT */ |
| bogdanm | 0:9b334a45a8ff | 511 | #define _ETM_ETMTSEVR_ETMFCNEVT_MASK 0x1C000UL /**< Bit mask for ETM_ETMFCNEVT */ |
| bogdanm | 0:9b334a45a8ff | 512 | #define _ETM_ETMTSEVR_ETMFCNEVT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTSEVR */ |
| bogdanm | 0:9b334a45a8ff | 513 | #define ETM_ETMTSEVR_ETMFCNEVT_DEFAULT (_ETM_ETMTSEVR_ETMFCNEVT_DEFAULT << 14) /**< Shifted mode DEFAULT for ETM_ETMTSEVR */ |
| bogdanm | 0:9b334a45a8ff | 514 | |
| bogdanm | 0:9b334a45a8ff | 515 | /* Bit fields for ETM ETMTRACEIDR */ |
| bogdanm | 0:9b334a45a8ff | 516 | #define _ETM_ETMTRACEIDR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMTRACEIDR */ |
| bogdanm | 0:9b334a45a8ff | 517 | #define _ETM_ETMTRACEIDR_MASK 0x0000007FUL /**< Mask for ETM_ETMTRACEIDR */ |
| bogdanm | 0:9b334a45a8ff | 518 | #define _ETM_ETMTRACEIDR_TRACEID_SHIFT 0 /**< Shift value for ETM_TRACEID */ |
| bogdanm | 0:9b334a45a8ff | 519 | #define _ETM_ETMTRACEIDR_TRACEID_MASK 0x7FUL /**< Bit mask for ETM_TRACEID */ |
| bogdanm | 0:9b334a45a8ff | 520 | #define _ETM_ETMTRACEIDR_TRACEID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMTRACEIDR */ |
| bogdanm | 0:9b334a45a8ff | 521 | #define ETM_ETMTRACEIDR_TRACEID_DEFAULT (_ETM_ETMTRACEIDR_TRACEID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMTRACEIDR */ |
| bogdanm | 0:9b334a45a8ff | 522 | |
| bogdanm | 0:9b334a45a8ff | 523 | /* Bit fields for ETM ETMIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 524 | #define _ETM_ETMIDR2_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 525 | #define _ETM_ETMIDR2_MASK 0x00000003UL /**< Mask for ETM_ETMIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 526 | #define ETM_ETMIDR2_RFE (0x1UL << 0) /**< RFE Transfer Order */ |
| bogdanm | 0:9b334a45a8ff | 527 | #define _ETM_ETMIDR2_RFE_SHIFT 0 /**< Shift value for ETM_RFE */ |
| bogdanm | 0:9b334a45a8ff | 528 | #define _ETM_ETMIDR2_RFE_MASK 0x1UL /**< Bit mask for ETM_RFE */ |
| bogdanm | 0:9b334a45a8ff | 529 | #define _ETM_ETMIDR2_RFE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 530 | #define _ETM_ETMIDR2_RFE_PC 0x00000000UL /**< Mode PC for ETM_ETMIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 531 | #define _ETM_ETMIDR2_RFE_CPSR 0x00000001UL /**< Mode CPSR for ETM_ETMIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 532 | #define ETM_ETMIDR2_RFE_DEFAULT (_ETM_ETMIDR2_RFE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 533 | #define ETM_ETMIDR2_RFE_PC (_ETM_ETMIDR2_RFE_PC << 0) /**< Shifted mode PC for ETM_ETMIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 534 | #define ETM_ETMIDR2_RFE_CPSR (_ETM_ETMIDR2_RFE_CPSR << 0) /**< Shifted mode CPSR for ETM_ETMIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 535 | #define ETM_ETMIDR2_SWP (0x1UL << 1) /**< SWP Transfer Order */ |
| bogdanm | 0:9b334a45a8ff | 536 | #define _ETM_ETMIDR2_SWP_SHIFT 1 /**< Shift value for ETM_SWP */ |
| bogdanm | 0:9b334a45a8ff | 537 | #define _ETM_ETMIDR2_SWP_MASK 0x2UL /**< Bit mask for ETM_SWP */ |
| bogdanm | 0:9b334a45a8ff | 538 | #define _ETM_ETMIDR2_SWP_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 539 | #define _ETM_ETMIDR2_SWP_LOAD 0x00000000UL /**< Mode LOAD for ETM_ETMIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 540 | #define _ETM_ETMIDR2_SWP_STORE 0x00000001UL /**< Mode STORE for ETM_ETMIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 541 | #define ETM_ETMIDR2_SWP_DEFAULT (_ETM_ETMIDR2_SWP_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 542 | #define ETM_ETMIDR2_SWP_LOAD (_ETM_ETMIDR2_SWP_LOAD << 1) /**< Shifted mode LOAD for ETM_ETMIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 543 | #define ETM_ETMIDR2_SWP_STORE (_ETM_ETMIDR2_SWP_STORE << 1) /**< Shifted mode STORE for ETM_ETMIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 544 | |
| bogdanm | 0:9b334a45a8ff | 545 | /* Bit fields for ETM ETMPDSR */ |
| bogdanm | 0:9b334a45a8ff | 546 | #define _ETM_ETMPDSR_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMPDSR */ |
| bogdanm | 0:9b334a45a8ff | 547 | #define _ETM_ETMPDSR_MASK 0x00000001UL /**< Mask for ETM_ETMPDSR */ |
| bogdanm | 0:9b334a45a8ff | 548 | #define ETM_ETMPDSR_ETMUP (0x1UL << 0) /**< ETM Powered Up */ |
| bogdanm | 0:9b334a45a8ff | 549 | #define _ETM_ETMPDSR_ETMUP_SHIFT 0 /**< Shift value for ETM_ETMUP */ |
| bogdanm | 0:9b334a45a8ff | 550 | #define _ETM_ETMPDSR_ETMUP_MASK 0x1UL /**< Bit mask for ETM_ETMUP */ |
| bogdanm | 0:9b334a45a8ff | 551 | #define _ETM_ETMPDSR_ETMUP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPDSR */ |
| bogdanm | 0:9b334a45a8ff | 552 | #define ETM_ETMPDSR_ETMUP_DEFAULT (_ETM_ETMPDSR_ETMUP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPDSR */ |
| bogdanm | 0:9b334a45a8ff | 553 | |
| bogdanm | 0:9b334a45a8ff | 554 | /* Bit fields for ETM ETMISCIN */ |
| bogdanm | 0:9b334a45a8ff | 555 | #define _ETM_ETMISCIN_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMISCIN */ |
| bogdanm | 0:9b334a45a8ff | 556 | #define _ETM_ETMISCIN_MASK 0x00000013UL /**< Mask for ETM_ETMISCIN */ |
| bogdanm | 0:9b334a45a8ff | 557 | #define _ETM_ETMISCIN_EXTIN_SHIFT 0 /**< Shift value for ETM_EXTIN */ |
| bogdanm | 0:9b334a45a8ff | 558 | #define _ETM_ETMISCIN_EXTIN_MASK 0x3UL /**< Bit mask for ETM_EXTIN */ |
| bogdanm | 0:9b334a45a8ff | 559 | #define _ETM_ETMISCIN_EXTIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */ |
| bogdanm | 0:9b334a45a8ff | 560 | #define ETM_ETMISCIN_EXTIN_DEFAULT (_ETM_ETMISCIN_EXTIN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMISCIN */ |
| bogdanm | 0:9b334a45a8ff | 561 | #define ETM_ETMISCIN_COREHALT (0x1UL << 4) /**< Core Halt */ |
| bogdanm | 0:9b334a45a8ff | 562 | #define _ETM_ETMISCIN_COREHALT_SHIFT 4 /**< Shift value for ETM_COREHALT */ |
| bogdanm | 0:9b334a45a8ff | 563 | #define _ETM_ETMISCIN_COREHALT_MASK 0x10UL /**< Bit mask for ETM_COREHALT */ |
| bogdanm | 0:9b334a45a8ff | 564 | #define _ETM_ETMISCIN_COREHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMISCIN */ |
| bogdanm | 0:9b334a45a8ff | 565 | #define ETM_ETMISCIN_COREHALT_DEFAULT (_ETM_ETMISCIN_COREHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMISCIN */ |
| bogdanm | 0:9b334a45a8ff | 566 | |
| bogdanm | 0:9b334a45a8ff | 567 | /* Bit fields for ETM ITTRIGOUT */ |
| bogdanm | 0:9b334a45a8ff | 568 | #define _ETM_ITTRIGOUT_RESETVALUE 0x00000000UL /**< Default value for ETM_ITTRIGOUT */ |
| bogdanm | 0:9b334a45a8ff | 569 | #define _ETM_ITTRIGOUT_MASK 0x00000001UL /**< Mask for ETM_ITTRIGOUT */ |
| bogdanm | 0:9b334a45a8ff | 570 | #define ETM_ITTRIGOUT_TRIGGEROUT (0x1UL << 0) /**< Trigger output value */ |
| bogdanm | 0:9b334a45a8ff | 571 | #define _ETM_ITTRIGOUT_TRIGGEROUT_SHIFT 0 /**< Shift value for ETM_TRIGGEROUT */ |
| bogdanm | 0:9b334a45a8ff | 572 | #define _ETM_ITTRIGOUT_TRIGGEROUT_MASK 0x1UL /**< Bit mask for ETM_TRIGGEROUT */ |
| bogdanm | 0:9b334a45a8ff | 573 | #define _ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ITTRIGOUT */ |
| bogdanm | 0:9b334a45a8ff | 574 | #define ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT (_ETM_ITTRIGOUT_TRIGGEROUT_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ITTRIGOUT */ |
| bogdanm | 0:9b334a45a8ff | 575 | |
| bogdanm | 0:9b334a45a8ff | 576 | /* Bit fields for ETM ETMITATBCTR2 */ |
| bogdanm | 0:9b334a45a8ff | 577 | #define _ETM_ETMITATBCTR2_RESETVALUE 0x00000001UL /**< Default value for ETM_ETMITATBCTR2 */ |
| bogdanm | 0:9b334a45a8ff | 578 | #define _ETM_ETMITATBCTR2_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR2 */ |
| bogdanm | 0:9b334a45a8ff | 579 | #define ETM_ETMITATBCTR2_ATREADY (0x1UL << 0) /**< ATREADY Input Value */ |
| bogdanm | 0:9b334a45a8ff | 580 | #define _ETM_ETMITATBCTR2_ATREADY_SHIFT 0 /**< Shift value for ETM_ATREADY */ |
| bogdanm | 0:9b334a45a8ff | 581 | #define _ETM_ETMITATBCTR2_ATREADY_MASK 0x1UL /**< Bit mask for ETM_ATREADY */ |
| bogdanm | 0:9b334a45a8ff | 582 | #define _ETM_ETMITATBCTR2_ATREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMITATBCTR2 */ |
| bogdanm | 0:9b334a45a8ff | 583 | #define ETM_ETMITATBCTR2_ATREADY_DEFAULT (_ETM_ETMITATBCTR2_ATREADY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR2 */ |
| bogdanm | 0:9b334a45a8ff | 584 | |
| bogdanm | 0:9b334a45a8ff | 585 | /* Bit fields for ETM ETMITATBCTR0 */ |
| bogdanm | 0:9b334a45a8ff | 586 | #define _ETM_ETMITATBCTR0_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITATBCTR0 */ |
| bogdanm | 0:9b334a45a8ff | 587 | #define _ETM_ETMITATBCTR0_MASK 0x00000001UL /**< Mask for ETM_ETMITATBCTR0 */ |
| bogdanm | 0:9b334a45a8ff | 588 | #define ETM_ETMITATBCTR0_ATVALID (0x1UL << 0) /**< ATVALID Output Value */ |
| bogdanm | 0:9b334a45a8ff | 589 | #define _ETM_ETMITATBCTR0_ATVALID_SHIFT 0 /**< Shift value for ETM_ATVALID */ |
| bogdanm | 0:9b334a45a8ff | 590 | #define _ETM_ETMITATBCTR0_ATVALID_MASK 0x1UL /**< Bit mask for ETM_ATVALID */ |
| bogdanm | 0:9b334a45a8ff | 591 | #define _ETM_ETMITATBCTR0_ATVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITATBCTR0 */ |
| bogdanm | 0:9b334a45a8ff | 592 | #define ETM_ETMITATBCTR0_ATVALID_DEFAULT (_ETM_ETMITATBCTR0_ATVALID_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITATBCTR0 */ |
| bogdanm | 0:9b334a45a8ff | 593 | |
| bogdanm | 0:9b334a45a8ff | 594 | /* Bit fields for ETM ETMITCTRL */ |
| bogdanm | 0:9b334a45a8ff | 595 | #define _ETM_ETMITCTRL_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMITCTRL */ |
| bogdanm | 0:9b334a45a8ff | 596 | #define _ETM_ETMITCTRL_MASK 0x00000001UL /**< Mask for ETM_ETMITCTRL */ |
| bogdanm | 0:9b334a45a8ff | 597 | #define ETM_ETMITCTRL_ITEN (0x1UL << 0) /**< Integration Mode Enable */ |
| bogdanm | 0:9b334a45a8ff | 598 | #define _ETM_ETMITCTRL_ITEN_SHIFT 0 /**< Shift value for ETM_ITEN */ |
| bogdanm | 0:9b334a45a8ff | 599 | #define _ETM_ETMITCTRL_ITEN_MASK 0x1UL /**< Bit mask for ETM_ITEN */ |
| bogdanm | 0:9b334a45a8ff | 600 | #define _ETM_ETMITCTRL_ITEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMITCTRL */ |
| bogdanm | 0:9b334a45a8ff | 601 | #define ETM_ETMITCTRL_ITEN_DEFAULT (_ETM_ETMITCTRL_ITEN_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMITCTRL */ |
| bogdanm | 0:9b334a45a8ff | 602 | |
| bogdanm | 0:9b334a45a8ff | 603 | /* Bit fields for ETM ETMCLAIMSET */ |
| bogdanm | 0:9b334a45a8ff | 604 | #define _ETM_ETMCLAIMSET_RESETVALUE 0x0000000FUL /**< Default value for ETM_ETMCLAIMSET */ |
| bogdanm | 0:9b334a45a8ff | 605 | #define _ETM_ETMCLAIMSET_MASK 0x000000FFUL /**< Mask for ETM_ETMCLAIMSET */ |
| bogdanm | 0:9b334a45a8ff | 606 | #define _ETM_ETMCLAIMSET_SETTAG_SHIFT 0 /**< Shift value for ETM_SETTAG */ |
| bogdanm | 0:9b334a45a8ff | 607 | #define _ETM_ETMCLAIMSET_SETTAG_MASK 0xFFUL /**< Bit mask for ETM_SETTAG */ |
| bogdanm | 0:9b334a45a8ff | 608 | #define _ETM_ETMCLAIMSET_SETTAG_DEFAULT 0x0000000FUL /**< Mode DEFAULT for ETM_ETMCLAIMSET */ |
| bogdanm | 0:9b334a45a8ff | 609 | #define ETM_ETMCLAIMSET_SETTAG_DEFAULT (_ETM_ETMCLAIMSET_SETTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMSET */ |
| bogdanm | 0:9b334a45a8ff | 610 | |
| bogdanm | 0:9b334a45a8ff | 611 | /* Bit fields for ETM ETMCLAIMCLR */ |
| bogdanm | 0:9b334a45a8ff | 612 | #define _ETM_ETMCLAIMCLR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMCLAIMCLR */ |
| bogdanm | 0:9b334a45a8ff | 613 | #define _ETM_ETMCLAIMCLR_MASK 0x00000001UL /**< Mask for ETM_ETMCLAIMCLR */ |
| bogdanm | 0:9b334a45a8ff | 614 | #define ETM_ETMCLAIMCLR_CLRTAG (0x1UL << 0) /**< Tag Bits */ |
| bogdanm | 0:9b334a45a8ff | 615 | #define _ETM_ETMCLAIMCLR_CLRTAG_SHIFT 0 /**< Shift value for ETM_CLRTAG */ |
| bogdanm | 0:9b334a45a8ff | 616 | #define _ETM_ETMCLAIMCLR_CLRTAG_MASK 0x1UL /**< Bit mask for ETM_CLRTAG */ |
| bogdanm | 0:9b334a45a8ff | 617 | #define _ETM_ETMCLAIMCLR_CLRTAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMCLAIMCLR */ |
| bogdanm | 0:9b334a45a8ff | 618 | #define ETM_ETMCLAIMCLR_CLRTAG_DEFAULT (_ETM_ETMCLAIMCLR_CLRTAG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCLAIMCLR */ |
| bogdanm | 0:9b334a45a8ff | 619 | |
| bogdanm | 0:9b334a45a8ff | 620 | /* Bit fields for ETM ETMLAR */ |
| bogdanm | 0:9b334a45a8ff | 621 | #define _ETM_ETMLAR_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMLAR */ |
| bogdanm | 0:9b334a45a8ff | 622 | #define _ETM_ETMLAR_MASK 0x00000001UL /**< Mask for ETM_ETMLAR */ |
| bogdanm | 0:9b334a45a8ff | 623 | #define ETM_ETMLAR_KEY (0x1UL << 0) /**< Key Value */ |
| bogdanm | 0:9b334a45a8ff | 624 | #define _ETM_ETMLAR_KEY_SHIFT 0 /**< Shift value for ETM_KEY */ |
| bogdanm | 0:9b334a45a8ff | 625 | #define _ETM_ETMLAR_KEY_MASK 0x1UL /**< Bit mask for ETM_KEY */ |
| bogdanm | 0:9b334a45a8ff | 626 | #define _ETM_ETMLAR_KEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMLAR */ |
| bogdanm | 0:9b334a45a8ff | 627 | #define ETM_ETMLAR_KEY_DEFAULT (_ETM_ETMLAR_KEY_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLAR */ |
| bogdanm | 0:9b334a45a8ff | 628 | |
| bogdanm | 0:9b334a45a8ff | 629 | /* Bit fields for ETM ETMLSR */ |
| bogdanm | 0:9b334a45a8ff | 630 | #define _ETM_ETMLSR_RESETVALUE 0x00000003UL /**< Default value for ETM_ETMLSR */ |
| bogdanm | 0:9b334a45a8ff | 631 | #define _ETM_ETMLSR_MASK 0x00000003UL /**< Mask for ETM_ETMLSR */ |
| bogdanm | 0:9b334a45a8ff | 632 | #define ETM_ETMLSR_LOCKIMP (0x1UL << 0) /**< ETM Locking Implemented */ |
| bogdanm | 0:9b334a45a8ff | 633 | #define _ETM_ETMLSR_LOCKIMP_SHIFT 0 /**< Shift value for ETM_LOCKIMP */ |
| bogdanm | 0:9b334a45a8ff | 634 | #define _ETM_ETMLSR_LOCKIMP_MASK 0x1UL /**< Bit mask for ETM_LOCKIMP */ |
| bogdanm | 0:9b334a45a8ff | 635 | #define _ETM_ETMLSR_LOCKIMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */ |
| bogdanm | 0:9b334a45a8ff | 636 | #define ETM_ETMLSR_LOCKIMP_DEFAULT (_ETM_ETMLSR_LOCKIMP_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMLSR */ |
| bogdanm | 0:9b334a45a8ff | 637 | #define ETM_ETMLSR_LOCKED (0x1UL << 1) /**< ETM locked */ |
| bogdanm | 0:9b334a45a8ff | 638 | #define _ETM_ETMLSR_LOCKED_SHIFT 1 /**< Shift value for ETM_LOCKED */ |
| bogdanm | 0:9b334a45a8ff | 639 | #define _ETM_ETMLSR_LOCKED_MASK 0x2UL /**< Bit mask for ETM_LOCKED */ |
| bogdanm | 0:9b334a45a8ff | 640 | #define _ETM_ETMLSR_LOCKED_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMLSR */ |
| bogdanm | 0:9b334a45a8ff | 641 | #define ETM_ETMLSR_LOCKED_DEFAULT (_ETM_ETMLSR_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for ETM_ETMLSR */ |
| bogdanm | 0:9b334a45a8ff | 642 | |
| bogdanm | 0:9b334a45a8ff | 643 | /* Bit fields for ETM ETMAUTHSTATUS */ |
| bogdanm | 0:9b334a45a8ff | 644 | #define _ETM_ETMAUTHSTATUS_RESETVALUE 0x000000C0UL /**< Default value for ETM_ETMAUTHSTATUS */ |
| bogdanm | 0:9b334a45a8ff | 645 | #define _ETM_ETMAUTHSTATUS_MASK 0x000000FFUL /**< Mask for ETM_ETMAUTHSTATUS */ |
| bogdanm | 0:9b334a45a8ff | 646 | #define _ETM_ETMAUTHSTATUS_NONSECINVDBG_SHIFT 0 /**< Shift value for ETM_NONSECINVDBG */ |
| bogdanm | 0:9b334a45a8ff | 647 | #define _ETM_ETMAUTHSTATUS_NONSECINVDBG_MASK 0x3UL /**< Bit mask for ETM_NONSECINVDBG */ |
| bogdanm | 0:9b334a45a8ff | 648 | #define _ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ |
| bogdanm | 0:9b334a45a8ff | 649 | #define ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECINVDBG_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ |
| bogdanm | 0:9b334a45a8ff | 650 | #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_SHIFT 2 /**< Shift value for ETM_NONSECNONINVDBG */ |
| bogdanm | 0:9b334a45a8ff | 651 | #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_MASK 0xCUL /**< Bit mask for ETM_NONSECNONINVDBG */ |
| bogdanm | 0:9b334a45a8ff | 652 | #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ |
| bogdanm | 0:9b334a45a8ff | 653 | #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE 0x00000002UL /**< Mode DISABLE for ETM_ETMAUTHSTATUS */ |
| bogdanm | 0:9b334a45a8ff | 654 | #define _ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE 0x00000003UL /**< Mode ENABLE for ETM_ETMAUTHSTATUS */ |
| bogdanm | 0:9b334a45a8ff | 655 | #define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DEFAULT << 2) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ |
| bogdanm | 0:9b334a45a8ff | 656 | #define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_DISABLE << 2) /**< Shifted mode DISABLE for ETM_ETMAUTHSTATUS */ |
| bogdanm | 0:9b334a45a8ff | 657 | #define ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE (_ETM_ETMAUTHSTATUS_NONSECNONINVDBG_ENABLE << 2) /**< Shifted mode ENABLE for ETM_ETMAUTHSTATUS */ |
| bogdanm | 0:9b334a45a8ff | 658 | #define _ETM_ETMAUTHSTATUS_SECINVDBG_SHIFT 4 /**< Shift value for ETM_SECINVDBG */ |
| bogdanm | 0:9b334a45a8ff | 659 | #define _ETM_ETMAUTHSTATUS_SECINVDBG_MASK 0x30UL /**< Bit mask for ETM_SECINVDBG */ |
| bogdanm | 0:9b334a45a8ff | 660 | #define _ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ |
| bogdanm | 0:9b334a45a8ff | 661 | #define ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECINVDBG_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ |
| bogdanm | 0:9b334a45a8ff | 662 | #define _ETM_ETMAUTHSTATUS_SECNONINVDBG_SHIFT 6 /**< Shift value for ETM_SECNONINVDBG */ |
| bogdanm | 0:9b334a45a8ff | 663 | #define _ETM_ETMAUTHSTATUS_SECNONINVDBG_MASK 0xC0UL /**< Bit mask for ETM_SECNONINVDBG */ |
| bogdanm | 0:9b334a45a8ff | 664 | #define _ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMAUTHSTATUS */ |
| bogdanm | 0:9b334a45a8ff | 665 | #define ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT (_ETM_ETMAUTHSTATUS_SECNONINVDBG_DEFAULT << 6) /**< Shifted mode DEFAULT for ETM_ETMAUTHSTATUS */ |
| bogdanm | 0:9b334a45a8ff | 666 | |
| bogdanm | 0:9b334a45a8ff | 667 | /* Bit fields for ETM ETMDEVTYPE */ |
| bogdanm | 0:9b334a45a8ff | 668 | #define _ETM_ETMDEVTYPE_RESETVALUE 0x00000013UL /**< Default value for ETM_ETMDEVTYPE */ |
| bogdanm | 0:9b334a45a8ff | 669 | #define _ETM_ETMDEVTYPE_MASK 0x000000FFUL /**< Mask for ETM_ETMDEVTYPE */ |
| bogdanm | 0:9b334a45a8ff | 670 | #define _ETM_ETMDEVTYPE_TRACESRC_SHIFT 0 /**< Shift value for ETM_TRACESRC */ |
| bogdanm | 0:9b334a45a8ff | 671 | #define _ETM_ETMDEVTYPE_TRACESRC_MASK 0xFUL /**< Bit mask for ETM_TRACESRC */ |
| bogdanm | 0:9b334a45a8ff | 672 | #define _ETM_ETMDEVTYPE_TRACESRC_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */ |
| bogdanm | 0:9b334a45a8ff | 673 | #define ETM_ETMDEVTYPE_TRACESRC_DEFAULT (_ETM_ETMDEVTYPE_TRACESRC_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */ |
| bogdanm | 0:9b334a45a8ff | 674 | #define _ETM_ETMDEVTYPE_PROCTRACE_SHIFT 4 /**< Shift value for ETM_PROCTRACE */ |
| bogdanm | 0:9b334a45a8ff | 675 | #define _ETM_ETMDEVTYPE_PROCTRACE_MASK 0xF0UL /**< Bit mask for ETM_PROCTRACE */ |
| bogdanm | 0:9b334a45a8ff | 676 | #define _ETM_ETMDEVTYPE_PROCTRACE_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMDEVTYPE */ |
| bogdanm | 0:9b334a45a8ff | 677 | #define ETM_ETMDEVTYPE_PROCTRACE_DEFAULT (_ETM_ETMDEVTYPE_PROCTRACE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMDEVTYPE */ |
| bogdanm | 0:9b334a45a8ff | 678 | |
| bogdanm | 0:9b334a45a8ff | 679 | /* Bit fields for ETM ETMPIDR4 */ |
| bogdanm | 0:9b334a45a8ff | 680 | #define _ETM_ETMPIDR4_RESETVALUE 0x00000004UL /**< Default value for ETM_ETMPIDR4 */ |
| bogdanm | 0:9b334a45a8ff | 681 | #define _ETM_ETMPIDR4_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR4 */ |
| bogdanm | 0:9b334a45a8ff | 682 | #define _ETM_ETMPIDR4_CONTCODE_SHIFT 0 /**< Shift value for ETM_CONTCODE */ |
| bogdanm | 0:9b334a45a8ff | 683 | #define _ETM_ETMPIDR4_CONTCODE_MASK 0xFUL /**< Bit mask for ETM_CONTCODE */ |
| bogdanm | 0:9b334a45a8ff | 684 | #define _ETM_ETMPIDR4_CONTCODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for ETM_ETMPIDR4 */ |
| bogdanm | 0:9b334a45a8ff | 685 | #define ETM_ETMPIDR4_CONTCODE_DEFAULT (_ETM_ETMPIDR4_CONTCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */ |
| bogdanm | 0:9b334a45a8ff | 686 | #define _ETM_ETMPIDR4_COUNT_SHIFT 4 /**< Shift value for ETM_COUNT */ |
| bogdanm | 0:9b334a45a8ff | 687 | #define _ETM_ETMPIDR4_COUNT_MASK 0xF0UL /**< Bit mask for ETM_COUNT */ |
| bogdanm | 0:9b334a45a8ff | 688 | #define _ETM_ETMPIDR4_COUNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR4 */ |
| bogdanm | 0:9b334a45a8ff | 689 | #define ETM_ETMPIDR4_COUNT_DEFAULT (_ETM_ETMPIDR4_COUNT_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR4 */ |
| bogdanm | 0:9b334a45a8ff | 690 | |
| bogdanm | 0:9b334a45a8ff | 691 | /* Bit fields for ETM ETMPIDR5 */ |
| bogdanm | 0:9b334a45a8ff | 692 | #define _ETM_ETMPIDR5_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR5 */ |
| bogdanm | 0:9b334a45a8ff | 693 | #define _ETM_ETMPIDR5_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR5 */ |
| bogdanm | 0:9b334a45a8ff | 694 | |
| bogdanm | 0:9b334a45a8ff | 695 | /* Bit fields for ETM ETMPIDR6 */ |
| bogdanm | 0:9b334a45a8ff | 696 | #define _ETM_ETMPIDR6_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR6 */ |
| bogdanm | 0:9b334a45a8ff | 697 | #define _ETM_ETMPIDR6_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR6 */ |
| bogdanm | 0:9b334a45a8ff | 698 | |
| bogdanm | 0:9b334a45a8ff | 699 | /* Bit fields for ETM ETMPIDR7 */ |
| bogdanm | 0:9b334a45a8ff | 700 | #define _ETM_ETMPIDR7_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR7 */ |
| bogdanm | 0:9b334a45a8ff | 701 | #define _ETM_ETMPIDR7_MASK 0x00000000UL /**< Mask for ETM_ETMPIDR7 */ |
| bogdanm | 0:9b334a45a8ff | 702 | |
| bogdanm | 0:9b334a45a8ff | 703 | /* Bit fields for ETM ETMPIDR0 */ |
| bogdanm | 0:9b334a45a8ff | 704 | #define _ETM_ETMPIDR0_RESETVALUE 0x00000024UL /**< Default value for ETM_ETMPIDR0 */ |
| bogdanm | 0:9b334a45a8ff | 705 | #define _ETM_ETMPIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR0 */ |
| bogdanm | 0:9b334a45a8ff | 706 | #define _ETM_ETMPIDR0_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */ |
| bogdanm | 0:9b334a45a8ff | 707 | #define _ETM_ETMPIDR0_PARTNUM_MASK 0xFFUL /**< Bit mask for ETM_PARTNUM */ |
| bogdanm | 0:9b334a45a8ff | 708 | #define _ETM_ETMPIDR0_PARTNUM_DEFAULT 0x00000024UL /**< Mode DEFAULT for ETM_ETMPIDR0 */ |
| bogdanm | 0:9b334a45a8ff | 709 | #define ETM_ETMPIDR0_PARTNUM_DEFAULT (_ETM_ETMPIDR0_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR0 */ |
| bogdanm | 0:9b334a45a8ff | 710 | |
| bogdanm | 0:9b334a45a8ff | 711 | /* Bit fields for ETM ETMPIDR1 */ |
| bogdanm | 0:9b334a45a8ff | 712 | #define _ETM_ETMPIDR1_RESETVALUE 0x000000B9UL /**< Default value for ETM_ETMPIDR1 */ |
| bogdanm | 0:9b334a45a8ff | 713 | #define _ETM_ETMPIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR1 */ |
| bogdanm | 0:9b334a45a8ff | 714 | #define _ETM_ETMPIDR1_PARTNUM_SHIFT 0 /**< Shift value for ETM_PARTNUM */ |
| bogdanm | 0:9b334a45a8ff | 715 | #define _ETM_ETMPIDR1_PARTNUM_MASK 0xFUL /**< Bit mask for ETM_PARTNUM */ |
| bogdanm | 0:9b334a45a8ff | 716 | #define _ETM_ETMPIDR1_PARTNUM_DEFAULT 0x00000009UL /**< Mode DEFAULT for ETM_ETMPIDR1 */ |
| bogdanm | 0:9b334a45a8ff | 717 | #define ETM_ETMPIDR1_PARTNUM_DEFAULT (_ETM_ETMPIDR1_PARTNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */ |
| bogdanm | 0:9b334a45a8ff | 718 | #define _ETM_ETMPIDR1_IDCODE_SHIFT 4 /**< Shift value for ETM_IDCODE */ |
| bogdanm | 0:9b334a45a8ff | 719 | #define _ETM_ETMPIDR1_IDCODE_MASK 0xF0UL /**< Bit mask for ETM_IDCODE */ |
| bogdanm | 0:9b334a45a8ff | 720 | #define _ETM_ETMPIDR1_IDCODE_DEFAULT 0x0000000BUL /**< Mode DEFAULT for ETM_ETMPIDR1 */ |
| bogdanm | 0:9b334a45a8ff | 721 | #define ETM_ETMPIDR1_IDCODE_DEFAULT (_ETM_ETMPIDR1_IDCODE_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR1 */ |
| bogdanm | 0:9b334a45a8ff | 722 | |
| bogdanm | 0:9b334a45a8ff | 723 | /* Bit fields for ETM ETMPIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 724 | #define _ETM_ETMPIDR2_RESETVALUE 0x0000003BUL /**< Default value for ETM_ETMPIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 725 | #define _ETM_ETMPIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 726 | #define _ETM_ETMPIDR2_IDCODE_SHIFT 0 /**< Shift value for ETM_IDCODE */ |
| bogdanm | 0:9b334a45a8ff | 727 | #define _ETM_ETMPIDR2_IDCODE_MASK 0x7UL /**< Bit mask for ETM_IDCODE */ |
| bogdanm | 0:9b334a45a8ff | 728 | #define _ETM_ETMPIDR2_IDCODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMPIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 729 | #define ETM_ETMPIDR2_IDCODE_DEFAULT (_ETM_ETMPIDR2_IDCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 730 | #define ETM_ETMPIDR2_ALWAYS1 (0x1UL << 3) /**< Always 1 */ |
| bogdanm | 0:9b334a45a8ff | 731 | #define _ETM_ETMPIDR2_ALWAYS1_SHIFT 3 /**< Shift value for ETM_ALWAYS1 */ |
| bogdanm | 0:9b334a45a8ff | 732 | #define _ETM_ETMPIDR2_ALWAYS1_MASK 0x8UL /**< Bit mask for ETM_ALWAYS1 */ |
| bogdanm | 0:9b334a45a8ff | 733 | #define _ETM_ETMPIDR2_ALWAYS1_DEFAULT 0x00000001UL /**< Mode DEFAULT for ETM_ETMPIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 734 | #define ETM_ETMPIDR2_ALWAYS1_DEFAULT (_ETM_ETMPIDR2_ALWAYS1_DEFAULT << 3) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 735 | #define _ETM_ETMPIDR2_REV_SHIFT 4 /**< Shift value for ETM_REV */ |
| bogdanm | 0:9b334a45a8ff | 736 | #define _ETM_ETMPIDR2_REV_MASK 0xF0UL /**< Bit mask for ETM_REV */ |
| bogdanm | 0:9b334a45a8ff | 737 | #define _ETM_ETMPIDR2_REV_DEFAULT 0x00000003UL /**< Mode DEFAULT for ETM_ETMPIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 738 | #define ETM_ETMPIDR2_REV_DEFAULT (_ETM_ETMPIDR2_REV_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 739 | |
| bogdanm | 0:9b334a45a8ff | 740 | /* Bit fields for ETM ETMPIDR3 */ |
| bogdanm | 0:9b334a45a8ff | 741 | #define _ETM_ETMPIDR3_RESETVALUE 0x00000000UL /**< Default value for ETM_ETMPIDR3 */ |
| bogdanm | 0:9b334a45a8ff | 742 | #define _ETM_ETMPIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMPIDR3 */ |
| bogdanm | 0:9b334a45a8ff | 743 | #define _ETM_ETMPIDR3_CUSTMOD_SHIFT 0 /**< Shift value for ETM_CUSTMOD */ |
| bogdanm | 0:9b334a45a8ff | 744 | #define _ETM_ETMPIDR3_CUSTMOD_MASK 0xFUL /**< Bit mask for ETM_CUSTMOD */ |
| bogdanm | 0:9b334a45a8ff | 745 | #define _ETM_ETMPIDR3_CUSTMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */ |
| bogdanm | 0:9b334a45a8ff | 746 | #define ETM_ETMPIDR3_CUSTMOD_DEFAULT (_ETM_ETMPIDR3_CUSTMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */ |
| bogdanm | 0:9b334a45a8ff | 747 | #define _ETM_ETMPIDR3_REVAND_SHIFT 4 /**< Shift value for ETM_REVAND */ |
| bogdanm | 0:9b334a45a8ff | 748 | #define _ETM_ETMPIDR3_REVAND_MASK 0xF0UL /**< Bit mask for ETM_REVAND */ |
| bogdanm | 0:9b334a45a8ff | 749 | #define _ETM_ETMPIDR3_REVAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for ETM_ETMPIDR3 */ |
| bogdanm | 0:9b334a45a8ff | 750 | #define ETM_ETMPIDR3_REVAND_DEFAULT (_ETM_ETMPIDR3_REVAND_DEFAULT << 4) /**< Shifted mode DEFAULT for ETM_ETMPIDR3 */ |
| bogdanm | 0:9b334a45a8ff | 751 | |
| bogdanm | 0:9b334a45a8ff | 752 | /* Bit fields for ETM ETMCIDR0 */ |
| bogdanm | 0:9b334a45a8ff | 753 | #define _ETM_ETMCIDR0_RESETVALUE 0x0000000DUL /**< Default value for ETM_ETMCIDR0 */ |
| bogdanm | 0:9b334a45a8ff | 754 | #define _ETM_ETMCIDR0_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR0 */ |
| bogdanm | 0:9b334a45a8ff | 755 | #define _ETM_ETMCIDR0_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ |
| bogdanm | 0:9b334a45a8ff | 756 | #define _ETM_ETMCIDR0_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ |
| bogdanm | 0:9b334a45a8ff | 757 | #define _ETM_ETMCIDR0_PREAMB_DEFAULT 0x0000000DUL /**< Mode DEFAULT for ETM_ETMCIDR0 */ |
| bogdanm | 0:9b334a45a8ff | 758 | #define ETM_ETMCIDR0_PREAMB_DEFAULT (_ETM_ETMCIDR0_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR0 */ |
| bogdanm | 0:9b334a45a8ff | 759 | |
| bogdanm | 0:9b334a45a8ff | 760 | /* Bit fields for ETM ETMCIDR1 */ |
| bogdanm | 0:9b334a45a8ff | 761 | #define _ETM_ETMCIDR1_RESETVALUE 0x00000090UL /**< Default value for ETM_ETMCIDR1 */ |
| bogdanm | 0:9b334a45a8ff | 762 | #define _ETM_ETMCIDR1_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR1 */ |
| bogdanm | 0:9b334a45a8ff | 763 | #define _ETM_ETMCIDR1_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ |
| bogdanm | 0:9b334a45a8ff | 764 | #define _ETM_ETMCIDR1_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ |
| bogdanm | 0:9b334a45a8ff | 765 | #define _ETM_ETMCIDR1_PREAMB_DEFAULT 0x00000090UL /**< Mode DEFAULT for ETM_ETMCIDR1 */ |
| bogdanm | 0:9b334a45a8ff | 766 | #define ETM_ETMCIDR1_PREAMB_DEFAULT (_ETM_ETMCIDR1_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR1 */ |
| bogdanm | 0:9b334a45a8ff | 767 | |
| bogdanm | 0:9b334a45a8ff | 768 | /* Bit fields for ETM ETMCIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 769 | #define _ETM_ETMCIDR2_RESETVALUE 0x00000005UL /**< Default value for ETM_ETMCIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 770 | #define _ETM_ETMCIDR2_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 771 | #define _ETM_ETMCIDR2_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ |
| bogdanm | 0:9b334a45a8ff | 772 | #define _ETM_ETMCIDR2_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ |
| bogdanm | 0:9b334a45a8ff | 773 | #define _ETM_ETMCIDR2_PREAMB_DEFAULT 0x00000005UL /**< Mode DEFAULT for ETM_ETMCIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 774 | #define ETM_ETMCIDR2_PREAMB_DEFAULT (_ETM_ETMCIDR2_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR2 */ |
| bogdanm | 0:9b334a45a8ff | 775 | |
| bogdanm | 0:9b334a45a8ff | 776 | /* Bit fields for ETM ETMCIDR3 */ |
| bogdanm | 0:9b334a45a8ff | 777 | #define _ETM_ETMCIDR3_RESETVALUE 0x000000B1UL /**< Default value for ETM_ETMCIDR3 */ |
| bogdanm | 0:9b334a45a8ff | 778 | #define _ETM_ETMCIDR3_MASK 0x000000FFUL /**< Mask for ETM_ETMCIDR3 */ |
| bogdanm | 0:9b334a45a8ff | 779 | #define _ETM_ETMCIDR3_PREAMB_SHIFT 0 /**< Shift value for ETM_PREAMB */ |
| bogdanm | 0:9b334a45a8ff | 780 | #define _ETM_ETMCIDR3_PREAMB_MASK 0xFFUL /**< Bit mask for ETM_PREAMB */ |
| bogdanm | 0:9b334a45a8ff | 781 | #define _ETM_ETMCIDR3_PREAMB_DEFAULT 0x000000B1UL /**< Mode DEFAULT for ETM_ETMCIDR3 */ |
| bogdanm | 0:9b334a45a8ff | 782 | #define ETM_ETMCIDR3_PREAMB_DEFAULT (_ETM_ETMCIDR3_PREAMB_DEFAULT << 0) /**< Shifted mode DEFAULT for ETM_ETMCIDR3 */ |
| bogdanm | 0:9b334a45a8ff | 783 | |
| bogdanm | 0:9b334a45a8ff | 784 | /** @} End of group EFM32LG_ETM */ |
| mbed_official | 50:a417edff4437 | 785 | /** @} End of group Parts */ |
| bogdanm | 0:9b334a45a8ff | 786 |