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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff
Child:: 83:a036322b8637

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f7xx_hal_spi.c
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.0.1
bogdanm	0:9b334a45a8ff	6	* @date 25-June-2015
bogdanm	0:9b334a45a8ff	7	* @brief SPI HAL module driver.
bogdanm	0:9b334a45a8ff	8	* This file provides firmware functions to manage the following
bogdanm	0:9b334a45a8ff	9	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
bogdanm	0:9b334a45a8ff	10	* + Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	11	* + IO operation functions
bogdanm	0:9b334a45a8ff	12	* + Peripheral Control functions
bogdanm	0:9b334a45a8ff	13	* + Peripheral State functions
bogdanm	0:9b334a45a8ff	14	@verbatim
bogdanm	0:9b334a45a8ff	15	==============================================================================
bogdanm	0:9b334a45a8ff	16	##### How to use this driver #####
bogdanm	0:9b334a45a8ff	17	==============================================================================
bogdanm	0:9b334a45a8ff	18	[..]
bogdanm	0:9b334a45a8ff	19	The SPI HAL driver can be used as follows:
bogdanm	0:9b334a45a8ff	20
bogdanm	0:9b334a45a8ff	21	(#) Declare a SPI_HandleTypeDef handle structure, for example:
bogdanm	0:9b334a45a8ff	22	SPI_HandleTypeDef hspi;
bogdanm	0:9b334a45a8ff	23
bogdanm	0:9b334a45a8ff	24	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
bogdanm	0:9b334a45a8ff	25	(##) Enable the SPIx interface clock
bogdanm	0:9b334a45a8ff	26	(##) SPI pins configuration
bogdanm	0:9b334a45a8ff	27	(+++) Enable the clock for the SPI GPIOs
bogdanm	0:9b334a45a8ff	28	(+++) Configure these SPI pins as alternate function push-pull
bogdanm	0:9b334a45a8ff	29	(##) NVIC configuration if you need to use interrupt process
bogdanm	0:9b334a45a8ff	30	(+++) Configure the SPIx interrupt priority
bogdanm	0:9b334a45a8ff	31	(+++) Enable the NVIC SPI IRQ handle
bogdanm	0:9b334a45a8ff	32	(##) DMA Configuration if you need to use DMA process
bogdanm	0:9b334a45a8ff	33	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
bogdanm	0:9b334a45a8ff	34	(+++) Enable the DMAx clock
bogdanm	0:9b334a45a8ff	35	(+++) Configure the DMA handle parameters
bogdanm	0:9b334a45a8ff	36	(+++) Configure the DMA Tx or Rx channel
bogdanm	0:9b334a45a8ff	37	(+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
bogdanm	0:9b334a45a8ff	38	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
bogdanm	0:9b334a45a8ff	39
bogdanm	0:9b334a45a8ff	40	(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
bogdanm	0:9b334a45a8ff	41	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
bogdanm	0:9b334a45a8ff	42
bogdanm	0:9b334a45a8ff	43	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
bogdanm	0:9b334a45a8ff	44	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
bogdanm	0:9b334a45a8ff	45	by calling the customised HAL_SPI_MspInit() API.
bogdanm	0:9b334a45a8ff	46	[..]
bogdanm	0:9b334a45a8ff	47	Circular mode restriction:
bogdanm	0:9b334a45a8ff	48	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
bogdanm	0:9b334a45a8ff	49	(##) Master 2Lines RxOnly
bogdanm	0:9b334a45a8ff	50	(##) Master 1Line Rx
bogdanm	0:9b334a45a8ff	51	(#) The CRC feature is not managed when the DMA circular mode is enabled
bogdanm	0:9b334a45a8ff	52	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
bogdanm	0:9b334a45a8ff	53	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
bogdanm	0:9b334a45a8ff	54
bogdanm	0:9b334a45a8ff	55	@endverbatim
bogdanm	0:9b334a45a8ff	56	******************************************************************************
bogdanm	0:9b334a45a8ff	57	* @attention
bogdanm	0:9b334a45a8ff	58	*
bogdanm	0:9b334a45a8ff	59	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	60	*
bogdanm	0:9b334a45a8ff	61	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	62	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	63	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	64	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	65	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	66	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	67	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	68	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	69	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	70	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	71	*
bogdanm	0:9b334a45a8ff	72	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	73	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	74	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	75	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	76	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	77	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	78	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	79	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	80	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	81	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	82	*
bogdanm	0:9b334a45a8ff	83	******************************************************************************
bogdanm	0:9b334a45a8ff	84	*/
bogdanm	0:9b334a45a8ff	85
bogdanm	0:9b334a45a8ff	86	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	87	#include "stm32f7xx_hal.h"
bogdanm	0:9b334a45a8ff	88
bogdanm	0:9b334a45a8ff	89	/** @addtogroup STM32F7xx_HAL_Driver
bogdanm	0:9b334a45a8ff	90	* @{
bogdanm	0:9b334a45a8ff	91	*/
bogdanm	0:9b334a45a8ff	92
bogdanm	0:9b334a45a8ff	93	/** @defgroup SPI SPI
bogdanm	0:9b334a45a8ff	94	* @brief SPI HAL module driver
bogdanm	0:9b334a45a8ff	95	* @{
bogdanm	0:9b334a45a8ff	96	*/
bogdanm	0:9b334a45a8ff	97	#ifdef HAL_SPI_MODULE_ENABLED
bogdanm	0:9b334a45a8ff	98
bogdanm	0:9b334a45a8ff	99	/* Private typedef -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	100	/* Private defines -----------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	101	/** @defgroup SPI_Private_Constants SPI Private Constants
bogdanm	0:9b334a45a8ff	102	* @{
bogdanm	0:9b334a45a8ff	103	*/
bogdanm	0:9b334a45a8ff	104	#define SPI_DEFAULT_TIMEOUT 50
bogdanm	0:9b334a45a8ff	105	/**
bogdanm	0:9b334a45a8ff	106	* @}
bogdanm	0:9b334a45a8ff	107	*/
bogdanm	0:9b334a45a8ff	108
bogdanm	0:9b334a45a8ff	109	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	110	/* Private variables ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	111	/* Private function prototypes -----------------------------------------------*/
bogdanm	0:9b334a45a8ff	112	/** @addtogroup SPI_Private_Functions
bogdanm	0:9b334a45a8ff	113	* @{
bogdanm	0:9b334a45a8ff	114	*/
bogdanm	0:9b334a45a8ff	115	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	116	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	117	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	118	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	119	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	120	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	121	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
bogdanm	0:9b334a45a8ff	122	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	123	static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	124	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	125	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	126	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	127	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	128	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	129	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	130	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	131	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	132	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	133	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	134	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	135	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	136	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	137	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	138	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
bogdanm	0:9b334a45a8ff	139	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	140	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
bogdanm	0:9b334a45a8ff	141	/**
bogdanm	0:9b334a45a8ff	142	* @}
bogdanm	0:9b334a45a8ff	143	*/
bogdanm	0:9b334a45a8ff	144
bogdanm	0:9b334a45a8ff	145	/* Exported functions ---------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	146
bogdanm	0:9b334a45a8ff	147	/** @defgroup SPI_Exported_Functions SPI Exported Functions
bogdanm	0:9b334a45a8ff	148	* @{
bogdanm	0:9b334a45a8ff	149	*/
bogdanm	0:9b334a45a8ff	150
bogdanm	0:9b334a45a8ff	151	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm	0:9b334a45a8ff	152	* @brief Initialization and Configuration functions
bogdanm	0:9b334a45a8ff	153	*
bogdanm	0:9b334a45a8ff	154	@verbatim
bogdanm	0:9b334a45a8ff	155	===============================================================================
bogdanm	0:9b334a45a8ff	156	##### Initialization and de-initialization functions #####
bogdanm	0:9b334a45a8ff	157	===============================================================================
bogdanm	0:9b334a45a8ff	158	[..] This subsection provides a set of functions allowing to initialize and
bogdanm	0:9b334a45a8ff	159	de-initialize the SPIx peripheral:
bogdanm	0:9b334a45a8ff	160
bogdanm	0:9b334a45a8ff	161	(+) User must implement HAL_SPI_MspInit() function in which he configures
bogdanm	0:9b334a45a8ff	162	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
bogdanm	0:9b334a45a8ff	163
bogdanm	0:9b334a45a8ff	164	(+) Call the function HAL_SPI_Init() to configure the selected device with
bogdanm	0:9b334a45a8ff	165	the selected configuration:
bogdanm	0:9b334a45a8ff	166	(++) Mode
bogdanm	0:9b334a45a8ff	167	(++) Direction
bogdanm	0:9b334a45a8ff	168	(++) Data Size
bogdanm	0:9b334a45a8ff	169	(++) Clock Polarity and Phase
bogdanm	0:9b334a45a8ff	170	(++) NSS Management
bogdanm	0:9b334a45a8ff	171	(++) BaudRate Prescaler
bogdanm	0:9b334a45a8ff	172	(++) FirstBit
bogdanm	0:9b334a45a8ff	173	(++) TIMode
bogdanm	0:9b334a45a8ff	174	(++) CRC Calculation
bogdanm	0:9b334a45a8ff	175	(++) CRC Polynomial if CRC enabled
bogdanm	0:9b334a45a8ff	176	(++) CRC Length, used only with Data8 and Data16
bogdanm	0:9b334a45a8ff	177	(++) FIFO reception threshold
bogdanm	0:9b334a45a8ff	178
bogdanm	0:9b334a45a8ff	179	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
bogdanm	0:9b334a45a8ff	180	of the selected SPIx peripheral.
bogdanm	0:9b334a45a8ff	181
bogdanm	0:9b334a45a8ff	182	@endverbatim
bogdanm	0:9b334a45a8ff	183	* @{
bogdanm	0:9b334a45a8ff	184	*/
bogdanm	0:9b334a45a8ff	185
bogdanm	0:9b334a45a8ff	186	/**
bogdanm	0:9b334a45a8ff	187	* @brief Initializes the SPI according to the specified parameters
bogdanm	0:9b334a45a8ff	188	* in the SPI_InitTypeDef and create the associated handle.
bogdanm	0:9b334a45a8ff	189	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	190	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	191	* @retval HAL status
bogdanm	0:9b334a45a8ff	192	*/
bogdanm	0:9b334a45a8ff	193	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	194	{
bogdanm	0:9b334a45a8ff	195	uint32_t frxth;
bogdanm	0:9b334a45a8ff	196
bogdanm	0:9b334a45a8ff	197	/* Check the SPI handle allocation */
bogdanm	0:9b334a45a8ff	198	if(hspi == NULL)
bogdanm	0:9b334a45a8ff	199	{
bogdanm	0:9b334a45a8ff	200	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	201	}
bogdanm	0:9b334a45a8ff	202
bogdanm	0:9b334a45a8ff	203	/* Check the parameters */
bogdanm	0:9b334a45a8ff	204	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
bogdanm	0:9b334a45a8ff	205	assert_param(IS_SPI_MODE(hspi->Init.Mode));
bogdanm	0:9b334a45a8ff	206	assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	207	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
bogdanm	0:9b334a45a8ff	208	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
bogdanm	0:9b334a45a8ff	209	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
bogdanm	0:9b334a45a8ff	210	assert_param(IS_SPI_NSS(hspi->Init.NSS));
bogdanm	0:9b334a45a8ff	211	assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
bogdanm	0:9b334a45a8ff	212	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
bogdanm	0:9b334a45a8ff	213	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
bogdanm	0:9b334a45a8ff	214	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
bogdanm	0:9b334a45a8ff	215	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
bogdanm	0:9b334a45a8ff	216	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
bogdanm	0:9b334a45a8ff	217	assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
bogdanm	0:9b334a45a8ff	218
bogdanm	0:9b334a45a8ff	219	if(hspi->State == HAL_SPI_STATE_RESET)
bogdanm	0:9b334a45a8ff	220	{
bogdanm	0:9b334a45a8ff	221	/* Allocate lock resource and initialize it */
bogdanm	0:9b334a45a8ff	222	hspi->Lock = HAL_UNLOCKED;
bogdanm	0:9b334a45a8ff	223
bogdanm	0:9b334a45a8ff	224	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
bogdanm	0:9b334a45a8ff	225	HAL_SPI_MspInit(hspi);
bogdanm	0:9b334a45a8ff	226	}
bogdanm	0:9b334a45a8ff	227
bogdanm	0:9b334a45a8ff	228	hspi->State = HAL_SPI_STATE_BUSY;
bogdanm	0:9b334a45a8ff	229
bogdanm	0:9b334a45a8ff	230	/* Disable the selected SPI peripheral */
bogdanm	0:9b334a45a8ff	231	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	232
bogdanm	0:9b334a45a8ff	233	/* Align by default the rs fifo threshold on the data size */
bogdanm	0:9b334a45a8ff	234	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	235	{
bogdanm	0:9b334a45a8ff	236	frxth = SPI_RXFIFO_THRESHOLD_HF;
bogdanm	0:9b334a45a8ff	237	}
bogdanm	0:9b334a45a8ff	238	else
bogdanm	0:9b334a45a8ff	239	{
bogdanm	0:9b334a45a8ff	240	frxth = SPI_RXFIFO_THRESHOLD_QF;
bogdanm	0:9b334a45a8ff	241	}
bogdanm	0:9b334a45a8ff	242
bogdanm	0:9b334a45a8ff	243	/* CRC calculation is valid only for 16Bit and 8 Bit */
bogdanm	0:9b334a45a8ff	244	if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
bogdanm	0:9b334a45a8ff	245	{
bogdanm	0:9b334a45a8ff	246	/* CRC must be disabled */
bogdanm	0:9b334a45a8ff	247	hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
bogdanm	0:9b334a45a8ff	248	}
bogdanm	0:9b334a45a8ff	249
bogdanm	0:9b334a45a8ff	250	/* Align the CRC Length on the data size */
bogdanm	0:9b334a45a8ff	251	if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
bogdanm	0:9b334a45a8ff	252	{
bogdanm	0:9b334a45a8ff	253	/* CRC Length aligned on the data size : value set by default */
bogdanm	0:9b334a45a8ff	254	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	255	{
bogdanm	0:9b334a45a8ff	256	hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
bogdanm	0:9b334a45a8ff	257	}
bogdanm	0:9b334a45a8ff	258	else
bogdanm	0:9b334a45a8ff	259	{
bogdanm	0:9b334a45a8ff	260	hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
bogdanm	0:9b334a45a8ff	261	}
bogdanm	0:9b334a45a8ff	262	}
bogdanm	0:9b334a45a8ff	263
bogdanm	0:9b334a45a8ff	264	/---------------------------- SPIx CR1 & CR2 Configuration ------------------------/
bogdanm	0:9b334a45a8ff	265	/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
bogdanm	0:9b334a45a8ff	266	Communication speed, First bit, CRC calculation state, CRC Length */
bogdanm	0:9b334a45a8ff	267	hspi->Instance->CR1 = (hspi->Init.Mode \| hspi->Init.Direction \|
bogdanm	0:9b334a45a8ff	268	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
bogdanm	0:9b334a45a8ff	269	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation);
bogdanm	0:9b334a45a8ff	270
bogdanm	0:9b334a45a8ff	271	if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
bogdanm	0:9b334a45a8ff	272	{
bogdanm	0:9b334a45a8ff	273	hspi->Instance->CR1\|= SPI_CR1_CRCL;
bogdanm	0:9b334a45a8ff	274	}
bogdanm	0:9b334a45a8ff	275
bogdanm	0:9b334a45a8ff	276	/* Configure : NSS management */
bogdanm	0:9b334a45a8ff	277	/* Configure : Rx Fifo Threshold */
bogdanm	0:9b334a45a8ff	278	hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) \| hspi->Init.TIMode \| hspi->Init.NSSPMode \|
bogdanm	0:9b334a45a8ff	279	hspi->Init.DataSize ) \| frxth;
bogdanm	0:9b334a45a8ff	280
bogdanm	0:9b334a45a8ff	281	/---------------------------- SPIx CRCPOLY Configuration --------------------/
bogdanm	0:9b334a45a8ff	282	/* Configure : CRC Polynomial */
bogdanm	0:9b334a45a8ff	283	hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
bogdanm	0:9b334a45a8ff	284
bogdanm	0:9b334a45a8ff	285	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	286	hspi->State= HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	287
bogdanm	0:9b334a45a8ff	288	return HAL_OK;
bogdanm	0:9b334a45a8ff	289	}
bogdanm	0:9b334a45a8ff	290
bogdanm	0:9b334a45a8ff	291	/**
bogdanm	0:9b334a45a8ff	292	* @brief DeInitializes the SPI peripheral
bogdanm	0:9b334a45a8ff	293	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	294	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	295	* @retval HAL status
bogdanm	0:9b334a45a8ff	296	*/
bogdanm	0:9b334a45a8ff	297	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	298	{
bogdanm	0:9b334a45a8ff	299	/* Check the SPI handle allocation */
bogdanm	0:9b334a45a8ff	300	if(hspi == NULL)
bogdanm	0:9b334a45a8ff	301	{
bogdanm	0:9b334a45a8ff	302	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	303	}
bogdanm	0:9b334a45a8ff	304
bogdanm	0:9b334a45a8ff	305	/* Check the parameters */
bogdanm	0:9b334a45a8ff	306	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
bogdanm	0:9b334a45a8ff	307
bogdanm	0:9b334a45a8ff	308	hspi->State = HAL_SPI_STATE_BUSY;
bogdanm	0:9b334a45a8ff	309
bogdanm	0:9b334a45a8ff	310	/* check flag before the SPI disable */
bogdanm	0:9b334a45a8ff	311	SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
bogdanm	0:9b334a45a8ff	312	SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT);
bogdanm	0:9b334a45a8ff	313	SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
bogdanm	0:9b334a45a8ff	314
bogdanm	0:9b334a45a8ff	315	/* Disable the SPI Peripheral Clock */
bogdanm	0:9b334a45a8ff	316	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	317
bogdanm	0:9b334a45a8ff	318	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
bogdanm	0:9b334a45a8ff	319	HAL_SPI_MspDeInit(hspi);
bogdanm	0:9b334a45a8ff	320
bogdanm	0:9b334a45a8ff	321	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	322	hspi->State = HAL_SPI_STATE_RESET;
bogdanm	0:9b334a45a8ff	323
bogdanm	0:9b334a45a8ff	324	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	325
bogdanm	0:9b334a45a8ff	326	return HAL_OK;
bogdanm	0:9b334a45a8ff	327	}
bogdanm	0:9b334a45a8ff	328
bogdanm	0:9b334a45a8ff	329	/**
bogdanm	0:9b334a45a8ff	330	* @brief SPI MSP Init
bogdanm	0:9b334a45a8ff	331	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	332	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	333	* @retval None
bogdanm	0:9b334a45a8ff	334	*/
bogdanm	0:9b334a45a8ff	335	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	336	{
bogdanm	0:9b334a45a8ff	337	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	338	the HAL_SPI_MspInit should be implemented in the user file
bogdanm	0:9b334a45a8ff	339	*/
bogdanm	0:9b334a45a8ff	340	}
bogdanm	0:9b334a45a8ff	341
bogdanm	0:9b334a45a8ff	342	/**
bogdanm	0:9b334a45a8ff	343	* @brief SPI MSP DeInit
bogdanm	0:9b334a45a8ff	344	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	345	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	346	* @retval None
bogdanm	0:9b334a45a8ff	347	*/
bogdanm	0:9b334a45a8ff	348	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	349	{
bogdanm	0:9b334a45a8ff	350	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	351	the HAL_SPI_MspDeInit should be implemented in the user file
bogdanm	0:9b334a45a8ff	352	*/
bogdanm	0:9b334a45a8ff	353	}
bogdanm	0:9b334a45a8ff	354
bogdanm	0:9b334a45a8ff	355	/**
bogdanm	0:9b334a45a8ff	356	* @}
bogdanm	0:9b334a45a8ff	357	*/
bogdanm	0:9b334a45a8ff	358
bogdanm	0:9b334a45a8ff	359	/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
bogdanm	0:9b334a45a8ff	360	* @brief Data transfers functions
bogdanm	0:9b334a45a8ff	361	*
bogdanm	0:9b334a45a8ff	362	@verbatim
bogdanm	0:9b334a45a8ff	363	==============================================================================
bogdanm	0:9b334a45a8ff	364	##### IO operation functions #####
bogdanm	0:9b334a45a8ff	365	===============================================================================
bogdanm	0:9b334a45a8ff	366	This subsection provides a set of functions allowing to manage the SPI
bogdanm	0:9b334a45a8ff	367	data transfers.
bogdanm	0:9b334a45a8ff	368
bogdanm	0:9b334a45a8ff	369	[..] The SPI supports master and slave mode :
bogdanm	0:9b334a45a8ff	370
bogdanm	0:9b334a45a8ff	371	(#) There are two modes of transfer:
bogdanm	0:9b334a45a8ff	372	(++) Blocking mode: The communication is performed in polling mode.
bogdanm	0:9b334a45a8ff	373	The HAL status of all data processing is returned by the same function
bogdanm	0:9b334a45a8ff	374	after finishing transfer.
bogdanm	0:9b334a45a8ff	375	(++) No-Blocking mode: The communication is performed using Interrupts
bogdanm	0:9b334a45a8ff	376	or DMA, These APIs return the HAL status.
bogdanm	0:9b334a45a8ff	377	The end of the data processing will be indicated through the
bogdanm	0:9b334a45a8ff	378	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
bogdanm	0:9b334a45a8ff	379	using DMA mode.
bogdanm	0:9b334a45a8ff	380	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
bogdanm	0:9b334a45a8ff	381	will be executed respectively at the end of the transmit or Receive process
bogdanm	0:9b334a45a8ff	382	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
bogdanm	0:9b334a45a8ff	383
bogdanm	0:9b334a45a8ff	384	(#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
bogdanm	0:9b334a45a8ff	385	exist for 1Line (simplex) and 2Lines (full duplex) modes.
bogdanm	0:9b334a45a8ff	386
bogdanm	0:9b334a45a8ff	387	@endverbatim
bogdanm	0:9b334a45a8ff	388	* @{
bogdanm	0:9b334a45a8ff	389	*/
bogdanm	0:9b334a45a8ff	390
bogdanm	0:9b334a45a8ff	391	/**
bogdanm	0:9b334a45a8ff	392	* @brief Transmit an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	393	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	394	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	395	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	396	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	397	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	398	* @retval HAL status
bogdanm	0:9b334a45a8ff	399	*/
bogdanm	0:9b334a45a8ff	400	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	401	{
bogdanm	0:9b334a45a8ff	402	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	403
bogdanm	0:9b334a45a8ff	404	/* Process Locked */
bogdanm	0:9b334a45a8ff	405	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	406
bogdanm	0:9b334a45a8ff	407	if(hspi->State != HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	408	{
bogdanm	0:9b334a45a8ff	409	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	410	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	411	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	412	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	413	}
bogdanm	0:9b334a45a8ff	414
bogdanm	0:9b334a45a8ff	415	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	416	{
bogdanm	0:9b334a45a8ff	417	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	418	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	419	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	420	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	421	}
bogdanm	0:9b334a45a8ff	422
bogdanm	0:9b334a45a8ff	423	/* Set the transaction information */
bogdanm	0:9b334a45a8ff	424	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	425	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	426	hspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	427	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	428	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	429	hspi->pRxBuffPtr = (uint8_t *)NULL;
bogdanm	0:9b334a45a8ff	430	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	431	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	432
bogdanm	0:9b334a45a8ff	433	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	434	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	435	{
bogdanm	0:9b334a45a8ff	436	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	437	}
bogdanm	0:9b334a45a8ff	438
bogdanm	0:9b334a45a8ff	439	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	440	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	441	{
bogdanm	0:9b334a45a8ff	442	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	443	}
bogdanm	0:9b334a45a8ff	444
bogdanm	0:9b334a45a8ff	445	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	446	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	447	{
bogdanm	0:9b334a45a8ff	448	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	449	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	450	}
bogdanm	0:9b334a45a8ff	451
bogdanm	0:9b334a45a8ff	452	/* Transmit data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	453	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	454	{
bogdanm	0:9b334a45a8ff	455	/* Transmit data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	456	while (hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	457	{
bogdanm	0:9b334a45a8ff	458	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	459	if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	460	{
bogdanm	0:9b334a45a8ff	461	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	462	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	463	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	464	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	465	}
bogdanm	0:9b334a45a8ff	466	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	467	hspi->pTxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	468	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	469	}
bogdanm	0:9b334a45a8ff	470	}
bogdanm	0:9b334a45a8ff	471	/* Transmit data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	472	else
bogdanm	0:9b334a45a8ff	473	{
bogdanm	0:9b334a45a8ff	474	while (hspi->TxXferCount > 0)
bogdanm	0:9b334a45a8ff	475	{
bogdanm	0:9b334a45a8ff	476	if(hspi->TxXferCount != 0x1)
bogdanm	0:9b334a45a8ff	477	{
bogdanm	0:9b334a45a8ff	478	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	479	if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	480	{
bogdanm	0:9b334a45a8ff	481	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	482	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	483	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	484	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	485	}
bogdanm	0:9b334a45a8ff	486	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	487	hspi->pTxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	488	hspi->TxXferCount -= 2;
bogdanm	0:9b334a45a8ff	489	}
bogdanm	0:9b334a45a8ff	490	else
bogdanm	0:9b334a45a8ff	491	{
bogdanm	0:9b334a45a8ff	492	/* Wait until TXE flag is set to send data */
bogdanm	0:9b334a45a8ff	493	if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	494	{
bogdanm	0:9b334a45a8ff	495	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	496	}
bogdanm	0:9b334a45a8ff	497	((__IO uint8_t)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	498	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	499	}
bogdanm	0:9b334a45a8ff	500	}
bogdanm	0:9b334a45a8ff	501	}
bogdanm	0:9b334a45a8ff	502
bogdanm	0:9b334a45a8ff	503	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	504	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	505	{
bogdanm	0:9b334a45a8ff	506	hspi->Instance->CR1\|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	507	}
bogdanm	0:9b334a45a8ff	508
bogdanm	0:9b334a45a8ff	509	/* Check the end of the transaction */
bogdanm	0:9b334a45a8ff	510	if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	511	{
bogdanm	0:9b334a45a8ff	512	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	513	}
bogdanm	0:9b334a45a8ff	514
bogdanm	0:9b334a45a8ff	515	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
bogdanm	0:9b334a45a8ff	516	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	517	{
bogdanm	0:9b334a45a8ff	518	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	519	}
bogdanm	0:9b334a45a8ff	520
bogdanm	0:9b334a45a8ff	521	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	522
bogdanm	0:9b334a45a8ff	523	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	524	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	525
bogdanm	0:9b334a45a8ff	526	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	527	{
bogdanm	0:9b334a45a8ff	528	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	529	}
bogdanm	0:9b334a45a8ff	530	else
bogdanm	0:9b334a45a8ff	531	{
bogdanm	0:9b334a45a8ff	532	return HAL_OK;
bogdanm	0:9b334a45a8ff	533	}
bogdanm	0:9b334a45a8ff	534	}
bogdanm	0:9b334a45a8ff	535
bogdanm	0:9b334a45a8ff	536	/**
bogdanm	0:9b334a45a8ff	537	* @brief Receive an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	538	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	539	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	540	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	541	* @param Size: amount of data to be received
bogdanm	0:9b334a45a8ff	542	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	543	* @retval HAL status
bogdanm	0:9b334a45a8ff	544	*/
bogdanm	0:9b334a45a8ff	545	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	546	{
bogdanm	0:9b334a45a8ff	547	__IO uint16_t tmpreg;
bogdanm	0:9b334a45a8ff	548
bogdanm	0:9b334a45a8ff	549	if(hspi->State != HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	550	{
bogdanm	0:9b334a45a8ff	551	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	552	}
bogdanm	0:9b334a45a8ff	553
bogdanm	0:9b334a45a8ff	554	if((pData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	555	{
bogdanm	0:9b334a45a8ff	556	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	557	}
bogdanm	0:9b334a45a8ff	558
bogdanm	0:9b334a45a8ff	559	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
bogdanm	0:9b334a45a8ff	560	{
bogdanm	0:9b334a45a8ff	561	/* the receive process is not supported in 2Lines direction master mode */
bogdanm	0:9b334a45a8ff	562	/* in this case we call the transmitReceive process */
bogdanm	0:9b334a45a8ff	563	return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
bogdanm	0:9b334a45a8ff	564	}
bogdanm	0:9b334a45a8ff	565
bogdanm	0:9b334a45a8ff	566	/* Process Locked */
bogdanm	0:9b334a45a8ff	567	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	568
bogdanm	0:9b334a45a8ff	569	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	570	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	571	hspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	572	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	573	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	574	hspi->pTxBuffPtr = (uint8_t *)NULL;
bogdanm	0:9b334a45a8ff	575	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	576	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	577
bogdanm	0:9b334a45a8ff	578	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	579	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	580	{
bogdanm	0:9b334a45a8ff	581	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	582	/* this is done to handle the CRCNEXT before the latest data */
bogdanm	0:9b334a45a8ff	583	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	584	}
bogdanm	0:9b334a45a8ff	585
bogdanm	0:9b334a45a8ff	586	/* Set the Rx Fido threshold */
bogdanm	0:9b334a45a8ff	587	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	588	{
bogdanm	0:9b334a45a8ff	589	/* set fiforxthreshold according the reception data length: 16bit */
bogdanm	0:9b334a45a8ff	590	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	591	}
bogdanm	0:9b334a45a8ff	592	else
bogdanm	0:9b334a45a8ff	593	{
bogdanm	0:9b334a45a8ff	594	/* set fiforxthreshold according the reception data length: 8bit */
bogdanm	0:9b334a45a8ff	595	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	596	}
bogdanm	0:9b334a45a8ff	597
bogdanm	0:9b334a45a8ff	598	/* Configure communication direction 1Line and enabled SPI if needed */
bogdanm	0:9b334a45a8ff	599	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	600	{
bogdanm	0:9b334a45a8ff	601	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	602	}
bogdanm	0:9b334a45a8ff	603
bogdanm	0:9b334a45a8ff	604	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	605	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	606	{
bogdanm	0:9b334a45a8ff	607	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	608	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	609	}
bogdanm	0:9b334a45a8ff	610
bogdanm	0:9b334a45a8ff	611	/* Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	612	if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	613	{
bogdanm	0:9b334a45a8ff	614	while(hspi->RxXferCount > 1)
bogdanm	0:9b334a45a8ff	615	{
bogdanm	0:9b334a45a8ff	616	/* Wait until the RXNE flag */
bogdanm	0:9b334a45a8ff	617	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	618	{
bogdanm	0:9b334a45a8ff	619	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	620	}
bogdanm	0:9b334a45a8ff	621	(hspi->pRxBuffPtr++)= (__IO uint8_t *)&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	622	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	623	}
bogdanm	0:9b334a45a8ff	624	}
bogdanm	0:9b334a45a8ff	625	else /* Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	626	{
bogdanm	0:9b334a45a8ff	627	while(hspi->RxXferCount > 1 )
bogdanm	0:9b334a45a8ff	628	{
bogdanm	0:9b334a45a8ff	629	/* Wait until RXNE flag is reset to read data */
bogdanm	0:9b334a45a8ff	630	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	631	{
bogdanm	0:9b334a45a8ff	632	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	633	}
bogdanm	0:9b334a45a8ff	634	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	635	hspi->pRxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	636	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	637	}
bogdanm	0:9b334a45a8ff	638	}
bogdanm	0:9b334a45a8ff	639
bogdanm	0:9b334a45a8ff	640	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	641	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	642	{
bogdanm	0:9b334a45a8ff	643	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	644	}
bogdanm	0:9b334a45a8ff	645
bogdanm	0:9b334a45a8ff	646	/* Wait until RXNE flag is set */
bogdanm	0:9b334a45a8ff	647	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	648	{
bogdanm	0:9b334a45a8ff	649	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	650	}
bogdanm	0:9b334a45a8ff	651
bogdanm	0:9b334a45a8ff	652	/* Receive last data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	653	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	654	{
bogdanm	0:9b334a45a8ff	655	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	656	hspi->pRxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	657	}
bogdanm	0:9b334a45a8ff	658	/* Receive last data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	659	else
bogdanm	0:9b334a45a8ff	660	{
bogdanm	0:9b334a45a8ff	661	(hspi->pRxBuffPtr++) = (__IO uint8_t *)&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	662	}
bogdanm	0:9b334a45a8ff	663	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	664
bogdanm	0:9b334a45a8ff	665	/* Read CRC from DR to close CRC calculation process */
bogdanm	0:9b334a45a8ff	666	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	667	{
bogdanm	0:9b334a45a8ff	668	/* Wait until TXE flag */
bogdanm	0:9b334a45a8ff	669	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	670	{
bogdanm	0:9b334a45a8ff	671	/* Error on the CRC reception */
bogdanm	0:9b334a45a8ff	672	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	673	}
bogdanm	0:9b334a45a8ff	674	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	675	{
bogdanm	0:9b334a45a8ff	676	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	677	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	678	}
bogdanm	0:9b334a45a8ff	679	else
bogdanm	0:9b334a45a8ff	680	{
bogdanm	0:9b334a45a8ff	681	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	682	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	683
bogdanm	0:9b334a45a8ff	684	if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
bogdanm	0:9b334a45a8ff	685	{
bogdanm	0:9b334a45a8ff	686	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	687	{
bogdanm	0:9b334a45a8ff	688	/* Error on the CRC reception */
bogdanm	0:9b334a45a8ff	689	hspi->ErrorCode\|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	690	}
bogdanm	0:9b334a45a8ff	691	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	692	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	693	}
bogdanm	0:9b334a45a8ff	694	}
bogdanm	0:9b334a45a8ff	695	}
bogdanm	0:9b334a45a8ff	696
bogdanm	0:9b334a45a8ff	697	/* Check the end of the transaction */
bogdanm	0:9b334a45a8ff	698	if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	699	{
bogdanm	0:9b334a45a8ff	700	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	701	}
bogdanm	0:9b334a45a8ff	702
bogdanm	0:9b334a45a8ff	703	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	704
bogdanm	0:9b334a45a8ff	705	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	706	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	707	{
bogdanm	0:9b334a45a8ff	708	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	709	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	710
bogdanm	0:9b334a45a8ff	711	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	712	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	713	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	714	}
bogdanm	0:9b334a45a8ff	715
bogdanm	0:9b334a45a8ff	716	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	717	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	718
bogdanm	0:9b334a45a8ff	719	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	720	{
bogdanm	0:9b334a45a8ff	721	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	722	}
bogdanm	0:9b334a45a8ff	723	else
bogdanm	0:9b334a45a8ff	724	{
bogdanm	0:9b334a45a8ff	725	return HAL_OK;
bogdanm	0:9b334a45a8ff	726	}
bogdanm	0:9b334a45a8ff	727	}
bogdanm	0:9b334a45a8ff	728
bogdanm	0:9b334a45a8ff	729	/**
bogdanm	0:9b334a45a8ff	730	* @brief Transmit and Receive an amount of data in blocking mode
bogdanm	0:9b334a45a8ff	731	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	732	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	733	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	734	* @param pRxData: pointer to reception data buffer
bogdanm	0:9b334a45a8ff	735	* @param Size: amount of data to be sent and received
bogdanm	0:9b334a45a8ff	736	* @param Timeout: Timeout duration
bogdanm	0:9b334a45a8ff	737	* @retval HAL status
bogdanm	0:9b334a45a8ff	738	*/
bogdanm	0:9b334a45a8ff	739	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	740	{
bogdanm	0:9b334a45a8ff	741	__IO uint16_t tmpreg = 0;
bogdanm	0:9b334a45a8ff	742	uint32_t tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	743
bogdanm	0:9b334a45a8ff	744	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	745
bogdanm	0:9b334a45a8ff	746	if(hspi->State != HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	747	{
bogdanm	0:9b334a45a8ff	748	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	749	}
bogdanm	0:9b334a45a8ff	750
bogdanm	0:9b334a45a8ff	751	if((pTxData == NULL) \|\| (pRxData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	752	{
bogdanm	0:9b334a45a8ff	753	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	754	}
bogdanm	0:9b334a45a8ff	755
bogdanm	0:9b334a45a8ff	756
bogdanm	0:9b334a45a8ff	757	/* Process Locked */
bogdanm	0:9b334a45a8ff	758	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	759
bogdanm	0:9b334a45a8ff	760	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	761	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	762	hspi->pRxBuffPtr = pRxData;
bogdanm	0:9b334a45a8ff	763	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	764	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	765	hspi->pTxBuffPtr = pTxData;
bogdanm	0:9b334a45a8ff	766	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	767	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	768
bogdanm	0:9b334a45a8ff	769	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	770	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	771	{
bogdanm	0:9b334a45a8ff	772	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	773	}
bogdanm	0:9b334a45a8ff	774
bogdanm	0:9b334a45a8ff	775	/* Set the Rx Fido threshold */
bogdanm	0:9b334a45a8ff	776	if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (hspi->RxXferCount > 1))
bogdanm	0:9b334a45a8ff	777	{
bogdanm	0:9b334a45a8ff	778	/* set fiforxthreshold according the reception data length: 16bit */
bogdanm	0:9b334a45a8ff	779	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	780	}
bogdanm	0:9b334a45a8ff	781	else
bogdanm	0:9b334a45a8ff	782	{
bogdanm	0:9b334a45a8ff	783	/* set fiforxthreshold according the reception data length: 8bit */
bogdanm	0:9b334a45a8ff	784	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	785	}
bogdanm	0:9b334a45a8ff	786
bogdanm	0:9b334a45a8ff	787	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	788	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	789	{
bogdanm	0:9b334a45a8ff	790	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	791	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	792	}
bogdanm	0:9b334a45a8ff	793
bogdanm	0:9b334a45a8ff	794	/* Transmit and Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	795	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	796	{
bogdanm	0:9b334a45a8ff	797	while ((hspi->TxXferCount > 0 ) \|\| (hspi->RxXferCount > 0))
bogdanm	0:9b334a45a8ff	798	{
bogdanm	0:9b334a45a8ff	799	/* Check TXE flag */
bogdanm	0:9b334a45a8ff	800	if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
bogdanm	0:9b334a45a8ff	801	{
bogdanm	0:9b334a45a8ff	802	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	803	hspi->pTxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	804	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	805
bogdanm	0:9b334a45a8ff	806	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	807	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	808	{
bogdanm	0:9b334a45a8ff	809	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	810	}
bogdanm	0:9b334a45a8ff	811	}
bogdanm	0:9b334a45a8ff	812
bogdanm	0:9b334a45a8ff	813	/* Check RXNE flag */
bogdanm	0:9b334a45a8ff	814	if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
bogdanm	0:9b334a45a8ff	815	{
bogdanm	0:9b334a45a8ff	816	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	817	hspi->pRxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	818	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	819	}
bogdanm	0:9b334a45a8ff	820	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	821	{
bogdanm	0:9b334a45a8ff	822	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
bogdanm	0:9b334a45a8ff	823	{
bogdanm	0:9b334a45a8ff	824	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	825	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	826	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	827	}
bogdanm	0:9b334a45a8ff	828	}
bogdanm	0:9b334a45a8ff	829	}
bogdanm	0:9b334a45a8ff	830	}
bogdanm	0:9b334a45a8ff	831	/* Transmit and Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	832	else
bogdanm	0:9b334a45a8ff	833	{
bogdanm	0:9b334a45a8ff	834	while((hspi->TxXferCount > 0) \|\| (hspi->RxXferCount > 0))
bogdanm	0:9b334a45a8ff	835	{
bogdanm	0:9b334a45a8ff	836	/* check TXE flag */
bogdanm	0:9b334a45a8ff	837	if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
bogdanm	0:9b334a45a8ff	838	{
bogdanm	0:9b334a45a8ff	839	if(hspi->TxXferCount > 1)
bogdanm	0:9b334a45a8ff	840	{
bogdanm	0:9b334a45a8ff	841	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	842	hspi->pTxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	843	hspi->TxXferCount -= 2;
bogdanm	0:9b334a45a8ff	844	}
bogdanm	0:9b334a45a8ff	845	else
bogdanm	0:9b334a45a8ff	846	{
bogdanm	0:9b334a45a8ff	847	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	848	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	849	}
bogdanm	0:9b334a45a8ff	850
bogdanm	0:9b334a45a8ff	851	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	852	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	853	{
bogdanm	0:9b334a45a8ff	854	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
bogdanm	0:9b334a45a8ff	855	}
bogdanm	0:9b334a45a8ff	856	}
bogdanm	0:9b334a45a8ff	857
bogdanm	0:9b334a45a8ff	858	/* Wait until RXNE flag is reset */
bogdanm	0:9b334a45a8ff	859	if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
bogdanm	0:9b334a45a8ff	860	{
bogdanm	0:9b334a45a8ff	861	if(hspi->RxXferCount > 1)
bogdanm	0:9b334a45a8ff	862	{
bogdanm	0:9b334a45a8ff	863	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	864	hspi->pRxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	865	hspi->RxXferCount -= 2;
bogdanm	0:9b334a45a8ff	866	if(hspi->RxXferCount <= 1)
bogdanm	0:9b334a45a8ff	867	{
bogdanm	0:9b334a45a8ff	868	/* set fiforxthreshold before to switch on 8 bit data size */
bogdanm	0:9b334a45a8ff	869	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	870	}
bogdanm	0:9b334a45a8ff	871	}
bogdanm	0:9b334a45a8ff	872	else
bogdanm	0:9b334a45a8ff	873	{
bogdanm	0:9b334a45a8ff	874	(hspi->pRxBuffPtr++) = (__IO uint8_t *)&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	875	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	876	}
bogdanm	0:9b334a45a8ff	877	}
bogdanm	0:9b334a45a8ff	878	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	879	{
bogdanm	0:9b334a45a8ff	880	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) > Timeout))
bogdanm	0:9b334a45a8ff	881	{
bogdanm	0:9b334a45a8ff	882	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	883	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	884	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	885	}
bogdanm	0:9b334a45a8ff	886	}
bogdanm	0:9b334a45a8ff	887	}
bogdanm	0:9b334a45a8ff	888	}
bogdanm	0:9b334a45a8ff	889
bogdanm	0:9b334a45a8ff	890	/* Read CRC from DR to close CRC calculation process */
bogdanm	0:9b334a45a8ff	891	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	892	{
bogdanm	0:9b334a45a8ff	893	/* Wait until TXE flag */
bogdanm	0:9b334a45a8ff	894	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	895	{
bogdanm	0:9b334a45a8ff	896	/* Error on the CRC reception */
bogdanm	0:9b334a45a8ff	897	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	898	}
bogdanm	0:9b334a45a8ff	899
bogdanm	0:9b334a45a8ff	900	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
bogdanm	0:9b334a45a8ff	901	{
bogdanm	0:9b334a45a8ff	902	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	903	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	904	}
bogdanm	0:9b334a45a8ff	905	else
bogdanm	0:9b334a45a8ff	906	{
bogdanm	0:9b334a45a8ff	907	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	908	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	909
bogdanm	0:9b334a45a8ff	910	if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
bogdanm	0:9b334a45a8ff	911	{
bogdanm	0:9b334a45a8ff	912	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	913	{
bogdanm	0:9b334a45a8ff	914	/* Error on the CRC reception */
bogdanm	0:9b334a45a8ff	915	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	916	}
bogdanm	0:9b334a45a8ff	917	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	918	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	919	}
bogdanm	0:9b334a45a8ff	920	}
bogdanm	0:9b334a45a8ff	921	}
bogdanm	0:9b334a45a8ff	922
bogdanm	0:9b334a45a8ff	923	/* Check the end of the transaction */
bogdanm	0:9b334a45a8ff	924	if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	925	{
bogdanm	0:9b334a45a8ff	926	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	927	}
bogdanm	0:9b334a45a8ff	928
bogdanm	0:9b334a45a8ff	929	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	930
bogdanm	0:9b334a45a8ff	931	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	932	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	933	{
bogdanm	0:9b334a45a8ff	934	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	935	/* Clear CRC Flag */
bogdanm	0:9b334a45a8ff	936	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	937
bogdanm	0:9b334a45a8ff	938	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	939	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	940
bogdanm	0:9b334a45a8ff	941	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	942	}
bogdanm	0:9b334a45a8ff	943
bogdanm	0:9b334a45a8ff	944	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	945	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	946
bogdanm	0:9b334a45a8ff	947	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	948	{
bogdanm	0:9b334a45a8ff	949	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	950	}
bogdanm	0:9b334a45a8ff	951	else
bogdanm	0:9b334a45a8ff	952	{
bogdanm	0:9b334a45a8ff	953	return HAL_OK;
bogdanm	0:9b334a45a8ff	954	}
bogdanm	0:9b334a45a8ff	955	}
bogdanm	0:9b334a45a8ff	956
bogdanm	0:9b334a45a8ff	957	/**
bogdanm	0:9b334a45a8ff	958	* @brief Transmit an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	959	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	960	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	961	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	962	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	963	* @retval HAL status
bogdanm	0:9b334a45a8ff	964	*/
bogdanm	0:9b334a45a8ff	965	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	966	{
bogdanm	0:9b334a45a8ff	967	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	968
bogdanm	0:9b334a45a8ff	969	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	970	{
bogdanm	0:9b334a45a8ff	971	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	972	{
bogdanm	0:9b334a45a8ff	973	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	974	}
bogdanm	0:9b334a45a8ff	975
bogdanm	0:9b334a45a8ff	976	/* Process Locked */
bogdanm	0:9b334a45a8ff	977	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	978
bogdanm	0:9b334a45a8ff	979	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	980	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	981	hspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	982	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	983	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	984	hspi->pRxBuffPtr = NULL;
bogdanm	0:9b334a45a8ff	985	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	986	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	987
bogdanm	0:9b334a45a8ff	988	/* Set the function for IT treatement */
bogdanm	0:9b334a45a8ff	989	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
bogdanm	0:9b334a45a8ff	990	{
bogdanm	0:9b334a45a8ff	991	hspi->RxISR = NULL;
bogdanm	0:9b334a45a8ff	992	hspi->TxISR = SPI_TxISR_16BIT;
bogdanm	0:9b334a45a8ff	993	}
bogdanm	0:9b334a45a8ff	994	else
bogdanm	0:9b334a45a8ff	995	{
bogdanm	0:9b334a45a8ff	996	hspi->RxISR = NULL;
bogdanm	0:9b334a45a8ff	997	hspi->TxISR = SPI_TxISR_8BIT;
bogdanm	0:9b334a45a8ff	998	}
bogdanm	0:9b334a45a8ff	999
bogdanm	0:9b334a45a8ff	1000	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1001	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1002	{
bogdanm	0:9b334a45a8ff	1003	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	1004	}
bogdanm	0:9b334a45a8ff	1005
bogdanm	0:9b334a45a8ff	1006	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1007	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1008	{
bogdanm	0:9b334a45a8ff	1009	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1010	}
bogdanm	0:9b334a45a8ff	1011
bogdanm	0:9b334a45a8ff	1012	/* Enable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1013	__HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
bogdanm	0:9b334a45a8ff	1014
bogdanm	0:9b334a45a8ff	1015	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1016	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1017
bogdanm	0:9b334a45a8ff	1018	/* Note : The SPI must be enabled after unlocking current process
bogdanm	0:9b334a45a8ff	1019	to avoid the risk of SPI interrupt handle execution before current
bogdanm	0:9b334a45a8ff	1020	process unlock */
bogdanm	0:9b334a45a8ff	1021
bogdanm	0:9b334a45a8ff	1022	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1023	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1024	{
bogdanm	0:9b334a45a8ff	1025	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1026	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1027	}
bogdanm	0:9b334a45a8ff	1028
bogdanm	0:9b334a45a8ff	1029	return HAL_OK;
bogdanm	0:9b334a45a8ff	1030	}
bogdanm	0:9b334a45a8ff	1031	else
bogdanm	0:9b334a45a8ff	1032	{
bogdanm	0:9b334a45a8ff	1033	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1034	}
bogdanm	0:9b334a45a8ff	1035	}
bogdanm	0:9b334a45a8ff	1036
bogdanm	0:9b334a45a8ff	1037	/**
bogdanm	0:9b334a45a8ff	1038	* @brief Receive an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	1039	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1040	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1041	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1042	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1043	* @retval HAL status
bogdanm	0:9b334a45a8ff	1044	*/
bogdanm	0:9b334a45a8ff	1045	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1046	{
bogdanm	0:9b334a45a8ff	1047	if(hspi->State == HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1048	{
bogdanm	0:9b334a45a8ff	1049	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1050	{
bogdanm	0:9b334a45a8ff	1051	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1052	}
bogdanm	0:9b334a45a8ff	1053
bogdanm	0:9b334a45a8ff	1054	/* Process Locked */
bogdanm	0:9b334a45a8ff	1055	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1056
bogdanm	0:9b334a45a8ff	1057	/* Configure communication */
bogdanm	0:9b334a45a8ff	1058	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	1059	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1060	hspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1061	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1062	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1063	hspi->pTxBuffPtr = NULL;
bogdanm	0:9b334a45a8ff	1064	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	1065	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1066
bogdanm	0:9b334a45a8ff	1067	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
bogdanm	0:9b334a45a8ff	1068	{
bogdanm	0:9b334a45a8ff	1069	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1070	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1071	/* the receive process is not supported in 2Lines direction master mode */
bogdanm	0:9b334a45a8ff	1072	/* in this we call the transmitReceive process */
bogdanm	0:9b334a45a8ff	1073	return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
bogdanm	0:9b334a45a8ff	1074	}
bogdanm	0:9b334a45a8ff	1075
bogdanm	0:9b334a45a8ff	1076	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1077	{
bogdanm	0:9b334a45a8ff	1078	hspi->CRCSize = 1;
bogdanm	0:9b334a45a8ff	1079	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
bogdanm	0:9b334a45a8ff	1080	{
bogdanm	0:9b334a45a8ff	1081	hspi->CRCSize = 2;
bogdanm	0:9b334a45a8ff	1082	}
bogdanm	0:9b334a45a8ff	1083	}
bogdanm	0:9b334a45a8ff	1084	else
bogdanm	0:9b334a45a8ff	1085	{
bogdanm	0:9b334a45a8ff	1086	hspi->CRCSize = 0;
bogdanm	0:9b334a45a8ff	1087	}
bogdanm	0:9b334a45a8ff	1088
bogdanm	0:9b334a45a8ff	1089	/* check the data size to adapt Rx threshold and the set the function for IT treatment */
bogdanm	0:9b334a45a8ff	1090	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
bogdanm	0:9b334a45a8ff	1091	{
bogdanm	0:9b334a45a8ff	1092	/* set fiforxthreshold according the reception data length: 16 bit */
bogdanm	0:9b334a45a8ff	1093	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1094	hspi->RxISR = SPI_RxISR_16BIT;
bogdanm	0:9b334a45a8ff	1095	hspi->TxISR = NULL;
bogdanm	0:9b334a45a8ff	1096	}
bogdanm	0:9b334a45a8ff	1097	else
bogdanm	0:9b334a45a8ff	1098	{
bogdanm	0:9b334a45a8ff	1099	/* set fiforxthreshold according the reception data length: 8 bit */
bogdanm	0:9b334a45a8ff	1100	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1101	hspi->RxISR = SPI_RxISR_8BIT;
bogdanm	0:9b334a45a8ff	1102	hspi->TxISR = NULL;
bogdanm	0:9b334a45a8ff	1103	}
bogdanm	0:9b334a45a8ff	1104
bogdanm	0:9b334a45a8ff	1105	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1106	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1107	{
bogdanm	0:9b334a45a8ff	1108	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	1109	}
bogdanm	0:9b334a45a8ff	1110
bogdanm	0:9b334a45a8ff	1111	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1112	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1113	{
bogdanm	0:9b334a45a8ff	1114	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1115	}
bogdanm	0:9b334a45a8ff	1116
bogdanm	0:9b334a45a8ff	1117	/* Enable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1118	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1119
bogdanm	0:9b334a45a8ff	1120	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1121	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1122
bogdanm	0:9b334a45a8ff	1123	/* Note : The SPI must be enabled after unlocking current process
bogdanm	0:9b334a45a8ff	1124	to avoid the risk of SPI interrupt handle execution before current
bogdanm	0:9b334a45a8ff	1125	process unlock */
bogdanm	0:9b334a45a8ff	1126
bogdanm	0:9b334a45a8ff	1127	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1128	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1129	{
bogdanm	0:9b334a45a8ff	1130	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1131	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1132	}
bogdanm	0:9b334a45a8ff	1133
bogdanm	0:9b334a45a8ff	1134	return HAL_OK;
bogdanm	0:9b334a45a8ff	1135	}
bogdanm	0:9b334a45a8ff	1136	else
bogdanm	0:9b334a45a8ff	1137	{
bogdanm	0:9b334a45a8ff	1138	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1139	}
bogdanm	0:9b334a45a8ff	1140	}
bogdanm	0:9b334a45a8ff	1141
bogdanm	0:9b334a45a8ff	1142	/**
bogdanm	0:9b334a45a8ff	1143	* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
bogdanm	0:9b334a45a8ff	1144	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1145	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1146	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	1147	* @param pRxData: pointer to reception data buffer
bogdanm	0:9b334a45a8ff	1148	* @param Size: amount of data to be sent and received
bogdanm	0:9b334a45a8ff	1149	* @retval HAL status
bogdanm	0:9b334a45a8ff	1150	*/
bogdanm	0:9b334a45a8ff	1151	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1152	{
bogdanm	0:9b334a45a8ff	1153	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1154
bogdanm	0:9b334a45a8ff	1155	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
bogdanm	0:9b334a45a8ff	1156	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
bogdanm	0:9b334a45a8ff	1157	{
bogdanm	0:9b334a45a8ff	1158	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1159	{
bogdanm	0:9b334a45a8ff	1160	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1161	}
bogdanm	0:9b334a45a8ff	1162
bogdanm	0:9b334a45a8ff	1163	/* Process locked */
bogdanm	0:9b334a45a8ff	1164	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1165
bogdanm	0:9b334a45a8ff	1166	hspi->CRCSize = 0;
bogdanm	0:9b334a45a8ff	1167	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1168	{
bogdanm	0:9b334a45a8ff	1169	hspi->CRCSize = 1;
bogdanm	0:9b334a45a8ff	1170	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
bogdanm	0:9b334a45a8ff	1171	{
bogdanm	0:9b334a45a8ff	1172	hspi->CRCSize = 2;
bogdanm	0:9b334a45a8ff	1173	}
bogdanm	0:9b334a45a8ff	1174	}
bogdanm	0:9b334a45a8ff	1175
bogdanm	0:9b334a45a8ff	1176	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1177	{
bogdanm	0:9b334a45a8ff	1178	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	1179	}
bogdanm	0:9b334a45a8ff	1180
bogdanm	0:9b334a45a8ff	1181	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1182	hspi->pTxBuffPtr = pTxData;
bogdanm	0:9b334a45a8ff	1183	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1184	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1185	hspi->pRxBuffPtr = pRxData;
bogdanm	0:9b334a45a8ff	1186	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1187	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1188
bogdanm	0:9b334a45a8ff	1189	/* Set the function for IT treatement */
bogdanm	0:9b334a45a8ff	1190	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
bogdanm	0:9b334a45a8ff	1191	{
bogdanm	0:9b334a45a8ff	1192	hspi->RxISR = SPI_2linesRxISR_16BIT;
bogdanm	0:9b334a45a8ff	1193	hspi->TxISR = SPI_2linesTxISR_16BIT;
bogdanm	0:9b334a45a8ff	1194	}
bogdanm	0:9b334a45a8ff	1195	else
bogdanm	0:9b334a45a8ff	1196	{
bogdanm	0:9b334a45a8ff	1197	hspi->RxISR = SPI_2linesRxISR_8BIT;
bogdanm	0:9b334a45a8ff	1198	hspi->TxISR = SPI_2linesTxISR_8BIT;
bogdanm	0:9b334a45a8ff	1199	}
bogdanm	0:9b334a45a8ff	1200
bogdanm	0:9b334a45a8ff	1201	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1202	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1203	{
bogdanm	0:9b334a45a8ff	1204	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1205	}
bogdanm	0:9b334a45a8ff	1206
bogdanm	0:9b334a45a8ff	1207	/* check if packing mode is enabled and if there is more than 2 data to receive */
bogdanm	0:9b334a45a8ff	1208	if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (hspi->RxXferCount >= 2))
bogdanm	0:9b334a45a8ff	1209	{
bogdanm	0:9b334a45a8ff	1210	/* set fiforxthreshold according the reception data length: 16 bit */
bogdanm	0:9b334a45a8ff	1211	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1212	}
bogdanm	0:9b334a45a8ff	1213	else
bogdanm	0:9b334a45a8ff	1214	{
bogdanm	0:9b334a45a8ff	1215	/* set fiforxthreshold according the reception data length: 8 bit */
bogdanm	0:9b334a45a8ff	1216	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1217	}
bogdanm	0:9b334a45a8ff	1218
bogdanm	0:9b334a45a8ff	1219	/* Enable TXE, RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	1220	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	1221
bogdanm	0:9b334a45a8ff	1222	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1223	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1224
bogdanm	0:9b334a45a8ff	1225	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1226	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1227	{
bogdanm	0:9b334a45a8ff	1228	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1229	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1230	}
bogdanm	0:9b334a45a8ff	1231
bogdanm	0:9b334a45a8ff	1232	return HAL_OK;
bogdanm	0:9b334a45a8ff	1233	}
bogdanm	0:9b334a45a8ff	1234	else
bogdanm	0:9b334a45a8ff	1235	{
bogdanm	0:9b334a45a8ff	1236	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1237	}
bogdanm	0:9b334a45a8ff	1238	}
bogdanm	0:9b334a45a8ff	1239
bogdanm	0:9b334a45a8ff	1240	/**
bogdanm	0:9b334a45a8ff	1241	* @brief Transmit an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1242	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1243	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1244	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1245	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1246	* @retval HAL status
bogdanm	0:9b334a45a8ff	1247	*/
bogdanm	0:9b334a45a8ff	1248	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1249	{
bogdanm	0:9b334a45a8ff	1250	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1251
bogdanm	0:9b334a45a8ff	1252	if(hspi->State != HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1253	{
bogdanm	0:9b334a45a8ff	1254	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1255	}
bogdanm	0:9b334a45a8ff	1256
bogdanm	0:9b334a45a8ff	1257	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1258	{
bogdanm	0:9b334a45a8ff	1259	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1260	}
bogdanm	0:9b334a45a8ff	1261
bogdanm	0:9b334a45a8ff	1262	/* Process Locked */
bogdanm	0:9b334a45a8ff	1263	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1264
bogdanm	0:9b334a45a8ff	1265	hspi->State = HAL_SPI_STATE_BUSY_TX;
bogdanm	0:9b334a45a8ff	1266	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1267	hspi->pTxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1268	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1269	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1270	hspi->pRxBuffPtr = (uint8_t *)NULL;
bogdanm	0:9b334a45a8ff	1271	hspi->RxXferSize = 0;
bogdanm	0:9b334a45a8ff	1272	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1273
bogdanm	0:9b334a45a8ff	1274	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1275	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1276	{
bogdanm	0:9b334a45a8ff	1277	SPI_1LINE_TX(hspi);
bogdanm	0:9b334a45a8ff	1278	}
bogdanm	0:9b334a45a8ff	1279
bogdanm	0:9b334a45a8ff	1280	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1281	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1282	{
bogdanm	0:9b334a45a8ff	1283	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1284	}
bogdanm	0:9b334a45a8ff	1285
bogdanm	0:9b334a45a8ff	1286	/* Set the SPI TxDMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1287	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
bogdanm	0:9b334a45a8ff	1288
bogdanm	0:9b334a45a8ff	1289	/* Set the SPI TxDMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1290	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
bogdanm	0:9b334a45a8ff	1291
bogdanm	0:9b334a45a8ff	1292	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1293	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1294
bogdanm	0:9b334a45a8ff	1295	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
bogdanm	0:9b334a45a8ff	1296	/* packing mode is enabled only if the DMA setting is HALWORD */
bogdanm	0:9b334a45a8ff	1297	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
bogdanm	0:9b334a45a8ff	1298	{
bogdanm	0:9b334a45a8ff	1299	/* Check the even/odd of the data size + crc if enabled */
bogdanm	0:9b334a45a8ff	1300	if((hspi->TxXferCount & 0x1) == 0)
bogdanm	0:9b334a45a8ff	1301	{
bogdanm	0:9b334a45a8ff	1302	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
bogdanm	0:9b334a45a8ff	1303	hspi->TxXferCount = (hspi->TxXferCount >> 1);
bogdanm	0:9b334a45a8ff	1304	}
bogdanm	0:9b334a45a8ff	1305	else
bogdanm	0:9b334a45a8ff	1306	{
bogdanm	0:9b334a45a8ff	1307	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
bogdanm	0:9b334a45a8ff	1308	hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
bogdanm	0:9b334a45a8ff	1309	}
bogdanm	0:9b334a45a8ff	1310	}
bogdanm	0:9b334a45a8ff	1311
bogdanm	0:9b334a45a8ff	1312	/* Enable the Tx DMA channel */
bogdanm	0:9b334a45a8ff	1313	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
bogdanm	0:9b334a45a8ff	1314
bogdanm	0:9b334a45a8ff	1315	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1316	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1317	{
bogdanm	0:9b334a45a8ff	1318	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1319	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1320	}
bogdanm	0:9b334a45a8ff	1321
bogdanm	0:9b334a45a8ff	1322	/* Enable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1323	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
bogdanm	0:9b334a45a8ff	1324
bogdanm	0:9b334a45a8ff	1325	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1326	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1327
bogdanm	0:9b334a45a8ff	1328	return HAL_OK;
bogdanm	0:9b334a45a8ff	1329	}
bogdanm	0:9b334a45a8ff	1330
bogdanm	0:9b334a45a8ff	1331	/**
bogdanm	0:9b334a45a8ff	1332	* @brief Receive an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1333	* @param hspi: SPI handle
bogdanm	0:9b334a45a8ff	1334	* @param pData: pointer to data buffer
bogdanm	0:9b334a45a8ff	1335	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1336	* @retval HAL status
bogdanm	0:9b334a45a8ff	1337	*/
bogdanm	0:9b334a45a8ff	1338	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1339	{
bogdanm	0:9b334a45a8ff	1340	if(hspi->State != HAL_SPI_STATE_READY)
bogdanm	0:9b334a45a8ff	1341	{
bogdanm	0:9b334a45a8ff	1342	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1343	}
bogdanm	0:9b334a45a8ff	1344
bogdanm	0:9b334a45a8ff	1345	if((pData == NULL) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1346	{
bogdanm	0:9b334a45a8ff	1347	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1348	}
bogdanm	0:9b334a45a8ff	1349
bogdanm	0:9b334a45a8ff	1350	/* Process Locked */
bogdanm	0:9b334a45a8ff	1351	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1352
bogdanm	0:9b334a45a8ff	1353	hspi->State = HAL_SPI_STATE_BUSY_RX;
bogdanm	0:9b334a45a8ff	1354	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1355	hspi->pRxBuffPtr = pData;
bogdanm	0:9b334a45a8ff	1356	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1357	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1358	hspi->pTxBuffPtr = (uint8_t *)NULL;
bogdanm	0:9b334a45a8ff	1359	hspi->TxXferSize = 0;
bogdanm	0:9b334a45a8ff	1360	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1361
bogdanm	0:9b334a45a8ff	1362	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
bogdanm	0:9b334a45a8ff	1363	{
bogdanm	0:9b334a45a8ff	1364	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1365	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1366	/* the receive process is not supported in 2Lines direction master mode */
bogdanm	0:9b334a45a8ff	1367	/* in this case we call the transmitReceive process */
bogdanm	0:9b334a45a8ff	1368	return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
bogdanm	0:9b334a45a8ff	1369	}
bogdanm	0:9b334a45a8ff	1370
bogdanm	0:9b334a45a8ff	1371	/* Configure communication direction : 1Line */
bogdanm	0:9b334a45a8ff	1372	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
bogdanm	0:9b334a45a8ff	1373	{
bogdanm	0:9b334a45a8ff	1374	SPI_1LINE_RX(hspi);
bogdanm	0:9b334a45a8ff	1375	}
bogdanm	0:9b334a45a8ff	1376
bogdanm	0:9b334a45a8ff	1377	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	1378	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1379	{
bogdanm	0:9b334a45a8ff	1380	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1381	}
bogdanm	0:9b334a45a8ff	1382
bogdanm	0:9b334a45a8ff	1383	/* packing mode management is enabled by the DMA settings */
bogdanm	0:9b334a45a8ff	1384	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
bogdanm	0:9b334a45a8ff	1385	{
bogdanm	0:9b334a45a8ff	1386	/* Process Locked */
bogdanm	0:9b334a45a8ff	1387	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1388	/* Restriction the DMA data received is not allowed in this mode */
bogdanm	0:9b334a45a8ff	1389	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1390	}
bogdanm	0:9b334a45a8ff	1391
bogdanm	0:9b334a45a8ff	1392	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
bogdanm	0:9b334a45a8ff	1393	if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	1394	{
bogdanm	0:9b334a45a8ff	1395	/* set fiforxthreshold according the reception data length: 16bit */
bogdanm	0:9b334a45a8ff	1396	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1397	}
bogdanm	0:9b334a45a8ff	1398	else
bogdanm	0:9b334a45a8ff	1399	{
bogdanm	0:9b334a45a8ff	1400	/* set fiforxthreshold according the reception data length: 8bit */
bogdanm	0:9b334a45a8ff	1401	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1402	}
bogdanm	0:9b334a45a8ff	1403
bogdanm	0:9b334a45a8ff	1404	/* Set the SPI RxDMA Half transfer complete callback */
bogdanm	0:9b334a45a8ff	1405	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
bogdanm	0:9b334a45a8ff	1406
bogdanm	0:9b334a45a8ff	1407	/* Set the SPI Rx DMA transfer complete callback */
bogdanm	0:9b334a45a8ff	1408	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
bogdanm	0:9b334a45a8ff	1409
bogdanm	0:9b334a45a8ff	1410	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1411	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1412
bogdanm	0:9b334a45a8ff	1413	/* Enable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1414	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
bogdanm	0:9b334a45a8ff	1415
bogdanm	0:9b334a45a8ff	1416	/* Enable the Rx DMA channel */
bogdanm	0:9b334a45a8ff	1417	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
bogdanm	0:9b334a45a8ff	1418
bogdanm	0:9b334a45a8ff	1419	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1420	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1421
bogdanm	0:9b334a45a8ff	1422	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1423	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1424	{
bogdanm	0:9b334a45a8ff	1425	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1426	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1427	}
bogdanm	0:9b334a45a8ff	1428
bogdanm	0:9b334a45a8ff	1429	return HAL_OK;
bogdanm	0:9b334a45a8ff	1430	}
bogdanm	0:9b334a45a8ff	1431
bogdanm	0:9b334a45a8ff	1432	/**
bogdanm	0:9b334a45a8ff	1433	* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
bogdanm	0:9b334a45a8ff	1434	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1435	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1436	* @param pTxData: pointer to transmission data buffer
bogdanm	0:9b334a45a8ff	1437	* @param pRxData: pointer to reception data buffer
bogdanm	0:9b334a45a8ff	1438	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
bogdanm	0:9b334a45a8ff	1439	* @param Size: amount of data to be sent
bogdanm	0:9b334a45a8ff	1440	* @retval HAL status
bogdanm	0:9b334a45a8ff	1441	*/
bogdanm	0:9b334a45a8ff	1442	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
bogdanm	0:9b334a45a8ff	1443	{
bogdanm	0:9b334a45a8ff	1444	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
bogdanm	0:9b334a45a8ff	1445
bogdanm	0:9b334a45a8ff	1446	if((hspi->State == HAL_SPI_STATE_READY) \|\|
bogdanm	0:9b334a45a8ff	1447	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
bogdanm	0:9b334a45a8ff	1448	{
bogdanm	0:9b334a45a8ff	1449	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
bogdanm	0:9b334a45a8ff	1450	{
bogdanm	0:9b334a45a8ff	1451	return HAL_ERROR;
bogdanm	0:9b334a45a8ff	1452	}
bogdanm	0:9b334a45a8ff	1453
bogdanm	0:9b334a45a8ff	1454	/* Process locked */
bogdanm	0:9b334a45a8ff	1455	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1456
bogdanm	0:9b334a45a8ff	1457	/* check if the transmit Receive function is not called by a receive master */
bogdanm	0:9b334a45a8ff	1458	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1459	{
bogdanm	0:9b334a45a8ff	1460	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
bogdanm	0:9b334a45a8ff	1461	}
bogdanm	0:9b334a45a8ff	1462
bogdanm	0:9b334a45a8ff	1463	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
bogdanm	0:9b334a45a8ff	1464	hspi->pTxBuffPtr = (uint8_t *)pTxData;
bogdanm	0:9b334a45a8ff	1465	hspi->TxXferSize = Size;
bogdanm	0:9b334a45a8ff	1466	hspi->TxXferCount = Size;
bogdanm	0:9b334a45a8ff	1467	hspi->pRxBuffPtr = (uint8_t *)pRxData;
bogdanm	0:9b334a45a8ff	1468	hspi->RxXferSize = Size;
bogdanm	0:9b334a45a8ff	1469	hspi->RxXferCount = Size;
bogdanm	0:9b334a45a8ff	1470
bogdanm	0:9b334a45a8ff	1471	/* Reset CRC Calculation + increase the rxsize */
bogdanm	0:9b334a45a8ff	1472	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1473	{
bogdanm	0:9b334a45a8ff	1474	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	1475	}
bogdanm	0:9b334a45a8ff	1476
bogdanm	0:9b334a45a8ff	1477	/* Reset the threshold bit */
bogdanm	0:9b334a45a8ff	1478	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
bogdanm	0:9b334a45a8ff	1479	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
bogdanm	0:9b334a45a8ff	1480
bogdanm	0:9b334a45a8ff	1481	/* the packing mode management is enabled by the DMA settings according the spi data size */
bogdanm	0:9b334a45a8ff	1482	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	1483	{
bogdanm	0:9b334a45a8ff	1484	/* set fiforxthreshold according the reception data length: 16bit */
bogdanm	0:9b334a45a8ff	1485	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1486	}
bogdanm	0:9b334a45a8ff	1487	else
bogdanm	0:9b334a45a8ff	1488	{
bogdanm	0:9b334a45a8ff	1489	/* set fiforxthreshold according the reception data length: 8bit */
bogdanm	0:9b334a45a8ff	1490	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1491
bogdanm	0:9b334a45a8ff	1492	if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
bogdanm	0:9b334a45a8ff	1493	{
bogdanm	0:9b334a45a8ff	1494	if((hspi->TxXferSize & 0x1) == 0x0 )
bogdanm	0:9b334a45a8ff	1495	{
bogdanm	0:9b334a45a8ff	1496	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
bogdanm	0:9b334a45a8ff	1497	hspi->TxXferCount = hspi->TxXferCount >> 1;
bogdanm	0:9b334a45a8ff	1498	}
bogdanm	0:9b334a45a8ff	1499	else
bogdanm	0:9b334a45a8ff	1500	{
bogdanm	0:9b334a45a8ff	1501	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
bogdanm	0:9b334a45a8ff	1502	hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
bogdanm	0:9b334a45a8ff	1503	}
bogdanm	0:9b334a45a8ff	1504	}
bogdanm	0:9b334a45a8ff	1505
bogdanm	0:9b334a45a8ff	1506	if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
bogdanm	0:9b334a45a8ff	1507	{
bogdanm	0:9b334a45a8ff	1508	/* set fiforxthreshold according the reception data length: 16bit */
bogdanm	0:9b334a45a8ff	1509	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	1510
bogdanm	0:9b334a45a8ff	1511	/* Size must include the CRC length */
bogdanm	0:9b334a45a8ff	1512	if((hspi->RxXferCount & 0x1) == 0x0 )
bogdanm	0:9b334a45a8ff	1513	{
bogdanm	0:9b334a45a8ff	1514	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
bogdanm	0:9b334a45a8ff	1515	hspi->RxXferCount = hspi->RxXferCount >> 1;
bogdanm	0:9b334a45a8ff	1516	}
bogdanm	0:9b334a45a8ff	1517	else
bogdanm	0:9b334a45a8ff	1518	{
bogdanm	0:9b334a45a8ff	1519	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
bogdanm	0:9b334a45a8ff	1520	hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
bogdanm	0:9b334a45a8ff	1521	}
bogdanm	0:9b334a45a8ff	1522	}
bogdanm	0:9b334a45a8ff	1523	}
bogdanm	0:9b334a45a8ff	1524
bogdanm	0:9b334a45a8ff	1525	/* Set the SPI Rx DMA transfer complete callback because the last generated transfer request is
bogdanm	0:9b334a45a8ff	1526	the reception request (RXNE) */
bogdanm	0:9b334a45a8ff	1527	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	1528	{
bogdanm	0:9b334a45a8ff	1529	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
bogdanm	0:9b334a45a8ff	1530	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
bogdanm	0:9b334a45a8ff	1531	}
bogdanm	0:9b334a45a8ff	1532	else
bogdanm	0:9b334a45a8ff	1533	{
bogdanm	0:9b334a45a8ff	1534	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
bogdanm	0:9b334a45a8ff	1535	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
bogdanm	0:9b334a45a8ff	1536	}
bogdanm	0:9b334a45a8ff	1537	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1538	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1539
bogdanm	0:9b334a45a8ff	1540	/* Enable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1541	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
bogdanm	0:9b334a45a8ff	1542
bogdanm	0:9b334a45a8ff	1543	/* Enable the Rx DMA channel */
bogdanm	0:9b334a45a8ff	1544	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
bogdanm	0:9b334a45a8ff	1545
bogdanm	0:9b334a45a8ff	1546	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
bogdanm	0:9b334a45a8ff	1547	is performed in DMA reception complete callback */
bogdanm	0:9b334a45a8ff	1548	hspi->hdmatx->XferHalfCpltCallback = NULL;
bogdanm	0:9b334a45a8ff	1549	hspi->hdmatx->XferCpltCallback = NULL;
bogdanm	0:9b334a45a8ff	1550
bogdanm	0:9b334a45a8ff	1551	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
bogdanm	0:9b334a45a8ff	1552	{
bogdanm	0:9b334a45a8ff	1553	/* Set the DMA error callback */
bogdanm	0:9b334a45a8ff	1554	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
bogdanm	0:9b334a45a8ff	1555	}
bogdanm	0:9b334a45a8ff	1556	else
bogdanm	0:9b334a45a8ff	1557	{
bogdanm	0:9b334a45a8ff	1558	hspi->hdmatx->XferErrorCallback = NULL;
bogdanm	0:9b334a45a8ff	1559	}
bogdanm	0:9b334a45a8ff	1560
bogdanm	0:9b334a45a8ff	1561	/* Enable the Tx DMA channel */
bogdanm	0:9b334a45a8ff	1562	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
bogdanm	0:9b334a45a8ff	1563
bogdanm	0:9b334a45a8ff	1564	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1565	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1566
bogdanm	0:9b334a45a8ff	1567	/* Check if the SPI is already enabled */
bogdanm	0:9b334a45a8ff	1568	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
bogdanm	0:9b334a45a8ff	1569	{
bogdanm	0:9b334a45a8ff	1570	/* Enable SPI peripheral */
bogdanm	0:9b334a45a8ff	1571	__HAL_SPI_ENABLE(hspi);
bogdanm	0:9b334a45a8ff	1572	}
bogdanm	0:9b334a45a8ff	1573
bogdanm	0:9b334a45a8ff	1574	/* Enable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1575	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
bogdanm	0:9b334a45a8ff	1576
bogdanm	0:9b334a45a8ff	1577	return HAL_OK;
bogdanm	0:9b334a45a8ff	1578	}
bogdanm	0:9b334a45a8ff	1579	else
bogdanm	0:9b334a45a8ff	1580	{
bogdanm	0:9b334a45a8ff	1581	return HAL_BUSY;
bogdanm	0:9b334a45a8ff	1582	}
bogdanm	0:9b334a45a8ff	1583	}
bogdanm	0:9b334a45a8ff	1584
bogdanm	0:9b334a45a8ff	1585	/**
bogdanm	0:9b334a45a8ff	1586	* @brief Pauses the DMA Transfer.
bogdanm	0:9b334a45a8ff	1587	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1588	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1589	* @retval HAL status
bogdanm	0:9b334a45a8ff	1590	*/
bogdanm	0:9b334a45a8ff	1591	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1592	{
bogdanm	0:9b334a45a8ff	1593	/* Process Locked */
bogdanm	0:9b334a45a8ff	1594	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1595
bogdanm	0:9b334a45a8ff	1596	/* Disable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1597	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1598
bogdanm	0:9b334a45a8ff	1599	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1600	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1601
bogdanm	0:9b334a45a8ff	1602	return HAL_OK;
bogdanm	0:9b334a45a8ff	1603	}
bogdanm	0:9b334a45a8ff	1604
bogdanm	0:9b334a45a8ff	1605	/**
bogdanm	0:9b334a45a8ff	1606	* @brief Resumes the DMA Transfer.
bogdanm	0:9b334a45a8ff	1607	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1608	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1609	* @retval HAL status
bogdanm	0:9b334a45a8ff	1610	*/
bogdanm	0:9b334a45a8ff	1611	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1612	{
bogdanm	0:9b334a45a8ff	1613	/* Process Locked */
bogdanm	0:9b334a45a8ff	1614	__HAL_LOCK(hspi);
bogdanm	0:9b334a45a8ff	1615
bogdanm	0:9b334a45a8ff	1616	/* Enable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1617	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1618
bogdanm	0:9b334a45a8ff	1619	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	1620	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	1621
bogdanm	0:9b334a45a8ff	1622	return HAL_OK;
bogdanm	0:9b334a45a8ff	1623	}
bogdanm	0:9b334a45a8ff	1624
bogdanm	0:9b334a45a8ff	1625	/**
bogdanm	0:9b334a45a8ff	1626	* @brief Stops the DMA Transfer.
bogdanm	0:9b334a45a8ff	1627	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1628	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1629	* @retval HAL status
bogdanm	0:9b334a45a8ff	1630	*/
bogdanm	0:9b334a45a8ff	1631	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1632	{
bogdanm	0:9b334a45a8ff	1633	/* The Lock is not implemented on this API to allow the user application
bogdanm	0:9b334a45a8ff	1634	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
bogdanm	0:9b334a45a8ff	1635	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
bogdanm	0:9b334a45a8ff	1636	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
bogdanm	0:9b334a45a8ff	1637	*/
bogdanm	0:9b334a45a8ff	1638
bogdanm	0:9b334a45a8ff	1639	/* Abort the SPI DMA tx Stream */
bogdanm	0:9b334a45a8ff	1640	if(hspi->hdmatx != NULL)
bogdanm	0:9b334a45a8ff	1641	{
bogdanm	0:9b334a45a8ff	1642	HAL_DMA_Abort(hspi->hdmatx);
bogdanm	0:9b334a45a8ff	1643	}
bogdanm	0:9b334a45a8ff	1644	/* Abort the SPI DMA rx Stream */
bogdanm	0:9b334a45a8ff	1645	if(hspi->hdmarx != NULL)
bogdanm	0:9b334a45a8ff	1646	{
bogdanm	0:9b334a45a8ff	1647	HAL_DMA_Abort(hspi->hdmarx);
bogdanm	0:9b334a45a8ff	1648	}
bogdanm	0:9b334a45a8ff	1649
bogdanm	0:9b334a45a8ff	1650	/* Disable the SPI DMA Tx & Rx requests */
bogdanm	0:9b334a45a8ff	1651	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1652	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1653	return HAL_OK;
bogdanm	0:9b334a45a8ff	1654	}
bogdanm	0:9b334a45a8ff	1655
bogdanm	0:9b334a45a8ff	1656	/**
bogdanm	0:9b334a45a8ff	1657	* @brief This function handles SPI interrupt request.
bogdanm	0:9b334a45a8ff	1658	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1659	* the configuration information for the specified SPI module.
bogdanm	0:9b334a45a8ff	1660	* @retval None
bogdanm	0:9b334a45a8ff	1661	*/
bogdanm	0:9b334a45a8ff	1662	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1663	{
bogdanm	0:9b334a45a8ff	1664	/* SPI in mode Receiver ----------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1665	if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET) &&
bogdanm	0:9b334a45a8ff	1666	(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET))
bogdanm	0:9b334a45a8ff	1667	{
bogdanm	0:9b334a45a8ff	1668	hspi->RxISR(hspi);
bogdanm	0:9b334a45a8ff	1669	return;
bogdanm	0:9b334a45a8ff	1670	}
bogdanm	0:9b334a45a8ff	1671
bogdanm	0:9b334a45a8ff	1672	/* SPI in mode Transmitter ---------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1673	if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET))
bogdanm	0:9b334a45a8ff	1674	{
bogdanm	0:9b334a45a8ff	1675	hspi->TxISR(hspi);
bogdanm	0:9b334a45a8ff	1676	return;
bogdanm	0:9b334a45a8ff	1677	}
bogdanm	0:9b334a45a8ff	1678
bogdanm	0:9b334a45a8ff	1679	/* SPI in ERROR Treatment ---------------------------------------------------*/
bogdanm	0:9b334a45a8ff	1680	if((hspi->Instance->SR & (SPI_FLAG_MODF \| SPI_FLAG_OVR \| SPI_FLAG_FRE)) != RESET)
bogdanm	0:9b334a45a8ff	1681	{
bogdanm	0:9b334a45a8ff	1682	/* SPI Overrun error interrupt occurred -------------------------------------*/
bogdanm	0:9b334a45a8ff	1683	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
bogdanm	0:9b334a45a8ff	1684	{
bogdanm	0:9b334a45a8ff	1685	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
bogdanm	0:9b334a45a8ff	1686	{
bogdanm	0:9b334a45a8ff	1687	hspi->ErrorCode \|= HAL_SPI_ERROR_OVR;
bogdanm	0:9b334a45a8ff	1688	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1689	}
bogdanm	0:9b334a45a8ff	1690	else
bogdanm	0:9b334a45a8ff	1691	{
bogdanm	0:9b334a45a8ff	1692	return;
bogdanm	0:9b334a45a8ff	1693	}
bogdanm	0:9b334a45a8ff	1694	}
bogdanm	0:9b334a45a8ff	1695
bogdanm	0:9b334a45a8ff	1696	/* SPI Mode Fault error interrupt occurred -------------------------------------*/
bogdanm	0:9b334a45a8ff	1697	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
bogdanm	0:9b334a45a8ff	1698	{
bogdanm	0:9b334a45a8ff	1699	hspi->ErrorCode \|= HAL_SPI_ERROR_MODF;
bogdanm	0:9b334a45a8ff	1700	__HAL_SPI_CLEAR_MODFFLAG(hspi);
bogdanm	0:9b334a45a8ff	1701	}
bogdanm	0:9b334a45a8ff	1702
bogdanm	0:9b334a45a8ff	1703	/* SPI Frame error interrupt occurred ----------------------------------------*/
bogdanm	0:9b334a45a8ff	1704	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
bogdanm	0:9b334a45a8ff	1705	{
bogdanm	0:9b334a45a8ff	1706	hspi->ErrorCode \|= HAL_SPI_ERROR_FRE;
bogdanm	0:9b334a45a8ff	1707	__HAL_SPI_CLEAR_FREFLAG(hspi);
bogdanm	0:9b334a45a8ff	1708	}
bogdanm	0:9b334a45a8ff	1709
bogdanm	0:9b334a45a8ff	1710	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
bogdanm	0:9b334a45a8ff	1711	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1712	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1713
bogdanm	0:9b334a45a8ff	1714	return;
bogdanm	0:9b334a45a8ff	1715	}
bogdanm	0:9b334a45a8ff	1716	}
bogdanm	0:9b334a45a8ff	1717
bogdanm	0:9b334a45a8ff	1718	/**
bogdanm	0:9b334a45a8ff	1719	* @brief Tx Transfer completed callback
bogdanm	0:9b334a45a8ff	1720	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1721	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1722	* @retval None
bogdanm	0:9b334a45a8ff	1723	*/
bogdanm	0:9b334a45a8ff	1724	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1725	{
bogdanm	0:9b334a45a8ff	1726	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1727	the HAL_SPI_TxCpltCallback should be implemented in the user file
bogdanm	0:9b334a45a8ff	1728	*/
bogdanm	0:9b334a45a8ff	1729	}
bogdanm	0:9b334a45a8ff	1730
bogdanm	0:9b334a45a8ff	1731	/**
bogdanm	0:9b334a45a8ff	1732	* @brief Rx Transfer completed callbacks
bogdanm	0:9b334a45a8ff	1733	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1734	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1735	* @retval None
bogdanm	0:9b334a45a8ff	1736	*/
bogdanm	0:9b334a45a8ff	1737	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1738	{
bogdanm	0:9b334a45a8ff	1739	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1740	the HAL_SPI_RxCpltCallback should be implemented in the user file
bogdanm	0:9b334a45a8ff	1741	*/
bogdanm	0:9b334a45a8ff	1742	}
bogdanm	0:9b334a45a8ff	1743
bogdanm	0:9b334a45a8ff	1744	/**
bogdanm	0:9b334a45a8ff	1745	* @brief Tx and Rx Transfer completed callback
bogdanm	0:9b334a45a8ff	1746	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1747	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1748	* @retval None
bogdanm	0:9b334a45a8ff	1749	*/
bogdanm	0:9b334a45a8ff	1750	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1751	{
bogdanm	0:9b334a45a8ff	1752	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1753	the HAL_SPI_TxRxCpltCallback should be implemented in the user file
bogdanm	0:9b334a45a8ff	1754	*/
bogdanm	0:9b334a45a8ff	1755	}
bogdanm	0:9b334a45a8ff	1756
bogdanm	0:9b334a45a8ff	1757	/**
bogdanm	0:9b334a45a8ff	1758	* @brief Tx Half Transfer completed callback
bogdanm	0:9b334a45a8ff	1759	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1760	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1761	* @retval None
bogdanm	0:9b334a45a8ff	1762	*/
bogdanm	0:9b334a45a8ff	1763	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1764	{
bogdanm	0:9b334a45a8ff	1765	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1766	the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
bogdanm	0:9b334a45a8ff	1767	*/
bogdanm	0:9b334a45a8ff	1768	}
bogdanm	0:9b334a45a8ff	1769
bogdanm	0:9b334a45a8ff	1770	/**
bogdanm	0:9b334a45a8ff	1771	* @brief Rx Half Transfer completed callback
bogdanm	0:9b334a45a8ff	1772	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1773	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1774	* @retval None
bogdanm	0:9b334a45a8ff	1775	*/
bogdanm	0:9b334a45a8ff	1776	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1777	{
bogdanm	0:9b334a45a8ff	1778	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1779	the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
bogdanm	0:9b334a45a8ff	1780	*/
bogdanm	0:9b334a45a8ff	1781	}
bogdanm	0:9b334a45a8ff	1782
bogdanm	0:9b334a45a8ff	1783	/**
bogdanm	0:9b334a45a8ff	1784	* @brief Tx and Rx Half Transfer callback
bogdanm	0:9b334a45a8ff	1785	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1786	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1787	* @retval None
bogdanm	0:9b334a45a8ff	1788	*/
bogdanm	0:9b334a45a8ff	1789	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1790	{
bogdanm	0:9b334a45a8ff	1791	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1792	the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
bogdanm	0:9b334a45a8ff	1793	*/
bogdanm	0:9b334a45a8ff	1794	}
bogdanm	0:9b334a45a8ff	1795
bogdanm	0:9b334a45a8ff	1796	/**
bogdanm	0:9b334a45a8ff	1797	* @brief SPI error callback
bogdanm	0:9b334a45a8ff	1798	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1799	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1800	* @retval None
bogdanm	0:9b334a45a8ff	1801	*/
bogdanm	0:9b334a45a8ff	1802	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1803	{
bogdanm	0:9b334a45a8ff	1804	/* NOTE : This function should not be modified, when the callback is needed,
bogdanm	0:9b334a45a8ff	1805	the HAL_SPI_ErrorCallback should be implemented in the user file
bogdanm	0:9b334a45a8ff	1806	*/
bogdanm	0:9b334a45a8ff	1807	/* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
bogdanm	0:9b334a45a8ff	1808	and user can use HAL_SPI_GetError() API to check the latest error occurred
bogdanm	0:9b334a45a8ff	1809	*/
bogdanm	0:9b334a45a8ff	1810	}
bogdanm	0:9b334a45a8ff	1811
bogdanm	0:9b334a45a8ff	1812	/**
bogdanm	0:9b334a45a8ff	1813	* @}
bogdanm	0:9b334a45a8ff	1814	*/
bogdanm	0:9b334a45a8ff	1815
bogdanm	0:9b334a45a8ff	1816	/**
bogdanm	0:9b334a45a8ff	1817	* @}
bogdanm	0:9b334a45a8ff	1818	*/
bogdanm	0:9b334a45a8ff	1819
bogdanm	0:9b334a45a8ff	1820	/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
bogdanm	0:9b334a45a8ff	1821	* @brief SPI control functions
bogdanm	0:9b334a45a8ff	1822	*
bogdanm	0:9b334a45a8ff	1823	@verbatim
bogdanm	0:9b334a45a8ff	1824	===============================================================================
bogdanm	0:9b334a45a8ff	1825	##### Peripheral State and Errors functions #####
bogdanm	0:9b334a45a8ff	1826	===============================================================================
bogdanm	0:9b334a45a8ff	1827	[..]
bogdanm	0:9b334a45a8ff	1828	This subsection provides a set of functions allowing to control the SPI.
bogdanm	0:9b334a45a8ff	1829	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
bogdanm	0:9b334a45a8ff	1830	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
bogdanm	0:9b334a45a8ff	1831	@endverbatim
bogdanm	0:9b334a45a8ff	1832	* @{
bogdanm	0:9b334a45a8ff	1833	*/
bogdanm	0:9b334a45a8ff	1834
bogdanm	0:9b334a45a8ff	1835	/**
bogdanm	0:9b334a45a8ff	1836	* @brief Return the SPI state
bogdanm	0:9b334a45a8ff	1837	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1838	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1839	* @retval SPI state
bogdanm	0:9b334a45a8ff	1840	*/
bogdanm	0:9b334a45a8ff	1841	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1842	{
bogdanm	0:9b334a45a8ff	1843	return hspi->State;
bogdanm	0:9b334a45a8ff	1844	}
bogdanm	0:9b334a45a8ff	1845
bogdanm	0:9b334a45a8ff	1846	/**
bogdanm	0:9b334a45a8ff	1847	* @brief Return the SPI error code
bogdanm	0:9b334a45a8ff	1848	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1849	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	1850	* @retval SPI error code in bitmap format
bogdanm	0:9b334a45a8ff	1851	*/
bogdanm	0:9b334a45a8ff	1852	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	1853	{
bogdanm	0:9b334a45a8ff	1854	return hspi->ErrorCode;
bogdanm	0:9b334a45a8ff	1855	}
bogdanm	0:9b334a45a8ff	1856
bogdanm	0:9b334a45a8ff	1857	/**
bogdanm	0:9b334a45a8ff	1858	* @}
bogdanm	0:9b334a45a8ff	1859	*/
bogdanm	0:9b334a45a8ff	1860
bogdanm	0:9b334a45a8ff	1861	/**
bogdanm	0:9b334a45a8ff	1862	* @}
bogdanm	0:9b334a45a8ff	1863	*/
bogdanm	0:9b334a45a8ff	1864
bogdanm	0:9b334a45a8ff	1865	/** @defgroup SPI_Private_Functions SPI Private Functions
bogdanm	0:9b334a45a8ff	1866	* @{
bogdanm	0:9b334a45a8ff	1867	*/
bogdanm	0:9b334a45a8ff	1868
bogdanm	0:9b334a45a8ff	1869	/**
bogdanm	0:9b334a45a8ff	1870	* @brief DMA SPI transmit process complete callback
bogdanm	0:9b334a45a8ff	1871	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1872	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1873	* @retval None
bogdanm	0:9b334a45a8ff	1874	*/
bogdanm	0:9b334a45a8ff	1875	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1876	{
bogdanm	0:9b334a45a8ff	1877	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1878
bogdanm	0:9b334a45a8ff	1879	/* DMA Normal Mode */
bogdanm	0:9b334a45a8ff	1880	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
bogdanm	0:9b334a45a8ff	1881	{
bogdanm	0:9b334a45a8ff	1882	/* Disable Tx DMA Request */
bogdanm	0:9b334a45a8ff	1883	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1884
bogdanm	0:9b334a45a8ff	1885	/* Clear OVERUN flag in 2 Lines communication mode because received data is not read */
bogdanm	0:9b334a45a8ff	1886	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	1887	{
bogdanm	0:9b334a45a8ff	1888	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1889	}
bogdanm	0:9b334a45a8ff	1890
bogdanm	0:9b334a45a8ff	1891	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	1892	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1893
bogdanm	0:9b334a45a8ff	1894	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1895	{
bogdanm	0:9b334a45a8ff	1896	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1897	return;
bogdanm	0:9b334a45a8ff	1898	}
bogdanm	0:9b334a45a8ff	1899	}
bogdanm	0:9b334a45a8ff	1900	HAL_SPI_TxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1901	}
bogdanm	0:9b334a45a8ff	1902
bogdanm	0:9b334a45a8ff	1903	/**
bogdanm	0:9b334a45a8ff	1904	* @brief DMA SPI receive process complete callback
bogdanm	0:9b334a45a8ff	1905	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1906	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1907	* @retval None
bogdanm	0:9b334a45a8ff	1908	*/
bogdanm	0:9b334a45a8ff	1909	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1910	{
bogdanm	0:9b334a45a8ff	1911	__IO uint16_t tmpreg;
bogdanm	0:9b334a45a8ff	1912	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1913
bogdanm	0:9b334a45a8ff	1914	/* DMA Normal mode */
bogdanm	0:9b334a45a8ff	1915	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
bogdanm	0:9b334a45a8ff	1916	{
bogdanm	0:9b334a45a8ff	1917	/* CRC handling */
bogdanm	0:9b334a45a8ff	1918	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1919	{
bogdanm	0:9b334a45a8ff	1920	/* Wait until TXE flag */
bogdanm	0:9b334a45a8ff	1921	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
bogdanm	0:9b334a45a8ff	1922	{
bogdanm	0:9b334a45a8ff	1923	/* Error on the CRC reception */
bogdanm	0:9b334a45a8ff	1924	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	1925	}
bogdanm	0:9b334a45a8ff	1926	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
bogdanm	0:9b334a45a8ff	1927	{
bogdanm	0:9b334a45a8ff	1928	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1929	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	1930	}
bogdanm	0:9b334a45a8ff	1931	else
bogdanm	0:9b334a45a8ff	1932	{
bogdanm	0:9b334a45a8ff	1933	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1934	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	1935
bogdanm	0:9b334a45a8ff	1936	if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
bogdanm	0:9b334a45a8ff	1937	{
bogdanm	0:9b334a45a8ff	1938	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
bogdanm	0:9b334a45a8ff	1939	{
bogdanm	0:9b334a45a8ff	1940	/* Error on the CRC reception */
bogdanm	0:9b334a45a8ff	1941	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	1942	}
bogdanm	0:9b334a45a8ff	1943	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	1944	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	1945	}
bogdanm	0:9b334a45a8ff	1946	}
bogdanm	0:9b334a45a8ff	1947	}
bogdanm	0:9b334a45a8ff	1948
bogdanm	0:9b334a45a8ff	1949	/* Disable Rx DMA Request */
bogdanm	0:9b334a45a8ff	1950	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	1951	/* Disable Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
bogdanm	0:9b334a45a8ff	1952	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	1953
bogdanm	0:9b334a45a8ff	1954	/* Check the end of the transaction */
bogdanm	0:9b334a45a8ff	1955	SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
bogdanm	0:9b334a45a8ff	1956
bogdanm	0:9b334a45a8ff	1957	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	1958	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	1959
bogdanm	0:9b334a45a8ff	1960	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	1961	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	1962	{
bogdanm	0:9b334a45a8ff	1963	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	1964	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	1965	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1966	}
bogdanm	0:9b334a45a8ff	1967	else
bogdanm	0:9b334a45a8ff	1968	{
bogdanm	0:9b334a45a8ff	1969	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	1970	{
bogdanm	0:9b334a45a8ff	1971	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1972	}
bogdanm	0:9b334a45a8ff	1973	else
bogdanm	0:9b334a45a8ff	1974	{
bogdanm	0:9b334a45a8ff	1975	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	1976	}
bogdanm	0:9b334a45a8ff	1977	}
bogdanm	0:9b334a45a8ff	1978	}
bogdanm	0:9b334a45a8ff	1979	else
bogdanm	0:9b334a45a8ff	1980	{
bogdanm	0:9b334a45a8ff	1981	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	1982	}
bogdanm	0:9b334a45a8ff	1983	}
bogdanm	0:9b334a45a8ff	1984
bogdanm	0:9b334a45a8ff	1985	/**
bogdanm	0:9b334a45a8ff	1986	* @brief DMA SPI transmit receive process complete callback
bogdanm	0:9b334a45a8ff	1987	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	1988	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	1989	* @retval None
bogdanm	0:9b334a45a8ff	1990	*/
bogdanm	0:9b334a45a8ff	1991	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	1992	{
bogdanm	0:9b334a45a8ff	1993	__IO int16_t tmpreg;
bogdanm	0:9b334a45a8ff	1994	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	1995
bogdanm	0:9b334a45a8ff	1996	/* CRC handling */
bogdanm	0:9b334a45a8ff	1997	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	1998	{
bogdanm	0:9b334a45a8ff	1999	if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
bogdanm	0:9b334a45a8ff	2000	{
bogdanm	0:9b334a45a8ff	2001	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
bogdanm	0:9b334a45a8ff	2002	{
bogdanm	0:9b334a45a8ff	2003	/* Error on the CRC reception */
bogdanm	0:9b334a45a8ff	2004	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	2005	}
bogdanm	0:9b334a45a8ff	2006	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2007	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	2008	}
bogdanm	0:9b334a45a8ff	2009	else
bogdanm	0:9b334a45a8ff	2010	{
bogdanm	0:9b334a45a8ff	2011	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
bogdanm	0:9b334a45a8ff	2012	{
bogdanm	0:9b334a45a8ff	2013	/* Error on the CRC reception */
bogdanm	0:9b334a45a8ff	2014	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	2015	}
bogdanm	0:9b334a45a8ff	2016	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2017	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	2018	}
bogdanm	0:9b334a45a8ff	2019	}
bogdanm	0:9b334a45a8ff	2020
bogdanm	0:9b334a45a8ff	2021	/* Check the end of the transaction */
bogdanm	0:9b334a45a8ff	2022	SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
bogdanm	0:9b334a45a8ff	2023
bogdanm	0:9b334a45a8ff	2024	/* Disable Tx DMA Request */
bogdanm	0:9b334a45a8ff	2025	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
bogdanm	0:9b334a45a8ff	2026
bogdanm	0:9b334a45a8ff	2027	/* Disable Rx DMA Request */
bogdanm	0:9b334a45a8ff	2028	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	2029
bogdanm	0:9b334a45a8ff	2030	hspi->TxXferCount = 0;
bogdanm	0:9b334a45a8ff	2031	hspi->RxXferCount = 0;
bogdanm	0:9b334a45a8ff	2032	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2033
bogdanm	0:9b334a45a8ff	2034	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	2035	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	2036	{
bogdanm	0:9b334a45a8ff	2037	hspi->ErrorCode = HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	2038	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2039	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2040	}
bogdanm	0:9b334a45a8ff	2041	else
bogdanm	0:9b334a45a8ff	2042	{
bogdanm	0:9b334a45a8ff	2043	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2044	{
bogdanm	0:9b334a45a8ff	2045	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2046	}
bogdanm	0:9b334a45a8ff	2047	else
bogdanm	0:9b334a45a8ff	2048	{
bogdanm	0:9b334a45a8ff	2049	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2050	}
bogdanm	0:9b334a45a8ff	2051	}
bogdanm	0:9b334a45a8ff	2052	}
bogdanm	0:9b334a45a8ff	2053
bogdanm	0:9b334a45a8ff	2054	/**
bogdanm	0:9b334a45a8ff	2055	* @brief DMA SPI half transmit process complete callback
bogdanm	0:9b334a45a8ff	2056	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2057	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2058	* @retval None
bogdanm	0:9b334a45a8ff	2059	*/
bogdanm	0:9b334a45a8ff	2060	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2061	{
bogdanm	0:9b334a45a8ff	2062	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2063
bogdanm	0:9b334a45a8ff	2064	HAL_SPI_TxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2065	}
bogdanm	0:9b334a45a8ff	2066
bogdanm	0:9b334a45a8ff	2067	/**
bogdanm	0:9b334a45a8ff	2068	* @brief DMA SPI half receive process complete callback
bogdanm	0:9b334a45a8ff	2069	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2070	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2071	* @retval None
bogdanm	0:9b334a45a8ff	2072	*/
bogdanm	0:9b334a45a8ff	2073	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2074	{
bogdanm	0:9b334a45a8ff	2075	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2076
bogdanm	0:9b334a45a8ff	2077	HAL_SPI_RxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2078	}
bogdanm	0:9b334a45a8ff	2079
bogdanm	0:9b334a45a8ff	2080	/**
bogdanm	0:9b334a45a8ff	2081	* @brief DMA SPI Half transmit receive process complete callback
bogdanm	0:9b334a45a8ff	2082	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2083	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2084	* @retval None
bogdanm	0:9b334a45a8ff	2085	*/
bogdanm	0:9b334a45a8ff	2086	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2087	{
bogdanm	0:9b334a45a8ff	2088	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2089
bogdanm	0:9b334a45a8ff	2090	HAL_SPI_TxRxHalfCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2091	}
bogdanm	0:9b334a45a8ff	2092
bogdanm	0:9b334a45a8ff	2093	/**
bogdanm	0:9b334a45a8ff	2094	* @brief DMA SPI communication error callback
bogdanm	0:9b334a45a8ff	2095	* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2096	* the configuration information for the specified DMA module.
bogdanm	0:9b334a45a8ff	2097	* @retval None
bogdanm	0:9b334a45a8ff	2098	*/
bogdanm	0:9b334a45a8ff	2099	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
bogdanm	0:9b334a45a8ff	2100	{
bogdanm	0:9b334a45a8ff	2101	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
bogdanm	0:9b334a45a8ff	2102
bogdanm	0:9b334a45a8ff	2103	/* Stop the disable DMA transfer on SPI side */
bogdanm	0:9b334a45a8ff	2104	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN \| SPI_CR2_RXDMAEN);
bogdanm	0:9b334a45a8ff	2105
bogdanm	0:9b334a45a8ff	2106	hspi->ErrorCode\|= HAL_SPI_ERROR_DMA;
bogdanm	0:9b334a45a8ff	2107	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2108	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2109	}
bogdanm	0:9b334a45a8ff	2110
bogdanm	0:9b334a45a8ff	2111	/**
bogdanm	0:9b334a45a8ff	2112	* @brief Rx Handler for Transmit and Receive in Interrupt mode
bogdanm	0:9b334a45a8ff	2113	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2114	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2115	* @retval None
bogdanm	0:9b334a45a8ff	2116	*/
bogdanm	0:9b334a45a8ff	2117	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2118	{
bogdanm	0:9b334a45a8ff	2119	/* Receive data in packing mode */
bogdanm	0:9b334a45a8ff	2120	if(hspi->RxXferCount > 1)
bogdanm	0:9b334a45a8ff	2121	{
bogdanm	0:9b334a45a8ff	2122	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2123	hspi->pRxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	2124	hspi->RxXferCount -= 2;
bogdanm	0:9b334a45a8ff	2125	if(hspi->RxXferCount == 1)
bogdanm	0:9b334a45a8ff	2126	{
bogdanm	0:9b334a45a8ff	2127	/* set fiforxthreshold according the reception data length: 8bit */
bogdanm	0:9b334a45a8ff	2128	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	2129	}
bogdanm	0:9b334a45a8ff	2130	}
bogdanm	0:9b334a45a8ff	2131	/* Receive data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	2132	else
bogdanm	0:9b334a45a8ff	2133	{
bogdanm	0:9b334a45a8ff	2134	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
bogdanm	0:9b334a45a8ff	2135	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	2136	}
bogdanm	0:9b334a45a8ff	2137
bogdanm	0:9b334a45a8ff	2138	/* check end of the reception */
bogdanm	0:9b334a45a8ff	2139	if(hspi->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	2140	{
bogdanm	0:9b334a45a8ff	2141	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2142	{
bogdanm	0:9b334a45a8ff	2143	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
bogdanm	0:9b334a45a8ff	2144	hspi->RxISR = SPI_2linesRxISR_8BITCRC;
bogdanm	0:9b334a45a8ff	2145	return;
bogdanm	0:9b334a45a8ff	2146	}
bogdanm	0:9b334a45a8ff	2147
bogdanm	0:9b334a45a8ff	2148	/* Disable RXNE interrupt */
bogdanm	0:9b334a45a8ff	2149	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
bogdanm	0:9b334a45a8ff	2150
bogdanm	0:9b334a45a8ff	2151	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	2152	{
bogdanm	0:9b334a45a8ff	2153	SPI_CloseRxTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2154	}
bogdanm	0:9b334a45a8ff	2155	}
bogdanm	0:9b334a45a8ff	2156	}
bogdanm	0:9b334a45a8ff	2157
bogdanm	0:9b334a45a8ff	2158	/**
bogdanm	0:9b334a45a8ff	2159	* @brief Rx Handler for Transmit and Receive in Interrupt mode
bogdanm	0:9b334a45a8ff	2160	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2161	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2162	* @retval None
bogdanm	0:9b334a45a8ff	2163	*/
bogdanm	0:9b334a45a8ff	2164	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2165	{
bogdanm	0:9b334a45a8ff	2166	__IO uint8_t tmpreg;
bogdanm	0:9b334a45a8ff	2167
bogdanm	0:9b334a45a8ff	2168	tmpreg = ((__IO uint8_t )&hspi->Instance->DR);
bogdanm	0:9b334a45a8ff	2169	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	2170
bogdanm	0:9b334a45a8ff	2171	hspi->CRCSize--;
bogdanm	0:9b334a45a8ff	2172
bogdanm	0:9b334a45a8ff	2173	/* check end of the reception */
bogdanm	0:9b334a45a8ff	2174	if(hspi->CRCSize == 0)
bogdanm	0:9b334a45a8ff	2175	{
bogdanm	0:9b334a45a8ff	2176	/* Disable RXNE interrupt */
bogdanm	0:9b334a45a8ff	2177	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
bogdanm	0:9b334a45a8ff	2178
bogdanm	0:9b334a45a8ff	2179	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	2180	{
bogdanm	0:9b334a45a8ff	2181	SPI_CloseRxTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2182	}
bogdanm	0:9b334a45a8ff	2183	}
bogdanm	0:9b334a45a8ff	2184	}
bogdanm	0:9b334a45a8ff	2185
bogdanm	0:9b334a45a8ff	2186	/**
bogdanm	0:9b334a45a8ff	2187	* @brief Tx Handler for Transmit and Receive in Interrupt mode
bogdanm	0:9b334a45a8ff	2188	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2189	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2190	* @retval None
bogdanm	0:9b334a45a8ff	2191	*/
bogdanm	0:9b334a45a8ff	2192	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2193	{
bogdanm	0:9b334a45a8ff	2194	/* Transmit data in packing Bit mode */
bogdanm	0:9b334a45a8ff	2195	if(hspi->TxXferCount >= 2)
bogdanm	0:9b334a45a8ff	2196	{
bogdanm	0:9b334a45a8ff	2197	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	2198	hspi->pTxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	2199	hspi->TxXferCount -= 2;
bogdanm	0:9b334a45a8ff	2200	}
bogdanm	0:9b334a45a8ff	2201	/* Transmit data in 8 Bit mode */
bogdanm	0:9b334a45a8ff	2202	else
bogdanm	0:9b334a45a8ff	2203	{
bogdanm	0:9b334a45a8ff	2204	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	2205	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	2206	}
bogdanm	0:9b334a45a8ff	2207
bogdanm	0:9b334a45a8ff	2208	/* check the end of the transmission */
bogdanm	0:9b334a45a8ff	2209	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	2210	{
bogdanm	0:9b334a45a8ff	2211	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2212	{
bogdanm	0:9b334a45a8ff	2213	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	2214	}
bogdanm	0:9b334a45a8ff	2215	/* Disable TXE interrupt */
bogdanm	0:9b334a45a8ff	2216	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
bogdanm	0:9b334a45a8ff	2217
bogdanm	0:9b334a45a8ff	2218	if(hspi->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	2219	{
bogdanm	0:9b334a45a8ff	2220	SPI_CloseRxTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2221	}
bogdanm	0:9b334a45a8ff	2222	}
bogdanm	0:9b334a45a8ff	2223	}
bogdanm	0:9b334a45a8ff	2224
bogdanm	0:9b334a45a8ff	2225	/**
bogdanm	0:9b334a45a8ff	2226	* @brief Rx 16Bit Handler for Transmit and Receive in Interrupt mode
bogdanm	0:9b334a45a8ff	2227	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2228	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2229	* @retval None
bogdanm	0:9b334a45a8ff	2230	*/
bogdanm	0:9b334a45a8ff	2231	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2232	{
bogdanm	0:9b334a45a8ff	2233	/* Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	2234	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2235	hspi->pRxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	2236	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	2237
bogdanm	0:9b334a45a8ff	2238	if(hspi->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	2239	{
bogdanm	0:9b334a45a8ff	2240	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2241	{
bogdanm	0:9b334a45a8ff	2242	hspi->RxISR = SPI_2linesRxISR_16BITCRC;
bogdanm	0:9b334a45a8ff	2243	return;
bogdanm	0:9b334a45a8ff	2244	}
bogdanm	0:9b334a45a8ff	2245
bogdanm	0:9b334a45a8ff	2246	/* Disable RXNE interrupt */
bogdanm	0:9b334a45a8ff	2247	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
bogdanm	0:9b334a45a8ff	2248
bogdanm	0:9b334a45a8ff	2249	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	2250	{
bogdanm	0:9b334a45a8ff	2251	SPI_CloseRxTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2252	}
bogdanm	0:9b334a45a8ff	2253	}
bogdanm	0:9b334a45a8ff	2254	}
bogdanm	0:9b334a45a8ff	2255
bogdanm	0:9b334a45a8ff	2256	/**
bogdanm	0:9b334a45a8ff	2257	* @brief Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode
bogdanm	0:9b334a45a8ff	2258	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2259	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2260	* @retval None
bogdanm	0:9b334a45a8ff	2261	*/
bogdanm	0:9b334a45a8ff	2262	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2263	{
bogdanm	0:9b334a45a8ff	2264	/* Receive data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	2265	__IO uint16_t tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2266	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	2267
bogdanm	0:9b334a45a8ff	2268	/* Disable RXNE interrupt */
bogdanm	0:9b334a45a8ff	2269	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
bogdanm	0:9b334a45a8ff	2270
bogdanm	0:9b334a45a8ff	2271	SPI_CloseRxTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2272	}
bogdanm	0:9b334a45a8ff	2273
bogdanm	0:9b334a45a8ff	2274	/**
bogdanm	0:9b334a45a8ff	2275	* @brief Tx Handler for Transmit and Receive in Interrupt mode
bogdanm	0:9b334a45a8ff	2276	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2277	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2278	* @retval None
bogdanm	0:9b334a45a8ff	2279	*/
bogdanm	0:9b334a45a8ff	2280	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2281	{
bogdanm	0:9b334a45a8ff	2282	/* Transmit data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	2283	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	2284	hspi->pTxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	2285	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	2286
bogdanm	0:9b334a45a8ff	2287	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	2288	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	2289	{
bogdanm	0:9b334a45a8ff	2290	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2291	{
bogdanm	0:9b334a45a8ff	2292	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	2293	}
bogdanm	0:9b334a45a8ff	2294	/* Disable TXE interrupt */
bogdanm	0:9b334a45a8ff	2295	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
bogdanm	0:9b334a45a8ff	2296
bogdanm	0:9b334a45a8ff	2297	if(hspi->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	2298	{
bogdanm	0:9b334a45a8ff	2299	SPI_CloseRxTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2300	}
bogdanm	0:9b334a45a8ff	2301	}
bogdanm	0:9b334a45a8ff	2302	}
bogdanm	0:9b334a45a8ff	2303
bogdanm	0:9b334a45a8ff	2304	/**
bogdanm	0:9b334a45a8ff	2305	* @brief Manage the CRC receive in Interrupt context
bogdanm	0:9b334a45a8ff	2306	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2307	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2308	* @retval None
bogdanm	0:9b334a45a8ff	2309	*/
bogdanm	0:9b334a45a8ff	2310	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2311	{
bogdanm	0:9b334a45a8ff	2312	__IO uint8_t tmpreg;
bogdanm	0:9b334a45a8ff	2313	tmpreg = ((__IO uint8_t)&hspi->Instance->DR);
bogdanm	0:9b334a45a8ff	2314	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	2315
bogdanm	0:9b334a45a8ff	2316	hspi->CRCSize--;
bogdanm	0:9b334a45a8ff	2317
bogdanm	0:9b334a45a8ff	2318	if(hspi->CRCSize == 0)
bogdanm	0:9b334a45a8ff	2319	{
bogdanm	0:9b334a45a8ff	2320	SPI_CloseRx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2321	}
bogdanm	0:9b334a45a8ff	2322	}
bogdanm	0:9b334a45a8ff	2323
bogdanm	0:9b334a45a8ff	2324	/**
bogdanm	0:9b334a45a8ff	2325	* @brief Manage the receive in Interrupt context
bogdanm	0:9b334a45a8ff	2326	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2327	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2328	* @retval None
bogdanm	0:9b334a45a8ff	2329	*/
bogdanm	0:9b334a45a8ff	2330	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2331	{
bogdanm	0:9b334a45a8ff	2332	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
bogdanm	0:9b334a45a8ff	2333	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	2334
bogdanm	0:9b334a45a8ff	2335	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	2336	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	2337	{
bogdanm	0:9b334a45a8ff	2338	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	2339	}
bogdanm	0:9b334a45a8ff	2340
bogdanm	0:9b334a45a8ff	2341	if(hspi->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	2342	{
bogdanm	0:9b334a45a8ff	2343	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2344	{
bogdanm	0:9b334a45a8ff	2345	hspi->RxISR = SPI_RxISR_8BITCRC;
bogdanm	0:9b334a45a8ff	2346	return;
bogdanm	0:9b334a45a8ff	2347	}
bogdanm	0:9b334a45a8ff	2348	SPI_CloseRx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2349	}
bogdanm	0:9b334a45a8ff	2350	}
bogdanm	0:9b334a45a8ff	2351
bogdanm	0:9b334a45a8ff	2352	/**
bogdanm	0:9b334a45a8ff	2353	* @brief Manage the CRC 16bit receive in Interrupt context
bogdanm	0:9b334a45a8ff	2354	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2355	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2356	* @retval None
bogdanm	0:9b334a45a8ff	2357	*/
bogdanm	0:9b334a45a8ff	2358	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2359	{
bogdanm	0:9b334a45a8ff	2360	__IO uint16_t tmpreg;
bogdanm	0:9b334a45a8ff	2361
bogdanm	0:9b334a45a8ff	2362	tmpreg = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2363	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	2364
bogdanm	0:9b334a45a8ff	2365	/* Disable RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	2366	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2367
bogdanm	0:9b334a45a8ff	2368	SPI_CloseRx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2369	}
bogdanm	0:9b334a45a8ff	2370
bogdanm	0:9b334a45a8ff	2371	/**
bogdanm	0:9b334a45a8ff	2372	* @brief Manage the 16Bit receive in Interrupt context
bogdanm	0:9b334a45a8ff	2373	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2374	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2375	* @retval None
bogdanm	0:9b334a45a8ff	2376	*/
bogdanm	0:9b334a45a8ff	2377	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2378	{
bogdanm	0:9b334a45a8ff	2379	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
bogdanm	0:9b334a45a8ff	2380	hspi->pRxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	2381	hspi->RxXferCount--;
bogdanm	0:9b334a45a8ff	2382
bogdanm	0:9b334a45a8ff	2383	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	2384	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
bogdanm	0:9b334a45a8ff	2385	{
bogdanm	0:9b334a45a8ff	2386	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	2387	}
bogdanm	0:9b334a45a8ff	2388
bogdanm	0:9b334a45a8ff	2389	if(hspi->RxXferCount == 0)
bogdanm	0:9b334a45a8ff	2390	{
bogdanm	0:9b334a45a8ff	2391	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2392	{
bogdanm	0:9b334a45a8ff	2393	hspi->RxISR = SPI_RxISR_16BITCRC;
bogdanm	0:9b334a45a8ff	2394	return;
bogdanm	0:9b334a45a8ff	2395	}
bogdanm	0:9b334a45a8ff	2396	SPI_CloseRx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2397	}
bogdanm	0:9b334a45a8ff	2398	}
bogdanm	0:9b334a45a8ff	2399
bogdanm	0:9b334a45a8ff	2400	/**
bogdanm	0:9b334a45a8ff	2401	* @brief Handle the data 8Bit transmit in Interrupt mode
bogdanm	0:9b334a45a8ff	2402	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2403	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2404	* @retval None
bogdanm	0:9b334a45a8ff	2405	*/
bogdanm	0:9b334a45a8ff	2406	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2407	{
bogdanm	0:9b334a45a8ff	2408	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
bogdanm	0:9b334a45a8ff	2409	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	2410
bogdanm	0:9b334a45a8ff	2411	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	2412	{
bogdanm	0:9b334a45a8ff	2413	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2414	{
bogdanm	0:9b334a45a8ff	2415	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	2416	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	2417	}
bogdanm	0:9b334a45a8ff	2418	SPI_CloseTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2419	}
bogdanm	0:9b334a45a8ff	2420	}
bogdanm	0:9b334a45a8ff	2421
bogdanm	0:9b334a45a8ff	2422	/**
bogdanm	0:9b334a45a8ff	2423	* @brief Handle the data 16Bit transmit in Interrupt mode
bogdanm	0:9b334a45a8ff	2424	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2425	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2426	* @retval None
bogdanm	0:9b334a45a8ff	2427	*/
bogdanm	0:9b334a45a8ff	2428	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2429	{
bogdanm	0:9b334a45a8ff	2430	/* Transmit data in 16 Bit mode */
bogdanm	0:9b334a45a8ff	2431	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
bogdanm	0:9b334a45a8ff	2432	hspi->pTxBuffPtr += sizeof(uint16_t);
bogdanm	0:9b334a45a8ff	2433	hspi->TxXferCount--;
bogdanm	0:9b334a45a8ff	2434
bogdanm	0:9b334a45a8ff	2435	if(hspi->TxXferCount == 0)
bogdanm	0:9b334a45a8ff	2436	{
bogdanm	0:9b334a45a8ff	2437	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2438	{
bogdanm	0:9b334a45a8ff	2439	/* Enable CRC Transmission */
bogdanm	0:9b334a45a8ff	2440	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
bogdanm	0:9b334a45a8ff	2441	}
bogdanm	0:9b334a45a8ff	2442	SPI_CloseTx_ISR(hspi);
bogdanm	0:9b334a45a8ff	2443	}
bogdanm	0:9b334a45a8ff	2444	}
bogdanm	0:9b334a45a8ff	2445
bogdanm	0:9b334a45a8ff	2446	/**
bogdanm	0:9b334a45a8ff	2447	* @brief This function handles SPI Communication Timeout.
bogdanm	0:9b334a45a8ff	2448	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2449	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2450	* @param Flag : SPI flag to check
bogdanm	0:9b334a45a8ff	2451	* @param State : flag state to check
bogdanm	0:9b334a45a8ff	2452	* @param Timeout : Timeout duration
bogdanm	0:9b334a45a8ff	2453	* @retval HAL status
bogdanm	0:9b334a45a8ff	2454	*/
bogdanm	0:9b334a45a8ff	2455	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	2456	{
bogdanm	0:9b334a45a8ff	2457	uint32_t tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	2458
bogdanm	0:9b334a45a8ff	2459	while((hspi->Instance->SR & Flag) != State)
bogdanm	0:9b334a45a8ff	2460	{
bogdanm	0:9b334a45a8ff	2461	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	2462	{
bogdanm	0:9b334a45a8ff	2463	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) >= Timeout))
bogdanm	0:9b334a45a8ff	2464	{
bogdanm	0:9b334a45a8ff	2465	/* Disable the SPI and reset the CRC: the CRC value should be cleared
bogdanm	0:9b334a45a8ff	2466	on both master and slave sides in order to resynchronize the master
bogdanm	0:9b334a45a8ff	2467	and slave for their respective CRC calculation */
bogdanm	0:9b334a45a8ff	2468
bogdanm	0:9b334a45a8ff	2469	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
bogdanm	0:9b334a45a8ff	2470	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2471
bogdanm	0:9b334a45a8ff	2472	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	2473	{
bogdanm	0:9b334a45a8ff	2474	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	2475	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	2476	}
bogdanm	0:9b334a45a8ff	2477
bogdanm	0:9b334a45a8ff	2478	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	2479	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2480	{
bogdanm	0:9b334a45a8ff	2481	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	2482	}
bogdanm	0:9b334a45a8ff	2483
bogdanm	0:9b334a45a8ff	2484	hspi->State= HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2485
bogdanm	0:9b334a45a8ff	2486	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2487	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	2488
bogdanm	0:9b334a45a8ff	2489	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2490	}
bogdanm	0:9b334a45a8ff	2491	}
bogdanm	0:9b334a45a8ff	2492	}
bogdanm	0:9b334a45a8ff	2493
bogdanm	0:9b334a45a8ff	2494	return HAL_OK;
bogdanm	0:9b334a45a8ff	2495	}
bogdanm	0:9b334a45a8ff	2496
bogdanm	0:9b334a45a8ff	2497	/**
bogdanm	0:9b334a45a8ff	2498	* @brief This function handles SPI Communication Timeout.
bogdanm	0:9b334a45a8ff	2499	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2500	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2501	* @param Fifo : Fifo to check
bogdanm	0:9b334a45a8ff	2502	* @param State : Fifo state to check
bogdanm	0:9b334a45a8ff	2503	* @param Timeout : Timeout duration
bogdanm	0:9b334a45a8ff	2504	* @retval HAL status
bogdanm	0:9b334a45a8ff	2505	*/
bogdanm	0:9b334a45a8ff	2506	static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	2507	{
bogdanm	0:9b334a45a8ff	2508	__IO uint8_t tmpreg;
bogdanm	0:9b334a45a8ff	2509	uint32_t tickstart = HAL_GetTick();
bogdanm	0:9b334a45a8ff	2510
bogdanm	0:9b334a45a8ff	2511	while((hspi->Instance->SR & Fifo) != State)
bogdanm	0:9b334a45a8ff	2512	{
bogdanm	0:9b334a45a8ff	2513	if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
bogdanm	0:9b334a45a8ff	2514	{
bogdanm	0:9b334a45a8ff	2515	tmpreg = ((__IO uint8_t)&hspi->Instance->DR);
bogdanm	0:9b334a45a8ff	2516	UNUSED(tmpreg); /* To avoid GCC warning */
bogdanm	0:9b334a45a8ff	2517	}
bogdanm	0:9b334a45a8ff	2518
bogdanm	0:9b334a45a8ff	2519	if(Timeout != HAL_MAX_DELAY)
bogdanm	0:9b334a45a8ff	2520	{
bogdanm	0:9b334a45a8ff	2521	if((Timeout == 0) \|\| ((HAL_GetTick()-tickstart) >= Timeout))
bogdanm	0:9b334a45a8ff	2522	{
bogdanm	0:9b334a45a8ff	2523	/* Disable the SPI and reset the CRC: the CRC value should be cleared
bogdanm	0:9b334a45a8ff	2524	on both master and slave sides in order to resynchronize the master
bogdanm	0:9b334a45a8ff	2525	and slave for their respective CRC calculation */
bogdanm	0:9b334a45a8ff	2526
bogdanm	0:9b334a45a8ff	2527	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
bogdanm	0:9b334a45a8ff	2528	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2529
bogdanm	0:9b334a45a8ff	2530	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	2531	{
bogdanm	0:9b334a45a8ff	2532	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	2533	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	2534	}
bogdanm	0:9b334a45a8ff	2535
bogdanm	0:9b334a45a8ff	2536	/* Reset CRC Calculation */
bogdanm	0:9b334a45a8ff	2537	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
bogdanm	0:9b334a45a8ff	2538	{
bogdanm	0:9b334a45a8ff	2539	SPI_RESET_CRC(hspi);
bogdanm	0:9b334a45a8ff	2540	}
bogdanm	0:9b334a45a8ff	2541
bogdanm	0:9b334a45a8ff	2542	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2543
bogdanm	0:9b334a45a8ff	2544	/* Process Unlocked */
bogdanm	0:9b334a45a8ff	2545	__HAL_UNLOCK(hspi);
bogdanm	0:9b334a45a8ff	2546
bogdanm	0:9b334a45a8ff	2547	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2548	}
bogdanm	0:9b334a45a8ff	2549	}
bogdanm	0:9b334a45a8ff	2550	}
bogdanm	0:9b334a45a8ff	2551
bogdanm	0:9b334a45a8ff	2552	return HAL_OK;
bogdanm	0:9b334a45a8ff	2553	}
bogdanm	0:9b334a45a8ff	2554
bogdanm	0:9b334a45a8ff	2555	/**
bogdanm	0:9b334a45a8ff	2556	* @brief This function handles the check of the RX transaction complete.
bogdanm	0:9b334a45a8ff	2557	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2558	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2559	* @param Timeout : Timeout duration
bogdanm	0:9b334a45a8ff	2560	* @retval None
bogdanm	0:9b334a45a8ff	2561	*/
bogdanm	0:9b334a45a8ff	2562	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	2563	{
bogdanm	0:9b334a45a8ff	2564	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
bogdanm	0:9b334a45a8ff	2565	{
bogdanm	0:9b334a45a8ff	2566	/* Disable SPI peripheral */
bogdanm	0:9b334a45a8ff	2567	__HAL_SPI_DISABLE(hspi);
bogdanm	0:9b334a45a8ff	2568	}
bogdanm	0:9b334a45a8ff	2569	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	2570	{
bogdanm	0:9b334a45a8ff	2571	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	2572	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2573	}
bogdanm	0:9b334a45a8ff	2574	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	2575	{
bogdanm	0:9b334a45a8ff	2576	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	2577	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2578	}
bogdanm	0:9b334a45a8ff	2579
bogdanm	0:9b334a45a8ff	2580	return HAL_OK;
bogdanm	0:9b334a45a8ff	2581	}
bogdanm	0:9b334a45a8ff	2582
bogdanm	0:9b334a45a8ff	2583	/**
bogdanm	0:9b334a45a8ff	2584	* @brief This function handles the check of the RXTX or TX transaction complete.
bogdanm	0:9b334a45a8ff	2585	* @param hspi: SPI handle
bogdanm	0:9b334a45a8ff	2586	* @param Timeout : Timeout duration
bogdanm	0:9b334a45a8ff	2587	*/
bogdanm	0:9b334a45a8ff	2588	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
bogdanm	0:9b334a45a8ff	2589	{
bogdanm	0:9b334a45a8ff	2590	/* Procedure to check the transaction complete */
bogdanm	0:9b334a45a8ff	2591	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	2592	{
bogdanm	0:9b334a45a8ff	2593	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	2594	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2595	}
bogdanm	0:9b334a45a8ff	2596	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	2597	{
bogdanm	0:9b334a45a8ff	2598	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	2599	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2600	}
bogdanm	0:9b334a45a8ff	2601	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
bogdanm	0:9b334a45a8ff	2602	{
bogdanm	0:9b334a45a8ff	2603	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
bogdanm	0:9b334a45a8ff	2604	return HAL_TIMEOUT;
bogdanm	0:9b334a45a8ff	2605	}
bogdanm	0:9b334a45a8ff	2606	return HAL_OK;
bogdanm	0:9b334a45a8ff	2607	}
bogdanm	0:9b334a45a8ff	2608
bogdanm	0:9b334a45a8ff	2609	/**
bogdanm	0:9b334a45a8ff	2610	* @brief This function handles the close of the RXTX transaction.
bogdanm	0:9b334a45a8ff	2611	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2612	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2613	* @retval None
bogdanm	0:9b334a45a8ff	2614	*/
bogdanm	0:9b334a45a8ff	2615	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2616	{
bogdanm	0:9b334a45a8ff	2617	/* Disable ERR interrupt */
bogdanm	0:9b334a45a8ff	2618	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
bogdanm	0:9b334a45a8ff	2619
bogdanm	0:9b334a45a8ff	2620	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	2621	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	2622	{
bogdanm	0:9b334a45a8ff	2623	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2624	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	2625	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2626	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2627	}
bogdanm	0:9b334a45a8ff	2628	else
bogdanm	0:9b334a45a8ff	2629	{
bogdanm	0:9b334a45a8ff	2630	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2631	{
bogdanm	0:9b334a45a8ff	2632	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
bogdanm	0:9b334a45a8ff	2633	{
bogdanm	0:9b334a45a8ff	2634	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2635	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2636	}
bogdanm	0:9b334a45a8ff	2637	else
bogdanm	0:9b334a45a8ff	2638	{
bogdanm	0:9b334a45a8ff	2639	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2640	HAL_SPI_TxRxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2641	}
bogdanm	0:9b334a45a8ff	2642	}
bogdanm	0:9b334a45a8ff	2643	else
bogdanm	0:9b334a45a8ff	2644	{
bogdanm	0:9b334a45a8ff	2645	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2646	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2647	}
bogdanm	0:9b334a45a8ff	2648	}
bogdanm	0:9b334a45a8ff	2649	}
bogdanm	0:9b334a45a8ff	2650
bogdanm	0:9b334a45a8ff	2651	/**
bogdanm	0:9b334a45a8ff	2652	* @brief This function handles the close of the RX transaction.
bogdanm	0:9b334a45a8ff	2653	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2654	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2655	* @retval None
bogdanm	0:9b334a45a8ff	2656	*/
bogdanm	0:9b334a45a8ff	2657	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2658	{
bogdanm	0:9b334a45a8ff	2659	/* Disable RXNE and ERR interrupt */
bogdanm	0:9b334a45a8ff	2660	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2661
bogdanm	0:9b334a45a8ff	2662	/* Check the end of the transaction */
bogdanm	0:9b334a45a8ff	2663	SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
bogdanm	0:9b334a45a8ff	2664
bogdanm	0:9b334a45a8ff	2665	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2666
bogdanm	0:9b334a45a8ff	2667	/* Check if CRC error occurred */
bogdanm	0:9b334a45a8ff	2668	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
bogdanm	0:9b334a45a8ff	2669	{
bogdanm	0:9b334a45a8ff	2670	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
bogdanm	0:9b334a45a8ff	2671	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2672	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2673	}
bogdanm	0:9b334a45a8ff	2674	else
bogdanm	0:9b334a45a8ff	2675	{
bogdanm	0:9b334a45a8ff	2676	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2677	{
bogdanm	0:9b334a45a8ff	2678	HAL_SPI_RxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2679	}
bogdanm	0:9b334a45a8ff	2680	else
bogdanm	0:9b334a45a8ff	2681	{
bogdanm	0:9b334a45a8ff	2682	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2683	}
bogdanm	0:9b334a45a8ff	2684	}
bogdanm	0:9b334a45a8ff	2685	}
bogdanm	0:9b334a45a8ff	2686
bogdanm	0:9b334a45a8ff	2687	/**
bogdanm	0:9b334a45a8ff	2688	* @brief This function handles the close of the TX transaction.
bogdanm	0:9b334a45a8ff	2689	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
bogdanm	0:9b334a45a8ff	2690	* the configuration information for SPI module.
bogdanm	0:9b334a45a8ff	2691	* @retval None
bogdanm	0:9b334a45a8ff	2692	*/
bogdanm	0:9b334a45a8ff	2693	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
bogdanm	0:9b334a45a8ff	2694	{
bogdanm	0:9b334a45a8ff	2695	/* Disable TXE and ERR interrupt */
bogdanm	0:9b334a45a8ff	2696	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
bogdanm	0:9b334a45a8ff	2697
bogdanm	0:9b334a45a8ff	2698	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
bogdanm	0:9b334a45a8ff	2699	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
bogdanm	0:9b334a45a8ff	2700	{
bogdanm	0:9b334a45a8ff	2701	__HAL_SPI_CLEAR_OVRFLAG(hspi);
bogdanm	0:9b334a45a8ff	2702	}
bogdanm	0:9b334a45a8ff	2703
bogdanm	0:9b334a45a8ff	2704	hspi->State = HAL_SPI_STATE_READY;
bogdanm	0:9b334a45a8ff	2705	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
bogdanm	0:9b334a45a8ff	2706	{
bogdanm	0:9b334a45a8ff	2707	HAL_SPI_ErrorCallback(hspi);
bogdanm	0:9b334a45a8ff	2708	}
bogdanm	0:9b334a45a8ff	2709	else
bogdanm	0:9b334a45a8ff	2710	{
bogdanm	0:9b334a45a8ff	2711	HAL_SPI_TxCpltCallback(hspi);
bogdanm	0:9b334a45a8ff	2712	}
bogdanm	0:9b334a45a8ff	2713	}
bogdanm	0:9b334a45a8ff	2714
bogdanm	0:9b334a45a8ff	2715	/**
bogdanm	0:9b334a45a8ff	2716	* @}
bogdanm	0:9b334a45a8ff	2717	*/
bogdanm	0:9b334a45a8ff	2718
bogdanm	0:9b334a45a8ff	2719	#endif /* HAL_SPI_MODULE_ENABLED */
bogdanm	0:9b334a45a8ff	2720	/**
bogdanm	0:9b334a45a8ff	2721	* @}
bogdanm	0:9b334a45a8ff	2722	*/
bogdanm	0:9b334a45a8ff	2723
bogdanm	0:9b334a45a8ff	2724	/**
bogdanm	0:9b334a45a8ff	2725	* @}
bogdanm	0:9b334a45a8ff	2726	*/
bogdanm	0:9b334a45a8ff	2727
bogdanm	0:9b334a45a8ff	2728	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	13 Apr 2017
Imports:	0
Forks:	0
Commits:	150
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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.c@0:9b334a45a8ff, 2015-10-01 (annotated)

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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.c@0:9b334a45a8ff, 2015-10-01 (annotated)

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