Jolyon Hill / mbed-dev

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Diff: targets/hal/TARGET_STM/TARGET_STM32L4/rtc_api.c

Revision:
103:173fc4c67e73
Parent:
71:a5b1c83f05dc
Child:
111:86e691153a57
--- a/targets/hal/TARGET_STM/TARGET_STM32L4/rtc_api.c	Wed Mar 30 13:00:10 2016 +0100
+++ b/targets/hal/TARGET_STM/TARGET_STM32L4/rtc_api.c	Fri Apr 01 17:45:12 2016 +0100
@@ -52,16 +52,6 @@
 
     RtcHandle.Instance = RTC;
 
-    // Enable Power clock
-    __HAL_RCC_PWR_CLK_ENABLE();
-
-    // Enable access to Backup domain
-    HAL_PWR_EnableBkUpAccess();
-
-    // Reset Backup domain
-    __HAL_RCC_BACKUPRESET_FORCE();
-    __HAL_RCC_BACKUPRESET_RELEASE();
-
 #if !DEVICE_RTC_LSI
     // Enable LSE Oscillator
     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
@@ -78,6 +68,16 @@
 	    error("Cannot initialize RTC with LSE\n");
     }
 #else	
+    // Enable Power clock
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    // Enable access to Backup domain
+    HAL_PWR_EnableBkUpAccess();
+
+    // Reset Backup domain
+    __HAL_RCC_BACKUPRESET_FORCE();
+    __HAL_RCC_BACKUPRESET_RELEASE();
+
 	// Enable LSI clock
 	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
 	RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
@@ -116,6 +116,7 @@
 
 void rtc_free(void)
 {
+#if DEVICE_RTC_LSI
     // Enable Power clock
     __HAL_RCC_PWR_CLK_ENABLE();
 
@@ -128,6 +129,7 @@
 
     // Disable access to Backup domain
     HAL_PWR_DisableBkUpAccess();
+#endif
 
     // Disable LSI and LSE clocks
     RCC_OscInitTypeDef RCC_OscInitStruct;