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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
83:a036322b8637 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f7xx_hal_flash_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.0
<> 144:ef7eb2e8f9f7 6 * @date 22-April-2016
<> 144:ef7eb2e8f9f7 7 * @brief Extended FLASH HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the FLASH extension peripheral:
<> 144:ef7eb2e8f9f7 10 * + Extended programming operations functions
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 @verbatim
<> 144:ef7eb2e8f9f7 13 ==============================================================================
<> 144:ef7eb2e8f9f7 14 ##### Flash Extension features #####
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16
<> 144:ef7eb2e8f9f7 17 [..] Comparing to other previous devices, the FLASH interface for STM32F76xx/STM32F77xx
<> 144:ef7eb2e8f9f7 18 devices contains the following additional features
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
<> 144:ef7eb2e8f9f7 21 capability (RWW)
<> 144:ef7eb2e8f9f7 22 (+) Dual bank memory organization
<> 144:ef7eb2e8f9f7 23 (+) Dual boot mode
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 26 ==============================================================================
<> 144:ef7eb2e8f9f7 27 [..] This driver provides functions to configure and program the FLASH memory
<> 144:ef7eb2e8f9f7 28 of all STM32F7xx devices. It includes
<> 144:ef7eb2e8f9f7 29 (#) FLASH Memory Erase functions:
<> 144:ef7eb2e8f9f7 30 (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
<> 144:ef7eb2e8f9f7 31 HAL_FLASH_Lock() functions
<> 144:ef7eb2e8f9f7 32 (++) Erase function: Erase sector, erase all sectors
<> 144:ef7eb2e8f9f7 33 (++) There are two modes of erase :
<> 144:ef7eb2e8f9f7 34 (+++) Polling Mode using HAL_FLASHEx_Erase()
<> 144:ef7eb2e8f9f7 35 (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :
<> 144:ef7eb2e8f9f7 38 (++) Set/Reset the write protection
<> 144:ef7eb2e8f9f7 39 (++) Set the Read protection Level
<> 144:ef7eb2e8f9f7 40 (++) Set the BOR level
<> 144:ef7eb2e8f9f7 41 (++) Program the user Option Bytes
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 @endverbatim
<> 144:ef7eb2e8f9f7 44 ******************************************************************************
<> 144:ef7eb2e8f9f7 45 * @attention
<> 144:ef7eb2e8f9f7 46 *
<> 144:ef7eb2e8f9f7 47 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 48 *
<> 144:ef7eb2e8f9f7 49 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 50 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 51 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 52 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 53 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 54 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 55 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 56 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 57 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 58 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 59 *
<> 144:ef7eb2e8f9f7 60 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 61 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 63 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 66 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 67 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 68 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 69 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 70 *
<> 144:ef7eb2e8f9f7 71 ******************************************************************************
<> 144:ef7eb2e8f9f7 72 */
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 75 #include "stm32f7xx_hal.h"
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /** @addtogroup STM32F7xx_HAL_Driver
<> 144:ef7eb2e8f9f7 78 * @{
<> 144:ef7eb2e8f9f7 79 */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /** @defgroup FLASHEx FLASHEx
<> 144:ef7eb2e8f9f7 82 * @brief FLASH HAL Extension module driver
<> 144:ef7eb2e8f9f7 83 * @{
<> 144:ef7eb2e8f9f7 84 */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 #ifdef HAL_FLASH_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 89 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 90 /** @addtogroup FLASHEx_Private_Constants
<> 144:ef7eb2e8f9f7 91 * @{
<> 144:ef7eb2e8f9f7 92 */
<> 144:ef7eb2e8f9f7 93 #define SECTOR_MASK ((uint32_t)0xFFFFFF07)
<> 144:ef7eb2e8f9f7 94 #define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
<> 144:ef7eb2e8f9f7 95 /**
<> 144:ef7eb2e8f9f7 96 * @}
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 100 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 101 /** @addtogroup FLASHEx_Private_Variables
<> 144:ef7eb2e8f9f7 102 * @{
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104 extern FLASH_ProcessTypeDef pFlash;
<> 144:ef7eb2e8f9f7 105 /**
<> 144:ef7eb2e8f9f7 106 * @}
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 110 /** @addtogroup FLASHEx_Private_Functions
<> 144:ef7eb2e8f9f7 111 * @{
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113 /* Option bytes control */
<> 144:ef7eb2e8f9f7 114 static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector);
<> 144:ef7eb2e8f9f7 115 static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector);
<> 144:ef7eb2e8f9f7 116 static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level);
<> 144:ef7eb2e8f9f7 117 static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level);
<> 144:ef7eb2e8f9f7 118 static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address);
<> 144:ef7eb2e8f9f7 119 static uint32_t FLASH_OB_GetUser(void);
<> 144:ef7eb2e8f9f7 120 static uint32_t FLASH_OB_GetWRP(void);
<> 144:ef7eb2e8f9f7 121 static uint8_t FLASH_OB_GetRDP(void);
<> 144:ef7eb2e8f9f7 122 static uint32_t FLASH_OB_GetBOR(void);
<> 144:ef7eb2e8f9f7 123 static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption);
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 #if defined (FLASH_OPTCR_nDBANK)
<> 144:ef7eb2e8f9f7 126 static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);
<> 144:ef7eb2e8f9f7 127 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \
<> 144:ef7eb2e8f9f7 128 uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot);
<> 144:ef7eb2e8f9f7 129 #else
<> 144:ef7eb2e8f9f7 130 static void FLASH_MassErase(uint8_t VoltageRange);
<> 144:ef7eb2e8f9f7 131 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby);
<> 144:ef7eb2e8f9f7 132 #endif /* FLASH_OPTCR_nDBANK */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
<> 144:ef7eb2e8f9f7 135 /**
<> 144:ef7eb2e8f9f7 136 * @}
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 140 /** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
<> 144:ef7eb2e8f9f7 141 * @{
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
<> 144:ef7eb2e8f9f7 145 * @brief Extended IO operation functions
<> 144:ef7eb2e8f9f7 146 *
<> 144:ef7eb2e8f9f7 147 @verbatim
<> 144:ef7eb2e8f9f7 148 ===============================================================================
<> 144:ef7eb2e8f9f7 149 ##### Extended programming operation functions #####
<> 144:ef7eb2e8f9f7 150 ===============================================================================
<> 144:ef7eb2e8f9f7 151 [..]
<> 144:ef7eb2e8f9f7 152 This subsection provides a set of functions allowing to manage the Extension FLASH
<> 144:ef7eb2e8f9f7 153 programming operations Operations.
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 @endverbatim
<> 144:ef7eb2e8f9f7 156 * @{
<> 144:ef7eb2e8f9f7 157 */
<> 144:ef7eb2e8f9f7 158 /**
<> 144:ef7eb2e8f9f7 159 * @brief Perform a mass erase or erase the specified FLASH memory sectors
<> 144:ef7eb2e8f9f7 160 * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
<> 144:ef7eb2e8f9f7 161 * contains the configuration information for the erasing.
<> 144:ef7eb2e8f9f7 162 *
<> 144:ef7eb2e8f9f7 163 * @param[out] SectorError: pointer to variable that
<> 144:ef7eb2e8f9f7 164 * contains the configuration information on faulty sector in case of error
<> 144:ef7eb2e8f9f7 165 * (0xFFFFFFFF means that all the sectors have been correctly erased)
<> 144:ef7eb2e8f9f7 166 *
<> 144:ef7eb2e8f9f7 167 * @retval HAL Status
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
<> 144:ef7eb2e8f9f7 170 {
<> 144:ef7eb2e8f9f7 171 HAL_StatusTypeDef status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 172 uint32_t index = 0;
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /* Process Locked */
<> 144:ef7eb2e8f9f7 175 __HAL_LOCK(&pFlash);
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 /* Check the parameters */
<> 144:ef7eb2e8f9f7 178 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 181 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 184 {
<> 144:ef7eb2e8f9f7 185 /*Initialization of SectorError variable*/
<> 144:ef7eb2e8f9f7 186 *SectorError = 0xFFFFFFFFU;
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
<> 144:ef7eb2e8f9f7 189 {
<> 144:ef7eb2e8f9f7 190 /*Mass erase to be done*/
<> 144:ef7eb2e8f9f7 191 #if defined (FLASH_OPTCR_nDBANK)
<> 144:ef7eb2e8f9f7 192 FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
<> 144:ef7eb2e8f9f7 193 #else
<> 144:ef7eb2e8f9f7 194 FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);
<> 144:ef7eb2e8f9f7 195 #endif /* FLASH_OPTCR_nDBANK */
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 198 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /* if the erase operation is completed, disable the MER Bit */
<> 144:ef7eb2e8f9f7 201 FLASH->CR &= (~FLASH_MER_BIT);
<> 144:ef7eb2e8f9f7 202 }
<> 144:ef7eb2e8f9f7 203 else
<> 144:ef7eb2e8f9f7 204 {
<> 144:ef7eb2e8f9f7 205 /* Check the parameters */
<> 144:ef7eb2e8f9f7 206 assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /* Erase by sector by sector to be done*/
<> 144:ef7eb2e8f9f7 209 for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)
<> 144:ef7eb2e8f9f7 210 {
<> 144:ef7eb2e8f9f7 211 FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 214 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /* If the erase operation is completed, disable the SER Bit and SNB Bits */
<> 144:ef7eb2e8f9f7 217 CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB));
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 if(status != HAL_OK)
<> 144:ef7eb2e8f9f7 220 {
<> 144:ef7eb2e8f9f7 221 /* In case of error, stop erase procedure and return the faulty sector*/
<> 144:ef7eb2e8f9f7 222 *SectorError = index;
<> 144:ef7eb2e8f9f7 223 break;
<> 144:ef7eb2e8f9f7 224 }
<> 144:ef7eb2e8f9f7 225 }
<> 144:ef7eb2e8f9f7 226 }
<> 144:ef7eb2e8f9f7 227 }
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 230 __HAL_UNLOCK(&pFlash);
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 return status;
<> 144:ef7eb2e8f9f7 233 }
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /**
<> 144:ef7eb2e8f9f7 236 * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled
<> 144:ef7eb2e8f9f7 237 * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
<> 144:ef7eb2e8f9f7 238 * contains the configuration information for the erasing.
<> 144:ef7eb2e8f9f7 239 *
<> 144:ef7eb2e8f9f7 240 * @retval HAL Status
<> 144:ef7eb2e8f9f7 241 */
<> 144:ef7eb2e8f9f7 242 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
<> 144:ef7eb2e8f9f7 243 {
<> 144:ef7eb2e8f9f7 244 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /* Process Locked */
<> 144:ef7eb2e8f9f7 247 __HAL_LOCK(&pFlash);
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /* Check the parameters */
<> 144:ef7eb2e8f9f7 250 assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /* Enable End of FLASH Operation interrupt */
<> 144:ef7eb2e8f9f7 253 __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /* Enable Error source interrupt */
<> 144:ef7eb2e8f9f7 256 __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /* Clear pending flags (if any) */
<> 144:ef7eb2e8f9f7 259 __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
<> 144:ef7eb2e8f9f7 260 FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR);
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
<> 144:ef7eb2e8f9f7 263 {
<> 144:ef7eb2e8f9f7 264 /*Mass erase to be done*/
<> 144:ef7eb2e8f9f7 265 pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
<> 144:ef7eb2e8f9f7 266 #if defined (FLASH_OPTCR_nDBANK)
<> 144:ef7eb2e8f9f7 267 FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
<> 144:ef7eb2e8f9f7 268 #else
<> 144:ef7eb2e8f9f7 269 FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);
<> 144:ef7eb2e8f9f7 270 #endif /* FLASH_OPTCR_nDBANK */
<> 144:ef7eb2e8f9f7 271 }
<> 144:ef7eb2e8f9f7 272 else
<> 144:ef7eb2e8f9f7 273 {
<> 144:ef7eb2e8f9f7 274 /* Erase by sector to be done*/
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /* Check the parameters */
<> 144:ef7eb2e8f9f7 277 assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;
<> 144:ef7eb2e8f9f7 280 pFlash.NbSectorsToErase = pEraseInit->NbSectors;
<> 144:ef7eb2e8f9f7 281 pFlash.Sector = pEraseInit->Sector;
<> 144:ef7eb2e8f9f7 282 pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /*Erase 1st sector and wait for IT*/
<> 144:ef7eb2e8f9f7 285 FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);
<> 144:ef7eb2e8f9f7 286 }
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 return status;
<> 144:ef7eb2e8f9f7 289 }
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /**
<> 144:ef7eb2e8f9f7 292 * @brief Program option bytes
<> 144:ef7eb2e8f9f7 293 * @param pOBInit: pointer to an FLASH_OBInitStruct structure that
<> 144:ef7eb2e8f9f7 294 * contains the configuration information for the programming.
<> 144:ef7eb2e8f9f7 295 *
<> 144:ef7eb2e8f9f7 296 * @retval HAL Status
<> 144:ef7eb2e8f9f7 297 */
<> 144:ef7eb2e8f9f7 298 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
<> 144:ef7eb2e8f9f7 299 {
<> 144:ef7eb2e8f9f7 300 HAL_StatusTypeDef status = HAL_ERROR;
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /* Process Locked */
<> 144:ef7eb2e8f9f7 303 __HAL_LOCK(&pFlash);
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /* Check the parameters */
<> 144:ef7eb2e8f9f7 306 assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /* Write protection configuration */
<> 144:ef7eb2e8f9f7 309 if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
<> 144:ef7eb2e8f9f7 310 {
<> 144:ef7eb2e8f9f7 311 assert_param(IS_WRPSTATE(pOBInit->WRPState));
<> 144:ef7eb2e8f9f7 312 if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)
<> 144:ef7eb2e8f9f7 313 {
<> 144:ef7eb2e8f9f7 314 /*Enable of Write protection on the selected Sector*/
<> 144:ef7eb2e8f9f7 315 status = FLASH_OB_EnableWRP(pOBInit->WRPSector);
<> 144:ef7eb2e8f9f7 316 }
<> 144:ef7eb2e8f9f7 317 else
<> 144:ef7eb2e8f9f7 318 {
<> 144:ef7eb2e8f9f7 319 /*Disable of Write protection on the selected Sector*/
<> 144:ef7eb2e8f9f7 320 status = FLASH_OB_DisableWRP(pOBInit->WRPSector);
<> 144:ef7eb2e8f9f7 321 }
<> 144:ef7eb2e8f9f7 322 }
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /* Read protection configuration */
<> 144:ef7eb2e8f9f7 325 if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
<> 144:ef7eb2e8f9f7 326 {
<> 144:ef7eb2e8f9f7 327 status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
<> 144:ef7eb2e8f9f7 328 }
<> 144:ef7eb2e8f9f7 329
<> 144:ef7eb2e8f9f7 330 /* USER configuration */
<> 144:ef7eb2e8f9f7 331 if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
<> 144:ef7eb2e8f9f7 332 {
<> 144:ef7eb2e8f9f7 333 #if defined (FLASH_OPTCR_nDBANK)
<> 144:ef7eb2e8f9f7 334 status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW,
<> 144:ef7eb2e8f9f7 335 pOBInit->USERConfig & OB_IWDG_SW,
<> 144:ef7eb2e8f9f7 336 pOBInit->USERConfig & OB_STOP_NO_RST,
<> 144:ef7eb2e8f9f7 337 pOBInit->USERConfig & OB_STDBY_NO_RST,
<> 144:ef7eb2e8f9f7 338 pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,
<> 144:ef7eb2e8f9f7 339 pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE,
<> 144:ef7eb2e8f9f7 340 pOBInit->USERConfig & OB_NDBANK_SINGLE_BANK,
<> 144:ef7eb2e8f9f7 341 pOBInit->USERConfig & OB_DUAL_BOOT_DISABLE);
<> 144:ef7eb2e8f9f7 342 #else
<> 144:ef7eb2e8f9f7 343 status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW,
<> 144:ef7eb2e8f9f7 344 pOBInit->USERConfig & OB_IWDG_SW,
<> 144:ef7eb2e8f9f7 345 pOBInit->USERConfig & OB_STOP_NO_RST,
<> 144:ef7eb2e8f9f7 346 pOBInit->USERConfig & OB_STDBY_NO_RST,
<> 144:ef7eb2e8f9f7 347 pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,
<> 144:ef7eb2e8f9f7 348 pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE);
<> 144:ef7eb2e8f9f7 349 #endif /* FLASH_OPTCR_nDBANK */
<> 144:ef7eb2e8f9f7 350 }
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /* BOR Level configuration */
<> 144:ef7eb2e8f9f7 353 if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
<> 144:ef7eb2e8f9f7 354 {
<> 144:ef7eb2e8f9f7 355 status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
<> 144:ef7eb2e8f9f7 356 }
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /* Boot 0 Address configuration */
<> 144:ef7eb2e8f9f7 359 if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_0) == OPTIONBYTE_BOOTADDR_0)
<> 144:ef7eb2e8f9f7 360 {
<> 144:ef7eb2e8f9f7 361 status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_0, pOBInit->BootAddr0);
<> 144:ef7eb2e8f9f7 362 }
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /* Boot 1 Address configuration */
<> 144:ef7eb2e8f9f7 365 if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_1) == OPTIONBYTE_BOOTADDR_1)
<> 144:ef7eb2e8f9f7 366 {
<> 144:ef7eb2e8f9f7 367 status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_1, pOBInit->BootAddr1);
<> 144:ef7eb2e8f9f7 368 }
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 371 __HAL_UNLOCK(&pFlash);
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 return status;
<> 144:ef7eb2e8f9f7 374 }
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /**
<> 144:ef7eb2e8f9f7 377 * @brief Get the Option byte configuration
<> 144:ef7eb2e8f9f7 378 * @param pOBInit: pointer to an FLASH_OBInitStruct structure that
<> 144:ef7eb2e8f9f7 379 * contains the configuration information for the programming.
<> 144:ef7eb2e8f9f7 380 *
<> 144:ef7eb2e8f9f7 381 * @retval None
<> 144:ef7eb2e8f9f7 382 */
<> 144:ef7eb2e8f9f7 383 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
<> 144:ef7eb2e8f9f7 384 {
<> 144:ef7eb2e8f9f7 385 pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
<> 144:ef7eb2e8f9f7 386 OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1;
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /*Get WRP*/
<> 144:ef7eb2e8f9f7 389 pOBInit->WRPSector = FLASH_OB_GetWRP();
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /*Get RDP Level*/
<> 144:ef7eb2e8f9f7 392 pOBInit->RDPLevel = FLASH_OB_GetRDP();
<> 144:ef7eb2e8f9f7 393
<> 144:ef7eb2e8f9f7 394 /*Get USER*/
<> 144:ef7eb2e8f9f7 395 pOBInit->USERConfig = FLASH_OB_GetUser();
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /*Get BOR Level*/
<> 144:ef7eb2e8f9f7 398 pOBInit->BORLevel = FLASH_OB_GetBOR();
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 /*Get Boot Address when Boot pin = 0 */
<> 144:ef7eb2e8f9f7 401 pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0);
<> 144:ef7eb2e8f9f7 402
<> 144:ef7eb2e8f9f7 403 /*Get Boot Address when Boot pin = 1 */
<> 144:ef7eb2e8f9f7 404 pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1);
<> 144:ef7eb2e8f9f7 405 }
<> 144:ef7eb2e8f9f7 406 /**
<> 144:ef7eb2e8f9f7 407 * @}
<> 144:ef7eb2e8f9f7 408 */
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 #if defined (FLASH_OPTCR_nDBANK)
<> 144:ef7eb2e8f9f7 411 /**
<> 144:ef7eb2e8f9f7 412 * @brief Full erase of FLASH memory sectors
<> 144:ef7eb2e8f9f7 413 * @param VoltageRange: The device voltage range which defines the erase parallelism.
<> 144:ef7eb2e8f9f7 414 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 415 * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
<> 144:ef7eb2e8f9f7 416 * the operation will be done by byte (8-bit)
<> 144:ef7eb2e8f9f7 417 * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
<> 144:ef7eb2e8f9f7 418 * the operation will be done by half word (16-bit)
<> 144:ef7eb2e8f9f7 419 * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
<> 144:ef7eb2e8f9f7 420 * the operation will be done by word (32-bit)
<> 144:ef7eb2e8f9f7 421 * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
<> 144:ef7eb2e8f9f7 422 * the operation will be done by double word (64-bit)
<> 144:ef7eb2e8f9f7 423 * @param Banks: Banks to be erased
<> 144:ef7eb2e8f9f7 424 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 425 * @arg FLASH_BANK_1: Bank1 to be erased
<> 144:ef7eb2e8f9f7 426 * @arg FLASH_BANK_2: Bank2 to be erased
<> 144:ef7eb2e8f9f7 427 * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
<> 144:ef7eb2e8f9f7 428 *
<> 144:ef7eb2e8f9f7 429 * @retval HAL Status
<> 144:ef7eb2e8f9f7 430 */
<> 144:ef7eb2e8f9f7 431 static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
<> 144:ef7eb2e8f9f7 432 {
<> 144:ef7eb2e8f9f7 433 /* Check the parameters */
<> 144:ef7eb2e8f9f7 434 assert_param(IS_VOLTAGERANGE(VoltageRange));
<> 144:ef7eb2e8f9f7 435 assert_param(IS_FLASH_BANK(Banks));
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 /* if the previous operation is completed, proceed to erase all sectors */
<> 144:ef7eb2e8f9f7 438 FLASH->CR &= CR_PSIZE_MASK;
<> 144:ef7eb2e8f9f7 439 if(Banks == FLASH_BANK_BOTH)
<> 144:ef7eb2e8f9f7 440 {
<> 144:ef7eb2e8f9f7 441 /* bank1 & bank2 will be erased*/
<> 144:ef7eb2e8f9f7 442 FLASH->CR |= FLASH_MER_BIT;
<> 144:ef7eb2e8f9f7 443 }
<> 144:ef7eb2e8f9f7 444 else if(Banks == FLASH_BANK_2)
<> 144:ef7eb2e8f9f7 445 {
<> 144:ef7eb2e8f9f7 446 /*Only bank2 will be erased*/
<> 144:ef7eb2e8f9f7 447 FLASH->CR |= FLASH_CR_MER2;
<> 144:ef7eb2e8f9f7 448 }
<> 144:ef7eb2e8f9f7 449 else
<> 144:ef7eb2e8f9f7 450 {
<> 144:ef7eb2e8f9f7 451 /*Only bank1 will be erased*/
<> 144:ef7eb2e8f9f7 452 FLASH->CR |= FLASH_CR_MER1;
<> 144:ef7eb2e8f9f7 453 }
<> 144:ef7eb2e8f9f7 454 FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);
<> 144:ef7eb2e8f9f7 455 /* Data synchronous Barrier (DSB) Just after the write operation
<> 144:ef7eb2e8f9f7 456 This will force the CPU to respect the sequence of instruction (no optimization).*/
<> 144:ef7eb2e8f9f7 457 __DSB();
<> 144:ef7eb2e8f9f7 458 }
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /**
<> 144:ef7eb2e8f9f7 461 * @brief Erase the specified FLASH memory sector
<> 144:ef7eb2e8f9f7 462 * @param Sector: FLASH sector to erase
<> 144:ef7eb2e8f9f7 463 * The value of this parameter depend on device used within the same series
<> 144:ef7eb2e8f9f7 464 * @param VoltageRange: The device voltage range which defines the erase parallelism.
<> 144:ef7eb2e8f9f7 465 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 466 * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
<> 144:ef7eb2e8f9f7 467 * the operation will be done by byte (8-bit)
<> 144:ef7eb2e8f9f7 468 * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
<> 144:ef7eb2e8f9f7 469 * the operation will be done by half word (16-bit)
<> 144:ef7eb2e8f9f7 470 * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
<> 144:ef7eb2e8f9f7 471 * the operation will be done by word (32-bit)
<> 144:ef7eb2e8f9f7 472 * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
<> 144:ef7eb2e8f9f7 473 * the operation will be done by double word (64-bit)
<> 144:ef7eb2e8f9f7 474 *
<> 144:ef7eb2e8f9f7 475 * @retval None
<> 144:ef7eb2e8f9f7 476 */
<> 144:ef7eb2e8f9f7 477 void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
<> 144:ef7eb2e8f9f7 478 {
<> 144:ef7eb2e8f9f7 479 uint32_t tmp_psize = 0;
<> 144:ef7eb2e8f9f7 480
<> 144:ef7eb2e8f9f7 481 /* Check the parameters */
<> 144:ef7eb2e8f9f7 482 assert_param(IS_FLASH_SECTOR(Sector));
<> 144:ef7eb2e8f9f7 483 assert_param(IS_VOLTAGERANGE(VoltageRange));
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
<> 144:ef7eb2e8f9f7 486 {
<> 144:ef7eb2e8f9f7 487 tmp_psize = FLASH_PSIZE_BYTE;
<> 144:ef7eb2e8f9f7 488 }
<> 144:ef7eb2e8f9f7 489 else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
<> 144:ef7eb2e8f9f7 490 {
<> 144:ef7eb2e8f9f7 491 tmp_psize = FLASH_PSIZE_HALF_WORD;
<> 144:ef7eb2e8f9f7 492 }
<> 144:ef7eb2e8f9f7 493 else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
<> 144:ef7eb2e8f9f7 494 {
<> 144:ef7eb2e8f9f7 495 tmp_psize = FLASH_PSIZE_WORD;
<> 144:ef7eb2e8f9f7 496 }
<> 144:ef7eb2e8f9f7 497 else
<> 144:ef7eb2e8f9f7 498 {
<> 144:ef7eb2e8f9f7 499 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
<> 144:ef7eb2e8f9f7 500 }
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */
<> 144:ef7eb2e8f9f7 503 if(Sector > FLASH_SECTOR_11)
<> 144:ef7eb2e8f9f7 504 {
<> 144:ef7eb2e8f9f7 505 Sector += 4;
<> 144:ef7eb2e8f9f7 506 }
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /* If the previous operation is completed, proceed to erase the sector */
<> 144:ef7eb2e8f9f7 509 FLASH->CR &= CR_PSIZE_MASK;
<> 144:ef7eb2e8f9f7 510 FLASH->CR |= tmp_psize;
<> 144:ef7eb2e8f9f7 511 CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
<> 144:ef7eb2e8f9f7 512 FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
<> 144:ef7eb2e8f9f7 513 FLASH->CR |= FLASH_CR_STRT;
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 /* Data synchronous Barrier (DSB) Just after the write operation
<> 144:ef7eb2e8f9f7 516 This will force the CPU to respect the sequence of instruction (no optimization).*/
<> 144:ef7eb2e8f9f7 517 __DSB();
<> 144:ef7eb2e8f9f7 518 }
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 /**
<> 144:ef7eb2e8f9f7 521 * @brief Return the FLASH Write Protection Option Bytes value.
<> 144:ef7eb2e8f9f7 522 * @retval uint32_t FLASH Write Protection Option Bytes value
<> 144:ef7eb2e8f9f7 523 */
<> 144:ef7eb2e8f9f7 524 static uint32_t FLASH_OB_GetWRP(void)
<> 144:ef7eb2e8f9f7 525 {
<> 144:ef7eb2e8f9f7 526 /* Return the FLASH write protection Register value */
<> 144:ef7eb2e8f9f7 527 return ((uint32_t)(FLASH->OPTCR & 0x0FFF0000));
<> 144:ef7eb2e8f9f7 528 }
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /**
<> 144:ef7eb2e8f9f7 531 * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
<> 144:ef7eb2e8f9f7 532 * @param Wwdg: Selects the IWDG mode
<> 144:ef7eb2e8f9f7 533 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 534 * @arg OB_WWDG_SW: Software WWDG selected
<> 144:ef7eb2e8f9f7 535 * @arg OB_WWDG_HW: Hardware WWDG selected
<> 144:ef7eb2e8f9f7 536 * @param Iwdg: Selects the WWDG mode
<> 144:ef7eb2e8f9f7 537 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 538 * @arg OB_IWDG_SW: Software IWDG selected
<> 144:ef7eb2e8f9f7 539 * @arg OB_IWDG_HW: Hardware IWDG selected
<> 144:ef7eb2e8f9f7 540 * @param Stop: Reset event when entering STOP mode.
<> 144:ef7eb2e8f9f7 541 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 542 * @arg OB_STOP_NO_RST: No reset generated when entering in STOP
<> 144:ef7eb2e8f9f7 543 * @arg OB_STOP_RST: Reset generated when entering in STOP
<> 144:ef7eb2e8f9f7 544 * @param Stdby: Reset event when entering Standby mode.
<> 144:ef7eb2e8f9f7 545 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 546 * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
<> 144:ef7eb2e8f9f7 547 * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
<> 144:ef7eb2e8f9f7 548 * @param Iwdgstop: Independent watchdog counter freeze in Stop mode.
<> 144:ef7eb2e8f9f7 549 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 550 * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP
<> 144:ef7eb2e8f9f7 551 * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP
<> 144:ef7eb2e8f9f7 552 * @param Iwdgstdby: Independent watchdog counter freeze in standby mode.
<> 144:ef7eb2e8f9f7 553 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 554 * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY
<> 144:ef7eb2e8f9f7 555 * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY
<> 144:ef7eb2e8f9f7 556 * @param NDBank: Flash Single Bank mode enabled.
<> 144:ef7eb2e8f9f7 557 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 558 * @arg OB_NDBANK_SINGLE_BANK: enable 256 bits mode (Flash is a single bank)
<> 144:ef7eb2e8f9f7 559 * @arg OB_NDBANK_DUAL_BANK: disable 256 bits mode (Flash is a dual bank in 128 bits mode)
<> 144:ef7eb2e8f9f7 560 * @param NDBoot: Flash Dual boot mode disable.
<> 144:ef7eb2e8f9f7 561 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 562 * @arg OB_DUAL_BOOT_DISABLE: Disable Dual Boot
<> 144:ef7eb2e8f9f7 563 * @arg OB_DUAL_BOOT_ENABLE: Enable Dual Boot
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 * @retval HAL Status
<> 144:ef7eb2e8f9f7 566 */
<> 144:ef7eb2e8f9f7 567 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \
<> 144:ef7eb2e8f9f7 568 uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot)
<> 144:ef7eb2e8f9f7 569 {
<> 144:ef7eb2e8f9f7 570 uint32_t useroptionmask = 0x00;
<> 144:ef7eb2e8f9f7 571 uint32_t useroptionvalue = 0x00;
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 /* Check the parameters */
<> 144:ef7eb2e8f9f7 576 assert_param(IS_OB_WWDG_SOURCE(Wwdg));
<> 144:ef7eb2e8f9f7 577 assert_param(IS_OB_IWDG_SOURCE(Iwdg));
<> 144:ef7eb2e8f9f7 578 assert_param(IS_OB_STOP_SOURCE(Stop));
<> 144:ef7eb2e8f9f7 579 assert_param(IS_OB_STDBY_SOURCE(Stdby));
<> 144:ef7eb2e8f9f7 580 assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));
<> 144:ef7eb2e8f9f7 581 assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));
<> 144:ef7eb2e8f9f7 582 assert_param(IS_OB_NDBANK(NDBank));
<> 144:ef7eb2e8f9f7 583 assert_param(IS_OB_NDBOOT(NDBoot));
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 586 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 589 {
<> 144:ef7eb2e8f9f7 590 useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \
<> 144:ef7eb2e8f9f7 591 FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY | \
<> 144:ef7eb2e8f9f7 592 FLASH_OPTCR_nDBOOT | FLASH_OPTCR_nDBANK);
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby | NDBoot | NDBank);
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /* Update User Option Byte */
<> 144:ef7eb2e8f9f7 597 MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);
<> 144:ef7eb2e8f9f7 598 }
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 return status;
<> 144:ef7eb2e8f9f7 601 }
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /**
<> 144:ef7eb2e8f9f7 604 * @brief Return the FLASH User Option Byte value.
<> 144:ef7eb2e8f9f7 605 * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6),
<> 144:ef7eb2e8f9f7 606 * nRST_STDBY(Bit7), nDBOOT(Bit28), nDBANK(Bit29), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).
<> 144:ef7eb2e8f9f7 607 */
<> 144:ef7eb2e8f9f7 608 static uint32_t FLASH_OB_GetUser(void)
<> 144:ef7eb2e8f9f7 609 {
<> 144:ef7eb2e8f9f7 610 /* Return the User Option Byte */
<> 144:ef7eb2e8f9f7 611 return ((uint32_t)(FLASH->OPTCR & 0xF00000F0U));
<> 144:ef7eb2e8f9f7 612 }
<> 144:ef7eb2e8f9f7 613 #else
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 /**
<> 144:ef7eb2e8f9f7 616 * @brief Full erase of FLASH memory sectors
<> 144:ef7eb2e8f9f7 617 * @param VoltageRange: The device voltage range which defines the erase parallelism.
<> 144:ef7eb2e8f9f7 618 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 619 * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
<> 144:ef7eb2e8f9f7 620 * the operation will be done by byte (8-bit)
<> 144:ef7eb2e8f9f7 621 * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
<> 144:ef7eb2e8f9f7 622 * the operation will be done by half word (16-bit)
<> 144:ef7eb2e8f9f7 623 * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
<> 144:ef7eb2e8f9f7 624 * the operation will be done by word (32-bit)
<> 144:ef7eb2e8f9f7 625 * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
<> 144:ef7eb2e8f9f7 626 * the operation will be done by double word (64-bit)
<> 144:ef7eb2e8f9f7 627 *
<> 144:ef7eb2e8f9f7 628 * @retval HAL Status
<> 144:ef7eb2e8f9f7 629 */
<> 144:ef7eb2e8f9f7 630 static void FLASH_MassErase(uint8_t VoltageRange)
<> 144:ef7eb2e8f9f7 631 {
<> 144:ef7eb2e8f9f7 632 /* Check the parameters */
<> 144:ef7eb2e8f9f7 633 assert_param(IS_VOLTAGERANGE(VoltageRange));
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /* if the previous operation is completed, proceed to erase all sectors */
<> 144:ef7eb2e8f9f7 636 FLASH->CR &= CR_PSIZE_MASK;
<> 144:ef7eb2e8f9f7 637 FLASH->CR |= FLASH_CR_MER;
<> 144:ef7eb2e8f9f7 638 FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);
<> 144:ef7eb2e8f9f7 639 /* Data synchronous Barrier (DSB) Just after the write operation
<> 144:ef7eb2e8f9f7 640 This will force the CPU to respect the sequence of instruction (no optimization).*/
<> 144:ef7eb2e8f9f7 641 __DSB();
<> 144:ef7eb2e8f9f7 642 }
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 /**
<> 144:ef7eb2e8f9f7 645 * @brief Erase the specified FLASH memory sector
<> 144:ef7eb2e8f9f7 646 * @param Sector: FLASH sector to erase
<> 144:ef7eb2e8f9f7 647 * The value of this parameter depend on device used within the same series
<> 144:ef7eb2e8f9f7 648 * @param VoltageRange: The device voltage range which defines the erase parallelism.
<> 144:ef7eb2e8f9f7 649 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 650 * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
<> 144:ef7eb2e8f9f7 651 * the operation will be done by byte (8-bit)
<> 144:ef7eb2e8f9f7 652 * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
<> 144:ef7eb2e8f9f7 653 * the operation will be done by half word (16-bit)
<> 144:ef7eb2e8f9f7 654 * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
<> 144:ef7eb2e8f9f7 655 * the operation will be done by word (32-bit)
<> 144:ef7eb2e8f9f7 656 * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
<> 144:ef7eb2e8f9f7 657 * the operation will be done by double word (64-bit)
<> 144:ef7eb2e8f9f7 658 *
<> 144:ef7eb2e8f9f7 659 * @retval None
<> 144:ef7eb2e8f9f7 660 */
<> 144:ef7eb2e8f9f7 661 void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
<> 144:ef7eb2e8f9f7 662 {
<> 144:ef7eb2e8f9f7 663 uint32_t tmp_psize = 0;
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 /* Check the parameters */
<> 144:ef7eb2e8f9f7 666 assert_param(IS_FLASH_SECTOR(Sector));
<> 144:ef7eb2e8f9f7 667 assert_param(IS_VOLTAGERANGE(VoltageRange));
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
<> 144:ef7eb2e8f9f7 670 {
<> 144:ef7eb2e8f9f7 671 tmp_psize = FLASH_PSIZE_BYTE;
<> 144:ef7eb2e8f9f7 672 }
<> 144:ef7eb2e8f9f7 673 else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
<> 144:ef7eb2e8f9f7 674 {
<> 144:ef7eb2e8f9f7 675 tmp_psize = FLASH_PSIZE_HALF_WORD;
<> 144:ef7eb2e8f9f7 676 }
<> 144:ef7eb2e8f9f7 677 else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
<> 144:ef7eb2e8f9f7 678 {
<> 144:ef7eb2e8f9f7 679 tmp_psize = FLASH_PSIZE_WORD;
<> 144:ef7eb2e8f9f7 680 }
<> 144:ef7eb2e8f9f7 681 else
<> 144:ef7eb2e8f9f7 682 {
<> 144:ef7eb2e8f9f7 683 tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
<> 144:ef7eb2e8f9f7 684 }
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 /* If the previous operation is completed, proceed to erase the sector */
<> 144:ef7eb2e8f9f7 687 FLASH->CR &= CR_PSIZE_MASK;
<> 144:ef7eb2e8f9f7 688 FLASH->CR |= tmp_psize;
<> 144:ef7eb2e8f9f7 689 FLASH->CR &= SECTOR_MASK;
<> 144:ef7eb2e8f9f7 690 FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
<> 144:ef7eb2e8f9f7 691 FLASH->CR |= FLASH_CR_STRT;
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693 /* Data synchronous Barrier (DSB) Just after the write operation
<> 144:ef7eb2e8f9f7 694 This will force the CPU to respect the sequence of instruction (no optimization).*/
<> 144:ef7eb2e8f9f7 695 __DSB();
<> 144:ef7eb2e8f9f7 696 }
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 /**
<> 144:ef7eb2e8f9f7 699 * @brief Return the FLASH Write Protection Option Bytes value.
<> 144:ef7eb2e8f9f7 700 * @retval uint32_t FLASH Write Protection Option Bytes value
<> 144:ef7eb2e8f9f7 701 */
<> 144:ef7eb2e8f9f7 702 static uint32_t FLASH_OB_GetWRP(void)
<> 144:ef7eb2e8f9f7 703 {
<> 144:ef7eb2e8f9f7 704 /* Return the FLASH write protection Register value */
<> 144:ef7eb2e8f9f7 705 return ((uint32_t)(FLASH->OPTCR & 0x00FF0000));
<> 144:ef7eb2e8f9f7 706 }
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 /**
<> 144:ef7eb2e8f9f7 709 * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
<> 144:ef7eb2e8f9f7 710 * @param Wwdg: Selects the IWDG mode
<> 144:ef7eb2e8f9f7 711 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 712 * @arg OB_WWDG_SW: Software WWDG selected
<> 144:ef7eb2e8f9f7 713 * @arg OB_WWDG_HW: Hardware WWDG selected
<> 144:ef7eb2e8f9f7 714 * @param Iwdg: Selects the WWDG mode
<> 144:ef7eb2e8f9f7 715 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 716 * @arg OB_IWDG_SW: Software IWDG selected
<> 144:ef7eb2e8f9f7 717 * @arg OB_IWDG_HW: Hardware IWDG selected
<> 144:ef7eb2e8f9f7 718 * @param Stop: Reset event when entering STOP mode.
<> 144:ef7eb2e8f9f7 719 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 720 * @arg OB_STOP_NO_RST: No reset generated when entering in STOP
<> 144:ef7eb2e8f9f7 721 * @arg OB_STOP_RST: Reset generated when entering in STOP
<> 144:ef7eb2e8f9f7 722 * @param Stdby: Reset event when entering Standby mode.
<> 144:ef7eb2e8f9f7 723 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 724 * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
<> 144:ef7eb2e8f9f7 725 * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
<> 144:ef7eb2e8f9f7 726 * @param Iwdgstop: Independent watchdog counter freeze in Stop mode.
<> 144:ef7eb2e8f9f7 727 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 728 * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP
<> 144:ef7eb2e8f9f7 729 * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP
<> 144:ef7eb2e8f9f7 730 * @param Iwdgstdby: Independent watchdog counter freeze in standby mode.
<> 144:ef7eb2e8f9f7 731 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 732 * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY
<> 144:ef7eb2e8f9f7 733 * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY
<> 144:ef7eb2e8f9f7 734 * @retval HAL Status
<> 144:ef7eb2e8f9f7 735 */
<> 144:ef7eb2e8f9f7 736 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby)
<> 144:ef7eb2e8f9f7 737 {
<> 144:ef7eb2e8f9f7 738 uint32_t useroptionmask = 0x00;
<> 144:ef7eb2e8f9f7 739 uint32_t useroptionvalue = 0x00;
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 /* Check the parameters */
<> 144:ef7eb2e8f9f7 744 assert_param(IS_OB_WWDG_SOURCE(Wwdg));
<> 144:ef7eb2e8f9f7 745 assert_param(IS_OB_IWDG_SOURCE(Iwdg));
<> 144:ef7eb2e8f9f7 746 assert_param(IS_OB_STOP_SOURCE(Stop));
<> 144:ef7eb2e8f9f7 747 assert_param(IS_OB_STDBY_SOURCE(Stdby));
<> 144:ef7eb2e8f9f7 748 assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));
<> 144:ef7eb2e8f9f7 749 assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 752 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 755 {
<> 144:ef7eb2e8f9f7 756 useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \
<> 144:ef7eb2e8f9f7 757 FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY);
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby);
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 /* Update User Option Byte */
<> 144:ef7eb2e8f9f7 762 MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);
<> 144:ef7eb2e8f9f7 763 }
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 return status;
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 }
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /**
<> 144:ef7eb2e8f9f7 770 * @brief Return the FLASH User Option Byte value.
<> 144:ef7eb2e8f9f7 771 * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6),
<> 144:ef7eb2e8f9f7 772 * nRST_STDBY(Bit7), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).
<> 144:ef7eb2e8f9f7 773 */
<> 144:ef7eb2e8f9f7 774 static uint32_t FLASH_OB_GetUser(void)
<> 144:ef7eb2e8f9f7 775 {
<> 144:ef7eb2e8f9f7 776 /* Return the User Option Byte */
<> 144:ef7eb2e8f9f7 777 return ((uint32_t)(FLASH->OPTCR & 0xC00000F0));
<> 144:ef7eb2e8f9f7 778 }
<> 144:ef7eb2e8f9f7 779 #endif /* FLASH_OPTCR_nDBANK */
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781 /**
<> 144:ef7eb2e8f9f7 782 * @brief Enable the write protection of the desired bank1 or bank2 sectors
<> 144:ef7eb2e8f9f7 783 *
<> 144:ef7eb2e8f9f7 784 * @note When the memory read protection level is selected (RDP level = 1),
<> 144:ef7eb2e8f9f7 785 * it is not possible to program or erase the flash sector i if CortexM7
<> 144:ef7eb2e8f9f7 786 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
<> 144:ef7eb2e8f9f7 787 *
<> 144:ef7eb2e8f9f7 788 * @param WRPSector: specifies the sector(s) to be write protected.
<> 144:ef7eb2e8f9f7 789 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 790 * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices)
<> 144:ef7eb2e8f9f7 791 * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices)
<> 144:ef7eb2e8f9f7 792 * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices)
<> 144:ef7eb2e8f9f7 793 * @arg OB_WRP_SECTOR_All
<> 144:ef7eb2e8f9f7 794 *
<> 144:ef7eb2e8f9f7 795 * @retval HAL FLASH State
<> 144:ef7eb2e8f9f7 796 */
<> 144:ef7eb2e8f9f7 797 static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector)
<> 144:ef7eb2e8f9f7 798 {
<> 144:ef7eb2e8f9f7 799 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 800
<> 144:ef7eb2e8f9f7 801 /* Check the parameters */
<> 144:ef7eb2e8f9f7 802 assert_param(IS_OB_WRP_SECTOR(WRPSector));
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 805 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 808 {
<> 144:ef7eb2e8f9f7 809 /*Write protection enabled on sectors */
<> 144:ef7eb2e8f9f7 810 FLASH->OPTCR &= (~WRPSector);
<> 144:ef7eb2e8f9f7 811 }
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 return status;
<> 144:ef7eb2e8f9f7 814 }
<> 144:ef7eb2e8f9f7 815
<> 144:ef7eb2e8f9f7 816 /**
<> 144:ef7eb2e8f9f7 817 * @brief Disable the write protection of the desired bank1 or bank 2 sectors
<> 144:ef7eb2e8f9f7 818 *
<> 144:ef7eb2e8f9f7 819 * @note When the memory read protection level is selected (RDP level = 1),
<> 144:ef7eb2e8f9f7 820 * it is not possible to program or erase the flash sector i if CortexM4
<> 144:ef7eb2e8f9f7 821 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1
<> 144:ef7eb2e8f9f7 822 *
<> 144:ef7eb2e8f9f7 823 * @param WRPSector: specifies the sector(s) to be write protected.
<> 144:ef7eb2e8f9f7 824 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 825 * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices)
<> 144:ef7eb2e8f9f7 826 * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices)
<> 144:ef7eb2e8f9f7 827 * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices)
<> 144:ef7eb2e8f9f7 828 * @arg OB_WRP_Sector_All
<> 144:ef7eb2e8f9f7 829 *
<> 144:ef7eb2e8f9f7 830 *
<> 144:ef7eb2e8f9f7 831 * @retval HAL Status
<> 144:ef7eb2e8f9f7 832 */
<> 144:ef7eb2e8f9f7 833 static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)
<> 144:ef7eb2e8f9f7 834 {
<> 144:ef7eb2e8f9f7 835 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837 /* Check the parameters */
<> 144:ef7eb2e8f9f7 838 assert_param(IS_OB_WRP_SECTOR(WRPSector));
<> 144:ef7eb2e8f9f7 839
<> 144:ef7eb2e8f9f7 840 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 841 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 844 {
<> 144:ef7eb2e8f9f7 845 /* Write protection disabled on sectors */
<> 144:ef7eb2e8f9f7 846 FLASH->OPTCR |= (WRPSector);
<> 144:ef7eb2e8f9f7 847 }
<> 144:ef7eb2e8f9f7 848
<> 144:ef7eb2e8f9f7 849 return status;
<> 144:ef7eb2e8f9f7 850 }
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 /**
<> 144:ef7eb2e8f9f7 853 * @brief Set the read protection level.
<> 144:ef7eb2e8f9f7 854 * @param Level: specifies the read protection level.
<> 144:ef7eb2e8f9f7 855 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 856 * @arg OB_RDP_LEVEL_0: No protection
<> 144:ef7eb2e8f9f7 857 * @arg OB_RDP_LEVEL_1: Read protection of the memory
<> 144:ef7eb2e8f9f7 858 * @arg OB_RDP_LEVEL_2: Full chip protection
<> 144:ef7eb2e8f9f7 859 *
<> 144:ef7eb2e8f9f7 860 * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
<> 144:ef7eb2e8f9f7 861 *
<> 144:ef7eb2e8f9f7 862 * @retval HAL Status
<> 144:ef7eb2e8f9f7 863 */
<> 144:ef7eb2e8f9f7 864 static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
<> 144:ef7eb2e8f9f7 865 {
<> 144:ef7eb2e8f9f7 866 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 /* Check the parameters */
<> 144:ef7eb2e8f9f7 869 assert_param(IS_OB_RDP_LEVEL(Level));
<> 144:ef7eb2e8f9f7 870
<> 144:ef7eb2e8f9f7 871 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 872 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 875 {
<> 144:ef7eb2e8f9f7 876 *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level;
<> 144:ef7eb2e8f9f7 877 }
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879 return status;
<> 144:ef7eb2e8f9f7 880 }
<> 144:ef7eb2e8f9f7 881
<> 144:ef7eb2e8f9f7 882 /**
<> 144:ef7eb2e8f9f7 883 * @brief Set the BOR Level.
<> 144:ef7eb2e8f9f7 884 * @param Level: specifies the Option Bytes BOR Reset Level.
<> 144:ef7eb2e8f9f7 885 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 886 * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
<> 144:ef7eb2e8f9f7 887 * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
<> 144:ef7eb2e8f9f7 888 * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
<> 144:ef7eb2e8f9f7 889 * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
<> 144:ef7eb2e8f9f7 890 * @retval HAL Status
<> 144:ef7eb2e8f9f7 891 */
<> 144:ef7eb2e8f9f7 892 static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
<> 144:ef7eb2e8f9f7 893 {
<> 144:ef7eb2e8f9f7 894 /* Check the parameters */
<> 144:ef7eb2e8f9f7 895 assert_param(IS_OB_BOR_LEVEL(Level));
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /* Set the BOR Level */
<> 144:ef7eb2e8f9f7 898 MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_BOR_LEV, Level);
<> 144:ef7eb2e8f9f7 899
<> 144:ef7eb2e8f9f7 900 return HAL_OK;
<> 144:ef7eb2e8f9f7 901
<> 144:ef7eb2e8f9f7 902 }
<> 144:ef7eb2e8f9f7 903
<> 144:ef7eb2e8f9f7 904 /**
<> 144:ef7eb2e8f9f7 905 * @brief Configure Boot base address.
<> 144:ef7eb2e8f9f7 906 *
<> 144:ef7eb2e8f9f7 907 * @param BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1
<> 144:ef7eb2e8f9f7 908 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 909 * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0
<> 144:ef7eb2e8f9f7 910 * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1
<> 144:ef7eb2e8f9f7 911 * @param Address: specifies Boot base address
<> 144:ef7eb2e8f9f7 912 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 913 * @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)
<> 144:ef7eb2e8f9f7 914 * @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000)
<> 144:ef7eb2e8f9f7 915 * @arg OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)
<> 144:ef7eb2e8f9f7 916 * @arg OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)
<> 144:ef7eb2e8f9f7 917 * @arg OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)
<> 144:ef7eb2e8f9f7 918 * @arg OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)
<> 144:ef7eb2e8f9f7 919 * @arg OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000)
<> 144:ef7eb2e8f9f7 920 *
<> 144:ef7eb2e8f9f7 921 * @retval HAL Status
<> 144:ef7eb2e8f9f7 922 */
<> 144:ef7eb2e8f9f7 923 static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address)
<> 144:ef7eb2e8f9f7 924 {
<> 144:ef7eb2e8f9f7 925 HAL_StatusTypeDef status = HAL_OK;
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 /* Check the parameters */
<> 144:ef7eb2e8f9f7 928 assert_param(IS_OB_BOOT_ADDRESS(Address));
<> 144:ef7eb2e8f9f7 929
<> 144:ef7eb2e8f9f7 930 /* Wait for last operation to be completed */
<> 144:ef7eb2e8f9f7 931 status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
<> 144:ef7eb2e8f9f7 932
<> 144:ef7eb2e8f9f7 933 if(status == HAL_OK)
<> 144:ef7eb2e8f9f7 934 {
<> 144:ef7eb2e8f9f7 935 if(BootOption == OPTIONBYTE_BOOTADDR_0)
<> 144:ef7eb2e8f9f7 936 {
<> 144:ef7eb2e8f9f7 937 MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address);
<> 144:ef7eb2e8f9f7 938 }
<> 144:ef7eb2e8f9f7 939 else
<> 144:ef7eb2e8f9f7 940 {
<> 144:ef7eb2e8f9f7 941 MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16));
<> 144:ef7eb2e8f9f7 942 }
<> 144:ef7eb2e8f9f7 943 }
<> 144:ef7eb2e8f9f7 944
<> 144:ef7eb2e8f9f7 945 return status;
<> 144:ef7eb2e8f9f7 946 }
<> 144:ef7eb2e8f9f7 947
<> 144:ef7eb2e8f9f7 948 /**
<> 144:ef7eb2e8f9f7 949 * @brief Returns the FLASH Read Protection level.
<> 144:ef7eb2e8f9f7 950 * @retval FlagStatus FLASH ReadOut Protection Status:
<> 144:ef7eb2e8f9f7 951 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 952 * @arg OB_RDP_LEVEL_0: No protection
<> 144:ef7eb2e8f9f7 953 * @arg OB_RDP_LEVEL_1: Read protection of the memory
<> 144:ef7eb2e8f9f7 954 * @arg OB_RDP_LEVEL_2: Full chip protection
<> 144:ef7eb2e8f9f7 955 */
<> 144:ef7eb2e8f9f7 956 static uint8_t FLASH_OB_GetRDP(void)
<> 144:ef7eb2e8f9f7 957 {
<> 144:ef7eb2e8f9f7 958 uint8_t readstatus = OB_RDP_LEVEL_0;
<> 144:ef7eb2e8f9f7 959
<> 144:ef7eb2e8f9f7 960 if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_0)
<> 144:ef7eb2e8f9f7 961 {
<> 144:ef7eb2e8f9f7 962 readstatus = OB_RDP_LEVEL_0;
<> 144:ef7eb2e8f9f7 963 }
<> 144:ef7eb2e8f9f7 964 else if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_2)
<> 144:ef7eb2e8f9f7 965 {
<> 144:ef7eb2e8f9f7 966 readstatus = OB_RDP_LEVEL_2;
<> 144:ef7eb2e8f9f7 967 }
<> 144:ef7eb2e8f9f7 968 else
<> 144:ef7eb2e8f9f7 969 {
<> 144:ef7eb2e8f9f7 970 readstatus = OB_RDP_LEVEL_1;
<> 144:ef7eb2e8f9f7 971 }
<> 144:ef7eb2e8f9f7 972
<> 144:ef7eb2e8f9f7 973 return readstatus;
<> 144:ef7eb2e8f9f7 974 }
<> 144:ef7eb2e8f9f7 975
<> 144:ef7eb2e8f9f7 976 /**
<> 144:ef7eb2e8f9f7 977 * @brief Returns the FLASH BOR level.
<> 144:ef7eb2e8f9f7 978 * @retval uint32_t The FLASH BOR level:
<> 144:ef7eb2e8f9f7 979 * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
<> 144:ef7eb2e8f9f7 980 * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
<> 144:ef7eb2e8f9f7 981 * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
<> 144:ef7eb2e8f9f7 982 * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V
<> 144:ef7eb2e8f9f7 983 */
<> 144:ef7eb2e8f9f7 984 static uint32_t FLASH_OB_GetBOR(void)
<> 144:ef7eb2e8f9f7 985 {
<> 144:ef7eb2e8f9f7 986 /* Return the FLASH BOR level */
<> 144:ef7eb2e8f9f7 987 return ((uint32_t)(FLASH->OPTCR & 0x0C));
<> 144:ef7eb2e8f9f7 988 }
<> 144:ef7eb2e8f9f7 989
<> 144:ef7eb2e8f9f7 990 /**
<> 144:ef7eb2e8f9f7 991 * @brief Configure Boot base address.
<> 144:ef7eb2e8f9f7 992 *
<> 144:ef7eb2e8f9f7 993 * @param BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1
<> 144:ef7eb2e8f9f7 994 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 995 * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0
<> 144:ef7eb2e8f9f7 996 * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1
<> 144:ef7eb2e8f9f7 997 *
<> 144:ef7eb2e8f9f7 998 * @retval uint32_t Boot Base Address:
<> 144:ef7eb2e8f9f7 999 * - OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000)
<> 144:ef7eb2e8f9f7 1000 * - OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000)
<> 144:ef7eb2e8f9f7 1001 * - OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000)
<> 144:ef7eb2e8f9f7 1002 * - OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000)
<> 144:ef7eb2e8f9f7 1003 * - OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000)
<> 144:ef7eb2e8f9f7 1004 * - OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000)
<> 144:ef7eb2e8f9f7 1005 * - OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000)
<> 144:ef7eb2e8f9f7 1006 */
<> 144:ef7eb2e8f9f7 1007 static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption)
<> 144:ef7eb2e8f9f7 1008 {
<> 144:ef7eb2e8f9f7 1009 uint32_t Address = 0;
<> 144:ef7eb2e8f9f7 1010
<> 144:ef7eb2e8f9f7 1011 /* Return the Boot base Address */
<> 144:ef7eb2e8f9f7 1012 if(BootOption == OPTIONBYTE_BOOTADDR_0)
<> 144:ef7eb2e8f9f7 1013 {
<> 144:ef7eb2e8f9f7 1014 Address = FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD0;
<> 144:ef7eb2e8f9f7 1015 }
<> 144:ef7eb2e8f9f7 1016 else
<> 144:ef7eb2e8f9f7 1017 {
<> 144:ef7eb2e8f9f7 1018 Address = ((FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD1) >> 16);
<> 144:ef7eb2e8f9f7 1019 }
<> 144:ef7eb2e8f9f7 1020
<> 144:ef7eb2e8f9f7 1021 return Address;
<> 144:ef7eb2e8f9f7 1022 }
<> 144:ef7eb2e8f9f7 1023
<> 144:ef7eb2e8f9f7 1024 /**
<> 144:ef7eb2e8f9f7 1025 * @}
<> 144:ef7eb2e8f9f7 1026 */
<> 144:ef7eb2e8f9f7 1027
<> 144:ef7eb2e8f9f7 1028 #endif /* HAL_FLASH_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1029
<> 144:ef7eb2e8f9f7 1030 /**
<> 144:ef7eb2e8f9f7 1031 * @}
<> 144:ef7eb2e8f9f7 1032 */
<> 144:ef7eb2e8f9f7 1033
<> 144:ef7eb2e8f9f7 1034 /**
<> 144:ef7eb2e8f9f7 1035 * @}
<> 144:ef7eb2e8f9f7 1036 */
<> 144:ef7eb2e8f9f7 1037
<> 144:ef7eb2e8f9f7 1038 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/