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targets/hal/TARGET_STM/TARGET_STM32F4/serial_api.c@90:bd7e252b15f3, 2016-03-14 (annotated)
- Committer:
- mbed_official
- Date:
- Mon Mar 14 16:15:11 2016 +0000
- Revision:
- 90:bd7e252b15f3
- Parent:
- 69:41db872bbc3a
- Child:
- 94:17550cbf442f
Synchronized with git revision fec574a5ed6db26aca1b13992ff271bf527d4a0d
Full URL: https://github.com/mbedmicro/mbed/commit/fec574a5ed6db26aca1b13992ff271bf527d4a0d/
Increased allocated netbufs to handle DTLS handshakes
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 0:9b334a45a8ff | 1 | /* mbed Microcontroller Library |
bogdanm | 0:9b334a45a8ff | 2 | ******************************************************************************* |
bogdanm | 0:9b334a45a8ff | 3 | * Copyright (c) 2015, STMicroelectronics |
bogdanm | 0:9b334a45a8ff | 4 | * All rights reserved. |
bogdanm | 0:9b334a45a8ff | 5 | * |
bogdanm | 0:9b334a45a8ff | 6 | * Redistribution and use in source and binary forms, with or without |
bogdanm | 0:9b334a45a8ff | 7 | * modification, are permitted provided that the following conditions are met: |
bogdanm | 0:9b334a45a8ff | 8 | * |
bogdanm | 0:9b334a45a8ff | 9 | * 1. Redistributions of source code must retain the above copyright notice, |
bogdanm | 0:9b334a45a8ff | 10 | * this list of conditions and the following disclaimer. |
bogdanm | 0:9b334a45a8ff | 11 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
bogdanm | 0:9b334a45a8ff | 12 | * this list of conditions and the following disclaimer in the documentation |
bogdanm | 0:9b334a45a8ff | 13 | * and/or other materials provided with the distribution. |
bogdanm | 0:9b334a45a8ff | 14 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
bogdanm | 0:9b334a45a8ff | 15 | * may be used to endorse or promote products derived from this software |
bogdanm | 0:9b334a45a8ff | 16 | * without specific prior written permission. |
bogdanm | 0:9b334a45a8ff | 17 | * |
bogdanm | 0:9b334a45a8ff | 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
bogdanm | 0:9b334a45a8ff | 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
bogdanm | 0:9b334a45a8ff | 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
bogdanm | 0:9b334a45a8ff | 21 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
bogdanm | 0:9b334a45a8ff | 22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
bogdanm | 0:9b334a45a8ff | 23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
bogdanm | 0:9b334a45a8ff | 24 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
bogdanm | 0:9b334a45a8ff | 25 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
bogdanm | 0:9b334a45a8ff | 26 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
bogdanm | 0:9b334a45a8ff | 27 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
bogdanm | 0:9b334a45a8ff | 28 | ******************************************************************************* |
bogdanm | 0:9b334a45a8ff | 29 | */ |
mbed_official | 69:41db872bbc3a | 30 | #ifdef YOTTA_CFG_MBED_OS |
mbed_official | 69:41db872bbc3a | 31 | #include "target_config.h" |
mbed_official | 69:41db872bbc3a | 32 | #include "uvisor-lib/uvisor-lib.h" |
mbed_official | 69:41db872bbc3a | 33 | #include "mbed-drivers/mbed_assert.h" |
mbed_official | 69:41db872bbc3a | 34 | #else |
bogdanm | 0:9b334a45a8ff | 35 | #include "mbed_assert.h" |
mbed_official | 69:41db872bbc3a | 36 | #endif |
bogdanm | 0:9b334a45a8ff | 37 | #include "serial_api.h" |
bogdanm | 0:9b334a45a8ff | 38 | |
bogdanm | 0:9b334a45a8ff | 39 | #if DEVICE_SERIAL |
bogdanm | 0:9b334a45a8ff | 40 | |
bogdanm | 0:9b334a45a8ff | 41 | #include "cmsis.h" |
bogdanm | 0:9b334a45a8ff | 42 | #include "pinmap.h" |
bogdanm | 0:9b334a45a8ff | 43 | #include <string.h> |
bogdanm | 0:9b334a45a8ff | 44 | #include "PeripheralPins.h" |
mbed_official | 69:41db872bbc3a | 45 | #ifdef YOTTA_CFG_MBED_OS |
mbed_official | 69:41db872bbc3a | 46 | #include "mbed-drivers/mbed_error.h" |
mbed_official | 69:41db872bbc3a | 47 | #else |
bogdanm | 0:9b334a45a8ff | 48 | #include "mbed_error.h" |
mbed_official | 69:41db872bbc3a | 49 | #endif |
mbed_official | 69:41db872bbc3a | 50 | |
mbed_official | 69:41db872bbc3a | 51 | #define DEBUG_STDIO 0 |
mbed_official | 69:41db872bbc3a | 52 | |
mbed_official | 69:41db872bbc3a | 53 | #ifndef DEBUG_STDIO |
mbed_official | 69:41db872bbc3a | 54 | # define DEBUG_STDIO 0 |
mbed_official | 69:41db872bbc3a | 55 | #endif |
mbed_official | 69:41db872bbc3a | 56 | |
mbed_official | 69:41db872bbc3a | 57 | #if DEBUG_STDIO |
mbed_official | 69:41db872bbc3a | 58 | # include <stdio.h> |
mbed_official | 69:41db872bbc3a | 59 | # define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0) |
mbed_official | 69:41db872bbc3a | 60 | #else |
mbed_official | 69:41db872bbc3a | 61 | # define DEBUG_PRINTF(...) {} |
mbed_official | 69:41db872bbc3a | 62 | #endif |
bogdanm | 0:9b334a45a8ff | 63 | |
bogdanm | 0:9b334a45a8ff | 64 | #define UART_NUM (8) |
mbed_official | 55:814265bf5462 | 65 | #define UART_STATE_RX_ACTIVE 0x20 |
mbed_official | 55:814265bf5462 | 66 | #define UART_STATE_TX_ACTIVE 0x10 |
bogdanm | 0:9b334a45a8ff | 67 | |
mbed_official | 69:41db872bbc3a | 68 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 69:41db872bbc3a | 69 | static const uint32_t DMA_UartRx_Channel[UART_NUM] = {DMA_CHANNEL_4, DMA_CHANNEL_4, DMA_CHANNEL_4, DMA_CHANNEL_4, \ |
mbed_official | 69:41db872bbc3a | 70 | DMA_CHANNEL_4, DMA_CHANNEL_5, DMA_CHANNEL_5, DMA_CHANNEL_5}; |
mbed_official | 69:41db872bbc3a | 71 | DMA_Stream_TypeDef *DMA_UartRx_Stream[UART_NUM] = { |
mbed_official | 69:41db872bbc3a | 72 | DMA2_Stream5, DMA1_Stream5, DMA1_Stream1, \ |
mbed_official | 69:41db872bbc3a | 73 | DMA1_Stream2, DMA1_Stream0, DMA2_Stream1, \ |
mbed_official | 69:41db872bbc3a | 74 | DMA1_Stream3, DMA1_Stream6 |
mbed_official | 69:41db872bbc3a | 75 | }; |
mbed_official | 69:41db872bbc3a | 76 | static const uint32_t DMA_UartTx_Channel[UART_NUM] = {DMA_CHANNEL_4, DMA_CHANNEL_4, DMA_CHANNEL_4, DMA_CHANNEL_4, \ |
mbed_official | 69:41db872bbc3a | 77 | DMA_CHANNEL_4, DMA_CHANNEL_5, DMA_CHANNEL_5, DMA_CHANNEL_5}; |
mbed_official | 69:41db872bbc3a | 78 | DMA_Stream_TypeDef *DMA_UartTx_Stream[UART_NUM] = { |
mbed_official | 69:41db872bbc3a | 79 | DMA2_Stream7, DMA1_Stream6, DMA1_Stream3, \ |
mbed_official | 69:41db872bbc3a | 80 | DMA1_Stream4, DMA1_Stream7, DMA2_Stream6,\ |
mbed_official | 69:41db872bbc3a | 81 | DMA1_Stream1, DMA1_Stream0 |
mbed_official | 69:41db872bbc3a | 82 | }; |
mbed_official | 69:41db872bbc3a | 83 | DMA_HandleTypeDef DmaHandle; |
mbed_official | 69:41db872bbc3a | 84 | #endif |
bogdanm | 0:9b334a45a8ff | 85 | |
mbed_official | 69:41db872bbc3a | 86 | uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0, 0, 0, 0, 0, 0}; |
bogdanm | 0:9b334a45a8ff | 87 | static uart_irq_handler irq_handler; |
bogdanm | 0:9b334a45a8ff | 88 | |
mbed_official | 69:41db872bbc3a | 89 | static DMA_HandleTypeDef DmaTxHandle[UART_NUM]; |
mbed_official | 69:41db872bbc3a | 90 | static DMA_HandleTypeDef DmaRxHandle[UART_NUM]; |
mbed_official | 69:41db872bbc3a | 91 | static UART_HandleTypeDef UartHandle[UART_NUM]; |
bogdanm | 0:9b334a45a8ff | 92 | |
bogdanm | 0:9b334a45a8ff | 93 | int stdio_uart_inited = 0; |
bogdanm | 0:9b334a45a8ff | 94 | serial_t stdio_uart; |
bogdanm | 0:9b334a45a8ff | 95 | |
mbed_official | 55:814265bf5462 | 96 | #if DEVICE_SERIAL_ASYNCH |
mbed_official | 55:814265bf5462 | 97 | #define SERIAL_OBJ(X) (obj->serial.X) |
mbed_official | 55:814265bf5462 | 98 | #else |
mbed_official | 55:814265bf5462 | 99 | #define SERIAL_OBJ(X) (obj->X) |
mbed_official | 55:814265bf5462 | 100 | #endif |
mbed_official | 55:814265bf5462 | 101 | |
mbed_official | 69:41db872bbc3a | 102 | static void init_uart(serial_t *obj, UARTName instance) |
bogdanm | 0:9b334a45a8ff | 103 | { |
mbed_official | 55:814265bf5462 | 104 | |
mbed_official | 69:41db872bbc3a | 105 | UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)]; |
mbed_official | 69:41db872bbc3a | 106 | handle->Instance = (USART_TypeDef *)instance; |
bogdanm | 0:9b334a45a8ff | 107 | |
mbed_official | 69:41db872bbc3a | 108 | handle->Init.BaudRate = SERIAL_OBJ(baudrate); |
mbed_official | 69:41db872bbc3a | 109 | handle->Init.WordLength = SERIAL_OBJ(databits); |
mbed_official | 69:41db872bbc3a | 110 | handle->Init.StopBits = SERIAL_OBJ(stopbits); |
mbed_official | 69:41db872bbc3a | 111 | handle->Init.Parity = SERIAL_OBJ(parity); |
mbed_official | 60:6e6ed0527880 | 112 | #if DEVICE_SERIAL_FC |
mbed_official | 69:41db872bbc3a | 113 | handle->Init.HwFlowCtl = SERIAL_OBJ(hw_flow_ctl); |
mbed_official | 60:6e6ed0527880 | 114 | #else |
mbed_official | 69:41db872bbc3a | 115 | handle->Init.HwFlowCtl = UART_HWCONTROL_NONE; |
mbed_official | 60:6e6ed0527880 | 116 | #endif |
mbed_official | 69:41db872bbc3a | 117 | handle->Init.OverSampling = UART_OVERSAMPLING_16; |
mbed_official | 69:41db872bbc3a | 118 | handle->TxXferCount = 0; |
mbed_official | 69:41db872bbc3a | 119 | handle->RxXferCount = 0; |
bogdanm | 0:9b334a45a8ff | 120 | |
mbed_official | 55:814265bf5462 | 121 | if (SERIAL_OBJ(pin_rx) == NC) { |
mbed_official | 69:41db872bbc3a | 122 | handle->Init.Mode = UART_MODE_TX; |
mbed_official | 55:814265bf5462 | 123 | } else if (SERIAL_OBJ(pin_tx) == NC) { |
mbed_official | 69:41db872bbc3a | 124 | handle->Init.Mode = UART_MODE_RX; |
bogdanm | 0:9b334a45a8ff | 125 | } else { |
mbed_official | 69:41db872bbc3a | 126 | handle->Init.Mode = UART_MODE_TX_RX; |
bogdanm | 0:9b334a45a8ff | 127 | } |
mbed_official | 69:41db872bbc3a | 128 | |
mbed_official | 69:41db872bbc3a | 129 | #ifdef YOTTA_CFG_MBED_OS |
mbed_official | 69:41db872bbc3a | 130 | if (SERIAL_OBJ(pin_tx) == STDIO_UART_TX && SERIAL_OBJ(pin_rx) == STDIO_UART_RX) { |
mbed_official | 69:41db872bbc3a | 131 | handle->Init.BaudRate = YOTTA_CFG_MBED_OS_STDIO_DEFAULT_BAUD; |
mbed_official | 69:41db872bbc3a | 132 | } |
mbed_official | 69:41db872bbc3a | 133 | #endif |
mbed_official | 69:41db872bbc3a | 134 | |
mbed_official | 55:814265bf5462 | 135 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 55:814265bf5462 | 136 | if (SERIAL_OBJ(pin_tx) != NC) { |
mbed_official | 55:814265bf5462 | 137 | // set DMA in the UartHandle |
mbed_official | 69:41db872bbc3a | 138 | DMA_HandleTypeDef *hdma_tx = &DmaTxHandle[SERIAL_OBJ(index)]; |
mbed_official | 55:814265bf5462 | 139 | /* Configure the DMA handler for Transmission process */ |
mbed_official | 69:41db872bbc3a | 140 | hdma_tx->Instance = (DMA_Stream_TypeDef *)DMA_UartTx_Stream[SERIAL_OBJ(index)]; |
mbed_official | 69:41db872bbc3a | 141 | hdma_tx->Init.Channel = DMA_UartTx_Channel[SERIAL_OBJ(index)]; |
mbed_official | 69:41db872bbc3a | 142 | hdma_tx->Init.Direction = DMA_MEMORY_TO_PERIPH; |
mbed_official | 69:41db872bbc3a | 143 | hdma_tx->Init.PeriphInc = DMA_PINC_DISABLE; |
mbed_official | 69:41db872bbc3a | 144 | hdma_tx->Init.MemInc = DMA_MINC_ENABLE; |
mbed_official | 69:41db872bbc3a | 145 | hdma_tx->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; |
mbed_official | 69:41db872bbc3a | 146 | hdma_tx->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; |
mbed_official | 69:41db872bbc3a | 147 | hdma_tx->Init.Mode = DMA_NORMAL; |
mbed_official | 69:41db872bbc3a | 148 | hdma_tx->Init.Priority = DMA_PRIORITY_LOW; |
mbed_official | 69:41db872bbc3a | 149 | hdma_tx->Init.FIFOMode = DMA_FIFOMODE_DISABLE; |
mbed_official | 69:41db872bbc3a | 150 | hdma_tx->Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; |
mbed_official | 69:41db872bbc3a | 151 | hdma_tx->Init.MemBurst = DMA_MBURST_INC4; |
mbed_official | 69:41db872bbc3a | 152 | hdma_tx->Init.PeriphBurst = DMA_PBURST_INC4; |
mbed_official | 55:814265bf5462 | 153 | |
mbed_official | 69:41db872bbc3a | 154 | HAL_DMA_Init(hdma_tx); |
mbed_official | 55:814265bf5462 | 155 | |
mbed_official | 55:814265bf5462 | 156 | /* Associate the initialized DMA handle to the UART handle */ |
mbed_official | 69:41db872bbc3a | 157 | handle->hdmatx = hdma_tx; |
mbed_official | 69:41db872bbc3a | 158 | hdma_tx->Parent = handle; |
mbed_official | 55:814265bf5462 | 159 | } |
mbed_official | 55:814265bf5462 | 160 | |
mbed_official | 55:814265bf5462 | 161 | if (SERIAL_OBJ(pin_rx) != NC) { |
mbed_official | 55:814265bf5462 | 162 | /* Configure the DMA handler for reception process */ |
mbed_official | 69:41db872bbc3a | 163 | DMA_HandleTypeDef *hdma_rx = &DmaRxHandle[SERIAL_OBJ(index)]; |
mbed_official | 69:41db872bbc3a | 164 | hdma_rx->Instance = (DMA_Stream_TypeDef *)DMA_UartRx_Stream[SERIAL_OBJ(index)]; |
mbed_official | 69:41db872bbc3a | 165 | hdma_rx->Init.Channel = DMA_UartRx_Channel[SERIAL_OBJ(index)]; |
mbed_official | 69:41db872bbc3a | 166 | hdma_rx->Init.Direction = DMA_PERIPH_TO_MEMORY; |
mbed_official | 69:41db872bbc3a | 167 | hdma_rx->Init.PeriphInc = DMA_PINC_DISABLE; |
mbed_official | 69:41db872bbc3a | 168 | hdma_rx->Init.MemInc = DMA_MINC_ENABLE; |
mbed_official | 69:41db872bbc3a | 169 | hdma_rx->Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; |
mbed_official | 69:41db872bbc3a | 170 | hdma_rx->Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; |
mbed_official | 69:41db872bbc3a | 171 | hdma_rx->Init.Mode = DMA_NORMAL; |
mbed_official | 69:41db872bbc3a | 172 | hdma_rx->Init.Priority = DMA_PRIORITY_HIGH; |
mbed_official | 69:41db872bbc3a | 173 | hdma_rx->Init.FIFOMode = DMA_FIFOMODE_DISABLE; |
mbed_official | 69:41db872bbc3a | 174 | hdma_rx->Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; |
mbed_official | 69:41db872bbc3a | 175 | hdma_rx->Init.MemBurst = DMA_MBURST_INC4; |
mbed_official | 69:41db872bbc3a | 176 | hdma_rx->Init.PeriphBurst = DMA_PBURST_INC4; |
mbed_official | 55:814265bf5462 | 177 | |
mbed_official | 69:41db872bbc3a | 178 | HAL_DMA_Init(hdma_rx); |
mbed_official | 55:814265bf5462 | 179 | |
mbed_official | 55:814265bf5462 | 180 | /* Associate the initialized DMA handle to the UART handle */ |
mbed_official | 69:41db872bbc3a | 181 | handle->hdmarx = hdma_rx; |
mbed_official | 69:41db872bbc3a | 182 | hdma_rx->Parent = handle; |
mbed_official | 55:814265bf5462 | 183 | } |
mbed_official | 55:814265bf5462 | 184 | #endif |
bogdanm | 0:9b334a45a8ff | 185 | |
mbed_official | 69:41db872bbc3a | 186 | if (HAL_UART_Init(handle) != HAL_OK) { |
mbed_official | 55:814265bf5462 | 187 | error("Cannot initialize UART\n"); |
bogdanm | 0:9b334a45a8ff | 188 | } |
bogdanm | 0:9b334a45a8ff | 189 | } |
bogdanm | 0:9b334a45a8ff | 190 | |
bogdanm | 0:9b334a45a8ff | 191 | void serial_init(serial_t *obj, PinName tx, PinName rx) |
bogdanm | 0:9b334a45a8ff | 192 | { |
bogdanm | 0:9b334a45a8ff | 193 | // Determine the UART to use (UART_1, UART_2, ...) |
bogdanm | 0:9b334a45a8ff | 194 | UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX); |
bogdanm | 0:9b334a45a8ff | 195 | UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX); |
bogdanm | 0:9b334a45a8ff | 196 | |
bogdanm | 0:9b334a45a8ff | 197 | // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object |
mbed_official | 69:41db872bbc3a | 198 | UARTName instance = (UARTName)pinmap_merge(uart_tx, uart_rx); |
mbed_official | 55:814265bf5462 | 199 | |
mbed_official | 69:41db872bbc3a | 200 | MBED_ASSERT(instance != (UARTName)NC); |
bogdanm | 0:9b334a45a8ff | 201 | |
bogdanm | 0:9b334a45a8ff | 202 | // Enable USART clock |
mbed_official | 69:41db872bbc3a | 203 | switch (instance) { |
bogdanm | 0:9b334a45a8ff | 204 | case UART_1: |
bogdanm | 0:9b334a45a8ff | 205 | __HAL_RCC_USART1_CLK_ENABLE(); |
mbed_official | 55:814265bf5462 | 206 | SERIAL_OBJ(index) = 0; |
mbed_official | 55:814265bf5462 | 207 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 55:814265bf5462 | 208 | __HAL_RCC_DMA2_CLK_ENABLE(); |
mbed_official | 55:814265bf5462 | 209 | #endif |
bogdanm | 0:9b334a45a8ff | 210 | break; |
bogdanm | 0:9b334a45a8ff | 211 | case UART_2: |
bogdanm | 0:9b334a45a8ff | 212 | __HAL_RCC_USART2_CLK_ENABLE(); |
mbed_official | 55:814265bf5462 | 213 | SERIAL_OBJ(index) = 1; |
mbed_official | 55:814265bf5462 | 214 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 55:814265bf5462 | 215 | __HAL_RCC_DMA1_CLK_ENABLE(); |
mbed_official | 55:814265bf5462 | 216 | #endif |
bogdanm | 0:9b334a45a8ff | 217 | break; |
bogdanm | 0:9b334a45a8ff | 218 | #if defined(USART3_BASE) |
bogdanm | 0:9b334a45a8ff | 219 | case UART_3: |
bogdanm | 0:9b334a45a8ff | 220 | __HAL_RCC_USART3_CLK_ENABLE(); |
mbed_official | 55:814265bf5462 | 221 | SERIAL_OBJ(index) = 2; |
mbed_official | 55:814265bf5462 | 222 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 55:814265bf5462 | 223 | __HAL_RCC_DMA1_CLK_ENABLE(); |
mbed_official | 55:814265bf5462 | 224 | #endif |
bogdanm | 0:9b334a45a8ff | 225 | break; |
bogdanm | 0:9b334a45a8ff | 226 | #endif |
bogdanm | 0:9b334a45a8ff | 227 | #if defined(UART4_BASE) |
bogdanm | 0:9b334a45a8ff | 228 | case UART_4: |
bogdanm | 0:9b334a45a8ff | 229 | __HAL_RCC_UART4_CLK_ENABLE(); |
mbed_official | 55:814265bf5462 | 230 | SERIAL_OBJ(index) = 3; |
mbed_official | 55:814265bf5462 | 231 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 55:814265bf5462 | 232 | __HAL_RCC_DMA1_CLK_ENABLE(); |
mbed_official | 55:814265bf5462 | 233 | #endif |
bogdanm | 0:9b334a45a8ff | 234 | break; |
bogdanm | 0:9b334a45a8ff | 235 | #endif |
bogdanm | 0:9b334a45a8ff | 236 | #if defined(UART5_BASE) |
bogdanm | 0:9b334a45a8ff | 237 | case UART_5: |
bogdanm | 0:9b334a45a8ff | 238 | __HAL_RCC_UART5_CLK_ENABLE(); |
mbed_official | 55:814265bf5462 | 239 | SERIAL_OBJ(index) = 4; |
mbed_official | 55:814265bf5462 | 240 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 55:814265bf5462 | 241 | __HAL_RCC_DMA1_CLK_ENABLE(); |
mbed_official | 55:814265bf5462 | 242 | #endif |
bogdanm | 0:9b334a45a8ff | 243 | break; |
bogdanm | 0:9b334a45a8ff | 244 | #endif |
bogdanm | 0:9b334a45a8ff | 245 | #if defined(USART6_BASE) |
bogdanm | 0:9b334a45a8ff | 246 | case UART_6: |
bogdanm | 0:9b334a45a8ff | 247 | __HAL_RCC_USART6_CLK_ENABLE(); |
mbed_official | 55:814265bf5462 | 248 | SERIAL_OBJ(index) = 5; |
mbed_official | 55:814265bf5462 | 249 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 55:814265bf5462 | 250 | __HAL_RCC_DMA2_CLK_ENABLE(); |
mbed_official | 55:814265bf5462 | 251 | #endif |
bogdanm | 0:9b334a45a8ff | 252 | break; |
bogdanm | 0:9b334a45a8ff | 253 | #endif |
bogdanm | 0:9b334a45a8ff | 254 | #if defined(UART7_BASE) |
bogdanm | 0:9b334a45a8ff | 255 | case UART_7: |
bogdanm | 0:9b334a45a8ff | 256 | __HAL_RCC_UART7_CLK_ENABLE(); |
mbed_official | 55:814265bf5462 | 257 | SERIAL_OBJ(index) = 6; |
mbed_official | 55:814265bf5462 | 258 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 55:814265bf5462 | 259 | __HAL_RCC_DMA1_CLK_ENABLE(); |
mbed_official | 55:814265bf5462 | 260 | #endif |
bogdanm | 0:9b334a45a8ff | 261 | break; |
bogdanm | 0:9b334a45a8ff | 262 | #endif |
bogdanm | 0:9b334a45a8ff | 263 | #if defined(UART8_BASE) |
bogdanm | 0:9b334a45a8ff | 264 | case UART_8: |
bogdanm | 0:9b334a45a8ff | 265 | __HAL_RCC_UART8_CLK_ENABLE(); |
mbed_official | 55:814265bf5462 | 266 | SERIAL_OBJ(index) = 7; |
mbed_official | 55:814265bf5462 | 267 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 55:814265bf5462 | 268 | __HAL_RCC_DMA1_CLK_ENABLE(); |
mbed_official | 55:814265bf5462 | 269 | #endif |
bogdanm | 0:9b334a45a8ff | 270 | break; |
bogdanm | 0:9b334a45a8ff | 271 | #endif |
bogdanm | 0:9b334a45a8ff | 272 | } |
bogdanm | 0:9b334a45a8ff | 273 | |
bogdanm | 0:9b334a45a8ff | 274 | // Configure the UART pins |
bogdanm | 0:9b334a45a8ff | 275 | pinmap_pinout(tx, PinMap_UART_TX); |
bogdanm | 0:9b334a45a8ff | 276 | pinmap_pinout(rx, PinMap_UART_RX); |
mbed_official | 55:814265bf5462 | 277 | |
bogdanm | 0:9b334a45a8ff | 278 | if (tx != NC) { |
bogdanm | 0:9b334a45a8ff | 279 | pin_mode(tx, PullUp); |
bogdanm | 0:9b334a45a8ff | 280 | } |
bogdanm | 0:9b334a45a8ff | 281 | if (rx != NC) { |
bogdanm | 0:9b334a45a8ff | 282 | pin_mode(rx, PullUp); |
bogdanm | 0:9b334a45a8ff | 283 | } |
bogdanm | 0:9b334a45a8ff | 284 | |
bogdanm | 0:9b334a45a8ff | 285 | // Configure UART |
mbed_official | 55:814265bf5462 | 286 | SERIAL_OBJ(baudrate) = 9600; |
mbed_official | 55:814265bf5462 | 287 | SERIAL_OBJ(databits) = UART_WORDLENGTH_8B; |
mbed_official | 55:814265bf5462 | 288 | SERIAL_OBJ(stopbits) = UART_STOPBITS_1; |
mbed_official | 55:814265bf5462 | 289 | SERIAL_OBJ(parity) = UART_PARITY_NONE; |
bogdanm | 0:9b334a45a8ff | 290 | |
mbed_official | 55:814265bf5462 | 291 | SERIAL_OBJ(pin_tx) = tx; |
mbed_official | 55:814265bf5462 | 292 | SERIAL_OBJ(pin_rx) = rx; |
bogdanm | 0:9b334a45a8ff | 293 | |
mbed_official | 69:41db872bbc3a | 294 | init_uart(obj, instance); |
bogdanm | 0:9b334a45a8ff | 295 | |
mbed_official | 69:41db872bbc3a | 296 | #ifndef YOTTA_CFG_MBED_OS |
bogdanm | 0:9b334a45a8ff | 297 | // For stdio management |
mbed_official | 69:41db872bbc3a | 298 | if ((int)(UartHandle[SERIAL_OBJ(index)].Instance) == STDIO_UART) { |
bogdanm | 0:9b334a45a8ff | 299 | stdio_uart_inited = 1; |
bogdanm | 0:9b334a45a8ff | 300 | memcpy(&stdio_uart, obj, sizeof(serial_t)); |
bogdanm | 0:9b334a45a8ff | 301 | } |
mbed_official | 69:41db872bbc3a | 302 | #endif |
mbed_official | 69:41db872bbc3a | 303 | |
mbed_official | 69:41db872bbc3a | 304 | DEBUG_PRINTF("UART%u: Init\n", obj->serial.module+1); |
bogdanm | 0:9b334a45a8ff | 305 | } |
bogdanm | 0:9b334a45a8ff | 306 | |
bogdanm | 0:9b334a45a8ff | 307 | void serial_free(serial_t *obj) |
bogdanm | 0:9b334a45a8ff | 308 | { |
bogdanm | 0:9b334a45a8ff | 309 | // Reset UART and disable clock |
mbed_official | 69:41db872bbc3a | 310 | switch (SERIAL_OBJ(index)) { |
mbed_official | 69:41db872bbc3a | 311 | case 0: |
bogdanm | 0:9b334a45a8ff | 312 | __USART1_FORCE_RESET(); |
bogdanm | 0:9b334a45a8ff | 313 | __USART1_RELEASE_RESET(); |
bogdanm | 0:9b334a45a8ff | 314 | __USART1_CLK_DISABLE(); |
bogdanm | 0:9b334a45a8ff | 315 | break; |
mbed_official | 69:41db872bbc3a | 316 | case 1: |
bogdanm | 0:9b334a45a8ff | 317 | __USART2_FORCE_RESET(); |
bogdanm | 0:9b334a45a8ff | 318 | __USART2_RELEASE_RESET(); |
bogdanm | 0:9b334a45a8ff | 319 | __USART2_CLK_DISABLE(); |
mbed_official | 69:41db872bbc3a | 320 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 69:41db872bbc3a | 321 | __HAL_RCC_DMA1_CLK_DISABLE(); |
mbed_official | 69:41db872bbc3a | 322 | #endif |
bogdanm | 0:9b334a45a8ff | 323 | break; |
bogdanm | 0:9b334a45a8ff | 324 | #if defined(USART3_BASE) |
mbed_official | 69:41db872bbc3a | 325 | case 2: |
bogdanm | 0:9b334a45a8ff | 326 | __USART3_FORCE_RESET(); |
bogdanm | 0:9b334a45a8ff | 327 | __USART3_RELEASE_RESET(); |
bogdanm | 0:9b334a45a8ff | 328 | __USART3_CLK_DISABLE(); |
bogdanm | 0:9b334a45a8ff | 329 | break; |
bogdanm | 0:9b334a45a8ff | 330 | #endif |
bogdanm | 0:9b334a45a8ff | 331 | #if defined(UART4_BASE) |
mbed_official | 69:41db872bbc3a | 332 | case 3: |
bogdanm | 0:9b334a45a8ff | 333 | __UART4_FORCE_RESET(); |
bogdanm | 0:9b334a45a8ff | 334 | __UART4_RELEASE_RESET(); |
bogdanm | 0:9b334a45a8ff | 335 | __UART4_CLK_DISABLE(); |
mbed_official | 55:814265bf5462 | 336 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 55:814265bf5462 | 337 | __HAL_RCC_DMA1_CLK_DISABLE(); |
mbed_official | 55:814265bf5462 | 338 | #endif |
bogdanm | 0:9b334a45a8ff | 339 | break; |
bogdanm | 0:9b334a45a8ff | 340 | #endif |
bogdanm | 0:9b334a45a8ff | 341 | #if defined(UART5_BASE) |
mbed_official | 69:41db872bbc3a | 342 | case 4: |
bogdanm | 0:9b334a45a8ff | 343 | __UART5_FORCE_RESET(); |
bogdanm | 0:9b334a45a8ff | 344 | __UART5_RELEASE_RESET(); |
bogdanm | 0:9b334a45a8ff | 345 | __UART5_CLK_DISABLE(); |
bogdanm | 0:9b334a45a8ff | 346 | break; |
bogdanm | 0:9b334a45a8ff | 347 | #endif |
bogdanm | 0:9b334a45a8ff | 348 | #if defined(USART6_BASE) |
mbed_official | 69:41db872bbc3a | 349 | case 5: |
bogdanm | 0:9b334a45a8ff | 350 | __USART6_FORCE_RESET(); |
bogdanm | 0:9b334a45a8ff | 351 | __USART6_RELEASE_RESET(); |
bogdanm | 0:9b334a45a8ff | 352 | __USART6_CLK_DISABLE(); |
bogdanm | 0:9b334a45a8ff | 353 | break; |
bogdanm | 0:9b334a45a8ff | 354 | #endif |
bogdanm | 0:9b334a45a8ff | 355 | #if defined(UART7_BASE) |
mbed_official | 69:41db872bbc3a | 356 | case 6: |
bogdanm | 0:9b334a45a8ff | 357 | __UART7_FORCE_RESET(); |
bogdanm | 0:9b334a45a8ff | 358 | __UART7_RELEASE_RESET(); |
bogdanm | 0:9b334a45a8ff | 359 | __UART7_CLK_DISABLE(); |
bogdanm | 0:9b334a45a8ff | 360 | break; |
bogdanm | 0:9b334a45a8ff | 361 | #endif |
bogdanm | 0:9b334a45a8ff | 362 | #if defined(UART8_BASE) |
mbed_official | 69:41db872bbc3a | 363 | case 7: |
bogdanm | 0:9b334a45a8ff | 364 | __UART8_FORCE_RESET(); |
bogdanm | 0:9b334a45a8ff | 365 | __UART8_RELEASE_RESET(); |
bogdanm | 0:9b334a45a8ff | 366 | __UART8_CLK_DISABLE(); |
bogdanm | 0:9b334a45a8ff | 367 | break; |
bogdanm | 0:9b334a45a8ff | 368 | #endif |
bogdanm | 0:9b334a45a8ff | 369 | } |
mbed_official | 69:41db872bbc3a | 370 | |
bogdanm | 0:9b334a45a8ff | 371 | // Configure GPIOs |
mbed_official | 55:814265bf5462 | 372 | pin_function(SERIAL_OBJ(pin_tx), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); |
mbed_official | 55:814265bf5462 | 373 | pin_function(SERIAL_OBJ(pin_rx), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); |
bogdanm | 0:9b334a45a8ff | 374 | |
mbed_official | 55:814265bf5462 | 375 | serial_irq_ids[SERIAL_OBJ(index)] = 0; |
mbed_official | 69:41db872bbc3a | 376 | |
mbed_official | 69:41db872bbc3a | 377 | DEBUG_PRINTF("UART%u: Free\n", obj->serial.module+1); |
bogdanm | 0:9b334a45a8ff | 378 | } |
bogdanm | 0:9b334a45a8ff | 379 | |
bogdanm | 0:9b334a45a8ff | 380 | void serial_baud(serial_t *obj, int baudrate) |
bogdanm | 0:9b334a45a8ff | 381 | { |
mbed_official | 69:41db872bbc3a | 382 | UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)]; |
mbed_official | 69:41db872bbc3a | 383 | |
mbed_official | 55:814265bf5462 | 384 | SERIAL_OBJ(baudrate) = baudrate; |
mbed_official | 69:41db872bbc3a | 385 | handle->Init.BaudRate = baudrate; |
mbed_official | 69:41db872bbc3a | 386 | |
mbed_official | 69:41db872bbc3a | 387 | if (HAL_UART_Init(handle) != HAL_OK) { |
mbed_official | 69:41db872bbc3a | 388 | error("Cannot initialize UART\n"); |
mbed_official | 69:41db872bbc3a | 389 | } |
mbed_official | 69:41db872bbc3a | 390 | |
mbed_official | 69:41db872bbc3a | 391 | DEBUG_PRINTF("UART%u: Baudrate: %u\n", obj->serial.module+1, baudrate); |
bogdanm | 0:9b334a45a8ff | 392 | } |
bogdanm | 0:9b334a45a8ff | 393 | |
bogdanm | 0:9b334a45a8ff | 394 | void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) |
bogdanm | 0:9b334a45a8ff | 395 | { |
mbed_official | 69:41db872bbc3a | 396 | UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)]; |
mbed_official | 69:41db872bbc3a | 397 | |
bogdanm | 0:9b334a45a8ff | 398 | if (data_bits == 9) { |
mbed_official | 55:814265bf5462 | 399 | SERIAL_OBJ(databits) = UART_WORDLENGTH_9B; |
mbed_official | 69:41db872bbc3a | 400 | handle->Init.WordLength = UART_WORDLENGTH_9B; |
bogdanm | 0:9b334a45a8ff | 401 | } else { |
mbed_official | 55:814265bf5462 | 402 | SERIAL_OBJ(databits) = UART_WORDLENGTH_8B; |
mbed_official | 69:41db872bbc3a | 403 | handle->Init.WordLength = UART_WORDLENGTH_8B; |
bogdanm | 0:9b334a45a8ff | 404 | } |
bogdanm | 0:9b334a45a8ff | 405 | |
bogdanm | 0:9b334a45a8ff | 406 | switch (parity) { |
bogdanm | 0:9b334a45a8ff | 407 | case ParityOdd: |
mbed_official | 55:814265bf5462 | 408 | SERIAL_OBJ(parity) = UART_PARITY_ODD; |
mbed_official | 69:41db872bbc3a | 409 | handle->Init.Parity = UART_PARITY_ODD; |
bogdanm | 0:9b334a45a8ff | 410 | break; |
bogdanm | 0:9b334a45a8ff | 411 | case ParityEven: |
mbed_official | 55:814265bf5462 | 412 | SERIAL_OBJ(parity) = UART_PARITY_EVEN; |
mbed_official | 69:41db872bbc3a | 413 | handle->Init.Parity = UART_PARITY_EVEN; |
bogdanm | 0:9b334a45a8ff | 414 | break; |
bogdanm | 0:9b334a45a8ff | 415 | default: // ParityNone |
mbed_official | 69:41db872bbc3a | 416 | case ParityForced0: // unsupported! |
mbed_official | 69:41db872bbc3a | 417 | case ParityForced1: // unsupported! |
mbed_official | 55:814265bf5462 | 418 | SERIAL_OBJ(parity) = UART_PARITY_NONE; |
mbed_official | 69:41db872bbc3a | 419 | handle->Init.Parity = UART_PARITY_NONE; |
bogdanm | 0:9b334a45a8ff | 420 | break; |
bogdanm | 0:9b334a45a8ff | 421 | } |
bogdanm | 0:9b334a45a8ff | 422 | |
bogdanm | 0:9b334a45a8ff | 423 | if (stop_bits == 2) { |
mbed_official | 55:814265bf5462 | 424 | SERIAL_OBJ(stopbits) = UART_STOPBITS_2; |
mbed_official | 69:41db872bbc3a | 425 | handle->Init.StopBits = UART_STOPBITS_2; |
bogdanm | 0:9b334a45a8ff | 426 | } else { |
mbed_official | 55:814265bf5462 | 427 | SERIAL_OBJ(stopbits) = UART_STOPBITS_1; |
mbed_official | 69:41db872bbc3a | 428 | handle->Init.StopBits = UART_STOPBITS_1; |
bogdanm | 0:9b334a45a8ff | 429 | } |
bogdanm | 0:9b334a45a8ff | 430 | |
mbed_official | 69:41db872bbc3a | 431 | if (HAL_UART_Init(handle) != HAL_OK) { |
mbed_official | 69:41db872bbc3a | 432 | error("Cannot initialize UART\n"); |
mbed_official | 69:41db872bbc3a | 433 | } |
mbed_official | 69:41db872bbc3a | 434 | |
mbed_official | 69:41db872bbc3a | 435 | DEBUG_PRINTF("UART%u: Format: %u, %u, %u\n", obj->serial.module+1, data_bits, parity, stop_bits); |
bogdanm | 0:9b334a45a8ff | 436 | } |
bogdanm | 0:9b334a45a8ff | 437 | |
bogdanm | 0:9b334a45a8ff | 438 | /****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 439 | * INTERRUPTS HANDLING |
bogdanm | 0:9b334a45a8ff | 440 | ******************************************************************************/ |
bogdanm | 0:9b334a45a8ff | 441 | |
mbed_official | 69:41db872bbc3a | 442 | static void uart_irq(int id) |
bogdanm | 0:9b334a45a8ff | 443 | { |
mbed_official | 69:41db872bbc3a | 444 | UART_HandleTypeDef *handle = &UartHandle[id]; |
bogdanm | 0:9b334a45a8ff | 445 | if (serial_irq_ids[id] != 0) { |
mbed_official | 69:41db872bbc3a | 446 | if (__HAL_UART_GET_FLAG(handle, UART_FLAG_TC) != RESET) { |
bogdanm | 0:9b334a45a8ff | 447 | irq_handler(serial_irq_ids[id], TxIrq); |
mbed_official | 69:41db872bbc3a | 448 | __HAL_UART_CLEAR_FLAG(handle, UART_FLAG_TC); |
bogdanm | 0:9b334a45a8ff | 449 | } |
mbed_official | 69:41db872bbc3a | 450 | if (__HAL_UART_GET_FLAG(handle, UART_FLAG_RXNE) != RESET) { |
bogdanm | 0:9b334a45a8ff | 451 | irq_handler(serial_irq_ids[id], RxIrq); |
mbed_official | 69:41db872bbc3a | 452 | __HAL_UART_CLEAR_FLAG(handle, UART_FLAG_RXNE); |
bogdanm | 0:9b334a45a8ff | 453 | } |
mbed_official | 90:bd7e252b15f3 | 454 | if (__HAL_UART_GET_FLAG(handle, UART_FLAG_ORE) != RESET) { |
mbed_official | 90:bd7e252b15f3 | 455 | uint8_t c = handle->Instance->DR; |
mbed_official | 90:bd7e252b15f3 | 456 | } |
bogdanm | 0:9b334a45a8ff | 457 | } |
bogdanm | 0:9b334a45a8ff | 458 | } |
mbed_official | 69:41db872bbc3a | 459 | |
mbed_official | 55:814265bf5462 | 460 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 69:41db872bbc3a | 461 | static void dma_irq(DMAName name, int id, SerialIrq txrxirq) |
mbed_official | 55:814265bf5462 | 462 | { |
mbed_official | 69:41db872bbc3a | 463 | |
mbed_official | 69:41db872bbc3a | 464 | if (serial_irq_ids[id] != 0) { |
mbed_official | 69:41db872bbc3a | 465 | if (txrxirq == RxIrq) { |
mbed_official | 69:41db872bbc3a | 466 | if (__HAL_DMA_GET_TC_FLAG_INDEX(&DmaHandle) != RESET) { |
mbed_official | 69:41db872bbc3a | 467 | irq_handler(serial_irq_ids[id], RxIrq); |
mbed_official | 69:41db872bbc3a | 468 | __HAL_DMA_CLEAR_FLAG(&DmaHandle, DMA_FLAG_TCIF2_6); |
mbed_official | 69:41db872bbc3a | 469 | } |
mbed_official | 69:41db872bbc3a | 470 | } else { |
mbed_official | 69:41db872bbc3a | 471 | if (__HAL_DMA_GET_TC_FLAG_INDEX(&DmaHandle) != RESET) { |
mbed_official | 69:41db872bbc3a | 472 | irq_handler(serial_irq_ids[id], TxIrq); |
mbed_official | 69:41db872bbc3a | 473 | __HAL_DMA_CLEAR_FLAG(&DmaHandle, DMA_FLAG_TCIF0_4); |
mbed_official | 69:41db872bbc3a | 474 | } |
mbed_official | 69:41db872bbc3a | 475 | } |
mbed_official | 69:41db872bbc3a | 476 | } |
mbed_official | 55:814265bf5462 | 477 | DmaHandle.Instance = (DMA_Stream_TypeDef *)name; |
mbed_official | 55:814265bf5462 | 478 | if (serial_irq_ids[id] != 0) { |
mbed_official | 55:814265bf5462 | 479 | if (__HAL_DMA_GET_TC_FLAG_INDEX(&DmaHandle) != RESET) { |
mbed_official | 55:814265bf5462 | 480 | irq_handler(serial_irq_ids[id], TxIrq); |
mbed_official | 55:814265bf5462 | 481 | __HAL_DMA_CLEAR_FLAG(&DmaHandle, DMA_FLAG_TCIF0_4); |
mbed_official | 55:814265bf5462 | 482 | } |
mbed_official | 55:814265bf5462 | 483 | if (__HAL_DMA_GET_TC_FLAG_INDEX(&DmaHandle) != RESET) { |
mbed_official | 55:814265bf5462 | 484 | irq_handler(serial_irq_ids[id], RxIrq); |
mbed_official | 55:814265bf5462 | 485 | __HAL_DMA_CLEAR_FLAG(&DmaHandle, DMA_FLAG_TCIF2_6); |
mbed_official | 55:814265bf5462 | 486 | } |
mbed_official | 55:814265bf5462 | 487 | } |
mbed_official | 55:814265bf5462 | 488 | } |
mbed_official | 55:814265bf5462 | 489 | #endif |
bogdanm | 0:9b334a45a8ff | 490 | |
bogdanm | 0:9b334a45a8ff | 491 | static void uart1_irq(void) |
bogdanm | 0:9b334a45a8ff | 492 | { |
mbed_official | 69:41db872bbc3a | 493 | uart_irq(0); |
bogdanm | 0:9b334a45a8ff | 494 | } |
bogdanm | 0:9b334a45a8ff | 495 | |
bogdanm | 0:9b334a45a8ff | 496 | static void uart2_irq(void) |
bogdanm | 0:9b334a45a8ff | 497 | { |
mbed_official | 69:41db872bbc3a | 498 | uart_irq(1); |
bogdanm | 0:9b334a45a8ff | 499 | } |
bogdanm | 0:9b334a45a8ff | 500 | |
bogdanm | 0:9b334a45a8ff | 501 | #if defined(USART3_BASE) |
bogdanm | 0:9b334a45a8ff | 502 | static void uart3_irq(void) |
bogdanm | 0:9b334a45a8ff | 503 | { |
mbed_official | 69:41db872bbc3a | 504 | uart_irq(2); |
bogdanm | 0:9b334a45a8ff | 505 | } |
bogdanm | 0:9b334a45a8ff | 506 | #endif |
bogdanm | 0:9b334a45a8ff | 507 | |
bogdanm | 0:9b334a45a8ff | 508 | #if defined(UART4_BASE) |
bogdanm | 0:9b334a45a8ff | 509 | static void uart4_irq(void) |
bogdanm | 0:9b334a45a8ff | 510 | { |
mbed_official | 69:41db872bbc3a | 511 | uart_irq(3); |
bogdanm | 0:9b334a45a8ff | 512 | } |
mbed_official | 69:41db872bbc3a | 513 | #endif |
mbed_official | 69:41db872bbc3a | 514 | |
mbed_official | 55:814265bf5462 | 515 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 55:814265bf5462 | 516 | |
mbed_official | 69:41db872bbc3a | 517 | #if defined(UART5_BASE) |
mbed_official | 69:41db872bbc3a | 518 | static void dma1_stream0_irq(void) |
mbed_official | 69:41db872bbc3a | 519 | { |
mbed_official | 69:41db872bbc3a | 520 | dma_irq(DMA_1, 4, RxIrq); // uart5_rx |
mbed_official | 69:41db872bbc3a | 521 | } |
mbed_official | 69:41db872bbc3a | 522 | #endif |
mbed_official | 69:41db872bbc3a | 523 | |
mbed_official | 69:41db872bbc3a | 524 | #if defined(USART3_BASE) |
mbed_official | 69:41db872bbc3a | 525 | static void dma1_stream1_irq(void) |
mbed_official | 69:41db872bbc3a | 526 | { |
mbed_official | 69:41db872bbc3a | 527 | dma_irq(DMA_1, 2, RxIrq); // uart3_rx |
mbed_official | 69:41db872bbc3a | 528 | } |
mbed_official | 69:41db872bbc3a | 529 | #endif |
mbed_official | 69:41db872bbc3a | 530 | |
mbed_official | 69:41db872bbc3a | 531 | #if defined(UART4_BASE) |
mbed_official | 55:814265bf5462 | 532 | static void dma1_stream2_irq(void) |
mbed_official | 55:814265bf5462 | 533 | { |
mbed_official | 69:41db872bbc3a | 534 | dma_irq(DMA_1, 3, RxIrq); // uart4_rx |
mbed_official | 69:41db872bbc3a | 535 | } |
mbed_official | 69:41db872bbc3a | 536 | #endif |
mbed_official | 69:41db872bbc3a | 537 | |
mbed_official | 69:41db872bbc3a | 538 | #if defined(USART3_BASE) |
mbed_official | 69:41db872bbc3a | 539 | static void dma1_stream3_irq(void) |
mbed_official | 69:41db872bbc3a | 540 | { |
mbed_official | 69:41db872bbc3a | 541 | dma_irq(DMA_1, 2, TxIrq); // uart3_tx |
mbed_official | 69:41db872bbc3a | 542 | } |
mbed_official | 69:41db872bbc3a | 543 | #endif |
mbed_official | 69:41db872bbc3a | 544 | |
mbed_official | 69:41db872bbc3a | 545 | #if defined(UART4_BASE) |
mbed_official | 69:41db872bbc3a | 546 | static void dma1_stream4_irq(void) |
mbed_official | 69:41db872bbc3a | 547 | { |
mbed_official | 69:41db872bbc3a | 548 | dma_irq(DMA_1, 3, TxIrq); // uart4_tx |
mbed_official | 69:41db872bbc3a | 549 | } |
mbed_official | 69:41db872bbc3a | 550 | #endif |
mbed_official | 69:41db872bbc3a | 551 | |
mbed_official | 69:41db872bbc3a | 552 | static void dma1_stream5_irq(void) |
mbed_official | 69:41db872bbc3a | 553 | { |
mbed_official | 69:41db872bbc3a | 554 | dma_irq(DMA_1, 1, RxIrq); // uart2_rx |
mbed_official | 69:41db872bbc3a | 555 | } |
mbed_official | 69:41db872bbc3a | 556 | |
mbed_official | 69:41db872bbc3a | 557 | static void dma1_stream6_irq(void) |
mbed_official | 69:41db872bbc3a | 558 | { |
mbed_official | 69:41db872bbc3a | 559 | dma_irq(DMA_1, 1, TxIrq); // uart2_tx |
mbed_official | 55:814265bf5462 | 560 | } |
mbed_official | 55:814265bf5462 | 561 | |
mbed_official | 69:41db872bbc3a | 562 | #if defined(UART5_BASE) |
mbed_official | 69:41db872bbc3a | 563 | static void dma1_stream7_irq(void) |
mbed_official | 69:41db872bbc3a | 564 | { |
mbed_official | 69:41db872bbc3a | 565 | dma_irq(DMA_1, 4, TxIrq); // uart5_tx |
mbed_official | 69:41db872bbc3a | 566 | } |
mbed_official | 69:41db872bbc3a | 567 | #endif |
mbed_official | 55:814265bf5462 | 568 | |
mbed_official | 69:41db872bbc3a | 569 | #if defined(USART6_BASE) |
mbed_official | 69:41db872bbc3a | 570 | static void dma2_stream1_irq(void) |
mbed_official | 55:814265bf5462 | 571 | { |
mbed_official | 69:41db872bbc3a | 572 | dma_irq(DMA_2, 5, RxIrq); // uart6_rx |
mbed_official | 55:814265bf5462 | 573 | } |
mbed_official | 55:814265bf5462 | 574 | #endif |
mbed_official | 69:41db872bbc3a | 575 | |
mbed_official | 69:41db872bbc3a | 576 | static void dma2_stream5_irq(void) |
mbed_official | 69:41db872bbc3a | 577 | { |
mbed_official | 69:41db872bbc3a | 578 | dma_irq(DMA_2, 0, RxIrq); // uart1_rx |
mbed_official | 69:41db872bbc3a | 579 | } |
mbed_official | 69:41db872bbc3a | 580 | |
mbed_official | 69:41db872bbc3a | 581 | static void dma2_stream6_irq(void) |
mbed_official | 69:41db872bbc3a | 582 | { |
mbed_official | 69:41db872bbc3a | 583 | dma_irq(DMA_2, 5, TxIrq); // uart6_tx |
mbed_official | 69:41db872bbc3a | 584 | } |
mbed_official | 69:41db872bbc3a | 585 | |
mbed_official | 69:41db872bbc3a | 586 | static void dma2_stream7_irq(void) |
mbed_official | 69:41db872bbc3a | 587 | { |
mbed_official | 69:41db872bbc3a | 588 | dma_irq(DMA_2, 0, TxIrq); // uart1_tx |
mbed_official | 69:41db872bbc3a | 589 | } |
mbed_official | 69:41db872bbc3a | 590 | |
mbed_official | 69:41db872bbc3a | 591 | #endif // DEVICE_SERIAL_ASYNCH_DMA |
bogdanm | 0:9b334a45a8ff | 592 | |
bogdanm | 0:9b334a45a8ff | 593 | #if defined(UART5_BASE) |
bogdanm | 0:9b334a45a8ff | 594 | static void uart5_irq(void) |
bogdanm | 0:9b334a45a8ff | 595 | { |
mbed_official | 69:41db872bbc3a | 596 | uart_irq(4); |
bogdanm | 0:9b334a45a8ff | 597 | } |
bogdanm | 0:9b334a45a8ff | 598 | #endif |
bogdanm | 0:9b334a45a8ff | 599 | |
bogdanm | 0:9b334a45a8ff | 600 | #if defined(USART6_BASE) |
bogdanm | 0:9b334a45a8ff | 601 | static void uart6_irq(void) |
bogdanm | 0:9b334a45a8ff | 602 | { |
mbed_official | 69:41db872bbc3a | 603 | uart_irq(5); |
bogdanm | 0:9b334a45a8ff | 604 | } |
bogdanm | 0:9b334a45a8ff | 605 | #endif |
bogdanm | 0:9b334a45a8ff | 606 | |
bogdanm | 0:9b334a45a8ff | 607 | #if defined(UART7_BASE) |
bogdanm | 0:9b334a45a8ff | 608 | static void uart7_irq(void) |
bogdanm | 0:9b334a45a8ff | 609 | { |
mbed_official | 69:41db872bbc3a | 610 | uart_irq(6); |
bogdanm | 0:9b334a45a8ff | 611 | } |
bogdanm | 0:9b334a45a8ff | 612 | #endif |
bogdanm | 0:9b334a45a8ff | 613 | |
bogdanm | 0:9b334a45a8ff | 614 | #if defined(UART8_BASE) |
bogdanm | 0:9b334a45a8ff | 615 | static void uart8_irq(void) |
bogdanm | 0:9b334a45a8ff | 616 | { |
mbed_official | 69:41db872bbc3a | 617 | uart_irq(7); |
bogdanm | 0:9b334a45a8ff | 618 | } |
bogdanm | 0:9b334a45a8ff | 619 | #endif |
bogdanm | 0:9b334a45a8ff | 620 | |
bogdanm | 0:9b334a45a8ff | 621 | void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) |
bogdanm | 0:9b334a45a8ff | 622 | { |
bogdanm | 0:9b334a45a8ff | 623 | irq_handler = handler; |
mbed_official | 55:814265bf5462 | 624 | serial_irq_ids[SERIAL_OBJ(index)] = id; |
bogdanm | 0:9b334a45a8ff | 625 | } |
bogdanm | 0:9b334a45a8ff | 626 | |
bogdanm | 0:9b334a45a8ff | 627 | void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) |
bogdanm | 0:9b334a45a8ff | 628 | { |
bogdanm | 0:9b334a45a8ff | 629 | IRQn_Type irq_n = (IRQn_Type)0; |
bogdanm | 0:9b334a45a8ff | 630 | uint32_t vector = 0; |
mbed_official | 55:814265bf5462 | 631 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 55:814265bf5462 | 632 | IRQn_Type irqn_dma = (IRQn_Type)0; |
mbed_official | 55:814265bf5462 | 633 | uint32_t vector_dma = 0; |
mbed_official | 55:814265bf5462 | 634 | #endif |
bogdanm | 0:9b334a45a8ff | 635 | |
mbed_official | 69:41db872bbc3a | 636 | UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)]; |
bogdanm | 0:9b334a45a8ff | 637 | |
mbed_official | 69:41db872bbc3a | 638 | switch (SERIAL_OBJ(index)) { |
mbed_official | 69:41db872bbc3a | 639 | case 0: |
bogdanm | 0:9b334a45a8ff | 640 | irq_n = USART1_IRQn; |
bogdanm | 0:9b334a45a8ff | 641 | vector = (uint32_t)&uart1_irq; |
mbed_official | 69:41db872bbc3a | 642 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 69:41db872bbc3a | 643 | if (irq == RxIrq) { |
mbed_official | 69:41db872bbc3a | 644 | irqn_dma = DMA2_Stream5_IRQn; |
mbed_official | 69:41db872bbc3a | 645 | vector_dma = (uint32_t)&dma2_stream5_irq; |
mbed_official | 69:41db872bbc3a | 646 | } else { |
mbed_official | 69:41db872bbc3a | 647 | irqn_dma = DMA2_Stream7_IRQn; |
mbed_official | 69:41db872bbc3a | 648 | vector_dma = (uint32_t)&dma2_stream7_irq; |
mbed_official | 69:41db872bbc3a | 649 | } |
mbed_official | 69:41db872bbc3a | 650 | #endif |
bogdanm | 0:9b334a45a8ff | 651 | break; |
bogdanm | 0:9b334a45a8ff | 652 | |
mbed_official | 69:41db872bbc3a | 653 | case 1: |
bogdanm | 0:9b334a45a8ff | 654 | irq_n = USART2_IRQn; |
bogdanm | 0:9b334a45a8ff | 655 | vector = (uint32_t)&uart2_irq; |
mbed_official | 69:41db872bbc3a | 656 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 69:41db872bbc3a | 657 | if (irq == RxIrq) { |
mbed_official | 69:41db872bbc3a | 658 | irqn_dma = DMA1_Stream5_IRQn; |
mbed_official | 69:41db872bbc3a | 659 | vector_dma = (uint32_t)&dma1_stream5_irq; |
mbed_official | 69:41db872bbc3a | 660 | } else { |
mbed_official | 69:41db872bbc3a | 661 | irqn_dma = DMA1_Stream6_IRQn; |
mbed_official | 69:41db872bbc3a | 662 | vector_dma = (uint32_t)&dma1_stream6_irq; |
mbed_official | 69:41db872bbc3a | 663 | } |
mbed_official | 69:41db872bbc3a | 664 | #endif |
bogdanm | 0:9b334a45a8ff | 665 | break; |
bogdanm | 0:9b334a45a8ff | 666 | #if defined(USART3_BASE) |
mbed_official | 69:41db872bbc3a | 667 | case 2: |
bogdanm | 0:9b334a45a8ff | 668 | irq_n = USART3_IRQn; |
bogdanm | 0:9b334a45a8ff | 669 | vector = (uint32_t)&uart3_irq; |
mbed_official | 69:41db872bbc3a | 670 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 69:41db872bbc3a | 671 | if (irq == RxIrq) { |
mbed_official | 69:41db872bbc3a | 672 | irqn_dma = DMA1_Stream1_IRQn; |
mbed_official | 69:41db872bbc3a | 673 | vector_dma = (uint32_t)&dma1_stream1_irq; |
mbed_official | 69:41db872bbc3a | 674 | } else { |
mbed_official | 69:41db872bbc3a | 675 | irqn_dma = DMA1_Stream3_IRQn; |
mbed_official | 69:41db872bbc3a | 676 | vector_dma = (uint32_t)&dma1_stream3_irq; |
mbed_official | 69:41db872bbc3a | 677 | } |
mbed_official | 69:41db872bbc3a | 678 | #endif |
bogdanm | 0:9b334a45a8ff | 679 | break; |
bogdanm | 0:9b334a45a8ff | 680 | #endif |
bogdanm | 0:9b334a45a8ff | 681 | #if defined(UART4_BASE) |
mbed_official | 69:41db872bbc3a | 682 | case 3: |
bogdanm | 0:9b334a45a8ff | 683 | irq_n = UART4_IRQn; |
bogdanm | 0:9b334a45a8ff | 684 | vector = (uint32_t)&uart4_irq; |
mbed_official | 55:814265bf5462 | 685 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 55:814265bf5462 | 686 | if (irq == RxIrq) { |
mbed_official | 55:814265bf5462 | 687 | irqn_dma = DMA1_Stream2_IRQn; |
mbed_official | 55:814265bf5462 | 688 | vector_dma = (uint32_t)&dma1_stream2_irq; |
mbed_official | 55:814265bf5462 | 689 | } else { |
mbed_official | 55:814265bf5462 | 690 | irqn_dma = DMA1_Stream4_IRQn; |
mbed_official | 55:814265bf5462 | 691 | vector_dma = (uint32_t)&dma1_stream4_irq; |
mbed_official | 55:814265bf5462 | 692 | } |
mbed_official | 55:814265bf5462 | 693 | #endif |
bogdanm | 0:9b334a45a8ff | 694 | break; |
bogdanm | 0:9b334a45a8ff | 695 | #endif |
bogdanm | 0:9b334a45a8ff | 696 | #if defined(UART5_BASE) |
mbed_official | 69:41db872bbc3a | 697 | case 4: |
bogdanm | 0:9b334a45a8ff | 698 | irq_n = UART5_IRQn; |
bogdanm | 0:9b334a45a8ff | 699 | vector = (uint32_t)&uart5_irq; |
mbed_official | 69:41db872bbc3a | 700 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 69:41db872bbc3a | 701 | if (irq == RxIrq) { |
mbed_official | 69:41db872bbc3a | 702 | irqn_dma = DMA1_Stream0_IRQn; |
mbed_official | 69:41db872bbc3a | 703 | vector_dma = (uint32_t)&dma1_stream0_irq; |
mbed_official | 69:41db872bbc3a | 704 | } else { |
mbed_official | 69:41db872bbc3a | 705 | irqn_dma = DMA1_Stream4_IRQn; |
mbed_official | 69:41db872bbc3a | 706 | vector_dma = (uint32_t)&dma1_stream7_irq; |
mbed_official | 69:41db872bbc3a | 707 | } |
mbed_official | 69:41db872bbc3a | 708 | #endif |
bogdanm | 0:9b334a45a8ff | 709 | break; |
bogdanm | 0:9b334a45a8ff | 710 | #endif |
bogdanm | 0:9b334a45a8ff | 711 | #if defined(USART6_BASE) |
mbed_official | 69:41db872bbc3a | 712 | case 5: |
bogdanm | 0:9b334a45a8ff | 713 | irq_n = USART6_IRQn; |
bogdanm | 0:9b334a45a8ff | 714 | vector = (uint32_t)&uart6_irq; |
mbed_official | 69:41db872bbc3a | 715 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 69:41db872bbc3a | 716 | if (irq == RxIrq) { |
mbed_official | 69:41db872bbc3a | 717 | irqn_dma = DMA2_Stream1_IRQn; |
mbed_official | 69:41db872bbc3a | 718 | vector_dma = (uint32_t)&dma2_stream1_irq; |
mbed_official | 69:41db872bbc3a | 719 | } else { |
mbed_official | 69:41db872bbc3a | 720 | irqn_dma = DMA2_Stream6_IRQn; |
mbed_official | 69:41db872bbc3a | 721 | vector_dma = (uint32_t)&dma2_stream6_irq; |
mbed_official | 69:41db872bbc3a | 722 | } |
mbed_official | 69:41db872bbc3a | 723 | #endif |
bogdanm | 0:9b334a45a8ff | 724 | break; |
bogdanm | 0:9b334a45a8ff | 725 | #endif |
bogdanm | 0:9b334a45a8ff | 726 | #if defined(UART7_BASE) |
mbed_official | 69:41db872bbc3a | 727 | case 6: |
bogdanm | 0:9b334a45a8ff | 728 | irq_n = UART7_IRQn; |
bogdanm | 0:9b334a45a8ff | 729 | vector = (uint32_t)&uart7_irq; |
bogdanm | 0:9b334a45a8ff | 730 | break; |
bogdanm | 0:9b334a45a8ff | 731 | #endif |
bogdanm | 0:9b334a45a8ff | 732 | #if defined(UART8_BASE) |
mbed_official | 69:41db872bbc3a | 733 | case 7: |
bogdanm | 0:9b334a45a8ff | 734 | irq_n = UART8_IRQn; |
bogdanm | 0:9b334a45a8ff | 735 | vector = (uint32_t)&uart8_irq; |
bogdanm | 0:9b334a45a8ff | 736 | break; |
bogdanm | 0:9b334a45a8ff | 737 | #endif |
bogdanm | 0:9b334a45a8ff | 738 | } |
bogdanm | 0:9b334a45a8ff | 739 | |
bogdanm | 0:9b334a45a8ff | 740 | if (enable) { |
bogdanm | 0:9b334a45a8ff | 741 | |
bogdanm | 0:9b334a45a8ff | 742 | if (irq == RxIrq) { |
mbed_official | 69:41db872bbc3a | 743 | __HAL_UART_ENABLE_IT(handle, UART_IT_RXNE); |
mbed_official | 55:814265bf5462 | 744 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 55:814265bf5462 | 745 | NVIC_SetVector(irq_n, vector_dma); |
mbed_official | 55:814265bf5462 | 746 | NVIC_EnableIRQ(irq_n); |
mbed_official | 55:814265bf5462 | 747 | NVIC_SetVector(irqn_dma, vector_dma); |
mbed_official | 55:814265bf5462 | 748 | NVIC_EnableIRQ(irqn_dma); |
mbed_official | 55:814265bf5462 | 749 | #else |
mbed_official | 55:814265bf5462 | 750 | NVIC_SetVector(irq_n, vector); |
mbed_official | 55:814265bf5462 | 751 | NVIC_EnableIRQ(irq_n); |
mbed_official | 55:814265bf5462 | 752 | #endif |
bogdanm | 0:9b334a45a8ff | 753 | } else { // TxIrq |
mbed_official | 69:41db872bbc3a | 754 | __HAL_UART_ENABLE_IT(handle, UART_IT_TC); |
mbed_official | 55:814265bf5462 | 755 | NVIC_SetVector(irq_n, vector); |
mbed_official | 55:814265bf5462 | 756 | NVIC_EnableIRQ(irq_n); |
mbed_official | 55:814265bf5462 | 757 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 55:814265bf5462 | 758 | NVIC_SetVector(irqn_dma, vector_dma); |
mbed_official | 55:814265bf5462 | 759 | NVIC_EnableIRQ(irqn_dma); |
mbed_official | 55:814265bf5462 | 760 | #endif |
bogdanm | 0:9b334a45a8ff | 761 | } |
bogdanm | 0:9b334a45a8ff | 762 | } else { // disable |
bogdanm | 0:9b334a45a8ff | 763 | |
bogdanm | 0:9b334a45a8ff | 764 | int all_disabled = 0; |
bogdanm | 0:9b334a45a8ff | 765 | |
bogdanm | 0:9b334a45a8ff | 766 | if (irq == RxIrq) { |
mbed_official | 69:41db872bbc3a | 767 | __HAL_UART_DISABLE_IT(handle, UART_IT_RXNE); |
bogdanm | 0:9b334a45a8ff | 768 | // Check if TxIrq is disabled too |
mbed_official | 69:41db872bbc3a | 769 | if ((handle->Instance->CR1 & USART_CR1_TXEIE) == 0) all_disabled = 1; |
bogdanm | 0:9b334a45a8ff | 770 | } else { // TxIrq |
mbed_official | 69:41db872bbc3a | 771 | __HAL_UART_DISABLE_IT(handle, UART_IT_TXE); |
bogdanm | 0:9b334a45a8ff | 772 | // Check if RxIrq is disabled too |
mbed_official | 69:41db872bbc3a | 773 | if ((handle->Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1; |
bogdanm | 0:9b334a45a8ff | 774 | } |
bogdanm | 0:9b334a45a8ff | 775 | |
mbed_official | 55:814265bf5462 | 776 | if (all_disabled) { |
mbed_official | 55:814265bf5462 | 777 | NVIC_DisableIRQ(irq_n); |
mbed_official | 55:814265bf5462 | 778 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 55:814265bf5462 | 779 | NVIC_DisableIRQ(irqn_dma); |
mbed_official | 55:814265bf5462 | 780 | #endif |
mbed_official | 55:814265bf5462 | 781 | } |
bogdanm | 0:9b334a45a8ff | 782 | |
bogdanm | 0:9b334a45a8ff | 783 | } |
bogdanm | 0:9b334a45a8ff | 784 | } |
bogdanm | 0:9b334a45a8ff | 785 | |
bogdanm | 0:9b334a45a8ff | 786 | /****************************************************************************** |
bogdanm | 0:9b334a45a8ff | 787 | * READ/WRITE |
bogdanm | 0:9b334a45a8ff | 788 | ******************************************************************************/ |
bogdanm | 0:9b334a45a8ff | 789 | |
bogdanm | 0:9b334a45a8ff | 790 | int serial_getc(serial_t *obj) |
bogdanm | 0:9b334a45a8ff | 791 | { |
mbed_official | 69:41db872bbc3a | 792 | UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)]; |
bogdanm | 0:9b334a45a8ff | 793 | while (!serial_readable(obj)); |
mbed_official | 69:41db872bbc3a | 794 | return (int)(handle->Instance->DR & 0x1FF); |
bogdanm | 0:9b334a45a8ff | 795 | } |
bogdanm | 0:9b334a45a8ff | 796 | |
bogdanm | 0:9b334a45a8ff | 797 | void serial_putc(serial_t *obj, int c) |
bogdanm | 0:9b334a45a8ff | 798 | { |
mbed_official | 69:41db872bbc3a | 799 | UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)]; |
bogdanm | 0:9b334a45a8ff | 800 | while (!serial_writable(obj)); |
mbed_official | 69:41db872bbc3a | 801 | handle->Instance->DR = (uint32_t)(c & 0x1FF); |
bogdanm | 0:9b334a45a8ff | 802 | } |
bogdanm | 0:9b334a45a8ff | 803 | |
bogdanm | 0:9b334a45a8ff | 804 | int serial_readable(serial_t *obj) |
bogdanm | 0:9b334a45a8ff | 805 | { |
bogdanm | 0:9b334a45a8ff | 806 | int status; |
mbed_official | 69:41db872bbc3a | 807 | UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)]; |
bogdanm | 0:9b334a45a8ff | 808 | // Check if data is received |
mbed_official | 69:41db872bbc3a | 809 | status = ((__HAL_UART_GET_FLAG(handle, UART_FLAG_RXNE) != RESET) ? 1 : 0); |
bogdanm | 0:9b334a45a8ff | 810 | return status; |
bogdanm | 0:9b334a45a8ff | 811 | } |
bogdanm | 0:9b334a45a8ff | 812 | |
bogdanm | 0:9b334a45a8ff | 813 | int serial_writable(serial_t *obj) |
bogdanm | 0:9b334a45a8ff | 814 | { |
bogdanm | 0:9b334a45a8ff | 815 | int status; |
mbed_official | 69:41db872bbc3a | 816 | UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)]; |
bogdanm | 0:9b334a45a8ff | 817 | // Check if data is transmitted |
mbed_official | 69:41db872bbc3a | 818 | status = ((__HAL_UART_GET_FLAG(handle, UART_FLAG_TXE) != RESET) ? 1 : 0); |
bogdanm | 0:9b334a45a8ff | 819 | return status; |
bogdanm | 0:9b334a45a8ff | 820 | } |
bogdanm | 0:9b334a45a8ff | 821 | |
bogdanm | 0:9b334a45a8ff | 822 | void serial_clear(serial_t *obj) |
bogdanm | 0:9b334a45a8ff | 823 | { |
mbed_official | 69:41db872bbc3a | 824 | UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)]; |
mbed_official | 69:41db872bbc3a | 825 | __HAL_UART_CLEAR_FLAG(handle, UART_FLAG_TXE); |
mbed_official | 69:41db872bbc3a | 826 | __HAL_UART_CLEAR_FLAG(handle, UART_FLAG_RXNE); |
bogdanm | 0:9b334a45a8ff | 827 | } |
bogdanm | 0:9b334a45a8ff | 828 | |
bogdanm | 0:9b334a45a8ff | 829 | void serial_pinout_tx(PinName tx) |
bogdanm | 0:9b334a45a8ff | 830 | { |
bogdanm | 0:9b334a45a8ff | 831 | pinmap_pinout(tx, PinMap_UART_TX); |
bogdanm | 0:9b334a45a8ff | 832 | } |
bogdanm | 0:9b334a45a8ff | 833 | |
bogdanm | 0:9b334a45a8ff | 834 | void serial_break_set(serial_t *obj) |
bogdanm | 0:9b334a45a8ff | 835 | { |
mbed_official | 69:41db872bbc3a | 836 | UART_HandleTypeDef *uart = &UartHandle[SERIAL_OBJ(index)]; |
mbed_official | 69:41db872bbc3a | 837 | HAL_LIN_SendBreak(uart); |
bogdanm | 0:9b334a45a8ff | 838 | } |
bogdanm | 0:9b334a45a8ff | 839 | |
bogdanm | 0:9b334a45a8ff | 840 | void serial_break_clear(serial_t *obj) |
bogdanm | 0:9b334a45a8ff | 841 | { |
mbed_official | 69:41db872bbc3a | 842 | (void)obj; |
bogdanm | 0:9b334a45a8ff | 843 | } |
bogdanm | 0:9b334a45a8ff | 844 | |
mbed_official | 55:814265bf5462 | 845 | //######################################################################################## |
mbed_official | 55:814265bf5462 | 846 | |
mbed_official | 55:814265bf5462 | 847 | #if DEVICE_SERIAL_ASYNCH |
mbed_official | 55:814265bf5462 | 848 | |
mbed_official | 55:814265bf5462 | 849 | //---------------------------------------------------------------------------------------- |
mbed_official | 55:814265bf5462 | 850 | // LOCAL HELPER FUNCTIONS |
mbed_official | 55:814265bf5462 | 851 | //---------------------------------------------------------------------------------------- |
mbed_official | 55:814265bf5462 | 852 | |
mbed_official | 55:814265bf5462 | 853 | /** Configure the TX buffer for an asynchronous write serial transaction |
mbed_official | 55:814265bf5462 | 854 | * |
mbed_official | 55:814265bf5462 | 855 | * @param obj The serial object. |
mbed_official | 55:814265bf5462 | 856 | * @param tx The buffer for sending. |
mbed_official | 55:814265bf5462 | 857 | * @param tx_length The number of words to transmit. |
mbed_official | 55:814265bf5462 | 858 | */ |
mbed_official | 55:814265bf5462 | 859 | static void h_serial_tx_buffer_set(serial_t *obj, void *tx, int tx_length, uint8_t width) |
mbed_official | 55:814265bf5462 | 860 | { |
mbed_official | 55:814265bf5462 | 861 | // We only support byte buffers for now |
mbed_official | 55:814265bf5462 | 862 | MBED_ASSERT(width == 8); |
mbed_official | 55:814265bf5462 | 863 | |
mbed_official | 55:814265bf5462 | 864 | // Exit if a transmit is already on-going |
mbed_official | 55:814265bf5462 | 865 | if (serial_tx_active(obj)) return; |
mbed_official | 55:814265bf5462 | 866 | |
mbed_official | 55:814265bf5462 | 867 | obj->tx_buff.buffer = tx; |
mbed_official | 55:814265bf5462 | 868 | obj->tx_buff.length = tx_length; |
mbed_official | 55:814265bf5462 | 869 | obj->tx_buff.pos = 0; |
mbed_official | 55:814265bf5462 | 870 | |
mbed_official | 55:814265bf5462 | 871 | return; |
mbed_official | 55:814265bf5462 | 872 | } |
mbed_official | 55:814265bf5462 | 873 | |
mbed_official | 55:814265bf5462 | 874 | /** Configure the RX buffer for an asynchronous write serial transaction |
mbed_official | 55:814265bf5462 | 875 | * |
mbed_official | 55:814265bf5462 | 876 | * @param obj The serial object. |
mbed_official | 55:814265bf5462 | 877 | * @param tx The buffer for sending. |
mbed_official | 55:814265bf5462 | 878 | * @param tx_length The number of words to transmit. |
mbed_official | 55:814265bf5462 | 879 | */ |
mbed_official | 55:814265bf5462 | 880 | static void h_serial_rx_buffer_set(serial_t *obj, void *rx, int rx_length, uint8_t width) |
mbed_official | 55:814265bf5462 | 881 | { |
mbed_official | 55:814265bf5462 | 882 | /* Sanity check arguments */ |
mbed_official | 55:814265bf5462 | 883 | MBED_ASSERT(obj); |
mbed_official | 55:814265bf5462 | 884 | MBED_ASSERT(rx != (void*)0); |
mbed_official | 55:814265bf5462 | 885 | // We only support byte buffers for now |
mbed_official | 55:814265bf5462 | 886 | MBED_ASSERT(width == 8); |
mbed_official | 55:814265bf5462 | 887 | |
mbed_official | 55:814265bf5462 | 888 | // Exit if a reception is already on-going |
mbed_official | 55:814265bf5462 | 889 | if (serial_rx_active(obj)) return; |
mbed_official | 55:814265bf5462 | 890 | |
mbed_official | 55:814265bf5462 | 891 | obj->rx_buff.buffer = rx; |
mbed_official | 55:814265bf5462 | 892 | obj->rx_buff.length = rx_length; |
mbed_official | 55:814265bf5462 | 893 | obj->rx_buff.pos = 0; |
mbed_official | 55:814265bf5462 | 894 | |
mbed_official | 55:814265bf5462 | 895 | return; |
mbed_official | 55:814265bf5462 | 896 | } |
mbed_official | 55:814265bf5462 | 897 | |
mbed_official | 55:814265bf5462 | 898 | /** Configure TX events |
mbed_official | 55:814265bf5462 | 899 | * |
mbed_official | 55:814265bf5462 | 900 | * @param obj The serial object |
mbed_official | 55:814265bf5462 | 901 | * @param event The logical OR of the TX events to configure |
mbed_official | 55:814265bf5462 | 902 | * @param enable Set to non-zero to enable events, or zero to disable them |
mbed_official | 55:814265bf5462 | 903 | */ |
mbed_official | 55:814265bf5462 | 904 | static void h_serial_tx_enable_event(serial_t *obj, int event, uint8_t enable) |
mbed_official | 55:814265bf5462 | 905 | { |
mbed_official | 55:814265bf5462 | 906 | // Shouldn't have to enable TX interrupt here, just need to keep track of the requested events. |
mbed_official | 55:814265bf5462 | 907 | if (enable) SERIAL_OBJ(events) |= event; |
mbed_official | 55:814265bf5462 | 908 | else SERIAL_OBJ(events) &= ~event; |
mbed_official | 55:814265bf5462 | 909 | } |
mbed_official | 55:814265bf5462 | 910 | |
mbed_official | 55:814265bf5462 | 911 | /** Configure RX events |
mbed_official | 55:814265bf5462 | 912 | * |
mbed_official | 55:814265bf5462 | 913 | * @param obj The serial object |
mbed_official | 55:814265bf5462 | 914 | * @param event The logical OR of the RX events to configure |
mbed_official | 55:814265bf5462 | 915 | * @param enable Set to non-zero to enable events, or zero to disable them |
mbed_official | 55:814265bf5462 | 916 | */ |
mbed_official | 55:814265bf5462 | 917 | static void h_serial_rx_enable_event(serial_t *obj, int event, uint8_t enable) |
mbed_official | 55:814265bf5462 | 918 | { |
mbed_official | 55:814265bf5462 | 919 | // Shouldn't have to enable RX interrupt here, just need to keep track of the requested events. |
mbed_official | 55:814265bf5462 | 920 | if (enable) SERIAL_OBJ(events) |= event; |
mbed_official | 55:814265bf5462 | 921 | else SERIAL_OBJ(events) &= ~event; |
mbed_official | 55:814265bf5462 | 922 | } |
mbed_official | 55:814265bf5462 | 923 | |
mbed_official | 55:814265bf5462 | 924 | /** |
mbed_official | 55:814265bf5462 | 925 | * Get index of serial object TX IRQ, relating it to the physical peripheral. |
mbed_official | 55:814265bf5462 | 926 | * |
mbed_official | 55:814265bf5462 | 927 | * @param obj pointer to serial object |
mbed_official | 55:814265bf5462 | 928 | * @return internal NVIC TX IRQ index of U(S)ART peripheral |
mbed_official | 55:814265bf5462 | 929 | */ |
mbed_official | 55:814265bf5462 | 930 | static IRQn_Type h_serial_get_irq_index(serial_t *obj) |
mbed_official | 55:814265bf5462 | 931 | { |
mbed_official | 55:814265bf5462 | 932 | IRQn_Type irq_n = (IRQn_Type)0; |
mbed_official | 55:814265bf5462 | 933 | |
mbed_official | 69:41db872bbc3a | 934 | switch (SERIAL_OBJ(index)) { |
mbed_official | 55:814265bf5462 | 935 | #if defined(USART1_BASE) |
mbed_official | 69:41db872bbc3a | 936 | case 0: |
mbed_official | 55:814265bf5462 | 937 | irq_n = USART1_IRQn; |
mbed_official | 55:814265bf5462 | 938 | break; |
bogdanm | 0:9b334a45a8ff | 939 | #endif |
mbed_official | 55:814265bf5462 | 940 | #if defined(USART2_BASE) |
mbed_official | 69:41db872bbc3a | 941 | case 1: |
mbed_official | 55:814265bf5462 | 942 | irq_n = USART2_IRQn; |
mbed_official | 55:814265bf5462 | 943 | break; |
mbed_official | 55:814265bf5462 | 944 | #endif |
mbed_official | 55:814265bf5462 | 945 | #if defined(USART3_BASE) |
mbed_official | 69:41db872bbc3a | 946 | case 2: |
mbed_official | 55:814265bf5462 | 947 | irq_n = USART3_IRQn; |
mbed_official | 55:814265bf5462 | 948 | break; |
mbed_official | 55:814265bf5462 | 949 | #endif |
mbed_official | 55:814265bf5462 | 950 | #if defined(UART4_BASE) |
mbed_official | 69:41db872bbc3a | 951 | case 3: |
mbed_official | 55:814265bf5462 | 952 | irq_n = UART4_IRQn; |
mbed_official | 55:814265bf5462 | 953 | break; |
mbed_official | 55:814265bf5462 | 954 | #endif |
mbed_official | 69:41db872bbc3a | 955 | #if defined(USART5_BASE) |
mbed_official | 69:41db872bbc3a | 956 | case 4: |
mbed_official | 55:814265bf5462 | 957 | irq_n = UART5_IRQn; |
mbed_official | 55:814265bf5462 | 958 | break; |
mbed_official | 55:814265bf5462 | 959 | #endif |
mbed_official | 55:814265bf5462 | 960 | #if defined(USART6_BASE) |
mbed_official | 69:41db872bbc3a | 961 | case 5: |
mbed_official | 55:814265bf5462 | 962 | irq_n = USART6_IRQn; |
mbed_official | 55:814265bf5462 | 963 | break; |
mbed_official | 55:814265bf5462 | 964 | #endif |
mbed_official | 55:814265bf5462 | 965 | #if defined(UART7_BASE) |
mbed_official | 69:41db872bbc3a | 966 | case 6: |
mbed_official | 55:814265bf5462 | 967 | irq_n = UART7_IRQn; |
mbed_official | 55:814265bf5462 | 968 | break; |
mbed_official | 55:814265bf5462 | 969 | #endif |
mbed_official | 55:814265bf5462 | 970 | #if defined(UART8_BASE) |
mbed_official | 69:41db872bbc3a | 971 | case 7: |
mbed_official | 55:814265bf5462 | 972 | irq_n = UART8_IRQn; |
mbed_official | 55:814265bf5462 | 973 | break; |
mbed_official | 55:814265bf5462 | 974 | #endif |
mbed_official | 55:814265bf5462 | 975 | default: |
mbed_official | 55:814265bf5462 | 976 | irq_n = (IRQn_Type)0; |
mbed_official | 55:814265bf5462 | 977 | } |
mbed_official | 55:814265bf5462 | 978 | |
mbed_official | 55:814265bf5462 | 979 | return irq_n; |
mbed_official | 55:814265bf5462 | 980 | } |
mbed_official | 55:814265bf5462 | 981 | |
mbed_official | 55:814265bf5462 | 982 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 55:814265bf5462 | 983 | |
mbed_official | 69:41db872bbc3a | 984 | /** |
mbed_official | 69:41db872bbc3a | 985 | * @brief Start the DMA Transfer with interrupt enabled. |
mbed_official | 69:41db872bbc3a | 986 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
mbed_official | 69:41db872bbc3a | 987 | * the configuration information for the specified DMA Stream. |
mbed_official | 69:41db872bbc3a | 988 | * @param SrcAddress: The source memory Buffer address |
mbed_official | 69:41db872bbc3a | 989 | * @param DstAddress: The destination memory Buffer address |
mbed_official | 69:41db872bbc3a | 990 | * @param DataLength: The length of data to be transferred from source to destination |
mbed_official | 69:41db872bbc3a | 991 | * @retval HAL status |
mbed_official | 69:41db872bbc3a | 992 | */ |
mbed_official | 69:41db872bbc3a | 993 | static HAL_StatusTypeDef MBED_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
mbed_official | 55:814265bf5462 | 994 | { |
mbed_official | 69:41db872bbc3a | 995 | /* Process locked */ |
mbed_official | 69:41db872bbc3a | 996 | __HAL_LOCK(hdma); |
mbed_official | 69:41db872bbc3a | 997 | |
mbed_official | 69:41db872bbc3a | 998 | /* Change DMA peripheral state */ |
mbed_official | 69:41db872bbc3a | 999 | hdma->State = HAL_DMA_STATE_BUSY; |
mbed_official | 69:41db872bbc3a | 1000 | |
mbed_official | 69:41db872bbc3a | 1001 | /* Check the parameters */ |
mbed_official | 69:41db872bbc3a | 1002 | assert_param(IS_DMA_BUFFER_SIZE(DataLength)); |
mbed_official | 69:41db872bbc3a | 1003 | |
mbed_official | 69:41db872bbc3a | 1004 | /* Disable the peripheral */ |
mbed_official | 69:41db872bbc3a | 1005 | __HAL_DMA_DISABLE(hdma); |
mbed_official | 69:41db872bbc3a | 1006 | |
mbed_official | 69:41db872bbc3a | 1007 | /* Configure the source, destination address and the data length */ |
mbed_official | 69:41db872bbc3a | 1008 | /* Clear DBM bit */ |
mbed_official | 69:41db872bbc3a | 1009 | hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); |
mbed_official | 69:41db872bbc3a | 1010 | |
mbed_official | 69:41db872bbc3a | 1011 | /* Configure DMA Stream data length */ |
mbed_official | 69:41db872bbc3a | 1012 | hdma->Instance->NDTR = DataLength; |
mbed_official | 69:41db872bbc3a | 1013 | |
mbed_official | 69:41db872bbc3a | 1014 | /* Peripheral to Memory */ |
mbed_official | 69:41db872bbc3a | 1015 | if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) { |
mbed_official | 69:41db872bbc3a | 1016 | /* Configure DMA Stream destination address */ |
mbed_official | 69:41db872bbc3a | 1017 | hdma->Instance->PAR = DstAddress; |
mbed_official | 69:41db872bbc3a | 1018 | |
mbed_official | 69:41db872bbc3a | 1019 | /* Configure DMA Stream source address */ |
mbed_official | 69:41db872bbc3a | 1020 | hdma->Instance->M0AR = SrcAddress; |
mbed_official | 69:41db872bbc3a | 1021 | } else { |
mbed_official | 69:41db872bbc3a | 1022 | /* Memory to Peripheral */ |
mbed_official | 69:41db872bbc3a | 1023 | /* Configure DMA Stream source address */ |
mbed_official | 69:41db872bbc3a | 1024 | hdma->Instance->PAR = SrcAddress; |
mbed_official | 69:41db872bbc3a | 1025 | |
mbed_official | 69:41db872bbc3a | 1026 | /* Configure DMA Stream destination address */ |
mbed_official | 69:41db872bbc3a | 1027 | hdma->Instance->M0AR = DstAddress; |
mbed_official | 69:41db872bbc3a | 1028 | } |
mbed_official | 69:41db872bbc3a | 1029 | |
mbed_official | 69:41db872bbc3a | 1030 | /* Enable all interrupts EXCEPT HALF TRANSFER COMPLETE */ |
mbed_official | 69:41db872bbc3a | 1031 | hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; |
mbed_official | 69:41db872bbc3a | 1032 | hdma->Instance->FCR |= DMA_IT_FE; |
mbed_official | 69:41db872bbc3a | 1033 | |
mbed_official | 69:41db872bbc3a | 1034 | /* Enable the Peripheral */ |
mbed_official | 69:41db872bbc3a | 1035 | __HAL_DMA_ENABLE(hdma); |
mbed_official | 69:41db872bbc3a | 1036 | |
mbed_official | 69:41db872bbc3a | 1037 | return HAL_OK; |
mbed_official | 69:41db872bbc3a | 1038 | } |
mbed_official | 69:41db872bbc3a | 1039 | /** |
mbed_official | 69:41db872bbc3a | 1040 | * @brief DMA UART receive process half complete callback |
mbed_official | 69:41db872bbc3a | 1041 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
mbed_official | 69:41db872bbc3a | 1042 | * the configuration information for the specified DMA module. |
mbed_official | 69:41db872bbc3a | 1043 | * @retval None |
mbed_official | 69:41db872bbc3a | 1044 | */ |
mbed_official | 69:41db872bbc3a | 1045 | static void h_UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) |
mbed_official | 69:41db872bbc3a | 1046 | { |
mbed_official | 69:41db872bbc3a | 1047 | UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; |
mbed_official | 69:41db872bbc3a | 1048 | |
mbed_official | 69:41db872bbc3a | 1049 | HAL_UART_RxHalfCpltCallback(huart); |
mbed_official | 55:814265bf5462 | 1050 | } |
mbed_official | 69:41db872bbc3a | 1051 | |
mbed_official | 69:41db872bbc3a | 1052 | /** |
mbed_official | 69:41db872bbc3a | 1053 | * @brief DMA UART receive process complete callback. |
mbed_official | 69:41db872bbc3a | 1054 | * @param hdma: DMA handle |
mbed_official | 69:41db872bbc3a | 1055 | * @retval None |
mbed_official | 69:41db872bbc3a | 1056 | */ |
mbed_official | 69:41db872bbc3a | 1057 | static void h_UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) |
mbed_official | 69:41db872bbc3a | 1058 | { |
mbed_official | 69:41db872bbc3a | 1059 | UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
mbed_official | 69:41db872bbc3a | 1060 | /* DMA Normal mode*/ |
mbed_official | 69:41db872bbc3a | 1061 | if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) |
mbed_official | 69:41db872bbc3a | 1062 | { |
mbed_official | 69:41db872bbc3a | 1063 | huart->RxXferCount = 0; |
mbed_official | 69:41db872bbc3a | 1064 | |
mbed_official | 69:41db872bbc3a | 1065 | /* Disable the DMA transfer for the receiver request by setting the DMAR bit |
mbed_official | 69:41db872bbc3a | 1066 | in the UART CR3 register */ |
mbed_official | 69:41db872bbc3a | 1067 | huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); |
mbed_official | 69:41db872bbc3a | 1068 | |
mbed_official | 69:41db872bbc3a | 1069 | /* Check if a transmit process is ongoing or not */ |
mbed_official | 69:41db872bbc3a | 1070 | if(huart->State == HAL_UART_STATE_BUSY_TX_RX) |
mbed_official | 69:41db872bbc3a | 1071 | { |
mbed_official | 69:41db872bbc3a | 1072 | huart->State = HAL_UART_STATE_BUSY_TX; |
mbed_official | 69:41db872bbc3a | 1073 | } |
mbed_official | 69:41db872bbc3a | 1074 | else |
mbed_official | 69:41db872bbc3a | 1075 | { |
mbed_official | 69:41db872bbc3a | 1076 | huart->State = HAL_UART_STATE_READY; |
mbed_official | 69:41db872bbc3a | 1077 | } |
mbed_official | 69:41db872bbc3a | 1078 | } |
mbed_official | 69:41db872bbc3a | 1079 | HAL_UART_RxCpltCallback(huart); |
mbed_official | 69:41db872bbc3a | 1080 | } |
mbed_official | 69:41db872bbc3a | 1081 | /** |
mbed_official | 69:41db872bbc3a | 1082 | * @brief DMA UART communication error callback. |
mbed_official | 69:41db872bbc3a | 1083 | * @param hdma: DMA handle |
mbed_official | 69:41db872bbc3a | 1084 | * @retval None |
mbed_official | 69:41db872bbc3a | 1085 | */ |
mbed_official | 69:41db872bbc3a | 1086 | static void h_UART_DMAError(DMA_HandleTypeDef *hdma) |
mbed_official | 55:814265bf5462 | 1087 | { |
mbed_official | 69:41db872bbc3a | 1088 | UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
mbed_official | 69:41db872bbc3a | 1089 | huart->RxXferCount = 0; |
mbed_official | 69:41db872bbc3a | 1090 | huart->TxXferCount = 0; |
mbed_official | 69:41db872bbc3a | 1091 | huart->State= HAL_UART_STATE_READY; |
mbed_official | 69:41db872bbc3a | 1092 | huart->ErrorCode |= HAL_UART_ERROR_DMA; |
mbed_official | 69:41db872bbc3a | 1093 | HAL_UART_ErrorCallback(huart); |
mbed_official | 69:41db872bbc3a | 1094 | } |
mbed_official | 69:41db872bbc3a | 1095 | |
mbed_official | 69:41db872bbc3a | 1096 | /** |
mbed_official | 69:41db872bbc3a | 1097 | * @brief Receives an amount of data in non blocking mode. |
mbed_official | 69:41db872bbc3a | 1098 | * @note This function differs from HAL's function as it does not enable HalfTranferComplete |
mbed_official | 69:41db872bbc3a | 1099 | * @param huart: pointer to a UART_HandleTypeDef structure that contains |
mbed_official | 69:41db872bbc3a | 1100 | * the configuration information for the specified UART module. |
mbed_official | 69:41db872bbc3a | 1101 | * @param pData: Pointer to data buffer |
mbed_official | 69:41db872bbc3a | 1102 | * @param Size: Amount of data to be received |
mbed_official | 69:41db872bbc3a | 1103 | * @note When the UART parity is enabled (PCE = 1) the data received contain the parity bit. |
mbed_official | 69:41db872bbc3a | 1104 | * @retval HAL status |
mbed_official | 69:41db872bbc3a | 1105 | */ |
mbed_official | 69:41db872bbc3a | 1106 | static HAL_StatusTypeDef MBED_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) |
mbed_official | 69:41db872bbc3a | 1107 | { |
mbed_official | 69:41db872bbc3a | 1108 | uint32_t *tmp; |
mbed_official | 69:41db872bbc3a | 1109 | uint32_t tmp1 = 0; |
mbed_official | 69:41db872bbc3a | 1110 | |
mbed_official | 69:41db872bbc3a | 1111 | tmp1 = huart->State; |
mbed_official | 69:41db872bbc3a | 1112 | if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_TX)) { |
mbed_official | 69:41db872bbc3a | 1113 | if((pData == NULL ) || (Size == 0)) { |
mbed_official | 69:41db872bbc3a | 1114 | return HAL_ERROR; |
mbed_official | 69:41db872bbc3a | 1115 | } |
mbed_official | 69:41db872bbc3a | 1116 | |
mbed_official | 69:41db872bbc3a | 1117 | /* Process Locked */ |
mbed_official | 69:41db872bbc3a | 1118 | __HAL_LOCK(huart); |
mbed_official | 69:41db872bbc3a | 1119 | |
mbed_official | 69:41db872bbc3a | 1120 | huart->pRxBuffPtr = pData; |
mbed_official | 69:41db872bbc3a | 1121 | huart->RxXferSize = Size; |
mbed_official | 69:41db872bbc3a | 1122 | |
mbed_official | 69:41db872bbc3a | 1123 | huart->ErrorCode = HAL_UART_ERROR_NONE; |
mbed_official | 69:41db872bbc3a | 1124 | /* Check if a transmit process is ongoing or not */ |
mbed_official | 69:41db872bbc3a | 1125 | if(huart->State == HAL_UART_STATE_BUSY_TX) { |
mbed_official | 69:41db872bbc3a | 1126 | huart->State = HAL_UART_STATE_BUSY_TX_RX; |
mbed_official | 69:41db872bbc3a | 1127 | } else { |
mbed_official | 69:41db872bbc3a | 1128 | huart->State = HAL_UART_STATE_BUSY_RX; |
mbed_official | 69:41db872bbc3a | 1129 | } |
mbed_official | 69:41db872bbc3a | 1130 | |
mbed_official | 69:41db872bbc3a | 1131 | /* Set the UART DMA transfer complete callback */ |
mbed_official | 69:41db872bbc3a | 1132 | huart->hdmarx->XferCpltCallback = h_UART_DMAReceiveCplt; |
mbed_official | 69:41db872bbc3a | 1133 | |
mbed_official | 69:41db872bbc3a | 1134 | /* Set the UART DMA Half transfer complete callback */ |
mbed_official | 69:41db872bbc3a | 1135 | huart->hdmarx->XferHalfCpltCallback = h_UART_DMARxHalfCplt; |
mbed_official | 69:41db872bbc3a | 1136 | |
mbed_official | 69:41db872bbc3a | 1137 | /* Set the DMA error callback */ |
mbed_official | 69:41db872bbc3a | 1138 | huart->hdmarx->XferErrorCallback = h_UART_DMAError; |
mbed_official | 69:41db872bbc3a | 1139 | |
mbed_official | 69:41db872bbc3a | 1140 | /* Enable the DMA Stream */ |
mbed_official | 69:41db872bbc3a | 1141 | tmp = (uint32_t*)&pData; |
mbed_official | 69:41db872bbc3a | 1142 | MBED_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size); |
mbed_official | 69:41db872bbc3a | 1143 | |
mbed_official | 69:41db872bbc3a | 1144 | /* Enable the DMA transfer for the receiver request by setting the DMAR bit |
mbed_official | 69:41db872bbc3a | 1145 | in the UART CR3 register */ |
mbed_official | 69:41db872bbc3a | 1146 | huart->Instance->CR3 |= USART_CR3_DMAR; |
mbed_official | 69:41db872bbc3a | 1147 | |
mbed_official | 69:41db872bbc3a | 1148 | /* Process Unlocked */ |
mbed_official | 69:41db872bbc3a | 1149 | __HAL_UNLOCK(huart); |
mbed_official | 69:41db872bbc3a | 1150 | |
mbed_official | 69:41db872bbc3a | 1151 | return HAL_OK; |
mbed_official | 69:41db872bbc3a | 1152 | } else { |
mbed_official | 69:41db872bbc3a | 1153 | return HAL_BUSY; |
mbed_official | 69:41db872bbc3a | 1154 | } |
mbed_official | 55:814265bf5462 | 1155 | } |
mbed_official | 55:814265bf5462 | 1156 | |
mbed_official | 55:814265bf5462 | 1157 | /** |
mbed_official | 55:814265bf5462 | 1158 | * Get index of serial object TX DMA IRQ, relating it to the physical peripheral. |
mbed_official | 55:814265bf5462 | 1159 | * |
mbed_official | 55:814265bf5462 | 1160 | * @param obj pointer to serial object |
mbed_official | 55:814265bf5462 | 1161 | * @return internal NVIC TX DMA IRQ index of U(S)ART peripheral |
mbed_official | 55:814265bf5462 | 1162 | */ |
mbed_official | 55:814265bf5462 | 1163 | static IRQn_Type h_serial_tx_get_irqdma_index(serial_t *obj) |
mbed_official | 55:814265bf5462 | 1164 | { |
mbed_official | 55:814265bf5462 | 1165 | IRQn_Type irq_n = (IRQn_Type)0; |
mbed_official | 55:814265bf5462 | 1166 | |
mbed_official | 69:41db872bbc3a | 1167 | switch (SERIAL_OBJ(index)) { |
mbed_official | 55:814265bf5462 | 1168 | #if defined(USART1_BASE) |
mbed_official | 69:41db872bbc3a | 1169 | case 0: |
mbed_official | 55:814265bf5462 | 1170 | irq_n = DMA2_Stream7_IRQn; |
mbed_official | 55:814265bf5462 | 1171 | break; |
mbed_official | 55:814265bf5462 | 1172 | #endif |
mbed_official | 55:814265bf5462 | 1173 | #if defined(USART2_BASE) |
mbed_official | 69:41db872bbc3a | 1174 | case 1: |
mbed_official | 55:814265bf5462 | 1175 | irq_n = DMA1_Stream6_IRQn; |
mbed_official | 55:814265bf5462 | 1176 | break; |
mbed_official | 55:814265bf5462 | 1177 | #endif |
mbed_official | 55:814265bf5462 | 1178 | #if defined(USART3_BASE) |
mbed_official | 69:41db872bbc3a | 1179 | case 2: |
mbed_official | 55:814265bf5462 | 1180 | irq_n = DMA1_Stream3_IRQn; |
mbed_official | 55:814265bf5462 | 1181 | break; |
mbed_official | 55:814265bf5462 | 1182 | #endif |
mbed_official | 55:814265bf5462 | 1183 | #if defined(UART4_BASE) |
mbed_official | 69:41db872bbc3a | 1184 | case 3: |
mbed_official | 55:814265bf5462 | 1185 | irq_n = DMA1_Stream4_IRQn; |
mbed_official | 55:814265bf5462 | 1186 | break; |
mbed_official | 55:814265bf5462 | 1187 | #endif |
mbed_official | 55:814265bf5462 | 1188 | #if defined(UART5_BASE) |
mbed_official | 69:41db872bbc3a | 1189 | case 4: |
mbed_official | 55:814265bf5462 | 1190 | irq_n = DMA1_Stream7_IRQn; |
mbed_official | 55:814265bf5462 | 1191 | break; |
mbed_official | 55:814265bf5462 | 1192 | #endif |
mbed_official | 55:814265bf5462 | 1193 | #if defined(USART6_BASE) |
mbed_official | 69:41db872bbc3a | 1194 | case 5: |
mbed_official | 55:814265bf5462 | 1195 | irq_n = DMA2_Stream6_IRQn; |
mbed_official | 55:814265bf5462 | 1196 | break; |
mbed_official | 55:814265bf5462 | 1197 | #endif |
mbed_official | 55:814265bf5462 | 1198 | default: |
mbed_official | 55:814265bf5462 | 1199 | irq_n = (IRQn_Type)0; |
mbed_official | 55:814265bf5462 | 1200 | } |
mbed_official | 55:814265bf5462 | 1201 | |
mbed_official | 55:814265bf5462 | 1202 | return irq_n; |
mbed_official | 55:814265bf5462 | 1203 | } |
mbed_official | 55:814265bf5462 | 1204 | /** |
mbed_official | 55:814265bf5462 | 1205 | * Get index of serial object RX DMA IRQ, relating it to the physical peripheral. |
mbed_official | 55:814265bf5462 | 1206 | * |
mbed_official | 55:814265bf5462 | 1207 | * @param obj pointer to serial object |
mbed_official | 55:814265bf5462 | 1208 | * @return internal NVIC RX DMA IRQ index of U(S)ART peripheral |
mbed_official | 55:814265bf5462 | 1209 | */ |
mbed_official | 55:814265bf5462 | 1210 | static IRQn_Type h_serial_rx_get_irqdma_index(serial_t *obj) |
mbed_official | 55:814265bf5462 | 1211 | { |
mbed_official | 55:814265bf5462 | 1212 | IRQn_Type irq_n = (IRQn_Type)0; |
mbed_official | 55:814265bf5462 | 1213 | |
mbed_official | 69:41db872bbc3a | 1214 | switch (SERIAL_OBJ(index)) { |
mbed_official | 55:814265bf5462 | 1215 | #if defined(USART1_BASE) |
mbed_official | 69:41db872bbc3a | 1216 | case 0: |
mbed_official | 55:814265bf5462 | 1217 | irq_n = DMA2_Stream5_IRQn; |
mbed_official | 55:814265bf5462 | 1218 | break; |
mbed_official | 55:814265bf5462 | 1219 | #endif |
mbed_official | 55:814265bf5462 | 1220 | #if defined(USART2_BASE) |
mbed_official | 69:41db872bbc3a | 1221 | case 1: |
mbed_official | 55:814265bf5462 | 1222 | irq_n = DMA1_Stream5_IRQn; |
mbed_official | 55:814265bf5462 | 1223 | break; |
mbed_official | 55:814265bf5462 | 1224 | #endif |
mbed_official | 55:814265bf5462 | 1225 | #if defined(USART3_BASE) |
mbed_official | 69:41db872bbc3a | 1226 | case 2: |
mbed_official | 55:814265bf5462 | 1227 | irq_n = DMA1_Stream1_IRQn; |
mbed_official | 55:814265bf5462 | 1228 | break; |
mbed_official | 55:814265bf5462 | 1229 | #endif |
mbed_official | 55:814265bf5462 | 1230 | #if defined(UART4_BASE) |
mbed_official | 69:41db872bbc3a | 1231 | case 3: |
mbed_official | 55:814265bf5462 | 1232 | irq_n = DMA1_Stream2_IRQn; |
mbed_official | 55:814265bf5462 | 1233 | break; |
mbed_official | 55:814265bf5462 | 1234 | #endif |
mbed_official | 55:814265bf5462 | 1235 | #if defined(UART5_BASE) |
mbed_official | 69:41db872bbc3a | 1236 | case 4: |
mbed_official | 55:814265bf5462 | 1237 | irq_n = DMA1_Stream0_IRQn; |
mbed_official | 55:814265bf5462 | 1238 | break; |
mbed_official | 55:814265bf5462 | 1239 | #endif |
mbed_official | 55:814265bf5462 | 1240 | #if defined(USART6_BASE) |
mbed_official | 69:41db872bbc3a | 1241 | case 5: |
mbed_official | 69:41db872bbc3a | 1242 | irq_n = DMA2_Stream1_IRQn; |
mbed_official | 55:814265bf5462 | 1243 | break; |
mbed_official | 55:814265bf5462 | 1244 | #endif |
mbed_official | 55:814265bf5462 | 1245 | default: |
mbed_official | 55:814265bf5462 | 1246 | irq_n = (IRQn_Type)0; |
mbed_official | 55:814265bf5462 | 1247 | } |
mbed_official | 55:814265bf5462 | 1248 | |
mbed_official | 55:814265bf5462 | 1249 | return irq_n; |
mbed_official | 55:814265bf5462 | 1250 | } |
mbed_official | 55:814265bf5462 | 1251 | #endif |
mbed_official | 55:814265bf5462 | 1252 | //---------------------------------------------------------------------------------------- |
mbed_official | 55:814265bf5462 | 1253 | // MBED API FUNCTIONS |
mbed_official | 55:814265bf5462 | 1254 | //---------------------------------------------------------------------------------------- |
mbed_official | 55:814265bf5462 | 1255 | |
mbed_official | 55:814265bf5462 | 1256 | /** Begin asynchronous TX transfer. The used buffer is specified in the serial object, |
mbed_official | 55:814265bf5462 | 1257 | * tx_buff |
mbed_official | 55:814265bf5462 | 1258 | * |
mbed_official | 55:814265bf5462 | 1259 | * @param obj The serial object |
mbed_official | 55:814265bf5462 | 1260 | * @param tx The buffer for sending |
mbed_official | 55:814265bf5462 | 1261 | * @param tx_length The number of words to transmit |
mbed_official | 55:814265bf5462 | 1262 | * @param tx_width The bit width of buffer word |
mbed_official | 55:814265bf5462 | 1263 | * @param handler The serial handler |
mbed_official | 55:814265bf5462 | 1264 | * @param event The logical OR of events to be registered |
mbed_official | 55:814265bf5462 | 1265 | * @param hint A suggestion for how to use DMA with this transfer |
mbed_official | 55:814265bf5462 | 1266 | * @return Returns number of data transfered, or 0 otherwise |
mbed_official | 55:814265bf5462 | 1267 | */ |
mbed_official | 69:41db872bbc3a | 1268 | #ifdef YOTTA_CFG_MBED_OS |
mbed_official | 69:41db872bbc3a | 1269 | int serial_tx_asynch(serial_t *obj, void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) |
mbed_official | 69:41db872bbc3a | 1270 | #else |
mbed_official | 55:814265bf5462 | 1271 | int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint) |
mbed_official | 69:41db872bbc3a | 1272 | #endif |
mbed_official | 55:814265bf5462 | 1273 | { |
mbed_official | 69:41db872bbc3a | 1274 | // DMA usage is currently ignored |
mbed_official | 69:41db872bbc3a | 1275 | (void) hint; |
mbed_official | 69:41db872bbc3a | 1276 | |
mbed_official | 55:814265bf5462 | 1277 | // Check buffer is ok |
mbed_official | 55:814265bf5462 | 1278 | MBED_ASSERT(tx != (void*)0); |
mbed_official | 55:814265bf5462 | 1279 | MBED_ASSERT(tx_width == 8); // support only 8b width |
mbed_official | 55:814265bf5462 | 1280 | |
mbed_official | 55:814265bf5462 | 1281 | if (tx_length == 0) return 0; |
mbed_official | 55:814265bf5462 | 1282 | |
mbed_official | 55:814265bf5462 | 1283 | // Set up buffer |
mbed_official | 55:814265bf5462 | 1284 | h_serial_tx_buffer_set(obj, (void *)tx, tx_length, tx_width); |
mbed_official | 55:814265bf5462 | 1285 | |
mbed_official | 55:814265bf5462 | 1286 | // Set up events |
mbed_official | 55:814265bf5462 | 1287 | h_serial_tx_enable_event(obj, SERIAL_EVENT_TX_ALL, 0); // Clear all events |
mbed_official | 55:814265bf5462 | 1288 | h_serial_tx_enable_event(obj, event, 1); // Set only the wanted events |
mbed_official | 55:814265bf5462 | 1289 | |
mbed_official | 69:41db872bbc3a | 1290 | UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)]; |
mbed_official | 55:814265bf5462 | 1291 | // Enable interrupt |
mbed_official | 55:814265bf5462 | 1292 | IRQn_Type irqn = h_serial_get_irq_index(obj); |
mbed_official | 55:814265bf5462 | 1293 | NVIC_ClearPendingIRQ(irqn); |
mbed_official | 55:814265bf5462 | 1294 | NVIC_DisableIRQ(irqn); |
mbed_official | 55:814265bf5462 | 1295 | NVIC_SetPriority(irqn, 1); |
mbed_official | 55:814265bf5462 | 1296 | NVIC_SetVector(irqn, (uint32_t)handler); |
mbed_official | 55:814265bf5462 | 1297 | NVIC_EnableIRQ(irqn); |
mbed_official | 55:814265bf5462 | 1298 | |
mbed_official | 55:814265bf5462 | 1299 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 55:814265bf5462 | 1300 | // Enable DMA interrupt |
mbed_official | 55:814265bf5462 | 1301 | irqn = h_serial_tx_get_irqdma_index(obj); |
mbed_official | 55:814265bf5462 | 1302 | NVIC_ClearPendingIRQ(irqn); |
mbed_official | 55:814265bf5462 | 1303 | NVIC_DisableIRQ(irqn); |
mbed_official | 55:814265bf5462 | 1304 | NVIC_SetPriority(irqn, 1); |
mbed_official | 55:814265bf5462 | 1305 | NVIC_SetVector(irqn, (uint32_t)handler); |
mbed_official | 55:814265bf5462 | 1306 | NVIC_EnableIRQ(irqn); |
mbed_official | 55:814265bf5462 | 1307 | |
mbed_official | 55:814265bf5462 | 1308 | // the following function will enable program and enable the DMA transfer |
mbed_official | 69:41db872bbc3a | 1309 | if (HAL_UART_Transmit_DMA(handle, (uint8_t*)tx, tx_length) != HAL_OK) |
mbed_official | 55:814265bf5462 | 1310 | { |
mbed_official | 55:814265bf5462 | 1311 | /* Transfer error in transmission process */ |
mbed_official | 55:814265bf5462 | 1312 | return 0; |
mbed_official | 55:814265bf5462 | 1313 | } |
mbed_official | 55:814265bf5462 | 1314 | #else |
mbed_official | 55:814265bf5462 | 1315 | // the following function will enable UART_IT_TXE and error interrupts |
mbed_official | 69:41db872bbc3a | 1316 | if (HAL_UART_Transmit_IT(handle, (uint8_t*)tx, tx_length) != HAL_OK) |
mbed_official | 55:814265bf5462 | 1317 | { |
mbed_official | 55:814265bf5462 | 1318 | /* Transfer error in transmission process */ |
mbed_official | 55:814265bf5462 | 1319 | return 0; |
mbed_official | 55:814265bf5462 | 1320 | } |
mbed_official | 55:814265bf5462 | 1321 | #endif |
mbed_official | 69:41db872bbc3a | 1322 | |
mbed_official | 69:41db872bbc3a | 1323 | DEBUG_PRINTF("UART%u: Tx: 0=(%u, %u) %x\n", obj->serial.module+1, tx_length, tx_width, HAL_UART_GetState(handle)); |
mbed_official | 69:41db872bbc3a | 1324 | |
mbed_official | 55:814265bf5462 | 1325 | return tx_length; |
mbed_official | 55:814265bf5462 | 1326 | } |
mbed_official | 55:814265bf5462 | 1327 | |
mbed_official | 55:814265bf5462 | 1328 | /** Begin asynchronous RX transfer (enable interrupt for data collecting) |
mbed_official | 55:814265bf5462 | 1329 | * The used buffer is specified in the serial object - rx_buff |
mbed_official | 55:814265bf5462 | 1330 | * |
mbed_official | 55:814265bf5462 | 1331 | * @param obj The serial object |
mbed_official | 55:814265bf5462 | 1332 | * @param rx The buffer for sending |
mbed_official | 55:814265bf5462 | 1333 | * @param rx_length The number of words to transmit |
mbed_official | 55:814265bf5462 | 1334 | * @param rx_width The bit width of buffer word |
mbed_official | 55:814265bf5462 | 1335 | * @param handler The serial handler |
mbed_official | 55:814265bf5462 | 1336 | * @param event The logical OR of events to be registered |
mbed_official | 55:814265bf5462 | 1337 | * @param handler The serial handler |
mbed_official | 55:814265bf5462 | 1338 | * @param char_match A character in range 0-254 to be matched |
mbed_official | 55:814265bf5462 | 1339 | * @param hint A suggestion for how to use DMA with this transfer |
mbed_official | 55:814265bf5462 | 1340 | */ |
mbed_official | 55:814265bf5462 | 1341 | void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint) |
mbed_official | 55:814265bf5462 | 1342 | { |
mbed_official | 69:41db872bbc3a | 1343 | // DMA usage is currently ignored |
mbed_official | 69:41db872bbc3a | 1344 | (void) hint; |
mbed_official | 69:41db872bbc3a | 1345 | |
mbed_official | 55:814265bf5462 | 1346 | /* Sanity check arguments */ |
mbed_official | 55:814265bf5462 | 1347 | MBED_ASSERT(obj); |
mbed_official | 55:814265bf5462 | 1348 | MBED_ASSERT(rx != (void*)0); |
mbed_official | 55:814265bf5462 | 1349 | MBED_ASSERT(rx_width == 8); // support only 8b width |
mbed_official | 55:814265bf5462 | 1350 | |
mbed_official | 55:814265bf5462 | 1351 | h_serial_rx_enable_event(obj, SERIAL_EVENT_RX_ALL, 0); |
mbed_official | 55:814265bf5462 | 1352 | h_serial_rx_enable_event(obj, event, 1); |
mbed_official | 55:814265bf5462 | 1353 | // set CharMatch |
mbed_official | 55:814265bf5462 | 1354 | if (char_match != SERIAL_RESERVED_CHAR_MATCH) { |
mbed_official | 55:814265bf5462 | 1355 | obj->char_match = char_match; |
mbed_official | 55:814265bf5462 | 1356 | } |
mbed_official | 55:814265bf5462 | 1357 | h_serial_rx_buffer_set(obj, rx, rx_length, rx_width); |
mbed_official | 55:814265bf5462 | 1358 | |
mbed_official | 55:814265bf5462 | 1359 | IRQn_Type irqn = h_serial_get_irq_index(obj); |
mbed_official | 55:814265bf5462 | 1360 | NVIC_ClearPendingIRQ(irqn); |
mbed_official | 55:814265bf5462 | 1361 | NVIC_DisableIRQ(irqn); |
mbed_official | 55:814265bf5462 | 1362 | NVIC_SetPriority(irqn, 0); |
mbed_official | 55:814265bf5462 | 1363 | NVIC_SetVector(irqn, (uint32_t)handler); |
mbed_official | 55:814265bf5462 | 1364 | NVIC_EnableIRQ(irqn); |
mbed_official | 55:814265bf5462 | 1365 | |
mbed_official | 69:41db872bbc3a | 1366 | |
mbed_official | 69:41db872bbc3a | 1367 | UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)]; |
mbed_official | 55:814265bf5462 | 1368 | // flush current data + error flags |
mbed_official | 69:41db872bbc3a | 1369 | __HAL_UART_CLEAR_PEFLAG(handle); |
mbed_official | 55:814265bf5462 | 1370 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 55:814265bf5462 | 1371 | // Enable DMA interrupt |
mbed_official | 55:814265bf5462 | 1372 | irqn = h_serial_rx_get_irqdma_index(obj); |
mbed_official | 55:814265bf5462 | 1373 | NVIC_ClearPendingIRQ(irqn); |
mbed_official | 55:814265bf5462 | 1374 | NVIC_DisableIRQ(irqn); |
mbed_official | 55:814265bf5462 | 1375 | NVIC_SetPriority(irqn, 1); |
mbed_official | 55:814265bf5462 | 1376 | NVIC_SetVector(irqn, (uint32_t)handler); |
mbed_official | 55:814265bf5462 | 1377 | NVIC_EnableIRQ(irqn); |
mbed_official | 55:814265bf5462 | 1378 | // following HAL function will program and enable the DMA transfer |
mbed_official | 69:41db872bbc3a | 1379 | MBED_UART_Receive_DMA(handle, (uint8_t*)rx, rx_length); |
mbed_official | 55:814265bf5462 | 1380 | #else |
mbed_official | 55:814265bf5462 | 1381 | // following HAL function will enable the RXNE interrupt + error interrupts |
mbed_official | 69:41db872bbc3a | 1382 | HAL_UART_Receive_IT(handle, (uint8_t*)rx, rx_length); |
mbed_official | 55:814265bf5462 | 1383 | #endif |
mbed_official | 55:814265bf5462 | 1384 | /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ |
mbed_official | 69:41db872bbc3a | 1385 | __HAL_UART_ENABLE_IT(handle, UART_IT_ERR); |
mbed_official | 55:814265bf5462 | 1386 | |
mbed_official | 69:41db872bbc3a | 1387 | DEBUG_PRINTF("UART%u: Rx: 0=(%u, %u, %u) %x\n", obj->serial.module+1, rx_length, rx_width, char_match, HAL_UART_GetState(handle)); |
mbed_official | 55:814265bf5462 | 1388 | return; |
mbed_official | 55:814265bf5462 | 1389 | } |
mbed_official | 55:814265bf5462 | 1390 | |
mbed_official | 55:814265bf5462 | 1391 | /** Attempts to determine if the serial peripheral is already in use for TX |
mbed_official | 55:814265bf5462 | 1392 | * |
mbed_official | 55:814265bf5462 | 1393 | * @param obj The serial object |
mbed_official | 55:814265bf5462 | 1394 | * @return Non-zero if the TX transaction is ongoing, 0 otherwise |
mbed_official | 55:814265bf5462 | 1395 | */ |
mbed_official | 55:814265bf5462 | 1396 | uint8_t serial_tx_active(serial_t *obj) |
mbed_official | 55:814265bf5462 | 1397 | { |
mbed_official | 55:814265bf5462 | 1398 | MBED_ASSERT(obj); |
mbed_official | 69:41db872bbc3a | 1399 | UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)]; |
mbed_official | 69:41db872bbc3a | 1400 | return ((HAL_UART_GetState(handle) & UART_STATE_TX_ACTIVE) ? 1 : 0); |
mbed_official | 55:814265bf5462 | 1401 | } |
mbed_official | 55:814265bf5462 | 1402 | |
mbed_official | 55:814265bf5462 | 1403 | /** Attempts to determine if the serial peripheral is already in use for RX |
mbed_official | 55:814265bf5462 | 1404 | * |
mbed_official | 55:814265bf5462 | 1405 | * @param obj The serial object |
mbed_official | 55:814265bf5462 | 1406 | * @return Non-zero if the RX transaction is ongoing, 0 otherwise |
mbed_official | 55:814265bf5462 | 1407 | */ |
mbed_official | 55:814265bf5462 | 1408 | uint8_t serial_rx_active(serial_t *obj) |
mbed_official | 55:814265bf5462 | 1409 | { |
mbed_official | 55:814265bf5462 | 1410 | MBED_ASSERT(obj); |
mbed_official | 69:41db872bbc3a | 1411 | UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)]; |
mbed_official | 69:41db872bbc3a | 1412 | return ((HAL_UART_GetState(handle) & UART_STATE_RX_ACTIVE) ? 1 : 0); |
mbed_official | 55:814265bf5462 | 1413 | |
mbed_official | 55:814265bf5462 | 1414 | } |
mbed_official | 55:814265bf5462 | 1415 | |
mbed_official | 55:814265bf5462 | 1416 | /** The asynchronous TX and RX handler. |
mbed_official | 55:814265bf5462 | 1417 | * |
mbed_official | 55:814265bf5462 | 1418 | * @param obj The serial object |
mbed_official | 55:814265bf5462 | 1419 | * @return Returns event flags if a TX/RX transfer termination condition was met or 0 otherwise |
mbed_official | 55:814265bf5462 | 1420 | */ |
mbed_official | 55:814265bf5462 | 1421 | int serial_irq_handler_asynch(serial_t *obj) |
mbed_official | 55:814265bf5462 | 1422 | { |
mbed_official | 55:814265bf5462 | 1423 | volatile int return_event = 0; |
mbed_official | 55:814265bf5462 | 1424 | uint8_t *buf = (uint8_t*)obj->rx_buff.buffer; |
mbed_official | 55:814265bf5462 | 1425 | uint8_t i = 0; |
mbed_official | 55:814265bf5462 | 1426 | |
mbed_official | 55:814265bf5462 | 1427 | // Irq handler is common to Tx and Rx |
mbed_official | 69:41db872bbc3a | 1428 | UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)]; |
mbed_official | 55:814265bf5462 | 1429 | #if DEVICE_SERIAL_ASYNCH_DMA |
mbed_official | 69:41db872bbc3a | 1430 | if ((handle->Instance->CR3 & USART_CR3_DMAT) !=0) { |
mbed_official | 55:814265bf5462 | 1431 | // call dma tx interrupt |
mbed_official | 69:41db872bbc3a | 1432 | HAL_DMA_IRQHandler(handle->hdmatx); |
mbed_official | 55:814265bf5462 | 1433 | } |
mbed_official | 69:41db872bbc3a | 1434 | if ((handle->Instance->CR3 & USART_CR3_DMAR) !=0) { |
mbed_official | 55:814265bf5462 | 1435 | // call dma rx interrupt |
mbed_official | 69:41db872bbc3a | 1436 | HAL_DMA_IRQHandler(handle->hdmarx); |
mbed_official | 55:814265bf5462 | 1437 | } |
mbed_official | 55:814265bf5462 | 1438 | #endif |
mbed_official | 69:41db872bbc3a | 1439 | HAL_UART_IRQHandler(handle); |
mbed_official | 55:814265bf5462 | 1440 | // TX PART: |
mbed_official | 69:41db872bbc3a | 1441 | if (__HAL_UART_GET_FLAG(handle, UART_FLAG_TC) != RESET) { |
mbed_official | 69:41db872bbc3a | 1442 | __HAL_UART_CLEAR_FLAG(handle, UART_FLAG_TC); |
mbed_official | 55:814265bf5462 | 1443 | // return event SERIAL_EVENT_TX_COMPLETE if requested |
mbed_official | 55:814265bf5462 | 1444 | if ((SERIAL_OBJ(events) & SERIAL_EVENT_TX_COMPLETE ) != 0){ |
mbed_official | 55:814265bf5462 | 1445 | return_event |= SERIAL_EVENT_TX_COMPLETE & obj->serial.events; |
mbed_official | 55:814265bf5462 | 1446 | } |
mbed_official | 55:814265bf5462 | 1447 | } |
mbed_official | 55:814265bf5462 | 1448 | // handle error events: |
mbed_official | 69:41db872bbc3a | 1449 | if (__HAL_UART_GET_FLAG(handle, HAL_UART_ERROR_PE)) { |
mbed_official | 69:41db872bbc3a | 1450 | __HAL_UART_CLEAR_FLAG(handle, HAL_UART_ERROR_PE); |
mbed_official | 55:814265bf5462 | 1451 | return_event |= SERIAL_EVENT_RX_PARITY_ERROR & obj->serial.events; |
mbed_official | 55:814265bf5462 | 1452 | } |
mbed_official | 69:41db872bbc3a | 1453 | if (__HAL_UART_GET_FLAG(handle, HAL_UART_ERROR_NE)||(handle->ErrorCode & HAL_UART_ERROR_NE)!=0) { |
mbed_official | 69:41db872bbc3a | 1454 | __HAL_UART_CLEAR_FLAG(handle, HAL_UART_ERROR_NE); |
mbed_official | 55:814265bf5462 | 1455 | // not supported by mbed |
mbed_official | 55:814265bf5462 | 1456 | } |
mbed_official | 69:41db872bbc3a | 1457 | if (__HAL_UART_GET_FLAG(handle, HAL_UART_ERROR_FE)||(handle->ErrorCode & HAL_UART_ERROR_FE)!=0) { |
mbed_official | 69:41db872bbc3a | 1458 | __HAL_UART_CLEAR_FLAG(handle, HAL_UART_ERROR_FE); |
mbed_official | 69:41db872bbc3a | 1459 | return_event |= SERIAL_EVENT_RX_FRAMING_ERROR & SERIAL_OBJ(events); |
mbed_official | 55:814265bf5462 | 1460 | } |
mbed_official | 69:41db872bbc3a | 1461 | if (__HAL_UART_GET_FLAG(handle, HAL_UART_ERROR_ORE)||(handle->ErrorCode & HAL_UART_ERROR_ORE)!=0) { |
mbed_official | 69:41db872bbc3a | 1462 | __HAL_UART_CLEAR_FLAG(handle, HAL_UART_ERROR_ORE); |
mbed_official | 69:41db872bbc3a | 1463 | return_event |= SERIAL_EVENT_RX_OVERRUN_ERROR & SERIAL_OBJ(events); |
mbed_official | 55:814265bf5462 | 1464 | } |
mbed_official | 55:814265bf5462 | 1465 | |
mbed_official | 55:814265bf5462 | 1466 | //RX PART |
mbed_official | 55:814265bf5462 | 1467 | // increment rx_buff.pos |
mbed_official | 69:41db872bbc3a | 1468 | if (handle->RxXferSize !=0) { |
mbed_official | 69:41db872bbc3a | 1469 | obj->rx_buff.pos = handle->RxXferSize - handle->RxXferCount; |
mbed_official | 55:814265bf5462 | 1470 | } |
mbed_official | 69:41db872bbc3a | 1471 | if ((handle->RxXferCount==0)&&(obj->rx_buff.pos >= (obj->rx_buff.length - 1))) { |
mbed_official | 69:41db872bbc3a | 1472 | return_event |= SERIAL_EVENT_RX_COMPLETE & SERIAL_OBJ(events); |
mbed_official | 55:814265bf5462 | 1473 | } |
mbed_official | 55:814265bf5462 | 1474 | // Chek if Char_match is present |
mbed_official | 55:814265bf5462 | 1475 | if (SERIAL_OBJ(events) & SERIAL_EVENT_RX_CHARACTER_MATCH) { |
mbed_official | 55:814265bf5462 | 1476 | if (buf != NULL){ |
mbed_official | 69:41db872bbc3a | 1477 | while((buf[i] != obj->char_match)&&(i<handle->RxXferSize)){//for (i=0;i<UartHandle.RxXferSize;i++){ |
mbed_official | 55:814265bf5462 | 1478 | i++;//if (buf[i] == obj->char_match{ |
mbed_official | 55:814265bf5462 | 1479 | //} |
mbed_official | 55:814265bf5462 | 1480 | } |
mbed_official | 69:41db872bbc3a | 1481 | if (i<handle->RxXferSize){ |
mbed_official | 55:814265bf5462 | 1482 | obj->rx_buff.pos = i; |
mbed_official | 69:41db872bbc3a | 1483 | return_event |= SERIAL_EVENT_RX_CHARACTER_MATCH & SERIAL_OBJ(events); |
mbed_official | 55:814265bf5462 | 1484 | } |
mbed_official | 55:814265bf5462 | 1485 | } |
mbed_official | 55:814265bf5462 | 1486 | } |
mbed_official | 55:814265bf5462 | 1487 | return return_event; |
mbed_official | 55:814265bf5462 | 1488 | } |
mbed_official | 55:814265bf5462 | 1489 | |
mbed_official | 55:814265bf5462 | 1490 | /** Abort the ongoing TX transaction. It disables the enabled interupt for TX and |
mbed_official | 55:814265bf5462 | 1491 | * flush TX hardware buffer if TX FIFO is used |
mbed_official | 55:814265bf5462 | 1492 | * |
mbed_official | 55:814265bf5462 | 1493 | * @param obj The serial object |
mbed_official | 55:814265bf5462 | 1494 | */ |
mbed_official | 55:814265bf5462 | 1495 | void serial_tx_abort_asynch(serial_t *obj) |
mbed_official | 55:814265bf5462 | 1496 | { |
mbed_official | 69:41db872bbc3a | 1497 | UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)]; |
mbed_official | 69:41db872bbc3a | 1498 | __HAL_UART_DISABLE_IT(handle, UART_IT_TC|UART_IT_TXE); |
mbed_official | 69:41db872bbc3a | 1499 | // clear flags |
mbed_official | 69:41db872bbc3a | 1500 | __HAL_UART_CLEAR_PEFLAG(handle); |
mbed_official | 69:41db872bbc3a | 1501 | // reset states |
mbed_official | 69:41db872bbc3a | 1502 | handle->TxXferCount = 0; |
mbed_official | 69:41db872bbc3a | 1503 | // update handle state |
mbed_official | 69:41db872bbc3a | 1504 | if (handle->State == HAL_UART_STATE_BUSY_TX_RX) { |
mbed_official | 69:41db872bbc3a | 1505 | handle->State = HAL_UART_STATE_BUSY_RX; |
mbed_official | 69:41db872bbc3a | 1506 | } else { |
mbed_official | 69:41db872bbc3a | 1507 | handle->State = HAL_UART_STATE_READY; |
mbed_official | 69:41db872bbc3a | 1508 | } |
mbed_official | 55:814265bf5462 | 1509 | } |
mbed_official | 55:814265bf5462 | 1510 | |
mbed_official | 55:814265bf5462 | 1511 | /** Abort the ongoing RX transaction It disables the enabled interrupt for RX and |
mbed_official | 55:814265bf5462 | 1512 | * flush RX hardware buffer if RX FIFO is used |
mbed_official | 55:814265bf5462 | 1513 | * |
mbed_official | 55:814265bf5462 | 1514 | * @param obj The serial object |
mbed_official | 55:814265bf5462 | 1515 | */ |
mbed_official | 55:814265bf5462 | 1516 | void serial_rx_abort_asynch(serial_t *obj) |
mbed_official | 55:814265bf5462 | 1517 | { |
mbed_official | 69:41db872bbc3a | 1518 | UART_HandleTypeDef *handle = &UartHandle[SERIAL_OBJ(index)]; |
mbed_official | 69:41db872bbc3a | 1519 | __HAL_UART_DISABLE_IT(handle, UART_IT_RXNE); |
mbed_official | 69:41db872bbc3a | 1520 | // clear flags |
mbed_official | 69:41db872bbc3a | 1521 | __HAL_UART_CLEAR_PEFLAG(handle); |
mbed_official | 69:41db872bbc3a | 1522 | // reset states |
mbed_official | 69:41db872bbc3a | 1523 | handle->RxXferCount = 0; |
mbed_official | 69:41db872bbc3a | 1524 | // update handle state |
mbed_official | 69:41db872bbc3a | 1525 | if (handle->State == HAL_UART_STATE_BUSY_TX_RX) { |
mbed_official | 69:41db872bbc3a | 1526 | handle->State = HAL_UART_STATE_BUSY_TX; |
mbed_official | 69:41db872bbc3a | 1527 | } else { |
mbed_official | 69:41db872bbc3a | 1528 | handle->State = HAL_UART_STATE_READY; |
mbed_official | 69:41db872bbc3a | 1529 | } |
mbed_official | 55:814265bf5462 | 1530 | } |
mbed_official | 55:814265bf5462 | 1531 | |
mbed_official | 55:814265bf5462 | 1532 | #endif |
mbed_official | 55:814265bf5462 | 1533 | |
mbed_official | 60:6e6ed0527880 | 1534 | #if DEVICE_SERIAL_FC |
mbed_official | 60:6e6ed0527880 | 1535 | /** Set HW Control Flow |
mbed_official | 60:6e6ed0527880 | 1536 | * @param obj The serial object |
mbed_official | 60:6e6ed0527880 | 1537 | * @param type The Control Flow type (FlowControlNone, FlowControlRTS, FlowControlCTS, FlowControlRTSCTS) |
mbed_official | 60:6e6ed0527880 | 1538 | * @param rxflow Pin for the rxflow |
mbed_official | 60:6e6ed0527880 | 1539 | * @param txflow Pin for the txflow |
mbed_official | 60:6e6ed0527880 | 1540 | */ |
mbed_official | 60:6e6ed0527880 | 1541 | void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) |
mbed_official | 60:6e6ed0527880 | 1542 | { |
mbed_official | 60:6e6ed0527880 | 1543 | |
mbed_official | 60:6e6ed0527880 | 1544 | // Determine the UART to use (UART_1, UART_2, ...) |
mbed_official | 60:6e6ed0527880 | 1545 | UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS); |
mbed_official | 60:6e6ed0527880 | 1546 | UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS); |
mbed_official | 60:6e6ed0527880 | 1547 | |
mbed_official | 60:6e6ed0527880 | 1548 | // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object |
mbed_official | 69:41db872bbc3a | 1549 | UARTName instance = (UARTName)pinmap_merge(uart_cts, uart_rts); |
mbed_official | 60:6e6ed0527880 | 1550 | |
mbed_official | 69:41db872bbc3a | 1551 | MBED_ASSERT(instance != (UARTName)NC); |
mbed_official | 60:6e6ed0527880 | 1552 | |
mbed_official | 60:6e6ed0527880 | 1553 | if(type == FlowControlNone) { |
mbed_official | 60:6e6ed0527880 | 1554 | // Disable hardware flow control |
mbed_official | 60:6e6ed0527880 | 1555 | SERIAL_OBJ(hw_flow_ctl) = UART_HWCONTROL_NONE; |
mbed_official | 60:6e6ed0527880 | 1556 | } |
mbed_official | 60:6e6ed0527880 | 1557 | if (type == FlowControlRTS) { |
mbed_official | 60:6e6ed0527880 | 1558 | // Enable RTS |
mbed_official | 60:6e6ed0527880 | 1559 | MBED_ASSERT(uart_rts != (UARTName)NC); |
mbed_official | 60:6e6ed0527880 | 1560 | SERIAL_OBJ(hw_flow_ctl) = UART_HWCONTROL_RTS; |
mbed_official | 60:6e6ed0527880 | 1561 | SERIAL_OBJ(pin_rts) = rxflow; |
mbed_official | 60:6e6ed0527880 | 1562 | // Enable the pin for RTS function |
mbed_official | 60:6e6ed0527880 | 1563 | pinmap_pinout(rxflow, PinMap_UART_RTS); |
mbed_official | 60:6e6ed0527880 | 1564 | } |
mbed_official | 60:6e6ed0527880 | 1565 | if (type == FlowControlCTS) { |
mbed_official | 60:6e6ed0527880 | 1566 | // Enable CTS |
mbed_official | 60:6e6ed0527880 | 1567 | MBED_ASSERT(uart_cts != (UARTName)NC); |
mbed_official | 60:6e6ed0527880 | 1568 | SERIAL_OBJ(hw_flow_ctl) = UART_HWCONTROL_CTS; |
mbed_official | 60:6e6ed0527880 | 1569 | SERIAL_OBJ(pin_cts) = txflow; |
mbed_official | 60:6e6ed0527880 | 1570 | // Enable the pin for CTS function |
mbed_official | 60:6e6ed0527880 | 1571 | pinmap_pinout(txflow, PinMap_UART_CTS); |
mbed_official | 60:6e6ed0527880 | 1572 | } |
mbed_official | 60:6e6ed0527880 | 1573 | if (type == FlowControlRTSCTS) { |
mbed_official | 60:6e6ed0527880 | 1574 | // Enable CTS & RTS |
mbed_official | 60:6e6ed0527880 | 1575 | MBED_ASSERT(uart_rts != (UARTName)NC); |
mbed_official | 60:6e6ed0527880 | 1576 | MBED_ASSERT(uart_cts != (UARTName)NC); |
mbed_official | 60:6e6ed0527880 | 1577 | SERIAL_OBJ(hw_flow_ctl) = UART_HWCONTROL_RTS_CTS; |
mbed_official | 60:6e6ed0527880 | 1578 | SERIAL_OBJ(pin_rts) = rxflow; |
mbed_official | 60:6e6ed0527880 | 1579 | SERIAL_OBJ(pin_cts) = txflow; |
mbed_official | 60:6e6ed0527880 | 1580 | // Enable the pin for CTS function |
mbed_official | 60:6e6ed0527880 | 1581 | pinmap_pinout(txflow, PinMap_UART_CTS); |
mbed_official | 60:6e6ed0527880 | 1582 | // Enable the pin for RTS function |
mbed_official | 60:6e6ed0527880 | 1583 | pinmap_pinout(rxflow, PinMap_UART_RTS); |
mbed_official | 60:6e6ed0527880 | 1584 | } |
mbed_official | 69:41db872bbc3a | 1585 | init_uart(obj, instance); |
mbed_official | 60:6e6ed0527880 | 1586 | } |
mbed_official | 55:814265bf5462 | 1587 | #endif |
mbed_official | 60:6e6ed0527880 | 1588 | #endif |