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Dependencies: MAX30003 max32630fthr
Fork of MAX30003_Demo_Plot by
main.cpp
00001 /******************************************************************************* 00002 * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved. 00003 * 00004 * Permission is hereby granted, free of charge, to any person obtaining a 00005 * copy of this software and associated documentation files (the "Software"), 00006 * to deal in the Software without restriction, including without limitation 00007 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 00008 * and/or sell copies of the Software, and to permit persons to whom the 00009 * Software is furnished to do so, subject to the following conditions: 00010 * 00011 * The above copyright notice and this permission notice shall be included 00012 * in all copies or substantial portions of the Software. 00013 * 00014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 00015 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 00016 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 00017 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES 00018 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 00019 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 00020 * OTHER DEALINGS IN THE SOFTWARE. 00021 * 00022 * Except as contained in this notice, the name of Maxim Integrated 00023 * Products, Inc. shall not be used except as stated in the Maxim Integrated 00024 * Products, Inc. Branding Policy. 00025 * 00026 * The mere transfer of this software does not imply any licenses 00027 * of trade secrets, proprietary technology, copyrights, patents, 00028 * trademarks, maskwork rights, or any other form of intellectual 00029 * property whatsoever. Maxim Integrated Products, Inc. retains all 00030 * ownership rights. 00031 ******************************************************************************* 00032 */ 00033 00034 00035 00036 #include "mbed.h" 00037 #include "max32630fthr.h" 00038 #include "MAX30003.h" 00039 00040 MAX32630FTHR pegasus(MAX32630FTHR::VIO_3V3); 00041 00042 void ecg_config(MAX30003 &ecgAFE); 00043 00044 /* ECG FIFO nearly full callback */ 00045 volatile bool ecgFIFOIntFlag = 0; 00046 void ecgFIFO_callback() { 00047 00048 ecgFIFOIntFlag = 1; 00049 00050 } 00051 00052 int main() 00053 { 00054 00055 // Constants 00056 const int EINT_STATUS_MASK = 1 << 23; 00057 const int FIFO_OVF_MASK = 0x7; 00058 const int FIFO_VALID_SAMPLE_MASK = 0x0; 00059 const int FIFO_FAST_SAMPLE_MASK = 0x1; 00060 const int ETAG_BITS_MASK = 0x7; 00061 00062 // Ports and serial connections 00063 Serial pc(USBTX, USBRX); // Use USB debug probe for serial link 00064 pc.baud(115200); // Baud rate = 115200 00065 00066 DigitalOut rLed(LED1, LED_OFF); // Debug LEDs 00067 DigitalOut gLed(LED2, LED_OFF); 00068 DigitalOut bLed(LED3, LED_OFF); 00069 00070 InterruptIn ecgFIFO_int(P5_4); // Config P5_4 as int. in for the 00071 ecgFIFO_int.fall(&ecgFIFO_callback); // ecg FIFO almost full interrupt 00072 00073 SPI spiBus(SPI2_MOSI, SPI2_MISO, SPI2_SCK); // SPI bus, P5_1 = MOSI, 00074 // P5_2 = MISO, P5_0 = SCK 00075 00076 MAX30003 ecgAFE(spiBus, P5_3); // New MAX30003 on spiBus, CS = P5_3 00077 ecg_config(ecgAFE); // Config ECG 00078 00079 00080 ecgAFE.writeRegister( MAX30003::SYNCH , 0); 00081 00082 uint32_t ecgFIFO, readECGSamples, idx, ETAG[32], status; 00083 int16_t ecgSample[32]; 00084 00085 while(1) { 00086 00087 // Read back ECG samples from the FIFO 00088 if( ecgFIFOIntFlag ) { 00089 00090 ecgFIFOIntFlag = 0; 00091 status = ecgAFE.readRegister( MAX30003::STATUS ); // Read the STATUS register 00092 00093 // Check if EINT interrupt asserted 00094 if ( ( status & EINT_STATUS_MASK ) == EINT_STATUS_MASK ) { 00095 00096 readECGSamples = 0; // Reset sample counter 00097 00098 do { 00099 ecgFIFO = ecgAFE.readRegister( MAX30003::ECG_FIFO ); // Read FIFO 00100 ecgSample[readECGSamples] = ecgFIFO >> 8; // Isolate voltage data 00101 ETAG[readECGSamples] = ( ecgFIFO >> 3 ) & ETAG_BITS_MASK; // Isolate ETAG 00102 readECGSamples++; // Increment sample counter 00103 00104 // Check that sample is not last sample in FIFO 00105 } while ( ETAG[readECGSamples-1] == FIFO_VALID_SAMPLE_MASK || 00106 ETAG[readECGSamples-1] == FIFO_FAST_SAMPLE_MASK ); 00107 00108 // Check if FIFO has overflowed 00109 if( ETAG[readECGSamples - 1] == FIFO_OVF_MASK ){ 00110 ecgAFE.writeRegister( MAX30003::FIFO_RST , 0); // Reset FIFO 00111 } 00112 00113 // Print results 00114 for( idx = 0; idx < readECGSamples; idx++ ) { 00115 pc.printf("%6d\r\n", ecgSample[idx]); 00116 } 00117 00118 } 00119 } 00120 } 00121 } 00122 00123 00124 00125 00126 void ecg_config(MAX30003& ecgAFE) { 00127 00128 // Reset ECG to clear registers 00129 ecgAFE.writeRegister( MAX30003::SW_RST , 0); 00130 00131 // General config register setting 00132 MAX30003::GeneralConfiguration_u CNFG_GEN_r; 00133 CNFG_GEN_r.bits.en_ecg = 1; // Enable ECG channel 00134 CNFG_GEN_r.bits.rbiasn = 1; // Enable resistive bias on negative input 00135 CNFG_GEN_r.bits.rbiasp = 1; // Enable resistive bias on positive input 00136 CNFG_GEN_r.bits.en_rbias = 1; // Enable resistive bias 00137 CNFG_GEN_r.bits.imag = 2; // Current magnitude = 10nA 00138 CNFG_GEN_r.bits.en_dcloff = 1; // Enable DC lead-off detection 00139 ecgAFE.writeRegister( MAX30003::CNFG_GEN , CNFG_GEN_r.all); 00140 00141 00142 // ECG Config register setting 00143 MAX30003::ECGConfiguration_u CNFG_ECG_r; 00144 CNFG_ECG_r.bits.dlpf = 1; // Digital LPF cutoff = 40Hz 00145 CNFG_ECG_r.bits.dhpf = 1; // Digital HPF cutoff = 0.5Hz 00146 CNFG_ECG_r.bits.gain = 3; // ECG gain = 160V/V 00147 CNFG_ECG_r.bits.rate = 2; // Sample rate = 128 sps 00148 ecgAFE.writeRegister( MAX30003::CNFG_ECG , CNFG_ECG_r.all); 00149 00150 00151 //R-to-R configuration 00152 MAX30003::RtoR1Configuration_u CNFG_RTOR_r; 00153 CNFG_RTOR_r.bits.en_rtor = 1; // Enable R-to-R detection 00154 ecgAFE.writeRegister( MAX30003::CNFG_RTOR1 , CNFG_RTOR_r.all); 00155 00156 00157 //Manage interrupts register setting 00158 MAX30003::ManageInterrupts_u MNG_INT_r; 00159 MNG_INT_r.bits.efit = 0b00011; // Assert EINT w/ 4 unread samples 00160 MNG_INT_r.bits.clr_rrint = 0b01; // Clear R-to-R on RTOR reg. read back 00161 ecgAFE.writeRegister( MAX30003::MNGR_INT , MNG_INT_r.all); 00162 00163 00164 //Enable interrupts register setting 00165 MAX30003::EnableInterrupts_u EN_INT_r; 00166 EN_INT_r.all = 0; 00167 EN_INT_r.bits.en_eint = 1; // Enable EINT interrupt 00168 EN_INT_r.bits.en_rrint = 0; // Disable R-to-R interrupt 00169 EN_INT_r.bits.intb_type = 3; // Open-drain NMOS with internal pullup 00170 ecgAFE.writeRegister( MAX30003::EN_INT , EN_INT_r.all); 00171 00172 00173 //Dyanmic modes config 00174 MAX30003::ManageDynamicModes_u MNG_DYN_r; 00175 MNG_DYN_r.bits.fast = 0; // Fast recovery mode disabled 00176 ecgAFE.writeRegister( MAX30003::MNGR_DYN , MNG_DYN_r.all); 00177 00178 // MUX Config 00179 MAX30003::MuxConfiguration_u CNFG_MUX_r; 00180 CNFG_MUX_r.bits.openn = 0; // Connect ECGN to AFE channel 00181 CNFG_MUX_r.bits.openp = 0; // Connect ECGP to AFE channel 00182 ecgAFE.writeRegister( MAX30003::CNFG_EMUX , CNFG_MUX_r.all); 00183 00184 return; 00185 } 00186
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