James Reynolds
/
AD594x Driver
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(wiki syntax)
ADCCLKSRC_Const
[MISC_Block_Const]
Select ADC clock source. More...
Select ADC clock source.
The maximum clock is 32MHz.
- Warning:
- The ADC raw data update rate is equal to ADCClock/20. When ADC clock is 32MHz, sample rate is 1.6MSPS. The SINC3 filter clock are sourced from ADC clock and should be limited to 16MHz. When ADC clock is set to 32MHz. Clear bit ADCFILTERCON.BIT0 to enable the SINC3 clock divider.
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