James Reynolds
/
AD594x Driver
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Embed:
(wiki syntax)
Show/hide line numbers
ad5940.h
Go to the documentation of this file.
00001 /** 00002 * @file ad5940.h 00003 * @brief AD5940 library. This file contains all AD5940 library functions. 00004 * @author ADI 00005 * @date March 2019 00006 * @par Revision History: 00007 * 00008 * Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. 00009 * 00010 * This software is proprietary to Analog Devices, Inc. and its licensors. 00011 * By using this software you agree to the terms of the associated 00012 * Analog Devices Software License Agreement. 00013 **/ 00014 00015 #ifdef __cplusplus 00016 extern "C" { 00017 #endif 00018 00019 #ifndef _AD5940_H_ 00020 #define _AD5940_H_ 00021 00022 00023 00024 #include "math.h" 00025 #include "string.h" 00026 #include "stdio.h" 00027 /** @addtogroup AD5940_Library 00028 * @{ 00029 */ 00030 00031 /** 00032 * Select the correct chip. 00033 * Recommend to define this in your compiler. 00034 * */ 00035 //#define CHIPSEL_M355 /**< ADuCM355 */ 00036 #define CHIPSEL_594X /**< AD5940 or AD5941 */ 00037 00038 /* library version number */ 00039 #define AD5940LIB_VER_MAJOR 0 /**< Major number */ 00040 #define AD5940LIB_VER_MINOR 2 /**< Minor number */ 00041 #define AD5940LIB_VER_PATCH 1 /**< Path number */ 00042 #define AD5940LIB_VER (AD5940LIB_VER_MAJOR<<16)|(AD5940LIB_VER_MINOR<<8)|(AD5940LIB_VER_PATCH) 00043 00044 //#define ADI_DEBUG /**< Comment this line to remove debug info. */ 00045 00046 #ifdef ADI_DEBUG 00047 #define ADI_Print printf /**< Select the method to print out debug message */ 00048 #endif 00049 00050 #if defined(CHIPSEL_M355) && defined(CHIPSEL_594X) 00051 #error Please select the correct chip by define CHIPSEL_M355 or CHIPSEL_594X. 00052 #endif 00053 00054 #if !defined(CHIPSEL_M355) && !defined(CHIPSEL_594X) 00055 #error Please select the correct chip by define CHIPSEL_M355 or CHIPSEL_594X. 00056 #endif 00057 00058 /** 00059 * @cond 00060 * @defgroup AD5940RegistersBitfields 00061 * @brief All AD5940 registers and bitfields definition. 00062 * @{ 00063 */ 00064 //#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) 00065 #include <stdint.h> 00066 //#endif /* _LANGUAGE_C */ 00067 00068 #ifndef __ADI_GENERATED_DEF_HEADERS__ 00069 #define __ADI_GENERATED_DEF_HEADERS__ 1 00070 #endif 00071 00072 #define __ADI_HAS_AGPIO__ 1 00073 #define __ADI_HAS_ALLON__ 1 00074 #define __ADI_HAS_INTC__ 1 00075 #define __ADI_HAS_AFECON__ 1 00076 #define __ADI_HAS_WUPTMR__ 1 00077 #define __ADI_HAS_AFE__ 1 00078 00079 /* ============================================================================================================================ 00080 GPIO 00081 ============================================================================================================================ */ 00082 00083 /* ============================================================================================================================ 00084 AGPIO 00085 ============================================================================================================================ */ 00086 #define REG_AGPIO_GP0CON_RESET 0x00000000 /* Reset Value for GP0CON */ 00087 #define REG_AGPIO_GP0CON 0x00000000 /* AGPIO GPIO Port 0 Configuration */ 00088 #define REG_AGPIO_GP0OEN_RESET 0x00000000 /* Reset Value for GP0OEN */ 00089 #define REG_AGPIO_GP0OEN 0x00000004 /* AGPIO GPIO Port 0 Output Enable */ 00090 #define REG_AGPIO_GP0PE_RESET 0x00000000 /* Reset Value for GP0PE */ 00091 #define REG_AGPIO_GP0PE 0x00000008 /* AGPIO GPIO Port 0 Pullup/Pulldown Enable */ 00092 #define REG_AGPIO_GP0IEN_RESET 0x00000000 /* Reset Value for GP0IEN */ 00093 #define REG_AGPIO_GP0IEN 0x0000000C /* AGPIO GPIO Port 0 Input Path Enable */ 00094 #define REG_AGPIO_GP0IN_RESET 0x00000000 /* Reset Value for GP0IN */ 00095 #define REG_AGPIO_GP0IN 0x00000010 /* AGPIO GPIO Port 0 Registered Data Input */ 00096 #define REG_AGPIO_GP0OUT_RESET 0x00000000 /* Reset Value for GP0OUT */ 00097 #define REG_AGPIO_GP0OUT 0x00000014 /* AGPIO GPIO Port 0 Data Output */ 00098 #define REG_AGPIO_GP0SET_RESET 0x00000000 /* Reset Value for GP0SET */ 00099 #define REG_AGPIO_GP0SET 0x00000018 /* AGPIO GPIO Port 0 Data Out Set */ 00100 #define REG_AGPIO_GP0CLR_RESET 0x00000000 /* Reset Value for GP0CLR */ 00101 #define REG_AGPIO_GP0CLR 0x0000001C /* AGPIO GPIO Port 0 Data Out Clear */ 00102 #define REG_AGPIO_GP0TGL_RESET 0x00000000 /* Reset Value for GP0TGL */ 00103 #define REG_AGPIO_GP0TGL 0x00000020 /* AGPIO GPIO Port 0 Pin Toggle */ 00104 00105 /* ============================================================================================================================ 00106 AGPIO Register BitMasks, Positions & Enumerations 00107 ============================================================================================================================ */ 00108 /* ------------------------------------------------------------------------------------------------------------------------- 00109 AGPIO_GP0CON Pos/Masks Description 00110 ------------------------------------------------------------------------------------------------------------------------- */ 00111 #define BITP_AGPIO_GP0CON_PIN7CFG 14 /* P0.7 Configuration Bits */ 00112 #define BITP_AGPIO_GP0CON_PIN6CFG 12 /* P0.6 Configuration Bits */ 00113 #define BITP_AGPIO_GP0CON_PIN5CFG 10 /* P0.5 Configuration Bits */ 00114 #define BITP_AGPIO_GP0CON_PIN4CFG 8 /* P0.4 Configuration Bits */ 00115 #define BITP_AGPIO_GP0CON_PIN3CFG 6 /* P0.3 Configuration Bits */ 00116 #define BITP_AGPIO_GP0CON_PIN2CFG 4 /* P0.2 Configuration Bits */ 00117 #define BITP_AGPIO_GP0CON_PIN1CFG 2 /* P0.1 Configuration Bits */ 00118 #define BITP_AGPIO_GP0CON_PIN0CFG 0 /* P0.0 Configuration Bits */ 00119 #define BITM_AGPIO_GP0CON_PIN7CFG 0x0000C000 /* P0.7 Configuration Bits */ 00120 #define BITM_AGPIO_GP0CON_PIN6CFG 0x00003000 /* P0.6 Configuration Bits */ 00121 #define BITM_AGPIO_GP0CON_PIN5CFG 0x00000C00 /* P0.5 Configuration Bits */ 00122 #define BITM_AGPIO_GP0CON_PIN4CFG 0x00000300 /* P0.4 Configuration Bits */ 00123 #define BITM_AGPIO_GP0CON_PIN3CFG 0x000000C0 /* P0.3 Configuration Bits */ 00124 #define BITM_AGPIO_GP0CON_PIN2CFG 0x00000030 /* P0.2 Configuration Bits */ 00125 #define BITM_AGPIO_GP0CON_PIN1CFG 0x0000000C /* P0.1 Configuration Bits */ 00126 #define BITM_AGPIO_GP0CON_PIN0CFG 0x00000003 /* P0.0 Configuration Bits */ 00127 00128 /* ------------------------------------------------------------------------------------------------------------------------- 00129 AGPIO_GP0OEN Pos/Masks Description 00130 ------------------------------------------------------------------------------------------------------------------------- */ 00131 #define BITP_AGPIO_GP0OEN_OEN 0 /* Pin Output Drive Enable */ 00132 #define BITM_AGPIO_GP0OEN_OEN 0x000000FF /* Pin Output Drive Enable */ 00133 00134 /* ------------------------------------------------------------------------------------------------------------------------- 00135 AGPIO_GP0PE Pos/Masks Description 00136 ------------------------------------------------------------------------------------------------------------------------- */ 00137 #define BITP_AGPIO_GP0PE_PE 0 /* Pin Pull Enable */ 00138 #define BITM_AGPIO_GP0PE_PE 0x000000FF /* Pin Pull Enable */ 00139 00140 /* ------------------------------------------------------------------------------------------------------------------------- 00141 AGPIO_GP0IEN Pos/Masks Description 00142 ------------------------------------------------------------------------------------------------------------------------- */ 00143 #define BITP_AGPIO_GP0IEN_IEN 0 /* Input Path Enable */ 00144 #define BITM_AGPIO_GP0IEN_IEN 0x000000FF /* Input Path Enable */ 00145 00146 /* ------------------------------------------------------------------------------------------------------------------------- 00147 AGPIO_GP0IN Pos/Masks Description 00148 ------------------------------------------------------------------------------------------------------------------------- */ 00149 #define BITP_AGPIO_GP0IN_IN 0 /* Registered Data Input */ 00150 #define BITM_AGPIO_GP0IN_IN 0x000000FF /* Registered Data Input */ 00151 00152 /* ------------------------------------------------------------------------------------------------------------------------- 00153 AGPIO_GP0OUT Pos/Masks Description 00154 ------------------------------------------------------------------------------------------------------------------------- */ 00155 #define BITP_AGPIO_GP0OUT_OUT 0 /* Data Out */ 00156 #define BITM_AGPIO_GP0OUT_OUT 0x000000FF /* Data Out */ 00157 00158 /* ------------------------------------------------------------------------------------------------------------------------- 00159 AGPIO_GP0SET Pos/Masks Description 00160 ------------------------------------------------------------------------------------------------------------------------- */ 00161 #define BITP_AGPIO_GP0SET_SET 0 /* Set the Output HIGH */ 00162 #define BITM_AGPIO_GP0SET_SET 0x000000FF /* Set the Output HIGH */ 00163 00164 /* ------------------------------------------------------------------------------------------------------------------------- 00165 AGPIO_GP0CLR Pos/Masks Description 00166 ------------------------------------------------------------------------------------------------------------------------- */ 00167 #define BITP_AGPIO_GP0CLR_CLR 0 /* Set the Output LOW */ 00168 #define BITM_AGPIO_GP0CLR_CLR 0x000000FF /* Set the Output LOW */ 00169 00170 /* ------------------------------------------------------------------------------------------------------------------------- 00171 AGPIO_GP0TGL Pos/Masks Description 00172 ------------------------------------------------------------------------------------------------------------------------- */ 00173 #define BITP_AGPIO_GP0TGL_TGL 0 /* Toggle the Output */ 00174 #define BITM_AGPIO_GP0TGL_TGL 0x000000FF /* Toggle the Output */ 00175 00176 00177 /* ============================================================================================================================ 00178 00179 ============================================================================================================================ */ 00180 00181 /* ============================================================================================================================ 00182 AFECON 00183 ============================================================================================================================ */ 00184 #define REG_AFECON_ADIID_RESET 0x00000000 /* Reset Value for ADIID */ 00185 #define REG_AFECON_ADIID 0x00000400 /* AFECON ADI Identification */ 00186 #define REG_AFECON_CHIPID_RESET 0x00000000 /* Reset Value for CHIPID */ 00187 #define REG_AFECON_CHIPID 0x00000404 /* AFECON Chip Identification */ 00188 #define REG_AFECON_CLKCON0_RESET 0x00000441 /* Reset Value for CLKCON0 */ 00189 #define REG_AFECON_CLKCON0 0x00000408 /* AFECON Clock Divider Configuration */ 00190 #define REG_AFECON_CLKEN1_RESET 0x000002C0 /* Reset Value for CLKEN1 */ 00191 #define REG_AFECON_CLKEN1 0x00000410 /* AFECON Clock Gate Enable */ 00192 #define REG_AFECON_CLKSEL_RESET 0x00000000 /* Reset Value for CLKSEL */ 00193 #define REG_AFECON_CLKSEL 0x00000414 /* AFECON Clock Select */ 00194 #define REG_AFECON_CLKCON0KEY_RESET 0x00000000 /* Reset Value for CLKCON0KEY */ 00195 #define REG_AFECON_CLKCON0KEY 0x00000420 /* AFECON Enable Clock Division to 8Mhz,4Mhz and 2Mhz */ 00196 #define REG_AFECON_SWRSTCON_RESET 0x00000001 /* Reset Value for SWRSTCON */ 00197 #define REG_AFECON_SWRSTCON 0x00000424 /* AFECON Software Reset */ 00198 #define REG_AFECON_TRIGSEQ_RESET 0x00000000 /* Reset Value for TRIGSEQ */ 00199 #define REG_AFECON_TRIGSEQ 0x00000430 /* AFECON Trigger Sequence */ 00200 00201 /* ============================================================================================================================ 00202 AFECON Register BitMasks, Positions & Enumerations 00203 ============================================================================================================================ */ 00204 /* ------------------------------------------------------------------------------------------------------------------------- 00205 AFECON_ADIID Pos/Masks Description 00206 ------------------------------------------------------------------------------------------------------------------------- */ 00207 #define BITP_AFECON_ADIID_ADIID 0 /* ADI Identifier. */ 00208 #define BITM_AFECON_ADIID_ADIID 0x0000FFFF /* ADI Identifier. */ 00209 00210 /* ------------------------------------------------------------------------------------------------------------------------- 00211 AFECON_CHIPID Pos/Masks Description 00212 ------------------------------------------------------------------------------------------------------------------------- */ 00213 #define BITP_AFECON_CHIPID_PARTID 4 /* Part Identifier */ 00214 #define BITP_AFECON_CHIPID_REVISION 0 /* Silicon Revision Number */ 00215 #define BITM_AFECON_CHIPID_PARTID 0x0000FFF0 /* Part Identifier */ 00216 #define BITM_AFECON_CHIPID_REVISION 0x0000000F /* Silicon Revision Number */ 00217 00218 /* ------------------------------------------------------------------------------------------------------------------------- 00219 AFECON_CLKCON0 Pos/Masks Description 00220 ------------------------------------------------------------------------------------------------------------------------- */ 00221 #define BITP_AFECON_CLKCON0_SFFTCLKDIVCNT 10 /* SFFT Clock Divider Configuration */ 00222 #define BITP_AFECON_CLKCON0_ADCCLKDIV 6 /* ADC Clock Divider Configuration */ 00223 #define BITP_AFECON_CLKCON0_SYSCLKDIV 0 /* System Clock Divider Configuration */ 00224 #define BITM_AFECON_CLKCON0_SFFTCLKDIVCNT 0x0000FC00 /* SFFT Clock Divider Configuration */ 00225 #define BITM_AFECON_CLKCON0_ADCCLKDIV 0x000003C0 /* ADC Clock Divider Configuration */ 00226 #define BITM_AFECON_CLKCON0_SYSCLKDIV 0x0000003F /* System Clock Divider Configuration */ 00227 00228 /* ------------------------------------------------------------------------------------------------------------------------- 00229 AFECON_CLKEN1 Pos/Masks Description 00230 ------------------------------------------------------------------------------------------------------------------------- */ 00231 #define BITP_AFECON_CLKEN1_GPT1DIS 7 /* GPT1 Clock Enable */ 00232 #define BITP_AFECON_CLKEN1_GPT0DIS 6 /* GPT0 Clock Enable */ 00233 #define BITP_AFECON_CLKEN1_ACLKDIS 5 /* ACLK Clock Enable */ 00234 #define BITM_AFECON_CLKEN1_GPT1DIS 0x00000080 /* GPT1 Clock Enable */ 00235 #define BITM_AFECON_CLKEN1_GPT0DIS 0x00000040 /* GPT0 Clock Enable */ 00236 #define BITM_AFECON_CLKEN1_ACLKDIS 0x00000020 /* ACLK Clock Enable */ 00237 00238 /* ------------------------------------------------------------------------------------------------------------------------- 00239 AFECON_CLKSEL Pos/Masks Description 00240 ------------------------------------------------------------------------------------------------------------------------- */ 00241 #define BITP_AFECON_CLKSEL_ADCCLKSEL 2 /* Select ADC Clock Source */ 00242 #define BITP_AFECON_CLKSEL_SYSCLKSEL 0 /* Select System Clock Source */ 00243 #define BITM_AFECON_CLKSEL_ADCCLKSEL 0x0000000C /* Select ADC Clock Source */ 00244 #define BITM_AFECON_CLKSEL_SYSCLKSEL 0x00000003 /* Select System Clock Source */ 00245 00246 /* ------------------------------------------------------------------------------------------------------------------------- 00247 AFECON_CLKCON0KEY Pos/Masks Description 00248 ------------------------------------------------------------------------------------------------------------------------- */ 00249 #define BITP_AFECON_CLKCON0KEY_DIVSYSCLK_ULP_EN 0 /* Enable Clock Division to 8Mhz,4Mhz and 2Mhz */ 00250 #define BITM_AFECON_CLKCON0KEY_DIVSYSCLK_ULP_EN 0x0000FFFF /* Enable Clock Division to 8Mhz,4Mhz and 2Mhz */ 00251 00252 /* ------------------------------------------------------------------------------------------------------------------------- 00253 AFECON_SWRSTCON Pos/Masks Description 00254 ------------------------------------------------------------------------------------------------------------------------- */ 00255 #define BITP_AFECON_SWRSTCON_SWRSTL 0 /* Software Reset */ 00256 #define BITM_AFECON_SWRSTCON_SWRSTL 0x0000FFFF /* Software Reset */ 00257 00258 /* ------------------------------------------------------------------------------------------------------------------------- 00259 AFECON_TRIGSEQ Pos/Masks Description 00260 ------------------------------------------------------------------------------------------------------------------------- */ 00261 #define BITP_AFECON_TRIGSEQ_TRIG3 3 /* Trigger Sequence 3 */ 00262 #define BITP_AFECON_TRIGSEQ_TRIG2 2 /* Trigger Sequence 2 */ 00263 #define BITP_AFECON_TRIGSEQ_TRIG1 1 /* Trigger Sequence 1 */ 00264 #define BITP_AFECON_TRIGSEQ_TRIG0 0 /* Trigger Sequence 0 */ 00265 #define BITM_AFECON_TRIGSEQ_TRIG3 0x00000008 /* Trigger Sequence 3 */ 00266 #define BITM_AFECON_TRIGSEQ_TRIG2 0x00000004 /* Trigger Sequence 2 */ 00267 #define BITM_AFECON_TRIGSEQ_TRIG1 0x00000002 /* Trigger Sequence 1 */ 00268 #define BITM_AFECON_TRIGSEQ_TRIG0 0x00000001 /* Trigger Sequence 0 */ 00269 00270 /* ============================================================================================================================ 00271 AFEWDT 00272 ============================================================================================================================ */ 00273 #define REG_AFEWDT_WDTLD 0x00000900 /* AFEWDT Watchdog Timer Load Value */ 00274 #define REG_AFEWDT_WDTVALS 0x00000904 /* AFEWDT Current Count Value */ 00275 #define REG_AFEWDT_WDTCON 0x00000908 /* AFEWDT Watchdog Timer Control Register */ 00276 #define REG_AFEWDT_WDTCLRI 0x0000090C /* AFEWDT Refresh Watchdog Register */ 00277 #define REG_AFEWDT_WDTSTA 0x00000918 /* AFEWDT Timer Status */ 00278 #define REG_AFEWDT_WDTMINLD 0x0000091C /* AFEWDT Minimum Load Value */ 00279 00280 /* ============================================================================================================================ 00281 AFEWDT Register BitMasks, Positions & Enumerations 00282 ============================================================================================================================ */ 00283 /* ------------------------------------------------------------------------------------------------------------------------- 00284 AFEWDT_WDTLD Pos/Masks Description 00285 ------------------------------------------------------------------------------------------------------------------------- */ 00286 #define BITP_AFEWDT_WDTLD_LOAD 0 /* WDT Load Value */ 00287 #define BITM_AFEWDT_WDTLD_LOAD (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* WDT Load Value */ 00288 00289 /* ------------------------------------------------------------------------------------------------------------------------- 00290 AFEWDT_WDTVALS Pos/Masks Description 00291 ------------------------------------------------------------------------------------------------------------------------- */ 00292 #define BITP_AFEWDT_WDTVALS_CCOUNT 0 /* Current WDT Count Value. */ 00293 #define BITM_AFEWDT_WDTVALS_CCOUNT (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Current WDT Count Value. */ 00294 00295 /* ------------------------------------------------------------------------------------------------------------------------- 00296 AFEWDT_WDTCON Pos/Masks Description 00297 ------------------------------------------------------------------------------------------------------------------------- */ 00298 #define BITP_AFEWDT_WDTCON_RESERVED_15_11 11 /* RESERVED */ 00299 #define BITP_AFEWDT_WDTCON_WDTIRQEN 10 /* WDT Interrupt Enable */ 00300 #define BITP_AFEWDT_WDTCON_MINLOAD_EN 9 /* Timer Window Control */ 00301 #define BITP_AFEWDT_WDTCON_CLKDIV2 8 /* Clock Source */ 00302 #define BITP_AFEWDT_WDTCON_RESERVED1_7 7 /* Reserved */ 00303 #define BITP_AFEWDT_WDTCON_MDE 6 /* Timer Mode Select */ 00304 #define BITP_AFEWDT_WDTCON_EN 5 /* Timer Enable */ 00305 #define BITP_AFEWDT_WDTCON_PRE 2 /* Prescaler. */ 00306 #define BITP_AFEWDT_WDTCON_IRQ 1 /* WDT Interrupt Enable */ 00307 #define BITP_AFEWDT_WDTCON_PDSTOP 0 /* Power Down Stop Enable */ 00308 #define BITM_AFEWDT_WDTCON_RESERVED_15_11 (_ADI_MSK_3(0x0000F800,0x0000F800U, uint16_t )) /* RESERVED */ 00309 #define BITM_AFEWDT_WDTCON_WDTIRQEN (_ADI_MSK_3(0x00000400,0x00000400U, uint16_t )) /* WDT Interrupt Enable */ 00310 #define BITM_AFEWDT_WDTCON_MINLOAD_EN (_ADI_MSK_3(0x00000200,0x00000200U, uint16_t )) /* Timer Window Control */ 00311 #define BITM_AFEWDT_WDTCON_CLKDIV2 (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Clock Source */ 00312 #define BITM_AFEWDT_WDTCON_RESERVED1_7 (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Reserved */ 00313 #define BITM_AFEWDT_WDTCON_MDE (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Timer Mode Select */ 00314 #define BITM_AFEWDT_WDTCON_EN (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Timer Enable */ 00315 #define BITM_AFEWDT_WDTCON_PRE (_ADI_MSK_3(0x0000000C,0x0000000CU, uint16_t )) /* Prescaler. */ 00316 #define BITM_AFEWDT_WDTCON_IRQ (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* WDT Interrupt Enable */ 00317 #define BITM_AFEWDT_WDTCON_PDSTOP (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Power Down Stop Enable */ 00318 #define ENUM_AFEWDT_WDTCON_RESET (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* IRQ: Watchdog Timer timeout creates a reset. */ 00319 #define ENUM_AFEWDT_WDTCON_INTERRUPT (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* IRQ: Watchdog Timer timeout creates an interrupt instead of reset. */ 00320 #define ENUM_AFEWDT_WDTCON_CONTINUE (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* PDSTOP: Continue Counting When In Hibernate */ 00321 #define ENUM_AFEWDT_WDTCON_STOP (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* PDSTOP: Stop Counter When In Hibernate. */ 00322 00323 /* ------------------------------------------------------------------------------------------------------------------------- 00324 AFEWDT_WDTCLRI Pos/Masks Description 00325 ------------------------------------------------------------------------------------------------------------------------- */ 00326 #define BITP_AFEWDT_WDTCLRI_CLRWDG 0 /* Refresh Register */ 00327 #define BITM_AFEWDT_WDTCLRI_CLRWDG (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Refresh Register */ 00328 00329 /* ------------------------------------------------------------------------------------------------------------------------- 00330 AFEWDT_WDTSTA Pos/Masks Description 00331 ------------------------------------------------------------------------------------------------------------------------- */ 00332 #define BITP_AFEWDT_WDTSTA_RESERVED_15_7 7 /* RESERVED */ 00333 #define BITP_AFEWDT_WDTSTA_TMINLD 6 /* WDTMINLD Write Status */ 00334 #define BITP_AFEWDT_WDTSTA_OTPWRDONE 5 /* Reset Type Status */ 00335 #define BITP_AFEWDT_WDTSTA_LOCK 4 /* Lock Status */ 00336 #define BITP_AFEWDT_WDTSTA_CON 3 /* WDTCON Write Status */ 00337 #define BITP_AFEWDT_WDTSTA_TLD 2 /* WDTVAL Write Status */ 00338 #define BITP_AFEWDT_WDTSTA_CLRI 1 /* WDTCLRI Write Status */ 00339 #define BITP_AFEWDT_WDTSTA_IRQ 0 /* WDT Interrupt */ 00340 #define BITM_AFEWDT_WDTSTA_RESERVED_15_7 (_ADI_MSK_3(0x0000FF80,0x0000FF80U, uint16_t )) /* RESERVED */ 00341 #define BITM_AFEWDT_WDTSTA_TMINLD (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* WDTMINLD Write Status */ 00342 #define BITM_AFEWDT_WDTSTA_OTPWRDONE (_ADI_MSK_3(0x00000020,0x00000020U, uint16_t )) /* Reset Type Status */ 00343 #define BITM_AFEWDT_WDTSTA_LOCK (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Lock Status */ 00344 #define BITM_AFEWDT_WDTSTA_CON (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* WDTCON Write Status */ 00345 #define BITM_AFEWDT_WDTSTA_TLD (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* WDTVAL Write Status */ 00346 #define BITM_AFEWDT_WDTSTA_CLRI (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* WDTCLRI Write Status */ 00347 #define BITM_AFEWDT_WDTSTA_IRQ (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* WDT Interrupt */ 00348 #define ENUM_AFEWDT_WDTSTA_OPEN (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* LOCK: Timer Operation Not Locked */ 00349 #define ENUM_AFEWDT_WDTSTA_LOCKED (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* LOCK: Timer Enabled and Locked */ 00350 #define ENUM_AFEWDT_WDTSTA_SYNC_COMPLETE (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* TLD: Arm and AFE Watchdog Clock Domains WDTLD values match */ 00351 #define ENUM_AFEWDT_WDTSTA_SYNC_IN_PROGRESS (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* TLD: Synchronize In Progress */ 00352 #define ENUM_AFEWDT_WDTSTA_CLEARED (_ADI_MSK_3(0x00000000,0x00000000U, uint16_t )) /* IRQ: Watchdog Timer Interrupt Not Pending */ 00353 #define ENUM_AFEWDT_WDTSTA_PENDING (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* IRQ: Watchdog Timer Interrupt Pending */ 00354 00355 /* ------------------------------------------------------------------------------------------------------------------------- 00356 AFEWDT_WDTMINLD Pos/Masks Description 00357 ------------------------------------------------------------------------------------------------------------------------- */ 00358 #define BITP_AFEWDT_WDTMINLD_MIN_LOAD 0 /* WDT Min Load Value */ 00359 #define BITM_AFEWDT_WDTMINLD_MIN_LOAD (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* WDT Min Load Value */ 00360 00361 /* ============================================================================================================================ 00362 Wakeup Timer 00363 ============================================================================================================================ */ 00364 00365 /* ============================================================================================================================ 00366 WUPTMR 00367 ============================================================================================================================ */ 00368 #define REG_WUPTMR_CON_RESET 0x00000000 /* Reset Value for CON */ 00369 #define REG_WUPTMR_CON 0x00000800 /* WUPTMR Timer Control */ 00370 #define REG_WUPTMR_SEQORDER_RESET 0x00000000 /* Reset Value for SEQORDER */ 00371 #define REG_WUPTMR_SEQORDER 0x00000804 /* WUPTMR Order Control */ 00372 #define REG_WUPTMR_SEQ0WUPL_RESET 0x0000FFFF /* Reset Value for SEQ0WUPL */ 00373 #define REG_WUPTMR_SEQ0WUPL 0x00000808 /* WUPTMR SEQ0 WTimeL (LSB) */ 00374 #define REG_WUPTMR_SEQ0WUPH_RESET 0x0000000F /* Reset Value for SEQ0WUPH */ 00375 #define REG_WUPTMR_SEQ0WUPH 0x0000080C /* WUPTMR SEQ0 WTimeH (MSB) */ 00376 #define REG_WUPTMR_SEQ0SLEEPL_RESET 0x0000FFFF /* Reset Value for SEQ0SLEEPL */ 00377 #define REG_WUPTMR_SEQ0SLEEPL 0x00000810 /* WUPTMR SEQ0 STimeL (LSB) */ 00378 #define REG_WUPTMR_SEQ0SLEEPH_RESET 0x0000000F /* Reset Value for SEQ0SLEEPH */ 00379 #define REG_WUPTMR_SEQ0SLEEPH 0x00000814 /* WUPTMR SEQ0 STimeH (MSB) */ 00380 #define REG_WUPTMR_SEQ1WUPL_RESET 0x0000FFFF /* Reset Value for SEQ1WUPL */ 00381 #define REG_WUPTMR_SEQ1WUPL 0x00000818 /* WUPTMR SEQ1 WTimeL (LSB) */ 00382 #define REG_WUPTMR_SEQ1WUPH_RESET 0x0000000F /* Reset Value for SEQ1WUPH */ 00383 #define REG_WUPTMR_SEQ1WUPH 0x0000081C /* WUPTMR SEQ1 WTimeH (MSB) */ 00384 #define REG_WUPTMR_SEQ1SLEEPL_RESET 0x0000FFFF /* Reset Value for SEQ1SLEEPL */ 00385 #define REG_WUPTMR_SEQ1SLEEPL 0x00000820 /* WUPTMR SEQ1 STimeL (LSB) */ 00386 #define REG_WUPTMR_SEQ1SLEEPH_RESET 0x0000000F /* Reset Value for SEQ1SLEEPH */ 00387 #define REG_WUPTMR_SEQ1SLEEPH 0x00000824 /* WUPTMR SEQ1 STimeH (MSB) */ 00388 #define REG_WUPTMR_SEQ2WUPL_RESET 0x0000FFFF /* Reset Value for SEQ2WUPL */ 00389 #define REG_WUPTMR_SEQ2WUPL 0x00000828 /* WUPTMR SEQ2 WTimeL (LSB) */ 00390 #define REG_WUPTMR_SEQ2WUPH_RESET 0x0000000F /* Reset Value for SEQ2WUPH */ 00391 #define REG_WUPTMR_SEQ2WUPH 0x0000082C /* WUPTMR SEQ2 WTimeH (MSB) */ 00392 #define REG_WUPTMR_SEQ2SLEEPL_RESET 0x0000FFFF /* Reset Value for SEQ2SLEEPL */ 00393 #define REG_WUPTMR_SEQ2SLEEPL 0x00000830 /* WUPTMR SEQ2 STimeL (LSB) */ 00394 #define REG_WUPTMR_SEQ2SLEEPH_RESET 0x0000000F /* Reset Value for SEQ2SLEEPH */ 00395 #define REG_WUPTMR_SEQ2SLEEPH 0x00000834 /* WUPTMR SEQ2 STimeH (MSB) */ 00396 #define REG_WUPTMR_SEQ3WUPL_RESET 0x0000FFFF /* Reset Value for SEQ3WUPL */ 00397 #define REG_WUPTMR_SEQ3WUPL 0x00000838 /* WUPTMR SEQ3 WTimeL (LSB) */ 00398 #define REG_WUPTMR_SEQ3WUPH_RESET 0x0000000F /* Reset Value for SEQ3WUPH */ 00399 #define REG_WUPTMR_SEQ3WUPH 0x0000083C /* WUPTMR SEQ3 WTimeH (MSB) */ 00400 #define REG_WUPTMR_SEQ3SLEEPL_RESET 0x0000FFFF /* Reset Value for SEQ3SLEEPL */ 00401 #define REG_WUPTMR_SEQ3SLEEPL 0x00000840 /* WUPTMR SEQ3 STimeL (LSB) */ 00402 #define REG_WUPTMR_SEQ3SLEEPH_RESET 0x0000000F /* Reset Value for SEQ3SLEEPH */ 00403 #define REG_WUPTMR_SEQ3SLEEPH 0x00000844 /* WUPTMR SEQ3 STimeH (MSB) */ 00404 00405 /* ============================================================================================================================ 00406 WUPTMR Register BitMasks, Positions & Enumerations 00407 ============================================================================================================================ */ 00408 /* ------------------------------------------------------------------------------------------------------------------------- 00409 WUPTMR_CON Pos/Masks Description 00410 ------------------------------------------------------------------------------------------------------------------------- */ 00411 #define BITP_WUPTMR_CON_MSKTRG 6 /* Mark Sequence Trigger from Sleep Wakeup Timer */ 00412 #define BITP_WUPTMR_CON_CLKSEL 4 /* Clock Selection */ 00413 #define BITP_WUPTMR_CON_ENDSEQ 1 /* End Sequence */ 00414 #define BITP_WUPTMR_CON_EN 0 /* Sleep Wake Timer Enable Bit */ 00415 #define BITM_WUPTMR_CON_MSKTRG 0x00000040 /* Mark Sequence Trigger from Sleep Wakeup Timer */ 00416 #define BITM_WUPTMR_CON_CLKSEL 0x00000030 /* Clock Selection */ 00417 #define BITM_WUPTMR_CON_ENDSEQ 0x0000000E /* End Sequence */ 00418 #define BITM_WUPTMR_CON_EN 0x00000001 /* Sleep Wake Timer Enable Bit */ 00419 #define ENUM_WUPTMR_CON_SWT32K0 0x00000000 /* CLKSEL: Internal 32kHz OSC */ 00420 #define ENUM_WUPTMR_CON_SWTEXT0 0x00000010 /* CLKSEL: External Clock */ 00421 #define ENUM_WUPTMR_CON_SWT32K 0x00000020 /* CLKSEL: Internal 32kHz OSC */ 00422 #define ENUM_WUPTMR_CON_SWTEXT 0x00000030 /* CLKSEL: External Clock */ 00423 #define ENUM_WUPTMR_CON_ENDSEQA 0x00000000 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqA And Then Go Back To SeqA */ 00424 #define ENUM_WUPTMR_CON_ENDSEQB 0x00000002 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqB And Then Go Back To SeqA */ 00425 #define ENUM_WUPTMR_CON_ENDSEQC 0x00000004 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqC And Then Go Back To SeqA */ 00426 #define ENUM_WUPTMR_CON_ENDSEQD 0x00000006 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqD And Then Go Back To SeqA */ 00427 #define ENUM_WUPTMR_CON_ENDSEQE 0x00000008 /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqE And Then Go Back To SeqA */ 00428 #define ENUM_WUPTMR_CON_ENDSEQF 0x0000000A /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqF And Then Go Back To SeqA */ 00429 #define ENUM_WUPTMR_CON_ENDSEQG 0x0000000C /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqG And Then Go Back To SeqA */ 00430 #define ENUM_WUPTMR_CON_ENDSEQH 0x0000000E /* ENDSEQ: The Sleep Wakeup Timer Will Stop At SeqH And Then Go Back To SeqA */ 00431 #define ENUM_WUPTMR_CON_SWTEN 0x00000000 /* EN: Enable Sleep Wakeup Timer */ 00432 #define ENUM_WUPTMR_CON_SWTDIS 0x00000001 /* EN: Disable Sleep Wakeup Timer */ 00433 00434 /* ------------------------------------------------------------------------------------------------------------------------- 00435 WUPTMR_SEQORDER Pos/Masks Description 00436 ------------------------------------------------------------------------------------------------------------------------- */ 00437 #define BITP_WUPTMR_SEQORDER_SEQH 14 /* SEQH Config */ 00438 #define BITP_WUPTMR_SEQORDER_SEQG 12 /* SEQG Config */ 00439 #define BITP_WUPTMR_SEQORDER_SEQF 10 /* SEQF Config */ 00440 #define BITP_WUPTMR_SEQORDER_SEQE 8 /* SEQE Config */ 00441 #define BITP_WUPTMR_SEQORDER_SEQD 6 /* SEQD Config */ 00442 #define BITP_WUPTMR_SEQORDER_SEQC 4 /* SEQC Config */ 00443 #define BITP_WUPTMR_SEQORDER_SEQB 2 /* SEQB Config */ 00444 #define BITP_WUPTMR_SEQORDER_SEQA 0 /* SEQA Config */ 00445 #define BITM_WUPTMR_SEQORDER_SEQH 0x0000C000 /* SEQH Config */ 00446 #define BITM_WUPTMR_SEQORDER_SEQG 0x00003000 /* SEQG Config */ 00447 #define BITM_WUPTMR_SEQORDER_SEQF 0x00000C00 /* SEQF Config */ 00448 #define BITM_WUPTMR_SEQORDER_SEQE 0x00000300 /* SEQE Config */ 00449 #define BITM_WUPTMR_SEQORDER_SEQD 0x000000C0 /* SEQD Config */ 00450 #define BITM_WUPTMR_SEQORDER_SEQC 0x00000030 /* SEQC Config */ 00451 #define BITM_WUPTMR_SEQORDER_SEQB 0x0000000C /* SEQB Config */ 00452 #define BITM_WUPTMR_SEQORDER_SEQA 0x00000003 /* SEQA Config */ 00453 #define ENUM_WUPTMR_SEQORDER_SEQH0 0x00000000 /* SEQH: Fill SEQ0 In */ 00454 #define ENUM_WUPTMR_SEQORDER_SEQH1 0x00004000 /* SEQH: Fill SEQ1 In */ 00455 #define ENUM_WUPTMR_SEQORDER_SEQH2 0x00008000 /* SEQH: Fill SEQ2 In */ 00456 #define ENUM_WUPTMR_SEQORDER_SEQH3 0x0000C000 /* SEQH: Fill SEQ3 In */ 00457 #define ENUM_WUPTMR_SEQORDER_SEQG0 0x00000000 /* SEQG: Fill SEQ0 In */ 00458 #define ENUM_WUPTMR_SEQORDER_SEQG1 0x00001000 /* SEQG: Fill SEQ1 In */ 00459 #define ENUM_WUPTMR_SEQORDER_SEQG2 0x00002000 /* SEQG: Fill SEQ2 In */ 00460 #define ENUM_WUPTMR_SEQORDER_SEQG3 0x00003000 /* SEQG: Fill SEQ3 In */ 00461 #define ENUM_WUPTMR_SEQORDER_SEQF0 0x00000000 /* SEQF: Fill SEQ0 In */ 00462 #define ENUM_WUPTMR_SEQORDER_SEQF1 0x00000400 /* SEQF: Fill SEQ1 In */ 00463 #define ENUM_WUPTMR_SEQORDER_SEQF2 0x00000800 /* SEQF: Fill SEQ2 In */ 00464 #define ENUM_WUPTMR_SEQORDER_SEQF3 0x00000C00 /* SEQF: Fill SEQ3 In */ 00465 #define ENUM_WUPTMR_SEQORDER_SEQE0 0x00000000 /* SEQE: Fill SEQ0 In */ 00466 #define ENUM_WUPTMR_SEQORDER_SEQE1 0x00000100 /* SEQE: Fill SEQ1 In */ 00467 #define ENUM_WUPTMR_SEQORDER_SEQE2 0x00000200 /* SEQE: Fill SEQ2 In */ 00468 #define ENUM_WUPTMR_SEQORDER_SEQE3 0x00000300 /* SEQE: Fill SEQ3 In */ 00469 #define ENUM_WUPTMR_SEQORDER_SEQD0 0x00000000 /* SEQD: Fill SEQ0 In */ 00470 #define ENUM_WUPTMR_SEQORDER_SEQD1 0x00000040 /* SEQD: Fill SEQ1 In */ 00471 #define ENUM_WUPTMR_SEQORDER_SEQD2 0x00000080 /* SEQD: Fill SEQ2 In */ 00472 #define ENUM_WUPTMR_SEQORDER_SEQD3 0x000000C0 /* SEQD: Fill SEQ3 In */ 00473 #define ENUM_WUPTMR_SEQORDER_SEQC0 0x00000000 /* SEQC: Fill SEQ0 In */ 00474 #define ENUM_WUPTMR_SEQORDER_SEQC1 0x00000010 /* SEQC: Fill SEQ1 In */ 00475 #define ENUM_WUPTMR_SEQORDER_SEQC2 0x00000020 /* SEQC: Fill SEQ2 In */ 00476 #define ENUM_WUPTMR_SEQORDER_SEQC3 0x00000030 /* SEQC: Fill SEQ3 In */ 00477 #define ENUM_WUPTMR_SEQORDER_SEQB0 0x00000000 /* SEQB: Fill SEQ0 In */ 00478 #define ENUM_WUPTMR_SEQORDER_SEQB1 0x00000004 /* SEQB: Fill SEQ1 In */ 00479 #define ENUM_WUPTMR_SEQORDER_SEQB2 0x00000008 /* SEQB: Fill SEQ2 In */ 00480 #define ENUM_WUPTMR_SEQORDER_SEQB3 0x0000000C /* SEQB: Fill SEQ3 In */ 00481 #define ENUM_WUPTMR_SEQORDER_SEQA0 0x00000000 /* SEQA: Fill SEQ0 In */ 00482 #define ENUM_WUPTMR_SEQORDER_SEQA1 0x00000001 /* SEQA: Fill SEQ1 In */ 00483 #define ENUM_WUPTMR_SEQORDER_SEQA2 0x00000002 /* SEQA: Fill SEQ2 In */ 00484 #define ENUM_WUPTMR_SEQORDER_SEQA3 0x00000003 /* SEQA: Fill SEQ3 In */ 00485 00486 /* ------------------------------------------------------------------------------------------------------------------------- 00487 WUPTMR_SEQ0WUPL Pos/Masks Description 00488 ------------------------------------------------------------------------------------------------------------------------- */ 00489 #define BITP_WUPTMR_SEQ0WUPL_WAKEUPTIME0 0 /* Sequence 0 Sleep Period */ 00490 #define BITM_WUPTMR_SEQ0WUPL_WAKEUPTIME0 0x0000FFFF /* Sequence 0 Sleep Period */ 00491 00492 /* ------------------------------------------------------------------------------------------------------------------------- 00493 WUPTMR_SEQ0WUPH Pos/Masks Description 00494 ------------------------------------------------------------------------------------------------------------------------- */ 00495 #define BITP_WUPTMR_SEQ0WUPH_WAKEUPTIME0 0 /* Sequence 0 Sleep Period */ 00496 #define BITM_WUPTMR_SEQ0WUPH_WAKEUPTIME0 0x0000000F /* Sequence 0 Sleep Period */ 00497 00498 /* ------------------------------------------------------------------------------------------------------------------------- 00499 WUPTMR_SEQ0SLEEPL Pos/Masks Description 00500 ------------------------------------------------------------------------------------------------------------------------- */ 00501 #define BITP_WUPTMR_SEQ0SLEEPL_SLEEPTIME0 0 /* Sequence 0 Active Period */ 00502 #define BITM_WUPTMR_SEQ0SLEEPL_SLEEPTIME0 0x0000FFFF /* Sequence 0 Active Period */ 00503 00504 /* ------------------------------------------------------------------------------------------------------------------------- 00505 WUPTMR_SEQ0SLEEPH Pos/Masks Description 00506 ------------------------------------------------------------------------------------------------------------------------- */ 00507 #define BITP_WUPTMR_SEQ0SLEEPH_SLEEPTIME0 0 /* Sequence 0 Active Period */ 00508 #define BITM_WUPTMR_SEQ0SLEEPH_SLEEPTIME0 0x0000000F /* Sequence 0 Active Period */ 00509 00510 /* ------------------------------------------------------------------------------------------------------------------------- 00511 WUPTMR_SEQ1WUPL Pos/Masks Description 00512 ------------------------------------------------------------------------------------------------------------------------- */ 00513 #define BITP_WUPTMR_SEQ1WUPL_WAKEUPTIME 0 /* Sequence 1 Sleep Period */ 00514 #define BITM_WUPTMR_SEQ1WUPL_WAKEUPTIME 0x0000FFFF /* Sequence 1 Sleep Period */ 00515 00516 /* ------------------------------------------------------------------------------------------------------------------------- 00517 WUPTMR_SEQ1WUPH Pos/Masks Description 00518 ------------------------------------------------------------------------------------------------------------------------- */ 00519 #define BITP_WUPTMR_SEQ1WUPH_WAKEUPTIME 0 /* Sequence 1 Sleep Period */ 00520 #define BITM_WUPTMR_SEQ1WUPH_WAKEUPTIME 0x0000000F /* Sequence 1 Sleep Period */ 00521 00522 /* ------------------------------------------------------------------------------------------------------------------------- 00523 WUPTMR_SEQ1SLEEPL Pos/Masks Description 00524 ------------------------------------------------------------------------------------------------------------------------- */ 00525 #define BITP_WUPTMR_SEQ1SLEEPL_SLEEPTIME1 0 /* Sequence 1 Active Period */ 00526 #define BITM_WUPTMR_SEQ1SLEEPL_SLEEPTIME1 0x0000FFFF /* Sequence 1 Active Period */ 00527 00528 /* ------------------------------------------------------------------------------------------------------------------------- 00529 WUPTMR_SEQ1SLEEPH Pos/Masks Description 00530 ------------------------------------------------------------------------------------------------------------------------- */ 00531 #define BITP_WUPTMR_SEQ1SLEEPH_SLEEPTIME1 0 /* Sequence 1 Active Period */ 00532 #define BITM_WUPTMR_SEQ1SLEEPH_SLEEPTIME1 0x0000000F /* Sequence 1 Active Period */ 00533 00534 /* ------------------------------------------------------------------------------------------------------------------------- 00535 WUPTMR_SEQ2WUPL Pos/Masks Description 00536 ------------------------------------------------------------------------------------------------------------------------- */ 00537 #define BITP_WUPTMR_SEQ2WUPL_WAKEUPTIME2 0 /* Sequence 2 Sleep Period */ 00538 #define BITM_WUPTMR_SEQ2WUPL_WAKEUPTIME2 0x0000FFFF /* Sequence 2 Sleep Period */ 00539 00540 /* ------------------------------------------------------------------------------------------------------------------------- 00541 WUPTMR_SEQ2WUPH Pos/Masks Description 00542 ------------------------------------------------------------------------------------------------------------------------- */ 00543 #define BITP_WUPTMR_SEQ2WUPH_WAKEUPTIME2 0 /* Sequence 2 Sleep Period */ 00544 #define BITM_WUPTMR_SEQ2WUPH_WAKEUPTIME2 0x0000000F /* Sequence 2 Sleep Period */ 00545 00546 /* ------------------------------------------------------------------------------------------------------------------------- 00547 WUPTMR_SEQ2SLEEPL Pos/Masks Description 00548 ------------------------------------------------------------------------------------------------------------------------- */ 00549 #define BITP_WUPTMR_SEQ2SLEEPL_SLEEPTIME2 0 /* Sequence 2 Active Period */ 00550 #define BITM_WUPTMR_SEQ2SLEEPL_SLEEPTIME2 0x0000FFFF /* Sequence 2 Active Period */ 00551 00552 /* ------------------------------------------------------------------------------------------------------------------------- 00553 WUPTMR_SEQ2SLEEPH Pos/Masks Description 00554 ------------------------------------------------------------------------------------------------------------------------- */ 00555 #define BITP_WUPTMR_SEQ2SLEEPH_SLEEPTIME2 0 /* Sequence 2 Active Period */ 00556 #define BITM_WUPTMR_SEQ2SLEEPH_SLEEPTIME2 0x0000000F /* Sequence 2 Active Period */ 00557 00558 /* ------------------------------------------------------------------------------------------------------------------------- 00559 WUPTMR_SEQ3WUPL Pos/Masks Description 00560 ------------------------------------------------------------------------------------------------------------------------- */ 00561 #define BITP_WUPTMR_SEQ3WUPL_WAKEUPTIME3 0 /* Sequence 3 Sleep Period */ 00562 #define BITM_WUPTMR_SEQ3WUPL_WAKEUPTIME3 0x0000FFFF /* Sequence 3 Sleep Period */ 00563 00564 /* ------------------------------------------------------------------------------------------------------------------------- 00565 WUPTMR_SEQ3WUPH Pos/Masks Description 00566 ------------------------------------------------------------------------------------------------------------------------- */ 00567 #define BITP_WUPTMR_SEQ3WUPH_WAKEUPTIME3 0 /* Sequence 3 Sleep Period */ 00568 #define BITM_WUPTMR_SEQ3WUPH_WAKEUPTIME3 0x0000000F /* Sequence 3 Sleep Period */ 00569 00570 /* ------------------------------------------------------------------------------------------------------------------------- 00571 WUPTMR_SEQ3SLEEPL Pos/Masks Description 00572 ------------------------------------------------------------------------------------------------------------------------- */ 00573 #define BITP_WUPTMR_SEQ3SLEEPL_SLEEPTIME3 0 /* Sequence 3 Active Period */ 00574 #define BITM_WUPTMR_SEQ3SLEEPL_SLEEPTIME3 0x0000FFFF /* Sequence 3 Active Period */ 00575 00576 /* ------------------------------------------------------------------------------------------------------------------------- 00577 WUPTMR_SEQ3SLEEPH Pos/Masks Description 00578 ------------------------------------------------------------------------------------------------------------------------- */ 00579 #define BITP_WUPTMR_SEQ3SLEEPH_SLEEPTIME3 0 /* Sequence 3 Active Period */ 00580 #define BITM_WUPTMR_SEQ3SLEEPH_SLEEPTIME3 0x0000000F /* Sequence 3 Active Period */ 00581 00582 00583 /* ============================================================================================================================ 00584 Always On Register 00585 ============================================================================================================================ */ 00586 00587 /* ============================================================================================================================ 00588 ALLON 00589 ============================================================================================================================ */ 00590 #define REG_ALLON_PWRMOD_RESET 0x00000001 /* Reset Value for PWRMOD */ 00591 #define REG_ALLON_PWRMOD 0x00000A00 /* ALLON Power Modes */ 00592 #define REG_ALLON_PWRKEY_RESET 0x00000000 /* Reset Value for PWRKEY */ 00593 #define REG_ALLON_PWRKEY 0x00000A04 /* ALLON Key Protection for PWRMOD */ 00594 #define REG_ALLON_OSCKEY_RESET 0x00000000 /* Reset Value for OSCKEY */ 00595 #define REG_ALLON_OSCKEY 0x00000A0C /* ALLON Key Protection for OSCCON */ 00596 #define REG_ALLON_OSCCON_RESET 0x00000003 /* Reset Value for OSCCON */ 00597 #define REG_ALLON_OSCCON 0x00000A10 /* ALLON Oscillator Control */ 00598 #define REG_ALLON_TMRCON_RESET 0x00000000 /* Reset Value for TMRCON */ 00599 #define REG_ALLON_TMRCON 0x00000A1C /* ALLON Timer Wakeup Configuration */ 00600 #define REG_ALLON_EI0CON_RESET 0x00000000 /* Reset Value for EI0CON */ 00601 #define REG_ALLON_EI0CON 0x00000A20 /* ALLON External Interrupt Configuration 0 */ 00602 #define REG_ALLON_EI1CON_RESET 0x00000000 /* Reset Value for EI1CON */ 00603 #define REG_ALLON_EI1CON 0x00000A24 /* ALLON External Interrupt Configuration 1 */ 00604 #define REG_ALLON_EI2CON_RESET 0x00000000 /* Reset Value for EI2CON */ 00605 #define REG_ALLON_EI2CON 0x00000A28 /* ALLON External Interrupt Configuration 2 */ 00606 #define REG_ALLON_EICLR_RESET 0x0000C000 /* Reset Value for EICLR */ 00607 #define REG_ALLON_EICLR 0x00000A30 /* ALLON External Interrupt Clear */ 00608 #define REG_ALLON_RSTSTA_RESET 0x00000000 /* Reset Value for RSTSTA */ 00609 #define REG_ALLON_RSTSTA 0x00000A40 /* ALLON Reset Status */ 00610 #define REG_ALLON_RSTCONKEY_RESET 0x00000000 /* Reset Value for RSTCONKEY */ 00611 #define REG_ALLON_RSTCONKEY 0x00000A5C /* ALLON Key Protection for RSTCON Register */ 00612 #define REG_ALLON_LOSCTST_RESET 0x0000008F /* Reset Value for LOSCTST */ 00613 #define REG_ALLON_LOSCTST 0x00000A6C /* ALLON Internal LF Oscillator Test */ 00614 #define REG_ALLON_CLKEN0_RESET 0x00000004 /* Reset Value for CLKEN0 */ 00615 #define REG_ALLON_CLKEN0 0x00000A70 /* ALLON 32KHz Peripheral Clock Enable */ 00616 00617 /* ============================================================================================================================ 00618 ALLON Register BitMasks, Positions & Enumerations 00619 ============================================================================================================================ */ 00620 /* ------------------------------------------------------------------------------------------------------------------------- 00621 ALLON_PWRMOD Pos/Masks Description 00622 ------------------------------------------------------------------------------------------------------------------------- */ 00623 #define BITP_ALLON_PWRMOD_RAMRETEN 15 /* Retention for RAM */ 00624 #define BITP_ALLON_PWRMOD_ADCRETEN 14 /* Keep ADC Power Switch on in Hibernate */ 00625 #define BITP_ALLON_PWRMOD_SEQSLPEN 3 /* Auto Sleep by Sequencer Command */ 00626 #define BITP_ALLON_PWRMOD_TMRSLPEN 2 /* Auto Sleep by Sleep Wakeup Timer */ 00627 #define BITP_ALLON_PWRMOD_PWRMOD 0 /* Power Mode Control Bits */ 00628 #define BITM_ALLON_PWRMOD_RAMRETEN 0x00008000 /* Retention for RAM */ 00629 #define BITM_ALLON_PWRMOD_ADCRETEN 0x00004000 /* Keep ADC Power Switch on in Hibernate */ 00630 #define BITM_ALLON_PWRMOD_SEQSLPEN 0x00000008 /* Auto Sleep by Sequencer Command */ 00631 #define BITM_ALLON_PWRMOD_TMRSLPEN 0x00000004 /* Auto Sleep by Sleep Wakeup Timer */ 00632 #define BITM_ALLON_PWRMOD_PWRMOD 0x00000003 /* Power Mode Control Bits */ 00633 00634 /* ------------------------------------------------------------------------------------------------------------------------- 00635 ALLON_PWRKEY Pos/Masks Description 00636 ------------------------------------------------------------------------------------------------------------------------- */ 00637 #define BITP_ALLON_PWRKEY_PWRKEY 0 /* PWRMOD Key Register */ 00638 #define BITM_ALLON_PWRKEY_PWRKEY 0x0000FFFF /* PWRMOD Key Register */ 00639 00640 /* ------------------------------------------------------------------------------------------------------------------------- 00641 ALLON_OSCKEY Pos/Masks Description 00642 ------------------------------------------------------------------------------------------------------------------------- */ 00643 #define BITP_ALLON_OSCKEY_OSCKEY 0 /* Oscillator Control Key Register. */ 00644 #define BITM_ALLON_OSCKEY_OSCKEY 0x0000FFFF /* Oscillator Control Key Register. */ 00645 00646 /* ------------------------------------------------------------------------------------------------------------------------- 00647 ALLON_OSCCON Pos/Masks Description 00648 ------------------------------------------------------------------------------------------------------------------------- */ 00649 #define BITP_ALLON_OSCCON_HFXTALOK 10 /* Status of HFXTAL Oscillator */ 00650 #define BITP_ALLON_OSCCON_HFOSCOK 9 /* Status of HFOSC Oscillator */ 00651 #define BITP_ALLON_OSCCON_LFOSCOK 8 /* Status of LFOSC Oscillator */ 00652 #define BITP_ALLON_OSCCON_HFXTALEN 2 /* High Frequency Crystal Oscillator Enable */ 00653 #define BITP_ALLON_OSCCON_HFOSCEN 1 /* High Frequency Internal Oscillator Enable */ 00654 #define BITP_ALLON_OSCCON_LFOSCEN 0 /* Low Frequency Internal Oscillator Enable */ 00655 #define BITM_ALLON_OSCCON_HFXTALOK 0x00000400 /* Status of HFXTAL Oscillator */ 00656 #define BITM_ALLON_OSCCON_HFOSCOK 0x00000200 /* Status of HFOSC Oscillator */ 00657 #define BITM_ALLON_OSCCON_LFOSCOK 0x00000100 /* Status of LFOSC Oscillator */ 00658 #define BITM_ALLON_OSCCON_HFXTALEN 0x00000004 /* High Frequency Crystal Oscillator Enable */ 00659 #define BITM_ALLON_OSCCON_HFOSCEN 0x00000002 /* High Frequency Internal Oscillator Enable */ 00660 #define BITM_ALLON_OSCCON_LFOSCEN 0x00000001 /* Low Frequency Internal Oscillator Enable */ 00661 00662 /* ------------------------------------------------------------------------------------------------------------------------- 00663 ALLON_TMRCON Pos/Masks Description 00664 ------------------------------------------------------------------------------------------------------------------------- */ 00665 #define BITP_ALLON_TMRCON_TMRINTEN 0 /* Enable Wakeup Timer */ 00666 #define BITM_ALLON_TMRCON_TMRINTEN 0x00000001 /* Enable Wakeup Timer */ 00667 00668 /* ------------------------------------------------------------------------------------------------------------------------- 00669 ALLON_EI0CON Pos/Masks Description 00670 ------------------------------------------------------------------------------------------------------------------------- */ 00671 #define BITP_ALLON_EI0CON_IRQ3EN 15 /* External Interrupt 3 Enable Bit */ 00672 #define BITP_ALLON_EI0CON_IRQ3MDE 12 /* External Interrupt 3 Mode Registers */ 00673 #define BITP_ALLON_EI0CON_IRQ2EN 11 /* External Interrupt 2 Enable Bit */ 00674 #define BITP_ALLON_EI0CON_IRQ2MDE 8 /* External Interrupt 2 Mode Registers */ 00675 #define BITP_ALLON_EI0CON_IRQ1EN 7 /* External Interrupt 1 Enable Bit */ 00676 #define BITP_ALLON_EI0CON_IRQ1MDE 4 /* External Interrupt 1 Mode Registers */ 00677 #define BITP_ALLON_EI0CON_IRQ0EN 3 /* External Interrupt 0 Enable Bit */ 00678 #define BITP_ALLON_EI0CON_IRQ0MDE 0 /* External Interrupt 0 Mode Registers */ 00679 #define BITM_ALLON_EI0CON_IRQ3EN 0x00008000 /* External Interrupt 3 Enable Bit */ 00680 #define BITM_ALLON_EI0CON_IRQ3MDE 0x00007000 /* External Interrupt 3 Mode Registers */ 00681 #define BITM_ALLON_EI0CON_IRQ2EN 0x00000800 /* External Interrupt 2 Enable Bit */ 00682 #define BITM_ALLON_EI0CON_IRQ2MDE 0x00000700 /* External Interrupt 2 Mode Registers */ 00683 #define BITM_ALLON_EI0CON_IRQ1EN 0x00000080 /* External Interrupt 1 Enable Bit */ 00684 #define BITM_ALLON_EI0CON_IRQ1MDE 0x00000070 /* External Interrupt 1 Mode Registers */ 00685 #define BITM_ALLON_EI0CON_IRQ0EN 0x00000008 /* External Interrupt 0 Enable Bit */ 00686 #define BITM_ALLON_EI0CON_IRQ0MDE 0x00000007 /* External Interrupt 0 Mode Registers */ 00687 00688 /* ------------------------------------------------------------------------------------------------------------------------- 00689 ALLON_EI1CON Pos/Masks Description 00690 ------------------------------------------------------------------------------------------------------------------------- */ 00691 #define BITP_ALLON_EI1CON_IRQ7EN 15 /* External Interrupt 7 Enable Bit */ 00692 #define BITP_ALLON_EI1CON_IRQ7MDE 12 /* External Interrupt 7 Mode Registers */ 00693 #define BITP_ALLON_EI1CON_IRQ6EN 11 /* External Interrupt 6 Enable Bit */ 00694 #define BITP_ALLON_EI1CON_IRQ6MDE 8 /* External Interrupt 6 Mode Registers */ 00695 #define BITP_ALLON_EI1CON_IRQ5EN 7 /* External Interrupt 5 Enable Bit */ 00696 #define BITP_ALLON_EI1CON_IRQ5MDE 4 /* External Interrupt 5 Mode Registers */ 00697 #define BITP_ALLON_EI1CON_IRQ4EN 3 /* External Interrupt 4 Enable Bit */ 00698 #define BITP_ALLON_EI1CON_IRQ4MDE 0 /* External Interrupt 4 Mode Registers */ 00699 #define BITM_ALLON_EI1CON_IRQ7EN 0x00008000 /* External Interrupt 7 Enable Bit */ 00700 #define BITM_ALLON_EI1CON_IRQ7MDE 0x00007000 /* External Interrupt 7 Mode Registers */ 00701 #define BITM_ALLON_EI1CON_IRQ6EN 0x00000800 /* External Interrupt 6 Enable Bit */ 00702 #define BITM_ALLON_EI1CON_IRQ6MDE 0x00000700 /* External Interrupt 6 Mode Registers */ 00703 #define BITM_ALLON_EI1CON_IRQ5EN 0x00000080 /* External Interrupt 5 Enable Bit */ 00704 #define BITM_ALLON_EI1CON_IRQ5MDE 0x00000070 /* External Interrupt 5 Mode Registers */ 00705 #define BITM_ALLON_EI1CON_IRQ4EN 0x00000008 /* External Interrupt 4 Enable Bit */ 00706 #define BITM_ALLON_EI1CON_IRQ4MDE 0x00000007 /* External Interrupt 4 Mode Registers */ 00707 00708 /* ------------------------------------------------------------------------------------------------------------------------- 00709 ALLON_EI2CON Pos/Masks Description 00710 ------------------------------------------------------------------------------------------------------------------------- */ 00711 #define BITP_ALLON_EI2CON_BUSINTEN 3 /* BUS Interrupt Detection Enable Bit */ 00712 #define BITP_ALLON_EI2CON_BUSINTMDE 0 /* BUS Interrupt Detection Mode Registers */ 00713 #define BITM_ALLON_EI2CON_BUSINTEN 0x00000008 /* BUS Interrupt Detection Enable Bit */ 00714 #define BITM_ALLON_EI2CON_BUSINTMDE 0x00000007 /* BUS Interrupt Detection Mode Registers */ 00715 00716 /* ------------------------------------------------------------------------------------------------------------------------- 00717 ALLON_EICLR Pos/Masks Description 00718 ------------------------------------------------------------------------------------------------------------------------- */ 00719 #define BITP_ALLON_EICLR_AUTCLRBUSEN 15 /* Enable Auto Clear of Bus Interrupt */ 00720 #define BITP_ALLON_EICLR_BUSINT 8 /* BUS Interrupt */ 00721 #define BITM_ALLON_EICLR_AUTCLRBUSEN 0x00008000 /* Enable Auto Clear of Bus Interrupt */ 00722 #define BITM_ALLON_EICLR_BUSINT 0x00000100 /* BUS Interrupt */ 00723 00724 /* ------------------------------------------------------------------------------------------------------------------------- 00725 ALLON_RSTSTA Pos/Masks Description 00726 ------------------------------------------------------------------------------------------------------------------------- */ 00727 #define BITP_ALLON_RSTSTA_PINSWRST 4 /* Software Reset Pin */ 00728 #define BITP_ALLON_RSTSTA_MMRSWRST 3 /* MMR Software Reset */ 00729 #define BITP_ALLON_RSTSTA_WDRST 2 /* Watchdog Timeout */ 00730 #define BITP_ALLON_RSTSTA_EXTRST 1 /* External Reset */ 00731 #define BITP_ALLON_RSTSTA_POR 0 /* Power-on Reset */ 00732 #define BITM_ALLON_RSTSTA_PINSWRST 0x00000010 /* Software Reset Pin */ 00733 #define BITM_ALLON_RSTSTA_MMRSWRST 0x00000008 /* MMR Software Reset */ 00734 #define BITM_ALLON_RSTSTA_WDRST 0x00000004 /* Watchdog Timeout */ 00735 #define BITM_ALLON_RSTSTA_EXTRST 0x00000002 /* External Reset */ 00736 #define BITM_ALLON_RSTSTA_POR 0x00000001 /* Power-on Reset */ 00737 00738 /* ------------------------------------------------------------------------------------------------------------------------- 00739 ALLON_RSTCONKEY Pos/Masks Description 00740 ------------------------------------------------------------------------------------------------------------------------- */ 00741 #define BITP_ALLON_RSTCONKEY_KEY 0 /* Reset Control Key Register */ 00742 #define BITM_ALLON_RSTCONKEY_KEY 0x0000FFFF /* Reset Control Key Register */ 00743 00744 /* ------------------------------------------------------------------------------------------------------------------------- 00745 ALLON_LOSCTST Pos/Masks Description 00746 ------------------------------------------------------------------------------------------------------------------------- */ 00747 #define BITP_ALLON_LOSCTST_TRIM 0 /* Trim Caps to Adjust Frequency. */ 00748 #define BITM_ALLON_LOSCTST_TRIM 0x0000000F /* Trim Caps to Adjust Frequency. */ 00749 00750 /* ------------------------------------------------------------------------------------------------------------------------- 00751 ALLON_CLKEN0 Pos/Masks Description 00752 ------------------------------------------------------------------------------------------------------------------------- */ 00753 #define BITP_ALLON_CLKEN0_TIACHPDIS 2 /* TIA Chop Clock Disable */ 00754 #define BITP_ALLON_CLKEN0_SLPWUTDIS 1 /* Sleep/Wakeup Timer Clock Disable */ 00755 #define BITP_ALLON_CLKEN0_WDTDIS 0 /* Watch Dog Timer Clock Disable */ 00756 #define BITM_ALLON_CLKEN0_TIACHPDIS 0x00000004 /* TIA Chop Clock Disable */ 00757 #define BITM_ALLON_CLKEN0_SLPWUTDIS 0x00000002 /* Sleep/Wakeup Timer Clock Disable */ 00758 #define BITM_ALLON_CLKEN0_WDTDIS 0x00000001 /* Watch Dog Timer Clock Disable */ 00759 00760 /* ============================================================================================================================ 00761 General Purpose Timer 00762 ============================================================================================================================ */ 00763 00764 /* ============================================================================================================================ 00765 AGPT0 00766 ============================================================================================================================ */ 00767 #define REG_AGPT0_LD0 0x00000D00 /* AGPT0 16-bit Load Value Register. */ 00768 #define REG_AGPT0_VAL0 0x00000D04 /* AGPT0 16-Bit Timer Value Register. */ 00769 #define REG_AGPT0_CON0 0x00000D08 /* AGPT0 Control Register. */ 00770 #define REG_AGPT0_CLRI0 0x00000D0C /* AGPT0 Clear Interrupt Register. */ 00771 #define REG_AGPT0_CAP0 0x00000D10 /* AGPT0 Capture Register. */ 00772 #define REG_AGPT0_ALD0 0x00000D14 /* AGPT0 16-Bit Load Value, Asynchronous. */ 00773 #define REG_AGPT0_AVAL0 0x00000D18 /* AGPT0 16-Bit Timer Value, Asynchronous Register. */ 00774 #define REG_AGPT0_STA0 0x00000D1C /* AGPT0 Status Register. */ 00775 #define REG_AGPT0_PWMCON0 0x00000D20 /* AGPT0 PWM Control Register. */ 00776 #define REG_AGPT0_PWMMAT0 0x00000D24 /* AGPT0 PWM Match Value Register. */ 00777 #define REG_AGPT0_INTEN 0x00000D28 /* AGPT0 Interrupt Enable */ 00778 00779 /* ============================================================================================================================ 00780 AGPT0 Register BitMasks, Positions & Enumerations 00781 ============================================================================================================================ */ 00782 /* ------------------------------------------------------------------------------------------------------------------------- 00783 AGPT0_LD0 Pos/Masks Description 00784 ------------------------------------------------------------------------------------------------------------------------- */ 00785 #define BITP_AGPT0_LD0_LOAD 0 /* Load Value */ 00786 #define BITM_AGPT0_LD0_LOAD (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Load Value */ 00787 00788 /* ------------------------------------------------------------------------------------------------------------------------- 00789 AGPT0_VAL0 Pos/Masks Description 00790 ------------------------------------------------------------------------------------------------------------------------- */ 00791 #define BITP_AGPT0_VAL0_VAL 0 /* Current Count */ 00792 #define BITM_AGPT0_VAL0_VAL (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Current Count */ 00793 00794 /* ------------------------------------------------------------------------------------------------------------------------- 00795 AGPT0_CON0 Pos/Masks Description 00796 ------------------------------------------------------------------------------------------------------------------------- */ 00797 #define BITP_AGPT0_CON0_SYNCBYP 15 /* Synchronization Bypass */ 00798 #define BITP_AGPT0_CON0_RSTEN 14 /* Counter and Prescale Reset Enable */ 00799 #define BITP_AGPT0_CON0_EVTEN 13 /* Event Select */ 00800 #define BITP_AGPT0_CON0_EVENT 8 /* Event Select Range */ 00801 #define BITP_AGPT0_CON0_RLD 7 /* Reload Control */ 00802 #define BITP_AGPT0_CON0_CLK 5 /* Clock Select */ 00803 #define BITP_AGPT0_CON0_ENABLE 4 /* Timer Enable */ 00804 #define BITP_AGPT0_CON0_MOD 3 /* Timer Mode */ 00805 #define BITP_AGPT0_CON0_UP 2 /* Count up */ 00806 #define BITP_AGPT0_CON0_PRE 0 /* Prescaler */ 00807 #define BITM_AGPT0_CON0_SYNCBYP (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Synchronization Bypass */ 00808 #define BITM_AGPT0_CON0_RSTEN (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Counter and Prescale Reset Enable */ 00809 #define BITM_AGPT0_CON0_EVTEN (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Event Select */ 00810 #define BITM_AGPT0_CON0_EVENT (_ADI_MSK_3(0x00001F00,0x00001F00U, uint16_t )) /* Event Select Range */ 00811 #define BITM_AGPT0_CON0_RLD (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Reload Control */ 00812 #define BITM_AGPT0_CON0_CLK (_ADI_MSK_3(0x00000060,0x00000060U, uint16_t )) /* Clock Select */ 00813 #define BITM_AGPT0_CON0_ENABLE (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Timer Enable */ 00814 #define BITM_AGPT0_CON0_MOD (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Timer Mode */ 00815 #define BITM_AGPT0_CON0_UP (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Count up */ 00816 #define BITM_AGPT0_CON0_PRE (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Prescaler */ 00817 00818 /* ------------------------------------------------------------------------------------------------------------------------- 00819 AGPT0_CLRI0 Pos/Masks Description 00820 ------------------------------------------------------------------------------------------------------------------------- */ 00821 #define BITP_AGPT0_CLRI0_CAP 1 /* Clear Captured Event Interrupt */ 00822 #define BITP_AGPT0_CLRI0_TMOUT 0 /* Clear Timeout Interrupt */ 00823 #define BITM_AGPT0_CLRI0_CAP (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Clear Captured Event Interrupt */ 00824 #define BITM_AGPT0_CLRI0_TMOUT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Clear Timeout Interrupt */ 00825 00826 /* ------------------------------------------------------------------------------------------------------------------------- 00827 AGPT0_CAP0 Pos/Masks Description 00828 ------------------------------------------------------------------------------------------------------------------------- */ 00829 #define BITP_AGPT0_CAP0_CAP 0 /* 16-bit Captured Value */ 00830 #define BITM_AGPT0_CAP0_CAP (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* 16-bit Captured Value */ 00831 00832 /* ------------------------------------------------------------------------------------------------------------------------- 00833 AGPT0_ALD0 Pos/Masks Description 00834 ------------------------------------------------------------------------------------------------------------------------- */ 00835 #define BITP_AGPT0_ALD0_ALOAD 0 /* Load Value, Asynchronous */ 00836 #define BITM_AGPT0_ALD0_ALOAD (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Load Value, Asynchronous */ 00837 00838 /* ------------------------------------------------------------------------------------------------------------------------- 00839 AGPT0_AVAL0 Pos/Masks Description 00840 ------------------------------------------------------------------------------------------------------------------------- */ 00841 #define BITP_AGPT0_AVAL0_AVAL 0 /* Counter Value */ 00842 #define BITM_AGPT0_AVAL0_AVAL (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Counter Value */ 00843 00844 /* ------------------------------------------------------------------------------------------------------------------------- 00845 AGPT0_STA0 Pos/Masks Description 00846 ------------------------------------------------------------------------------------------------------------------------- */ 00847 #define BITP_AGPT0_STA0_RSTCNT 8 /* Counter Reset Occurring */ 00848 #define BITP_AGPT0_STA0_PDOK 7 /* Clear Interrupt Register Synchronization */ 00849 #define BITP_AGPT0_STA0_BUSY 6 /* Timer Busy */ 00850 #define BITP_AGPT0_STA0_CAP 1 /* Capture Event Pending */ 00851 #define BITP_AGPT0_STA0_TMOUT 0 /* Timeout Event Occurred */ 00852 #define BITM_AGPT0_STA0_RSTCNT (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Counter Reset Occurring */ 00853 #define BITM_AGPT0_STA0_PDOK (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Clear Interrupt Register Synchronization */ 00854 #define BITM_AGPT0_STA0_BUSY (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Timer Busy */ 00855 #define BITM_AGPT0_STA0_CAP (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Capture Event Pending */ 00856 #define BITM_AGPT0_STA0_TMOUT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Timeout Event Occurred */ 00857 00858 /* ------------------------------------------------------------------------------------------------------------------------- 00859 AGPT0_PWMCON0 Pos/Masks Description 00860 ------------------------------------------------------------------------------------------------------------------------- */ 00861 #define BITP_AGPT0_PWMCON0_IDLE 1 /* PWM Idle State */ 00862 #define BITP_AGPT0_PWMCON0_MATCHEN 0 /* PWM Match Enabled */ 00863 #define BITM_AGPT0_PWMCON0_IDLE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* PWM Idle State */ 00864 #define BITM_AGPT0_PWMCON0_MATCHEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* PWM Match Enabled */ 00865 00866 /* ------------------------------------------------------------------------------------------------------------------------- 00867 AGPT0_PWMMAT0 Pos/Masks Description 00868 ------------------------------------------------------------------------------------------------------------------------- */ 00869 #define BITP_AGPT0_PWMMAT0_MATCHVAL 0 /* PWM Match Value */ 00870 #define BITM_AGPT0_PWMMAT0_MATCHVAL (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* PWM Match Value */ 00871 00872 /* ------------------------------------------------------------------------------------------------------------------------- 00873 AGPT0_INTEN Pos/Masks Description 00874 ------------------------------------------------------------------------------------------------------------------------- */ 00875 #define BITP_AGPT0_INTEN_INTEN 0 /* Interrupt Enable */ 00876 #define BITM_AGPT0_INTEN_INTEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Interrupt Enable */ 00877 00878 00879 /* ============================================================================================================================ 00880 General Purpose Timer 00881 ============================================================================================================================ */ 00882 00883 /* ============================================================================================================================ 00884 AGPT1 00885 ============================================================================================================================ */ 00886 #define REG_AGPT1_LD1 0x00000E00 /* AGPT1 16-bit Load Value Register */ 00887 #define REG_AGPT1_VAL1 0x00000E04 /* AGPT1 16-bit Timer Value Register */ 00888 #define REG_AGPT1_CON1 0x00000E08 /* AGPT1 Control Register */ 00889 #define REG_AGPT1_CLRI1 0x00000E0C /* AGPT1 Clear Interrupt Register */ 00890 #define REG_AGPT1_CAP1 0x00000E10 /* AGPT1 Capture Register */ 00891 #define REG_AGPT1_ALD1 0x00000E14 /* AGPT1 16-bit Load Value, Asynchronous Register */ 00892 #define REG_AGPT1_AVAL1 0x00000E18 /* AGPT1 16-bit Timer Value, Asynchronous Register */ 00893 #define REG_AGPT1_STA1 0x00000E1C /* AGPT1 Status Register */ 00894 #define REG_AGPT1_PWMCON1 0x00000E20 /* AGPT1 PWM Control Register */ 00895 #define REG_AGPT1_PWMMAT1 0x00000E24 /* AGPT1 PWM Match Value Register */ 00896 #define REG_AGPT1_INTEN1 0x00000E28 /* AGPT1 Interrupt Enable */ 00897 00898 /* ============================================================================================================================ 00899 AGPT1 Register BitMasks, Positions & Enumerations 00900 ============================================================================================================================ */ 00901 /* ------------------------------------------------------------------------------------------------------------------------- 00902 AGPT1_LD1 Pos/Masks Description 00903 ------------------------------------------------------------------------------------------------------------------------- */ 00904 #define BITP_AGPT1_LD1_LOAD 0 /* Load Value */ 00905 #define BITM_AGPT1_LD1_LOAD (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Load Value */ 00906 00907 /* ------------------------------------------------------------------------------------------------------------------------- 00908 AGPT1_VAL1 Pos/Masks Description 00909 ------------------------------------------------------------------------------------------------------------------------- */ 00910 #define BITP_AGPT1_VAL1_VAL 0 /* Current Count */ 00911 #define BITM_AGPT1_VAL1_VAL (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Current Count */ 00912 00913 /* ------------------------------------------------------------------------------------------------------------------------- 00914 AGPT1_CON1 Pos/Masks Description 00915 ------------------------------------------------------------------------------------------------------------------------- */ 00916 #define BITP_AGPT1_CON1_SYNCBYP 15 /* Synchronization Bypass */ 00917 #define BITP_AGPT1_CON1_RSTEN 14 /* Counter and Prescale Reset Enable */ 00918 #define BITP_AGPT1_CON1_EVENTEN 13 /* Event Select */ 00919 #define BITP_AGPT1_CON1_EVENT 8 /* Event Select Range */ 00920 #define BITP_AGPT1_CON1_RLD 7 /* Reload Control */ 00921 #define BITP_AGPT1_CON1_CLK 5 /* Clock Select */ 00922 #define BITP_AGPT1_CON1_ENABLE 4 /* Timer Enable */ 00923 #define BITP_AGPT1_CON1_MOD 3 /* Timer Mode */ 00924 #define BITP_AGPT1_CON1_UP 2 /* Count up */ 00925 #define BITP_AGPT1_CON1_PRE 0 /* Prescaler */ 00926 #define BITM_AGPT1_CON1_SYNCBYP (_ADI_MSK_3(0x00008000,0x00008000U, uint16_t )) /* Synchronization Bypass */ 00927 #define BITM_AGPT1_CON1_RSTEN (_ADI_MSK_3(0x00004000,0x00004000U, uint16_t )) /* Counter and Prescale Reset Enable */ 00928 #define BITM_AGPT1_CON1_EVENTEN (_ADI_MSK_3(0x00002000,0x00002000U, uint16_t )) /* Event Select */ 00929 #define BITM_AGPT1_CON1_EVENT (_ADI_MSK_3(0x00001F00,0x00001F00U, uint16_t )) /* Event Select Range */ 00930 #define BITM_AGPT1_CON1_RLD (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Reload Control */ 00931 #define BITM_AGPT1_CON1_CLK (_ADI_MSK_3(0x00000060,0x00000060U, uint16_t )) /* Clock Select */ 00932 #define BITM_AGPT1_CON1_ENABLE (_ADI_MSK_3(0x00000010,0x00000010U, uint16_t )) /* Timer Enable */ 00933 #define BITM_AGPT1_CON1_MOD (_ADI_MSK_3(0x00000008,0x00000008U, uint16_t )) /* Timer Mode */ 00934 #define BITM_AGPT1_CON1_UP (_ADI_MSK_3(0x00000004,0x00000004U, uint16_t )) /* Count up */ 00935 #define BITM_AGPT1_CON1_PRE (_ADI_MSK_3(0x00000003,0x00000003U, uint16_t )) /* Prescaler */ 00936 00937 /* ------------------------------------------------------------------------------------------------------------------------- 00938 AGPT1_CLRI1 Pos/Masks Description 00939 ------------------------------------------------------------------------------------------------------------------------- */ 00940 #define BITP_AGPT1_CLRI1_CAP 1 /* Clear Captured Event Interrupt */ 00941 #define BITP_AGPT1_CLRI1_TMOUT 0 /* Clear Timeout Interrupt */ 00942 #define BITM_AGPT1_CLRI1_CAP (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Clear Captured Event Interrupt */ 00943 #define BITM_AGPT1_CLRI1_TMOUT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Clear Timeout Interrupt */ 00944 00945 /* ------------------------------------------------------------------------------------------------------------------------- 00946 AGPT1_CAP1 Pos/Masks Description 00947 ------------------------------------------------------------------------------------------------------------------------- */ 00948 #define BITP_AGPT1_CAP1_CAP 0 /* 16-bit Captured Value. */ 00949 #define BITM_AGPT1_CAP1_CAP (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* 16-bit Captured Value. */ 00950 00951 /* ------------------------------------------------------------------------------------------------------------------------- 00952 AGPT1_ALD1 Pos/Masks Description 00953 ------------------------------------------------------------------------------------------------------------------------- */ 00954 #define BITP_AGPT1_ALD1_ALOAD 0 /* Load Value, Asynchronous */ 00955 #define BITM_AGPT1_ALD1_ALOAD (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Load Value, Asynchronous */ 00956 00957 /* ------------------------------------------------------------------------------------------------------------------------- 00958 AGPT1_AVAL1 Pos/Masks Description 00959 ------------------------------------------------------------------------------------------------------------------------- */ 00960 #define BITP_AGPT1_AVAL1_AVAL 0 /* Counter Value */ 00961 #define BITM_AGPT1_AVAL1_AVAL (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* Counter Value */ 00962 00963 /* ------------------------------------------------------------------------------------------------------------------------- 00964 AGPT1_STA1 Pos/Masks Description 00965 ------------------------------------------------------------------------------------------------------------------------- */ 00966 #define BITP_AGPT1_STA1_RSTCNT 8 /* Counter Reset Occurring */ 00967 #define BITP_AGPT1_STA1_PDOK 7 /* Clear Interrupt Register Synchronization */ 00968 #define BITP_AGPT1_STA1_BUSY 6 /* Timer Busy */ 00969 #define BITP_AGPT1_STA1_CAP 1 /* Capture Event Pending */ 00970 #define BITP_AGPT1_STA1_TMOUT 0 /* Timeout Event Occurred */ 00971 #define BITM_AGPT1_STA1_RSTCNT (_ADI_MSK_3(0x00000100,0x00000100U, uint16_t )) /* Counter Reset Occurring */ 00972 #define BITM_AGPT1_STA1_PDOK (_ADI_MSK_3(0x00000080,0x00000080U, uint16_t )) /* Clear Interrupt Register Synchronization */ 00973 #define BITM_AGPT1_STA1_BUSY (_ADI_MSK_3(0x00000040,0x00000040U, uint16_t )) /* Timer Busy */ 00974 #define BITM_AGPT1_STA1_CAP (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* Capture Event Pending */ 00975 #define BITM_AGPT1_STA1_TMOUT (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Timeout Event Occurred */ 00976 00977 /* ------------------------------------------------------------------------------------------------------------------------- 00978 AGPT1_PWMCON1 Pos/Masks Description 00979 ------------------------------------------------------------------------------------------------------------------------- */ 00980 #define BITP_AGPT1_PWMCON1_IDLE 1 /* PWM Idle State. */ 00981 #define BITP_AGPT1_PWMCON1_MATCHEN 0 /* PWM Match Enabled. */ 00982 #define BITM_AGPT1_PWMCON1_IDLE (_ADI_MSK_3(0x00000002,0x00000002U, uint16_t )) /* PWM Idle State. */ 00983 #define BITM_AGPT1_PWMCON1_MATCHEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* PWM Match Enabled. */ 00984 00985 /* ------------------------------------------------------------------------------------------------------------------------- 00986 AGPT1_PWMMAT1 Pos/Masks Description 00987 ------------------------------------------------------------------------------------------------------------------------- */ 00988 #define BITP_AGPT1_PWMMAT1_MATCHVAL 0 /* PWM Match Value */ 00989 #define BITM_AGPT1_PWMMAT1_MATCHVAL (_ADI_MSK_3(0x0000FFFF,0x0000FFFF, int16_t )) /* PWM Match Value */ 00990 00991 /* ------------------------------------------------------------------------------------------------------------------------- 00992 AGPT1_INTEN1 Pos/Masks Description 00993 ------------------------------------------------------------------------------------------------------------------------- */ 00994 #define BITP_AGPT1_INTEN1_INTEN 0 /* Interrupt Enable */ 00995 #define BITM_AGPT1_INTEN1_INTEN (_ADI_MSK_3(0x00000001,0x00000001U, uint16_t )) /* Interrupt Enable */ 00996 00997 00998 /* ============================================================================================================================ 00999 CRC Accelerator 01000 ============================================================================================================================ */ 01001 01002 /* ============================================================================================================================ 01003 AFECRC 01004 ============================================================================================================================ */ 01005 #define REG_AFECRC_CTL 0x00001000 /* AFECRC CRC Control Register */ 01006 #define REG_AFECRC_IPDATA 0x00001004 /* AFECRC Data Input. */ 01007 #define REG_AFECRC_RESULT 0x00001008 /* AFECRC CRC Residue */ 01008 #define REG_AFECRC_POLY 0x0000100C /* AFECRC CRC Reduction Polynomial */ 01009 #define REG_AFECRC_IPBITS 0x00001010 /* AFECRC Input Data Bits */ 01010 #define REG_AFECRC_IPBYTE 0x00001014 /* AFECRC Input Data Byte */ 01011 #define REG_AFECRC_CRC_SIG_COMP 0x00001020 /* AFECRC CRC Signature Compare Data Input. */ 01012 #define REG_AFECRC_CRCINTEN 0x00001024 /* AFECRC CRC Error Interrupt Enable Bit */ 01013 #define REG_AFECRC_INTSTA 0x00001028 /* AFECRC CRC Error Interrupt Status Bit */ 01014 01015 /* ============================================================================================================================ 01016 AFECRC Register BitMasks, Positions & Enumerations 01017 ============================================================================================================================ */ 01018 /* ------------------------------------------------------------------------------------------------------------------------- 01019 AFECRC_CTL Pos/Masks Description 01020 ------------------------------------------------------------------------------------------------------------------------- */ 01021 #define BITP_AFECRC_CTL_REVID 28 /* Revision ID */ 01022 #define BITP_AFECRC_CTL_MON_EN 9 /* Enable Apb32/Apb16 to Get Address/Data for CRC Calculation */ 01023 #define BITP_AFECRC_CTL_W16SWP 4 /* Word16 Swap Enabled. */ 01024 #define BITP_AFECRC_CTL_BYTMIRR 3 /* Byte Mirroring. */ 01025 #define BITP_AFECRC_CTL_BITMIRR 2 /* Bit Mirroring. */ 01026 #define BITP_AFECRC_CTL_LSBFIRST 1 /* LSB First Calculation Order */ 01027 #define BITP_AFECRC_CTL_EN 0 /* CRC Peripheral Enable */ 01028 #define BITM_AFECRC_CTL_REVID (_ADI_MSK_3(0xF0000000,0xF0000000UL, uint32_t )) /* Revision ID */ 01029 #define BITM_AFECRC_CTL_MON_EN (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* Enable Apb32/Apb16 to Get Address/Data for CRC Calculation */ 01030 #define BITM_AFECRC_CTL_W16SWP (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* Word16 Swap Enabled. */ 01031 #define BITM_AFECRC_CTL_BYTMIRR (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* Byte Mirroring. */ 01032 #define BITM_AFECRC_CTL_BITMIRR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Bit Mirroring. */ 01033 #define BITM_AFECRC_CTL_LSBFIRST (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* LSB First Calculation Order */ 01034 #define BITM_AFECRC_CTL_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* CRC Peripheral Enable */ 01035 01036 /* ------------------------------------------------------------------------------------------------------------------------- 01037 AFECRC_IPDATA Pos/Masks Description 01038 ------------------------------------------------------------------------------------------------------------------------- */ 01039 #define BITP_AFECRC_IPDATA_VALUE 0 /* Data Input. */ 01040 #define BITM_AFECRC_IPDATA_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFF, int32_t )) /* Data Input. */ 01041 01042 /* ------------------------------------------------------------------------------------------------------------------------- 01043 AFECRC_RESULT Pos/Masks Description 01044 ------------------------------------------------------------------------------------------------------------------------- */ 01045 #define BITP_AFECRC_RESULT_VALUE 0 /* CRC Residue */ 01046 #define BITM_AFECRC_RESULT_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFF, int32_t )) /* CRC Residue */ 01047 01048 /* ------------------------------------------------------------------------------------------------------------------------- 01049 AFECRC_POLY Pos/Masks Description 01050 ------------------------------------------------------------------------------------------------------------------------- */ 01051 #define BITP_AFECRC_POLY_VALUE 0 /* CRC Reduction Polynomial */ 01052 #define BITM_AFECRC_POLY_VALUE (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* CRC Reduction Polynomial */ 01053 01054 /* ------------------------------------------------------------------------------------------------------------------------- 01055 AFECRC_IPBITS Pos/Masks Description 01056 ------------------------------------------------------------------------------------------------------------------------- */ 01057 #define BITP_AFECRC_IPBITS_DATA_BITS 0 /* Input Data Bits. */ 01058 #define BITM_AFECRC_IPBITS_DATA_BITS (_ADI_MSK_3(0x000000FF,0x000000FFU, uint8_t )) /* Input Data Bits. */ 01059 01060 /* ------------------------------------------------------------------------------------------------------------------------- 01061 AFECRC_IPBYTE Pos/Masks Description 01062 ------------------------------------------------------------------------------------------------------------------------- */ 01063 #define BITP_AFECRC_IPBYTE_DATA_BYTE 0 /* Input Data Byte. */ 01064 #define BITM_AFECRC_IPBYTE_DATA_BYTE (_ADI_MSK_3(0x000000FF,0x000000FFU, uint8_t )) /* Input Data Byte. */ 01065 01066 /* ------------------------------------------------------------------------------------------------------------------------- 01067 AFECRC_CRC_SIG_COMP Pos/Masks Description 01068 ------------------------------------------------------------------------------------------------------------------------- */ 01069 #define BITP_AFECRC_CRC_SIG_COMP_CRC_SIG 0 /* CRC Signature Compare Data Input. */ 01070 #define BITM_AFECRC_CRC_SIG_COMP_CRC_SIG (_ADI_MSK_3(0xFFFFFFFF,0xFFFFFFFFUL, uint32_t )) /* CRC Signature Compare Data Input. */ 01071 01072 /* ------------------------------------------------------------------------------------------------------------------------- 01073 AFECRC_CRCINTEN Pos/Masks Description 01074 ------------------------------------------------------------------------------------------------------------------------- */ 01075 #define BITP_AFECRC_CRCINTEN_RESERVED_31_1 1 /* Reserved */ 01076 #define BITP_AFECRC_CRCINTEN_CRC_ERR_EN 0 /* CRC Error Interrupt Enable Bit */ 01077 #define BITM_AFECRC_CRCINTEN_RESERVED_31_1 (_ADI_MSK_3(0xFFFFFFFE,0xFFFFFFFEUL, uint32_t )) /* Reserved */ 01078 #define BITM_AFECRC_CRCINTEN_CRC_ERR_EN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* CRC Error Interrupt Enable Bit */ 01079 01080 /* ------------------------------------------------------------------------------------------------------------------------- 01081 AFECRC_INTSTA Pos/Masks Description 01082 ------------------------------------------------------------------------------------------------------------------------- */ 01083 #define BITP_AFECRC_INTSTA_CRC_ERR_ST 0 /* CRC Error Interrupt Status Bit */ 01084 #define BITM_AFECRC_INTSTA_CRC_ERR_ST (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* CRC Error Interrupt Status Bit */ 01085 01086 01087 /* ============================================================================================================================ 01088 01089 ============================================================================================================================ */ 01090 01091 /* ============================================================================================================================ 01092 AFE 01093 ============================================================================================================================ */ 01094 #define REG_AFE_AFECON_RESET 0x00080000 /* Reset Value for AFECON */ 01095 #define REG_AFE_AFECON 0x00002000 /* AFE AFE Configuration */ 01096 #define REG_AFE_SEQCON_RESET 0x00000002 /* Reset Value for SEQCON */ 01097 #define REG_AFE_SEQCON 0x00002004 /* AFE Sequencer Configuration */ 01098 #define REG_AFE_FIFOCON_RESET 0x00001010 /* Reset Value for FIFOCON */ 01099 #define REG_AFE_FIFOCON 0x00002008 /* AFE FIFOs Configuration */ 01100 #define REG_AFE_SWCON_RESET 0x0000FFFF /* Reset Value for SWCON */ 01101 #define REG_AFE_SWCON 0x0000200C /* AFE Switch Matrix Configuration */ 01102 #define REG_AFE_HSDACCON_RESET 0x0000001E /* Reset Value for HSDACCON */ 01103 #define REG_AFE_HSDACCON 0x00002010 /* AFE High Speed DAC Configuration */ 01104 #define REG_AFE_WGCON_RESET 0x00000030 /* Reset Value for WGCON */ 01105 #define REG_AFE_WGCON 0x00002014 /* AFE Waveform Generator Configuration */ 01106 #define REG_AFE_WGDCLEVEL1_RESET 0x00000000 /* Reset Value for WGDCLEVEL1 */ 01107 #define REG_AFE_WGDCLEVEL1 0x00002018 /* AFE Waveform Generator - Trapezoid DC Level 1 */ 01108 #define REG_AFE_WGDCLEVEL2_RESET 0x00000000 /* Reset Value for WGDCLEVEL2 */ 01109 #define REG_AFE_WGDCLEVEL2 0x0000201C /* AFE Waveform Generator - Trapezoid DC Level 2 */ 01110 #define REG_AFE_WGDELAY1_RESET 0x00000000 /* Reset Value for WGDELAY1 */ 01111 #define REG_AFE_WGDELAY1 0x00002020 /* AFE Waveform Generator - Trapezoid Delay 1 Time */ 01112 #define REG_AFE_WGSLOPE1_RESET 0x00000000 /* Reset Value for WGSLOPE1 */ 01113 #define REG_AFE_WGSLOPE1 0x00002024 /* AFE Waveform Generator - Trapezoid Slope 1 Time */ 01114 #define REG_AFE_WGDELAY2_RESET 0x00000000 /* Reset Value for WGDELAY2 */ 01115 #define REG_AFE_WGDELAY2 0x00002028 /* AFE Waveform Generator - Trapezoid Delay 2 Time */ 01116 #define REG_AFE_WGSLOPE2_RESET 0x00000000 /* Reset Value for WGSLOPE2 */ 01117 #define REG_AFE_WGSLOPE2 0x0000202C /* AFE Waveform Generator - Trapezoid Slope 2 Time */ 01118 #define REG_AFE_WGFCW_RESET 0x00000000 /* Reset Value for WGFCW */ 01119 #define REG_AFE_WGFCW 0x00002030 /* AFE Waveform Generator - Sinusoid Frequency Control Word */ 01120 #define REG_AFE_WGPHASE_RESET 0x00000000 /* Reset Value for WGPHASE */ 01121 #define REG_AFE_WGPHASE 0x00002034 /* AFE Waveform Generator - Sinusoid Phase Offset */ 01122 #define REG_AFE_WGOFFSET_RESET 0x00000000 /* Reset Value for WGOFFSET */ 01123 #define REG_AFE_WGOFFSET 0x00002038 /* AFE Waveform Generator - Sinusoid Offset */ 01124 #define REG_AFE_WGAMPLITUDE_RESET 0x00000000 /* Reset Value for WGAMPLITUDE */ 01125 #define REG_AFE_WGAMPLITUDE 0x0000203C /* AFE Waveform Generator - Sinusoid Amplitude */ 01126 #define REG_AFE_ADCFILTERCON_RESET 0x00000301 /* Reset Value for ADCFILTERCON */ 01127 #define REG_AFE_ADCFILTERCON 0x00002044 /* AFE ADC Output Filters Configuration */ 01128 #define REG_AFE_HSDACDAT_RESET 0x00000800 /* Reset Value for HSDACDAT */ 01129 #define REG_AFE_HSDACDAT 0x00002048 /* AFE HS DAC Code */ 01130 #define REG_AFE_LPREFBUFCON_RESET 0x00000000 /* Reset Value for LPREFBUFCON */ 01131 #define REG_AFE_LPREFBUFCON 0x00002050 /* AFE LPREF_BUF_CON */ 01132 #define REG_AFE_SYNCEXTDEVICE_RESET 0x00000000 /* Reset Value for SYNCEXTDEVICE */ 01133 #define REG_AFE_SYNCEXTDEVICE 0x00002054 /* AFE SYNC External Devices */ 01134 #define REG_AFE_SEQCRC_RESET 0x00000001 /* Reset Value for SEQCRC */ 01135 #define REG_AFE_SEQCRC 0x00002060 /* AFE Sequencer CRC Value */ 01136 #define REG_AFE_SEQCNT_RESET 0x00000000 /* Reset Value for SEQCNT */ 01137 #define REG_AFE_SEQCNT 0x00002064 /* AFE Sequencer Command Count */ 01138 #define REG_AFE_SEQTIMEOUT_RESET 0x00000000 /* Reset Value for SEQTIMEOUT */ 01139 #define REG_AFE_SEQTIMEOUT 0x00002068 /* AFE Sequencer Timeout Counter */ 01140 #define REG_AFE_DATAFIFORD_RESET 0x00000000 /* Reset Value for DATAFIFORD */ 01141 #define REG_AFE_DATAFIFORD 0x0000206C /* AFE Data FIFO Read */ 01142 #define REG_AFE_CMDFIFOWRITE_RESET 0x00000000 /* Reset Value for CMDFIFOWRITE */ 01143 #define REG_AFE_CMDFIFOWRITE 0x00002070 /* AFE Command FIFO Write */ 01144 #define REG_AFE_ADCDAT_RESET 0x00000000 /* Reset Value for ADCDAT */ 01145 #define REG_AFE_ADCDAT 0x00002074 /* AFE ADC Raw Result */ 01146 #define REG_AFE_DFTREAL_RESET 0x00000000 /* Reset Value for DFTREAL */ 01147 #define REG_AFE_DFTREAL 0x00002078 /* AFE DFT Result, Real Part */ 01148 #define REG_AFE_DFTIMAG_RESET 0x00000000 /* Reset Value for DFTIMAG */ 01149 #define REG_AFE_DFTIMAG 0x0000207C /* AFE DFT Result, Imaginary Part */ 01150 #define REG_AFE_SINC2DAT_RESET 0x00000000 /* Reset Value for SINC2DAT */ 01151 #define REG_AFE_SINC2DAT 0x00002080 /* AFE Supply Rejection Filter Result */ 01152 #define REG_AFE_TEMPSENSDAT_RESET 0x00000000 /* Reset Value for TEMPSENSDAT */ 01153 #define REG_AFE_TEMPSENSDAT 0x00002084 /* AFE Temperature Sensor Result */ 01154 #define REG_AFE_AFEGENINTSTA_RESET 0x00000000 /* Reset Value for AFEGENINTSTA */ 01155 #define REG_AFE_AFEGENINTSTA 0x0000209C /* AFE Analog Generation Interrupt */ 01156 #define REG_AFE_ADCMIN_RESET 0x00000000 /* Reset Value for ADCMIN */ 01157 #define REG_AFE_ADCMIN 0x000020A8 /* AFE ADC Minimum Value Check */ 01158 #define REG_AFE_ADCMINSM_RESET 0x00000000 /* Reset Value for ADCMINSM */ 01159 #define REG_AFE_ADCMINSM 0x000020AC /* AFE ADCMIN Hysteresis Value */ 01160 #define REG_AFE_ADCMAX_RESET 0x00000000 /* Reset Value for ADCMAX */ 01161 #define REG_AFE_ADCMAX 0x000020B0 /* AFE ADC Maximum Value Check */ 01162 #define REG_AFE_ADCMAXSMEN_RESET 0x00000000 /* Reset Value for ADCMAXSMEN */ 01163 #define REG_AFE_ADCMAXSMEN 0x000020B4 /* AFE ADCMAX Hysteresis Value */ 01164 #define REG_AFE_ADCDELTA_RESET 0x00000000 /* Reset Value for ADCDELTA */ 01165 #define REG_AFE_ADCDELTA 0x000020B8 /* AFE ADC Delta Value */ 01166 #define REG_AFE_HPOSCCON_RESET 0x00000024 /* Reset Value for HPOSCCON */ 01167 #define REG_AFE_HPOSCCON 0x000020BC /* AFE HPOSC Configuration */ 01168 #define REG_AFE_DFTCON_RESET 0x00000090 /* Reset Value for DFTCON */ 01169 #define REG_AFE_DFTCON 0x000020D0 /* AFE AFE DSP Configuration */ 01170 #define REG_AFE_LPTIASW1 0x000020E0 /* AFE ULPTIA Switch Configuration for Channel 1 */ 01171 #define REG_AFE_LPTIASW0_RESET 0x00000000 /* Reset Value for LPTIASW0 */ 01172 #define REG_AFE_LPTIACON1 0x000020E8 /* AFE ULPTIA Control Bits Channel 1 */ 01173 #define REG_AFE_LPTIASW0 0x000020E4 /* AFE ULPTIA Switch Configuration for Channel 0 */ 01174 #define REG_AFE_LPTIACON0_RESET 0x00000003 /* Reset Value for LPTIACON0 */ 01175 #define REG_AFE_LPTIACON0 0x000020EC /* AFE ULPTIA Control Bits Channel 0 */ 01176 #define REG_AFE_HSRTIACON_RESET 0x0000000F /* Reset Value for HSRTIACON */ 01177 #define REG_AFE_HSRTIACON 0x000020F0 /* AFE High Power RTIA Configuration */ 01178 #define REG_AFE_DE1RESCON 0x000020F4 /* AFE DE1 HSTIA Resistors Configuration */ 01179 #define REG_AFE_DE0RESCON_RESET 0x000000FF /* Reset Value for DE0RESCON */ 01180 #define REG_AFE_DE0RESCON 0x000020F8 /* AFE DE0 HSTIA Resistors Configuration */ 01181 #define REG_AFE_HSTIACON_RESET 0x00000000 /* Reset Value for HSTIACON */ 01182 #define REG_AFE_HSTIACON 0x000020FC /* AFE HSTIA Amplifier Configuration */ 01183 #define REG_AFE_LPMODEKEY_RESET 0x00000000 /* Reset Value for LPMODEKEY */ 01184 #define REG_AFE_LPMODEKEY 0x0000210C /* AFE LP Mode AFE Control Lock */ 01185 #define REG_AFE_LPMODECLKSEL_RESET 0x00000000 /* Reset Value for LPMODECLKSEL */ 01186 #define REG_AFE_LPMODECLKSEL 0x00002110 /* AFE LFSYSCLKEN */ 01187 #define REG_AFE_LPMODECON_RESET 0x00000102 /* Reset Value for LPMODECON */ 01188 #define REG_AFE_LPMODECON 0x00002114 /* AFE LPMODECON */ 01189 #define REG_AFE_SEQSLPLOCK_RESET 0x00000000 /* Reset Value for SEQSLPLOCK */ 01190 #define REG_AFE_SEQSLPLOCK 0x00002118 /* AFE Sequencer Sleep Control Lock */ 01191 #define REG_AFE_SEQTRGSLP_RESET 0x00000000 /* Reset Value for SEQTRGSLP */ 01192 #define REG_AFE_SEQTRGSLP 0x0000211C /* AFE Sequencer Trigger Sleep */ 01193 #define REG_AFE_LPDACDAT0_RESET 0x00000000 /* Reset Value for LPDACDAT0 */ 01194 #define REG_AFE_LPDACDAT0 0x00002120 /* AFE LPDAC Data-out */ 01195 #define REG_AFE_LPDACSW0_RESET 0x00000000 /* Reset Value for LPDACSW0 */ 01196 #define REG_AFE_LPDACSW0 0x00002124 /* AFE LPDAC0 Switch Control */ 01197 #define REG_AFE_LPDACCON0_RESET 0x00000002 /* Reset Value for LPDACCON0 */ 01198 #define REG_AFE_LPDACCON0 0x00002128 /* AFE LPDAC Control Bits */ 01199 #define REG_AFE_LPDACDAT1 0x0000212C /* AFE Low Power DAC1 data register */ 01200 #define REG_AFE_LPDACSW1 0x00002130 /* AFE Control register for switches to LPDAC1 */ 01201 #define REG_AFE_LPDACCON1 0x00002134 /* AFE ULP_DACCON1 */ 01202 #define REG_AFE_DSWFULLCON_RESET 0x00000000 /* Reset Value for DSWFULLCON */ 01203 #define REG_AFE_DSWFULLCON 0x00002150 /* AFE Switch Matrix Full Configuration (D) */ 01204 #define REG_AFE_NSWFULLCON_RESET 0x00000000 /* Reset Value for NSWFULLCON */ 01205 #define REG_AFE_NSWFULLCON 0x00002154 /* AFE Switch Matrix Full Configuration (N) */ 01206 #define REG_AFE_PSWFULLCON_RESET 0x00000000 /* Reset Value for PSWFULLCON */ 01207 #define REG_AFE_PSWFULLCON 0x00002158 /* AFE Switch Matrix Full Configuration (P) */ 01208 #define REG_AFE_TSWFULLCON_RESET 0x00000000 /* Reset Value for TSWFULLCON */ 01209 #define REG_AFE_TSWFULLCON 0x0000215C /* AFE Switch Matrix Full Configuration (T) */ 01210 #define REG_AFE_TEMPSENS_RESET 0x00000000 /* Reset Value for TEMPSENS */ 01211 #define REG_AFE_TEMPSENS 0x00002174 /* AFE Temp Sensor Configuration */ 01212 #define REG_AFE_BUFSENCON_RESET 0x00000037 /* Reset Value for BUFSENCON */ 01213 #define REG_AFE_BUFSENCON 0x00002180 /* AFE HP and LP Buffer Control */ 01214 #define REG_AFE_ADCCON_RESET 0x00000000 /* Reset Value for ADCCON */ 01215 #define REG_AFE_ADCCON 0x000021A8 /* AFE ADC Configuration */ 01216 #define REG_AFE_DSWSTA_RESET 0x00000000 /* Reset Value for DSWSTA */ 01217 #define REG_AFE_DSWSTA 0x000021B0 /* AFE Switch Matrix Status (D) */ 01218 #define REG_AFE_PSWSTA_RESET 0x00006000 /* Reset Value for PSWSTA */ 01219 #define REG_AFE_PSWSTA 0x000021B4 /* AFE Switch Matrix Status (P) */ 01220 #define REG_AFE_NSWSTA_RESET 0x00000C00 /* Reset Value for NSWSTA */ 01221 #define REG_AFE_NSWSTA 0x000021B8 /* AFE Switch Matrix Status (N) */ 01222 #define REG_AFE_TSWSTA_RESET 0x00000000 /* Reset Value for TSWSTA */ 01223 #define REG_AFE_TSWSTA 0x000021BC /* AFE Switch Matrix Status (T) */ 01224 #define REG_AFE_STATSVAR_RESET 0x00000000 /* Reset Value for STATSVAR */ 01225 #define REG_AFE_STATSVAR 0x000021C0 /* AFE Variance Output */ 01226 #define REG_AFE_STATSCON_RESET 0x00000000 /* Reset Value for STATSCON */ 01227 #define REG_AFE_STATSCON 0x000021C4 /* AFE Statistics Control */ 01228 #define REG_AFE_STATSMEAN_RESET 0x00000000 /* Reset Value for STATSMEAN */ 01229 #define REG_AFE_STATSMEAN 0x000021C8 /* AFE Statistics Mean Output */ 01230 #define REG_AFE_SEQ0INFO_RESET 0x00000000 /* Reset Value for SEQ0INFO */ 01231 #define REG_AFE_SEQ0INFO 0x000021CC /* AFE Sequence 0 Info */ 01232 #define REG_AFE_SEQ2INFO_RESET 0x00000000 /* Reset Value for SEQ2INFO */ 01233 #define REG_AFE_SEQ2INFO 0x000021D0 /* AFE Sequence 2 Info */ 01234 #define REG_AFE_CMDFIFOWADDR_RESET 0x00000000 /* Reset Value for CMDFIFOWADDR */ 01235 #define REG_AFE_CMDFIFOWADDR 0x000021D4 /* AFE Command FIFO Write Address */ 01236 #define REG_AFE_CMDDATACON_RESET 0x00000410 /* Reset Value for CMDDATACON */ 01237 #define REG_AFE_CMDDATACON 0x000021D8 /* AFE Command Data Control */ 01238 #define REG_AFE_DATAFIFOTHRES_RESET 0x00000000 /* Reset Value for DATAFIFOTHRES */ 01239 #define REG_AFE_DATAFIFOTHRES 0x000021E0 /* AFE Data FIFO Threshold */ 01240 #define REG_AFE_SEQ3INFO_RESET 0x00000000 /* Reset Value for SEQ3INFO */ 01241 #define REG_AFE_SEQ3INFO 0x000021E4 /* AFE Sequence 3 Info */ 01242 #define REG_AFE_SEQ1INFO_RESET 0x00000000 /* Reset Value for SEQ1INFO */ 01243 #define REG_AFE_SEQ1INFO 0x000021E8 /* AFE Sequence 1 Info */ 01244 #define REG_AFE_REPEATADCCNV_RESET 0x00000160 /* Reset Value for REPEATADCCNV */ 01245 #define REG_AFE_REPEATADCCNV 0x000021F0 /* AFE REPEAT ADC Conversions */ 01246 #define REG_AFE_FIFOCNTSTA_RESET 0x00000000 /* Reset Value for FIFOCNTSTA */ 01247 #define REG_AFE_FIFOCNTSTA 0x00002200 /* AFE CMD and DATA FIFO INTERNAL DATA COUNT */ 01248 #define REG_AFE_CALDATLOCK_RESET 0x00000000 /* Reset Value for CALDATLOCK */ 01249 #define REG_AFE_CALDATLOCK 0x00002230 /* AFE Calibration Data Lock */ 01250 #define REG_AFE_ADCOFFSETHSTIA_RESET 0x00000000 /* Reset Value for ADCOFFSETHSTIA */ 01251 #define REG_AFE_ADCOFFSETHSTIA 0x00002234 /* AFE ADC Offset Calibration High Speed TIA Channel */ 01252 #define REG_AFE_ADCGAINTEMPSENS0_RESET 0x00004000 /* Reset Value for ADCGAINTEMPSENS0 */ 01253 #define REG_AFE_ADCGAINTEMPSENS0 0x00002238 /* AFE ADC Gain Calibration Temp Sensor Channel */ 01254 #define REG_AFE_ADCOFFSETTEMPSENS0_RESET 0x00000000 /* Reset Value for ADCOFFSETTEMPSENS0 */ 01255 #define REG_AFE_ADCOFFSETTEMPSENS0 0x0000223C /* AFE ADC Offset Calibration Temp Sensor Channel 0 */ 01256 #define REG_AFE_ADCGAINGN1_RESET 0x00004000 /* Reset Value for ADCGAINGN1 */ 01257 #define REG_AFE_ADCGAINGN1 0x00002240 /* AFE ADCPGAGN1: ADC Gain Calibration Auxiliary Input Channel */ 01258 #define REG_AFE_ADCOFFSETGN1_RESET 0x00000000 /* Reset Value for ADCOFFSETGN1 */ 01259 #define REG_AFE_ADCOFFSETGN1 0x00002244 /* AFE ADC Offset Calibration Auxiliary Channel (PGA Gain=1) */ 01260 #define REG_AFE_DACGAIN_RESET 0x00000800 /* Reset Value for DACGAIN */ 01261 #define REG_AFE_DACGAIN 0x00002260 /* AFE DACGAIN */ 01262 #define REG_AFE_DACOFFSETATTEN_RESET 0x00000000 /* Reset Value for DACOFFSETATTEN */ 01263 #define REG_AFE_DACOFFSETATTEN 0x00002264 /* AFE DAC Offset with Attenuator Enabled (LP Mode) */ 01264 #define REG_AFE_DACOFFSET_RESET 0x00000000 /* Reset Value for DACOFFSET */ 01265 #define REG_AFE_DACOFFSET 0x00002268 /* AFE DAC Offset with Attenuator Disabled (LP Mode) */ 01266 #define REG_AFE_ADCGAINGN1P5_RESET 0x00004000 /* Reset Value for ADCGAINGN1P5 */ 01267 #define REG_AFE_ADCGAINGN1P5 0x00002270 /* AFE ADC Gain Calibration Auxiliary Input Channel (PGA Gain=1.5) */ 01268 #define REG_AFE_ADCGAINGN2_RESET 0x00004000 /* Reset Value for ADCGAINGN2 */ 01269 #define REG_AFE_ADCGAINGN2 0x00002274 /* AFE ADC Gain Calibration Auxiliary Input Channel (PGA Gain=2) */ 01270 #define REG_AFE_ADCGAINGN4_RESET 0x00004000 /* Reset Value for ADCGAINGN4 */ 01271 #define REG_AFE_ADCGAINGN4 0x00002278 /* AFE ADC Gain Calibration Auxiliary Input Channel (PGA Gain=4) */ 01272 #define REG_AFE_ADCPGAOFFSETCANCEL_RESET 0x00000000 /* Reset Value for ADCPGAOFFSETCANCEL */ 01273 #define REG_AFE_ADCPGAOFFSETCANCEL 0x00002280 /* AFE ADC Offset Cancellation (Optional) */ 01274 #define REG_AFE_ADCGNHSTIA_RESET 0x00004000 /* Reset Value for ADCGNHSTIA */ 01275 #define REG_AFE_ADCGNHSTIA 0x00002284 /* AFE ADC Gain Calibration for HS TIA Channel */ 01276 #define REG_AFE_ADCOFFSETLPTIA0_RESET 0x00000000 /* Reset Value for ADCOFFSETLPTIA0 */ 01277 #define REG_AFE_ADCOFFSETLPTIA0 0x00002288 /* AFE ADC Offset Calibration ULP-TIA0 Channel */ 01278 #define REG_AFE_ADCGNLPTIA0_RESET 0x00004000 /* Reset Value for ADCGNLPTIA0 */ 01279 #define REG_AFE_ADCGNLPTIA0 0x0000228C /* AFE ADC GAIN Calibration for LP TIA0 Channel */ 01280 #define REG_AFE_ADCPGAGN4OFCAL_RESET 0x00004000 /* Reset Value for ADCPGAGN4OFCAL */ 01281 #define REG_AFE_ADCPGAGN4OFCAL 0x00002294 /* AFE ADC Gain Calibration with DC Cancellation(PGA G=4) */ 01282 #define REG_AFE_ADCGAINGN9_RESET 0x00004000 /* Reset Value for ADCGAINGN9 */ 01283 #define REG_AFE_ADCGAINGN9 0x00002298 /* AFE ADC Gain Calibration Auxiliary Input Channel (PGA Gain=9) */ 01284 #define REG_AFE_ADCOFFSETEMPSENS1_RESET 0x00000000 /* Reset Value for ADCOFFSETEMPSENS1 */ 01285 #define REG_AFE_ADCOFFSETEMPSENS1 0x000022A8 /* AFE ADC Offset Calibration Temp Sensor Channel 1 */ 01286 #define REG_AFE_ADCGAINDIOTEMPSENS_RESET 0x00004000 /* Reset Value for ADCGAINDIOTEMPSENS */ 01287 #define REG_AFE_ADCGAINDIOTEMPSENS 0x000022AC /* AFE ADC Gain Calibration Diode Temperature Sensor Channel */ 01288 #define REG_AFE_DACOFFSETATTENHP_RESET 0x00000000 /* Reset Value for DACOFFSETATTENHP */ 01289 #define REG_AFE_DACOFFSETATTENHP 0x000022B8 /* AFE DAC Offset with Attenuator Enabled (HP Mode) */ 01290 #define REG_AFE_DACOFFSETHP_RESET 0x00000000 /* Reset Value for DACOFFSETHP */ 01291 #define REG_AFE_DACOFFSETHP 0x000022BC /* AFE DAC Offset with Attenuator Disabled (HP Mode) */ 01292 #define REG_AFE_ADCGNLPTIA1_RESET 0x00004000 /* Reset Value for ADCGNLPTIA1 */ 01293 #define REG_AFE_ADCOFFSETLPTIA1 0x000022C0 /* AFE ADC Offset Calibration ULP-TIA0 Channel */ 01294 #define REG_AFE_ADCGNLPTIA1 0x000022C4 /* AFE ADC GAIN Calibration for LP TIA1 Channel */ 01295 #define REG_AFE_ADCOFFSETGN2_RESET 0x00000000 /* Reset Value for ADCOFFSETGN2 */ 01296 #define REG_AFE_ADCOFFSETGN2 0x000022C8 /* AFE Offset Calibration Auxiliary Channel (PGA Gain =2) */ 01297 #define REG_AFE_ADCOFFSETGN1P5_RESET 0x00000000 /* Reset Value for ADCOFFSETGN1P5 */ 01298 #define REG_AFE_ADCOFFSETGN1P5 0x000022CC /* AFE Offset Calibration Auxiliary Channel (PGA Gain =1.5) */ 01299 #define REG_AFE_ADCOFFSETGN9_RESET 0x00000000 /* Reset Value for ADCOFFSETGN9 */ 01300 #define REG_AFE_ADCOFFSETGN9 0x000022D0 /* AFE Offset Calibration Auxiliary Channel (PGA Gain =9) */ 01301 #define REG_AFE_ADCOFFSETGN4_RESET 0x00000000 /* Reset Value for ADCOFFSETGN4 */ 01302 #define REG_AFE_ADCOFFSETGN4 0x000022D4 /* AFE Offset Calibration Auxiliary Channel (PGA Gain =4) */ 01303 #define REG_AFE_PMBW_RESET 0x00088800 /* Reset Value for PMBW */ 01304 #define REG_AFE_PMBW 0x000022F0 /* AFE Power Mode Configuration */ 01305 #define REG_AFE_SWMUX_RESET 0x00000000 /* Reset Value for SWMUX */ 01306 #define REG_AFE_SWMUX 0x0000235C /* AFE Switch Mux for ECG */ 01307 #define REG_AFE_AFE_TEMPSEN_DIO_RESET 0x00020000 /* Reset Value for AFE_TEMPSEN_DIO */ 01308 #define REG_AFE_AFE_TEMPSEN_DIO 0x00002374 /* AFE AFE_TEMPSEN_DIO */ 01309 #define REG_AFE_ADCBUFCON_RESET 0x005F3D00 /* Reset Value for ADCBUFCON */ 01310 #define REG_AFE_ADCBUFCON 0x0000238C /* AFE Configure ADC Input Buffer */ 01311 01312 /* ============================================================================================================================ 01313 AFE Register BitMasks, Positions & Enumerations 01314 ============================================================================================================================ */ 01315 /* ------------------------------------------------------------------------------------------------------------------------- 01316 AFE_AFECON Pos/Masks Description 01317 ------------------------------------------------------------------------------------------------------------------------- */ 01318 #define BITP_AFE_AFECON_DACBUFEN 21 /* Enable DC DAC Buffer */ 01319 #define BITP_AFE_AFECON_DACREFEN 20 /* High Speed DAC Reference Enable */ 01320 #define BITP_AFE_AFECON_ALDOILIMITEN 19 /* Analog LDO Current Limiting Enable */ 01321 #define BITP_AFE_AFECON_SINC2EN 16 /* ADC Output 50/60Hz Filter Enable */ 01322 #define BITP_AFE_AFECON_DFTEN 15 /* DFT Hardware Accelerator Enable */ 01323 #define BITP_AFE_AFECON_WAVEGENEN 14 /* Waveform Generator Enable */ 01324 #define BITP_AFE_AFECON_TEMPCONVEN 13 /* ADC Temp Sensor Convert Enable */ 01325 #define BITP_AFE_AFECON_TEMPSENSEN 12 /* ADC Temperature Sensor Channel Enable */ 01326 #define BITP_AFE_AFECON_TIAEN 11 /* High Power TIA Enable */ 01327 #define BITP_AFE_AFECON_INAMPEN 10 /* Enable Excitation Amplifier */ 01328 #define BITP_AFE_AFECON_EXBUFEN 9 /* Enable Excitation Buffer */ 01329 #define BITP_AFE_AFECON_ADCCONVEN 8 /* ADC Conversion Start Enable */ 01330 #define BITP_AFE_AFECON_ADCEN 7 /* ADC Power Enable */ 01331 #define BITP_AFE_AFECON_DACEN 6 /* High Power DAC Enable */ 01332 #define BITP_AFE_AFECON_HPREFDIS 5 /* Disable High Power Reference */ 01333 #define BITM_AFE_AFECON_DACBUFEN 0x00200000 /* Enable DC DAC Buffer */ 01334 #define BITM_AFE_AFECON_DACREFEN 0x00100000 /* High Speed DAC Reference Enable */ 01335 #define BITM_AFE_AFECON_ALDOILIMITEN 0x00080000 /* Analog LDO Current Limiting Enable */ 01336 #define BITM_AFE_AFECON_SINC2EN 0x00010000 /* ADC Output 50/60Hz Filter Enable */ 01337 #define BITM_AFE_AFECON_DFTEN 0x00008000 /* DFT Hardware Accelerator Enable */ 01338 #define BITM_AFE_AFECON_WAVEGENEN 0x00004000 /* Waveform Generator Enable */ 01339 #define BITM_AFE_AFECON_TEMPCONVEN 0x00002000 /* ADC Temp Sensor Convert Enable */ 01340 #define BITM_AFE_AFECON_TEMPSENSEN 0x00001000 /* ADC Temperature Sensor Channel Enable */ 01341 #define BITM_AFE_AFECON_TIAEN 0x00000800 /* High Power TIA Enable */ 01342 #define BITM_AFE_AFECON_INAMPEN 0x00000400 /* Enable Excitation Amplifier */ 01343 #define BITM_AFE_AFECON_EXBUFEN 0x00000200 /* Enable Excitation Buffer */ 01344 #define BITM_AFE_AFECON_ADCCONVEN 0x00000100 /* ADC Conversion Start Enable */ 01345 #define BITM_AFE_AFECON_ADCEN 0x00000080 /* ADC Power Enable */ 01346 #define BITM_AFE_AFECON_DACEN 0x00000040 /* High Power DAC Enable */ 01347 #define BITM_AFE_AFECON_HPREFDIS 0x00000020 /* Disable High Power Reference */ 01348 #define ENUM_AFE_AFECON_OFF 0x00000000 /* DACEN: High Power DAC Disabled */ 01349 #define ENUM_AFE_AFECON_ON 0x00000040 /* DACEN: High Power DAC Enabled */ 01350 01351 /* ------------------------------------------------------------------------------------------------------------------------- 01352 AFE_SEQCON Pos/Masks Description 01353 ------------------------------------------------------------------------------------------------------------------------- */ 01354 #define BITP_AFE_SEQCON_SEQWRTMR 8 /* Timer for Sequencer Write Commands */ 01355 #define BITP_AFE_SEQCON_SEQHALT 4 /* Halt Seq */ 01356 #define BITP_AFE_SEQCON_SEQHALTFIFOEMPTY 1 /* Halt Sequencer If Empty */ 01357 #define BITP_AFE_SEQCON_SEQEN 0 /* Enable Sequencer */ 01358 #define BITM_AFE_SEQCON_SEQWRTMR 0x0000FF00 /* Timer for Sequencer Write Commands */ 01359 #define BITM_AFE_SEQCON_SEQHALT 0x00000010 /* Halt Seq */ 01360 #define BITM_AFE_SEQCON_SEQHALTFIFOEMPTY 0x00000002 /* Halt Sequencer If Empty */ 01361 #define BITM_AFE_SEQCON_SEQEN 0x00000001 /* Enable Sequencer */ 01362 01363 /* ------------------------------------------------------------------------------------------------------------------------- 01364 AFE_FIFOCON Pos/Masks Description 01365 ------------------------------------------------------------------------------------------------------------------------- */ 01366 #define BITP_AFE_FIFOCON_DATAFIFOSRCSEL 13 /* Selects the Source for the Data FIFO. */ 01367 #define BITP_AFE_FIFOCON_DATAFIFOEN 11 /* Data FIFO Enable. */ 01368 #define BITM_AFE_FIFOCON_DATAFIFOSRCSEL 0x0000E000 /* Selects the Source for the Data FIFO. */ 01369 #define BITM_AFE_FIFOCON_DATAFIFOEN 0x00000800 /* Data FIFO Enable. */ 01370 01371 /* ------------------------------------------------------------------------------------------------------------------------- 01372 AFE_SWCON Pos/Masks Description 01373 ------------------------------------------------------------------------------------------------------------------------- */ 01374 #define BITP_AFE_SWCON_T11CON 19 /* Control of T[11] */ 01375 #define BITP_AFE_SWCON_T10CON 18 /* Control of T[10] */ 01376 #define BITP_AFE_SWCON_T9CON 17 /* Control of T[9] */ 01377 #define BITP_AFE_SWCON_SWSOURCESEL 16 /* Switch Control Select */ 01378 #define BITP_AFE_SWCON_TMUXCON 12 /* Control of T Switch MUX. */ 01379 #define BITP_AFE_SWCON_NMUXCON 8 /* Control of N Switch MUX */ 01380 #define BITP_AFE_SWCON_PMUXCON 4 /* Control of P Switch MUX */ 01381 #define BITP_AFE_SWCON_DMUXCON 0 /* Control of D Switch MUX */ 01382 #define BITM_AFE_SWCON_T11CON 0x00080000 /* Control of T[11] */ 01383 #define BITM_AFE_SWCON_T10CON 0x00040000 /* Control of T[10] */ 01384 #define BITM_AFE_SWCON_T9CON 0x00020000 /* Control of T[9] */ 01385 #define BITM_AFE_SWCON_SWSOURCESEL 0x00010000 /* Switch Control Select */ 01386 #define BITM_AFE_SWCON_TMUXCON 0x0000F000 /* Control of T Switch MUX. */ 01387 #define BITM_AFE_SWCON_NMUXCON 0x00000F00 /* Control of N Switch MUX */ 01388 #define BITM_AFE_SWCON_PMUXCON 0x000000F0 /* Control of P Switch MUX */ 01389 #define BITM_AFE_SWCON_DMUXCON 0x0000000F /* Control of D Switch MUX */ 01390 01391 /* ------------------------------------------------------------------------------------------------------------------------- 01392 AFE_HSDACCON Pos/Masks Description 01393 ------------------------------------------------------------------------------------------------------------------------- */ 01394 #define BITP_AFE_HSDACCON_INAMPGNMDE 12 /* Excitation Amplifier Gain Control */ 01395 #define BITP_AFE_HSDACCON_RATE 1 /* DAC Update Rate */ 01396 #define BITP_AFE_HSDACCON_ATTENEN 0 /* PGA Stage Gain Attenuation */ 01397 #define BITM_AFE_HSDACCON_INAMPGNMDE 0x00001000 /* Excitation Amplifier Gain Control */ 01398 #define BITM_AFE_HSDACCON_RATE 0x000001FE /* DAC Update Rate */ 01399 #define BITM_AFE_HSDACCON_ATTENEN 0x00000001 /* PGA Stage Gain Attenuation */ 01400 01401 /* ------------------------------------------------------------------------------------------------------------------------- 01402 AFE_WGCON Pos/Masks Description 01403 ------------------------------------------------------------------------------------------------------------------------- */ 01404 #define BITP_AFE_WGCON_DACGAINCAL 5 /* Bypass DAC Gain */ 01405 #define BITP_AFE_WGCON_DACOFFSETCAL 4 /* Bypass DAC Offset */ 01406 #define BITP_AFE_WGCON_TYPESEL 1 /* Selects the Type of Waveform */ 01407 #define BITP_AFE_WGCON_TRAPRSTEN 0 /* Resets the Trapezoid Waveform Generator */ 01408 #define BITM_AFE_WGCON_DACGAINCAL 0x00000020 /* Bypass DAC Gain */ 01409 #define BITM_AFE_WGCON_DACOFFSETCAL 0x00000010 /* Bypass DAC Offset */ 01410 #define BITM_AFE_WGCON_TYPESEL 0x00000006 /* Selects the Type of Waveform */ 01411 #define BITM_AFE_WGCON_TRAPRSTEN 0x00000001 /* Resets the Trapezoid Waveform Generator */ 01412 01413 /* ------------------------------------------------------------------------------------------------------------------------- 01414 AFE_WGDCLEVEL1 Pos/Masks Description 01415 ------------------------------------------------------------------------------------------------------------------------- */ 01416 #define BITP_AFE_WGDCLEVEL1_TRAPDCLEVEL1 0 /* DC Level 1 Value for Trapezoid Waveform Generation */ 01417 #define BITM_AFE_WGDCLEVEL1_TRAPDCLEVEL1 0x00000FFF /* DC Level 1 Value for Trapezoid Waveform Generation */ 01418 01419 /* ------------------------------------------------------------------------------------------------------------------------- 01420 AFE_WGDCLEVEL2 Pos/Masks Description 01421 ------------------------------------------------------------------------------------------------------------------------- */ 01422 #define BITP_AFE_WGDCLEVEL2_TRAPDCLEVEL2 0 /* DC Level 2 Value for Trapezoid Waveform Generation */ 01423 #define BITM_AFE_WGDCLEVEL2_TRAPDCLEVEL2 0x00000FFF /* DC Level 2 Value for Trapezoid Waveform Generation */ 01424 01425 /* ------------------------------------------------------------------------------------------------------------------------- 01426 AFE_WGDELAY1 Pos/Masks Description 01427 ------------------------------------------------------------------------------------------------------------------------- */ 01428 #define BITP_AFE_WGDELAY1_DELAY1 0 /* Delay 1 Value for Trapezoid Waveform Generation */ 01429 #define BITM_AFE_WGDELAY1_DELAY1 0x000FFFFF /* Delay 1 Value for Trapezoid Waveform Generation */ 01430 01431 /* ------------------------------------------------------------------------------------------------------------------------- 01432 AFE_WGSLOPE1 Pos/Masks Description 01433 ------------------------------------------------------------------------------------------------------------------------- */ 01434 #define BITP_AFE_WGSLOPE1_SLOPE1 0 /* Slope 1 Value for Trapezoid Waveform Generation */ 01435 #define BITM_AFE_WGSLOPE1_SLOPE1 0x000FFFFF /* Slope 1 Value for Trapezoid Waveform Generation */ 01436 01437 /* ------------------------------------------------------------------------------------------------------------------------- 01438 AFE_WGDELAY2 Pos/Masks Description 01439 ------------------------------------------------------------------------------------------------------------------------- */ 01440 #define BITP_AFE_WGDELAY2_DELAY2 0 /* Delay 2 Value for Trapezoid Waveform Generation */ 01441 #define BITM_AFE_WGDELAY2_DELAY2 0x000FFFFF /* Delay 2 Value for Trapezoid Waveform Generation */ 01442 01443 /* ------------------------------------------------------------------------------------------------------------------------- 01444 AFE_WGSLOPE2 Pos/Masks Description 01445 ------------------------------------------------------------------------------------------------------------------------- */ 01446 #define BITP_AFE_WGSLOPE2_SLOPE2 0 /* Slope 2 Value for Trapezoid Waveform Generation. */ 01447 #define BITM_AFE_WGSLOPE2_SLOPE2 0x000FFFFF /* Slope 2 Value for Trapezoid Waveform Generation. */ 01448 01449 /* ------------------------------------------------------------------------------------------------------------------------- 01450 AFE_WGFCW Pos/Masks Description 01451 ------------------------------------------------------------------------------------------------------------------------- */ 01452 #define BITP_AFE_WGFCW_SINEFCW 0 /* Sinusoid Generator Frequency Control Word */ 01453 #define BITM_AFE_WGFCW_SINEFCW 0x00FFFFFF /* Sinusoid Generator Frequency Control Word */ 01454 01455 /* ------------------------------------------------------------------------------------------------------------------------- 01456 AFE_WGPHASE Pos/Masks Description 01457 ------------------------------------------------------------------------------------------------------------------------- */ 01458 #define BITP_AFE_WGPHASE_SINEOFFSET 0 /* Sinusoid Phase Offset */ 01459 #define BITM_AFE_WGPHASE_SINEOFFSET 0x000FFFFF /* Sinusoid Phase Offset */ 01460 01461 /* ------------------------------------------------------------------------------------------------------------------------- 01462 AFE_WGOFFSET Pos/Masks Description 01463 ------------------------------------------------------------------------------------------------------------------------- */ 01464 #define BITP_AFE_WGOFFSET_SINEOFFSET 0 /* Sinusoid Offset */ 01465 #define BITM_AFE_WGOFFSET_SINEOFFSET 0x00000FFF /* Sinusoid Offset */ 01466 01467 /* ------------------------------------------------------------------------------------------------------------------------- 01468 AFE_WGAMPLITUDE Pos/Masks Description 01469 ------------------------------------------------------------------------------------------------------------------------- */ 01470 #define BITP_AFE_WGAMPLITUDE_SINEAMPLITUDE 0 /* Sinusoid Amplitude */ 01471 #define BITM_AFE_WGAMPLITUDE_SINEAMPLITUDE 0x000007FF /* Sinusoid Amplitude */ 01472 01473 /* ------------------------------------------------------------------------------------------------------------------------- 01474 AFE_ADCFILTERCON Pos/Masks Description 01475 ------------------------------------------------------------------------------------------------------------------------- */ 01476 #define BITP_AFE_ADCFILTERCON_AVRGNUM 14 /* Number of Samples Averaged */ 01477 #define BITP_AFE_ADCFILTERCON_SINC3OSR 12 /* SINC3 OSR */ 01478 #define BITP_AFE_ADCFILTERCON_SINC2OSR 8 /* SINC2 OSR */ 01479 #define BITP_AFE_ADCFILTERCON_AVRGEN 7 /* Average Function Enable */ 01480 #define BITP_AFE_ADCFILTERCON_SINC3BYP 6 /* SINC3 Filter Bypass */ 01481 #define BITP_AFE_ADCFILTERCON_LPFBYPEN 4 /* 50/60Hz Low Pass Filter */ 01482 #define BITP_AFE_ADCFILTERCON_ADCCLK 0 /* ADC Data Rate */ 01483 #define BITM_AFE_ADCFILTERCON_AVRGNUM 0x0000C000 /* Number of Samples Averaged */ 01484 #define BITM_AFE_ADCFILTERCON_SINC3OSR 0x00003000 /* SINC3 OSR */ 01485 #define BITM_AFE_ADCFILTERCON_SINC2OSR 0x00000F00 /* SINC2 OSR */ 01486 #define BITM_AFE_ADCFILTERCON_AVRGEN 0x00000080 /* Average Function Enable */ 01487 #define BITM_AFE_ADCFILTERCON_SINC3BYP 0x00000040 /* SINC3 Filter Bypass */ 01488 #define BITM_AFE_ADCFILTERCON_LPFBYPEN 0x00000010 /* 50/60Hz Low Pass Filter */ 01489 #define BITM_AFE_ADCFILTERCON_ADCCLK 0x00000001 /* ADC Data Rate */ 01490 01491 /* ------------------------------------------------------------------------------------------------------------------------- 01492 AFE_HSDACDAT Pos/Masks Description 01493 ------------------------------------------------------------------------------------------------------------------------- */ 01494 #define BITP_AFE_HSDACDAT_DACDAT 0 /* DAC Code */ 01495 #define BITM_AFE_HSDACDAT_DACDAT 0x00000FFF /* DAC Code */ 01496 01497 /* ------------------------------------------------------------------------------------------------------------------------- 01498 AFE_LPREFBUFCON Pos/Masks Description 01499 ------------------------------------------------------------------------------------------------------------------------- */ 01500 #define BITP_AFE_LPREFBUFCON_BOOSTCURRENT 2 /* Set: Drive 2 Dac ;Unset Drive 1 Dac, and Save Power */ 01501 #define BITP_AFE_LPREFBUFCON_LPBUF2P5DIS 1 /* Low Power Bandgap's Output Buffer */ 01502 #define BITP_AFE_LPREFBUFCON_LPREFDIS 0 /* Set This Bit Will Power Down Low Power Bandgap */ 01503 #define BITM_AFE_LPREFBUFCON_BOOSTCURRENT 0x00000004 /* Set: Drive 2 Dac ;Unset Drive 1 Dac, and Save Power */ 01504 #define BITM_AFE_LPREFBUFCON_LPBUF2P5DIS 0x00000002 /* Low Power Bandgap's Output Buffer */ 01505 #define BITM_AFE_LPREFBUFCON_LPREFDIS 0x00000001 /* Set This Bit Will Power Down Low Power Bandgap */ 01506 01507 /* ------------------------------------------------------------------------------------------------------------------------- 01508 AFE_SYNCEXTDEVICE Pos/Masks Description 01509 ------------------------------------------------------------------------------------------------------------------------- */ 01510 #define BITP_AFE_SYNCEXTDEVICE_SYNC 0 /* As Output Data of GPIO */ 01511 #define BITM_AFE_SYNCEXTDEVICE_SYNC 0x000000FF /* As Output Data of GPIO */ 01512 01513 /* ------------------------------------------------------------------------------------------------------------------------- 01514 AFE_SEQCRC Pos/Masks Description 01515 ------------------------------------------------------------------------------------------------------------------------- */ 01516 #define BITP_AFE_SEQCRC_CRC 0 /* Sequencer Command CRC Value. */ 01517 #define BITM_AFE_SEQCRC_CRC 0x000000FF /* Sequencer Command CRC Value. */ 01518 01519 /* ------------------------------------------------------------------------------------------------------------------------- 01520 AFE_SEQCNT Pos/Masks Description 01521 ------------------------------------------------------------------------------------------------------------------------- */ 01522 #define BITP_AFE_SEQCNT_COUNT 0 /* Sequencer Command Count */ 01523 #define BITM_AFE_SEQCNT_COUNT 0x0000FFFF /* Sequencer Command Count */ 01524 01525 /* ------------------------------------------------------------------------------------------------------------------------- 01526 AFE_SEQTIMEOUT Pos/Masks Description 01527 ------------------------------------------------------------------------------------------------------------------------- */ 01528 #define BITP_AFE_SEQTIMEOUT_TIMEOUT 0 /* Current Value of the Sequencer Timeout Counter. */ 01529 #define BITM_AFE_SEQTIMEOUT_TIMEOUT 0x3FFFFFFF /* Current Value of the Sequencer Timeout Counter. */ 01530 01531 /* ------------------------------------------------------------------------------------------------------------------------- 01532 AFE_DATAFIFORD Pos/Masks Description 01533 ------------------------------------------------------------------------------------------------------------------------- */ 01534 #define BITP_AFE_DATAFIFORD_DATAFIFOOUT 0 /* Data FIFO Read */ 01535 #define BITM_AFE_DATAFIFORD_DATAFIFOOUT 0x0000FFFF /* Data FIFO Read */ 01536 01537 /* ------------------------------------------------------------------------------------------------------------------------- 01538 AFE_CMDFIFOWRITE Pos/Masks Description 01539 ------------------------------------------------------------------------------------------------------------------------- */ 01540 #define BITP_AFE_CMDFIFOWRITE_CMDFIFOIN 0 /* Command FIFO Write. */ 01541 #define BITM_AFE_CMDFIFOWRITE_CMDFIFOIN 0xFFFFFFFF /* Command FIFO Write. */ 01542 01543 /* ------------------------------------------------------------------------------------------------------------------------- 01544 AFE_ADCDAT Pos/Masks Description 01545 ------------------------------------------------------------------------------------------------------------------------- */ 01546 #define BITP_AFE_ADCDAT_DATA 0 /* ADC Result */ 01547 #define BITM_AFE_ADCDAT_DATA 0x0000FFFF /* ADC Result */ 01548 01549 /* ------------------------------------------------------------------------------------------------------------------------- 01550 AFE_DFTREAL Pos/Masks Description 01551 ------------------------------------------------------------------------------------------------------------------------- */ 01552 #define BITP_AFE_DFTREAL_DATA 0 /* DFT Real */ 01553 #define BITM_AFE_DFTREAL_DATA 0x0003FFFF /* DFT Real */ 01554 01555 /* ------------------------------------------------------------------------------------------------------------------------- 01556 AFE_DFTIMAG Pos/Masks Description 01557 ------------------------------------------------------------------------------------------------------------------------- */ 01558 #define BITP_AFE_DFTIMAG_DATA 0 /* DFT Imaginary */ 01559 #define BITM_AFE_DFTIMAG_DATA 0x0003FFFF /* DFT Imaginary */ 01560 01561 /* ------------------------------------------------------------------------------------------------------------------------- 01562 AFE_SINC2DAT Pos/Masks Description 01563 ------------------------------------------------------------------------------------------------------------------------- */ 01564 #define BITP_AFE_SINC2DAT_DATA 0 /* LPF Result */ 01565 #define BITM_AFE_SINC2DAT_DATA 0x0000FFFF /* LPF Result */ 01566 01567 /* ------------------------------------------------------------------------------------------------------------------------- 01568 AFE_TEMPSENSDAT Pos/Masks Description 01569 ------------------------------------------------------------------------------------------------------------------------- */ 01570 #define BITP_AFE_TEMPSENSDAT_DATA 0 /* Temp Sensor */ 01571 #define BITM_AFE_TEMPSENSDAT_DATA 0x0000FFFF /* Temp Sensor */ 01572 01573 /* ------------------------------------------------------------------------------------------------------------------------- 01574 AFE_AFEGENINTSTA Pos/Masks Description 01575 ------------------------------------------------------------------------------------------------------------------------- */ 01576 #define BITP_AFE_AFEGENINTSTA_CUSTOMIRQ3 3 /* Custom IRQ 3. */ 01577 #define BITP_AFE_AFEGENINTSTA_CUSTOMIRQ2 2 /* Custom IRQ 2 */ 01578 #define BITP_AFE_AFEGENINTSTA_CUSTOMIRQ1 1 /* Custom IRQ 1. */ 01579 #define BITP_AFE_AFEGENINTSTA_CUSTOMIRQ0 0 /* Custom IRQ 0 */ 01580 #define BITM_AFE_AFEGENINTSTA_CUSTOMIRQ3 0x00000008 /* Custom IRQ 3. */ 01581 #define BITM_AFE_AFEGENINTSTA_CUSTOMIRQ2 0x00000004 /* Custom IRQ 2 */ 01582 #define BITM_AFE_AFEGENINTSTA_CUSTOMIRQ1 0x00000002 /* Custom IRQ 1. */ 01583 #define BITM_AFE_AFEGENINTSTA_CUSTOMIRQ0 0x00000001 /* Custom IRQ 0 */ 01584 01585 /* ------------------------------------------------------------------------------------------------------------------------- 01586 AFE_ADCMIN Pos/Masks Description 01587 ------------------------------------------------------------------------------------------------------------------------- */ 01588 #define BITP_AFE_ADCMIN_MINVAL 0 /* ADC Minimum Value Threshold */ 01589 #define BITM_AFE_ADCMIN_MINVAL 0x0000FFFF /* ADC Minimum Value Threshold */ 01590 01591 /* ------------------------------------------------------------------------------------------------------------------------- 01592 AFE_ADCMINSM Pos/Masks Description 01593 ------------------------------------------------------------------------------------------------------------------------- */ 01594 #define BITP_AFE_ADCMINSM_MINCLRVAL 0 /* ADCMIN Hysteresis Value */ 01595 #define BITM_AFE_ADCMINSM_MINCLRVAL 0x0000FFFF /* ADCMIN Hysteresis Value */ 01596 01597 /* ------------------------------------------------------------------------------------------------------------------------- 01598 AFE_ADCMAX Pos/Masks Description 01599 ------------------------------------------------------------------------------------------------------------------------- */ 01600 #define BITP_AFE_ADCMAX_MAXVAL 0 /* ADC Max Threshold */ 01601 #define BITM_AFE_ADCMAX_MAXVAL 0x0000FFFF /* ADC Max Threshold */ 01602 01603 /* ------------------------------------------------------------------------------------------------------------------------- 01604 AFE_ADCMAXSMEN Pos/Masks Description 01605 ------------------------------------------------------------------------------------------------------------------------- */ 01606 #define BITP_AFE_ADCMAXSMEN_MAXSWEN 0 /* ADCMAX Hysteresis Value */ 01607 #define BITM_AFE_ADCMAXSMEN_MAXSWEN 0x0000FFFF /* ADCMAX Hysteresis Value */ 01608 01609 /* ------------------------------------------------------------------------------------------------------------------------- 01610 AFE_ADCDELTA Pos/Masks Description 01611 ------------------------------------------------------------------------------------------------------------------------- */ 01612 #define BITP_AFE_ADCDELTA_DELTAVAL 0 /* ADCDAT Code Differences Limit Option */ 01613 #define BITM_AFE_ADCDELTA_DELTAVAL 0x0000FFFF /* ADCDAT Code Differences Limit Option */ 01614 01615 /* ------------------------------------------------------------------------------------------------------------------------- 01616 AFE_HPOSCCON Pos/Masks Description 01617 ------------------------------------------------------------------------------------------------------------------------- */ 01618 #define BITP_AFE_HPOSCCON_CLK32MHZEN 2 /* 16M/32M Output Selector Signal. */ 01619 #define BITM_AFE_HPOSCCON_CLK32MHZEN 0x00000004 /* 16M/32M Output Selector Signal. */ 01620 01621 /* ------------------------------------------------------------------------------------------------------------------------- 01622 AFE_DFTCON Pos/Masks Description 01623 ------------------------------------------------------------------------------------------------------------------------- */ 01624 #define BITP_AFE_DFTCON_DFTINSEL 20 /* DFT Input Select */ 01625 #define BITP_AFE_DFTCON_DFTNUM 4 /* ADC Samples Used */ 01626 #define BITP_AFE_DFTCON_HANNINGEN 0 /* Hanning Window Enable */ 01627 #define BITM_AFE_DFTCON_DFTINSEL 0x00300000 /* DFT Input Select */ 01628 #define BITM_AFE_DFTCON_DFTNUM 0x000000F0 /* ADC Samples Used */ 01629 #define BITM_AFE_DFTCON_HANNINGEN 0x00000001 /* Hanning Window Enable */ 01630 01631 /* ------------------------------------------------------------------------------------------------------------------------- 01632 AFE_LPTIASW1 Pos/Masks Description 01633 ------------------------------------------------------------------------------------------------------------------------- */ 01634 #define BITP_AFE_LPTIASW1_TIABIASSEL 13 /* TIA SW13 Control. Active High */ 01635 #define BITP_AFE_LPTIASW1_PABIASSEL 12 /* TIA SW12 Control. Active High */ 01636 #define BITP_AFE_LPTIASW1_TIASWCON 0 /* TIA SW[11:0] Control */ 01637 #define BITM_AFE_LPTIASW1_TIABIASSEL (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* TIA SW13 Control. Active High */ 01638 #define BITM_AFE_LPTIASW1_PABIASSEL (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t )) /* TIA SW12 Control. Active High */ 01639 #define BITM_AFE_LPTIASW1_TIASWCON (_ADI_MSK_3(0x00000FFF,0x00000FFFUL, uint32_t )) /* TIA SW[11:0] Control */ 01640 #define ENUM_AFE_LPTIASW1_CAPA_LP (_ADI_MSK_3(0x00000014,0x00000014UL, uint32_t )) /* TIASWCON: CAPA test with LP TIA */ 01641 #define ENUM_AFE_LPTIASW1_NORM (_ADI_MSK_3(0x0000002C,0x0000002CUL, uint32_t )) /* TIASWCON: Normal work mode */ 01642 #define ENUM_AFE_LPTIASW1_DIO (_ADI_MSK_3(0x0000002D,0x0000002DUL, uint32_t )) /* TIASWCON: Normal work mode with back-back diode enabled. */ 01643 #define ENUM_AFE_LPTIASW1_SHORTSW (_ADI_MSK_3(0x0000002E,0x0000002EUL, uint32_t )) /* TIASWCON: Work mode with short switch protection */ 01644 #define ENUM_AFE_LPTIASW1_LOWNOISE (_ADI_MSK_3(0x0000006C,0x0000006CUL, uint32_t )) /* TIASWCON: Work mode, vzero-vbias=0. */ 01645 #define ENUM_AFE_LPTIASW1_CAPA_RAMP_H (_ADI_MSK_3(0x00000094,0x00000094UL, uint32_t )) /* TIASWCON: CAPA test or Ramp test with HP TIA */ 01646 #define ENUM_AFE_LPTIASW1_BUFDIS (_ADI_MSK_3(0x00000180,0x00000180UL, uint32_t )) /* TIASWCON: Set PA/TIA as unity gain buffer. */ 01647 #define ENUM_AFE_LPTIASW1_BUFEN (_ADI_MSK_3(0x000001A4,0x000001A4UL, uint32_t )) /* TIASWCON: Set PA/TIA as unity gain buffer. Connect amp's output to CE1 & RC11. */ 01648 #define ENUM_AFE_LPTIASW1_TWOLEAD (_ADI_MSK_3(0x0000042C,0x0000042CUL, uint32_t )) /* TIASWCON: Two lead sensor, set PA as unity gain buffer. */ 01649 #define ENUM_AFE_LPTIASW1_BUFEN2 (_ADI_MSK_3(0x000004A4,0x000004A4UL, uint32_t )) /* TIASWCON: Set PA/TIA as unity gain buffer. */ 01650 #define ENUM_AFE_LPTIASW1_SESHORTRE (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* TIASWCON: Close SW11 - Short SE1 to RE1, */ 01651 01652 /* ------------------------------------------------------------------------------------------------------------------------- 01653 AFE_LPTIASW0 Pos/Masks Description 01654 ------------------------------------------------------------------------------------------------------------------------- */ 01655 #define BITP_AFE_LPTIASW0_RECAL 15 /* TIA SW15 Control. Active High */ 01656 #define BITP_AFE_LPTIASW0_VZEROSHARE 14 /* TIA SW14 Control. Active High */ 01657 #define BITP_AFE_LPTIASW0_TIABIASSEL 13 /* TIA SW13 Control. Active High */ 01658 #define BITP_AFE_LPTIASW0_PABIASSEL 12 /* TIA SW12 Control. Active High */ 01659 #define BITP_AFE_LPTIASW0_TIASWCON 0 /* TIA SW[11:0] Control */ 01660 #define BITM_AFE_LPTIASW0_RECAL 0x00008000 /* TIA SW15 Control. Active High */ 01661 #define BITM_AFE_LPTIASW0_VZEROSHARE 0x00004000 /* TIA SW14 Control. Active High */ 01662 #define BITM_AFE_LPTIASW0_TIABIASSEL 0x00002000 /* TIA SW13 Control. Active High */ 01663 #define BITM_AFE_LPTIASW0_PABIASSEL 0x00001000 /* TIA SW12 Control. Active High */ 01664 #define BITM_AFE_LPTIASW0_TIASWCON 0x00000FFF /* TIA SW[11:0] Control */ 01665 #define ENUM_AFE_LPTIASW0_11 0x00000014 /* TIASWCON: CAPA test with LP TIA */ 01666 #define ENUM_AFE_LPTIASW0_NORM 0x0000002C /* TIASWCON: Normal work mode */ 01667 #define ENUM_AFE_LPTIASW0_DIO 0x0000002D /* TIASWCON: Normal work mode with back-back diode enabled. */ 01668 #define ENUM_AFE_LPTIASW0_SHORTSW 0x0000002E /* TIASWCON: Work mode with short switch protection */ 01669 #define ENUM_AFE_LPTIASW0_LOWNOISE 0x0000006C /* TIASWCON: Work mode, vzero-vbias=0. */ 01670 #define ENUM_AFE_LPTIASW0_1 0x00000094 /* TIASWCON: CAPA test or Ramp test with HP TIA */ 01671 #define ENUM_AFE_LPTIASW0_BUFDIS 0x00000180 /* TIASWCON: Set PA/TIA as unity gain buffer. */ 01672 #define ENUM_AFE_LPTIASW0_BUFEN 0x000001A4 /* TIASWCON: Set PA/TIA as unity gain buffer. Connect amp's output to CE0 & RC01. */ 01673 #define ENUM_AFE_LPTIASW0_TWOLEAD 0x0000042C /* TIASWCON: Two lead sensor, set PA as unity gain buffer. */ 01674 #define ENUM_AFE_LPTIASW0_BUFEN2 0x000004A4 /* TIASWCON: Set PA/TIA as unity gain buffer. */ 01675 #define ENUM_AFE_LPTIASW0_SESHORTRE 0x00000800 /* TIASWCON: Close SW11 - Short SE0 to RE0. */ 01676 01677 /* ------------------------------------------------------------------------------------------------------------------------- 01678 AFE_LPTIACON1 Pos/Masks Description 01679 ------------------------------------------------------------------------------------------------------------------------- */ 01680 #define BITP_AFE_LPTIACON1_CHOPEN 16 /* Chopping Enable */ 01681 #define BITP_AFE_LPTIACON1_TIARF 13 /* Set LPF Resistor */ 01682 #define BITP_AFE_LPTIACON1_TIARL 10 /* Set RLOAD */ 01683 #define BITP_AFE_LPTIACON1_TIAGAIN 5 /* Set RTIA Gain Resistor */ 01684 #define BITP_AFE_LPTIACON1_IBOOST 3 /* Current Boost Control */ 01685 #define BITP_AFE_LPTIACON1_HALFPWR 2 /* Half Power Mode Select */ 01686 #define BITP_AFE_LPTIACON1_PAPDEN 1 /* PA Power Down */ 01687 #define BITP_AFE_LPTIACON1_TIAPDEN 0 /* TIA Power Down */ 01688 #define BITM_AFE_LPTIACON1_CHOPEN (_ADI_MSK_3(0x00030000,0x00030000UL, uint32_t )) /* Chopping Enable */ 01689 #define BITM_AFE_LPTIACON1_TIARF (_ADI_MSK_3(0x0000E000,0x0000E000UL, uint32_t )) /* Set LPF Resistor */ 01690 #define BITM_AFE_LPTIACON1_TIARL (_ADI_MSK_3(0x00001C00,0x00001C00UL, uint32_t )) /* Set RLOAD */ 01691 #define BITM_AFE_LPTIACON1_TIAGAIN (_ADI_MSK_3(0x000003E0,0x000003E0UL, uint32_t )) /* Set RTIA Gain Resistor */ 01692 #define BITM_AFE_LPTIACON1_IBOOST (_ADI_MSK_3(0x00000018,0x00000018UL, uint32_t )) /* Current Boost Control */ 01693 #define BITM_AFE_LPTIACON1_HALFPWR (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* Half Power Mode Select */ 01694 #define BITM_AFE_LPTIACON1_PAPDEN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* PA Power Down */ 01695 #define BITM_AFE_LPTIACON1_TIAPDEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* TIA Power Down */ 01696 #define ENUM_AFE_LPTIACON1_DISCONRF (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* TIARF: Disconnect TIA output from LPF pin */ 01697 #define ENUM_AFE_LPTIACON1_BYPRF (_ADI_MSK_3(0x00002000,0x00002000UL, uint32_t )) /* TIARF: Bypass resistor */ 01698 #define ENUM_AFE_LPTIACON1_RF20K (_ADI_MSK_3(0x00004000,0x00004000UL, uint32_t )) /* TIARF: 20k Ohm */ 01699 #define ENUM_AFE_LPTIACON1_RF100K (_ADI_MSK_3(0x00006000,0x00006000UL, uint32_t )) /* TIARF: 100k Ohm */ 01700 #define ENUM_AFE_LPTIACON1_RF200K (_ADI_MSK_3(0x00008000,0x00008000UL, uint32_t )) /* TIARF: 200k Ohm */ 01701 #define ENUM_AFE_LPTIACON1_RF400K (_ADI_MSK_3(0x0000A000,0x0000A000UL, uint32_t )) /* TIARF: 400k Ohm */ 01702 #define ENUM_AFE_LPTIACON1_RF600K (_ADI_MSK_3(0x0000C000,0x0000C000UL, uint32_t )) /* TIARF: 600k Ohm */ 01703 #define ENUM_AFE_LPTIACON1_RF1MOHM (_ADI_MSK_3(0x0000E000,0x0000E000UL, uint32_t )) /* TIARF: 1Meg Ohm */ 01704 #define ENUM_AFE_LPTIACON1_RL0 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* TIARL: 0 ohm */ 01705 #define ENUM_AFE_LPTIACON1_RL10 (_ADI_MSK_3(0x00000400,0x00000400UL, uint32_t )) /* TIARL: 10 ohm */ 01706 #define ENUM_AFE_LPTIACON1_RL30 (_ADI_MSK_3(0x00000800,0x00000800UL, uint32_t )) /* TIARL: 30 ohm */ 01707 #define ENUM_AFE_LPTIACON1_RL50 (_ADI_MSK_3(0x00000C00,0x00000C00UL, uint32_t )) /* TIARL: 50 ohm */ 01708 #define ENUM_AFE_LPTIACON1_RL100 (_ADI_MSK_3(0x00001000,0x00001000UL, uint32_t )) /* TIARL: 100 ohm */ 01709 #define ENUM_AFE_LPTIACON1_RL1P6K (_ADI_MSK_3(0x00001400,0x00001400UL, uint32_t )) /* TIARL: 1.6kohm */ 01710 #define ENUM_AFE_LPTIACON1_RL3P1K (_ADI_MSK_3(0x00001800,0x00001800UL, uint32_t )) /* TIARL: 3.1kohm */ 01711 #define ENUM_AFE_LPTIACON1_RL3P5K (_ADI_MSK_3(0x00001C00,0x00001C00UL, uint32_t )) /* TIARL: 3.6kohm */ 01712 #define ENUM_AFE_LPTIACON1_DISCONTIA (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* TIAGAIN: Disconnect TIA Gain resistor */ 01713 #define ENUM_AFE_LPTIACON1_TIAGAIN200 (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* TIAGAIN: 200 Ohm */ 01714 #define ENUM_AFE_LPTIACON1_TIAGAIN1K (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* TIAGAIN: 1k ohm */ 01715 #define ENUM_AFE_LPTIACON1_TIAGAIN2K (_ADI_MSK_3(0x00000060,0x00000060UL, uint32_t )) /* TIAGAIN: 2k */ 01716 #define ENUM_AFE_LPTIACON1_TIAGAIN3K (_ADI_MSK_3(0x00000080,0x00000080UL, uint32_t )) /* TIAGAIN: 3k */ 01717 #define ENUM_AFE_LPTIACON1_TIAGAIN4K (_ADI_MSK_3(0x000000A0,0x000000A0UL, uint32_t )) /* TIAGAIN: 4k */ 01718 #define ENUM_AFE_LPTIACON1_TIAGAIN6K (_ADI_MSK_3(0x000000C0,0x000000C0UL, uint32_t )) /* TIAGAIN: 6k */ 01719 #define ENUM_AFE_LPTIACON1_TIAGAIN8K (_ADI_MSK_3(0x000000E0,0x000000E0UL, uint32_t )) /* TIAGAIN: 8k */ 01720 #define ENUM_AFE_LPTIACON1_TIAGAIN10K (_ADI_MSK_3(0x00000100,0x00000100UL, uint32_t )) /* TIAGAIN: 10k */ 01721 #define ENUM_AFE_LPTIACON1_TIAGAIN12K (_ADI_MSK_3(0x00000120,0x00000120UL, uint32_t )) /* TIAGAIN: 12k */ 01722 #define ENUM_AFE_LPTIACON1_TIAGAIN16K (_ADI_MSK_3(0x00000140,0x00000140UL, uint32_t )) /* TIAGAIN: 16k */ 01723 #define ENUM_AFE_LPTIACON1_TIAGAIN20K (_ADI_MSK_3(0x00000160,0x00000160UL, uint32_t )) /* TIAGAIN: 20k */ 01724 #define ENUM_AFE_LPTIACON1_TIAGAIN24K (_ADI_MSK_3(0x00000180,0x00000180UL, uint32_t )) /* TIAGAIN: 24k */ 01725 #define ENUM_AFE_LPTIACON1_TIAGAIN30K (_ADI_MSK_3(0x000001A0,0x000001A0UL, uint32_t )) /* TIAGAIN: 30k */ 01726 #define ENUM_AFE_LPTIACON1_TIAGAIN32K (_ADI_MSK_3(0x000001C0,0x000001C0UL, uint32_t )) /* TIAGAIN: 32k */ 01727 #define ENUM_AFE_LPTIACON1_TIAGAIN40K (_ADI_MSK_3(0x000001E0,0x000001E0UL, uint32_t )) /* TIAGAIN: 40k */ 01728 #define ENUM_AFE_LPTIACON1_TIAGAIN48K (_ADI_MSK_3(0x00000200,0x00000200UL, uint32_t )) /* TIAGAIN: 48k */ 01729 #define ENUM_AFE_LPTIACON1_TIAGAIN64K (_ADI_MSK_3(0x00000220,0x00000220UL, uint32_t )) /* TIAGAIN: 64k */ 01730 #define ENUM_AFE_LPTIACON1_TIAGAIN85K (_ADI_MSK_3(0x00000240,0x00000240UL, uint32_t )) /* TIAGAIN: 85k */ 01731 #define ENUM_AFE_LPTIACON1_TIAGAIN96K (_ADI_MSK_3(0x00000260,0x00000260UL, uint32_t )) /* TIAGAIN: 96k */ 01732 #define ENUM_AFE_LPTIACON1_TIAGAIN100K (_ADI_MSK_3(0x00000280,0x00000280UL, uint32_t )) /* TIAGAIN: 100k */ 01733 #define ENUM_AFE_LPTIACON1_TIAGAIN120K (_ADI_MSK_3(0x000002A0,0x000002A0UL, uint32_t )) /* TIAGAIN: 120k */ 01734 #define ENUM_AFE_LPTIACON1_TIAGAIN128K (_ADI_MSK_3(0x000002C0,0x000002C0UL, uint32_t )) /* TIAGAIN: 128k */ 01735 #define ENUM_AFE_LPTIACON1_TIAGAIN160K (_ADI_MSK_3(0x000002E0,0x000002E0UL, uint32_t )) /* TIAGAIN: 160k */ 01736 #define ENUM_AFE_LPTIACON1_TIAGAIN196K (_ADI_MSK_3(0x00000300,0x00000300UL, uint32_t )) /* TIAGAIN: 196k */ 01737 #define ENUM_AFE_LPTIACON1_TIAGAIN256K (_ADI_MSK_3(0x00000320,0x00000320UL, uint32_t )) /* TIAGAIN: 256k */ 01738 #define ENUM_AFE_LPTIACON1_TIAGAIN512K (_ADI_MSK_3(0x00000340,0x00000340UL, uint32_t )) /* TIAGAIN: 512k */ 01739 01740 /* ------------------------------------------------------------------------------------------------------------------------- 01741 AFE_LPTIACON0 Pos/Masks Description 01742 ------------------------------------------------------------------------------------------------------------------------- */ 01743 #define BITP_AFE_LPTIACON0_CHOPEN 16 /* Chopping Enable */ 01744 #define BITP_AFE_LPTIACON0_TIARF 13 /* Set LPF Resistor */ 01745 #define BITP_AFE_LPTIACON0_TIARL 10 /* Set RLOAD */ 01746 #define BITP_AFE_LPTIACON0_TIAGAIN 5 /* Set RTIA */ 01747 #define BITP_AFE_LPTIACON0_IBOOST 3 /* Current Boost Control */ 01748 #define BITP_AFE_LPTIACON0_HALFPWR 2 /* Half Power Mode Select */ 01749 #define BITP_AFE_LPTIACON0_PAPDEN 1 /* PA Power Down */ 01750 #define BITP_AFE_LPTIACON0_TIAPDEN 0 /* TIA Power Down */ 01751 #define BITM_AFE_LPTIACON0_CHOPEN 0x00030000 /* Chopping Enable */ 01752 #define BITM_AFE_LPTIACON0_TIARF 0x0000E000 /* Set LPF Resistor */ 01753 #define BITM_AFE_LPTIACON0_TIARL 0x00001C00 /* Set RLOAD */ 01754 #define BITM_AFE_LPTIACON0_TIAGAIN 0x000003E0 /* Set RTIA */ 01755 #define BITM_AFE_LPTIACON0_IBOOST 0x00000018 /* Current Boost Control */ 01756 #define BITM_AFE_LPTIACON0_HALFPWR 0x00000004 /* Half Power Mode Select */ 01757 #define BITM_AFE_LPTIACON0_PAPDEN 0x00000002 /* PA Power Down */ 01758 #define BITM_AFE_LPTIACON0_TIAPDEN 0x00000001 /* TIA Power Down */ 01759 #define ENUM_AFE_LPTIACON0_DISCONRF 0x00000000 /* TIARF: Disconnect TIA output from LPF pin */ 01760 #define ENUM_AFE_LPTIACON0_BYPRF 0x00002000 /* TIARF: Bypass resistor */ 01761 #define ENUM_AFE_LPTIACON0_RF20K 0x00004000 /* TIARF: 20k Ohm */ 01762 #define ENUM_AFE_LPTIACON0_RF100K 0x00006000 /* TIARF: 100k Ohm */ 01763 #define ENUM_AFE_LPTIACON0_RF200K 0x00008000 /* TIARF: 200k Ohm */ 01764 #define ENUM_AFE_LPTIACON0_RF400K 0x0000A000 /* TIARF: 400k Ohm */ 01765 #define ENUM_AFE_LPTIACON0_RF600K 0x0000C000 /* TIARF: 600k Ohm */ 01766 #define ENUM_AFE_LPTIACON0_RF1MOHM 0x0000E000 /* TIARF: 1Meg Ohm */ 01767 #define ENUM_AFE_LPTIACON0_RL0 0x00000000 /* TIARL: 0 ohm */ 01768 #define ENUM_AFE_LPTIACON0_RL10 0x00000400 /* TIARL: 10 ohm */ 01769 #define ENUM_AFE_LPTIACON0_RL30 0x00000800 /* TIARL: 30 ohm */ 01770 #define ENUM_AFE_LPTIACON0_RL50 0x00000C00 /* TIARL: 50 ohm */ 01771 #define ENUM_AFE_LPTIACON0_RL100 0x00001000 /* TIARL: 100 ohm */ 01772 #define ENUM_AFE_LPTIACON0_RL1P6K 0x00001400 /* TIARL: 1.6kohm */ 01773 #define ENUM_AFE_LPTIACON0_RL3P1K 0x00001800 /* TIARL: 3.1kohm */ 01774 #define ENUM_AFE_LPTIACON0_RL3P5K 0x00001C00 /* TIARL: 3.6kohm */ 01775 #define ENUM_AFE_LPTIACON0_DISCONTIA 0x00000000 /* TIAGAIN: Disconnect TIA Gain resistor */ 01776 #define ENUM_AFE_LPTIACON0_TIAGAIN200 0x00000020 /* TIAGAIN: 200 Ohm */ 01777 #define ENUM_AFE_LPTIACON0_TIAGAIN1K 0x00000040 /* TIAGAIN: 1k ohm */ 01778 #define ENUM_AFE_LPTIACON0_TIAGAIN2K 0x00000060 /* TIAGAIN: 2k */ 01779 #define ENUM_AFE_LPTIACON0_TIAGAIN3K 0x00000080 /* TIAGAIN: 3k */ 01780 #define ENUM_AFE_LPTIACON0_TIAGAIN4K 0x000000A0 /* TIAGAIN: 4k */ 01781 #define ENUM_AFE_LPTIACON0_TIAGAIN6K 0x000000C0 /* TIAGAIN: 6k */ 01782 #define ENUM_AFE_LPTIACON0_TIAGAIN8K 0x000000E0 /* TIAGAIN: 8k */ 01783 #define ENUM_AFE_LPTIACON0_TIAGAIN10K 0x00000100 /* TIAGAIN: 10k */ 01784 #define ENUM_AFE_LPTIACON0_TIAGAIN12K 0x00000120 /* TIAGAIN: 12k */ 01785 #define ENUM_AFE_LPTIACON0_TIAGAIN16K 0x00000140 /* TIAGAIN: 16k */ 01786 #define ENUM_AFE_LPTIACON0_TIAGAIN20K 0x00000160 /* TIAGAIN: 20k */ 01787 #define ENUM_AFE_LPTIACON0_TIAGAIN24K 0x00000180 /* TIAGAIN: 24k */ 01788 #define ENUM_AFE_LPTIACON0_TIAGAIN30K 0x000001A0 /* TIAGAIN: 30k */ 01789 #define ENUM_AFE_LPTIACON0_TIAGAIN32K 0x000001C0 /* TIAGAIN: 32k */ 01790 #define ENUM_AFE_LPTIACON0_TIAGAIN40K 0x000001E0 /* TIAGAIN: 40k */ 01791 #define ENUM_AFE_LPTIACON0_TIAGAIN48K 0x00000200 /* TIAGAIN: 48k */ 01792 #define ENUM_AFE_LPTIACON0_TIAGAIN64K 0x00000220 /* TIAGAIN: 64k */ 01793 #define ENUM_AFE_LPTIACON0_TIAGAIN85K 0x00000240 /* TIAGAIN: 85k */ 01794 #define ENUM_AFE_LPTIACON0_TIAGAIN96K 0x00000260 /* TIAGAIN: 96k */ 01795 #define ENUM_AFE_LPTIACON0_TIAGAIN100K 0x00000280 /* TIAGAIN: 100k */ 01796 #define ENUM_AFE_LPTIACON0_TIAGAIN120K 0x000002A0 /* TIAGAIN: 120k */ 01797 #define ENUM_AFE_LPTIACON0_TIAGAIN128K 0x000002C0 /* TIAGAIN: 128k */ 01798 #define ENUM_AFE_LPTIACON0_TIAGAIN160K 0x000002E0 /* TIAGAIN: 160k */ 01799 #define ENUM_AFE_LPTIACON0_TIAGAIN196K 0x00000300 /* TIAGAIN: 196k */ 01800 #define ENUM_AFE_LPTIACON0_TIAGAIN256K 0x00000320 /* TIAGAIN: 256k */ 01801 #define ENUM_AFE_LPTIACON0_TIAGAIN512K 0x00000340 /* TIAGAIN: 512k */ 01802 01803 /* ------------------------------------------------------------------------------------------------------------------------- 01804 AFE_HSRTIACON Pos/Masks Description 01805 ------------------------------------------------------------------------------------------------------------------------- */ 01806 #define BITP_AFE_HSRTIACON_CTIACON 5 /* Configure Capacitor in Parallel with RTIA */ 01807 #define BITP_AFE_HSRTIACON_TIASW6CON 4 /* SW6 Control */ 01808 #define BITP_AFE_HSRTIACON_RTIACON 0 /* Configure General RTIA Value */ 01809 #define BITM_AFE_HSRTIACON_CTIACON 0x00001FE0 /* Configure Capacitor in Parallel with RTIA */ 01810 #define BITM_AFE_HSRTIACON_TIASW6CON 0x00000010 /* SW6 Control */ 01811 #define BITM_AFE_HSRTIACON_RTIACON 0x0000000F /* Configure General RTIA Value */ 01812 01813 /* ------------------------------------------------------------------------------------------------------------------------- 01814 AFE_DE1RESCON Pos/Masks Description 01815 ------------------------------------------------------------------------------------------------------------------------- */ 01816 #define BITP_AFE_DE1RESCON_DE1RCON 0 /* DE1 RLOAD RTIA Setting */ 01817 #define BITM_AFE_DE1RESCON_DE1RCON (_ADI_MSK_3(0x000000FF,0x000000FFUL, uint32_t )) /* DE1 RLOAD RTIA Setting */ 01818 01819 /* ------------------------------------------------------------------------------------------------------------------------- 01820 AFE_DE0RESCON Pos/Masks Description 01821 ------------------------------------------------------------------------------------------------------------------------- */ 01822 #define BITP_AFE_DE0RESCON_DE0RCON 0 /* DE0 RLOAD RTIA Setting */ 01823 #define BITM_AFE_DE0RESCON_DE0RCON 0x000000FF /* DE0 RLOAD RTIA Setting */ 01824 01825 /* ------------------------------------------------------------------------------------------------------------------------- 01826 AFE_HSTIACON Pos/Masks Description 01827 ------------------------------------------------------------------------------------------------------------------------- */ 01828 #define BITP_AFE_HSTIACON_VBIASSEL 0 /* Select HSTIA Positive Input */ 01829 #define BITM_AFE_HSTIACON_VBIASSEL 0x00000003 /* Select HSTIA Positive Input */ 01830 01831 /* ------------------------------------------------------------------------------------------------------------------------- 01832 AFE_DACDCBUFCON Pos/Masks Description 01833 ------------------------------------------------------------------------------------------------------------------------- */ 01834 #define BITP_AFE_DACDCBUFCON_CHANSEL 1 /* DAC DC Channel Selection */ 01835 #define BITP_AFE_DACDCBUFCON_RESERVED_0 0 /* Reserved */ 01836 #define BITM_AFE_DACDCBUFCON_CHANSEL (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* DAC DC Channel Selection */ 01837 #define BITM_AFE_DACDCBUFCON_RESERVED_0 (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Reserved */ 01838 #define ENUM_AFE_DACDCBUFCON_CHAN0 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* CHANSEL: ULPDAC0 Sets DC level */ 01839 #define ENUM_AFE_DACDCBUFCON_CHAN1 (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* CHANSEL: ULPDAC1 Sets DC level */ 01840 01841 /* ------------------------------------------------------------------------------------------------------------------------- 01842 AFE_LPMODEKEY Pos/Masks Description 01843 ------------------------------------------------------------------------------------------------------------------------- */ 01844 #define BITP_AFE_LPMODEKEY_KEY 0 /* LP Key */ 01845 #define BITM_AFE_LPMODEKEY_KEY 0x000FFFFF /* LP Key */ 01846 01847 /* ------------------------------------------------------------------------------------------------------------------------- 01848 AFE_LPMODECLKSEL Pos/Masks Description 01849 ------------------------------------------------------------------------------------------------------------------------- */ 01850 #define BITP_AFE_LPMODECLKSEL_LFSYSCLKEN 0 /* Enable Switching System Clock to 32KHz by Sequencer */ 01851 #define BITM_AFE_LPMODECLKSEL_LFSYSCLKEN 0x00000001 /* Enable Switching System Clock to 32KHz by Sequencer */ 01852 01853 /* ------------------------------------------------------------------------------------------------------------------------- 01854 AFE_LPMODECON Pos/Masks Description 01855 ------------------------------------------------------------------------------------------------------------------------- */ 01856 #define BITP_AFE_LPMODECON_ALDOEN 8 /* Set High to Power Down of Analog LDO */ 01857 #define BITP_AFE_LPMODECON_V1P1HPADCEN 7 /* Set High to Enable 1.1V HP CM Buffer */ 01858 #define BITP_AFE_LPMODECON_V1P8HPADCEN 6 /* Set High to Enable HP 1.8V Reference Buffer */ 01859 #define BITP_AFE_LPMODECON_PTATEN 5 /* Set to High to Generate Ptat Current Bias */ 01860 #define BITP_AFE_LPMODECON_ZTATEN 4 /* Set High to Generate Ztat Current Bias */ 01861 #define BITP_AFE_LPMODECON_REPEATADCCNVEN_P 3 /* Set High to Enable Repeat ADC Conversion */ 01862 #define BITP_AFE_LPMODECON_ADCCONVEN 2 /* Set High to Enable ADC Conversion */ 01863 #define BITP_AFE_LPMODECON_HPREFDIS 1 /* Set High to Power Down HP Reference */ 01864 #define BITP_AFE_LPMODECON_HFOSCPD 0 /* Set High to Power Down HP Power Oscillator */ 01865 #define BITM_AFE_LPMODECON_ALDOEN 0x00000100 /* Set High to Power Down of Analog LDO */ 01866 #define BITM_AFE_LPMODECON_V1P1HPADCEN 0x00000080 /* Set High to Enable 1.1V HP CM Buffer */ 01867 #define BITM_AFE_LPMODECON_V1P8HPADCEN 0x00000040 /* Set High to Enable HP 1.8V Reference Buffer */ 01868 #define BITM_AFE_LPMODECON_PTATEN 0x00000020 /* Set to High to Generate Ptat Current Bias */ 01869 #define BITM_AFE_LPMODECON_ZTATEN 0x00000010 /* Set High to Generate Ztat Current Bias */ 01870 #define BITM_AFE_LPMODECON_REPEATADCCNVEN_P 0x00000008 /* Set High to Enable Repeat ADC Conversion */ 01871 #define BITM_AFE_LPMODECON_ADCCONVEN 0x00000004 /* Set High to Enable ADC Conversion */ 01872 #define BITM_AFE_LPMODECON_HPREFDIS 0x00000002 /* Set High to Power Down HP Reference */ 01873 #define BITM_AFE_LPMODECON_HFOSCPD 0x00000001 /* Set High to Power Down HP Power Oscillator */ 01874 01875 /* ------------------------------------------------------------------------------------------------------------------------- 01876 AFE_SEQSLPLOCK Pos/Masks Description 01877 ------------------------------------------------------------------------------------------------------------------------- */ 01878 #define BITP_AFE_SEQSLPLOCK_SEQ_SLP_PW 0 /* Password for SLPBYSEQ Register */ 01879 #define BITM_AFE_SEQSLPLOCK_SEQ_SLP_PW 0x000FFFFF /* Password for SLPBYSEQ Register */ 01880 01881 /* ------------------------------------------------------------------------------------------------------------------------- 01882 AFE_SEQTRGSLP Pos/Masks Description 01883 ------------------------------------------------------------------------------------------------------------------------- */ 01884 #define BITP_AFE_SEQTRGSLP_TRGSLP 0 /* Trigger Sleep by Sequencer */ 01885 #define BITM_AFE_SEQTRGSLP_TRGSLP 0x00000001 /* Trigger Sleep by Sequencer */ 01886 01887 /* ------------------------------------------------------------------------------------------------------------------------- 01888 AFE_LPDACDAT0 Pos/Masks Description 01889 ------------------------------------------------------------------------------------------------------------------------- */ 01890 #define BITP_AFE_LPDACDAT0_DACIN6 12 /* 6BITVAL, 1LSB=34.375mV */ 01891 #define BITP_AFE_LPDACDAT0_DACIN12 0 /* 12BITVAL, 1LSB=537uV */ 01892 #define BITM_AFE_LPDACDAT0_DACIN6 0x0003F000 /* 6BITVAL, 1LSB=34.375mV */ 01893 #define BITM_AFE_LPDACDAT0_DACIN12 0x00000FFF /* 12BITVAL, 1LSB=537uV */ 01894 01895 /* ------------------------------------------------------------------------------------------------------------------------- 01896 AFE_LPDACSW0 Pos/Masks Description 01897 ------------------------------------------------------------------------------------------------------------------------- */ 01898 #define BITP_AFE_LPDACSW0_LPMODEDIS 5 /* Switch Control */ 01899 #define BITP_AFE_LPDACSW0_LPDACSW 0 /* LPDAC0 Switches Matrix */ 01900 #define BITM_AFE_LPDACSW0_LPMODEDIS 0x00000020 /* Switch Control */ 01901 #define BITM_AFE_LPDACSW0_LPDACSW 0x0000001F /* LPDAC0 Switches Matrix */ 01902 #define ENUM_AFE_LPDACSW0_DACCONBIT5 0x00000000 /* LPMODEDIS: REG_AFE_LPDACDAT0 Switch controlled by REG_AFE_LPDACDAT0CON0 bit 5 */ 01903 #define ENUM_AFE_LPDACSW0_OVRRIDE 0x00000020 /* LPMODEDIS: REG_AFE_LPDACDAT0 Switches override */ 01904 01905 /* ------------------------------------------------------------------------------------------------------------------------- 01906 AFE_LPDACCON0 Pos/Masks Description 01907 ------------------------------------------------------------------------------------------------------------------------- */ 01908 #define BITP_AFE_LPDACCON0_WAVETYPE 6 /* LPDAC Data Source */ 01909 #define BITP_AFE_LPDACCON0_DACMDE 5 /* LPDAC0 Switch Settings */ 01910 #define BITP_AFE_LPDACCON0_VZEROMUX 4 /* VZERO MUX Select */ 01911 #define BITP_AFE_LPDACCON0_VBIASMUX 3 /* VBIAS MUX Select */ 01912 #define BITP_AFE_LPDACCON0_REFSEL 2 /* Reference Select Bit */ 01913 #define BITP_AFE_LPDACCON0_PWDEN 1 /* LPDAC0 Power Down */ 01914 #define BITP_AFE_LPDACCON0_RSTEN 0 /* Enable Writes to REG_AFE_LPDACDAT00 */ 01915 #define BITM_AFE_LPDACCON0_WAVETYPE 0x00000040 /* LPDAC Data Source */ 01916 #define BITM_AFE_LPDACCON0_DACMDE 0x00000020 /* LPDAC0 Switch Settings */ 01917 #define BITM_AFE_LPDACCON0_VZEROMUX 0x00000010 /* VZERO MUX Select */ 01918 #define BITM_AFE_LPDACCON0_VBIASMUX 0x00000008 /* VBIAS MUX Select */ 01919 #define BITM_AFE_LPDACCON0_REFSEL 0x00000004 /* Reference Select Bit */ 01920 #define BITM_AFE_LPDACCON0_PWDEN 0x00000002 /* LPDAC0 Power Down */ 01921 #define BITM_AFE_LPDACCON0_RSTEN 0x00000001 /* Enable Writes to REG_AFE_LPDACDAT00 */ 01922 #define ENUM_AFE_LPDACCON0_MMR 0x00000000 /* WAVETYPE: Direct from REG_AFE_LPDACDAT0DAT0 */ 01923 #define ENUM_AFE_LPDACCON0_WAVEGEN 0x00000040 /* WAVETYPE: Waveform generator */ 01924 #define ENUM_AFE_LPDACCON0_NORM 0x00000000 /* DACMDE: REG_AFE_LPDACDAT00 switches set for normal mode */ 01925 #define ENUM_AFE_LPDACCON0_DIAG 0x00000020 /* DACMDE: REG_AFE_LPDACDAT00 switches set for Diagnostic mode */ 01926 #define ENUM_AFE_LPDACCON0_BITS6 0x00000000 /* VZEROMUX: VZERO 6BIT */ 01927 #define ENUM_AFE_LPDACCON0_BITS12 0x00000010 /* VZEROMUX: VZERO 12BIT */ 01928 #define ENUM_AFE_LPDACCON0_12BIT 0x00000000 /* VBIASMUX: Output 12Bit */ 01929 #define ENUM_AFE_LPDACCON0_EN 0x00000008 /* VBIASMUX: output 6Bit */ 01930 #define ENUM_AFE_LPDACCON0_ULPREF 0x00000000 /* REFSEL: ULP2P5V Ref */ 01931 #define ENUM_AFE_LPDACCON0_AVDD 0x00000004 /* REFSEL: AVDD Reference */ 01932 #define ENUM_AFE_LPDACCON0_PWREN 0x00000000 /* PWDEN: REG_AFE_LPDACDAT00 Powered On */ 01933 #define ENUM_AFE_LPDACCON0_PWRDIS 0x00000002 /* PWDEN: REG_AFE_LPDACDAT00 Powered Off */ 01934 #define ENUM_AFE_LPDACCON0_WRITEDIS 0x00000000 /* RSTEN: Disable REG_AFE_LPDACDAT00 Writes */ 01935 #define ENUM_AFE_LPDACCON0_WRITEEN 0x00000001 /* RSTEN: Enable REG_AFE_LPDACDAT00 Writes */ 01936 01937 /* ------------------------------------------------------------------------------------------------------------------------- 01938 AFE_LPDACDAT1 Pos/Masks Description 01939 ------------------------------------------------------------------------------------------------------------------------- */ 01940 #define BITP_AFE_LPDACDAT1_DACIN6 12 /* 6BITVAL, 1LSB=34.375mV */ 01941 #define BITP_AFE_LPDACDAT1_DACIN12 0 /* 12BITVAL, 1LSB=537uV */ 01942 #define BITM_AFE_LPDACDAT1_DACIN6 (_ADI_MSK_3(0x0003F000,0x0003F000UL, uint32_t )) /* 6BITVAL, 1LSB=34.375mV */ 01943 #define BITM_AFE_LPDACDAT1_DACIN12 (_ADI_MSK_3(0x00000FFF,0x00000FFFUL, uint32_t )) /* 12BITVAL, 1LSB=537uV */ 01944 01945 /* ------------------------------------------------------------------------------------------------------------------------- 01946 AFE_LPDACSW1 Pos/Masks Description 01947 ------------------------------------------------------------------------------------------------------------------------- */ 01948 #define BITP_AFE_LPDACSW1_LPMODEDIS 5 /* Switch Control */ 01949 #define BITP_AFE_LPDACSW1_LPDACSW 0 /* ULPDAC0 Switches Matrix */ 01950 #define BITM_AFE_LPDACSW1_LPMODEDIS (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* Switch Control */ 01951 #define BITM_AFE_LPDACSW1_LPDACSW (_ADI_MSK_3(0x0000001F,0x0000001FUL, uint32_t )) /* ULPDAC0 Switches Matrix */ 01952 #define ENUM_AFE_LPDACSW1_DACCONBIT5 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* LPMODEDIS: ULPDAC Switch controlled by ULPDACCON1 bit 5 */ 01953 #define ENUM_AFE_LPDACSW1_OVRRIDE (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* LPMODEDIS: ULPDAC Switches override */ 01954 01955 /* ------------------------------------------------------------------------------------------------------------------------- 01956 AFE_LPDACCON1 Pos/Masks Description 01957 ------------------------------------------------------------------------------------------------------------------------- */ 01958 #define BITP_AFE_LPDACCON1_WAVETYPE 6 /* DAC Input Source */ 01959 #define BITP_AFE_LPDACCON1_DACMDE 5 /* LPDAC1 Switch Settings */ 01960 #define BITP_AFE_LPDACCON1_VZEROMUX 4 /* VZEROOUT */ 01961 #define BITP_AFE_LPDACCON1_VBIASMUX 3 /* BITSEL */ 01962 #define BITP_AFE_LPDACCON1_REFSEL 2 /* REFSEL */ 01963 #define BITP_AFE_LPDACCON1_PWDEN 1 /* ULPDAC0 Power */ 01964 #define BITP_AFE_LPDACCON1_RSTEN 0 /* Enable Writes to ULPDAC1 */ 01965 #define BITM_AFE_LPDACCON1_WAVETYPE (_ADI_MSK_3(0x00000040,0x00000040UL, uint32_t )) /* DAC Input Source */ 01966 #define BITM_AFE_LPDACCON1_DACMDE (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* LPDAC1 Switch Settings */ 01967 #define BITM_AFE_LPDACCON1_VZEROMUX (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* VZEROOUT */ 01968 #define BITM_AFE_LPDACCON1_VBIASMUX (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* BITSEL */ 01969 #define BITM_AFE_LPDACCON1_REFSEL (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) /* REFSEL */ 01970 #define BITM_AFE_LPDACCON1_PWDEN (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* ULPDAC0 Power */ 01971 #define BITM_AFE_LPDACCON1_RSTEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* Enable Writes to ULPDAC1 */ 01972 #define ENUM_AFE_LPDACCON1_NORM (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* DACMDE: ULPDAC1 switches set for normal mode */ 01973 #define ENUM_AFE_LPDACCON1_DIAG (_ADI_MSK_3(0x00000020,0x00000020UL, uint32_t )) /* DACMDE: ULPDAC1 switches set for Diagnostic mode */ 01974 #define ENUM_AFE_LPDACCON1_BITS6 (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* VZEROMUX: VZERO 6BIT */ 01975 #define ENUM_AFE_LPDACCON1_BITS12 (_ADI_MSK_3(0x00000010,0x00000010UL, uint32_t )) /* VZEROMUX: VZERO 12BIT */ 01976 #define ENUM_AFE_LPDACCON1_DIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* VBIASMUX: 12BIT Output */ 01977 #define ENUM_AFE_LPDACCON1_EN (_ADI_MSK_3(0x00000008,0x00000008UL, uint32_t )) /* VBIASMUX: 6BIT Output */ 01978 #define ENUM_AFE_LPDACCON1_ULPREF (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) 01979 #define ENUM_AFE_LPDACCON1_AVDD (_ADI_MSK_3(0x00000004,0x00000004UL, uint32_t )) 01980 #define ENUM_AFE_LPDACCON1_PWREN (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* PWDEN: ULPDAC1 Powered On */ 01981 #define ENUM_AFE_LPDACCON1_PWRDIS (_ADI_MSK_3(0x00000002,0x00000002UL, uint32_t )) /* PWDEN: ULPDAC1 Powered Off */ 01982 #define ENUM_AFE_LPDACCON1_WRITEDIS (_ADI_MSK_3(0x00000000,0x00000000UL, uint32_t )) /* RSTEN: Disable ULPDAC1 Writes */ 01983 #define ENUM_AFE_LPDACCON1_WRITEEN (_ADI_MSK_3(0x00000001,0x00000001UL, uint32_t )) /* RSTEN: Enable ULPDAC1 Writes */ 01984 01985 /* ------------------------------------------------------------------------------------------------------------------------- 01986 AFE_DSWFULLCON Pos/Masks Description 01987 ------------------------------------------------------------------------------------------------------------------------- */ 01988 #define BITP_AFE_DSWFULLCON_D8 7 /* Control of D8 Switch. */ 01989 #define BITP_AFE_DSWFULLCON_D7 6 /* Control of D7 Switch. */ 01990 #define BITP_AFE_DSWFULLCON_D6 5 /* Control of D6 Switch. */ 01991 #define BITP_AFE_DSWFULLCON_D5 4 /* Control of D5 Switch. */ 01992 #define BITP_AFE_DSWFULLCON_D4 3 /* Control of D4 Switch. */ 01993 #define BITP_AFE_DSWFULLCON_D3 2 /* Control of D3 Switch. */ 01994 #define BITP_AFE_DSWFULLCON_D2 1 /* Control of D2 Switch. */ 01995 #define BITP_AFE_DSWFULLCON_DR0 0 /* Control of Dr0 Switch. */ 01996 #define BITM_AFE_DSWFULLCON_D8 0x00000080 /* Control of D8 Switch. */ 01997 #define BITM_AFE_DSWFULLCON_D7 0x00000040 /* Control of D7 Switch. */ 01998 #define BITM_AFE_DSWFULLCON_D6 0x00000020 /* Control of D6 Switch. */ 01999 #define BITM_AFE_DSWFULLCON_D5 0x00000010 /* Control of D5 Switch. */ 02000 #define BITM_AFE_DSWFULLCON_D4 0x00000008 /* Control of D4 Switch. */ 02001 #define BITM_AFE_DSWFULLCON_D3 0x00000004 /* Control of D3 Switch. */ 02002 #define BITM_AFE_DSWFULLCON_D2 0x00000002 /* Control of D2 Switch. */ 02003 #define BITM_AFE_DSWFULLCON_DR0 0x00000001 /* Control of Dr0 Switch. */ 02004 02005 /* ------------------------------------------------------------------------------------------------------------------------- 02006 AFE_NSWFULLCON Pos/Masks Description 02007 ------------------------------------------------------------------------------------------------------------------------- */ 02008 #define BITP_AFE_NSWFULLCON_NL2 11 /* Control of NL2 Switch. */ 02009 #define BITP_AFE_NSWFULLCON_NL 10 /* Control of NL Switch. */ 02010 #define BITP_AFE_NSWFULLCON_NR1 9 /* Control of Nr1 Switch. Set Will Close Nr1, Unset Open */ 02011 #define BITP_AFE_NSWFULLCON_N9 8 /* Control of N9 Switch. Set Will Close N9, Unset Open */ 02012 #define BITP_AFE_NSWFULLCON_N8 7 /* Control of N8 Switch. Set Will Close N8, Unset Open */ 02013 #define BITP_AFE_NSWFULLCON_N7 6 /* Control of N7 Switch. Set Will Close N7, Unset Open */ 02014 #define BITP_AFE_NSWFULLCON_N6 5 /* Control of N6 Switch. Set Will Close N6, Unset Open */ 02015 #define BITP_AFE_NSWFULLCON_N5 4 /* Control of N5 Switch. Set Will Close N5, Unset Open */ 02016 #define BITP_AFE_NSWFULLCON_N4 3 /* Control of N4 Switch. Set Will Close N4, Unset Open */ 02017 #define BITP_AFE_NSWFULLCON_N3 2 /* Control of N3 Switch. Set Will Close N3, Unset Open */ 02018 #define BITP_AFE_NSWFULLCON_N2 1 /* Control of N2 Switch. Set Will Close N2, Unset Open */ 02019 #define BITP_AFE_NSWFULLCON_N1 0 /* Control of N1 Switch. Set Will Close N1, Unset Open */ 02020 #define BITM_AFE_NSWFULLCON_NL2 0x00000800 /* Control of NL2 Switch. */ 02021 #define BITM_AFE_NSWFULLCON_NL 0x00000400 /* Control of NL Switch. */ 02022 #define BITM_AFE_NSWFULLCON_NR1 0x00000200 /* Control of Nr1 Switch. Set Will Close Nr1, Unset Open */ 02023 #define BITM_AFE_NSWFULLCON_N9 0x00000100 /* Control of N9 Switch. Set Will Close N9, Unset Open */ 02024 #define BITM_AFE_NSWFULLCON_N8 0x00000080 /* Control of N8 Switch. Set Will Close N8, Unset Open */ 02025 #define BITM_AFE_NSWFULLCON_N7 0x00000040 /* Control of N7 Switch. Set Will Close N7, Unset Open */ 02026 #define BITM_AFE_NSWFULLCON_N6 0x00000020 /* Control of N6 Switch. Set Will Close N6, Unset Open */ 02027 #define BITM_AFE_NSWFULLCON_N5 0x00000010 /* Control of N5 Switch. Set Will Close N5, Unset Open */ 02028 #define BITM_AFE_NSWFULLCON_N4 0x00000008 /* Control of N4 Switch. Set Will Close N4, Unset Open */ 02029 #define BITM_AFE_NSWFULLCON_N3 0x00000004 /* Control of N3 Switch. Set Will Close N3, Unset Open */ 02030 #define BITM_AFE_NSWFULLCON_N2 0x00000002 /* Control of N2 Switch. Set Will Close N2, Unset Open */ 02031 #define BITM_AFE_NSWFULLCON_N1 0x00000001 /* Control of N1 Switch. Set Will Close N1, Unset Open */ 02032 02033 /* ------------------------------------------------------------------------------------------------------------------------- 02034 AFE_PSWFULLCON Pos/Masks Description 02035 ------------------------------------------------------------------------------------------------------------------------- */ 02036 #define BITP_AFE_PSWFULLCON_PL2 14 /* PL2 Switch Control */ 02037 #define BITP_AFE_PSWFULLCON_PL 13 /* PL Switch Control */ 02038 #define BITP_AFE_PSWFULLCON_P12 11 /* Control of P12 Switch. Set Will Close P12, Unset Open */ 02039 #define BITP_AFE_PSWFULLCON_P11 10 /* Control of P11 Switch. Set Will Close P11, Unset Open */ 02040 #define BITP_AFE_PSWFULLCON_P10 9 /* P10 Switch Control */ 02041 #define BITP_AFE_PSWFULLCON_P9 8 /* Control of P9 Switch. Set Will Close P9, Unset Open */ 02042 #define BITP_AFE_PSWFULLCON_P8 7 /* Control of P8 Switch. Set Will Close P8, Unset Open */ 02043 #define BITP_AFE_PSWFULLCON_P7 6 /* Control of P7 Switch. Set Will Close P7, Unset Open */ 02044 #define BITP_AFE_PSWFULLCON_P6 5 /* Control of P6 Switch. Set Will Close P6, Unset Open */ 02045 #define BITP_AFE_PSWFULLCON_P5 4 /* Control of P5 Switch. Set Will Close P5, Unset Open */ 02046 #define BITP_AFE_PSWFULLCON_P4 3 /* Control of P4 Switch. Set Will Close P4, Unset Open */ 02047 #define BITP_AFE_PSWFULLCON_P3 2 /* Control of P3 Switch. Set Will Close P3, Unset Open */ 02048 #define BITP_AFE_PSWFULLCON_P2 1 /* Control of P2 Switch. Set Will Close P2, Unset Open */ 02049 #define BITP_AFE_PSWFULLCON_PR0 0 /* PR0 Switch Control */ 02050 #define BITM_AFE_PSWFULLCON_PL2 0x00004000 /* PL2 Switch Control */ 02051 #define BITM_AFE_PSWFULLCON_PL 0x00002000 /* PL Switch Control */ 02052 #define BITM_AFE_PSWFULLCON_P12 0x00000800 /* Control of P12 Switch. Set Will Close P12, Unset Open */ 02053 #define BITM_AFE_PSWFULLCON_P11 0x00000400 /* Control of P11 Switch. Set Will Close P11, Unset Open */ 02054 #define BITM_AFE_PSWFULLCON_P10 0x00000200 /* P10 Switch Control */ 02055 #define BITM_AFE_PSWFULLCON_P9 0x00000100 /* Control of P9 Switch. Set Will Close P9, Unset Open */ 02056 #define BITM_AFE_PSWFULLCON_P8 0x00000080 /* Control of P8 Switch. Set Will Close P8, Unset Open */ 02057 #define BITM_AFE_PSWFULLCON_P7 0x00000040 /* Control of P7 Switch. Set Will Close P7, Unset Open */ 02058 #define BITM_AFE_PSWFULLCON_P6 0x00000020 /* Control of P6 Switch. Set Will Close P6, Unset Open */ 02059 #define BITM_AFE_PSWFULLCON_P5 0x00000010 /* Control of P5 Switch. Set Will Close P5, Unset Open */ 02060 #define BITM_AFE_PSWFULLCON_P4 0x00000008 /* Control of P4 Switch. Set Will Close P4, Unset Open */ 02061 #define BITM_AFE_PSWFULLCON_P3 0x00000004 /* Control of P3 Switch. Set Will Close P3, Unset Open */ 02062 #define BITM_AFE_PSWFULLCON_P2 0x00000002 /* Control of P2 Switch. Set Will Close P2, Unset Open */ 02063 #define BITM_AFE_PSWFULLCON_PR0 0x00000001 /* PR0 Switch Control */ 02064 02065 /* ------------------------------------------------------------------------------------------------------------------------- 02066 AFE_TSWFULLCON Pos/Masks Description 02067 ------------------------------------------------------------------------------------------------------------------------- */ 02068 #define BITP_AFE_TSWFULLCON_TR1 11 /* Control of Tr1 Switch. Set Will Close Tr1, Unset Open */ 02069 #define BITP_AFE_TSWFULLCON_T11 10 /* Control of T11 Switch. Set Will Close T11, Unset Open */ 02070 #define BITP_AFE_TSWFULLCON_T10 9 /* Control of T10 Switch. Set Will Close T10, Unset Open */ 02071 #define BITP_AFE_TSWFULLCON_T9 8 /* Control of T9 Switch. Set Will Close T9, Unset Open */ 02072 #define BITP_AFE_TSWFULLCON_T7 6 /* Control of T7 Switch. Set Will Close T7, Unset Open */ 02073 #define BITP_AFE_TSWFULLCON_T5 4 /* Control of T5 Switch. Set Will Close T5, Unset Open */ 02074 #define BITP_AFE_TSWFULLCON_T4 3 /* Control of T4 Switch. Set Will Close T4, Unset Open */ 02075 #define BITP_AFE_TSWFULLCON_T3 2 /* Control of T3 Switch. Set Will Close T3, Unset Open */ 02076 #define BITP_AFE_TSWFULLCON_T2 1 /* Control of T2 Switch. Set Will Close T2, Unset Open */ 02077 #define BITP_AFE_TSWFULLCON_T1 0 /* Control of T1 Switch. Set Will Close T1, Unset Open */ 02078 #define BITM_AFE_TSWFULLCON_TR1 0x00000800 /* Control of Tr1 Switch. Set Will Close Tr1, Unset Open */ 02079 #define BITM_AFE_TSWFULLCON_T11 0x00000400 /* Control of T11 Switch. Set Will Close T11, Unset Open */ 02080 #define BITM_AFE_TSWFULLCON_T10 0x00000200 /* Control of T10 Switch. Set Will Close T10, Unset Open */ 02081 #define BITM_AFE_TSWFULLCON_T9 0x00000100 /* Control of T9 Switch. Set Will Close T9, Unset Open */ 02082 #define BITM_AFE_TSWFULLCON_T7 0x00000040 /* Control of T7 Switch. Set Will Close T7, Unset Open */ 02083 #define BITM_AFE_TSWFULLCON_T5 0x00000010 /* Control of T5 Switch. Set Will Close T5, Unset Open */ 02084 #define BITM_AFE_TSWFULLCON_T4 0x00000008 /* Control of T4 Switch. Set Will Close T4, Unset Open */ 02085 #define BITM_AFE_TSWFULLCON_T3 0x00000004 /* Control of T3 Switch. Set Will Close T3, Unset Open */ 02086 #define BITM_AFE_TSWFULLCON_T2 0x00000002 /* Control of T2 Switch. Set Will Close T2, Unset Open */ 02087 #define BITM_AFE_TSWFULLCON_T1 0x00000001 /* Control of T1 Switch. Set Will Close T1, Unset Open */ 02088 02089 /* ------------------------------------------------------------------------------------------------------------------------- 02090 AFE_TEMPSENS Pos/Masks Description 02091 ------------------------------------------------------------------------------------------------------------------------- */ 02092 #define BITP_AFE_TEMPSENS_CHOPFRESEL 2 /* Chop Mode Frequency Setting */ 02093 #define BITP_AFE_TEMPSENS_CHOPCON 1 /* Temp Sensor Chop Mode */ 02094 #define BITP_AFE_TEMPSENS_ENABLE 0 /* Unused */ 02095 #define BITM_AFE_TEMPSENS_CHOPFRESEL 0x0000000C /* Chop Mode Frequency Setting */ 02096 #define BITM_AFE_TEMPSENS_CHOPCON 0x00000002 /* Temp Sensor Chop Mode */ 02097 #define BITM_AFE_TEMPSENS_ENABLE 0x00000001 /* Unused */ 02098 #define ENUM_AFE_TEMPSENS_DIS 0x00000000 /* CHOPCON: Disable chop */ 02099 #define ENUM_AFE_TEMPSENS_EN 0x00000002 /* CHOPCON: Enable chop */ 02100 02101 /* ------------------------------------------------------------------------------------------------------------------------- 02102 AFE_BUFSENCON Pos/Masks Description 02103 ------------------------------------------------------------------------------------------------------------------------- */ 02104 #define BITP_AFE_BUFSENCON_V1P8THERMSTEN 8 /* Buffered Reference Output */ 02105 #define BITP_AFE_BUFSENCON_V1P1LPADCCHGDIS 6 /* Controls Decoupling Cap Discharge Switch */ 02106 #define BITP_AFE_BUFSENCON_V1P1LPADCEN 5 /* ADC 1.1V LP Buffer */ 02107 #define BITP_AFE_BUFSENCON_V1P1HPADCEN 4 /* Enable 1.1V HP CM Buffer */ 02108 #define BITP_AFE_BUFSENCON_V1P8HPADCCHGDIS 3 /* Controls Decoupling Cap Discharge Switch */ 02109 #define BITP_AFE_BUFSENCON_V1P8LPADCEN 2 /* ADC 1.8V LP Reference Buffer */ 02110 #define BITP_AFE_BUFSENCON_V1P8HPADCILIMITEN 1 /* HP ADC Input Current Limit */ 02111 #define BITP_AFE_BUFSENCON_V1P8HPADCEN 0 /* HP 1.8V Reference Buffer */ 02112 #define BITM_AFE_BUFSENCON_V1P8THERMSTEN 0x00000100 /* Buffered Reference Output */ 02113 #define BITM_AFE_BUFSENCON_V1P1LPADCCHGDIS 0x00000040 /* Controls Decoupling Cap Discharge Switch */ 02114 #define BITM_AFE_BUFSENCON_V1P1LPADCEN 0x00000020 /* ADC 1.1V LP Buffer */ 02115 #define BITM_AFE_BUFSENCON_V1P1HPADCEN 0x00000010 /* Enable 1.1V HP CM Buffer */ 02116 #define BITM_AFE_BUFSENCON_V1P8HPADCCHGDIS 0x00000008 /* Controls Decoupling Cap Discharge Switch */ 02117 #define BITM_AFE_BUFSENCON_V1P8LPADCEN 0x00000004 /* ADC 1.8V LP Reference Buffer */ 02118 #define BITM_AFE_BUFSENCON_V1P8HPADCILIMITEN 0x00000002 /* HP ADC Input Current Limit */ 02119 #define BITM_AFE_BUFSENCON_V1P8HPADCEN 0x00000001 /* HP 1.8V Reference Buffer */ 02120 #define ENUM_AFE_BUFSENCON_DIS 0x00000000 /* V1P8THERMSTEN: Disable 1.8V Buffered Reference output */ 02121 #define ENUM_AFE_BUFSENCON_EN 0x00000100 /* V1P8THERMSTEN: Enable 1.8V Buffered Reference output */ 02122 #define ENUM_AFE_BUFSENCON_ENCHRG 0x00000000 /* V1P1LPADCCHGDIS: Open switch */ 02123 #define ENUM_AFE_BUFSENCON_DISCHRG 0x00000040 /* V1P1LPADCCHGDIS: Close Switch */ 02124 #define ENUM_AFE_BUFSENCON_DISABLE 0x00000000 /* V1P1LPADCEN: Disable ADC 1.8V LP Reference Buffer */ 02125 #define ENUM_AFE_BUFSENCON_ENABLE 0x00000020 /* V1P1LPADCEN: Enable ADC 1.8V LP Reference Buffer */ 02126 #define ENUM_AFE_BUFSENCON_OFF 0x00000000 /* V1P1HPADCEN: Disable 1.1V HP Common Mode Buffer */ 02127 #define ENUM_AFE_BUFSENCON_ON 0x00000010 /* V1P1HPADCEN: Enable 1.1V HP Common Mode Buffer */ 02128 #define ENUM_AFE_BUFSENCON_OPEN 0x00000000 /* V1P8HPADCCHGDIS: Open switch */ 02129 #define ENUM_AFE_BUFSENCON_CLOSED 0x00000008 /* V1P8HPADCCHGDIS: Close Switch */ 02130 #define ENUM_AFE_BUFSENCON_LPADCREF_DIS 0x00000000 /* V1P8LPADCEN: Disable LP 1.8V Reference Buffer */ 02131 #define ENUM_AFE_BUFSENCON_LPADCREF_EN 0x00000004 /* V1P8LPADCEN: Enable LP 1.8V Reference Buffer */ 02132 #define ENUM_AFE_BUFSENCON_LIMIT_DIS 0x00000000 /* V1P8HPADCILIMITEN: Disable buffer Current Limit */ 02133 #define ENUM_AFE_BUFSENCON_LIMIT_EN 0x00000002 /* V1P8HPADCILIMITEN: Enable buffer Current Limit */ 02134 #define ENUM_AFE_BUFSENCON_HPBUF_DIS 0x00000000 /* V1P8HPADCEN: Disable 1.8V HP ADC Reference Buffer */ 02135 #define ENUM_AFE_BUFSENCON_HPBUF_EN 0x00000001 /* V1P8HPADCEN: Enable 1.8V HP ADC Reference Buffer */ 02136 02137 /* ------------------------------------------------------------------------------------------------------------------------- 02138 AFE_ADCCON Pos/Masks Description 02139 ------------------------------------------------------------------------------------------------------------------------- */ 02140 #define BITP_AFE_ADCCON_GNPGA 16 /* PGA Gain Setup */ 02141 #define BITP_AFE_ADCCON_GNOFSELPGA 15 /* Internal Offset/Gain Cancellation */ 02142 #define BITP_AFE_ADCCON_GNOFFSEL 13 /* Obsolete */ 02143 #define BITP_AFE_ADCCON_MUXSELN 8 /* Select Negative Input */ 02144 #define BITP_AFE_ADCCON_MUXSELP 0 /* Select Positive Input */ 02145 #define BITM_AFE_ADCCON_GNPGA 0x00070000 /* PGA Gain Setup */ 02146 #define BITM_AFE_ADCCON_GNOFSELPGA 0x00008000 /* Internal Offset/Gain Cancellation */ 02147 #define BITM_AFE_ADCCON_GNOFFSEL 0x00006000 /* Obsolete */ 02148 #define BITM_AFE_ADCCON_MUXSELN 0x00001F00 /* Select Negative Input */ 02149 #define BITM_AFE_ADCCON_MUXSELP 0x0000003F /* Select Positive Input */ 02150 #define ENUM_AFE_ADCCON_RESERVED 0x00000011 /* MUXSELP: Reserved */ 02151 02152 /* ------------------------------------------------------------------------------------------------------------------------- 02153 AFE_DSWSTA Pos/Masks Description 02154 ------------------------------------------------------------------------------------------------------------------------- */ 02155 #define BITP_AFE_DSWSTA_D8STA 7 /* Status of D8 Switch. */ 02156 #define BITP_AFE_DSWSTA_D7STA 6 /* Status of D7 Switch. */ 02157 #define BITP_AFE_DSWSTA_D6STA 5 /* Status of D6 Switch. */ 02158 #define BITP_AFE_DSWSTA_D5STA 4 /* Status of D5 Switch. */ 02159 #define BITP_AFE_DSWSTA_D4STA 3 /* Status of D4 Switch. */ 02160 #define BITP_AFE_DSWSTA_D3STA 2 /* Status of D3 Switch. */ 02161 #define BITP_AFE_DSWSTA_D2STA 1 /* Status of D2 Switch. */ 02162 #define BITP_AFE_DSWSTA_D1STA 0 /* Status of Dr0 Switch. */ 02163 #define BITM_AFE_DSWSTA_D8STA 0x00000080 /* Status of D8 Switch. */ 02164 #define BITM_AFE_DSWSTA_D7STA 0x00000040 /* Status of D7 Switch. */ 02165 #define BITM_AFE_DSWSTA_D6STA 0x00000020 /* Status of D6 Switch. */ 02166 #define BITM_AFE_DSWSTA_D5STA 0x00000010 /* Status of D5 Switch. */ 02167 #define BITM_AFE_DSWSTA_D4STA 0x00000008 /* Status of D4 Switch. */ 02168 #define BITM_AFE_DSWSTA_D3STA 0x00000004 /* Status of D3 Switch. */ 02169 #define BITM_AFE_DSWSTA_D2STA 0x00000002 /* Status of D2 Switch. */ 02170 #define BITM_AFE_DSWSTA_D1STA 0x00000001 /* Status of Dr0 Switch. */ 02171 02172 /* ------------------------------------------------------------------------------------------------------------------------- 02173 AFE_PSWSTA Pos/Masks Description 02174 ------------------------------------------------------------------------------------------------------------------------- */ 02175 #define BITP_AFE_PSWSTA_PL2STA 14 /* PL Switch Control */ 02176 #define BITP_AFE_PSWSTA_PLSTA 13 /* PL Switch Control */ 02177 #define BITP_AFE_PSWSTA_P13STA 12 /* Status of P13 Switch. */ 02178 #define BITP_AFE_PSWSTA_P12STA 11 /* Status of P12 Switch. */ 02179 #define BITP_AFE_PSWSTA_P11STA 10 /* Status of P11 Switch. */ 02180 #define BITP_AFE_PSWSTA_P10STA 9 /* Status of P10 Switch. */ 02181 #define BITP_AFE_PSWSTA_P9STA 8 /* Status of P9 Switch. */ 02182 #define BITP_AFE_PSWSTA_P8STA 7 /* Status of P8 Switch. */ 02183 #define BITP_AFE_PSWSTA_P7STA 6 /* Status of P7 Switch. */ 02184 #define BITP_AFE_PSWSTA_P6STA 5 /* Status of P6 Switch. */ 02185 #define BITP_AFE_PSWSTA_P5STA 4 /* Status of P5 Switch. */ 02186 #define BITP_AFE_PSWSTA_P4STA 3 /* Status of P4 Switch. */ 02187 #define BITP_AFE_PSWSTA_P3STA 2 /* Status of P3 Switch. */ 02188 #define BITP_AFE_PSWSTA_P2STA 1 /* Status of P2 Switch. */ 02189 #define BITP_AFE_PSWSTA_PR0STA 0 /* PR0 Switch Control */ 02190 #define BITM_AFE_PSWSTA_PL2STA 0x00004000 /* PL Switch Control */ 02191 #define BITM_AFE_PSWSTA_PLSTA 0x00002000 /* PL Switch Control */ 02192 #define BITM_AFE_PSWSTA_P13STA 0x00001000 /* Status of P13 Switch. */ 02193 #define BITM_AFE_PSWSTA_P12STA 0x00000800 /* Status of P12 Switch. */ 02194 #define BITM_AFE_PSWSTA_P11STA 0x00000400 /* Status of P11 Switch. */ 02195 #define BITM_AFE_PSWSTA_P10STA 0x00000200 /* Status of P10 Switch. */ 02196 #define BITM_AFE_PSWSTA_P9STA 0x00000100 /* Status of P9 Switch. */ 02197 #define BITM_AFE_PSWSTA_P8STA 0x00000080 /* Status of P8 Switch. */ 02198 #define BITM_AFE_PSWSTA_P7STA 0x00000040 /* Status of P7 Switch. */ 02199 #define BITM_AFE_PSWSTA_P6STA 0x00000020 /* Status of P6 Switch. */ 02200 #define BITM_AFE_PSWSTA_P5STA 0x00000010 /* Status of P5 Switch. */ 02201 #define BITM_AFE_PSWSTA_P4STA 0x00000008 /* Status of P4 Switch. */ 02202 #define BITM_AFE_PSWSTA_P3STA 0x00000004 /* Status of P3 Switch. */ 02203 #define BITM_AFE_PSWSTA_P2STA 0x00000002 /* Status of P2 Switch. */ 02204 #define BITM_AFE_PSWSTA_PR0STA 0x00000001 /* PR0 Switch Control */ 02205 02206 /* ------------------------------------------------------------------------------------------------------------------------- 02207 AFE_NSWSTA Pos/Masks Description 02208 ------------------------------------------------------------------------------------------------------------------------- */ 02209 #define BITP_AFE_NSWSTA_NL2STA 11 /* Status of NL2 Switch. */ 02210 #define BITP_AFE_NSWSTA_NLSTA 10 /* Status of NL Switch. */ 02211 #define BITP_AFE_NSWSTA_NR1STA 9 /* Status of NR1 Switch. */ 02212 #define BITP_AFE_NSWSTA_N9STA 8 /* Status of N9 Switch. */ 02213 #define BITP_AFE_NSWSTA_N8STA 7 /* Status of N8 Switch. */ 02214 #define BITP_AFE_NSWSTA_N7STA 6 /* Status of N7 Switch. */ 02215 #define BITP_AFE_NSWSTA_N6STA 5 /* Status of N6 Switch. */ 02216 #define BITP_AFE_NSWSTA_N5STA 4 /* Status of N5 Switch. */ 02217 #define BITP_AFE_NSWSTA_N4STA 3 /* Status of N4 Switch. */ 02218 #define BITP_AFE_NSWSTA_N3STA 2 /* Status of N3 Switch. */ 02219 #define BITP_AFE_NSWSTA_N2STA 1 /* Status of N2 Switch. */ 02220 #define BITP_AFE_NSWSTA_N1STA 0 /* Status of N1 Switch. */ 02221 #define BITM_AFE_NSWSTA_NL2STA 0x00000800 /* Status of NL2 Switch. */ 02222 #define BITM_AFE_NSWSTA_NLSTA 0x00000400 /* Status of NL Switch. */ 02223 #define BITM_AFE_NSWSTA_NR1STA 0x00000200 /* Status of NR1 Switch. */ 02224 #define BITM_AFE_NSWSTA_N9STA 0x00000100 /* Status of N9 Switch. */ 02225 #define BITM_AFE_NSWSTA_N8STA 0x00000080 /* Status of N8 Switch. */ 02226 #define BITM_AFE_NSWSTA_N7STA 0x00000040 /* Status of N7 Switch. */ 02227 #define BITM_AFE_NSWSTA_N6STA 0x00000020 /* Status of N6 Switch. */ 02228 #define BITM_AFE_NSWSTA_N5STA 0x00000010 /* Status of N5 Switch. */ 02229 #define BITM_AFE_NSWSTA_N4STA 0x00000008 /* Status of N4 Switch. */ 02230 #define BITM_AFE_NSWSTA_N3STA 0x00000004 /* Status of N3 Switch. */ 02231 #define BITM_AFE_NSWSTA_N2STA 0x00000002 /* Status of N2 Switch. */ 02232 #define BITM_AFE_NSWSTA_N1STA 0x00000001 /* Status of N1 Switch. */ 02233 02234 /* ------------------------------------------------------------------------------------------------------------------------- 02235 AFE_TSWSTA Pos/Masks Description 02236 ------------------------------------------------------------------------------------------------------------------------- */ 02237 #define BITP_AFE_TSWSTA_TR1STA 11 /* Status of TR1 Switch. */ 02238 #define BITP_AFE_TSWSTA_T11STA 10 /* Status of T11 Switch. */ 02239 #define BITP_AFE_TSWSTA_T10STA 9 /* Status of T10 Switch. */ 02240 #define BITP_AFE_TSWSTA_T9STA 8 /* Status of T9 Switch. */ 02241 #define BITP_AFE_TSWSTA_T8STA 7 /* Status of T8 Switch. */ 02242 #define BITP_AFE_TSWSTA_T7STA 6 /* Status of T7 Switch. */ 02243 #define BITP_AFE_TSWSTA_T6STA 5 /* Status of T6 Switch. */ 02244 #define BITP_AFE_TSWSTA_T5STA 4 /* Status of T5 Switch. */ 02245 #define BITP_AFE_TSWSTA_T4STA 3 /* Status of T4 Switch. */ 02246 #define BITP_AFE_TSWSTA_T3STA 2 /* Status of T3 Switch. */ 02247 #define BITP_AFE_TSWSTA_T2STA 1 /* Status of T2 Switch. */ 02248 #define BITP_AFE_TSWSTA_T1STA 0 /* Status of T1 Switch. */ 02249 #define BITM_AFE_TSWSTA_TR1STA 0x00000800 /* Status of TR1 Switch. */ 02250 #define BITM_AFE_TSWSTA_T11STA 0x00000400 /* Status of T11 Switch. */ 02251 #define BITM_AFE_TSWSTA_T10STA 0x00000200 /* Status of T10 Switch. */ 02252 #define BITM_AFE_TSWSTA_T9STA 0x00000100 /* Status of T9 Switch. */ 02253 #define BITM_AFE_TSWSTA_T8STA 0x00000080 /* Status of T8 Switch. */ 02254 #define BITM_AFE_TSWSTA_T7STA 0x00000040 /* Status of T7 Switch. */ 02255 #define BITM_AFE_TSWSTA_T6STA 0x00000020 /* Status of T6 Switch. */ 02256 #define BITM_AFE_TSWSTA_T5STA 0x00000010 /* Status of T5 Switch. */ 02257 #define BITM_AFE_TSWSTA_T4STA 0x00000008 /* Status of T4 Switch. */ 02258 #define BITM_AFE_TSWSTA_T3STA 0x00000004 /* Status of T3 Switch. */ 02259 #define BITM_AFE_TSWSTA_T2STA 0x00000002 /* Status of T2 Switch. */ 02260 #define BITM_AFE_TSWSTA_T1STA 0x00000001 /* Status of T1 Switch. */ 02261 02262 /* ------------------------------------------------------------------------------------------------------------------------- 02263 AFE_STATSVAR Pos/Masks Description 02264 ------------------------------------------------------------------------------------------------------------------------- */ 02265 #define BITP_AFE_STATSVAR_VARIANCE 0 /* Statistical Variance Value */ 02266 #define BITM_AFE_STATSVAR_VARIANCE 0x7FFFFFFF /* Statistical Variance Value */ 02267 02268 /* ------------------------------------------------------------------------------------------------------------------------- 02269 AFE_STATSCON Pos/Masks Description 02270 ------------------------------------------------------------------------------------------------------------------------- */ 02271 #define BITP_AFE_STATSCON_STDDEV 7 /* Standard Deviation Configuration */ 02272 #define BITP_AFE_STATSCON_SAMPLENUM 4 /* Sample Size */ 02273 #define BITP_AFE_STATSCON_RESRVED 1 /* Reserved */ 02274 #define BITP_AFE_STATSCON_STATSEN 0 /* Statistics Enable */ 02275 #define BITM_AFE_STATSCON_STDDEV 0x00000F80 /* Standard Deviation Configuration */ 02276 #define BITM_AFE_STATSCON_SAMPLENUM 0x00000070 /* Sample Size */ 02277 #define BITM_AFE_STATSCON_RESRVED 0x0000000E /* Reserved */ 02278 #define BITM_AFE_STATSCON_STATSEN 0x00000001 /* Statistics Enable */ 02279 #define ENUM_AFE_STATSCON_DIS 0x00000000 /* STATSEN: Disable Statistics */ 02280 #define ENUM_AFE_STATSCON_EN 0x00000001 /* STATSEN: Enable Statistics */ 02281 02282 /* ------------------------------------------------------------------------------------------------------------------------- 02283 AFE_STATSMEAN Pos/Masks Description 02284 ------------------------------------------------------------------------------------------------------------------------- */ 02285 #define BITP_AFE_STATSMEAN_MEAN 0 /* Mean Output */ 02286 #define BITM_AFE_STATSMEAN_MEAN 0x0000FFFF /* Mean Output */ 02287 02288 /* ------------------------------------------------------------------------------------------------------------------------- 02289 AFE_SEQ0INFO Pos/Masks Description 02290 ------------------------------------------------------------------------------------------------------------------------- */ 02291 #define BITP_AFE_SEQ0INFO_LEN 16 /* SEQ0 Instruction Number */ 02292 #define BITP_AFE_SEQ0INFO_ADDR 0 /* SEQ0 Start Address */ 02293 #define BITM_AFE_SEQ0INFO_LEN 0x07FF0000 /* SEQ0 Instruction Number */ 02294 #define BITM_AFE_SEQ0INFO_ADDR 0x000007FF /* SEQ0 Start Address */ 02295 02296 /* ------------------------------------------------------------------------------------------------------------------------- 02297 AFE_SEQ2INFO Pos/Masks Description 02298 ------------------------------------------------------------------------------------------------------------------------- */ 02299 #define BITP_AFE_SEQ2INFO_LEN 16 /* SEQ2 Instruction Number */ 02300 #define BITP_AFE_SEQ2INFO_ADDR 0 /* SEQ2 Start Address */ 02301 #define BITM_AFE_SEQ2INFO_LEN 0x07FF0000 /* SEQ2 Instruction Number */ 02302 #define BITM_AFE_SEQ2INFO_ADDR 0x000007FF /* SEQ2 Start Address */ 02303 02304 /* ------------------------------------------------------------------------------------------------------------------------- 02305 AFE_CMDFIFOWADDR Pos/Masks Description 02306 ------------------------------------------------------------------------------------------------------------------------- */ 02307 #define BITP_AFE_CMDFIFOWADDR_WADDR 0 /* Write Address */ 02308 #define BITM_AFE_CMDFIFOWADDR_WADDR 0x000007FF /* Write Address */ 02309 02310 /* ------------------------------------------------------------------------------------------------------------------------- 02311 AFE_CMDDATACON Pos/Masks Description 02312 ------------------------------------------------------------------------------------------------------------------------- */ 02313 #define BITP_AFE_CMDDATACON_DATAMEMMDE 9 /* Data FIFO Mode Select */ 02314 #define BITP_AFE_CMDDATACON_DATA_MEM_SEL 6 /* Data FIFO Size Select */ 02315 #define BITP_AFE_CMDDATACON_CMDMEMMDE 3 /* This is Command Fifo Mode Register */ 02316 #define BITP_AFE_CMDDATACON_CMD_MEM_SEL 0 /* Command Memory Select */ 02317 #define BITM_AFE_CMDDATACON_DATAMEMMDE 0x00000E00 /* Data FIFO Mode Select */ 02318 #define BITM_AFE_CMDDATACON_DATA_MEM_SEL 0x000001C0 /* Data FIFO Size Select */ 02319 #define BITM_AFE_CMDDATACON_CMDMEMMDE 0x00000038 /* This is Command Fifo Mode Register */ 02320 #define BITM_AFE_CMDDATACON_CMD_MEM_SEL 0x00000007 /* Command Memory Select */ 02321 #define ENUM_AFE_CMDDATACON_DFIFO 0x00000400 /* DATAMEMMDE: FIFO MODE */ 02322 #define ENUM_AFE_CMDDATACON_DSTM 0x00000600 /* DATAMEMMDE: STREAM MODE */ 02323 #define ENUM_AFE_CMDDATACON_DMEM32B 0x00000000 /* DATA_MEM_SEL: 32B_1 Local Memory */ 02324 #define ENUM_AFE_CMDDATACON_DMEM2K 0x00000040 /* DATA_MEM_SEL: 2K_2 SRAM */ 02325 #define ENUM_AFE_CMDDATACON_DMEM4K 0x00000080 /* DATA_MEM_SEL: 2K_2~1 SRAM */ 02326 #define ENUM_AFE_CMDDATACON_DMEM6K 0x000000C0 /* DATA_MEM_SEL: 2K_2~0 SRAM */ 02327 #define ENUM_AFE_CMDDATACON_CMEM 0x00000008 /* CMDMEMMDE: MEMORY MODE */ 02328 #define ENUM_AFE_CMDDATACON_CFIFO 0x00000010 /* CMDMEMMDE: FIFO MODE */ 02329 #define ENUM_AFE_CMDDATACON_CSTM 0x00000018 /* CMDMEMMDE: STREAM MODE */ 02330 #define ENUM_AFE_CMDDATACON_CMEM32B 0x00000000 /* CMD_MEM_SEL: 32B_0 Local Memory */ 02331 #define ENUM_AFE_CMDDATACON_CMEM2K 0x00000001 /* CMD_MEM_SEL: 2K_0 SRAM */ 02332 #define ENUM_AFE_CMDDATACON_CMEM4K 0x00000002 /* CMD_MEM_SEL: 2K_0~1 SRAM */ 02333 #define ENUM_AFE_CMDDATACON_CMEM6K 0x00000003 /* CMD_MEM_SEL: 2K_0~2 SRAM */ 02334 02335 /* ------------------------------------------------------------------------------------------------------------------------- 02336 AFE_DATAFIFOTHRES Pos/Masks Description 02337 ------------------------------------------------------------------------------------------------------------------------- */ 02338 #define BITP_AFE_DATAFIFOTHRES_HIGHTHRES 16 /* High Threshold */ 02339 #define BITM_AFE_DATAFIFOTHRES_HIGHTHRES 0x07FF0000 /* High Threshold */ 02340 02341 /* ------------------------------------------------------------------------------------------------------------------------- 02342 AFE_SEQ3INFO Pos/Masks Description 02343 ------------------------------------------------------------------------------------------------------------------------- */ 02344 #define BITP_AFE_SEQ3INFO_LEN 16 /* SEQ3 Instruction Number */ 02345 #define BITP_AFE_SEQ3INFO_ADDR 0 /* SEQ3 Start Address */ 02346 #define BITM_AFE_SEQ3INFO_LEN 0x07FF0000 /* SEQ3 Instruction Number */ 02347 #define BITM_AFE_SEQ3INFO_ADDR 0x000007FF /* SEQ3 Start Address */ 02348 02349 /* ------------------------------------------------------------------------------------------------------------------------- 02350 AFE_SEQ1INFO Pos/Masks Description 02351 ------------------------------------------------------------------------------------------------------------------------- */ 02352 #define BITP_AFE_SEQ1INFO_LEN 16 /* SEQ1 Instruction Number */ 02353 #define BITP_AFE_SEQ1INFO_ADDR 0 /* SEQ1 Start Address */ 02354 #define BITM_AFE_SEQ1INFO_LEN 0x07FF0000 /* SEQ1 Instruction Number */ 02355 #define BITM_AFE_SEQ1INFO_ADDR 0x000007FF /* SEQ1 Start Address */ 02356 02357 /* ------------------------------------------------------------------------------------------------------------------------- 02358 AFE_REPEATADCCNV Pos/Masks Description 02359 ------------------------------------------------------------------------------------------------------------------------- */ 02360 #define BITP_AFE_REPEATADCCNV_NUM 4 /* Repeat Value */ 02361 #define BITP_AFE_REPEATADCCNV_EN 0 /* Enable Repeat ADC Conversions */ 02362 #define BITM_AFE_REPEATADCCNV_NUM 0x00000FF0 /* Repeat Value */ 02363 #define BITM_AFE_REPEATADCCNV_EN 0x00000001 /* Enable Repeat ADC Conversions */ 02364 #define ENUM_AFE_REPEATADCCNV_DIS 0x00000000 /* EN: Disable Repeat ADC Conversions */ 02365 #define ENUM_AFE_REPEATADCCNV_EN 0x00000001 /* EN: Enable Repeat ADC Conversions */ 02366 02367 /* ------------------------------------------------------------------------------------------------------------------------- 02368 AFE_FIFOCNTSTA Pos/Masks Description 02369 ------------------------------------------------------------------------------------------------------------------------- */ 02370 #define BITP_AFE_FIFOCNTSTA_DATAFIFOCNTSTA 16 /* Current Number of Words in the Data FIFO */ 02371 #define BITM_AFE_FIFOCNTSTA_DATAFIFOCNTSTA 0x07FF0000 /* Current Number of Words in the Data FIFO */ 02372 02373 /* ------------------------------------------------------------------------------------------------------------------------- 02374 AFE_CALDATLOCK Pos/Masks Description 02375 ------------------------------------------------------------------------------------------------------------------------- */ 02376 #define BITP_AFE_CALDATLOCK_KEY 0 /* Password for Calibration Data Registers */ 02377 #define BITM_AFE_CALDATLOCK_KEY 0xFFFFFFFF /* Password for Calibration Data Registers */ 02378 02379 /* ------------------------------------------------------------------------------------------------------------------------- 02380 AFE_ADCOFFSETHSTIA Pos/Masks Description 02381 ------------------------------------------------------------------------------------------------------------------------- */ 02382 #define BITP_AFE_ADCOFFSETHSTIA_VALUE 0 /* HSTIA Offset Calibration */ 02383 #define BITM_AFE_ADCOFFSETHSTIA_VALUE 0x00007FFF /* HSTIA Offset Calibration */ 02384 02385 /* ------------------------------------------------------------------------------------------------------------------------- 02386 AFE_ADCGAINTEMPSENS0 Pos/Masks Description 02387 ------------------------------------------------------------------------------------------------------------------------- */ 02388 #define BITP_AFE_ADCGAINTEMPSENS0_VALUE 0 /* Gain Calibration Temp Sensor Channel */ 02389 #define BITM_AFE_ADCGAINTEMPSENS0_VALUE 0x00007FFF /* Gain Calibration Temp Sensor Channel */ 02390 02391 /* ------------------------------------------------------------------------------------------------------------------------- 02392 AFE_ADCOFFSETTEMPSENS0 Pos/Masks Description 02393 ------------------------------------------------------------------------------------------------------------------------- */ 02394 #define BITP_AFE_ADCOFFSETTEMPSENS0_VALUE 0 /* Offset Calibration Temp Sensor */ 02395 #define BITM_AFE_ADCOFFSETTEMPSENS0_VALUE 0x00007FFF /* Offset Calibration Temp Sensor */ 02396 02397 /* ------------------------------------------------------------------------------------------------------------------------- 02398 AFE_ADCGAINGN1 Pos/Masks Description 02399 ------------------------------------------------------------------------------------------------------------------------- */ 02400 #define BITP_AFE_ADCGAINGN1_VALUE 0 /* Gain Calibration PGA Gain 1x */ 02401 #define BITM_AFE_ADCGAINGN1_VALUE 0x00007FFF /* Gain Calibration PGA Gain 1x */ 02402 02403 /* ------------------------------------------------------------------------------------------------------------------------- 02404 AFE_ADCOFFSETGN1 Pos/Masks Description 02405 ------------------------------------------------------------------------------------------------------------------------- */ 02406 #define BITP_AFE_ADCOFFSETGN1_VALUE 0 /* Offset Calibration Gain1 */ 02407 #define BITM_AFE_ADCOFFSETGN1_VALUE 0x00007FFF /* Offset Calibration Gain1 */ 02408 02409 /* ------------------------------------------------------------------------------------------------------------------------- 02410 AFE_DACGAIN Pos/Masks Description 02411 ------------------------------------------------------------------------------------------------------------------------- */ 02412 #define BITP_AFE_DACGAIN_VALUE 0 /* HS DAC Gain Correction Factor */ 02413 #define BITM_AFE_DACGAIN_VALUE 0x00000FFF /* HS DAC Gain Correction Factor */ 02414 02415 /* ------------------------------------------------------------------------------------------------------------------------- 02416 AFE_DACOFFSETATTEN Pos/Masks Description 02417 ------------------------------------------------------------------------------------------------------------------------- */ 02418 #define BITP_AFE_DACOFFSETATTEN_VALUE 0 /* DAC Offset Correction Factor */ 02419 #define BITM_AFE_DACOFFSETATTEN_VALUE 0x00000FFF /* DAC Offset Correction Factor */ 02420 02421 /* ------------------------------------------------------------------------------------------------------------------------- 02422 AFE_DACOFFSET Pos/Masks Description 02423 ------------------------------------------------------------------------------------------------------------------------- */ 02424 #define BITP_AFE_DACOFFSET_VALUE 0 /* DAC Offset Correction Factor */ 02425 #define BITM_AFE_DACOFFSET_VALUE 0x00000FFF /* DAC Offset Correction Factor */ 02426 02427 /* ------------------------------------------------------------------------------------------------------------------------- 02428 AFE_ADCGAINGN1P5 Pos/Masks Description 02429 ------------------------------------------------------------------------------------------------------------------------- */ 02430 #define BITP_AFE_ADCGAINGN1P5_VALUE 0 /* Gain Calibration PGA Gain 1.5x */ 02431 #define BITM_AFE_ADCGAINGN1P5_VALUE 0x00007FFF /* Gain Calibration PGA Gain 1.5x */ 02432 02433 /* ------------------------------------------------------------------------------------------------------------------------- 02434 AFE_ADCGAINGN2 Pos/Masks Description 02435 ------------------------------------------------------------------------------------------------------------------------- */ 02436 #define BITP_AFE_ADCGAINGN2_VALUE 0 /* Gain Calibration PGA Gain 2x */ 02437 #define BITM_AFE_ADCGAINGN2_VALUE 0x00007FFF /* Gain Calibration PGA Gain 2x */ 02438 02439 /* ------------------------------------------------------------------------------------------------------------------------- 02440 AFE_ADCGAINGN4 Pos/Masks Description 02441 ------------------------------------------------------------------------------------------------------------------------- */ 02442 #define BITP_AFE_ADCGAINGN4_VALUE 0 /* Gain Calibration PGA Gain 4x */ 02443 #define BITM_AFE_ADCGAINGN4_VALUE 0x00007FFF /* Gain Calibration PGA Gain 4x */ 02444 02445 /* ------------------------------------------------------------------------------------------------------------------------- 02446 AFE_ADCPGAOFFSETCANCEL Pos/Masks Description 02447 ------------------------------------------------------------------------------------------------------------------------- */ 02448 #define BITP_AFE_ADCPGAOFFSETCANCEL_OFFSETCANCEL 0 /* Offset Cancellation */ 02449 #define BITM_AFE_ADCPGAOFFSETCANCEL_OFFSETCANCEL 0x00007FFF /* Offset Cancellation */ 02450 02451 /* ------------------------------------------------------------------------------------------------------------------------- 02452 AFE_ADCGNHSTIA Pos/Masks Description 02453 ------------------------------------------------------------------------------------------------------------------------- */ 02454 #define BITP_AFE_ADCGNHSTIA_VALUE 0 /* Gain Error Calibration HS TIA Channel */ 02455 #define BITM_AFE_ADCGNHSTIA_VALUE 0x00007FFF /* Gain Error Calibration HS TIA Channel */ 02456 02457 /* ------------------------------------------------------------------------------------------------------------------------- 02458 AFE_ADCOFFSETLPTIA0 Pos/Masks Description 02459 ------------------------------------------------------------------------------------------------------------------------- */ 02460 #define BITP_AFE_ADCOFFSETLPTIA0_VALUE 0 /* Offset Calibration for ULP-TIA0 */ 02461 #define BITM_AFE_ADCOFFSETLPTIA0_VALUE 0x00007FFF /* Offset Calibration for ULP-TIA0 */ 02462 02463 /* ------------------------------------------------------------------------------------------------------------------------- 02464 AFE_ADCGNLPTIA0 Pos/Masks Description 02465 ------------------------------------------------------------------------------------------------------------------------- */ 02466 #define BITP_AFE_ADCGNLPTIA0_VALUE 0 /* Gain Error Calibration ULPTIA0 */ 02467 #define BITM_AFE_ADCGNLPTIA0_VALUE 0x00007FFF /* Gain Error Calibration ULPTIA0 */ 02468 02469 /* ------------------------------------------------------------------------------------------------------------------------- 02470 AFE_ADCPGAGN4OFCAL Pos/Masks Description 02471 ------------------------------------------------------------------------------------------------------------------------- */ 02472 #define BITP_AFE_ADCPGAGN4OFCAL_ADCGAINAUX 0 /* DC Calibration Gain=4 */ 02473 #define BITM_AFE_ADCPGAGN4OFCAL_ADCGAINAUX 0x00007FFF /* DC Calibration Gain=4 */ 02474 02475 /* ------------------------------------------------------------------------------------------------------------------------- 02476 AFE_ADCGAINGN9 Pos/Masks Description 02477 ------------------------------------------------------------------------------------------------------------------------- */ 02478 #define BITP_AFE_ADCGAINGN9_VALUE 0 /* Gain Calibration PGA Gain 9x */ 02479 #define BITM_AFE_ADCGAINGN9_VALUE 0x00007FFF /* Gain Calibration PGA Gain 9x */ 02480 02481 /* ------------------------------------------------------------------------------------------------------------------------- 02482 AFE_ADCOFFSETEMPSENS1 Pos/Masks Description 02483 ------------------------------------------------------------------------------------------------------------------------- */ 02484 #define BITP_AFE_ADCOFFSETEMPSENS1_VALUE 0 /* Offset Calibration Temp Sensor */ 02485 #define BITM_AFE_ADCOFFSETEMPSENS1_VALUE 0x00007FFF /* Offset Calibration Temp Sensor */ 02486 02487 /* ------------------------------------------------------------------------------------------------------------------------- 02488 AFE_ADCGAINDIOTEMPSENS Pos/Masks Description 02489 ------------------------------------------------------------------------------------------------------------------------- */ 02490 #define BITP_AFE_ADCGAINDIOTEMPSENS_VALUE 0 /* Gain Calibration for Diode Temp Sensor */ 02491 #define BITM_AFE_ADCGAINDIOTEMPSENS_VALUE 0x00007FFF /* Gain Calibration for Diode Temp Sensor */ 02492 02493 /* ------------------------------------------------------------------------------------------------------------------------- 02494 AFE_DACOFFSETATTENHP Pos/Masks Description 02495 ------------------------------------------------------------------------------------------------------------------------- */ 02496 #define BITP_AFE_DACOFFSETATTENHP_VALUE 0 /* DAC Offset Correction Factor */ 02497 #define BITM_AFE_DACOFFSETATTENHP_VALUE 0x00000FFF /* DAC Offset Correction Factor */ 02498 02499 /* ------------------------------------------------------------------------------------------------------------------------- 02500 AFE_DACOFFSETHP Pos/Masks Description 02501 ------------------------------------------------------------------------------------------------------------------------- */ 02502 #define BITP_AFE_DACOFFSETHP_VALUE 0 /* DAC Offset Correction Factor */ 02503 #define BITM_AFE_DACOFFSETHP_VALUE 0x00000FFF /* DAC Offset Correction Factor */ 02504 02505 /* ------------------------------------------------------------------------------------------------------------------------- 02506 AFE_ADCOFFSETLPTIA1 Pos/Masks Description 02507 ------------------------------------------------------------------------------------------------------------------------- */ 02508 #define BITP_AFE_ADCOFFSETLPTIA1_VALUE 0 /* Offset Calibration for ULP-TIA1 */ 02509 #define BITM_AFE_ADCOFFSETLPTIA1_VALUE (_ADI_MSK_3(0x00007FFF,0x00007FFFUL, uint32_t )) /* Offset Calibration for ULP-TIA1 */ 02510 02511 /* ------------------------------------------------------------------------------------------------------------------------- 02512 AFE_ADCGNLPTIA1 Pos/Masks Description 02513 ------------------------------------------------------------------------------------------------------------------------- */ 02514 #define BITP_AFE_ADCGNLPTIA1_ULPTIA1GN 0 /* Gain Calibration ULP-TIA1 */ 02515 #define BITM_AFE_ADCGNLPTIA1_ULPTIA1GN 0x00007FFF /* Gain Calibration ULP-TIA1 */ 02516 02517 /* ------------------------------------------------------------------------------------------------------------------------- 02518 AFE_ADCOFFSETGN2 Pos/Masks Description 02519 ------------------------------------------------------------------------------------------------------------------------- */ 02520 #define BITP_AFE_ADCOFFSETGN2_VALUE 0 /* Offset Calibration Auxiliary Channel (PGA Gain =2) */ 02521 #define BITM_AFE_ADCOFFSETGN2_VALUE 0x00007FFF /* Offset Calibration Auxiliary Channel (PGA Gain =2) */ 02522 02523 /* ------------------------------------------------------------------------------------------------------------------------- 02524 AFE_ADCOFFSETGN1P5 Pos/Masks Description 02525 ------------------------------------------------------------------------------------------------------------------------- */ 02526 #define BITP_AFE_ADCOFFSETGN1P5_VALUE 0 /* Offset Calibration Gain1.5 */ 02527 #define BITM_AFE_ADCOFFSETGN1P5_VALUE 0x00007FFF /* Offset Calibration Gain1.5 */ 02528 02529 /* ------------------------------------------------------------------------------------------------------------------------- 02530 AFE_ADCOFFSETGN9 Pos/Masks Description 02531 ------------------------------------------------------------------------------------------------------------------------- */ 02532 #define BITP_AFE_ADCOFFSETGN9_VALUE 0 /* Offset Calibration Gain9 */ 02533 #define BITM_AFE_ADCOFFSETGN9_VALUE 0x00007FFF /* Offset Calibration Gain9 */ 02534 02535 /* ------------------------------------------------------------------------------------------------------------------------- 02536 AFE_ADCOFFSETGN4 Pos/Masks Description 02537 ------------------------------------------------------------------------------------------------------------------------- */ 02538 #define BITP_AFE_ADCOFFSETGN4_VALUE 0 /* Offset Calibration Gain4 */ 02539 #define BITM_AFE_ADCOFFSETGN4_VALUE 0x00007FFF /* Offset Calibration Gain4 */ 02540 02541 /* ------------------------------------------------------------------------------------------------------------------------- 02542 AFE_PMBW Pos/Masks Description 02543 ------------------------------------------------------------------------------------------------------------------------- */ 02544 #define BITP_AFE_PMBW_SYSBW 2 /* Configure System Bandwidth */ 02545 #define BITP_AFE_PMBW_SYSHP 0 /* Set High Speed DAC and ADC in High Power Mode */ 02546 #define BITM_AFE_PMBW_SYSBW 0x0000000C /* Configure System Bandwidth */ 02547 #define BITM_AFE_PMBW_SYSHP 0x00000001 /* Set High Speed DAC and ADC in High Power Mode */ 02548 #define ENUM_AFE_PMBW_BWNA 0x00000000 /* SYSBW: no action for system configuration */ 02549 #define ENUM_AFE_PMBW_BW50 0x00000004 /* SYSBW: 50kHz -3dB bandwidth */ 02550 #define ENUM_AFE_PMBW_BW100 0x00000008 /* SYSBW: 100kHz -3dB bandwidth */ 02551 #define ENUM_AFE_PMBW_BW250 0x0000000C /* SYSBW: 250kHz -3dB bandwidth */ 02552 #define ENUM_AFE_PMBW_LP 0x00000000 /* SYSHP: LP mode */ 02553 #define ENUM_AFE_PMBW_HP 0x00000001 /* SYSHP: HP mode */ 02554 02555 /* ------------------------------------------------------------------------------------------------------------------------- 02556 AFE_SWMUX Pos/Masks Description 02557 ------------------------------------------------------------------------------------------------------------------------- */ 02558 #define BITP_AFE_SWMUX_CMMUX 3 /* CM Resistor Select for Ain2, Ain3 */ 02559 #define BITM_AFE_SWMUX_CMMUX 0x00000008 /* CM Resistor Select for Ain2, Ain3 */ 02560 02561 /* ------------------------------------------------------------------------------------------------------------------------- 02562 AFE_AFE_TEMPSEN_DIO Pos/Masks Description 02563 ------------------------------------------------------------------------------------------------------------------------- */ 02564 #define BITP_AFE_AFE_TEMPSEN_DIO_TSDIO_PD 17 /* Power Down Control */ 02565 #define BITP_AFE_AFE_TEMPSEN_DIO_TSDIO_EN 16 /* Test Signal Enable */ 02566 #define BITP_AFE_AFE_TEMPSEN_DIO_TSDIO_CON 0 /* Bias Current Selection */ 02567 #define BITM_AFE_AFE_TEMPSEN_DIO_TSDIO_PD 0x00020000 /* Power Down Control */ 02568 #define BITM_AFE_AFE_TEMPSEN_DIO_TSDIO_EN 0x00010000 /* Test Signal Enable */ 02569 #define BITM_AFE_AFE_TEMPSEN_DIO_TSDIO_CON 0x0000FFFF /* Bias Current Selection */ 02570 02571 /* ------------------------------------------------------------------------------------------------------------------------- 02572 AFE_ADCBUFCON Pos/Masks Description 02573 ------------------------------------------------------------------------------------------------------------------------- */ 02574 #define BITP_AFE_ADCBUFCON_AMPDIS 4 /* Disable OpAmp. */ 02575 #define BITP_AFE_ADCBUFCON_CHOPDIS 0 /* Disable Chop */ 02576 #define BITM_AFE_ADCBUFCON_AMPDIS 0x000001F0 /* Disable OpAmp. */ 02577 #define BITM_AFE_ADCBUFCON_CHOPDIS 0x0000000F /* Disable Chop */ 02578 02579 02580 /* ============================================================================================================================ 02581 Interrupt Controller Register Map 02582 ============================================================================================================================ */ 02583 02584 /* ============================================================================================================================ 02585 INTC 02586 ============================================================================================================================ */ 02587 #define REG_INTC_INTCPOL_RESET 0x00000000 /* Reset Value for INTCPOL */ 02588 #define REG_INTC_INTCPOL 0x00003000 /* INTC Interrupt Polarity Register */ 02589 #define REG_INTC_INTCCLR_RESET 0x00000000 /* Reset Value for INTCCLR */ 02590 #define REG_INTC_INTCCLR 0x00003004 /* INTC Interrupt Clear Register */ 02591 #define REG_INTC_INTCSEL0_RESET 0x00002000 /* Reset Value for INTCSEL0 */ 02592 #define REG_INTC_INTCSEL0 0x00003008 /* INTC INT0 Select Register */ 02593 #define REG_INTC_INTCSEL1_RESET 0x00000000 /* Reset Value for INTCSEL1 */ 02594 #define REG_INTC_INTCSEL1 0x0000300C /* INTC INT1 Select Register */ 02595 #define REG_INTC_INTCFLAG0_RESET 0x00000000 /* Reset Value for INTCFLAG0 */ 02596 #define REG_INTC_INTCFLAG0 0x00003010 /* INTC INT0 FLAG Register */ 02597 #define REG_INTC_INTCFLAG1_RESET 0x00000000 /* Reset Value for INTCFLAG1 */ 02598 #define REG_INTC_INTCFLAG1 0x00003014 /* INTC INT1 FLAG Register */ 02599 02600 /* ============================================================================================================================ 02601 INTC Register BitMasks, Positions & Enumerations 02602 ============================================================================================================================ */ 02603 /* ------------------------------------------------------------------------------------------------------------------------- 02604 INTC_INTCPOL Pos/Masks Description 02605 ------------------------------------------------------------------------------------------------------------------------- */ 02606 #define BITP_INTC_INTCPOL_INTPOL 0 02607 #define BITM_INTC_INTCPOL_INTPOL 0x00000001 02608 02609 /* ------------------------------------------------------------------------------------------------------------------------- 02610 INTC_INTCCLR Pos/Masks Description 02611 ------------------------------------------------------------------------------------------------------------------------- */ 02612 #define BITP_INTC_INTCCLR_INTCLR31 31 02613 #define BITP_INTC_INTCCLR_INTCLR30 30 02614 #define BITP_INTC_INTCCLR_INTCLR29 29 02615 #define BITP_INTC_INTCCLR_INTCLR28 28 02616 #define BITP_INTC_INTCCLR_INTCLR27 27 02617 #define BITP_INTC_INTCCLR_INTCLR26 26 02618 #define BITP_INTC_INTCCLR_INTCLR25 25 02619 #define BITP_INTC_INTCCLR_INTCLR24 24 02620 #define BITP_INTC_INTCCLR_INTCLR23 23 02621 #define BITP_INTC_INTCCLR_INTCLR22 22 02622 #define BITP_INTC_INTCCLR_INTCLR21 21 02623 #define BITP_INTC_INTCCLR_INTCLR20 20 02624 #define BITP_INTC_INTCCLR_INTCLR19 19 02625 #define BITP_INTC_INTCCLR_INTCLR18 18 02626 #define BITP_INTC_INTCCLR_INTCLR17 17 02627 #define BITP_INTC_INTCCLR_INTCLR16 16 02628 #define BITP_INTC_INTCCLR_INTCLR15 15 02629 #define BITP_INTC_INTCCLR_INTCLR14 14 02630 #define BITP_INTC_INTCCLR_INTCLR13 13 02631 #define BITP_INTC_INTCCLR_INTCLR12 12 /* Custom IRQ 3. Write 1 to clear. */ 02632 #define BITP_INTC_INTCCLR_INTCLR11 11 /* Custom IRQ 2. Write 1 to clear. */ 02633 #define BITP_INTC_INTCCLR_INTCLR10 10 /* Custom IRQ 1. Write 1 to clear. */ 02634 #define BITP_INTC_INTCCLR_INTCLR9 9 /* Custom IRQ 0. Write 1 to clear */ 02635 #define BITP_INTC_INTCCLR_INTCLR8 8 02636 #define BITP_INTC_INTCCLR_INTCLR7 7 02637 #define BITP_INTC_INTCCLR_INTCLR6 6 02638 #define BITP_INTC_INTCCLR_INTCLR5 5 02639 #define BITP_INTC_INTCCLR_INTCLR4 4 02640 #define BITP_INTC_INTCCLR_INTCLR3 3 02641 #define BITP_INTC_INTCCLR_INTCLR2 2 02642 #define BITP_INTC_INTCCLR_INTCLR1 1 02643 #define BITP_INTC_INTCCLR_INTCLR0 0 02644 #define BITM_INTC_INTCCLR_INTCLR31 0x80000000 02645 #define BITM_INTC_INTCCLR_INTCLR30 0x40000000 02646 #define BITM_INTC_INTCCLR_INTCLR29 0x20000000 02647 #define BITM_INTC_INTCCLR_INTCLR28 0x10000000 02648 #define BITM_INTC_INTCCLR_INTCLR27 0x08000000 02649 #define BITM_INTC_INTCCLR_INTCLR26 0x04000000 02650 #define BITM_INTC_INTCCLR_INTCLR25 0x02000000 02651 #define BITM_INTC_INTCCLR_INTCLR24 0x01000000 02652 #define BITM_INTC_INTCCLR_INTCLR23 0x00800000 02653 #define BITM_INTC_INTCCLR_INTCLR22 0x00400000 02654 #define BITM_INTC_INTCCLR_INTCLR21 0x00200000 02655 #define BITM_INTC_INTCCLR_INTCLR20 0x00100000 02656 #define BITM_INTC_INTCCLR_INTCLR19 0x00080000 02657 #define BITM_INTC_INTCCLR_INTCLR18 0x00040000 02658 #define BITM_INTC_INTCCLR_INTCLR17 0x00020000 02659 #define BITM_INTC_INTCCLR_INTCLR16 0x00010000 02660 #define BITM_INTC_INTCCLR_INTCLR15 0x00008000 02661 #define BITM_INTC_INTCCLR_INTCLR14 0x00004000 02662 #define BITM_INTC_INTCCLR_INTCLR13 0x00002000 02663 #define BITM_INTC_INTCCLR_INTCLR12 0x00001000 /* Custom IRQ 3. Write 1 to clear. */ 02664 #define BITM_INTC_INTCCLR_INTCLR11 0x00000800 /* Custom IRQ 2. Write 1 to clear. */ 02665 #define BITM_INTC_INTCCLR_INTCLR10 0x00000400 /* Custom IRQ 1. Write 1 to clear. */ 02666 #define BITM_INTC_INTCCLR_INTCLR9 0x00000200 /* Custom IRQ 0. Write 1 to clear */ 02667 #define BITM_INTC_INTCCLR_INTCLR8 0x00000100 02668 #define BITM_INTC_INTCCLR_INTCLR7 0x00000080 02669 #define BITM_INTC_INTCCLR_INTCLR6 0x00000040 02670 #define BITM_INTC_INTCCLR_INTCLR5 0x00000020 02671 #define BITM_INTC_INTCCLR_INTCLR4 0x00000010 02672 #define BITM_INTC_INTCCLR_INTCLR3 0x00000008 02673 #define BITM_INTC_INTCCLR_INTCLR2 0x00000004 02674 #define BITM_INTC_INTCCLR_INTCLR1 0x00000002 02675 #define BITM_INTC_INTCCLR_INTCLR0 0x00000001 02676 02677 /* ------------------------------------------------------------------------------------------------------------------------- 02678 INTC_INTCSEL0 Pos/Masks Description 02679 ------------------------------------------------------------------------------------------------------------------------- */ 02680 #define BITP_INTC_INTCSEL0_INTSEL31 31 02681 #define BITP_INTC_INTCSEL0_INTSEL30 30 02682 #define BITP_INTC_INTCSEL0_INTSEL29 29 02683 #define BITP_INTC_INTCSEL0_INTSEL28 28 02684 #define BITP_INTC_INTCSEL0_INTSEL27 27 02685 #define BITP_INTC_INTCSEL0_INTSEL26 26 02686 #define BITP_INTC_INTCSEL0_INTSEL25 25 02687 #define BITP_INTC_INTCSEL0_INTSEL24 24 02688 #define BITP_INTC_INTCSEL0_INTSEL23 23 02689 #define BITP_INTC_INTCSEL0_INTSEL22 22 02690 #define BITP_INTC_INTCSEL0_INTSEL21 21 02691 #define BITP_INTC_INTCSEL0_INTSEL20 20 02692 #define BITP_INTC_INTCSEL0_INTSEL19 19 02693 #define BITP_INTC_INTCSEL0_INTSEL18 18 02694 #define BITP_INTC_INTCSEL0_INTSEL17 17 02695 #define BITP_INTC_INTCSEL0_INTSEL16 16 02696 #define BITP_INTC_INTCSEL0_INTSEL15 15 02697 #define BITP_INTC_INTCSEL0_INTSEL14 14 02698 #define BITP_INTC_INTCSEL0_INTSEL13 13 02699 #define BITP_INTC_INTCSEL0_INTSEL12 12 /* Custom IRQ 3 Enable */ 02700 #define BITP_INTC_INTCSEL0_INTSEL11 11 /* Custom IRQ 2 Enable */ 02701 #define BITP_INTC_INTCSEL0_INTSEL10 10 /* Custom IRQ 1 Enable */ 02702 #define BITP_INTC_INTCSEL0_INTSEL9 9 /* Custom IRQ 0 Enable */ 02703 #define BITP_INTC_INTCSEL0_INTSEL8 8 02704 #define BITP_INTC_INTCSEL0_INTSEL7 7 02705 #define BITP_INTC_INTCSEL0_INTSEL6 6 02706 #define BITP_INTC_INTCSEL0_INTSEL5 5 02707 #define BITP_INTC_INTCSEL0_INTSEL4 4 02708 #define BITP_INTC_INTCSEL0_INTSEL3 3 02709 #define BITP_INTC_INTCSEL0_INTSEL2 2 02710 #define BITP_INTC_INTCSEL0_INTSEL1 1 02711 #define BITP_INTC_INTCSEL0_INTSEL0 0 02712 #define BITM_INTC_INTCSEL0_INTSEL31 0x80000000 02713 #define BITM_INTC_INTCSEL0_INTSEL30 0x40000000 02714 #define BITM_INTC_INTCSEL0_INTSEL29 0x20000000 02715 #define BITM_INTC_INTCSEL0_INTSEL28 0x10000000 02716 #define BITM_INTC_INTCSEL0_INTSEL27 0x08000000 02717 #define BITM_INTC_INTCSEL0_INTSEL26 0x04000000 02718 #define BITM_INTC_INTCSEL0_INTSEL25 0x02000000 02719 #define BITM_INTC_INTCSEL0_INTSEL24 0x01000000 02720 #define BITM_INTC_INTCSEL0_INTSEL23 0x00800000 02721 #define BITM_INTC_INTCSEL0_INTSEL22 0x00400000 02722 #define BITM_INTC_INTCSEL0_INTSEL21 0x00200000 02723 #define BITM_INTC_INTCSEL0_INTSEL20 0x00100000 02724 #define BITM_INTC_INTCSEL0_INTSEL19 0x00080000 02725 #define BITM_INTC_INTCSEL0_INTSEL18 0x00040000 02726 #define BITM_INTC_INTCSEL0_INTSEL17 0x00020000 02727 #define BITM_INTC_INTCSEL0_INTSEL16 0x00010000 02728 #define BITM_INTC_INTCSEL0_INTSEL15 0x00008000 02729 #define BITM_INTC_INTCSEL0_INTSEL14 0x00004000 02730 #define BITM_INTC_INTCSEL0_INTSEL13 0x00002000 02731 #define BITM_INTC_INTCSEL0_INTSEL12 0x00001000 /* Custom IRQ 3 Enable */ 02732 #define BITM_INTC_INTCSEL0_INTSEL11 0x00000800 /* Custom IRQ 2 Enable */ 02733 #define BITM_INTC_INTCSEL0_INTSEL10 0x00000400 /* Custom IRQ 1 Enable */ 02734 #define BITM_INTC_INTCSEL0_INTSEL9 0x00000200 /* Custom IRQ 0 Enable */ 02735 #define BITM_INTC_INTCSEL0_INTSEL8 0x00000100 02736 #define BITM_INTC_INTCSEL0_INTSEL7 0x00000080 02737 #define BITM_INTC_INTCSEL0_INTSEL6 0x00000040 02738 #define BITM_INTC_INTCSEL0_INTSEL5 0x00000020 02739 #define BITM_INTC_INTCSEL0_INTSEL4 0x00000010 02740 #define BITM_INTC_INTCSEL0_INTSEL3 0x00000008 02741 #define BITM_INTC_INTCSEL0_INTSEL2 0x00000004 02742 #define BITM_INTC_INTCSEL0_INTSEL1 0x00000002 02743 #define BITM_INTC_INTCSEL0_INTSEL0 0x00000001 02744 02745 /* ------------------------------------------------------------------------------------------------------------------------- 02746 INTC_INTCSEL1 Pos/Masks Description 02747 ------------------------------------------------------------------------------------------------------------------------- */ 02748 #define BITP_INTC_INTCSEL1_INTSEL31 31 02749 #define BITP_INTC_INTCSEL1_INTSEL30 30 02750 #define BITP_INTC_INTCSEL1_INTSEL29 29 02751 #define BITP_INTC_INTCSEL1_INTSEL28 28 02752 #define BITP_INTC_INTCSEL1_INTSEL27 27 02753 #define BITP_INTC_INTCSEL1_INTSEL26 26 02754 #define BITP_INTC_INTCSEL1_INTSEL25 25 02755 #define BITP_INTC_INTCSEL1_INTSEL24 24 02756 #define BITP_INTC_INTCSEL1_INTSEL23 23 02757 #define BITP_INTC_INTCSEL1_INTSEL22 22 02758 #define BITP_INTC_INTCSEL1_INTSEL21 21 02759 #define BITP_INTC_INTCSEL1_INTSEL20 20 02760 #define BITP_INTC_INTCSEL1_INTSEL19 19 02761 #define BITP_INTC_INTCSEL1_INTSEL18 18 02762 #define BITP_INTC_INTCSEL1_INTSEL17 17 02763 #define BITP_INTC_INTCSEL1_INTSEL16 16 02764 #define BITP_INTC_INTCSEL1_INTSEL15 15 02765 #define BITP_INTC_INTCSEL1_INTSEL14 14 02766 #define BITP_INTC_INTCSEL1_INTSEL13 13 02767 #define BITP_INTC_INTCSEL1_INTSEL12 12 /* Custom IRQ 3 Enable */ 02768 #define BITP_INTC_INTCSEL1_INTSEL11 11 /* Custom IRQ 2 Enable */ 02769 #define BITP_INTC_INTCSEL1_INTSEL10 10 /* Custom IRQ 1 Enable */ 02770 #define BITP_INTC_INTCSEL1_INTSEL9 9 /* Custom IRQ 0 Enable */ 02771 #define BITP_INTC_INTCSEL1_INTSEL8 8 02772 #define BITP_INTC_INTCSEL1_INTSEL7 7 02773 #define BITP_INTC_INTCSEL1_INTSEL6 6 02774 #define BITP_INTC_INTCSEL1_INTSEL5 5 02775 #define BITP_INTC_INTCSEL1_INTSEL4 4 02776 #define BITP_INTC_INTCSEL1_INTSEL3 3 02777 #define BITP_INTC_INTCSEL1_INTSEL2 2 02778 #define BITP_INTC_INTCSEL1_INTSEL1 1 02779 #define BITP_INTC_INTCSEL1_INTSEL0 0 02780 #define BITM_INTC_INTCSEL1_INTSEL31 0x80000000 02781 #define BITM_INTC_INTCSEL1_INTSEL30 0x40000000 02782 #define BITM_INTC_INTCSEL1_INTSEL29 0x20000000 02783 #define BITM_INTC_INTCSEL1_INTSEL28 0x10000000 02784 #define BITM_INTC_INTCSEL1_INTSEL27 0x08000000 02785 #define BITM_INTC_INTCSEL1_INTSEL26 0x04000000 02786 #define BITM_INTC_INTCSEL1_INTSEL25 0x02000000 02787 #define BITM_INTC_INTCSEL1_INTSEL24 0x01000000 02788 #define BITM_INTC_INTCSEL1_INTSEL23 0x00800000 02789 #define BITM_INTC_INTCSEL1_INTSEL22 0x00400000 02790 #define BITM_INTC_INTCSEL1_INTSEL21 0x00200000 02791 #define BITM_INTC_INTCSEL1_INTSEL20 0x00100000 02792 #define BITM_INTC_INTCSEL1_INTSEL19 0x00080000 02793 #define BITM_INTC_INTCSEL1_INTSEL18 0x00040000 02794 #define BITM_INTC_INTCSEL1_INTSEL17 0x00020000 02795 #define BITM_INTC_INTCSEL1_INTSEL16 0x00010000 02796 #define BITM_INTC_INTCSEL1_INTSEL15 0x00008000 02797 #define BITM_INTC_INTCSEL1_INTSEL14 0x00004000 02798 #define BITM_INTC_INTCSEL1_INTSEL13 0x00002000 02799 #define BITM_INTC_INTCSEL1_INTSEL12 0x00001000 /* Custom IRQ 3 Enable */ 02800 #define BITM_INTC_INTCSEL1_INTSEL11 0x00000800 /* Custom IRQ 2 Enable */ 02801 #define BITM_INTC_INTCSEL1_INTSEL10 0x00000400 /* Custom IRQ 1 Enable */ 02802 #define BITM_INTC_INTCSEL1_INTSEL9 0x00000200 /* Custom IRQ 0 Enable */ 02803 #define BITM_INTC_INTCSEL1_INTSEL8 0x00000100 02804 #define BITM_INTC_INTCSEL1_INTSEL7 0x00000080 02805 #define BITM_INTC_INTCSEL1_INTSEL6 0x00000040 02806 #define BITM_INTC_INTCSEL1_INTSEL5 0x00000020 02807 #define BITM_INTC_INTCSEL1_INTSEL4 0x00000010 02808 #define BITM_INTC_INTCSEL1_INTSEL3 0x00000008 02809 #define BITM_INTC_INTCSEL1_INTSEL2 0x00000004 02810 #define BITM_INTC_INTCSEL1_INTSEL1 0x00000002 02811 #define BITM_INTC_INTCSEL1_INTSEL0 0x00000001 02812 02813 /* ------------------------------------------------------------------------------------------------------------------------- 02814 INTC_INTCFLAG0 Pos/Masks Description 02815 ------------------------------------------------------------------------------------------------------------------------- */ 02816 #define BITP_INTC_INTCFLAG0_FLAG31 31 02817 #define BITP_INTC_INTCFLAG0_FLAG30 30 02818 #define BITP_INTC_INTCFLAG0_FLAG29 29 02819 #define BITP_INTC_INTCFLAG0_FLAG28 28 02820 #define BITP_INTC_INTCFLAG0_FLAG27 27 02821 #define BITP_INTC_INTCFLAG0_FLAG26 26 02822 #define BITP_INTC_INTCFLAG0_FLAG25 25 02823 #define BITP_INTC_INTCFLAG0_FLAG24 24 02824 #define BITP_INTC_INTCFLAG0_FLAG23 23 02825 #define BITP_INTC_INTCFLAG0_FLAG22 22 02826 #define BITP_INTC_INTCFLAG0_FLAG21 21 02827 #define BITP_INTC_INTCFLAG0_FLAG20 20 02828 #define BITP_INTC_INTCFLAG0_FLAG19 19 02829 #define BITP_INTC_INTCFLAG0_FLAG18 18 02830 #define BITP_INTC_INTCFLAG0_FLAG17 17 02831 #define BITP_INTC_INTCFLAG0_FLAG16 16 02832 #define BITP_INTC_INTCFLAG0_FLAG15 15 02833 #define BITP_INTC_INTCFLAG0_FLAG14 14 02834 #define BITP_INTC_INTCFLAG0_FLAG13 13 02835 #define BITP_INTC_INTCFLAG0_FLAG12 12 /* Custom IRQ 3 Status */ 02836 #define BITP_INTC_INTCFLAG0_FLAG11 11 /* Custom IRQ 2 Status */ 02837 #define BITP_INTC_INTCFLAG0_FLAG10 10 /* Custom IRQ 1 Status */ 02838 #define BITP_INTC_INTCFLAG0_FLAG9 9 /* Custom IRQ 0 Status */ 02839 #define BITP_INTC_INTCFLAG0_FLAG8 8 /* Variance IRQ status. */ 02840 #define BITP_INTC_INTCFLAG0_FLAG7 7 02841 #define BITP_INTC_INTCFLAG0_FLAG6 6 02842 #define BITP_INTC_INTCFLAG0_FLAG5 5 02843 #define BITP_INTC_INTCFLAG0_FLAG4 4 02844 #define BITP_INTC_INTCFLAG0_FLAG3 3 02845 #define BITP_INTC_INTCFLAG0_FLAG2 2 02846 #define BITP_INTC_INTCFLAG0_FLAG1 1 02847 #define BITP_INTC_INTCFLAG0_FLAG0 0 02848 #define BITM_INTC_INTCFLAG0_FLAG31 0x80000000 02849 #define BITM_INTC_INTCFLAG0_FLAG30 0x40000000 02850 #define BITM_INTC_INTCFLAG0_FLAG29 0x20000000 02851 #define BITM_INTC_INTCFLAG0_FLAG28 0x10000000 02852 #define BITM_INTC_INTCFLAG0_FLAG27 0x08000000 02853 #define BITM_INTC_INTCFLAG0_FLAG26 0x04000000 02854 #define BITM_INTC_INTCFLAG0_FLAG25 0x02000000 02855 #define BITM_INTC_INTCFLAG0_FLAG24 0x01000000 02856 #define BITM_INTC_INTCFLAG0_FLAG23 0x00800000 02857 #define BITM_INTC_INTCFLAG0_FLAG22 0x00400000 02858 #define BITM_INTC_INTCFLAG0_FLAG21 0x00200000 02859 #define BITM_INTC_INTCFLAG0_FLAG20 0x00100000 02860 #define BITM_INTC_INTCFLAG0_FLAG19 0x00080000 02861 #define BITM_INTC_INTCFLAG0_FLAG18 0x00040000 02862 #define BITM_INTC_INTCFLAG0_FLAG17 0x00020000 02863 #define BITM_INTC_INTCFLAG0_FLAG16 0x00010000 02864 #define BITM_INTC_INTCFLAG0_FLAG15 0x00008000 02865 #define BITM_INTC_INTCFLAG0_FLAG14 0x00004000 02866 #define BITM_INTC_INTCFLAG0_FLAG13 0x00002000 02867 #define BITM_INTC_INTCFLAG0_FLAG12 0x00001000 /* Custom IRQ 3 Status */ 02868 #define BITM_INTC_INTCFLAG0_FLAG11 0x00000800 /* Custom IRQ 2 Status */ 02869 #define BITM_INTC_INTCFLAG0_FLAG10 0x00000400 /* Custom IRQ 1 Status */ 02870 #define BITM_INTC_INTCFLAG0_FLAG9 0x00000200 /* Custom IRQ 0 Status */ 02871 #define BITM_INTC_INTCFLAG0_FLAG8 0x00000100 /* Variance IRQ status. */ 02872 #define BITM_INTC_INTCFLAG0_FLAG7 0x00000080 02873 #define BITM_INTC_INTCFLAG0_FLAG6 0x00000040 02874 #define BITM_INTC_INTCFLAG0_FLAG5 0x00000020 02875 #define BITM_INTC_INTCFLAG0_FLAG4 0x00000010 02876 #define BITM_INTC_INTCFLAG0_FLAG3 0x00000008 02877 #define BITM_INTC_INTCFLAG0_FLAG2 0x00000004 02878 #define BITM_INTC_INTCFLAG0_FLAG1 0x00000002 02879 #define BITM_INTC_INTCFLAG0_FLAG0 0x00000001 02880 02881 /* ------------------------------------------------------------------------------------------------------------------------- 02882 INTC_INTCFLAG1 Pos/Masks Description 02883 ------------------------------------------------------------------------------------------------------------------------- */ 02884 #define BITP_INTC_INTCFLAG1_FLAG31 31 02885 #define BITP_INTC_INTCFLAG1_FLAG30 30 02886 #define BITP_INTC_INTCFLAG1_FLAG29 29 02887 #define BITP_INTC_INTCFLAG1_FLAG28 28 02888 #define BITP_INTC_INTCFLAG1_FLAG27 27 02889 #define BITP_INTC_INTCFLAG1_FLAG26 26 02890 #define BITP_INTC_INTCFLAG1_FLAG25 25 02891 #define BITP_INTC_INTCFLAG1_FLAG24 24 02892 #define BITP_INTC_INTCFLAG1_FLAG23 23 02893 #define BITP_INTC_INTCFLAG1_FLAG22 22 02894 #define BITP_INTC_INTCFLAG1_FLAG21 21 02895 #define BITP_INTC_INTCFLAG1_FLAG20 20 02896 #define BITP_INTC_INTCFLAG1_FLAG19 19 02897 #define BITP_INTC_INTCFLAG1_FLAG18 18 02898 #define BITP_INTC_INTCFLAG1_FLAG17 17 02899 #define BITP_INTC_INTCFLAG1_FLAG16 16 02900 #define BITP_INTC_INTCFLAG1_FLAG15 15 02901 #define BITP_INTC_INTCFLAG1_FLAG14 14 02902 #define BITP_INTC_INTCFLAG1_FLAG13 13 02903 #define BITP_INTC_INTCFLAG1_FLAG12 12 /* Custom IRQ 3 Status */ 02904 #define BITP_INTC_INTCFLAG1_FLAG11 11 /* Custom IRQ 2 Status */ 02905 #define BITP_INTC_INTCFLAG1_FLAG10 10 /* Custom IRQ 1 Status */ 02906 #define BITP_INTC_INTCFLAG1_FLAG9 9 /* Custom IRQ 0 Status */ 02907 #define BITP_INTC_INTCFLAG1_FLAG8 8 /* Variance IRQ status. */ 02908 #define BITP_INTC_INTCFLAG1_FLAG7 7 02909 #define BITP_INTC_INTCFLAG1_FLAG6 6 02910 #define BITP_INTC_INTCFLAG1_FLAG5 5 02911 #define BITP_INTC_INTCFLAG1_FLAG4 4 02912 #define BITP_INTC_INTCFLAG1_FLAG3 3 02913 #define BITP_INTC_INTCFLAG1_FLAG2 2 02914 #define BITP_INTC_INTCFLAG1_FLAG1 1 02915 #define BITP_INTC_INTCFLAG1_FLAG0 0 02916 #define BITM_INTC_INTCFLAG1_FLAG31 0x80000000 02917 #define BITM_INTC_INTCFLAG1_FLAG30 0x40000000 02918 #define BITM_INTC_INTCFLAG1_FLAG29 0x20000000 02919 #define BITM_INTC_INTCFLAG1_FLAG28 0x10000000 02920 #define BITM_INTC_INTCFLAG1_FLAG27 0x08000000 02921 #define BITM_INTC_INTCFLAG1_FLAG26 0x04000000 02922 #define BITM_INTC_INTCFLAG1_FLAG25 0x02000000 02923 #define BITM_INTC_INTCFLAG1_FLAG24 0x01000000 02924 #define BITM_INTC_INTCFLAG1_FLAG23 0x00800000 02925 #define BITM_INTC_INTCFLAG1_FLAG22 0x00400000 02926 #define BITM_INTC_INTCFLAG1_FLAG21 0x00200000 02927 #define BITM_INTC_INTCFLAG1_FLAG20 0x00100000 02928 #define BITM_INTC_INTCFLAG1_FLAG19 0x00080000 02929 #define BITM_INTC_INTCFLAG1_FLAG18 0x00040000 02930 #define BITM_INTC_INTCFLAG1_FLAG17 0x00020000 02931 #define BITM_INTC_INTCFLAG1_FLAG16 0x00010000 02932 #define BITM_INTC_INTCFLAG1_FLAG15 0x00008000 02933 #define BITM_INTC_INTCFLAG1_FLAG14 0x00004000 02934 #define BITM_INTC_INTCFLAG1_FLAG13 0x00002000 02935 #define BITM_INTC_INTCFLAG1_FLAG12 0x00001000 /* Custom IRQ 3 Status */ 02936 #define BITM_INTC_INTCFLAG1_FLAG11 0x00000800 /* Custom IRQ 2 Status */ 02937 #define BITM_INTC_INTCFLAG1_FLAG10 0x00000400 /* Custom IRQ 1 Status */ 02938 #define BITM_INTC_INTCFLAG1_FLAG9 0x00000200 /* Custom IRQ 0 Status */ 02939 #define BITM_INTC_INTCFLAG1_FLAG8 0x00000100 /* Variance IRQ status. */ 02940 #define BITM_INTC_INTCFLAG1_FLAG7 0x00000080 02941 #define BITM_INTC_INTCFLAG1_FLAG6 0x00000040 02942 #define BITM_INTC_INTCFLAG1_FLAG5 0x00000020 02943 #define BITM_INTC_INTCFLAG1_FLAG4 0x00000010 02944 #define BITM_INTC_INTCFLAG1_FLAG3 0x00000008 02945 #define BITM_INTC_INTCFLAG1_FLAG2 0x00000004 02946 #define BITM_INTC_INTCFLAG1_FLAG1 0x00000002 02947 #define BITM_INTC_INTCFLAG1_FLAG0 0x00000001 02948 /** 02949 * @} AD5940RegistersBitfields 02950 * @endcond 02951 * */ 02952 02953 /** 02954 * @addtogroup SPI_Block 02955 * @{ 02956 * @defgroup SPI_Block_Const 02957 * @{ 02958 * 02959 */ 02960 #define SPICMD_SETADDR 0x20 /**< set the register address that is going to operate. */ 02961 #define SPICMD_READREG 0x6d /**< command to read register */ 02962 #define SPICMD_WRITEREG 0x2d /**< command to write register */ 02963 #define SPICMD_READFIFO 0x5f /**< command to read FIFO */ 02964 /** 02965 * @} SPI_Block_Const 02966 * @} SPI_Block 02967 */ 02968 02969 /** 02970 * @addtogroup AFE_Control 02971 * @{ 02972 * */ 02973 02974 /** 02975 * @defgroup AFE_Control_Const 02976 * @{ 02977 * */ 02978 02979 /** 02980 * @defgroup AFEINTC_Const 02981 * @brief AD5940 has two interrupt controller INTC0 and INTC1. Both of them have ability to generate interrupt signal from GPIO. 02982 * @{ 02983 * */ 02984 /* AFE Interrupt controller selection */ 02985 #define AFEINTC_0 0 /**< Interrupt controller 0 */ 02986 #define AFEINTC_1 1 /**< Interrupt controller 1 */ 02987 /** @} */ 02988 02989 /** 02990 * @defgroup AFEINTC_SRC_Const 02991 * @brief Interrupt source selection. These sources are defined as bit mask. They are available for register INTCCLR, INTCSEL0/1, INTCFLAG0/1 02992 * @{ 02993 * */ 02994 #define AFEINTSRC_ADCRDY 0x00000001 /**< Bit0, ADC Result Ready Status */ 02995 #define AFEINTSRC_DFTRDY 0x00000002 /**< Bit1, DFT Result Ready Status */ 02996 #define AFEINTSRC_SINC2RDY 0x00000004 /**< Bit2, SINC2/Low Pass Filter Result Status */ 02997 #define AFEINTSRC_TEMPRDY 0x00000008 /**< Bit3, Temp Sensor Result Ready */ 02998 #define AFEINTSRC_ADCMINERR 0x00000010 /**< Bit4, ADC Minimum Value */ 02999 #define AFEINTSRC_ADCMAXERR 0x00000020 /**< Bit5, ADC Maximum Value */ 03000 #define AFEINTSRC_ADCDIFFERR 0x00000040 /**< Bit6, ADC Delta Ready */ 03001 #define AFEINTSRC_MEANRDY 0x00000080 /**< Bit7, Mean Result Ready */ 03002 #define AFEINTSRC_VARRDY 0x00000100 /**< Bit8, Variance Result Ready */ 03003 #define AFEINTSRC_CUSTOMINT0 0x00000200 /**< Bit9, Custom interrupt source 0. It happens when **sequencer** writes 1 to register AFEGENINTSTA.BIT0 */ 03004 #define AFEINTSRC_CUSTOMINT1 0x00000400 /**< Bit10, Custom interrupt source 1. It happens when **sequencer** writes 1 to register AFEGENINTSTA.BIT1*/ 03005 #define AFEINTSRC_CUSTOMINT2 0x00000800 /**< Bit11, Custom interrupt source 2. It happens when **sequencer** writes 1 to register AFEGENINTSTA.BIT2 */ 03006 #define AFEINTSRC_CUSTOMINT3 0x00001000 /**< Bit12, Custom interrupt source 3. It happens when **sequencer** writes 1 to register AFEGENINTSTA.BIT3 */ 03007 #define AFEINTSRC_BOOTLDDONE 0x00002000 /**< Bit13, OTP Boot Loading Done */ 03008 #define AFEINTSRC_WAKEUP 0x00004000 /**< Bit14, AFE Woken up*/ 03009 #define AFEINTSRC_ENDSEQ 0x00008000 /**< Bit15, End of Sequence Interrupt. */ 03010 #define AFEINTSRC_SEQTIMEOUT 0x00010000 /**< Bit16, Sequencer Timeout Command Finished. */ 03011 #define AFEINTSRC_SEQTIMEOUTERR 0x00020000 /**< Bit17, Sequencer Timeout Command Error. */ 03012 #define AFEINTSRC_CMDFIFOFULL 0x00040000 /**< Bit18, Command FIFO Full Interrupt. */ 03013 #define AFEINTSRC_CMDFIFOEMPTY 0x00080000 /**< Bit19, Command FIFO Empty */ 03014 #define AFEINTSRC_CMDFIFOTHRESH 0x00100000 /**< Bit20, Command FIFO Threshold Interrupt. */ 03015 #define AFEINTSRC_CMDFIFOOF 0x00200000 /**< Bit21, Command FIFO Overflow Interrupt. */ 03016 #define AFEINTSRC_CMDFIFOUF 0x00400000 /**< Bit22, Command FIFO Underflow Interrupt. */ 03017 #define AFEINTSRC_DATAFIFOFULL 0x00800000 /**< Bit23, Data FIFO Full Interrupt. */ 03018 #define AFEINTSRC_DATAFIFOEMPTY 0x01000000 /**< Bit24, Data FIFO Empty */ 03019 #define AFEINTSRC_DATAFIFOTHRESH 0x02000000 /**< Bit25, Data FIFO Threshold Interrupt. */ 03020 #define AFEINTSRC_DATAFIFOOF 0x04000000 /**< Bit26, Data FIFO Overflow Interrupt. */ 03021 #define AFEINTSRC_DATAFIFOUF 0x08000000 /**< Bit27, Data FIFO Underflow Interrupt. */ 03022 #define AFEINTSRC_WDTIRQ 0x10000000 /**< Bit28, WDT Timeout Interrupt. */ 03023 #define AFEINTSRC_CRC_OUTLIER 0x20000000 /**< Bit29, CRC interrupt for M355, Outlier Int for AD5940 */ 03024 #define AFEINTSRC_GPT0INT_SLPWUT 0x40000000 /**< Bit30, Gneral Pupose Timer0 IRQ for M355. Sleep or Wakeup Tiemr timeout for AD5940*/ 03025 #define AFEINTSRC_GPT1INT_TRYBRK 0x80000000 /**< Bit31, Gneral Pupose Timer1 IRQ for M355. Tried to Break IRQ for AD5940*/ 03026 #define AFEINTSRC_ALLINT 0xffffffff /**< mask of all interrupt */ 03027 /** @} */ 03028 03029 /** 03030 * @defgroup AFEPWR_Const 03031 * @brief AFE power mode. 03032 * @details It will set the whole analog system power mode include HSDAC, Excitation Buffer, HSTIA, ADC front-buffer etc. 03033 * @{ 03034 */ 03035 #define AFEPWR_LP 0 /**< Set AFE to Low Power mode. For signal <80kHz, use it. */ 03036 #define AFEPWR_HP 1 /**< Set AFE to High Power mode. For signal >80kHz, use it. */ 03037 /** 03038 * @} 03039 */ 03040 03041 /** 03042 * @defgroup AFEBW_Const 03043 * @brief AFE system bandwidth. 03044 * @details It will set the whole analog bandwidth include HSDAC, Excitation Buffer, HSTIA, ADC front-buffer etc. 03045 * @{ 03046 */ 03047 #define AFEBW_AUTOSET 0 /**< Set the bandwidth automatically based on WGFCW frequency word. */ 03048 #define AFEBW_50KHZ 1 /**< 50kHZ system bandwidth(DAC/ADC) */ 03049 #define AFEBW_100KHZ 2 /**< 100kHZ system bandwidth(DAC/ADC) */ 03050 #define AFEBW_250KHZ 3 /**< 250kHZ system bandwidth(DAC/ADC) */ 03051 /** 03052 * @} 03053 */ 03054 03055 /** 03056 * @defgroup AFECTRL_Const 03057 * @brief AFE Control signal set. Bit masks for register AFECON. 03058 * @details This is all the available control signal for function @ref AD5940_AFECtrlS 03059 * @warning Bit field in register AFECON has some opposite meaning as below definitions. We use all positive word here 03060 * like HPREF instead of HPREFDIS. This set is only used in function @ref AD5940_AFECtrlS, the second parameter 03061 * decides whether enable it or disable it. 03062 * @{ 03063 */ 03064 #define AFECTRL_HPREFPWR (1L<<5) /**< High power reference on-off control */ 03065 #define AFECTRL_HSDACPWR (1L<<6) /**< High speed DAC on-off control */ 03066 #define AFECTRL_ADCPWR (1L<<7) /**< ADC power on-off control */ 03067 #define AFECTRL_ADCCNV (1L<<8) /**< Start ADC convert enable */ 03068 #define AFECTRL_EXTBUFPWR (1L<<9) /**< Excitation buffer power control */ 03069 #define AFECTRL_INAMPPWR (1L<<10) /**< Excitation loop input amplifier before P/N node power control */ 03070 #define AFECTRL_HSTIAPWR (1L<<11) /**< High speed TIA amplifier power control */ 03071 #define AFECTRL_TEMPSPWR (1L<<12) /**< Temperature sensor power */ 03072 #define AFECTRL_TEMPCNV (1L<<13) /**< Start Temperature sensor convert */ 03073 #define AFECTRL_WG (1L<<14) /**< Waveform generator on-off control */ 03074 #define AFECTRL_DFT (1L<<15) /**< DFT engine on-off control */ 03075 #define AFECTRL_SINC2NOTCH (1L<<16) /**< SIN2+Notch block on-off control */ 03076 #define AFECTRL_ALDOLIMIT (1L<<19) /**< ALDO current limit on-off control */ 03077 #define AFECTRL_DACREFPWR (1L<<20) /**< DAC reference buffer power control */ 03078 #define AFECTRL_DCBUFPWR (1L<<21) /**< Excitation loop DC offset buffer sourced from LPDAC power control */ 03079 #define AFECTRL_ALL 0x39ffe0 /**< All control signals */ 03080 /** 03081 * @} 03082 */ 03083 03084 /** 03085 * @defgroup LPMODECTRL_Const 03086 * @brief LP Control signal(bit mask) for register LPMODECON 03087 * @details This is all the available control signal for function @ref AD5940_LPModeCtrlS 03088 * @warning Bit field in register LPMODECON has some opposite meaning as below definitions. We use all positive word here 03089 * like HPREFPWR instead of HPREFDIS. This set is only used in function @ref AD5940_AFECtrlS, the second parameter 03090 * decides whether enable or disable selected block(s). 03091 * @{ 03092 */ 03093 #define LPMODECTRL_HFOSCEN (1<<0) /**< Enable internal HFOSC. Note: the register defination is set this bit to 1 to disable it. */ 03094 #define LPMODECTRL_HPREFPWR (1<<1) /**< High power reference power EN. Note: the register defination is set this bit to 1 to disable it. */ 03095 #define LPMODECTRL_ADCCNV (1<<2) /**< Start ADC convert enable */ 03096 #define LPMODECTRL_REPEATEN (1<<3) /**< Enable repeat convert function. This will enable ADC power automatically */ 03097 #define LPMODECTRL_GLBBIASZ (1<<4) /**< Enable Global ZTAT bias. Disable it to save more power */ 03098 #define LPMODECTRL_GLBBIASP (1<<5) /**< Enable Global PTAT bias. Disable it to save more power */ 03099 #define LPMODECTRL_BUFHP1P8V (1<<6) /**< High power 1.8V reference buffer */ 03100 #define LPMODECTRL_BUFHP1P1V (1<<7) /**< High power 1.1V reference buffer */ 03101 #define LPMODECTRL_ALDOPWR (1<<8) /**< Enable ALDO. Note: register defination is set this bit to 1 to disable ALDO. */ 03102 #define LPMODECTRL_ALL 0x1ff /**< All Control signal Or'ed together*/ 03103 #define LPMODECTRL_NONE 0 /**< No blocks selected */ 03104 /** @} */ 03105 03106 /** 03107 * @defgroup AFERESULT_Const 03108 * @brief The available AFE results type. Used for function @ref AD5940_ReadAfeResult 03109 * @{ 03110 */ 03111 #define AFERESULT_SINC3 0 /**< SINC3 result */ 03112 #define AFERESULT_SINC2 1 /**< SINC2+NOTCH result */ 03113 #define AFERESULT_TEMPSENSOR 2 /**< Temperature sensor result */ 03114 #define AFERESULT_DFTREAL 3 /**< DFT Real result */ 03115 #define AFERESULT_DFTIMAGE 4 /**< DFT Imaginary result */ 03116 #define AFERESULT_STATSMEAN 5 /**< Statistic Mean result */ 03117 #define AFERESULT_STATSVAR 6 /**< Statistic Variance result */ 03118 /** @} */ 03119 03120 /** 03121 * @} AFE_Control_Const 03122 * @} AFE_Control 03123 * */ 03124 03125 /** 03126 * @addtogroup High_Speed_Loop 03127 * @{ 03128 * @defgroup High_Speed_Loop_Const 03129 * @{ 03130 */ 03131 03132 /** 03133 * @defgroup Switch_Matrix_Block_Const 03134 * @{ 03135 * @defgroup SWD_Const 03136 * @brief Switch D set. This is bit mask for register DSWFULLCON. 03137 * @details 03138 * It's used to initialize structure @ref SWMatrixCfg_Type 03139 * The bit masks can be OR'ed together. For example 03140 * - `SWD_AIN1|SWD_RCAL0` means close SWD_AIN1 and SWD_RCAL0 in same time, and open all other D switches. 03141 * - `SWD_AIN2` means close SWD_AIN2 and open all other D switches. 03142 * @{ 03143 */ 03144 #define SWD_OPEN (0<<0) /**< Open all D switch. */ 03145 #define SWD_RCAL0 (1<<0) /**< pin RCAL0 */ 03146 #define SWD_AIN1 (1<<1) /**< Pin AIN1 */ 03147 #define SWD_AIN2 (1<<2) /**< Pin AIN2 */ 03148 #define SWD_AIN3 (1<<3) /**< Pin AIN3 */ 03149 #define SWD_CE0 (1<<4) /**< Pin CE0 */ 03150 #define SWD_CE1 (1<<5) /**< CE1 in ADuCM355 */ 03151 #define SWD_AFE1 (1<<5) /**< AFE1 in AD594x */ 03152 #define SWD_SE0 (1<<6) /**< Pin SE0 */ 03153 #define SWD_SE1 (1<<7) /**< SE1 in ADuCM355 */ 03154 #define SWD_AFE3 (1<<7) /**< AFE3 in AD594x */ 03155 /** @} */ 03156 03157 /** 03158 * @defgroup SWP_Const 03159 * @brief Switch P set. This is bit mask for register PSWFULLCON. 03160 * @details 03161 * It's used to initialize structure @ref SWMatrixCfg_Type. 03162 * The bit masks can be OR'ed together. For example 03163 * - `SWP_RCAL0|SWP_AIN1` means close SWP_RCAL0 and SWP_AIN1 in same time, and open all other P switches. 03164 * - `SWP_SE0` means close SWP_SE0 and open all other P switches. 03165 * @{ 03166 */ 03167 #define SWP_OPEN 0 /**< Open all P switches */ 03168 #define SWP_RCAL0 (1<<0) /**< Pin RCAL0 */ 03169 #define SWP_AIN1 (1<<1) /**< Pin AIN1 */ 03170 #define SWP_AIN2 (1<<2) /**< Pin AIN2 */ 03171 #define SWP_AIN3 (1<<3) /**< Pin AIN3 */ 03172 #define SWP_RE0 (1<<4) /**< Pin RE0 */ 03173 #define SWP_RE1 (1<<5) /**< RE1 in ADuCM355 */ 03174 #define SWP_AFE2 (1<<5) /**< AFE2 in AD5940 */ 03175 #define SWP_SE0 (1<<6) /**< Pin SE0 */ 03176 #define SWP_DE0 (1<<7) /**< Pin DE0 */ 03177 #define SWP_SE1 (1<<8) /**< SE1 in ADuCM355 */ 03178 #define SWP_AFE3 (1<<8) /**< AFE3 in AD5940 */ 03179 #define SWP_DE1 (1<<9) /**< ADuCM355 Only. */ 03180 #define SWP_CE0 (1<<10) /**< Pin CE0 */ 03181 #define SWP_CE1 (1<<11) /**< CE1 in ADuCM355 */ 03182 #define SWP_AFE1 (1<<11) /**< AFE1 in AD5940 */ 03183 #define SWP_PL (1<<13) /**< Internal PL switch */ 03184 #define SWP_PL2 (1<<14) /**< Internal PL2 switch */ 03185 /** @} */ 03186 03187 /** 03188 * @defgroup SWN_Const 03189 * @brief Switch N set. This is bit mask for register NSWFULLCON. 03190 * @details 03191 * It's used to initialize structure @ref SWMatrixCfg_Type. 03192 * The bit masks can be OR'ed together. For example 03193 * - `SWN_RCAL0|SWN_AIN1` means close SWN_RCAL0 and SWN_AIN1 in same time, and open all other N switches. 03194 * - `SWN_SE0` means close SWN_SE0 and open all other N switches. 03195 * @{ 03196 */ 03197 #define SWN_OPEN 0 /**< Open all N switches */ 03198 #define SWN_RCAL1 (1<<9) /**< Pin RCAL1 */ 03199 #define SWN_AIN0 (1<<0) /**< Pin AIN0 */ 03200 #define SWN_AIN1 (1<<1) /**< Pin AIN1 */ 03201 #define SWN_AIN2 (1<<2) /**< Pin AIN2 */ 03202 #define SWN_AIN3 (1<<3) /**< Pin AIN3 */ 03203 #define SWN_SE0LOAD (1<<4) /**< SE0_LOAD is different from PIN SE0. It's the point after 100Ohm load resistor */ 03204 #define SWN_DE0LOAD (1<<5) /**< DE0_Load is after Rload resistor */ 03205 #define SWN_SE1LOAD (1<<6) /**< SE1_LOAD in ADuCM355 */ 03206 #define SWN_AFE3LOAD (1<<6) /**< AFE3LOAD in ADuCM355 */ 03207 #define SWN_DE1LOAD (1<<7) /**< ADuCM355 Only*/ 03208 #define SWN_SE0 (1<<8) /**< SE0 here means the PIN SE0. */ 03209 #define SWN_NL (1<<10) /**< Internal NL switch */ 03210 #define SWN_NL2 (1<<11) /**< Internal NL2 switch */ 03211 /** @} */ 03212 03213 /** 03214 * @defgroup SWT_Const 03215 * @brief Switch T set. This is bit mask for register TSWFULLCON. 03216 * @details 03217 * It's used to initialize structure @ref SWMatrixCfg_Type. 03218 * The bit masks can be OR'ed together. For example 03219 * - SWT_RCAL0|SWT_AIN1 means close SWT_RCAL0 and SWT_AIN1 in same time, and open all other T switches. 03220 * - SWT_SE0LOAD means close SWT_SE0LOAD and open all other T switches. 03221 * @{ 03222 */ 03223 #define SWT_OPEN 0 /**< Open all T switches */ 03224 #define SWT_RCAL1 (1<<11) /**< Pin RCAL1 */ 03225 #define SWT_AIN0 (1<<0) /**< Pin AIN0 */ 03226 #define SWT_AIN1 (1<<1) /**< Pin AIN1 */ 03227 #define SWT_AIN2 (1<<2) /**< Pin AIN2 */ 03228 #define SWT_AIN3 (1<<3) /**< Pin AIN3 */ 03229 #define SWT_SE0LOAD (1<<4) /**< SE0_LOAD is different from PIN SE0. It's the point after 100Ohm load resistor */ 03230 #define SWT_DE0 (1<<5) /**< DE0 pin. */ 03231 #define SWT_SE1LOAD (1<<6) /**< SE1_LOAD on ADuCM355*/ 03232 #define SWT_AFE3LOAD (1<<6) /**< AFE3_LOAD on ADuCM355*/ 03233 #define SWT_DE1 (1<<7) /**< ADuCM355 Only*/ 03234 #define SWT_TRTIA (1<<8) /**< T9 switch. Connect RTIA to T matrix */ 03235 #define SWT_DE0LOAD (1<<9) /**< DE0Load is the position after Rload Resisor */ 03236 #define SWT_DE1LOAD (1<<10) /**< DE1Load is the position after Rload Resisor */ 03237 /** @} */ 03238 03239 /** @} Switch_Matrix_Block_Const */ 03240 03241 03242 /** 03243 * @defgroup Waveform_Generator_Block_Const 03244 * @{ 03245 */ 03246 /** 03247 * @defgroup WGTYPE_Const 03248 * @brief Waveform generator signal type 03249 * @{ 03250 */ 03251 #define WGTYPE_MMR 0 /**< Direct write to DAC using register */ 03252 #define WGTYPE_SIN 2 /**< Sine wave generator */ 03253 #define WGTYPE_TRAPZ 3 /**< Trapezoid generator */ 03254 /** @} */ 03255 /** @} Waveform_Generator_Block_Const */ 03256 03257 /** 03258 * @defgroup HSDAC_Block_Const 03259 * @{ 03260 */ 03261 /* Excitation buffer gain selection */ 03262 /** 03263 * @defgroup EXCITBUFGAIN_Const 03264 * @{ 03265 */ 03266 #define EXCITBUFGAIN_2 0 /**< Excitation buffer gain is x2 */ 03267 #define EXCITBUFGAIN_0P25 1 /**< Excitation buffer gain is x1/4 */ 03268 /** @} */ 03269 03270 /** 03271 * @defgroup HSDACGAIN_Const 03272 * @{ 03273 */ 03274 /* HSDAC PGA Gain selection(DACCON.BIT0) */ 03275 #define HSDACGAIN_1 0 /**< Gain is x1 */ 03276 #define HSDACGAIN_0P2 1 /**< Gain is x1/5 */ 03277 /** @} */ 03278 /** @} */ //HSDAC_Block_Const 03279 03280 /** 03281 * @defgroup HSTIA_Block_Const 03282 * @{ 03283 * */ 03284 /* HSTIA Amplifier Positive Input selection */ 03285 03286 /** 03287 * @defgroup HSTIABIAS_Const 03288 * @warning When select Vzero0 as bias, close LPDAC switch<xxx> 03289 * @{ 03290 */ 03291 #define HSTIABIAS_1P1 0 /**< Internal 1.1V common voltage from internal 1.1V reference buffer */ 03292 #define HSTIABIAS_VZERO0 1 /**< From LPDAC0 Vzero0 output */ 03293 #define HSTIABIAS_VZERO1 2 /**< From LPDAC1 Vzero1 output. Only available on ADuCM355. */ 03294 /** @} */ 03295 03296 03297 /* HSTIA Internal RTIA selection */ 03298 03299 /** 03300 * @defgroup HSTIARTIA_Const 03301 * @{ 03302 */ 03303 #define HSTIARTIA_200 0 /**< HSTIA Internal RTIA resistor 200 */ 03304 #define HSTIARTIA_1K 1 /**< HSTIA Internal RTIA resistor 1K */ 03305 #define HSTIARTIA_5K 2 /**< HSTIA Internal RTIA resistor 5K */ 03306 #define HSTIARTIA_10K 3 /**< HSTIA Internal RTIA resistor 10K */ 03307 #define HSTIARTIA_20K 4 /**< HSTIA Internal RTIA resistor 20K */ 03308 #define HSTIARTIA_40K 5 /**< HSTIA Internal RTIA resistor 40K */ 03309 #define HSTIARTIA_80K 6 /**< HSTIA Internal RTIA resistor 80K */ 03310 #define HSTIARTIA_160K 7 /**< HSTIA Internal RTIA resistor 160K */ 03311 #define HSTIARTIA_OPEN 8 /**< Open internal resistor */ 03312 /** @} */ 03313 03314 /** 03315 * @defgroup HSTIADERTIA_Const 03316 * @{ 03317 */ 03318 #define HSTIADERTIA_50 0 /**< 50Ohm Settings depends on RLOAD resistor. */ 03319 #define HSTIADERTIA_100 1 /**< 100Ohm Settings depends on RLOAD resistor.*/ 03320 #define HSTIADERTIA_200 2 /**< 200Ohm Settings depends on RLOAD resistor.*/ 03321 #define HSTIADERTIA_1K 3 /**< set bit[7:3] to 0x0b(11) */ 03322 #define HSTIADERTIA_5K 4 /**< set bit[7:3] to 0x0c(12) */ 03323 #define HSTIADERTIA_10K 5 /**< set bit[7:3] to 0x0d(13) */ 03324 #define HSTIADERTIA_20K 6 /**< set bit[7:3] to 0x0e(14) */ 03325 #define HSTIADERTIA_40K 7 /**< set bit[7:3] to 0x0f(15) */ 03326 #define HSTIADERTIA_80K 8 /**< set bit[7:3] to 0x10(16) */ 03327 #define HSTIADERTIA_160K 9 /**< set bit[7:3] to 0x11(17) */ 03328 #define HSTIADERTIA_TODE 10 /**< short HSTIA output to DE0 pin. set bit[7:3] to 0x12(18) */ 03329 #define HSTIADERTIA_OPEN 11 /**< Default state is set to OPEN RTIA by setting bit[7:3] to 0x1f */ 03330 /** @} */ 03331 03332 /* HSTIA DE0 Terminal internal RLOAD selection */ 03333 /** 03334 * @defgroup HSTIADERLOAD_Const 03335 * @{ 03336 */ 03337 #define HSTIADERLOAD_0R 0 /**< set bit[2:0] to 0x00 */ 03338 #define HSTIADERLOAD_10R 1 /**< set bit[2:0] to 0x01 */ 03339 #define HSTIADERLOAD_30R 2 /**< set bit[2:0] to 0x02 */ 03340 #define HSTIADERLOAD_50R 3 /**< set bit[2:0] to 0x03 */ 03341 #define HSTIADERLOAD_100R 4 /**< set bit[2:0] to 0x04 */ 03342 #define HSTIADERLOAD_OPEN 5 /**< RLOAD open means open switch between HSTIA negative input and Rload resistor(<S1>).Default state is OPEN RLOAD by setting HSTIARES03CON[2:0] to 0x5, 0x6 or 0x7 */ 03343 /** @} */ 03344 03345 /** 03346 * @defgroup HSTIAPWRMOE_Const 03347 * @{ 03348 */ 03349 #define HSTIAPWRMOE_LP 0 /**< HSTIA in LP mode */ 03350 #define HSTIAPWRMOE_HP 1 /**< HSTIA in HP mode */ 03351 /** @} */ 03352 03353 03354 /** @} HSTIA_Block_Const */ 03355 /** 03356 * @} High_Speed_Loop_Const 03357 * @} High_Speed_Loop 03358 */ 03359 03360 /** 03361 * @addtogroup Low_Power_Loop 03362 * Low power includes low power DAC and two low power amplifiers(PA and TIA) 03363 * @{ 03364 * @defgroup Low_Power_Loop_Const 03365 * The constant used in Low power loop. 03366 * @{ 03367 */ 03368 03369 /** 03370 * @defgroup LPDAC_Block_Const 03371 * @{ 03372 * */ 03373 /** 03374 * @defgroup LPDAC_Const 03375 * Select which LPDAC is accessing. 03376 * @note This parameter must be configured correctly 03377 * @{ 03378 */ 03379 #define LPDAC0 0 /**< LPDAC0 */ 03380 #define LPDAC1 1 /**< LPDAC1, ADuCM355 Only */ 03381 /** @} */ 03382 /** 03383 * @defgroup LPDACSRC_Const 03384 * LPDAC data source selection. Either from MMR or from waveform generator. 03385 * @{ 03386 */ 03387 #define LPDACSRC_MMR 0 /**< Get data from register REG_AFE_LPDACDAT0DATA0 */ 03388 #define LPDACSRC_WG 1 /**< Get data from waveform generator */ 03389 /** @} */ 03390 03391 /** 03392 * @defgroup LPDACSW_Const 03393 * @brief LPDAC switch settings 03394 * @{ 03395 */ 03396 #define LPDACSW_VBIAS2LPPA 0x10 /**< switch between LPDAC Vbias output and LPPA(low power PA(Potential Amplifier)) */ 03397 #define LPDACSW_VBIAS2PIN 0x08 /**< Switch between LPDAC Vbias output and Vbias pin */ 03398 #define LPDACSW_VZERO2LPTIA 0x04 /**< Switch between LPDAC Vzero output and LPTIA positive input */ 03399 #define LPDACSW_VZERO2PIN 0x02 /**< Switch between LPDAC Vzero output and Vzero pin */ 03400 #define LPDACSW_VZERO2HSTIA 0x01 /**< Switch between LPDAC Vzero output and HSTIA positive input MUX */ 03401 /** @} */ 03402 03403 /** 03404 * @defgroup LPDACVZERO_Const 03405 * @brief Vzero MUX selection 03406 * @{ 03407 */ 03408 #define LPDACVZERO_6BIT 0 /**< Connect Vzero to 6bit LPDAC output */ 03409 #define LPDACVZERO_12BIT 1 /**< Connect Vzero to 12bit LPDAC output */ 03410 /** @} */ 03411 03412 /** 03413 * @defgroup LPDACVBIAS_Const 03414 * @brief Vbias MUX selection 03415 * @{ 03416 */ 03417 #define LPDACVBIAS_6BIT 1 /**< Connect Vbias to 6bit LPDAC output */ 03418 #define LPDACVBIAS_12BIT 0 /**< Connect Vbias to 12bit LPDAC output */ 03419 /** @} */ 03420 03421 03422 /** 03423 * @defgroup LPDACREF_Const 03424 * @brief LPDAC reference selection 03425 * @{ 03426 */ 03427 #define LPDACREF_2P5 0 /**< Internal 2.5V reference */ 03428 #define LPDACREF_AVDD 1 /**< Use AVDD as reference */ 03429 /** @} */ 03430 03431 /** @} */ //LPDAC_Block_Const 03432 03433 /** 03434 * @defgroup LPAMP_Block_Const 03435 * @brief Low power amplifies include potential-state amplifier(PA in short) and TIA. 03436 * @{ 03437 * */ 03438 03439 /** 03440 * @defgroup LPTIA_Const 03441 * @brief LPTIA selecion 03442 * @{ 03443 * */ 03444 #define LPTIA0 0 /**< LPTIA0 */ 03445 #define LPTIA1 1 /**< LPTIA1, ADuCM355 Only */ 03446 /** @} */ 03447 03448 /** 03449 * @defgroup LPTIARF_Const 03450 * @brief LPTIA LPF Resistor selection 03451 * @{ 03452 * */ 03453 #define LPTIARF_OPEN 0 /**< Disconnect Rf resistor */ 03454 #define LPTIARF_SHORT 1 /**< Bypass Rf resistor */ 03455 #define LPTIARF_20K 2 /**< 20kOhm Rf */ 03456 #define LPTIARF_100K 3 /**< Rf resistor 100kOhm */ 03457 #define LPTIARF_200K 4 /**< Rf resistor 200kOhm */ 03458 #define LPTIARF_400K 5 /**< Rf resistor 400kOhm */ 03459 #define LPTIARF_600K 6 /**< Rf resistor 600kOhm */ 03460 #define LPTIARF_1M 7 /**< Rf resistor 1MOhm */ 03461 /** @} */ 03462 03463 /** 03464 * @defgroup LPTIARLOAD_Const 03465 * @brief LPTIA Rload Selection 03466 * @{ 03467 */ 03468 #define LPTIARLOAD_SHORT 0 /**< 0Ohm Rload */ 03469 #define LPTIARLOAD_10R 1 /**< 10Ohm Rload */ 03470 #define LPTIARLOAD_30R 2 /**< Rload resistor 30Ohm */ 03471 #define LPTIARLOAD_50R 3 /**< Rload resistor 50Ohm */ 03472 #define LPTIARLOAD_100R 4 /**< Rload resistor 100Ohm */ 03473 #define LPTIARLOAD_1K6 5 /**< Only available when RTIA setting >= 2KOHM */ 03474 #define LPTIARLOAD_3K1 6 /**< Only available when RTIA setting >= 4KOHM */ 03475 #define LPTIARLOAD_3K6 7 /**< Only available when RTIA setting >= 4KOHM */ 03476 /** @} */ 03477 03478 /** 03479 * @defgroup LPTIARTIA_Const 03480 * @brief LPTIA RTIA Selection 03481 * @note The real RTIA resistor value dependents on Rload settings. 03482 * @{ 03483 */ 03484 #define LPTIARTIA_OPEN 0 /**< Disconnect LPTIA Internal RTIA */ 03485 #define LPTIARTIA_200R 1 /**< 200Ohm Internal RTIA */ 03486 #define LPTIARTIA_1K 2 /**< 1KOHM */ 03487 #define LPTIARTIA_2K 3 /**< 2KOHM */ 03488 #define LPTIARTIA_3K 4 /**< 3KOHM */ 03489 #define LPTIARTIA_4K 5 /**< 4KOHM */ 03490 #define LPTIARTIA_6K 6 /**< 6KOHM */ 03491 #define LPTIARTIA_8K 7 /**< 8KOHM */ 03492 #define LPTIARTIA_10K 8 /**< 10KOHM */ 03493 #define LPTIARTIA_12K 9 /**< 12KOHM */ 03494 #define LPTIARTIA_16K 10 /**< 16KOHM */ 03495 #define LPTIARTIA_20K 11 /**< 20KOHM */ 03496 #define LPTIARTIA_24K 12 /**< 24KOHM */ 03497 #define LPTIARTIA_30K 13 /**< 30KOHM */ 03498 #define LPTIARTIA_32K 14 /**< 32KOHM */ 03499 #define LPTIARTIA_40K 15 /**< 40KOHM */ 03500 #define LPTIARTIA_48K 16 /**< 48KOHM */ 03501 #define LPTIARTIA_64K 17 /**< 64KOHM */ 03502 #define LPTIARTIA_85K 18 /**< 85KOHM */ 03503 #define LPTIARTIA_96K 19 /**< 96KOHM */ 03504 #define LPTIARTIA_100K 20 /**< 100KOHM */ 03505 #define LPTIARTIA_120K 21 /**< 120KOHM */ 03506 #define LPTIARTIA_128K 22 /**< 128KOHM */ 03507 #define LPTIARTIA_160K 23 /**< 160KOHM */ 03508 #define LPTIARTIA_196K 24 /**< 196KOHM */ 03509 #define LPTIARTIA_256K 25 /**< 256KOHM */ 03510 #define LPTIARTIA_512K 26 /**< 512KOHM */ 03511 /** @} */ 03512 03513 /** 03514 * @defgroup LPAMP_Const 03515 * LPAMP selecion. On AD594x, only LPAMP0 is available. 03516 * @note This parameter must be configured correctly. 03517 * @{ 03518 * */ 03519 #define LPAMP0 0 /**< LPAMP0, AMP include both LPTIA and Potentio-stat amplifiers */ 03520 #define LPAMP1 1 /**< LPAMP1, ADuCM355 Only */ 03521 /** @} */ 03522 03523 /** 03524 * @defgroup LPAMPPWR_Const 03525 * @brief Low power amplifier(PA and TIA) power mode selection. 03526 * @{ 03527 */ 03528 #define LPAMPPWR_NORM 0 /**< Normal Power mode */ 03529 #define LPAMPPWR_BOOST1 1 /**< Boost power to level 1 */ 03530 #define LPAMPPWR_BOOST2 2 /**< Boost power to level 2 */ 03531 #define LPAMPPWR_BOOST3 3 /**< Boost power to level 3 */ 03532 #define LPAMPPWR_HALF 4 /**< Put PA and TIA in half power mode */ 03533 /** @} */ 03534 03535 #define LPTIASW(n) (1L<<n) /**< LPTIA switch control. Use this macro to set LpTiaSW field of @ref LPAmpCfg_Type */ 03536 03537 /** 03538 * @} LPAMP_Block_Const 03539 * @} Low_Power_Loop_Const 03540 * @} Low_Power_Loop 03541 * 03542 * */ 03543 03544 /** 03545 * @addtogroup DSP_Block 03546 * DSP block include signal chain from raw ADC data to various filters, DFT engine and Statistic Functions etc. 03547 * @{ 03548 * @defgroup DSP_Block_Const 03549 * @{ 03550 * @defgroup ADC_Block_Const 03551 * @{ 03552 */ 03553 03554 /** 03555 * @defgroup ADCPGA_Const 03556 * @brief ADC PGA Selection 03557 * @note Only gain 1.5 is factory calibrated. 03558 * @{ 03559 */ 03560 #define ADCPGA_1 0 /**< ADC PGA Gain of 1 */ 03561 #define ADCPGA_1P5 1 /**< ADC PGA Gain of 1.5 */ 03562 #define ADCPGA_2 2 /**< ADC PGA Gain of 2 */ 03563 #define ADCPGA_4 3 /**< ADC PGA Gain of 4 */ 03564 #define ADCPGA_9 4 /**< ADC PGA Gain of 9 */ 03565 #define IS_ADCPGA(pga) (((pga) == ADCPGA_1) ||\ 03566 (pga) == ADCPGA_1P5) ||\ 03567 (pga) == ADCPGA_2) ||\ 03568 (pga) == ADCPGA_4) ||\ 03569 (pga) == ADCPGA_9)) 03570 /** 03571 * @} 03572 * */ 03573 03574 /** 03575 * @defgroup ADCMUXP_Const 03576 * @brief ADC Channel P Configuration 03577 * @{ 03578 */ 03579 #define ADCMUXP_FLOAT 0x0 /**< float */ 03580 #define ADCMUXP_HSTIA_P 0x1 /**< output of HSTIA */ 03581 #define ADCMUXP_AIN0 0x4 /**< pin AIN0 */ 03582 #define ADCMUXP_AIN1 0x5 /**< pin AIN1 */ 03583 #define ADCMUXP_AIN2 0x6 /**< pin AIN2 */ 03584 #define ADCMUXP_AIN3 0x7 /**< pin AIN3 */ 03585 #define ADCMUXP_AVDD_2 0x8 /**< AVDD/2 */ 03586 #define ADCMUXP_DVDD_2 0x9 /**< DVDD/2 */ 03587 #define ADCMUXP_AVDDREG 0xA /**< AVDD internal regulator output. It's around 1.8V */ 03588 #define ADCMUXP_TEMPP 0xB /**< Internal temperature output postive terminal */ 03589 #define ADCMUXP_VSET1P1 0xC /**< Internal 1.1V bias voltage */ 03590 #define ADCMUXP_VDE0 0xD /**< Voltage of DE0 pin */ 03591 #define ADCMUXP_VSE0 0xE /**< Voltage of SE0 pin */ 03592 #define ADCMUXP_VSE1 0xF /**< Voltage of SE1 pin on ADuCM355 */ 03593 #define ADCMUXP_VAFE3 0xF /**< Voltage of AFE3 pin on AD5940. */ 03594 #define ADCMUXP_VREF2P5 0x10 /**< 1.25V. The internal 2.5V reference buffer output divided by 2. */ 03595 #define ADCMUXP_VREF1P8DAC 0x12 /**< HSDAC 1.8V internal reference. It's only available when both AFECON.BIT20 and AFECON.BIT6 are set. */ 03596 #define ADCMUXP_TEMPN 0x13 /**< Internal temperature output negative terminal */ 03597 #define ADCMUXP_AIN4 0x14 /**< Voltage of AIN4/LPF0 pin */ 03598 #define ADCMUXP_AIN5 0x15 /**< Voltage of AIN5 pin */ 03599 #define ADCMUXP_AIN6 0x16 /**< Voltage of AIN6 pin, not available on AD5941 */ 03600 #define ADCMUXP_VZERO0 0x17 /**< Voltage of Vzero0 pin */ 03601 #define ADCMUXP_VBIAS0 0x18 /**< Voltage of Vbias0 pin */ 03602 #define ADCMUXP_VCE0 0x19 /**< Pin CE0 */ 03603 #define ADCMUXP_VRE0 0x1A /**< Pin RE0 */ 03604 #define ADCMUXP_VZERO1 0x1B /**< Voltage of Vzero1 pin on ADuCM355 */ 03605 #define ADCMUXP_VAFE4 0x1B /**< Voltage of AFE4 pin on AD5940. */ 03606 #define ADCMUXP_VBIAS1 0x1C /**< Voltage of Vbias1 pin */ 03607 #define ADCMUXP_VCE1 0x1D /**< Voltage of CE1 pin on ADuCM355. */ 03608 #define ADCMUXP_VAFE1 0x1D /**< Voltage of AFE1 pin on AD5940. */ 03609 #define ADCMUXP_VRE1 0x1E /**< Voltage of RE1 pin on ADuCM355. */ 03610 #define ADCMUXP_VAFE2 0x1E /**< Voltage of AFE2 pin on AD5940. */ 03611 #define ADCMUXP_VCE0_2 0x1F /**< VCE0 divide by 2 */ 03612 #define ADCMUXP_VCE1_2 0x20 /**< VCE1 divide by 2 */ 03613 #define ADCMUXP_LPTIA0_P 0x21 /**< Output of LPTIA0 */ 03614 #define ADCMUXP_LPTIA1_P 0x22 /**< Output of LPTIA1 */ 03615 #define ADCMUXP_AGND 0x23 /**< Internal AGND node */ 03616 #define ADCMUXP_P_NODE 0x24 /**< Buffered voltage of excitation buffer P node. */ 03617 #define ADCMUXP_IOVDD_2 0x27 /**< IOVDD/2 */ 03618 /**@}*/ 03619 03620 /** 03621 * @defgroup ADCMUXN_Const 03622 * @brief ADC Channel N Configuration 03623 * @{ 03624 */ 03625 #define ADCMUXN_FLOAT 0x0 /**< float */ 03626 #define ADCMUXN_HSTIA_N 0x1 /**< HSTIA negative input node. */ 03627 #define ADCMUXN_LPTIA0_N 0x2 /**< LPTIA0 negative input node. */ 03628 #define ADCMUXN_LPTIA1_N 0x3 /**< LPTIA1 negative input node. */ 03629 #define ADCMUXN_AIN0 0x4 /**< Pin AIN0 */ 03630 #define ADCMUXN_AIN1 0x5 /**< Pin AIN1 */ 03631 #define ADCMUXN_AIN2 0x6 /**< Pin AIN2 */ 03632 #define ADCMUXN_AIN3 0x7 /**< Pin AIN3 */ 03633 #define ADCMUXN_VSET1P1 0x8 /**< Internal 1.11V reference */ 03634 #define ADCMUXN_VREF1P1 0x8 /**< Internal 1.11V reference, same as ADCMUXN_VSET1P1 */ 03635 #define ADCMUXN_TEMPN 0xB /**< Temperature sensor output. */ 03636 #define ADCMUXN_AIN4 0xC /**< AIN4 */ 03637 #define ADCMUXN_AIN5 0xD /**< AIN5 */ 03638 #define ADCMUXN_AIN6 0xE /**< AIN6 */ 03639 #define ADCMUXN_VZERO0 0x10 /**< pin Vzero0 */ 03640 #define ADCMUXN_VBIAS0 0x11 /**< pin Vbias0 */ 03641 #define ADCMUXN_VZERO1 0x12 /**< pin Vzero1 */ 03642 #define ADCMUXN_AFE4 0x12 /**< Pin AFE4 on AD5940. */ 03643 #define ADCMUXN_VBIAS1 0x13 /**< pin Vbias1 */ 03644 #define ADCMUXN_N_NODE 0x14 /**< Buffered voltage of excitation buffer N node. */ 03645 /** @} */ 03646 03647 /** 03648 * @defgroup ADCRATE_Const 03649 * @brief ADC Current Sample Rate. If ADC clock is 32MHz, set it to ADCRATE_1P6MHZ. Otherwise, set it to ADCRATE_800KHZ. 03650 * @{ 03651 */ 03652 #define ADCRATE_800KHZ 1 /**< ADC input clock is 16MHz, sample rate is 800kHz */ 03653 #define ADCRATE_1P6MHZ 0 /**< ADC input clock is 32MHz, sample rate is 1.6MHz */ 03654 #define IS_ADCRATE(rate) (((rate) == ADCRATE_800KHZ) ||\ 03655 (rate) == ADCRATE_1P6MHZ)) 03656 /** @} */ 03657 03658 /** 03659 * @defgroup ADCSINC3OSR_Const 03660 * @brief ADC SINC3 Filter OSR. 2, 4 is recommended value. 5 is not recommended. 03661 * @{ 03662 */ 03663 #define ADCSINC3OSR_2 2 /**< ADC SINC3 OSR 2 */ 03664 #define ADCSINC3OSR_4 1 /**< ADC SINC3 OSR 4 */ 03665 #define ADCSINC3OSR_5 0 /**< ADC SINC3 OSR 5 */ 03666 #define IS_ADCSINC3OSR(osr) (((osr) == ADCSINC3OSR_2) ||\ 03667 (osr) == ADCSINC3OSR_4) ||\ 03668 (osr) == ADCSINC3OSR_5)) /**< checker of ADCSINC3OSR */ 03669 /** @} */ 03670 03671 /** 03672 * @defgroup ADCSINC2OSR_Const 03673 * @brief ADC SINC2 Filter OSR. 03674 * @{ 03675 */ 03676 #define ADCSINC2OSR_22 0 /**< ADC SINC2 OSR 22 */ 03677 #define ADCSINC2OSR_44 1 /**< ADC SINC2 OSR 44 */ 03678 #define ADCSINC2OSR_89 2 /**< ADC SINC2 OSR 89 */ 03679 #define ADCSINC2OSR_178 3 /**< ADC SINC2 OSR 178 */ 03680 #define ADCSINC2OSR_267 4 /**< ADC SINC2 OSR 267 */ 03681 #define ADCSINC2OSR_533 5 /**< ADC SINC2 OSR 533 */ 03682 #define ADCSINC2OSR_640 6 /**< ADC SINC2 OSR 640 */ 03683 #define ADCSINC2OSR_667 7 /**< ADC SINC2 OSR 667 */ 03684 #define ADCSINC2OSR_800 8 /**< ADC SINC2 OSR 800 */ 03685 #define ADCSINC2OSR_889 9 /**< ADC SINC2 OSR 889 */ 03686 #define ADCSINC2OSR_1067 10 /**< ADC SINC2 OSR 1067 */ 03687 #define ADCSINC2OSR_1333 11 /**< ADC SINC2 OSR 1333 */ 03688 #define IS_ADCSINC2OSR(osr) (((osr) == ADCSINC2OSR_22) ||\ 03689 (osr) == ADCSINC2OSR_44) ||\ 03690 (osr) == ADCSINC2OSR_89) ||\ 03691 (osr) == ADCSINC2OSR_178) ||\ 03692 (osr) == ADCSINC2OSR_267) ||\ 03693 (osr) == ADCSINC2OSR_533) ||\ 03694 (osr) == ADCSINC2OSR_640) ||\ 03695 (osr) == ADCSINC2OSR_667) ||\ 03696 (osr) == ADCSINC2OSR_800) ||\ 03697 (osr) == ADCSINC2OSR_889) ||\ 03698 (osr) == ADCSINC2OSR_1067) ||\ 03699 (osr) == ADCSINC2OSR_1333)) /**< checker of ADCSINC2OSR */ 03700 /** @} */ 03701 03702 /** 03703 * @defgroup ADCAVGNUM_Const 03704 * @brief ADC Average filter for DFT. The average block locates after SINC3 filter. 03705 * The output of average filter is directly feed into DFT block. 03706 * @warning Once average filter is enabled, DFT source is automatically changed to averaged data. 03707 * @{ 03708 */ 03709 #define ADCAVGNUM_2 0 /**< Take 2 input to do average. */ 03710 #define ADCAVGNUM_4 1 /**< Take 4 input to do average. */ 03711 #define ADCAVGNUM_8 2 /**< Take 8 input to do average. */ 03712 #define ADCAVGNUM_16 3 /**< Take 16 input to do average. */ 03713 #define IS_ADCAVGNUM(num) (((num) == ADCAVGNUM_2) ||\ 03714 (num) == ADCAVGNUM_4) ||\ 03715 (num) == ADCAVGNUM_8) ||\ 03716 (num) == ADCAVGNUM_16)) /**< checker of ADCAVGNUM macro */ 03717 /** @} */ 03718 03719 /** @} ADC_Block_Const */ 03720 03721 /** 03722 * @defgroup DFT_Block_Const 03723 * @{ 03724 * */ 03725 03726 /** 03727 * @defgroup DFTSRC_Const 03728 * @brief DFT source selection. When average function is enabled, DFT source automatically switch to average output. 03729 * @{ 03730 * */ 03731 #define DFTSRC_SINC2NOTCH 0 /**< SINC2+Notch filter block output. Bypass Notch to use SINC2 data */ 03732 #define DFTSRC_SINC3 1 /**< SINC3 filter */ 03733 #define DFTSRC_ADCRAW 2 /**< Raw ADC data */ 03734 #define DFTSRC_AVG 3 /**< Average output of SINC3. */ 03735 /** @} */ 03736 03737 /** 03738 * @defgroup DFTNUM_Const 03739 * @brief DFT number selection. 03740 * @{ 03741 * */ 03742 #define DFTNUM_4 0 /**< 4 Point */ 03743 #define DFTNUM_8 1 /**< 8 Point */ 03744 #define DFTNUM_16 2 /**< 16 Point */ 03745 #define DFTNUM_32 3 /**< 32 Point */ 03746 #define DFTNUM_64 4 /**< 64 Point */ 03747 #define DFTNUM_128 5 /**< 128 Point */ 03748 #define DFTNUM_256 6 /**< 256 Point */ 03749 #define DFTNUM_512 7 /**< 512 Point */ 03750 #define DFTNUM_1024 8 /**< 1024 Point */ 03751 #define DFTNUM_2048 9 /**< 2048 Point */ 03752 #define DFTNUM_4096 10 /**< 4096 Point */ 03753 #define DFTNUM_8192 11 /**< 8192 Point */ 03754 #define DFTNUM_16384 12 /**< 16384 Point */ 03755 /** @} */ 03756 03757 /** 03758 * @} DFT_Block_Const 03759 */ 03760 03761 /** 03762 * @defgroup Statistic_Block_Const 03763 * @{ 03764 */ 03765 /** 03766 * @defgroup STATSAMPLE_Const 03767 * @brief The statistic module sample size. It decides how much data is used to do calculation. 03768 * @{ 03769 */ 03770 #define STATSAMPLE_128 0 /**< Sample size 128 */ 03771 #define STATSAMPLE_64 1 /**< Sample size 64 */ 03772 #define STATSAMPLE_32 2 /**< Sample size 32 */ 03773 #define STATSAMPLE_16 3 /**< Sample size 16 */ 03774 #define STATSAMPLE_8 4 /**< Sample size 8 */ 03775 /** @} */ 03776 03777 /* Statistic standard deviation configure */ 03778 /** 03779 * @defgroup STATDEV_Const 03780 * @brief The standard deviation configure 03781 * @{ 03782 */ 03783 #define STATDEV_1 1 /**< Used for check outlier of ADC result */ 03784 #define STATDEV_4 4 /**< Used for check outlier of ADC result */ 03785 #define STATDEV_9 9 /**< Used for check outlier of ADC result */ 03786 #define STATDEV_16 16 /**< Used for check outlier of ADC result */ 03787 #define STATDEV_25 25 /**< Used for check outlier of ADC result */ 03788 /** @} */ 03789 03790 /** 03791 * @} Statistic_Block_Const 03792 * @} DSP_Block_Const 03793 * @} DSP_Block 03794 * 03795 */ 03796 03797 /** 03798 * @addtogroup Sequencer_FIFO 03799 * @{ 03800 * @defgroup Sequencer_FIFO_Const 03801 * @brief This block includes sequencer and FIFO related all parameters. 03802 * @{ 03803 */ 03804 03805 /** 03806 * @defgroup SEQID_Const 03807 * @{ 03808 */ 03809 #define SEQID_0 0 /**< Sequence0 */ 03810 #define SEQID_1 1 /**< Sequence1 */ 03811 #define SEQID_2 2 /**< Sequence2 */ 03812 #define SEQID_3 3 /**< Sequence3 */ 03813 /** @} */ 03814 03815 /** 03816 * @defgroup SEQID_Const 03817 * @brief Sequencer memory size. SRAM is shared between FIFO and Sequencer 03818 * @warning The total available SRAM is 6kB. It's shared by FIFO and sequencer. 03819 * @{ 03820 */ 03821 #define SEQMEMSIZE_32B 0 /**< The selfbuild in 32Byte for sequencer. All 6kB SRAM can be used for data FIFO */ 03822 #define SEQMEMSIZE_2KB 1 /**< Sequencer use 2kB. The reset 4kB can be used for data FIFO */ 03823 #define SEQMEMSIZE_4KB 2 /**< 4kB for Sequencer. 2kB for data FIFO */ 03824 #define SEQMEMSIZE_6KB 3 /**< All 6kB for Sequencer. Build in 32Bytes memory can be used for data FIFO */ 03825 /** @} */ 03826 03827 03828 /* Mode of GPIO detecting used for triggering sequence */ 03829 /** 03830 * @defgroup SEQPINTRIGMODE_Const 03831 * @{ 03832 */ 03833 #define SEQPINTRIGMODE_RISING 0 /**< Rising edge */ 03834 #define SEQPINTRIGMODE_FALLING 1 /**< Falling edge */ 03835 #define SEQPINTRIGMODE_BOTHEDGE 2 /**< Rising or falling */ 03836 #define SEQPINTRIGMODE_HIGHL 3 /**< High level */ 03837 #define SEQPINTRIGMODE_LOWL 4 /**< Low level */ 03838 /** @} */ 03839 03840 /* Sequencer helper */ 03841 /** 03842 * @defgroup Sequencer_Helper 03843 * @{ 03844 */ 03845 03846 /* Three kinds of sequencer commands: wait, time-out, write */ 03847 /* Decoded by BIT[31:30] */ 03848 /** 03849 * Wait command. Wait some clocks-code Command Code: 'b00 03850 * @warning Maximum wait time is 0x3fff_ffff/System clock. 03851 */ 03852 #define SEQ_WAIT(ClkNum) (0x00000000| ((uint32_t)(ClkNum)&0x3fffffff)) 03853 03854 /** 03855 * Time-Out command. Set time-out count down value. Command Code: 'b01 03856 * @warning maximum time-out timer value is 0x3fffffff 03857 * */ 03858 #define SEQ_TOUT(ClkNum) (0x40000000| ((uint32_t)(ClkNum)&0x3fffffff)) 03859 03860 /** 03861 * Write register command. Command Code: 'b10 or 'b11 03862 * @warning Address range is 0x2000 to 0x21FF. Data is limited to 24bit width. 03863 * */ 03864 #define SEQ_WR(addr,data) (0x80000000|(((((uint32_t)(addr))>>2)&0x7f)<<24) \ 03865 |(((uint32_t)(data))&0xffffff)) 03866 03867 /* Some commands used frequently */ 03868 #define SEQ_NOP() SEQ_WAIT(0) /**< SEQ_NOP is just a simple wait command that wait one system clock */ 03869 #define SEQ_HALT() SEQ_WR(REG_AFE_SEQCON,0x12) /**< Can halt sequencer. Used for debug */ 03870 #define SEQ_STOP() SEQ_WR(REG_AFE_SEQCON,0x00) /**< Disable sequencer, this will generate End of Sequence interrupt */ 03871 03872 #define SEQ_SLP() SEQ_WR(REG_AFE_SEQTRGSLP, 1) /**< Trigger sleep. If sleep is allowed, AFE will go to sleep/hibernate mode */ 03873 03874 #define SEQ_INT0() SEQ_WR(REG_AFE_AFEGENINTSTA, (1L<<0)) /**< Generate custom interrupt 0 */ 03875 #define SEQ_INT1() SEQ_WR(REG_AFE_AFEGENINTSTA, (1L<<1)) /**< Generate custom interrupt 1 */ 03876 #define SEQ_INT2() SEQ_WR(REG_AFE_AFEGENINTSTA, (1L<<2)) /**< Generate custom interrupt 2 */ 03877 #define SEQ_INT3() SEQ_WR(REG_AFE_AFEGENINTSTA, (1L<<3)) /**< Generate custom interrupt 3 */ 03878 03879 /* Helper to calculate sequence length in array */ 03880 #define SEQ_LEN(n) (sizeof(n)/4) /**< Calculate how many commands are in sepecified array. */ 03881 /** @} */ //Sequencer_Helper 03882 03883 /* FIFO */ 03884 /** 03885 * @defgroup FIFOMODE_Const 03886 * @{ 03887 */ 03888 #define FIFOMODE_FIFO 2 /**< Standard FIFO mode. If FIFO is full, reject all comming data and put FIFO to fault state, report interrupt if enabled */ 03889 #define FIFOMODE_STREAM 3 /**< Stream mode. If FIFO is full, discard older data. Report FIFO full interrupt if enabled */ 03890 /** @} */ 03891 03892 /** 03893 * @defgroup FIFOSRC_Const 03894 * @{ 03895 */ 03896 #define FIFOSRC_SINC3 0 /**< SINC3 data */ 03897 #define FIFOSRC_DFT 2 /**< DFT real and imaginary part */ 03898 #define FIFOSRC_SINC2NOTCH 3 /**< SINC2+NOTCH block. Notch can be bypassed, so SINC2 data can be feed to FIFO */ 03899 #define FIFOSRC_VAR 4 /**< Statistic variarance output */ 03900 #define FIFOSRC_MEAN 5 /**< Statistic mean output */ 03901 /** @} */ 03902 03903 /** 03904 * @defgroup FIFO_Helper 03905 * @{ 03906 */ 03907 /** 03908 * Method to identify FIFO channel ID: 03909 * [31:25][24:23][22:16][15:0] 03910 * [ ECC ][SEQID][CH_ID][DATA] 03911 * 03912 * CH_ID: [22:16] 7bit in total: 03913 * xxxxx_xx 03914 * 11111_xx : DFT results 03915 * 11110_xx : Mean of statistic block 03916 * 11101_xx : Variance of statistic block 03917 * 1xxxx_xx : Notch filter result, where xxx_xx is the ADC MUX P settings(6bits of reg ADCCON[5:0]). 03918 * 0xxxx_xx : SINC3 filter result, where xxx_xx is the ADC MUX P settings(6bits of reg ADCCON[5:0]). 03919 */ 03920 #define FIFO_SEQID(data) ((((uint32_t)data)>>23)&0x3) /**< Return seqid of this FIFO result */ 03921 #define FIFO_ECC(data) ((((uint32_t)data)>>25)&0x7f) /**< Return ECC of this FIFO result */ 03922 #define FIFO_CHANID(data) ((((uint32_t)data)>>16)&0x7f) /**< Return Channel ID */ 03923 #define FIFOCHANID_MUXP(data) ((((uint32_t)data)>>16)&0x3f) /**< Return the ADC MUXP selection */ 03924 03925 #define ISCHANID_DFT(data) ((((((uint32_t)data)>>18)&0x1f)==0x1f)?bTRUE:bFALSE) /**< If the channel id is DFT */ 03926 #define ISCHANID_MEAN(data) ((((((uint32_t)data)>>18)&0x1f)==0x1e)?bTRUE:bFALSE) /**< If the channel id is MEAN */ 03927 #define ISCHANID_VAR(data) ((((((uint32_t)data)>>18)&0x1f)==0x1d)?bTRUE:bFALSE) /**< If the channel id is Variance */ 03928 #define ISCHANID_SINC3(data) ((((((uint32_t)data)>>18)&0x1f)< 0x10)?bTRUE:bFALSE) /**< If the channel id is SINC3 */ 03929 #define ISCHANID_NOTCH(data) ((((((uint32_t)data)>>18)&0x1f)>=0x10)&&(((((uint32_t)data>>18)&0x1f) < 0x1d)?bTRUE:bFALSE)) /**< If the channel id is Notch */ 03930 /** @} */ 03931 03932 /** 03933 * @defgroup FIFOSIZE_Const 03934 * @brief Set FIFO size. 03935 * @warning The total available SRAM is 6kB. It's shared by FIFO and sequencer. 03936 * @{ 03937 */ 03938 #define FIFOSIZE_32B 0 /**< The selfbuild in 32Byte for data FIFO. All 6kB SRAM for sequencer */ 03939 #define FIFOSIZE_2KB 1 /**< DATA FIFO use 2kB. The reset 4kB is used for sequencer */ 03940 #define FIFOSIZE_4KB 2 /**< 4kB for Data FIFO. 2kB for sequencer */ 03941 #define FIFOSIZE_6KB 3 /**< All 6kB for Data FIFO. Build in 32Bytes memory for sequencer */ 03942 /** @} */ 03943 03944 /* Wake up timer */ 03945 /** 03946 * @defgroup WUPTENDSEQ_Const 03947 * @{ 03948 */ 03949 #define WUPTENDSEQ_A 0 /**< End at slot A */ 03950 #define WUPTENDSEQ_B 1 /**< End at slot B */ 03951 #define WUPTENDSEQ_C 2 /**< End at slot C */ 03952 #define WUPTENDSEQ_D 3 /**< End at slot D */ 03953 #define WUPTENDSEQ_E 4 /**< End at slot E */ 03954 #define WUPTENDSEQ_F 5 /**< End at slot F */ 03955 #define WUPTENDSEQ_G 6 /**< End at slot G */ 03956 #define WUPTENDSEQ_H 7 /**< End at slot H */ 03957 /** @} */ 03958 03959 /** 03960 * @} End of sequencer_and_FIFO block 03961 * @} Sequencer_FIFO 03962 * */ 03963 03964 /** 03965 * @addtogroup MISC_Block 03966 * @{ 03967 * @defgroup MISC_Block_Const 03968 * @brief This block includes clock, GPIO, configuration. 03969 * @{ 03970 */ 03971 03972 /* Helper for calculate clocks needed for various of data type */ 03973 /** 03974 * @defgroup DATATYPE_Const 03975 * @{ 03976 */ 03977 #define DATATYPE_ADCRAW 0 /**< ADC raw data */ 03978 #define DATATYPE_SINC3 1 /**< SINC3 data */ 03979 #define DATATYPE_SINC2 2 /**< SINC2 Data */ 03980 #define DATATYPE_DFT 3 /**< DFT */ 03981 #define DATATYPE_NOTCH 4 /**< Notch filter output. (when notch is not bypassed) */ 03982 //#define DATATYPE_MEAN 03983 /** @} */ 03984 03985 03986 /** 03987 * @defgroup SLPKEY_Const 03988 * @{ 03989 */ 03990 #define SLPKEY_LOCK 0 /**< any incorrect value will lock the key */ 03991 #define SLPKEY_UNLOCK 0xa47e5 /**< The correct key for register SEQSLPLOCK */ 03992 /** @} */ 03993 03994 /** 03995 * @defgroup HPOSCOUT_Const 03996 * @brief Set HPOSC output clock frequency, 16MHz or 32MHz. 03997 * @{ 03998 */ 03999 #define HPOSCOUT_32MHZ 0 /**< Configure internal HFOSC output 32MHz clock */ 04000 #define HPOSCOUT_16MHZ 1 /**< 16MHz Clock */ 04001 /** @} */ 04002 04003 /* GPIO */ 04004 /** 04005 * @defgroup AGPIOPIN_Const 04006 * @brief The pin masks for register GP0OEN, GP0PE, GP0IEN,..., GP0TGL 04007 * @{ 04008 */ 04009 #define AGPIO_Pin0 0x01 /**< AFE GPIO0, only available on AD5940 and AD5941, not ADuCM355 */ 04010 #define AGPIO_Pin1 0x02 /**< AFE GPIO1, only available on AD5940 and AD5941, not ADuCM355 */ 04011 #define AGPIO_Pin2 0x04 /**< AFE GPIO2, only available on AD5940 and AD5941, not ADuCM355 */ 04012 #define AGPIO_Pin3 0x08 /**< AFE GPIO3, only available on AD5941. */ 04013 #define AGPIO_Pin4 0x10 /**< AFE GPIO4, only available on AD5941. */ 04014 #define AGPIO_Pin5 0x20 /**< AFE GPIO5, only available on AD5941. */ 04015 #define AGPIO_Pin6 0x40 /**< AFE GPIO6, only available on AD5941. */ 04016 #define AGPIO_Pin7 0x80 /**< AFE GPIO7, only available on AD5941. */ 04017 /** @} */ 04018 04019 /** 04020 * @defgroup GP0FUNC_Const 04021 * @{ 04022 */ 04023 #define GP0_INT 0 /**< Interrupt Controller 0 output */ 04024 #define GP0_TRIG 1 /**< Sequence0 trigger */ 04025 #define GP0_SYNC 2 /**< Use Sequencer to controll GP0 output level */ 04026 #define GP0_GPIO 3 /**< Normal GPIO function */ 04027 /** @} */ 04028 04029 /** 04030 * @defgroup GP1FUNC_Const 04031 * @{ 04032 */ 04033 #define GP1_GPIO (0<<2) /**< Normal GPIO function */ 04034 #define GP1_TRIG (1<<2) /**< Sequence1 trigger */ 04035 #define GP1_SYNC (2<<2) /**< Use Sequencer to controll GP1 output level */ 04036 #define GP1_SLEEP (3<<2) /**< Internal Sleep Signal */ 04037 /** @} */ 04038 04039 /** 04040 * @defgroup GP2FUNC_Const 04041 * @{ 04042 */ 04043 #define GP2_PORB (0<<4) /**< Internal Power ON reset signal */ 04044 #define GP2_TRIG (1<<4) /**< Sequence1 trigger */ 04045 #define GP2_SYNC (2<<4) /**< Use Sequencer to controll GP2 output level */ 04046 #define GP2_EXTCLK (3<<4) /**< External Clock input(32kHz/16MHz/32MHz) */ 04047 /** @} */ 04048 04049 /** 04050 * @defgroup GP3FUNC_Const 04051 * @{ 04052 */ 04053 #define GP3_GPIO (0<<6) /**< Normal GPIO function */ 04054 #define GP3_TRIG (1<<6) /**< Sequence3 trigger */ 04055 #define GP3_SYNC (2<<6) /**< Use Sequencer to controll GP3 output level */ 04056 #define GP3_INT0 (3<<6) /**< Interrupt Controller 0 output */ 04057 /** @} */ 04058 04059 /** 04060 * @defgroup GP4FUNC_Const 04061 * @note GP4 (Not available on AD5941) 04062 * @{ 04063 */ 04064 #define GP4_GPIO (0<<8) /**< Normal GPIO function */ 04065 #define GP4_TRIG (1<<8) /**< Sequence0 trigger */ 04066 #define GP4_SYNC (2<<8) /**< Use Sequencer to controll GP4 output level */ 04067 #define GP4_INT1 (3<<8) /**< Interrupt Controller 1 output */ 04068 /** @} */ 04069 04070 /** 04071 * @defgroup GP5FUNC_Const 04072 * @note GP5 (Not available on AD5941) 04073 * @{ 04074 */ 04075 #define GP5_GPIO (0<<10) /**< Internal Power ON reset signal */ 04076 #define GP5_TRIG (1<<10) /**< Sequence1 trigger */ 04077 #define GP5_SYNC (2<<10) /**< Use Sequencer to controll GP5 output level */ 04078 #define GP5_EXTCLK (3<<10) /**< External Clock input(32kHz/16MHz/32MHz) */ 04079 /** @} */ 04080 04081 /** 04082 * @defgroup GP6FUNC_Const 04083 * @note GP6 (Not available on AD5941) 04084 * @{ 04085 */ 04086 #define GP6_GPIO (0<<12) /**< Normal GPIO function */ 04087 #define GP6_TRIG (1<<12) /**< Sequence2 trigger */ 04088 #define GP6_SYNC (2<<12) /**< Use Sequencer to controll GP6 output level */ 04089 #define GP6_INT0 (3<<12) /**< Interrupt Controller 0 output */ 04090 /** @} */ 04091 04092 /** 04093 * @defgroup GP7FUNC_Const 04094 * @note GP7 (Not available on AD5941) 04095 * @{ 04096 */ 04097 #define GP7_GPIO (0<<14) /**< Normal GPIO function */ 04098 #define GP7_TRIG (1<<14) /**< Sequence2 trigger */ 04099 #define GP7_SYNC (2<<14) /**< Use Sequencer to controll GP7 output level */ 04100 #define GP7_INT (3<<14) /**< Interrupt Controller 1 output */ 04101 /** @} */ 04102 04103 //LPModeClk 04104 /** 04105 * @defgroup LPMODECLK_Const 04106 * @{ 04107 */ 04108 #define LPMODECLK_HFOSC 0 /**< Use HFOSC 16MHz/32MHz clock as system clock */ 04109 #define LPMODECLK_LFOSC 1 /**< Use LFOSC 32kHz clock as system clock */ 04110 /** @} */ 04111 04112 /* Clock */ 04113 /** 04114 * @defgroup SYSCLKSRC_Const 04115 * @brief Select system clock source. The clock must be available. If unavailable clock is selected, we can reset AD5940. 04116 * The system clock should be limited to 32MHz. If external clock or XTAL is faster than 16MHz, we use system clock divider to ensure it's always in range of 16MHz. 04117 * @warning Maximum SPI clock has relation with system clock. Limit the SPI clock to ensure SPI clock is slower than system clock. 04118 * @{ 04119 */ 04120 #define SYSCLKSRC_HFOSC 0 /**< Internal HFOSC. CLock is 16MHz or 32MHz configurable. Set clock divider to ensure system clock is always 16MHz */ 04121 #define SYSCLKSRC_XTAL 1 /**< External crystal. It can be 16MHz or 32MHz.Set clock divider to ensure system clock is always 16MHz */ 04122 #define SYSCLKSRC_LFOSC 2 /**< Internal 32kHz clock. Note the SPI clock also sourced with 32kHz so the register read/write frequency is lower down. */ 04123 #define SYSCLKSRC_EXT 3 /**< External clock from GPIO, AD594x Only */ 04124 /** @} */ 04125 04126 /** 04127 * @defgroup ADCCLKSRC_Const 04128 * @brief Select ADC clock source. 04129 * The maximum clock is 32MHz. 04130 * @warning The ADC raw data update rate is equal to ADCClock/20. When ADC clock is 32MHz, sample rate is 1.6MSPS. 04131 * The SINC3 filter clock are sourced from ADC clock and should be limited to 16MHz. When ADC clock is set to 32MHz. Clear bit ADCFILTERCON.BIT0 04132 * to enable the SINC3 clock divider. 04133 * @{ 04134 */ 04135 #define ADCCLKSRC_HFOSC 0 /**< Internal HFOSC. 16MHz or 32MHz which is configurable */ 04136 #define ADCCLKSRC_XTAL 1 /**< External crystal. Set ADC clock divider to get either 16MHz or 32MHz clock */ 04137 //#define ADCCLKSRC_LFOSC 2 /**< Do not use */ 04138 #define ADCCLKSRC_EXT 3 /**< External clock from GPIO. Set ADC clock divider to get the clock you want */ 04139 /** @} */ 04140 04141 04142 /** 04143 * @defgroup ADCCLKDIV_Const 04144 * @brief The divider for ADC clock. ADC clock = ClockSrc/Divider. 04145 * @{ 04146 */ 04147 #define ADCCLKDIV_1 1 /**< Divider ADCClk = ClkSrc/1 */ 04148 #define ADCCLKDIV_2 2 /**< Divider ADCClk = ClkSrc/2 */ 04149 /** @} */ 04150 04151 /** 04152 * @defgroup SYSCLKDV_Const 04153 * @brief The divider for system clock. System clock = ClockSrc/Divider. 04154 * @{ 04155 */ 04156 #define SYSCLKDIV_1 1 /**< Divider SysClk = ClkSrc/1 */ 04157 #define SYSCLKDIV_2 2 /**< Divider SysClk = ClkSrc/2 */ 04158 /** @} */ 04159 04160 /** 04161 * @defgroup PGACALTYPE_Const 04162 * @brief Calibration Type 04163 * @{ 04164 */ 04165 #define PGACALTYPE_OFFSET 0 /**< Calibrate offset */ 04166 #define PGACALTYPE_GAIN 1 /**< Calibrate gain */ 04167 #define PGACALTYPE_OFFSETGAIN 2 /**< Calibrate offset and gain */ 04168 /** @} */ 04169 04170 /** 04171 * @defgroup AD5940ERR_Const 04172 * @brief AD5940 error code used by library and example codes. 04173 * @{ 04174 */ 04175 #define AD5940ERR_OK 0 /**< No error */ 04176 #define AD5940ERR_ERROR -1 /**< General error message */ 04177 #define AD5940ERR_PARA -2 /**< Parameter is illegal */ 04178 #define AD5940ERR_NULLP -3 /**< Null pointer */ 04179 #define AD5940ERR_BUFF -4 /**< Buffer limited. */ 04180 #define AD5940ERR_ADDROR -5 /**< Out of Range. Register address is out of range. */ 04181 #define AD5940ERR_SEQGEN -6 /**< Sequence generator error */ 04182 #define AD5940ERR_SEQREG -7 /**< Register info is not found */ 04183 #define AD5940ERR_SEQLEN -8 /**< Sequence length is too long. */ 04184 #define AD5940ERR_WAKEUP -9 /**< Unable to wakeup AFE in specified time */ 04185 #define AD5940ERR_TIMEOUT -10 /**< Time out error. */ 04186 #define AD5940ERR_CALOR -11 /**< calibration out of range. */ 04187 #define AD5940ERR_APPERROR -100 /**< Used in example code to indicated the application has not been initialized. */ 04188 /** @} */ 04189 04190 #ifndef NULL 04191 #define NULL (void *) 0 /**< Null, if it's not defined. */ 04192 #endif 04193 #define MATH_PI 3.1415926f /**< Pi defination. */ 04194 04195 #define AD5940_ADIID 0x4144 /**< ADIID is fixed to 0x4144 */ 04196 #define AD5940_CHIPID 0x0000 /**< CHIPID is changing with silicon version */ 04197 #define M355_ADIID 0x4144 /**< ADIID is fixed to 0x4144 */ 04198 #define M355_CHIPID 0x0000 /**< CHIPID is changing with silicon version */ 04199 04200 #define AD5940_SWRST 0xa158 /**< AD594x only. The value to perform software reset via reigster SWRSTCON */ 04201 #define KEY_OSCCON 0xcb14 /**< key of register OSCCON. The key is auto locked after writing to any other register */ 04202 #define KEY_CALDATLOCK 0xde87a5af /**< Calibration key. */ 04203 #define KEY_LPMODEKEY 0xc59d6 /**< LP mode key */ 04204 04205 #define PARA_CHECK(n) /** add parameter check, Add DEBUG switch */ 04206 04207 /** 04208 * @} MISC_Block_Const 04209 * @} MISC_Block 04210 * */ 04211 /** 04212 * @defgroup TypeDefinitions 04213 * @{ 04214 */ 04215 04216 typedef int32_t AD5940Err; /**< error number defination */ 04217 04218 /** 04219 * bool definition for ad5940lib. 04220 */ 04221 typedef enum 04222 { 04223 bFALSE = 0, bTRUE = !bFALSE, /**< True and False definition*/ 04224 }BoolFlag; 04225 04226 typedef struct 04227 { 04228 /* ADC/DAC/TIA reference and buffer */ 04229 BoolFlag HpBandgapEn; /**< Enable High power band-gap. Clear bit AFECON.HPREFDIS will enable Bandgap, while set this bit will disable bandgap */ 04230 BoolFlag Hp1V8BuffEn; /**< High power 1.8V reference buffer enable */ 04231 BoolFlag Hp1V1BuffEn; /**< High power 1.1V reference buffer enable */ 04232 BoolFlag Lp1V8BuffEn; /**< Low power 1.8V reference buffer enable */ 04233 BoolFlag Lp1V1BuffEn; /**< Low power 1.1V reference buffer enable */ 04234 /* Low bandwidth loop reference and buffer */ 04235 BoolFlag LpBandgapEn; /**< Enable Low power band-gap. */ 04236 BoolFlag LpRefBufEn; /**< Enable the 2.5V low power reference buffer */ 04237 BoolFlag LpRefBoostEn; /**< Boost buffer current */ 04238 /* DAC Reference Buffer */ 04239 BoolFlag HSDACRefEn; /**< Enable DAC reference buffer from HP Bandgap */ 04240 /* Misc. control */ 04241 BoolFlag Hp1V8ThemBuff; /**< Thermal Buffer for internal 1.8V reference to AIN3 pin */ 04242 BoolFlag Hp1V8Ilimit; /**< Current limit for High power 1.8V reference buffer */ 04243 BoolFlag Disc1V8Cap; /**< Discharge 1.8V capacitor. Short external 1.8V decouple capacitor to ground. Be careful when use this bit */ 04244 BoolFlag Disc1V1Cap; /**< Discharge 1.1V capacitor. Short external 1.1V decouple capacitor to ground. Be careful when use this bit */ 04245 }AFERefCfg_Type; 04246 04247 /** 04248 * @defgroup ADC_BlockType 04249 * @{ 04250 */ 04251 04252 /** 04253 * Structure for ADC Basic settings include MUX and PGA. 04254 */ 04255 typedef struct 04256 { 04257 uint32_t ADCMuxP; /**< ADC Positive input channel selection. select from @ref ADCMUXP */ 04258 uint32_t ADCMuxN; /**< ADC negative input channel selection. select from @ref ADCMUXN */ 04259 uint32_t ADCPga; /**< ADC PGA settings, select from @ref ADCPGA */ 04260 }ADCBaseCfg_Type; 04261 04262 /** 04263 * Structure for ADC filter settings. 04264 */ 04265 typedef struct 04266 { 04267 uint32_t ADCSinc3Osr; 04268 uint32_t ADCSinc2Osr; 04269 uint32_t ADCAvgNum; /**< Average filter is enabled when DFT source is @ref DFTSRC_AVG in function @ref AD5940_DFTCfgS. This average filter is only used by DFT engine. */ 04270 uint32_t ADCRate; /**< ADC Core sample rate */ 04271 BoolFlag BpNotch; /**< Bypass Notch filter in SINC2+Notch block, so only SINC2 is used. ADCFILTERCON.BIT4 */ 04272 BoolFlag BpSinc3; /**< Bypass SINC3 Module */ 04273 BoolFlag Sinc2NotchEnable; /**< Enable SINC2+Notch block */ 04274 }ADCFilterCfg_Type; 04275 /** @} */ 04276 04277 /** 04278 * DFT Configuration structure. 04279 */ 04280 typedef struct 04281 { 04282 uint32_t DftNum; /**< DFT number */ 04283 uint32_t DftSrc; /**< DFT Source */ 04284 BoolFlag HanWinEn; /**< Enable Hanning window */ 04285 }DFTCfg_Type; 04286 04287 /** 04288 * ADC digital comparator 04289 */ 04290 typedef struct 04291 { 04292 uint16_t ADCMin; /**< The ADC code minimum limit value */ 04293 uint16_t ADCMinHys; 04294 uint16_t ADCMax; /**< The ADC code maximum limit value */ 04295 uint16_t ADCMaxHys; 04296 }ADCDigComp_Type; 04297 04298 /** 04299 * Statistic function 04300 */ 04301 typedef struct 04302 { 04303 uint32_t StatDev; /**< Statistic standard deviation configure */ 04304 uint32_t StatSample; /**< Sample size */ 04305 BoolFlag StatEnable; /**< Set true to enable statistic block */ 04306 }StatCfg_Type; 04307 04308 /** 04309 * Switch matrix configure */ 04310 typedef struct 04311 { 04312 uint32_t Dswitch; /**< D switch settings. Select from @ref SWD_Const*/ 04313 uint32_t Pswitch; /**< P switch settings. Select from @ref SWP_Const */ 04314 uint32_t Nswitch; /**< N switch settings. Select from @ref SWN_Const */ 04315 uint32_t Tswitch; /**< T switch settings. Select from @ref SWT_Const */ 04316 }SWMatrixCfg_Type; 04317 04318 /** HSTIA Configure */ 04319 typedef struct 04320 { 04321 uint32_t HstiaBias; /**< When select Vzero as bias, the related switch(VZERO2HSTIA) at LPDAC should be closed */ 04322 uint32_t HstiaRtiaSel; /**< RTIA selection @ref HSTIARTIA_Const */ 04323 uint32_t HstiaCtia; /**< Set internal CTIA value from 1 to 32 pF */ 04324 BoolFlag DiodeClose; /**< Close the switch for internal back to back diode */ 04325 uint32_t HstiaDeRtia; /**< DE0 node RTIA selection @ref HSTIADERTIA_Const */ 04326 uint32_t HstiaDeRload; /**< DE0 node Rload selection @ref HSTIADERLOAD_Const */ 04327 uint32_t HstiaDe1Rtia; /**< (ADuCM355 only, ignored on AD594x)DE1 node RTIA selection @ref HSTIADERTIA_Const */ 04328 uint32_t HstiaDe1Rload; /**< (ADuCM355 only)DE1 node Rload selection @ref HSTIADERLOAD_Const */ 04329 }HSTIACfg_Type; 04330 04331 /** HSDAC Configure */ 04332 typedef struct 04333 { 04334 uint32_t ExcitBufGain; /**< Select from EXCITBUFGAIN_2, EXCITBUFGAIN_0P25 */ 04335 uint32_t HsDacGain; /**< Select from HSDACGAIN_1, HSDACGAIN_0P2 */ 04336 uint32_t HsDacUpdateRate; /**< Divider for DAC update. Available range is 7~255. */ 04337 }HSDACCfg_Type; 04338 04339 /** LPDAC Configure 04340 * @note The LPDAC structure: 04341 * @code 04342 * Switch to select DAC output to Vzero and Vbias nodes. Vzero and Vbias can select from DAC6BIT and DAC12BIT output freely. 04343 * LPDAC >DAC6BIT ---- Vzero LPDACVZERO_12BIT 04344 * \--- Vbias LPDACVBIAS_6BIT 04345 * >DAC12BIT---- Vzero LPDACVZERO_6BIT 04346 * \--- Vbias LPDACVBIAS_12BIT 04347 * Vzero/Vbias switch, controlled by @ref LPDACCfg_Type LpDacSW 04348 * Vzero ------PIN 04349 * \-----LPTIA LPDACSW_VZERO2LPTIA. LPTIA positive input 04350 * \----HSTIA LPDACSW_VZERO2LPAMP. HSTIA positive input. Note, there is a MUX on HSTIA positive input pin to select the bias voltage between Vzero and 1.1V fixed internal reference. 04351 * Vbias ------PIN LPDACSW_VBIAS2PIN 04352 * \-----LPAMP LPDACSW_VBIAS2LPAMP positive input. The potential state amplifier input, or called LPAMP or PA(potential amplifier). 04353 * @endcode 04354 */ 04355 typedef struct 04356 { 04357 uint32_t LpdacSel; /**< Selectr from LPDAC0 or LPDAC1. LPDAC1 is only available on ADuCM355. */ 04358 uint32_t LpDacSrc; /**< LPDACSRC_MMR or LPDACSRC_WG. Note: HSDAC is always connects to WG. Disable HSDAC if there is need. */ 04359 uint32_t LpDacVzeroMux; /**< Select which DAC output connects to Vzero. 6Bit or 12Bit DAC */ 04360 uint32_t LpDacVbiasMux; /**< Select which DAC output connects to Vbias */ 04361 uint32_t LpDacSW; /**< LPDAC switch set. Only available from Si2 */ 04362 uint32_t LpDacRef; /**< Reference selection. Either internal 2.5V LPRef or AVDD. select from @ref LPDACREF_Const*/ 04363 BoolFlag DataRst; /**< Keep Reset register REG_AFE_LPDACDAT0DATA */ 04364 BoolFlag PowerEn; /**< Power up REG_AFE_LPDACDAT0 */ 04365 uint16_t DacData12Bit; /**< Data for 12bit DAC */ 04366 uint16_t DacData6Bit; /**< Data for 6bit DAC */ 04367 }LPDACCfg_Type; 04368 04369 /** 04370 * Low power amplifiers(PA and TIA) 04371 */ 04372 typedef struct 04373 { 04374 uint32_t LpAmpSel; /**< Select from LPAMP0 and LPAMP1. LPAMP1 is only available on ADuCM355. */ 04375 uint32_t LpTiaRf; /**< The one order RC filter resistor selection. Select from @ref LPTIARF_Const */ 04376 uint32_t LpTiaRload; /**< The Rload resistor right in front of LPTIA negative input terminal. Select from @ref LPTIARLOAD_Const*/ 04377 uint32_t LpTiaRtia; /**< LPTIA RTIA resistor selection. Set it to open(@ref LPTIARTIA_Const) when use external resistor. */ 04378 uint32_t LpAmpPwrMod; /**< Power mode for LP PA and LPTIA */ 04379 uint32_t LpTiaSW; /**< Set of switches, using macro LPTIASW() to close switch */ 04380 BoolFlag LpPaPwrEn; /**< Enable(bTRUE) or disable(bFALSE) power of PA(potential amplifier) */ 04381 BoolFlag LpTiaPwrEn; /**< Enable(bTRUE) or Disable(bFALSE) power of LPTIA amplifier */ 04382 }LPAmpCfg_Type; 04383 04384 /** 04385 * @brief Trapezoid Generator parameters 04386 * The definition of the Trapezoid waveform is shown below. Note the Delay and Slope are all in clock unit. 04387 * @code 04388 * 04389 * DCLevel2 _________ 04390 * / \ 04391 * / \ 04392 * DCLevel1 _____/ \______ 04393 * | | | | | 04394 * Delay1|S1|Delay2 |S2| Delay1 repeat... 04395 * Where S1 is slope1 and S2 is slop2 04396 * @endcode 04397 * The DAC update rate from Trapezoid generator is SystemClock/50. The default SystemClock 04398 * is internal HFOSC 16MHz. So the update rate is 320kHz. 04399 * The time parameter specifies in clock number. 04400 * For example, if Delay1 is set to 10, S1 is set 20, the time for Delay1 period is 10/320kHz = 31.25us, 04401 * and time for S1 period is 20/320kHz = 62.5us. 04402 */ 04403 typedef struct 04404 { 04405 uint32_t WGTrapzDCLevel1; /**< Trapezoid generator DC level1, this value is written directly to corresponding register */ 04406 uint32_t WGTrapzDCLevel2; /**< DC level2, similar to DCLevel1 */ 04407 uint32_t WGTrapzDelay1; /**< Trapezoid generator delay 1 */ 04408 uint32_t WGTrapzDelay2; /**< Trapezoid generator delay 2 */ 04409 uint32_t WGTrapzSlope1; /**< Trapezoid generator Slope 1 */ 04410 uint32_t WGTrapzSlope2; /**< Trapezoid generator Slope 2 */ 04411 }WGTrapzCfg_Type; 04412 04413 /** 04414 * Sin wave generator parameters 04415 */ 04416 typedef struct 04417 { 04418 uint32_t SinFreqWord; /**< Frequency word */ 04419 uint32_t SinAmplitudeWord; /**< Amplitude word, range is 0 to 2047 */ 04420 uint32_t SinOffsetWord; /**< Offset word, range is 0 to 4095 */ 04421 uint32_t SinPhaseWord; /**< the start phase of sine wave. Use to tune start phase of signal. */ 04422 }WGSinCfg_Type; 04423 04424 /** 04425 * Waveform generator configuration 04426 */ 04427 typedef struct 04428 { 04429 uint32_t WgType; /**< Select from WGTYPE_MMR, WGTYPE_SIN, WGTYPE_TRAPZ. HSDAC is always connected to WG. */ 04430 BoolFlag GainCalEn; /**< Enable Gain calibration */ 04431 BoolFlag OffsetCalEn; /**< Enable offset calibration */ 04432 WGTrapzCfg_Type TrapzCfg; /**< Configure Trapezoid generator */ 04433 WGSinCfg_Type SinCfg; /**< Configure Sine wave generator */ 04434 uint32_t WgCode; /**< The 12bit data WG will move to DAC data register. */ 04435 }WGCfg_Type; 04436 04437 /** 04438 * High speed loop configuration 04439 * */ 04440 typedef struct 04441 { 04442 SWMatrixCfg_Type SWMatCfg; /**< switch matrix configuration. */ 04443 HSDACCfg_Type HsDacCfg; /**< HSDAC configuration. */ 04444 WGCfg_Type WgCfg; /**< Waveform generator configuration. */ 04445 HSTIACfg_Type HsTiaCfg; /**< HSTIA configuration. */ 04446 }HSLoopCfg_Type; 04447 04448 /** 04449 * Low power loop Configure 04450 * */ 04451 typedef struct 04452 { 04453 LPDACCfg_Type LpDacCfg; /**< LPDAC configuration. @note Must select LPDAC0 or LPDAC1 in structure. */ 04454 LPAmpCfg_Type LpAmpCfg; /**< LPAMP(LPTIA and PA) configuration. @note Must select LPAMP0 or LPAMP1 in structure. */ 04455 }LPLoopCfg_Type; 04456 04457 /** 04458 * DSP Configure 04459 * */ 04460 typedef struct 04461 { 04462 ADCBaseCfg_Type ADCBaseCfg; /**< ADC base configuration */ 04463 ADCFilterCfg_Type ADCFilterCfg; /**< ADC filter configuration include SINC3/SINC2/Notch/Average(for DFT only) */ 04464 ADCDigComp_Type ADCDigCompCfg; /**< ADC digital comparator */ 04465 DFTCfg_Type DftCfg; /**< DFT configuration include data source, DFT number and Hanning Window */ 04466 StatCfg_Type StatCfg; /**< Statistic block */ 04467 }DSPCfg_Type; 04468 04469 /** 04470 * GPIO Configure 04471 * */ 04472 typedef struct 04473 { 04474 uint32_t FuncSet; /**< AGP0 to AGP7 function sets */ 04475 uint32_t OutputEnSet; /**< AGPIO_Pin0|AGPIO_Pin1|...|AGPIO_Pin7, Enable output of selected pins, disable other pins */ 04476 uint32_t InputEnSet; /**< Enable input of selected pins, disable other pins */ 04477 uint32_t PullEnSet; /**< Enable pull up or down on selected pin. disable other pins */ 04478 uint32_t OutVal; /**< Value for GPIOOUT register */ 04479 }AGPIOCfg_Type; 04480 04481 /** 04482 * FIFO configure 04483 */ 04484 typedef struct 04485 { 04486 BoolFlag FIFOEn; /**< Enable DATAFIFO. Disable FIFO will reset FIFO */ 04487 uint32_t FIFOMode; /**< Stream mode or standard FIFO mode */ 04488 uint32_t FIFOSize; /**< How to allocate the internal 6kB SRAM. Data FIFO and sequencer share all 6kB SRAM */ 04489 uint32_t FIFOSrc; /**< Select which data source will be stored to FIFO */ 04490 uint32_t FIFOThresh; /**< FIFO threshold value, 0 to 1023. Threshold can be used to generate interrupt so MCU can read back data before FIFO is full */ 04491 }FIFOCfg_Type; 04492 04493 /** 04494 * Sequencer configure 04495 */ 04496 typedef struct 04497 { 04498 uint32_t SeqMemSize; /**< Sequencer memory size. SRAM is used by both FIFO and Sequencer. Make sure the total SRAM used is less than 6kB. */ 04499 BoolFlag SeqEnable; /**< Enable sequencer. Only with valid trigger, sequencer can run */ 04500 BoolFlag SeqBreakEn; /**< Do not use it */ 04501 BoolFlag SeqIgnoreEn; /**< Do not use it */ 04502 BoolFlag SeqCntCRCClr; /**< Clear sequencer count and CRC */ 04503 uint32_t SeqWrTimer; /**< Set wait how much clocks after every commands executed */ 04504 }SEQCfg_Type; 04505 04506 /** 04507 * Sequence info structure 04508 */ 04509 typedef struct 04510 { 04511 uint32_t SeqId; /**< The Sequence ID @ref SEQID_Const */ 04512 uint32_t SeqRamAddr; /**< The start address that in AF5940 SRAM */ 04513 uint32_t SeqLen; /**< Sequence length */ 04514 BoolFlag WriteSRAM; /**< Write command to SRAM or not. */ 04515 const uint32_t *pSeqCmd; /**< Pointer to the sequencer commands that stored in MCU */ 04516 }SEQInfo_Type; 04517 04518 typedef struct 04519 { 04520 uint32_t PinSel; /**< Select which pin are going to be configured. @ref AGPIOPIN_Const */ 04521 uint32_t SeqPinTrigMode; /**< The pin detect mode. Select from @ref SEQPINTRIGMODE_Const */ 04522 BoolFlag bEnable; /**< Allow detected pin action to trigger corresponding sequence. */ 04523 }SeqGpioTrig_Cfg; 04524 04525 /** 04526 * Wakeup Timer Configure 04527 * */ 04528 typedef struct 04529 { 04530 uint32_t WuptEndSeq; /**< end sequence selection @ref WUPTENDSEQ_Const. Wupt will go back to slot A after this one is executed. */ 04531 uint32_t WuptOrder[8]; /**< The 8 slots for WakeupTimer. Place @ref SEQID_Const to this array. */ 04532 uint32_t SeqxSleepTime[4]; /**< Time before put AFE to sleep. 0 to 0x000f_ffff. We normally don't use this feature and it's disabled in @ref AD5940_Initialize */ 04533 uint32_t SeqxWakeupTime[4]; /**< Time before Wakeup AFE. */ 04534 BoolFlag WuptEn; /**< Timer enable. Once enabled, it starts to run. */ 04535 }WUPTCfg_Type; 04536 04537 /** 04538 * Clock configure 04539 */ 04540 typedef struct 04541 { 04542 uint32_t SysClkSrc; /**< System clock source @ref SYSCLKSRC_Const */ 04543 uint32_t ADCCLkSrc; /**< ADC clock source @ref ADCCLKSRC_Const */ 04544 uint32_t SysClkDiv; /**< System clock divider. Use this to ensure System clock < 16MHz. */ 04545 uint32_t ADCClkDiv; /**< ADC control clock divider. ADC core clock is @ADCCLkSrc, but control clock should be <16MHz. */ 04546 BoolFlag HFOSCEn; /**< Enable internal 16MHz/32MHz HFOSC */ 04547 BoolFlag HfOSC32MHzMode; /**< Enable internal HFOSC to output 32MHz */ 04548 BoolFlag LFOSCEn; /**< Enable internal 32kHZ OSC */ 04549 BoolFlag HFXTALEn; /**< Enable XTAL driver */ 04550 }CLKCfg_Type; 04551 04552 /** 04553 * HSTIA internal RTIA calibration structure 04554 * @note ADC filter settings and DFT should be configured properly based on signal frequency. 04555 */ 04556 typedef struct 04557 { 04558 float fFreq; /**< Calibration frequency */ 04559 float fRcal; /**< Rcal resistor value in Ohm*/ 04560 float SysClkFreq; /**< The real frequency of system clock */ 04561 float AdcClkFreq; /**< The real frequency of ADC clock */ 04562 04563 HSTIACfg_Type HsTiaCfg; /**< HSTIA configuration */ 04564 uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ 04565 uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ 04566 DFTCfg_Type DftCfg; /**< DFT configuration. */ 04567 uint32_t bPolarResult; /**< bTRUE-Polar coordinate:Return results in Magnitude and Phase. bFALSE-Cartesian coordinate: Return results in Real part and Imaginary Part */ 04568 }HSRTIACal_Type; 04569 04570 /** 04571 * LPTIA internal RTIA calibration structure 04572 */ 04573 typedef struct 04574 { 04575 float fFreq; /**< Calibration frequency. Set it to 0.0 for DC calibration */ 04576 float fRcal; /**< Rcal resistor value in Ohm*/ 04577 float SysClkFreq; /**< The real frequency of system clock */ 04578 float AdcClkFreq; /**< The real frequency of ADC clock */ 04579 04580 uint32_t LpAmpSel; /**< Select from LPAMP0 and LPAMP1. LPAMP1 is only available on ADuCM355. */ 04581 BoolFlag bWithCtia; /**< Connect external CTIA or not. */ 04582 uint32_t LpTiaRtia; /**< LPTIA RTIA selection. */ 04583 uint32_t LpAmpPwrMod; /**< Amplifiers power mode setting */ 04584 uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ 04585 uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ 04586 DFTCfg_Type DftCfg; /**< DFT configuration */ 04587 uint32_t bPolarResult; /**< bTRUE-Polar coordinate:Return results in Magnitude and Phase. bFALSE-Cartesian coordinate: Return results in Real part and Imaginary Part */ 04588 }LPRTIACal_Type; 04589 04590 /** 04591 * HSDAC calibration structure. 04592 */ 04593 typedef struct 04594 { 04595 float fRcal; /**< Rcal resistor value in Ohm*/ 04596 float SysClkFreq; /**< The real frequency of system clock */ 04597 float AdcClkFreq; /**< The real frequency of ADC clock */ 04598 04599 uint32_t AfePwrMode; /**< Calibrate DAC in High power mode */ 04600 uint32_t ExcitBufGain; /**< Select from EXCITBUFGAIN_2, EXCITBUFGAIN_0P25 */ 04601 uint32_t HsDacGain; /**< Select from HSDACGAIN_1, HSDACGAIN_0P2 */ 04602 04603 uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ 04604 uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ 04605 }HSDACCal_Type; 04606 04607 /** 04608 * LPDAC calibration structure. 04609 */ 04610 typedef struct 04611 { 04612 uint32_t LpdacSel; /**< Select from LPDAC0 and LPDAC1. LPDAC1 is ADuCM355 only. */ 04613 float SysClkFreq; /**< The real frequency of system clock */ 04614 float AdcClkFreq; /**< The real frequency of ADC clock */ 04615 float ADCRefVolt; /**< ADC reference voltage. Default is 1.82V*/ 04616 uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ 04617 uint32_t ADCSinc2Osr; /**< SINC2 OSR settings. */ 04618 int32_t SettleTime10us; /**< Wait how much time after TIA is enabled? */ 04619 int32_t TimeOut10us; /**< ADC converts signal need time. Specify the maximum time allowed. Timeout in 10us. negative number means wait no time. */ 04620 }LPDACCal_Type; 04621 04622 /** 04623 * LPDAC parameters: LPDAC code to voltage transfer function. 04624 * Voltage(mV) = kC2V_DACxB * Code + bC2V_DACxB; 04625 * where x is 12 or 6 represent 12Bit DAC and 6Bit DAC. C2V means code to voltage. 04626 * Code is the data register value for LPDAC. The equation gives real output voltage of LPDAC. 04627 * Similarly, Code(LSB) = kV2C_DACxB * Voltage(mV) + bC2V_DAC12B; 04628 * 04629 * Apparently, kV2C_DACxB = 1/kC2V_DACxB; 04630 * bC2V_DACxB = -bC2V_DACxB/kC2V_DACxB; 04631 */ 04632 typedef struct 04633 { 04634 /* Code to voltage equation parameters */ 04635 float kC2V_DAC12B; /**< the k factor of code to voltage(in mV) transfer function */ 04636 float bC2V_DAC12B; /**< the offset of code to voltage transfer function. It's the voltage in mV when code is zero. */ 04637 float kC2V_DAC6B; /**< the k factor for LPDAC 6 bit output. */ 04638 float bC2V_DAC6B; /**< the offset for LPDAC 6 bit output. */ 04639 /* Code to voltage equation parameters */ 04640 float kV2C_DAC12B; /**< the k factor for converting voltage to code for LPDAC 12bit output. */ 04641 float bV2C_DAC12B; /**< the offset for converting voltage to code for LPDAC 12bit output. */ 04642 float kV2C_DAC6B; /**< the k factor for converting voltage to code for LPDAC 6bit output. */ 04643 float bV2C_DAC6B; /**< the offset for converting voltage to code for LPDAC 6bit output. */ 04644 }LPDACPara_Type; 04645 04646 /** 04647 * LFOSC frequency measure structure 04648 */ 04649 typedef struct 04650 { 04651 uint32_t CalSeqAddr; /**< Sequence start address */ 04652 float CalDuration; /**< Time can be used for calibration in unit of ms. Recommend to use tens of millisecond like 10ms */ 04653 float SystemClkFreq; /**< System clock frequency. */ 04654 }LFOSCMeasure_Type; 04655 04656 /** 04657 * ADC PGA calibration type 04658 */ 04659 typedef struct 04660 { 04661 float SysClkFreq; /**< The real frequency of system clock */ 04662 float AdcClkFreq; /**< The real frequency of ADC clock */ 04663 float VRef1p82; /**< The real voltage of 1.82 reference. Unit is volt. */ 04664 float VRef1p11; /**< The real voltage of 1.1 reference. Unit is volt. */ 04665 uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ 04666 uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ 04667 uint32_t ADCPga; /**< Which PGA gain we are going to calibrate? */ 04668 uint32_t PGACalType; /**< Calibrate gain of offset or gain+offset? */ 04669 int32_t TimeOut10us; /**< Timeout in 10us. -1 means no time-out*/ 04670 }ADCPGACal_Type; 04671 04672 /** 04673 * LPTIA Offset calibration type 04674 */ 04675 typedef struct 04676 { 04677 uint32_t LpAmpSel; /**< Select from LPAMP0 and LPAMP1. LPAMP1 is only available on ADuCM355. */ 04678 float SysClkFreq; /**< The real frequency of system clock */ 04679 float AdcClkFreq; /**< The real frequency of ADC clock */ 04680 uint32_t ADCSinc3Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ 04681 uint32_t ADCSinc2Osr; /**< SINC3OSR_5, SINC3OSR_4 or SINC3OSR_2 */ 04682 uint32_t ADCPga; /**< PGA Gain selection */ 04683 uint32_t DacData12Bit; /**< 12Bit DAC data */ 04684 uint32_t DacData6Bit; /**< 6Bit DAC data */ 04685 uint32_t LpDacVzeroMux; /**< Vzero is used as LPTIA bias voltage, select 12Bit/6Bit DAC */ 04686 uint32_t LpAmpPwrMod; /**< LP amplifiers power mode, select from LPAMPPWR_NORM, LPAMPPWR_BOOSTn*/ 04687 uint32_t LpTiaSW; /**< Switch configuration for LPTIA. Normally for SW(5) and SW(9).*/ 04688 uint32_t LpTiaRtia; /**< LPTIA RTIA resistor selection. */ 04689 int32_t SettleTime10us; /**< Wait how much time after TIA is enabled? */ 04690 int32_t TimeOut10us; /**< ADC converts signal need time. Specify the maximum time allowed. Timeout in 10us. negative number means wait no time. */ 04691 }LPTIAOffsetCal_Type; 04692 04693 /** 04694 * Structure for calculating how much system clocks needed for specified number of data 04695 */ 04696 typedef struct 04697 { 04698 uint32_t DataType; /**< The final data output selection. @ref DATATYPE_Const */ 04699 uint32_t DataCount; /**< How many data you want. */ 04700 uint32_t ADCSinc3Osr; /**< ADC SINC3 filter OSR setting */ 04701 uint32_t ADCSinc2Osr; /**< ADC SINC2 filter OSR setting */ 04702 uint32_t ADCAvgNum; /**< Average number for DFT engine. Only used when data type is DATATYPE_DFT and DftSrc is DFTSRC_AVG */ 04703 uint32_t DftSrc; /**< The DFT source. Only used when data type is DATATYPE_DFT */ 04704 uint8_t ADCRate; /**< ADCRate @ref ADCRATE_Const. Only used when data type is DATATYPE_NOTCH */ 04705 BoolFlag BpNotch; /**< Bypass notch filter or not. Only used when data type is DATATYPE_DFT and DftSrc is DFTSRC_SINC2NOTCH */ 04706 float RatioSys2AdcClk; /**< Ratio of system clock to ADC clock frequency */ 04707 }ClksCalInfo_Type; 04708 04709 /** 04710 * Software controlled Sweep Function 04711 * */ 04712 typedef struct 04713 { 04714 BoolFlag SweepEn; /**< Software can automatically sweep frequency from following parameters. Set value to 1 to enable it. */ 04715 float SweepStart; /**< Sweep start frequency. Software will go back to the start frequency when it reaches SWEEP_STOP */ 04716 float SweepStop; /**< Sweep end frequency. */ 04717 uint32_t SweepPoints; /**< How many points from START to STOP frequency */ 04718 BoolFlag SweepLog; /**< The step is linear or logarithmic. 0: Linear, 1: Logarithmic*/ 04719 uint32_t SweepIndex; /**< Current position of sweep */ 04720 }SoftSweepCfg_Type; 04721 04722 /** 04723 * Impedance result in Polar coordinate 04724 */ 04725 typedef struct 04726 { 04727 float Magnitude; /**< The magnitude in polar coordinate */ 04728 float Phase; /**< The phase in polar coordinate */ 04729 }fImpPol_Type; //Polar 04730 04731 /** 04732 * Impedance result in Cartesian coordinate 04733 */ 04734 typedef struct 04735 { 04736 float Real; /**< The real part in Cartesian coordinate */ 04737 float Image; /**< The imaginary in Cartesian coordinate */ 04738 }fImpCar_Type; //Cartesian 04739 04740 /** 04741 * int32_t type Impedance result in Cartesian coordinate 04742 */ 04743 typedef struct 04744 { 04745 int32_t Real; /**< The real part in Cartesian coordinate */ 04746 int32_t Image; /**< The real imaginary in Cartesian coordinate */ 04747 }iImpCar_Type; 04748 04749 /** 04750 * FreqParams_Type - Structure to store optimum filter settings 04751 */ 04752 typedef struct 04753 { 04754 BoolFlag HighPwrMode; 04755 uint32_t DftNum; 04756 uint32_t DftSrc; 04757 uint32_t ADCSinc3Osr; 04758 uint32_t ADCSinc2Osr; 04759 uint32_t NumClks; 04760 }FreqParams_Type; 04761 04762 /** 04763 * @} TypeDefinitions 04764 */ 04765 04766 /** 04767 * @defgroup Exported_Functions 04768 * @{ 04769 */ 04770 /* 1. Basic SPI functions */ 04771 void AD5940_WriteReg(uint16_t RegAddr, uint32_t RegData); 04772 uint32_t AD5940_ReadReg(uint16_t RegAddr); 04773 void AD5940_FIFORd(uint32_t *pBuffer,uint32_t uiReadCount); 04774 04775 /* 2. AD5940 Top Control functions */ 04776 void AD5940_Initialize(void); /* Call this function firstly once AD5940 power on or come from soft reset */ 04777 void AD5940_AFECtrlS(uint32_t AfeCtrlSet, BoolFlag State); 04778 AD5940Err AD5940_LPModeCtrlS(uint32_t EnSet); 04779 void AD5940_AFEPwrBW(uint32_t AfePwr, uint32_t AfeBw); /* AFE power mode and system bandwidth control */ 04780 void AD5940_REFCfgS(AFERefCfg_Type *pBufCfg); 04781 04782 /* 3. High_Speed_Loop Functions */ 04783 void AD5940_HSLoopCfgS(HSLoopCfg_Type *pHsLoopCfg); 04784 void AD5940_SWMatrixCfgS(SWMatrixCfg_Type *pSwMatrix); 04785 void AD5940_HSDacCfgS(HSDACCfg_Type *pHsDacCfg); 04786 AD5940Err AD5940_HSTIACfgS(HSTIACfg_Type *pHsTiaCfg); 04787 void AD5940_HSRTIACfgS(uint32_t HSTIARtia); 04788 04789 /* 4. Low_Power_Loop Functions*/ 04790 void AD5940_LPLoopCfgS(LPLoopCfg_Type *pLpLoopCfg); 04791 void AD5940_LPDACCfgS(LPDACCfg_Type *pLpDacCfg); 04792 //void AD5940_LPDACWriteS(uint16_t Data12Bit, uint8_t Data6Bit); 04793 void AD5940_LPDAC0WriteS(uint16_t Data12Bit, uint8_t Data6Bit); 04794 void AD5940_LPDAC1WriteS(uint16_t Data12Bit, uint8_t Data6Bit); 04795 void AD5940_LPAMPCfgS(LPAmpCfg_Type *pLpAmpCfg); 04796 04797 /* 5. DSP_Block_Functions */ 04798 void AD5940_DSPCfgS(DSPCfg_Type *pDSPCfg); 04799 uint32_t AD5940_ReadAfeResult(uint32_t AfeResultSel); 04800 /* 5.1 ADC Block */ 04801 void AD5940_ADCBaseCfgS(ADCBaseCfg_Type *pADCInit); 04802 void AD5940_ADCFilterCfgS(ADCFilterCfg_Type *pFiltCfg); 04803 void AD5940_ADCPowerCtrlS(BoolFlag State); 04804 void AD5940_ADCConvtCtrlS(BoolFlag State); 04805 void AD5940_ADCMuxCfgS(uint32_t ADCMuxP, uint32_t ADCMuxN); 04806 void AD5940_ADCDigCompCfgS(ADCDigComp_Type *pCompCfg); 04807 void AD5940_StatisticCfgS(StatCfg_Type *pStatCfg); 04808 void AD5940_ADCRepeatCfgS(uint32_t Number); 04809 void AD5940_DFTCfgS(DFTCfg_Type *pDftCfg); 04810 /* 5.2 Waveform Generator Block */ 04811 void AD5940_WGCfgS(WGCfg_Type *pWGInit); 04812 AD5940Err AD5940_WGDACCodeS(uint32_t code); /* Directly write DAC Code */ 04813 void AD5940_WGFreqCtrlS(float SinFreqHz, float WGClock); 04814 uint32_t AD5940_WGFreqWordCal(float SinFreqHz, float WGClock); 04815 //uint32_t AD5940_WGAmpWordCal(float Amp, BoolFlag DacGain, BoolFlag ExcitGain); 04816 04817 /* 6. Sequencer_FIFO */ 04818 void AD5940_FIFOCfg(FIFOCfg_Type *pFifoCfg); 04819 AD5940Err AD5940_FIFOGetCfg(FIFOCfg_Type *pFifoCfg); /* Read back current configuration */ 04820 void AD5940_FIFOCtrlS(uint32_t FifoSrc, BoolFlag FifoEn); /* Configure FIFO data source. And disable/enable it.*/ 04821 void AD5940_FIFOThrshSet(uint32_t FIFOThresh); 04822 uint32_t AD5940_FIFOGetCnt(void); /* Get current FIFO count */ 04823 void AD5940_SEQCfg(SEQCfg_Type *pSeqCfg); 04824 AD5940Err AD5940_SEQGetCfg(SEQCfg_Type *pSeqCfg); /* Read back current configuration */ 04825 void AD5940_SEQCtrlS(BoolFlag SeqEn); 04826 void AD5940_SEQHaltS(void); 04827 void AD5940_SEQMmrTrig(uint32_t SeqId); /* Manually trigger sequence */ 04828 void AD5940_SEQCmdWrite(uint32_t StartAddr, const uint32_t *pCommand, uint32_t CmdCnt); 04829 void AD5940_SEQInfoCfg(SEQInfo_Type *pSeq); 04830 AD5940Err AD5940_SEQInfoGet(uint32_t SeqId, SEQInfo_Type *pSeqInfo); 04831 void AD5940_SEQGpioCtrlS(uint32_t GpioSet); /* Sequencer can control GPIO0~7 if the GPIO function is set to SYNC */ 04832 uint32_t AD5940_SEQTimeOutRd(void); /* Read back current sequence time out value */ 04833 AD5940Err AD5940_SEQGpioTrigCfg(SeqGpioTrig_Cfg *pSeqGpioTrigCfg); 04834 void AD5940_WUPTCfg(WUPTCfg_Type *pWuptCfg); 04835 void AD5940_WUPTCtrl(BoolFlag Enable); /* Enable or disable Wakeup timer */ 04836 AD5940Err AD5940_WUPTTime(uint32_t SeqId, uint32_t SleepTime, uint32_t WakeupTime); 04837 04838 /* 7. MISC_Block */ 04839 /* 7.1 Clock system */ 04840 void AD5940_CLKCfg(CLKCfg_Type *pClkCfg); 04841 void AD5940_HFOSC32MHzCtrl(BoolFlag Mode32MHz); 04842 void AD5940_HPModeEn(BoolFlag Enable); /* Switch system clocks to high power mode for EIS >80kHz)*/ 04843 /* 7.2 AFE Interrupt */ 04844 void AD5940_INTCCfg(uint32_t AfeIntcSel, uint32_t AFEIntSrc, BoolFlag State); 04845 uint32_t AD5940_INTCGetCfg(uint32_t AfeIntcSel); 04846 void AD5940_INTCClrFlag(uint32_t AfeIntSrcSel); 04847 BoolFlag AD5940_INTCTestFlag(uint32_t AfeIntcSel, uint32_t AfeIntSrcSel); /* Check if selected interrupt happened */ 04848 uint32_t AD5940_INTCGetFlag(uint32_t AfeIntcSel); /* Get current INTC interrupt flag */ 04849 /* 7.3 GPIO */ 04850 void AD5940_AGPIOCfg(AGPIOCfg_Type *pAgpioCfg); 04851 void AD5940_AGPIOFuncCfg(uint32_t uiCfgSet); 04852 void AD5940_AGPIOOen(uint32_t uiPinSet); 04853 void AD5940_AGPIOIen(uint32_t uiPinSet); 04854 uint32_t AD5940_AGPIOIn(void); 04855 void AD5940_AGPIOPen(uint32_t uiPinSet); 04856 void AD5940_AGPIOSet(uint32_t uiPinSet); 04857 void AD5940_AGPIOClr(uint32_t uiPinSet); 04858 void AD5940_AGPIOToggle(uint32_t uiPinSet); 04859 04860 /* 7.4 LPMODE */ 04861 AD5940Err AD5940_LPModeEnS(BoolFlag LPModeEn); /* Enable LP mode or disable it. */ 04862 void AD5940_LPModeClkS(uint32_t LPModeClk); 04863 void AD5940_ADCRepeatCfg(uint32_t Number); 04864 /* 7.5 Power */ 04865 void AD5940_SleepKeyCtrlS(uint32_t SlpKey); /* enter the correct key to allow AFE to enter sleep mode */ 04866 void AD5940_EnterSleepS(void); /* Put AFE to hibernate/sleep mode and keep LP loop as the default settings. */ 04867 void AD5940_ShutDownS(void); /* Unlock the key, turn off LP loop and enter sleep/hibernate mode */ 04868 uint32_t AD5940_WakeUp(int32_t TryCount); /* Try to wakeup AFE by read register */ 04869 uint32_t AD5940_GetADIID(void); /* Read ADIID */ 04870 uint32_t AD5940_GetChipID(void); /* Read Chip ID */ 04871 AD5940Err AD5940_SoftRst(void); 04872 void AD5940_HWReset(void); /* Do hardware reset to AD5940 using RESET pin */ 04873 /* Calibration functions */ 04874 /* 8. Calibration */ 04875 AD5940Err AD5940_ADCPGACal(ADCPGACal_Type *ADCPGACal); 04876 AD5940Err AD5940_LPDACCal(LPDACCal_Type *pCalCfg, LPDACPara_Type *pResult); 04877 AD5940Err AD5940_LPTIAOffsetCal(LPTIAOffsetCal_Type *pLPTIAOffsetCal); 04878 AD5940Err AD5940_HSRtiaCal(HSRTIACal_Type *pCalCfg, void *pResult); 04879 AD5940Err AD5940_HSDACCal(HSDACCal_Type *pCalCfg); 04880 AD5940Err AD5940_LPRtiaCal(LPRTIACal_Type *pCalCfg, void *pResult); 04881 AD5940Err AD5940_LFOSCMeasure(LFOSCMeasure_Type *pCfg, float *pFreq); 04882 //void AD5940_LFOSCTrim(uint32_t TrimValue); /* TrimValue: 0 to 15 */ 04883 //void AD5940_HFOSC16MHzTrim(uint32_t TrimValue); 04884 //void AD5940_HFOSC32MHzTrim(uint32_t TrimValue); 04885 04886 /* 9. Pure software functions. Functions with no register access. These functions are helpers */ 04887 /* Sequence Generator */ 04888 void AD5940_SEQGenInit(uint32_t *pBuffer, uint32_t BufferSize);/* Initialize sequence generator workspace */ 04889 void AD5940_SEQGenCtrl(BoolFlag bFlag); /* Enable or disable sequence generator */ 04890 void AD5940_SEQGenInsert(uint32_t CmdWord); /* Manually insert a sequence command */ 04891 AD5940Err AD5940_SEQGenFetchSeq(const uint32_t **ppSeqCmd, uint32_t *pSeqCount); /* Fetch generated sequence and start a new sequence */ 04892 void AD5940_ClksCalculate(ClksCalInfo_Type *pFilterInfo, uint32_t *pClocks); 04893 uint32_t AD5940_SEQCycleTime(void); 04894 void AD5940_SweepNext(SoftSweepCfg_Type *pSweepCfg, float *pNextFreq); 04895 void AD5940_StructInit(void *pStruct, uint32_t StructSize); 04896 float AD5940_ADCCode2Volt(uint32_t code, uint32_t ADCPga, float VRef1p82); /* Calculate ADC code to voltage */ 04897 BoolFlag AD5940_Notch50HzAvailable(ADCFilterCfg_Type *pFilterInfo, uint8_t *dl); 04898 BoolFlag AD5940_Notch60HzAvailable(ADCFilterCfg_Type *pFilterInfo, uint8_t *dl); 04899 fImpCar_Type AD5940_ComplexDivFloat(fImpCar_Type *a, fImpCar_Type *b); 04900 fImpCar_Type AD5940_ComplexMulFloat(fImpCar_Type *a, fImpCar_Type *b); 04901 fImpCar_Type AD5940_ComplexAddFloat(fImpCar_Type *a, fImpCar_Type *b); 04902 fImpCar_Type AD5940_ComplexSubFloat(fImpCar_Type *a, fImpCar_Type *b); 04903 04904 fImpCar_Type AD5940_ComplexDivInt(iImpCar_Type *a, iImpCar_Type *b); 04905 fImpCar_Type AD5940_ComplexMulInt(iImpCar_Type *a, iImpCar_Type *b); 04906 float AD5940_ComplexMag(fImpCar_Type *a); 04907 float AD5940_ComplexPhase(fImpCar_Type *a); 04908 FreqParams_Type AD5940_GetFreqParameters(float freq); 04909 /** 04910 * @} Exported_Functions 04911 */ 04912 04913 /** 04914 * @defgroup Library_Interface 04915 * The functions user should provide for specific MCU platform 04916 * @{ 04917 */ 04918 void AD5940_CsClr(void); 04919 void AD5940_CsSet(void); 04920 void AD5940_RstClr(void); 04921 void AD5940_RstSet(void); 04922 void AD5940_Delay10us(uint32_t time); 04923 /* (Not used for now.)AD5940 has 8 GPIOs, some of them are connected to MCU. MCU can set or read the status of these pins. */ 04924 void AD5940_MCUGpioWrite(uint32_t data); /* */ 04925 uint32_t AD5940_MCUGpioRead(uint32_t); 04926 void AD5940_MCUGpioCtrl(uint32_t, BoolFlag); 04927 void AD5940_ReadWriteNBytes(unsigned char *pSendBuffer,unsigned char *pRecvBuff,unsigned long length); 04928 /* Below functions are frequently used in example code but not necessary for library */ 04929 uint32_t AD5940_GetMCUIntFlag(void); 04930 uint32_t AD5940_ClrMCUIntFlag(void); 04931 uint32_t AD5940_MCUResourceInit(void *pCfg); 04932 /** 04933 * @} Library_Interface 04934 */ 04935 04936 04937 /** 04938 * @} AD5940_Library 04939 */ 04940 04941 #endif 04942 #ifdef __cplusplus 04943 } 04944 #endif
Generated on Tue Jul 12 2022 21:32:08 by
1.7.2