James Coleman / SX1272Lib

SX1272 Ping Pong test working with the Freescale K22F microcontroller and the Semtech SX1272 evaluation module.

Fork of SX1272Lib by Timothy Mulrooney

sx1272/sx1272.cpp@24:f103f1004961, 2016-02-11 (annotated)

Committer:
jlcolemanmbed
Date:
Thu Feb 11 14:47:16 2016 +0000
Revision:
24:f103f1004961
Parent:
23:273a2f93ae99 
Revisions were made to sx1272.cpp, sx1272-hal.cpp debug.h and main.cpp in order for the Ping Pong Program to work with the Freescale K22F microcontroller and the SX1272 evaluation module.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tmulrooney 23:273a2f93ae99 1 /*
tmulrooney 23:273a2f93ae99 2 / _____) _ | |
tmulrooney 23:273a2f93ae99 3 ( (____ _____ ____ _| |_ _____ ____| |__
tmulrooney 23:273a2f93ae99 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
tmulrooney 23:273a2f93ae99 5 _____) ) ____| | | || |_| ____( (___| | | |
tmulrooney 23:273a2f93ae99 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
tmulrooney 23:273a2f93ae99 7 (C) 2014 Semtech
tmulrooney 23:273a2f93ae99 8
tmulrooney 23:273a2f93ae99 9 Description: Actual implementation of a SX1272 radio, inherits Radio
tmulrooney 23:273a2f93ae99 10
tmulrooney 23:273a2f93ae99 11 License: Revised BSD License, see LICENSE.TXT file include in the project
tmulrooney 23:273a2f93ae99 12
tmulrooney 23:273a2f93ae99 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
tmulrooney 23:273a2f93ae99 14 */
tmulrooney 23:273a2f93ae99 15 #include "sx1272.h"
tmulrooney 23:273a2f93ae99 16 #include "debug.h"
tmulrooney 23:273a2f93ae99 17
tmulrooney 23:273a2f93ae99 18 const FskBandwidth_t SX1272::FskBandwidths[] =
tmulrooney 23:273a2f93ae99 19 {
tmulrooney 23:273a2f93ae99 20 { 2600 , 0x17 },
tmulrooney 23:273a2f93ae99 21 { 3100 , 0x0F },
tmulrooney 23:273a2f93ae99 22 { 3900 , 0x07 },
tmulrooney 23:273a2f93ae99 23 { 5200 , 0x16 },
tmulrooney 23:273a2f93ae99 24 { 6300 , 0x0E },
tmulrooney 23:273a2f93ae99 25 { 7800 , 0x06 },
tmulrooney 23:273a2f93ae99 26 { 10400 , 0x15 },
tmulrooney 23:273a2f93ae99 27 { 12500 , 0x0D },
tmulrooney 23:273a2f93ae99 28 { 15600 , 0x05 },
tmulrooney 23:273a2f93ae99 29 { 20800 , 0x14 },
tmulrooney 23:273a2f93ae99 30 { 25000 , 0x0C },
tmulrooney 23:273a2f93ae99 31 { 31300 , 0x04 },
tmulrooney 23:273a2f93ae99 32 { 41700 , 0x13 },
tmulrooney 23:273a2f93ae99 33 { 50000 , 0x0B },
tmulrooney 23:273a2f93ae99 34 { 62500 , 0x03 },
tmulrooney 23:273a2f93ae99 35 { 83333 , 0x12 },
tmulrooney 23:273a2f93ae99 36 { 100000, 0x0A },
tmulrooney 23:273a2f93ae99 37 { 125000, 0x02 },
tmulrooney 23:273a2f93ae99 38 { 166700, 0x11 },
tmulrooney 23:273a2f93ae99 39 { 200000, 0x09 },
tmulrooney 23:273a2f93ae99 40 { 250000, 0x01 },
tmulrooney 23:273a2f93ae99 41 { 300000, 0x00 }, // Invalid Badwidth
tmulrooney 23:273a2f93ae99 42 };
tmulrooney 23:273a2f93ae99 43
tmulrooney 23:273a2f93ae99 44
tmulrooney 23:273a2f93ae99 45 SX1272::SX1272( RadioEvents_t *events,
tmulrooney 23:273a2f93ae99 46 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
tmulrooney 23:273a2f93ae99 47 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
tmulrooney 23:273a2f93ae99 48 : Radio( events ),
tmulrooney 23:273a2f93ae99 49 // spi( mosi, miso, sclk ),
tmulrooney 23:273a2f93ae99 50 // nss( nss ),
tmulrooney 23:273a2f93ae99 51 spi( PTD6, PTD7, PTD5 ),
tmulrooney 23:273a2f93ae99 52 nss( PTD4 ),
tmulrooney 23:273a2f93ae99 53 reset( reset ),
jlcolemanmbed 24:f103f1004961 54 dio0(PTC2), dio1(PTB1), dio2(PTC3), dio3(PTB0),dio4(PTC4), dio5(PTC1), //added by jlc
jlcolemanmbed 24:f103f1004961 55 // dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
tmulrooney 23:273a2f93ae99 56 isRadioActive( false )
tmulrooney 23:273a2f93ae99 57 {
tmulrooney 23:273a2f93ae99 58 debug("SX1272 constructor\r\n");
tmulrooney 23:273a2f93ae99 59 wait_ms( 10 );
tmulrooney 23:273a2f93ae99 60 this->rxTx = 0;
tmulrooney 23:273a2f93ae99 61 this->rxBuffer = new uint8_t[RX_BUFFER_SIZE];
tmulrooney 23:273a2f93ae99 62 previousOpMode = RF_OPMODE_STANDBY;
tmulrooney 23:273a2f93ae99 63
tmulrooney 23:273a2f93ae99 64 this->RadioEvents = events;
tmulrooney 23:273a2f93ae99 65
tmulrooney 23:273a2f93ae99 66 this->dioIrq = new DioIrqHandler[6];
tmulrooney 23:273a2f93ae99 67
tmulrooney 23:273a2f93ae99 68 this->dioIrq[0] = &SX1272::OnDio0Irq;
tmulrooney 23:273a2f93ae99 69 this->dioIrq[1] = &SX1272::OnDio1Irq;
tmulrooney 23:273a2f93ae99 70 this->dioIrq[2] = &SX1272::OnDio2Irq;
tmulrooney 23:273a2f93ae99 71 this->dioIrq[3] = &SX1272::OnDio3Irq;
tmulrooney 23:273a2f93ae99 72 this->dioIrq[4] = &SX1272::OnDio4Irq;
tmulrooney 23:273a2f93ae99 73 this->dioIrq[5] = NULL;
tmulrooney 23:273a2f93ae99 74
tmulrooney 23:273a2f93ae99 75 this->settings.State = RF_IDLE;
tmulrooney 23:273a2f93ae99 76 }
tmulrooney 23:273a2f93ae99 77
tmulrooney 23:273a2f93ae99 78 SX1272::~SX1272( )
tmulrooney 23:273a2f93ae99 79 {
tmulrooney 23:273a2f93ae99 80 debug("SX1272x destructor\r\n");
tmulrooney 23:273a2f93ae99 81 delete this->rxBuffer;
tmulrooney 23:273a2f93ae99 82 delete this->dioIrq;
tmulrooney 23:273a2f93ae99 83 }
tmulrooney 23:273a2f93ae99 84
tmulrooney 23:273a2f93ae99 85 void SX1272::Init( RadioEvents_t *events )
tmulrooney 23:273a2f93ae99 86 {
tmulrooney 23:273a2f93ae99 87 debug("SX1272 Init\r\n");
tmulrooney 23:273a2f93ae99 88 this->RadioEvents = events;
tmulrooney 23:273a2f93ae99 89 }
tmulrooney 23:273a2f93ae99 90
tmulrooney 23:273a2f93ae99 91 RadioState SX1272::GetStatus( void )
tmulrooney 23:273a2f93ae99 92 {
tmulrooney 23:273a2f93ae99 93 debug("GetStatus\r\n");
tmulrooney 23:273a2f93ae99 94 return this->settings.State;
tmulrooney 23:273a2f93ae99 95 }
tmulrooney 23:273a2f93ae99 96
tmulrooney 23:273a2f93ae99 97 void SX1272::SetChannel( uint32_t freq )
tmulrooney 23:273a2f93ae99 98 {
tmulrooney 23:273a2f93ae99 99 debug("SetChannel %d\r\n",freq);
tmulrooney 23:273a2f93ae99 100 this->settings.Channel = freq;
tmulrooney 23:273a2f93ae99 101 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
tmulrooney 23:273a2f93ae99 102 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
tmulrooney 23:273a2f93ae99 103 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
tmulrooney 23:273a2f93ae99 104 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
tmulrooney 23:273a2f93ae99 105 }
tmulrooney 23:273a2f93ae99 106
tmulrooney 23:273a2f93ae99 107 bool SX1272::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh )
tmulrooney 23:273a2f93ae99 108 {
tmulrooney 23:273a2f93ae99 109 debug("IsChannelFree\r\n");
tmulrooney 23:273a2f93ae99 110 int16_t rssi = 0;
tmulrooney 23:273a2f93ae99 111
tmulrooney 23:273a2f93ae99 112 SetModem( modem );
tmulrooney 23:273a2f93ae99 113
tmulrooney 23:273a2f93ae99 114 SetChannel( freq );
tmulrooney 23:273a2f93ae99 115
tmulrooney 23:273a2f93ae99 116 SetOpMode( RF_OPMODE_RECEIVER );
tmulrooney 23:273a2f93ae99 117
tmulrooney 23:273a2f93ae99 118 wait_ms( 1 );
tmulrooney 23:273a2f93ae99 119
tmulrooney 23:273a2f93ae99 120 rssi = GetRssi( modem );
tmulrooney 23:273a2f93ae99 121
tmulrooney 23:273a2f93ae99 122 Sleep( );
tmulrooney 23:273a2f93ae99 123
tmulrooney 23:273a2f93ae99 124 if( rssi > rssiThresh )
tmulrooney 23:273a2f93ae99 125 {
tmulrooney 23:273a2f93ae99 126 return false;
tmulrooney 23:273a2f93ae99 127 }
tmulrooney 23:273a2f93ae99 128 return true;
tmulrooney 23:273a2f93ae99 129 }
tmulrooney 23:273a2f93ae99 130
tmulrooney 23:273a2f93ae99 131 uint32_t SX1272::Random( void )
tmulrooney 23:273a2f93ae99 132 {
tmulrooney 23:273a2f93ae99 133 debug("Random\r\n");
tmulrooney 23:273a2f93ae99 134 uint8_t i;
tmulrooney 23:273a2f93ae99 135 uint32_t rnd = 0;
tmulrooney 23:273a2f93ae99 136
tmulrooney 23:273a2f93ae99 137 /*
tmulrooney 23:273a2f93ae99 138 * Radio setup for random number generation
tmulrooney 23:273a2f93ae99 139 */
tmulrooney 23:273a2f93ae99 140 // Set LoRa modem ON
tmulrooney 23:273a2f93ae99 141 SetModem( MODEM_LORA );
tmulrooney 23:273a2f93ae99 142
tmulrooney 23:273a2f93ae99 143 // Disable LoRa modem interrupts
tmulrooney 23:273a2f93ae99 144 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:273a2f93ae99 145 RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:273a2f93ae99 146 RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:273a2f93ae99 147 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:273a2f93ae99 148 RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:273a2f93ae99 149 RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:273a2f93ae99 150 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
tmulrooney 23:273a2f93ae99 151 RFLR_IRQFLAGS_CADDETECTED );
tmulrooney 23:273a2f93ae99 152
tmulrooney 23:273a2f93ae99 153 // Set radio in continuous reception
tmulrooney 23:273a2f93ae99 154 SetOpMode( RF_OPMODE_RECEIVER );
tmulrooney 23:273a2f93ae99 155
tmulrooney 23:273a2f93ae99 156 for( i = 0; i < 32; i++ )
tmulrooney 23:273a2f93ae99 157 {
tmulrooney 23:273a2f93ae99 158 wait_ms( 1 );
tmulrooney 23:273a2f93ae99 159 // Unfiltered RSSI value reading. Only takes the LSB value
tmulrooney 23:273a2f93ae99 160 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
tmulrooney 23:273a2f93ae99 161 }
tmulrooney 23:273a2f93ae99 162
tmulrooney 23:273a2f93ae99 163 Sleep( );
tmulrooney 23:273a2f93ae99 164
tmulrooney 23:273a2f93ae99 165 return rnd;
tmulrooney 23:273a2f93ae99 166 }
tmulrooney 23:273a2f93ae99 167
tmulrooney 23:273a2f93ae99 168 /*!
tmulrooney 23:273a2f93ae99 169 * Performs the Rx chain calibration for LF and HF bands
tmulrooney 23:273a2f93ae99 170 * \remark Must be called just after the reset so all registers are at their
tmulrooney 23:273a2f93ae99 171 * default values
tmulrooney 23:273a2f93ae99 172 */
tmulrooney 23:273a2f93ae99 173 void SX1272::RxChainCalibration( void )
tmulrooney 23:273a2f93ae99 174 {
tmulrooney 23:273a2f93ae99 175 debug("RxChainCalibration\r\n");
tmulrooney 23:273a2f93ae99 176 uint8_t regPaConfigInitVal;
tmulrooney 23:273a2f93ae99 177 uint32_t initialFreq;
tmulrooney 23:273a2f93ae99 178
tmulrooney 23:273a2f93ae99 179 // Save context
tmulrooney 23:273a2f93ae99 180 regPaConfigInitVal = this->Read( REG_PACONFIG );
tmulrooney 23:273a2f93ae99 181 initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) |
tmulrooney 23:273a2f93ae99 182 ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) |
tmulrooney 23:273a2f93ae99 183 ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
tmulrooney 23:273a2f93ae99 184 debug("Initial Freq: %d\r\n", initialFreq);
tmulrooney 23:273a2f93ae99 185
tmulrooney 23:273a2f93ae99 186 // Cut the PA just in case, RFO output, power = -1 dBm
tmulrooney 23:273a2f93ae99 187 this->Write( REG_PACONFIG, 0x00 );
tmulrooney 23:273a2f93ae99 188
tmulrooney 23:273a2f93ae99 189 // Launch Rx chain calibration for LF band
tmulrooney 23:273a2f93ae99 190 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
tmulrooney 23:273a2f93ae99 191 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
tmulrooney 23:273a2f93ae99 192 {
tmulrooney 23:273a2f93ae99 193 }
tmulrooney 23:273a2f93ae99 194
tmulrooney 23:273a2f93ae99 195 // Sets a Frequency in HF band
tmulrooney 23:273a2f93ae99 196 SetChannel( 868000000 );
tmulrooney 23:273a2f93ae99 197
tmulrooney 23:273a2f93ae99 198 // Launch Rx chain calibration for HF band
tmulrooney 23:273a2f93ae99 199 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
tmulrooney 23:273a2f93ae99 200 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
tmulrooney 23:273a2f93ae99 201 {
tmulrooney 23:273a2f93ae99 202 }
tmulrooney 23:273a2f93ae99 203
tmulrooney 23:273a2f93ae99 204 // Restore context
tmulrooney 23:273a2f93ae99 205 this->Write( REG_PACONFIG, regPaConfigInitVal );
tmulrooney 23:273a2f93ae99 206 SetChannel( initialFreq );
tmulrooney 23:273a2f93ae99 207 }
tmulrooney 23:273a2f93ae99 208
tmulrooney 23:273a2f93ae99 209 /*!
tmulrooney 23:273a2f93ae99 210 * Returns the known FSK bandwidth registers value
tmulrooney 23:273a2f93ae99 211 *
tmulrooney 23:273a2f93ae99 212 * \param [IN] bandwidth Bandwidth value in Hz
tmulrooney 23:273a2f93ae99 213 * \retval regValue Bandwidth register value.
tmulrooney 23:273a2f93ae99 214 */
tmulrooney 23:273a2f93ae99 215 uint8_t SX1272::GetFskBandwidthRegValue( uint32_t bandwidth )
tmulrooney 23:273a2f93ae99 216 {
tmulrooney 23:273a2f93ae99 217 debug("GetFskBandwidthRegValue\r\n");
tmulrooney 23:273a2f93ae99 218 uint8_t i;
tmulrooney 23:273a2f93ae99 219
tmulrooney 23:273a2f93ae99 220 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
tmulrooney 23:273a2f93ae99 221 {
tmulrooney 23:273a2f93ae99 222 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
tmulrooney 23:273a2f93ae99 223 {
tmulrooney 23:273a2f93ae99 224 return FskBandwidths[i].RegValue;
tmulrooney 23:273a2f93ae99 225 }
tmulrooney 23:273a2f93ae99 226 }
tmulrooney 23:273a2f93ae99 227 // ERROR: Value not found
tmulrooney 23:273a2f93ae99 228 while( 1 );
tmulrooney 23:273a2f93ae99 229 }
tmulrooney 23:273a2f93ae99 230
tmulrooney 23:273a2f93ae99 231 void SX1272::SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
tmulrooney 23:273a2f93ae99 232 uint32_t datarate, uint8_t coderate,
tmulrooney 23:273a2f93ae99 233 uint32_t bandwidthAfc, uint16_t preambleLen,
tmulrooney 23:273a2f93ae99 234 uint16_t symbTimeout, bool fixLen,
tmulrooney 23:273a2f93ae99 235 uint8_t payloadLen,
tmulrooney 23:273a2f93ae99 236 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
tmulrooney 23:273a2f93ae99 237 bool iqInverted, bool rxContinuous )
tmulrooney 23:273a2f93ae99 238 {
tmulrooney 23:273a2f93ae99 239 debug("SetRxConfig\r\n");
tmulrooney 23:273a2f93ae99 240 SetModem( modem );
tmulrooney 23:273a2f93ae99 241
tmulrooney 23:273a2f93ae99 242 switch( modem )
tmulrooney 23:273a2f93ae99 243 {
tmulrooney 23:273a2f93ae99 244 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 245 {
tmulrooney 23:273a2f93ae99 246 this->settings.Fsk.Bandwidth = bandwidth;
tmulrooney 23:273a2f93ae99 247 this->settings.Fsk.Datarate = datarate;
tmulrooney 23:273a2f93ae99 248 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
tmulrooney 23:273a2f93ae99 249 this->settings.Fsk.FixLen = fixLen;
tmulrooney 23:273a2f93ae99 250 this->settings.Fsk.PayloadLen = payloadLen;
tmulrooney 23:273a2f93ae99 251 this->settings.Fsk.CrcOn = crcOn;
tmulrooney 23:273a2f93ae99 252 this->settings.Fsk.IqInverted = iqInverted;
tmulrooney 23:273a2f93ae99 253 this->settings.Fsk.RxContinuous = rxContinuous;
tmulrooney 23:273a2f93ae99 254 this->settings.Fsk.PreambleLen = preambleLen;
tmulrooney 23:273a2f93ae99 255
tmulrooney 23:273a2f93ae99 256 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
tmulrooney 23:273a2f93ae99 257 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
tmulrooney 23:273a2f93ae99 258 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
tmulrooney 23:273a2f93ae99 259
tmulrooney 23:273a2f93ae99 260 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
tmulrooney 23:273a2f93ae99 261 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
tmulrooney 23:273a2f93ae99 262
tmulrooney 23:273a2f93ae99 263 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
tmulrooney 23:273a2f93ae99 264 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
tmulrooney 23:273a2f93ae99 265
tmulrooney 23:273a2f93ae99 266 if( fixLen == 1 )
tmulrooney 23:273a2f93ae99 267 {
tmulrooney 23:273a2f93ae99 268 Write( REG_PAYLOADLENGTH, payloadLen );
tmulrooney 23:273a2f93ae99 269 }
tmulrooney 23:273a2f93ae99 270
tmulrooney 23:273a2f93ae99 271 Write( REG_PACKETCONFIG1,
tmulrooney 23:273a2f93ae99 272 ( Read( REG_PACKETCONFIG1 ) &
tmulrooney 23:273a2f93ae99 273 RF_PACKETCONFIG1_CRC_MASK &
tmulrooney 23:273a2f93ae99 274 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
tmulrooney 23:273a2f93ae99 275 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
tmulrooney 23:273a2f93ae99 276 ( crcOn << 4 ) );
tmulrooney 23:273a2f93ae99 277 }
tmulrooney 23:273a2f93ae99 278 break;
tmulrooney 23:273a2f93ae99 279 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 280 {
tmulrooney 23:273a2f93ae99 281 if( bandwidth > 2 )
tmulrooney 23:273a2f93ae99 282 {
tmulrooney 23:273a2f93ae99 283 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
tmulrooney 23:273a2f93ae99 284 while( 1 );
tmulrooney 23:273a2f93ae99 285 }
tmulrooney 23:273a2f93ae99 286 bandwidth += 7;
tmulrooney 23:273a2f93ae99 287 this->settings.LoRa.Bandwidth = bandwidth;
tmulrooney 23:273a2f93ae99 288 this->settings.LoRa.Datarate = datarate;
tmulrooney 23:273a2f93ae99 289 this->settings.LoRa.Coderate = coderate;
tmulrooney 23:273a2f93ae99 290 this->settings.LoRa.PreambleLen = preambleLen;
tmulrooney 23:273a2f93ae99 291 this->settings.LoRa.FixLen = fixLen;
tmulrooney 23:273a2f93ae99 292 this->settings.LoRa.PayloadLen = payloadLen;
tmulrooney 23:273a2f93ae99 293 this->settings.LoRa.CrcOn = crcOn;
tmulrooney 23:273a2f93ae99 294 this->settings.LoRa.FreqHopOn = freqHopOn;
tmulrooney 23:273a2f93ae99 295 this->settings.LoRa.HopPeriod = hopPeriod;
tmulrooney 23:273a2f93ae99 296 this->settings.LoRa.IqInverted = iqInverted;
tmulrooney 23:273a2f93ae99 297 this->settings.LoRa.RxContinuous = rxContinuous;
tmulrooney 23:273a2f93ae99 298
tmulrooney 23:273a2f93ae99 299 if( datarate > 12 )
tmulrooney 23:273a2f93ae99 300 {
tmulrooney 23:273a2f93ae99 301 datarate = 12;
tmulrooney 23:273a2f93ae99 302 }
tmulrooney 23:273a2f93ae99 303 else if( datarate < 6 )
tmulrooney 23:273a2f93ae99 304 {
tmulrooney 23:273a2f93ae99 305 datarate = 6;
tmulrooney 23:273a2f93ae99 306 }
tmulrooney 23:273a2f93ae99 307
tmulrooney 23:273a2f93ae99 308 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
tmulrooney 23:273a2f93ae99 309 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
tmulrooney 23:273a2f93ae99 310 {
tmulrooney 23:273a2f93ae99 311 this->settings.LoRa.LowDatarateOptimize = 0x01;
tmulrooney 23:273a2f93ae99 312 }
tmulrooney 23:273a2f93ae99 313 else
tmulrooney 23:273a2f93ae99 314 {
tmulrooney 23:273a2f93ae99 315 this->settings.LoRa.LowDatarateOptimize = 0x00;
tmulrooney 23:273a2f93ae99 316 }
tmulrooney 23:273a2f93ae99 317
tmulrooney 23:273a2f93ae99 318 Write( REG_LR_MODEMCONFIG1,
tmulrooney 23:273a2f93ae99 319 ( Read( REG_LR_MODEMCONFIG1 ) &
tmulrooney 23:273a2f93ae99 320 RFLR_MODEMCONFIG1_BW_MASK &
tmulrooney 23:273a2f93ae99 321 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
tmulrooney 23:273a2f93ae99 322 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
tmulrooney 23:273a2f93ae99 323 ( bandwidth << 4 ) | ( coderate << 1 ) |
tmulrooney 23:273a2f93ae99 324 fixLen );
tmulrooney 23:273a2f93ae99 325
tmulrooney 23:273a2f93ae99 326 Write( REG_LR_MODEMCONFIG2,
tmulrooney 23:273a2f93ae99 327 ( Read( REG_LR_MODEMCONFIG2 ) &
tmulrooney 23:273a2f93ae99 328 RFLR_MODEMCONFIG2_SF_MASK &
tmulrooney 23:273a2f93ae99 329 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
tmulrooney 23:273a2f93ae99 330 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
tmulrooney 23:273a2f93ae99 331 ( datarate << 4 ) | ( crcOn << 2 ) |
tmulrooney 23:273a2f93ae99 332 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
tmulrooney 23:273a2f93ae99 333
tmulrooney 23:273a2f93ae99 334 Write( REG_LR_MODEMCONFIG3,
tmulrooney 23:273a2f93ae99 335 ( Read( REG_LR_MODEMCONFIG3 ) &
tmulrooney 23:273a2f93ae99 336 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
tmulrooney 23:273a2f93ae99 337 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
tmulrooney 23:273a2f93ae99 338
tmulrooney 23:273a2f93ae99 339 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
tmulrooney 23:273a2f93ae99 340
tmulrooney 23:273a2f93ae99 341 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
tmulrooney 23:273a2f93ae99 342 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
tmulrooney 23:273a2f93ae99 343
tmulrooney 23:273a2f93ae99 344 if( fixLen == 1 )
tmulrooney 23:273a2f93ae99 345 {
tmulrooney 23:273a2f93ae99 346 Write( REG_LR_PAYLOADLENGTH, payloadLen );
tmulrooney 23:273a2f93ae99 347 }
tmulrooney 23:273a2f93ae99 348
tmulrooney 23:273a2f93ae99 349 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:273a2f93ae99 350 {
tmulrooney 23:273a2f93ae99 351 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
tmulrooney 23:273a2f93ae99 352 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
tmulrooney 23:273a2f93ae99 353 }
tmulrooney 23:273a2f93ae99 354
tmulrooney 23:273a2f93ae99 355 if( ( bandwidth == 9 ) && ( RF_MID_BAND_THRESH ) )
tmulrooney 23:273a2f93ae99 356 {
tmulrooney 23:273a2f93ae99 357 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
tmulrooney 23:273a2f93ae99 358 Write( REG_LR_TEST36, 0x02 );
tmulrooney 23:273a2f93ae99 359 Write( REG_LR_TEST3A, 0x64 );
tmulrooney 23:273a2f93ae99 360 }
tmulrooney 23:273a2f93ae99 361 else if( bandwidth == 9 )
tmulrooney 23:273a2f93ae99 362 {
tmulrooney 23:273a2f93ae99 363 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
tmulrooney 23:273a2f93ae99 364 Write( REG_LR_TEST36, 0x02 );
tmulrooney 23:273a2f93ae99 365 Write( REG_LR_TEST3A, 0x7F );
tmulrooney 23:273a2f93ae99 366 }
tmulrooney 23:273a2f93ae99 367 else
tmulrooney 23:273a2f93ae99 368 {
tmulrooney 23:273a2f93ae99 369 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
tmulrooney 23:273a2f93ae99 370 Write( REG_LR_TEST36, 0x03 );
tmulrooney 23:273a2f93ae99 371 }
tmulrooney 23:273a2f93ae99 372
tmulrooney 23:273a2f93ae99 373 if( datarate == 6 )
tmulrooney 23:273a2f93ae99 374 {
tmulrooney 23:273a2f93ae99 375 Write( REG_LR_DETECTOPTIMIZE,
tmulrooney 23:273a2f93ae99 376 ( Read( REG_LR_DETECTOPTIMIZE ) &
tmulrooney 23:273a2f93ae99 377 RFLR_DETECTIONOPTIMIZE_MASK ) |
tmulrooney 23:273a2f93ae99 378 RFLR_DETECTIONOPTIMIZE_SF6 );
tmulrooney 23:273a2f93ae99 379 Write( REG_LR_DETECTIONTHRESHOLD,
tmulrooney 23:273a2f93ae99 380 RFLR_DETECTIONTHRESH_SF6 );
tmulrooney 23:273a2f93ae99 381 }
tmulrooney 23:273a2f93ae99 382 else
tmulrooney 23:273a2f93ae99 383 {
tmulrooney 23:273a2f93ae99 384 Write( REG_LR_DETECTOPTIMIZE,
tmulrooney 23:273a2f93ae99 385 ( Read( REG_LR_DETECTOPTIMIZE ) &
tmulrooney 23:273a2f93ae99 386 RFLR_DETECTIONOPTIMIZE_MASK ) |
tmulrooney 23:273a2f93ae99 387 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
tmulrooney 23:273a2f93ae99 388 Write( REG_LR_DETECTIONTHRESHOLD,
tmulrooney 23:273a2f93ae99 389 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
tmulrooney 23:273a2f93ae99 390 }
tmulrooney 23:273a2f93ae99 391 }
tmulrooney 23:273a2f93ae99 392 break;
tmulrooney 23:273a2f93ae99 393 }
tmulrooney 23:273a2f93ae99 394 }
tmulrooney 23:273a2f93ae99 395
tmulrooney 23:273a2f93ae99 396 void SX1272::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
tmulrooney 23:273a2f93ae99 397 uint32_t bandwidth, uint32_t datarate,
tmulrooney 23:273a2f93ae99 398 uint8_t coderate, uint16_t preambleLen,
tmulrooney 23:273a2f93ae99 399 bool fixLen, bool crcOn, bool freqHopOn,
tmulrooney 23:273a2f93ae99 400 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
tmulrooney 23:273a2f93ae99 401 {
tmulrooney 23:273a2f93ae99 402 debug("SetTxConfig\r\n");
tmulrooney 23:273a2f93ae99 403 uint8_t paConfig = 0;
tmulrooney 23:273a2f93ae99 404 uint8_t paDac = 0;
tmulrooney 23:273a2f93ae99 405
tmulrooney 23:273a2f93ae99 406 SetModem( modem );
tmulrooney 23:273a2f93ae99 407
tmulrooney 23:273a2f93ae99 408 paConfig = Read( REG_PACONFIG );
tmulrooney 23:273a2f93ae99 409 paDac = Read( REG_PADAC );
tmulrooney 23:273a2f93ae99 410
tmulrooney 23:273a2f93ae99 411 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
tmulrooney 23:273a2f93ae99 412 paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
tmulrooney 23:273a2f93ae99 413
tmulrooney 23:273a2f93ae99 414 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
tmulrooney 23:273a2f93ae99 415 {
tmulrooney 23:273a2f93ae99 416 if( power > 17 )
tmulrooney 23:273a2f93ae99 417 {
tmulrooney 23:273a2f93ae99 418 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
tmulrooney 23:273a2f93ae99 419 }
tmulrooney 23:273a2f93ae99 420 else
tmulrooney 23:273a2f93ae99 421 {
tmulrooney 23:273a2f93ae99 422 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
tmulrooney 23:273a2f93ae99 423 }
tmulrooney 23:273a2f93ae99 424 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
tmulrooney 23:273a2f93ae99 425 {
tmulrooney 23:273a2f93ae99 426 if( power < 5 )
tmulrooney 23:273a2f93ae99 427 {
tmulrooney 23:273a2f93ae99 428 power = 5;
tmulrooney 23:273a2f93ae99 429 }
tmulrooney 23:273a2f93ae99 430 if( power > 20 )
tmulrooney 23:273a2f93ae99 431 {
tmulrooney 23:273a2f93ae99 432 power = 20;
tmulrooney 23:273a2f93ae99 433 }
tmulrooney 23:273a2f93ae99 434 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
tmulrooney 23:273a2f93ae99 435 }
tmulrooney 23:273a2f93ae99 436 else
tmulrooney 23:273a2f93ae99 437 {
tmulrooney 23:273a2f93ae99 438 if( power < 2 )
tmulrooney 23:273a2f93ae99 439 {
tmulrooney 23:273a2f93ae99 440 power = 2;
tmulrooney 23:273a2f93ae99 441 }
tmulrooney 23:273a2f93ae99 442 if( power > 17 )
tmulrooney 23:273a2f93ae99 443 {
tmulrooney 23:273a2f93ae99 444 power = 17;
tmulrooney 23:273a2f93ae99 445 }
tmulrooney 23:273a2f93ae99 446 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
tmulrooney 23:273a2f93ae99 447 }
tmulrooney 23:273a2f93ae99 448 }
tmulrooney 23:273a2f93ae99 449 else
tmulrooney 23:273a2f93ae99 450 {
tmulrooney 23:273a2f93ae99 451 if( power < -1 )
tmulrooney 23:273a2f93ae99 452 {
tmulrooney 23:273a2f93ae99 453 power = -1;
tmulrooney 23:273a2f93ae99 454 }
tmulrooney 23:273a2f93ae99 455 if( power > 14 )
tmulrooney 23:273a2f93ae99 456 {
tmulrooney 23:273a2f93ae99 457 power = 14;
tmulrooney 23:273a2f93ae99 458 }
tmulrooney 23:273a2f93ae99 459 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
tmulrooney 23:273a2f93ae99 460 }
tmulrooney 23:273a2f93ae99 461 Write( REG_PACONFIG, paConfig );
tmulrooney 23:273a2f93ae99 462 Write( REG_PADAC, paDac );
tmulrooney 23:273a2f93ae99 463
tmulrooney 23:273a2f93ae99 464 switch( modem )
tmulrooney 23:273a2f93ae99 465 {
tmulrooney 23:273a2f93ae99 466 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 467 {
tmulrooney 23:273a2f93ae99 468 this->settings.Fsk.Power = power;
tmulrooney 23:273a2f93ae99 469 this->settings.Fsk.Fdev = fdev;
tmulrooney 23:273a2f93ae99 470 this->settings.Fsk.Bandwidth = bandwidth;
tmulrooney 23:273a2f93ae99 471 this->settings.Fsk.Datarate = datarate;
tmulrooney 23:273a2f93ae99 472 this->settings.Fsk.PreambleLen = preambleLen;
tmulrooney 23:273a2f93ae99 473 this->settings.Fsk.FixLen = fixLen;
tmulrooney 23:273a2f93ae99 474 this->settings.Fsk.CrcOn = crcOn;
tmulrooney 23:273a2f93ae99 475 this->settings.Fsk.IqInverted = iqInverted;
tmulrooney 23:273a2f93ae99 476 this->settings.Fsk.TxTimeout = timeout;
tmulrooney 23:273a2f93ae99 477
tmulrooney 23:273a2f93ae99 478 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
tmulrooney 23:273a2f93ae99 479 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
tmulrooney 23:273a2f93ae99 480 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
tmulrooney 23:273a2f93ae99 481
tmulrooney 23:273a2f93ae99 482 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
tmulrooney 23:273a2f93ae99 483 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
tmulrooney 23:273a2f93ae99 484 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
tmulrooney 23:273a2f93ae99 485
tmulrooney 23:273a2f93ae99 486 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
tmulrooney 23:273a2f93ae99 487 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
tmulrooney 23:273a2f93ae99 488
tmulrooney 23:273a2f93ae99 489 Write( REG_PACKETCONFIG1,
tmulrooney 23:273a2f93ae99 490 ( Read( REG_PACKETCONFIG1 ) &
tmulrooney 23:273a2f93ae99 491 RF_PACKETCONFIG1_CRC_MASK &
tmulrooney 23:273a2f93ae99 492 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
tmulrooney 23:273a2f93ae99 493 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
tmulrooney 23:273a2f93ae99 494 ( crcOn << 4 ) );
tmulrooney 23:273a2f93ae99 495
tmulrooney 23:273a2f93ae99 496 }
tmulrooney 23:273a2f93ae99 497 break;
tmulrooney 23:273a2f93ae99 498 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 499 {
tmulrooney 23:273a2f93ae99 500 this->settings.LoRa.Power = power;
tmulrooney 23:273a2f93ae99 501 if( bandwidth > 2 )
tmulrooney 23:273a2f93ae99 502 {
tmulrooney 23:273a2f93ae99 503 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
tmulrooney 23:273a2f93ae99 504 while( 1 );
tmulrooney 23:273a2f93ae99 505 }
tmulrooney 23:273a2f93ae99 506 bandwidth += 7;
tmulrooney 23:273a2f93ae99 507 this->settings.LoRa.Bandwidth = bandwidth;
tmulrooney 23:273a2f93ae99 508 this->settings.LoRa.Datarate = datarate;
tmulrooney 23:273a2f93ae99 509 this->settings.LoRa.Coderate = coderate;
tmulrooney 23:273a2f93ae99 510 this->settings.LoRa.PreambleLen = preambleLen;
tmulrooney 23:273a2f93ae99 511 this->settings.LoRa.FixLen = fixLen;
tmulrooney 23:273a2f93ae99 512 this->settings.LoRa.FreqHopOn = freqHopOn;
tmulrooney 23:273a2f93ae99 513 this->settings.LoRa.HopPeriod = hopPeriod;
tmulrooney 23:273a2f93ae99 514 this->settings.LoRa.CrcOn = crcOn;
tmulrooney 23:273a2f93ae99 515 this->settings.LoRa.IqInverted = iqInverted;
tmulrooney 23:273a2f93ae99 516 this->settings.LoRa.TxTimeout = timeout;
tmulrooney 23:273a2f93ae99 517
tmulrooney 23:273a2f93ae99 518 if( datarate > 12 )
tmulrooney 23:273a2f93ae99 519 {
tmulrooney 23:273a2f93ae99 520 datarate = 12;
tmulrooney 23:273a2f93ae99 521 }
tmulrooney 23:273a2f93ae99 522 else if( datarate < 6 )
tmulrooney 23:273a2f93ae99 523 {
tmulrooney 23:273a2f93ae99 524 datarate = 6;
tmulrooney 23:273a2f93ae99 525 }
tmulrooney 23:273a2f93ae99 526 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
tmulrooney 23:273a2f93ae99 527 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
tmulrooney 23:273a2f93ae99 528 {
tmulrooney 23:273a2f93ae99 529 this->settings.LoRa.LowDatarateOptimize = 0x01;
tmulrooney 23:273a2f93ae99 530 }
tmulrooney 23:273a2f93ae99 531 else
tmulrooney 23:273a2f93ae99 532 {
tmulrooney 23:273a2f93ae99 533 this->settings.LoRa.LowDatarateOptimize = 0x00;
tmulrooney 23:273a2f93ae99 534 }
tmulrooney 23:273a2f93ae99 535
tmulrooney 23:273a2f93ae99 536 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:273a2f93ae99 537 {
tmulrooney 23:273a2f93ae99 538 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
tmulrooney 23:273a2f93ae99 539 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
tmulrooney 23:273a2f93ae99 540 }
tmulrooney 23:273a2f93ae99 541
tmulrooney 23:273a2f93ae99 542 Write( REG_LR_MODEMCONFIG1,
tmulrooney 23:273a2f93ae99 543 ( Read( REG_LR_MODEMCONFIG1 ) &
tmulrooney 23:273a2f93ae99 544 RFLR_MODEMCONFIG1_BW_MASK &
tmulrooney 23:273a2f93ae99 545 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
tmulrooney 23:273a2f93ae99 546 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
tmulrooney 23:273a2f93ae99 547 ( bandwidth << 4 ) | ( coderate << 1 ) |
tmulrooney 23:273a2f93ae99 548 fixLen );
tmulrooney 23:273a2f93ae99 549
tmulrooney 23:273a2f93ae99 550 Write( REG_LR_MODEMCONFIG2,
tmulrooney 23:273a2f93ae99 551 ( Read( REG_LR_MODEMCONFIG2 ) &
tmulrooney 23:273a2f93ae99 552 RFLR_MODEMCONFIG2_SF_MASK &
tmulrooney 23:273a2f93ae99 553 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
tmulrooney 23:273a2f93ae99 554 ( datarate << 4 ) | ( crcOn << 2 ) );
tmulrooney 23:273a2f93ae99 555
tmulrooney 23:273a2f93ae99 556 Write( REG_LR_MODEMCONFIG3,
tmulrooney 23:273a2f93ae99 557 ( Read( REG_LR_MODEMCONFIG3 ) &
tmulrooney 23:273a2f93ae99 558 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
tmulrooney 23:273a2f93ae99 559 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
tmulrooney 23:273a2f93ae99 560
tmulrooney 23:273a2f93ae99 561 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
tmulrooney 23:273a2f93ae99 562 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
tmulrooney 23:273a2f93ae99 563
tmulrooney 23:273a2f93ae99 564 if( datarate == 6 )
tmulrooney 23:273a2f93ae99 565 {
tmulrooney 23:273a2f93ae99 566 Write( REG_LR_DETECTOPTIMIZE,
tmulrooney 23:273a2f93ae99 567 ( Read( REG_LR_DETECTOPTIMIZE ) &
tmulrooney 23:273a2f93ae99 568 RFLR_DETECTIONOPTIMIZE_MASK ) |
tmulrooney 23:273a2f93ae99 569 RFLR_DETECTIONOPTIMIZE_SF6 );
tmulrooney 23:273a2f93ae99 570 Write( REG_LR_DETECTIONTHRESHOLD,
tmulrooney 23:273a2f93ae99 571 RFLR_DETECTIONTHRESH_SF6 );
tmulrooney 23:273a2f93ae99 572 }
tmulrooney 23:273a2f93ae99 573 else
tmulrooney 23:273a2f93ae99 574 {
tmulrooney 23:273a2f93ae99 575 Write( REG_LR_DETECTOPTIMIZE,
tmulrooney 23:273a2f93ae99 576 ( Read( REG_LR_DETECTOPTIMIZE ) &
tmulrooney 23:273a2f93ae99 577 RFLR_DETECTIONOPTIMIZE_MASK ) |
tmulrooney 23:273a2f93ae99 578 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
tmulrooney 23:273a2f93ae99 579 Write( REG_LR_DETECTIONTHRESHOLD,
tmulrooney 23:273a2f93ae99 580 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
tmulrooney 23:273a2f93ae99 581 }
tmulrooney 23:273a2f93ae99 582 }
tmulrooney 23:273a2f93ae99 583 break;
tmulrooney 23:273a2f93ae99 584 }
tmulrooney 23:273a2f93ae99 585 }
tmulrooney 23:273a2f93ae99 586
tmulrooney 23:273a2f93ae99 587 double SX1272::TimeOnAir( RadioModems_t modem, uint8_t pktLen )
tmulrooney 23:273a2f93ae99 588 {
tmulrooney 23:273a2f93ae99 589 debug("TimeOnAir\r\n");
tmulrooney 23:273a2f93ae99 590 uint32_t airTime = 0;
tmulrooney 23:273a2f93ae99 591
tmulrooney 23:273a2f93ae99 592 switch( modem )
tmulrooney 23:273a2f93ae99 593 {
tmulrooney 23:273a2f93ae99 594 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 595 {
tmulrooney 23:273a2f93ae99 596 airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen +
tmulrooney 23:273a2f93ae99 597 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
tmulrooney 23:273a2f93ae99 598 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
tmulrooney 23:273a2f93ae99 599 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
tmulrooney 23:273a2f93ae99 600 pktLen +
tmulrooney 23:273a2f93ae99 601 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
tmulrooney 23:273a2f93ae99 602 this->settings.Fsk.Datarate ) * 1e6 );
tmulrooney 23:273a2f93ae99 603 }
tmulrooney 23:273a2f93ae99 604 break;
tmulrooney 23:273a2f93ae99 605 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 606 {
tmulrooney 23:273a2f93ae99 607 double bw = 0.0;
tmulrooney 23:273a2f93ae99 608 // REMARK: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
tmulrooney 23:273a2f93ae99 609 switch( this->settings.LoRa.Bandwidth )
tmulrooney 23:273a2f93ae99 610 {
tmulrooney 23:273a2f93ae99 611 //case 0: // 7.8 kHz
tmulrooney 23:273a2f93ae99 612 // bw = 78e2;
tmulrooney 23:273a2f93ae99 613 // break;
tmulrooney 23:273a2f93ae99 614 //case 1: // 10.4 kHz
tmulrooney 23:273a2f93ae99 615 // bw = 104e2;
tmulrooney 23:273a2f93ae99 616 // break;
tmulrooney 23:273a2f93ae99 617 //case 2: // 15.6 kHz
tmulrooney 23:273a2f93ae99 618 // bw = 156e2;
tmulrooney 23:273a2f93ae99 619 // break;
tmulrooney 23:273a2f93ae99 620 //case 3: // 20.8 kHz
tmulrooney 23:273a2f93ae99 621 // bw = 208e2;
tmulrooney 23:273a2f93ae99 622 // break;
tmulrooney 23:273a2f93ae99 623 //case 4: // 31.2 kHz
tmulrooney 23:273a2f93ae99 624 // bw = 312e2;
tmulrooney 23:273a2f93ae99 625 // break;
tmulrooney 23:273a2f93ae99 626 //case 5: // 41.4 kHz
tmulrooney 23:273a2f93ae99 627 // bw = 414e2;
tmulrooney 23:273a2f93ae99 628 // break;
tmulrooney 23:273a2f93ae99 629 //case 6: // 62.5 kHz
tmulrooney 23:273a2f93ae99 630 // bw = 625e2;
tmulrooney 23:273a2f93ae99 631 // break;
tmulrooney 23:273a2f93ae99 632 case 7: // 125 kHz
tmulrooney 23:273a2f93ae99 633 bw = 125e3;
tmulrooney 23:273a2f93ae99 634 break;
tmulrooney 23:273a2f93ae99 635 case 8: // 250 kHz
tmulrooney 23:273a2f93ae99 636 bw = 250e3;
tmulrooney 23:273a2f93ae99 637 break;
tmulrooney 23:273a2f93ae99 638 case 9: // 500 kHz
tmulrooney 23:273a2f93ae99 639 bw = 500e3;
tmulrooney 23:273a2f93ae99 640 break;
tmulrooney 23:273a2f93ae99 641 }
tmulrooney 23:273a2f93ae99 642
tmulrooney 23:273a2f93ae99 643 // Symbol rate : time for one symbol (secs)
tmulrooney 23:273a2f93ae99 644 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
tmulrooney 23:273a2f93ae99 645 double ts = 1 / rs;
tmulrooney 23:273a2f93ae99 646 // time of preamble
tmulrooney 23:273a2f93ae99 647 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
tmulrooney 23:273a2f93ae99 648 // Symbol length of payload and time
tmulrooney 23:273a2f93ae99 649 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
tmulrooney 23:273a2f93ae99 650 28 + 16 * this->settings.LoRa.CrcOn -
tmulrooney 23:273a2f93ae99 651 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
tmulrooney 23:273a2f93ae99 652 ( double )( 4 * this->settings.LoRa.Datarate -
tmulrooney 23:273a2f93ae99 653 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) *
tmulrooney 23:273a2f93ae99 654 ( this->settings.LoRa.Coderate + 4 );
tmulrooney 23:273a2f93ae99 655 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
tmulrooney 23:273a2f93ae99 656 double tPayload = nPayload * ts;
tmulrooney 23:273a2f93ae99 657 // Time on air
tmulrooney 23:273a2f93ae99 658 double tOnAir = tPreamble + tPayload;
tmulrooney 23:273a2f93ae99 659 // return us secs
tmulrooney 23:273a2f93ae99 660 airTime = floor( tOnAir * 1e6 + 0.999 );
tmulrooney 23:273a2f93ae99 661 }
tmulrooney 23:273a2f93ae99 662 break;
tmulrooney 23:273a2f93ae99 663 }
tmulrooney 23:273a2f93ae99 664 return airTime;
tmulrooney 23:273a2f93ae99 665 }
tmulrooney 23:273a2f93ae99 666
tmulrooney 23:273a2f93ae99 667 void SX1272::Send( uint8_t *buffer, uint8_t size )
tmulrooney 23:273a2f93ae99 668 {
tmulrooney 23:273a2f93ae99 669 debug("Send\r\n");
tmulrooney 23:273a2f93ae99 670 uint32_t txTimeout = 0;
tmulrooney 23:273a2f93ae99 671
tmulrooney 23:273a2f93ae99 672 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 673 {
tmulrooney 23:273a2f93ae99 674 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 675 {
tmulrooney 23:273a2f93ae99 676 this->settings.FskPacketHandler.NbBytes = 0;
tmulrooney 23:273a2f93ae99 677 this->settings.FskPacketHandler.Size = size;
tmulrooney 23:273a2f93ae99 678
tmulrooney 23:273a2f93ae99 679 if( this->settings.Fsk.FixLen == false )
tmulrooney 23:273a2f93ae99 680 {
tmulrooney 23:273a2f93ae99 681 WriteFifo( ( uint8_t* )&size, 1 );
tmulrooney 23:273a2f93ae99 682 }
tmulrooney 23:273a2f93ae99 683 else
tmulrooney 23:273a2f93ae99 684 {
tmulrooney 23:273a2f93ae99 685 Write( REG_PAYLOADLENGTH, size );
tmulrooney 23:273a2f93ae99 686 }
tmulrooney 23:273a2f93ae99 687
tmulrooney 23:273a2f93ae99 688 if( ( size > 0 ) && ( size <= 64 ) )
tmulrooney 23:273a2f93ae99 689 {
tmulrooney 23:273a2f93ae99 690 this->settings.FskPacketHandler.ChunkSize = size;
tmulrooney 23:273a2f93ae99 691 }
tmulrooney 23:273a2f93ae99 692 else
tmulrooney 23:273a2f93ae99 693 {
tmulrooney 23:273a2f93ae99 694 this->settings.FskPacketHandler.ChunkSize = 32;
tmulrooney 23:273a2f93ae99 695 }
tmulrooney 23:273a2f93ae99 696
tmulrooney 23:273a2f93ae99 697 // Write payload buffer
tmulrooney 23:273a2f93ae99 698 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
tmulrooney 23:273a2f93ae99 699 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
tmulrooney 23:273a2f93ae99 700 txTimeout = this->settings.Fsk.TxTimeout;
tmulrooney 23:273a2f93ae99 701 }
tmulrooney 23:273a2f93ae99 702 break;
tmulrooney 23:273a2f93ae99 703 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 704 {
tmulrooney 23:273a2f93ae99 705 if( this->settings.LoRa.IqInverted == true )
tmulrooney 23:273a2f93ae99 706 {
tmulrooney 23:273a2f93ae99 707 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
tmulrooney 23:273a2f93ae99 708 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
tmulrooney 23:273a2f93ae99 709 }
tmulrooney 23:273a2f93ae99 710 else
tmulrooney 23:273a2f93ae99 711 {
tmulrooney 23:273a2f93ae99 712 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
tmulrooney 23:273a2f93ae99 713 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
tmulrooney 23:273a2f93ae99 714 }
tmulrooney 23:273a2f93ae99 715
tmulrooney 23:273a2f93ae99 716 this->settings.LoRaPacketHandler.Size = size;
tmulrooney 23:273a2f93ae99 717
tmulrooney 23:273a2f93ae99 718 // Initializes the payload size
tmulrooney 23:273a2f93ae99 719 Write( REG_LR_PAYLOADLENGTH, size );
tmulrooney 23:273a2f93ae99 720
tmulrooney 23:273a2f93ae99 721 // Full buffer used for Tx
tmulrooney 23:273a2f93ae99 722 Write( REG_LR_FIFOTXBASEADDR, 0 );
tmulrooney 23:273a2f93ae99 723 Write( REG_LR_FIFOADDRPTR, 0 );
tmulrooney 23:273a2f93ae99 724
tmulrooney 23:273a2f93ae99 725 // FIFO operations can not take place in Sleep mode
tmulrooney 23:273a2f93ae99 726 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
tmulrooney 23:273a2f93ae99 727 {
tmulrooney 23:273a2f93ae99 728 Standby( );
tmulrooney 23:273a2f93ae99 729 wait_ms( 1 );
tmulrooney 23:273a2f93ae99 730 }
tmulrooney 23:273a2f93ae99 731 // Write payload buffer
tmulrooney 23:273a2f93ae99 732 WriteFifo( buffer, size );
tmulrooney 23:273a2f93ae99 733 txTimeout = this->settings.LoRa.TxTimeout;
tmulrooney 23:273a2f93ae99 734 }
tmulrooney 23:273a2f93ae99 735 break;
tmulrooney 23:273a2f93ae99 736 }
tmulrooney 23:273a2f93ae99 737
tmulrooney 23:273a2f93ae99 738 Tx( txTimeout );
tmulrooney 23:273a2f93ae99 739 }
tmulrooney 23:273a2f93ae99 740
tmulrooney 23:273a2f93ae99 741 void SX1272::Sleep( void )
tmulrooney 23:273a2f93ae99 742 {
tmulrooney 23:273a2f93ae99 743 debug("Sleep\r\n");
tmulrooney 23:273a2f93ae99 744 txTimeoutTimer.detach( );
tmulrooney 23:273a2f93ae99 745 rxTimeoutTimer.detach( );
tmulrooney 23:273a2f93ae99 746
tmulrooney 23:273a2f93ae99 747 SetOpMode( RF_OPMODE_SLEEP );
tmulrooney 23:273a2f93ae99 748 this->settings.State = RF_IDLE;
tmulrooney 23:273a2f93ae99 749 }
tmulrooney 23:273a2f93ae99 750
tmulrooney 23:273a2f93ae99 751 void SX1272::Standby( void )
tmulrooney 23:273a2f93ae99 752 {
tmulrooney 23:273a2f93ae99 753 debug("Standby\r\n");
tmulrooney 23:273a2f93ae99 754 txTimeoutTimer.detach( );
tmulrooney 23:273a2f93ae99 755 rxTimeoutTimer.detach( );
tmulrooney 23:273a2f93ae99 756
tmulrooney 23:273a2f93ae99 757 SetOpMode( RF_OPMODE_STANDBY );
tmulrooney 23:273a2f93ae99 758 this->settings.State = RF_IDLE;
tmulrooney 23:273a2f93ae99 759 }
tmulrooney 23:273a2f93ae99 760
tmulrooney 23:273a2f93ae99 761 void SX1272::Rx( uint32_t timeout )
tmulrooney 23:273a2f93ae99 762 {
tmulrooney 23:273a2f93ae99 763 debug("Rx\r\n");
tmulrooney 23:273a2f93ae99 764 bool rxContinuous = false;
tmulrooney 23:273a2f93ae99 765
tmulrooney 23:273a2f93ae99 766 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 767 {
tmulrooney 23:273a2f93ae99 768 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 769 {
tmulrooney 23:273a2f93ae99 770 rxContinuous = this->settings.Fsk.RxContinuous;
tmulrooney 23:273a2f93ae99 771
tmulrooney 23:273a2f93ae99 772 // DIO0=PayloadReady
tmulrooney 23:273a2f93ae99 773 // DIO1=FifoLevel
tmulrooney 23:273a2f93ae99 774 // DIO2=SyncAddr
tmulrooney 23:273a2f93ae99 775 // DIO3=FifoEmpty
tmulrooney 23:273a2f93ae99 776 // DIO4=Preamble
tmulrooney 23:273a2f93ae99 777 // DIO5=ModeReady
tmulrooney 23:273a2f93ae99 778 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
tmulrooney 23:273a2f93ae99 779 RF_DIOMAPPING1_DIO2_MASK ) |
tmulrooney 23:273a2f93ae99 780 RF_DIOMAPPING1_DIO0_00 |
tmulrooney 23:273a2f93ae99 781 RF_DIOMAPPING1_DIO2_11 );
tmulrooney 23:273a2f93ae99 782
tmulrooney 23:273a2f93ae99 783 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
tmulrooney 23:273a2f93ae99 784 RF_DIOMAPPING2_MAP_MASK ) |
tmulrooney 23:273a2f93ae99 785 RF_DIOMAPPING2_DIO4_11 |
tmulrooney 23:273a2f93ae99 786 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
tmulrooney 23:273a2f93ae99 787
tmulrooney 23:273a2f93ae99 788 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
tmulrooney 23:273a2f93ae99 789
tmulrooney 23:273a2f93ae99 790 this->settings.FskPacketHandler.PreambleDetected = false;
tmulrooney 23:273a2f93ae99 791 this->settings.FskPacketHandler.SyncWordDetected = false;
tmulrooney 23:273a2f93ae99 792 this->settings.FskPacketHandler.NbBytes = 0;
tmulrooney 23:273a2f93ae99 793 this->settings.FskPacketHandler.Size = 0;
tmulrooney 23:273a2f93ae99 794 }
tmulrooney 23:273a2f93ae99 795 break;
tmulrooney 23:273a2f93ae99 796 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 797 {
tmulrooney 23:273a2f93ae99 798 if( this->settings.LoRa.IqInverted == true )
tmulrooney 23:273a2f93ae99 799 {
tmulrooney 23:273a2f93ae99 800 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
tmulrooney 23:273a2f93ae99 801 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
tmulrooney 23:273a2f93ae99 802 }
tmulrooney 23:273a2f93ae99 803 else
tmulrooney 23:273a2f93ae99 804 {
tmulrooney 23:273a2f93ae99 805 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
tmulrooney 23:273a2f93ae99 806 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
tmulrooney 23:273a2f93ae99 807 }
tmulrooney 23:273a2f93ae99 808
tmulrooney 23:273a2f93ae99 809
tmulrooney 23:273a2f93ae99 810 // ERRATA 2.3 - Receiver Spurious Reception of a LoRa Signal
tmulrooney 23:273a2f93ae99 811 if( this->settings.LoRa.Bandwidth < 9 )
tmulrooney 23:273a2f93ae99 812 {
tmulrooney 23:273a2f93ae99 813 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) & 0x7F );
tmulrooney 23:273a2f93ae99 814 Write( REG_LR_TEST30, 0x00 );
tmulrooney 23:273a2f93ae99 815 switch( this->settings.LoRa.Bandwidth )
tmulrooney 23:273a2f93ae99 816 {
tmulrooney 23:273a2f93ae99 817 case 0: // 7.8 kHz
tmulrooney 23:273a2f93ae99 818 Write( REG_LR_TEST2F, 0x48 );
tmulrooney 23:273a2f93ae99 819 SetChannel(this->settings.Channel + 7.81e3 );
tmulrooney 23:273a2f93ae99 820 break;
tmulrooney 23:273a2f93ae99 821 case 1: // 10.4 kHz
tmulrooney 23:273a2f93ae99 822 Write( REG_LR_TEST2F, 0x44 );
tmulrooney 23:273a2f93ae99 823 SetChannel(this->settings.Channel + 10.42e3 );
tmulrooney 23:273a2f93ae99 824 break;
tmulrooney 23:273a2f93ae99 825 case 2: // 15.6 kHz
tmulrooney 23:273a2f93ae99 826 Write( REG_LR_TEST2F, 0x44 );
tmulrooney 23:273a2f93ae99 827 SetChannel(this->settings.Channel + 15.62e3 );
tmulrooney 23:273a2f93ae99 828 break;
tmulrooney 23:273a2f93ae99 829 case 3: // 20.8 kHz
tmulrooney 23:273a2f93ae99 830 Write( REG_LR_TEST2F, 0x44 );
tmulrooney 23:273a2f93ae99 831 SetChannel(this->settings.Channel + 20.83e3 );
tmulrooney 23:273a2f93ae99 832 break;
tmulrooney 23:273a2f93ae99 833 case 4: // 31.2 kHz
tmulrooney 23:273a2f93ae99 834 Write( REG_LR_TEST2F, 0x44 );
tmulrooney 23:273a2f93ae99 835 SetChannel(this->settings.Channel + 31.25e3 );
tmulrooney 23:273a2f93ae99 836 break;
tmulrooney 23:273a2f93ae99 837 case 5: // 41.4 kHz
tmulrooney 23:273a2f93ae99 838 Write( REG_LR_TEST2F, 0x44 );
tmulrooney 23:273a2f93ae99 839 SetChannel(this->settings.Channel + 41.67e3 );
tmulrooney 23:273a2f93ae99 840 break;
tmulrooney 23:273a2f93ae99 841 case 6: // 62.5 kHz
tmulrooney 23:273a2f93ae99 842 Write( REG_LR_TEST2F, 0x40 );
tmulrooney 23:273a2f93ae99 843 break;
tmulrooney 23:273a2f93ae99 844 case 7: // 125 kHz
tmulrooney 23:273a2f93ae99 845 Write( REG_LR_TEST2F, 0x40 );
tmulrooney 23:273a2f93ae99 846 break;
tmulrooney 23:273a2f93ae99 847 case 8: // 250 kHz
tmulrooney 23:273a2f93ae99 848 Write( REG_LR_TEST2F, 0x40 );
tmulrooney 23:273a2f93ae99 849 break;
tmulrooney 23:273a2f93ae99 850 }
tmulrooney 23:273a2f93ae99 851 }
tmulrooney 23:273a2f93ae99 852 else
tmulrooney 23:273a2f93ae99 853 {
tmulrooney 23:273a2f93ae99 854 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) | 0x80 );
tmulrooney 23:273a2f93ae99 855 }
tmulrooney 23:273a2f93ae99 856
tmulrooney 23:273a2f93ae99 857 rxContinuous = this->settings.LoRa.RxContinuous;
tmulrooney 23:273a2f93ae99 858
tmulrooney 23:273a2f93ae99 859 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:273a2f93ae99 860 {
tmulrooney 23:273a2f93ae99 861 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:273a2f93ae99 862 //RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:273a2f93ae99 863 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:273a2f93ae99 864 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:273a2f93ae99 865 RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:273a2f93ae99 866 RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:273a2f93ae99 867 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
tmulrooney 23:273a2f93ae99 868 RFLR_IRQFLAGS_CADDETECTED );
tmulrooney 23:273a2f93ae99 869
tmulrooney 23:273a2f93ae99 870 // DIO0=RxDone, DIO2=FhssChangeChannel
tmulrooney 23:273a2f93ae99 871 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
tmulrooney 23:273a2f93ae99 872 }
tmulrooney 23:273a2f93ae99 873 else
tmulrooney 23:273a2f93ae99 874 {
tmulrooney 23:273a2f93ae99 875 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:273a2f93ae99 876 //RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:273a2f93ae99 877 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:273a2f93ae99 878 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:273a2f93ae99 879 RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:273a2f93ae99 880 RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:273a2f93ae99 881 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
tmulrooney 23:273a2f93ae99 882 RFLR_IRQFLAGS_CADDETECTED );
tmulrooney 23:273a2f93ae99 883
tmulrooney 23:273a2f93ae99 884 // DIO0=RxDone
tmulrooney 23:273a2f93ae99 885 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
tmulrooney 23:273a2f93ae99 886 }
tmulrooney 23:273a2f93ae99 887 Write( REG_LR_FIFORXBASEADDR, 0 );
tmulrooney 23:273a2f93ae99 888 Write( REG_LR_FIFOADDRPTR, 0 );
tmulrooney 23:273a2f93ae99 889 }
tmulrooney 23:273a2f93ae99 890 break;
tmulrooney 23:273a2f93ae99 891 }
tmulrooney 23:273a2f93ae99 892
tmulrooney 23:273a2f93ae99 893 memset( rxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
tmulrooney 23:273a2f93ae99 894
tmulrooney 23:273a2f93ae99 895 this->settings.State = RF_RX_RUNNING;
tmulrooney 23:273a2f93ae99 896 if( timeout != 0 )
tmulrooney 23:273a2f93ae99 897 {
tmulrooney 23:273a2f93ae99 898 rxTimeoutTimer.attach_us( this, &SX1272::OnTimeoutIrq, timeout );
tmulrooney 23:273a2f93ae99 899 }
tmulrooney 23:273a2f93ae99 900
tmulrooney 23:273a2f93ae99 901 if( this->settings.Modem == MODEM_FSK )
tmulrooney 23:273a2f93ae99 902 {
tmulrooney 23:273a2f93ae99 903 SetOpMode( RF_OPMODE_RECEIVER );
tmulrooney 23:273a2f93ae99 904
tmulrooney 23:273a2f93ae99 905 if( rxContinuous == false )
tmulrooney 23:273a2f93ae99 906 {
tmulrooney 23:273a2f93ae99 907 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
tmulrooney 23:273a2f93ae99 908 ( ( Read( REG_SYNCCONFIG ) &
tmulrooney 23:273a2f93ae99 909 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
tmulrooney 23:273a2f93ae99 910 1.0 ) + 10.0 ) /
tmulrooney 23:273a2f93ae99 911 ( double )this->settings.Fsk.Datarate ) * 1e6 );
tmulrooney 23:273a2f93ae99 912 }
tmulrooney 23:273a2f93ae99 913 }
tmulrooney 23:273a2f93ae99 914 else
tmulrooney 23:273a2f93ae99 915 {
tmulrooney 23:273a2f93ae99 916 if( rxContinuous == true )
tmulrooney 23:273a2f93ae99 917 {
tmulrooney 23:273a2f93ae99 918 SetOpMode( RFLR_OPMODE_RECEIVER );
tmulrooney 23:273a2f93ae99 919 }
tmulrooney 23:273a2f93ae99 920 else
tmulrooney 23:273a2f93ae99 921 {
tmulrooney 23:273a2f93ae99 922 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
tmulrooney 23:273a2f93ae99 923 }
tmulrooney 23:273a2f93ae99 924 }
tmulrooney 23:273a2f93ae99 925 }
tmulrooney 23:273a2f93ae99 926
tmulrooney 23:273a2f93ae99 927 void SX1272::Tx( uint32_t timeout )
tmulrooney 23:273a2f93ae99 928 {
tmulrooney 23:273a2f93ae99 929 debug("Tx\r\n");
tmulrooney 23:273a2f93ae99 930
tmulrooney 23:273a2f93ae99 931 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 932 {
tmulrooney 23:273a2f93ae99 933 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 934 {
tmulrooney 23:273a2f93ae99 935 // DIO0=PacketSent
tmulrooney 23:273a2f93ae99 936 // DIO1=FifoLevel
tmulrooney 23:273a2f93ae99 937 // DIO2=FifoFull
tmulrooney 23:273a2f93ae99 938 // DIO3=FifoEmpty
tmulrooney 23:273a2f93ae99 939 // DIO4=LowBat
tmulrooney 23:273a2f93ae99 940 // DIO5=ModeReady
tmulrooney 23:273a2f93ae99 941 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
tmulrooney 23:273a2f93ae99 942 RF_DIOMAPPING1_DIO2_MASK ) );
tmulrooney 23:273a2f93ae99 943
tmulrooney 23:273a2f93ae99 944 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
tmulrooney 23:273a2f93ae99 945 RF_DIOMAPPING2_MAP_MASK ) );
tmulrooney 23:273a2f93ae99 946 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
tmulrooney 23:273a2f93ae99 947 }
tmulrooney 23:273a2f93ae99 948 break;
tmulrooney 23:273a2f93ae99 949 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 950 {
tmulrooney 23:273a2f93ae99 951 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:273a2f93ae99 952 {
tmulrooney 23:273a2f93ae99 953 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:273a2f93ae99 954 RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:273a2f93ae99 955 RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:273a2f93ae99 956 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:273a2f93ae99 957 //RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:273a2f93ae99 958 RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:273a2f93ae99 959 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
tmulrooney 23:273a2f93ae99 960 RFLR_IRQFLAGS_CADDETECTED );
tmulrooney 23:273a2f93ae99 961
tmulrooney 23:273a2f93ae99 962 // DIO0=TxDone, DIO2=FhssChangeChannel
tmulrooney 23:273a2f93ae99 963 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
tmulrooney 23:273a2f93ae99 964 }
tmulrooney 23:273a2f93ae99 965 else
tmulrooney 23:273a2f93ae99 966 {
tmulrooney 23:273a2f93ae99 967 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:273a2f93ae99 968 RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:273a2f93ae99 969 RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:273a2f93ae99 970 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:273a2f93ae99 971 //RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:273a2f93ae99 972 RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:273a2f93ae99 973 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
tmulrooney 23:273a2f93ae99 974 RFLR_IRQFLAGS_CADDETECTED );
tmulrooney 23:273a2f93ae99 975
tmulrooney 23:273a2f93ae99 976 // DIO0=TxDone
tmulrooney 23:273a2f93ae99 977 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
tmulrooney 23:273a2f93ae99 978 }
tmulrooney 23:273a2f93ae99 979 }
tmulrooney 23:273a2f93ae99 980 break;
tmulrooney 23:273a2f93ae99 981 }
tmulrooney 23:273a2f93ae99 982
tmulrooney 23:273a2f93ae99 983 this->settings.State = RF_TX_RUNNING;
tmulrooney 23:273a2f93ae99 984 txTimeoutTimer.attach_us( this, &SX1272::OnTimeoutIrq, timeout );
tmulrooney 23:273a2f93ae99 985 SetOpMode( RF_OPMODE_TRANSMITTER );
tmulrooney 23:273a2f93ae99 986 }
tmulrooney 23:273a2f93ae99 987
tmulrooney 23:273a2f93ae99 988 void SX1272::StartCad( void )
tmulrooney 23:273a2f93ae99 989 {
tmulrooney 23:273a2f93ae99 990 debug("StartCad\r\n");
tmulrooney 23:273a2f93ae99 991 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 992 {
tmulrooney 23:273a2f93ae99 993 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 994 {
tmulrooney 23:273a2f93ae99 995
tmulrooney 23:273a2f93ae99 996 }
tmulrooney 23:273a2f93ae99 997 break;
tmulrooney 23:273a2f93ae99 998 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 999 {
tmulrooney 23:273a2f93ae99 1000 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:273a2f93ae99 1001 RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:273a2f93ae99 1002 RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:273a2f93ae99 1003 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:273a2f93ae99 1004 RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:273a2f93ae99 1005 //RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:273a2f93ae99 1006 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
tmulrooney 23:273a2f93ae99 1007 //RFLR_IRQFLAGS_CADDETECTED
tmulrooney 23:273a2f93ae99 1008 );
tmulrooney 23:273a2f93ae99 1009
tmulrooney 23:273a2f93ae99 1010 // DIO3=CADDone
tmulrooney 23:273a2f93ae99 1011 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
tmulrooney 23:273a2f93ae99 1012
tmulrooney 23:273a2f93ae99 1013 this->settings.State = RF_CAD;
tmulrooney 23:273a2f93ae99 1014 SetOpMode( RFLR_OPMODE_CAD );
tmulrooney 23:273a2f93ae99 1015 }
tmulrooney 23:273a2f93ae99 1016 break;
tmulrooney 23:273a2f93ae99 1017 default:
tmulrooney 23:273a2f93ae99 1018 break;
tmulrooney 23:273a2f93ae99 1019 }
tmulrooney 23:273a2f93ae99 1020 }
tmulrooney 23:273a2f93ae99 1021
tmulrooney 23:273a2f93ae99 1022 int16_t SX1272::GetRssi( RadioModems_t modem )
tmulrooney 23:273a2f93ae99 1023 {
tmulrooney 23:273a2f93ae99 1024 debug("GetRssi\r\n");
tmulrooney 23:273a2f93ae99 1025 int16_t rssi = 0;
tmulrooney 23:273a2f93ae99 1026
tmulrooney 23:273a2f93ae99 1027 switch( modem )
tmulrooney 23:273a2f93ae99 1028 {
tmulrooney 23:273a2f93ae99 1029 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1030 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
tmulrooney 23:273a2f93ae99 1031 break;
tmulrooney 23:273a2f93ae99 1032 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1033 if( this->settings.Channel > RF_MID_BAND_THRESH )
tmulrooney 23:273a2f93ae99 1034 {
tmulrooney 23:273a2f93ae99 1035 rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE );
tmulrooney 23:273a2f93ae99 1036 }
tmulrooney 23:273a2f93ae99 1037 else
tmulrooney 23:273a2f93ae99 1038 {
tmulrooney 23:273a2f93ae99 1039 rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE );
tmulrooney 23:273a2f93ae99 1040 }
tmulrooney 23:273a2f93ae99 1041 break;
tmulrooney 23:273a2f93ae99 1042 default:
tmulrooney 23:273a2f93ae99 1043 rssi = -1;
tmulrooney 23:273a2f93ae99 1044 break;
tmulrooney 23:273a2f93ae99 1045 }
tmulrooney 23:273a2f93ae99 1046 return rssi;
tmulrooney 23:273a2f93ae99 1047 }
tmulrooney 23:273a2f93ae99 1048
tmulrooney 23:273a2f93ae99 1049 void SX1272::SetOpMode( uint8_t opMode )
tmulrooney 23:273a2f93ae99 1050 {
tmulrooney 23:273a2f93ae99 1051 debug("SetOpMode %02X\r\n",opMode);
tmulrooney 23:273a2f93ae99 1052 if( opMode != previousOpMode )
tmulrooney 23:273a2f93ae99 1053 {
tmulrooney 23:273a2f93ae99 1054 previousOpMode = opMode;
tmulrooney 23:273a2f93ae99 1055 if( opMode == RF_OPMODE_SLEEP )
tmulrooney 23:273a2f93ae99 1056 {
tmulrooney 23:273a2f93ae99 1057 SetAntSwLowPower( true );
tmulrooney 23:273a2f93ae99 1058 }
tmulrooney 23:273a2f93ae99 1059 else
tmulrooney 23:273a2f93ae99 1060 {
tmulrooney 23:273a2f93ae99 1061 SetAntSwLowPower( false );
tmulrooney 23:273a2f93ae99 1062 if( opMode == RF_OPMODE_TRANSMITTER )
tmulrooney 23:273a2f93ae99 1063 {
tmulrooney 23:273a2f93ae99 1064 SetAntSw( 1 );
tmulrooney 23:273a2f93ae99 1065 }
tmulrooney 23:273a2f93ae99 1066 else
tmulrooney 23:273a2f93ae99 1067 {
tmulrooney 23:273a2f93ae99 1068 SetAntSw( 0 );
tmulrooney 23:273a2f93ae99 1069 }
tmulrooney 23:273a2f93ae99 1070 }
tmulrooney 23:273a2f93ae99 1071 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
tmulrooney 23:273a2f93ae99 1072 }
tmulrooney 23:273a2f93ae99 1073 }
tmulrooney 23:273a2f93ae99 1074
tmulrooney 23:273a2f93ae99 1075 void SX1272::SetModem( RadioModems_t modem )
tmulrooney 23:273a2f93ae99 1076 {
tmulrooney 23:273a2f93ae99 1077 debug("SetModem %d\r\n",modem);
tmulrooney 23:273a2f93ae99 1078 if( this->settings.Modem == modem )
tmulrooney 23:273a2f93ae99 1079 {
tmulrooney 23:273a2f93ae99 1080 return;
tmulrooney 23:273a2f93ae99 1081 }
tmulrooney 23:273a2f93ae99 1082
tmulrooney 23:273a2f93ae99 1083 this->settings.Modem = modem;
tmulrooney 23:273a2f93ae99 1084 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 1085 {
tmulrooney 23:273a2f93ae99 1086 default:
tmulrooney 23:273a2f93ae99 1087 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1088 SetOpMode( RF_OPMODE_SLEEP );
tmulrooney 23:273a2f93ae99 1089 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
tmulrooney 23:273a2f93ae99 1090
tmulrooney 23:273a2f93ae99 1091 Write( REG_DIOMAPPING1, 0x00 );
tmulrooney 23:273a2f93ae99 1092 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
tmulrooney 23:273a2f93ae99 1093 break;
tmulrooney 23:273a2f93ae99 1094 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1095 SetOpMode( RF_OPMODE_SLEEP );
tmulrooney 23:273a2f93ae99 1096 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
tmulrooney 23:273a2f93ae99 1097
tmulrooney 23:273a2f93ae99 1098 Write( REG_DIOMAPPING1, 0x00 );
tmulrooney 23:273a2f93ae99 1099 Write( REG_DIOMAPPING2, 0x00 );
tmulrooney 23:273a2f93ae99 1100 break;
tmulrooney 23:273a2f93ae99 1101 }
tmulrooney 23:273a2f93ae99 1102 }
tmulrooney 23:273a2f93ae99 1103
tmulrooney 23:273a2f93ae99 1104 void SX1272::SetMaxPayloadLength( RadioModems_t modem, uint8_t max )
tmulrooney 23:273a2f93ae99 1105 {
tmulrooney 23:273a2f93ae99 1106 debug("SetMaxPayloadLength\r\n");
tmulrooney 23:273a2f93ae99 1107 this->SetModem( modem );
tmulrooney 23:273a2f93ae99 1108
tmulrooney 23:273a2f93ae99 1109 switch( modem )
tmulrooney 23:273a2f93ae99 1110 {
tmulrooney 23:273a2f93ae99 1111 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1112 if( this->settings.Fsk.FixLen == false )
tmulrooney 23:273a2f93ae99 1113 {
tmulrooney 23:273a2f93ae99 1114 this->Write( REG_PAYLOADLENGTH, max );
tmulrooney 23:273a2f93ae99 1115 }
tmulrooney 23:273a2f93ae99 1116 break;
tmulrooney 23:273a2f93ae99 1117 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1118 this->Write( REG_LR_PAYLOADMAXLENGTH, max );
tmulrooney 23:273a2f93ae99 1119 break;
tmulrooney 23:273a2f93ae99 1120 }
tmulrooney 23:273a2f93ae99 1121 }
tmulrooney 23:273a2f93ae99 1122
tmulrooney 23:273a2f93ae99 1123 void SX1272::OnTimeoutIrq( void )
tmulrooney 23:273a2f93ae99 1124 {
tmulrooney 23:273a2f93ae99 1125 debug("OnTimeoutIrq\r\n");
tmulrooney 23:273a2f93ae99 1126 switch( this->settings.State )
tmulrooney 23:273a2f93ae99 1127 {
tmulrooney 23:273a2f93ae99 1128 case RF_RX_RUNNING:
tmulrooney 23:273a2f93ae99 1129 if( this->settings.Modem == MODEM_FSK )
tmulrooney 23:273a2f93ae99 1130 {
tmulrooney 23:273a2f93ae99 1131 this->settings.FskPacketHandler.PreambleDetected = false;
tmulrooney 23:273a2f93ae99 1132 this->settings.FskPacketHandler.SyncWordDetected = false;
tmulrooney 23:273a2f93ae99 1133 this->settings.FskPacketHandler.NbBytes = 0;
tmulrooney 23:273a2f93ae99 1134 this->settings.FskPacketHandler.Size = 0;
tmulrooney 23:273a2f93ae99 1135
tmulrooney 23:273a2f93ae99 1136 // Clear Irqs
tmulrooney 23:273a2f93ae99 1137 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
tmulrooney 23:273a2f93ae99 1138 RF_IRQFLAGS1_PREAMBLEDETECT |
tmulrooney 23:273a2f93ae99 1139 RF_IRQFLAGS1_SYNCADDRESSMATCH );
tmulrooney 23:273a2f93ae99 1140 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
tmulrooney 23:273a2f93ae99 1141
tmulrooney 23:273a2f93ae99 1142 if( this->settings.Fsk.RxContinuous == true )
tmulrooney 23:273a2f93ae99 1143 {
tmulrooney 23:273a2f93ae99 1144 // Continuous mode restart Rx chain
tmulrooney 23:273a2f93ae99 1145 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
tmulrooney 23:273a2f93ae99 1146 }
tmulrooney 23:273a2f93ae99 1147 else
tmulrooney 23:273a2f93ae99 1148 {
tmulrooney 23:273a2f93ae99 1149 this->settings.State = RF_IDLE;
tmulrooney 23:273a2f93ae99 1150 rxTimeoutSyncWord.detach( );
tmulrooney 23:273a2f93ae99 1151 }
tmulrooney 23:273a2f93ae99 1152 }
tmulrooney 23:273a2f93ae99 1153 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
tmulrooney 23:273a2f93ae99 1154 {
tmulrooney 23:273a2f93ae99 1155 this->RadioEvents->RxTimeout( );
tmulrooney 23:273a2f93ae99 1156 }
tmulrooney 23:273a2f93ae99 1157 break;
tmulrooney 23:273a2f93ae99 1158 case RF_TX_RUNNING:
tmulrooney 23:273a2f93ae99 1159 this->settings.State = RF_IDLE;
tmulrooney 23:273a2f93ae99 1160 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxTimeout != NULL ) )
tmulrooney 23:273a2f93ae99 1161 {
tmulrooney 23:273a2f93ae99 1162 this->RadioEvents->TxTimeout( );
tmulrooney 23:273a2f93ae99 1163 }
tmulrooney 23:273a2f93ae99 1164 break;
tmulrooney 23:273a2f93ae99 1165 default:
tmulrooney 23:273a2f93ae99 1166 break;
tmulrooney 23:273a2f93ae99 1167 }
tmulrooney 23:273a2f93ae99 1168 }
tmulrooney 23:273a2f93ae99 1169
tmulrooney 23:273a2f93ae99 1170 void SX1272::OnDio0Irq( void )
tmulrooney 23:273a2f93ae99 1171 {
tmulrooney 23:273a2f93ae99 1172 debug("OnDio0Irq\r\n");
tmulrooney 23:273a2f93ae99 1173 volatile uint8_t irqFlags = 0;
tmulrooney 23:273a2f93ae99 1174
tmulrooney 23:273a2f93ae99 1175 switch( this->settings.State )
tmulrooney 23:273a2f93ae99 1176 {
tmulrooney 23:273a2f93ae99 1177 case RF_RX_RUNNING:
tmulrooney 23:273a2f93ae99 1178 //TimerStop( &RxTimeoutTimer );
tmulrooney 23:273a2f93ae99 1179 // RxDone interrupt
tmulrooney 23:273a2f93ae99 1180 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 1181 {
tmulrooney 23:273a2f93ae99 1182 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1183 if( this->settings.Fsk.CrcOn == true )
tmulrooney 23:273a2f93ae99 1184 {
tmulrooney 23:273a2f93ae99 1185 irqFlags = Read( REG_IRQFLAGS2 );
tmulrooney 23:273a2f93ae99 1186 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
tmulrooney 23:273a2f93ae99 1187 {
tmulrooney 23:273a2f93ae99 1188 // Clear Irqs
tmulrooney 23:273a2f93ae99 1189 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
tmulrooney 23:273a2f93ae99 1190 RF_IRQFLAGS1_PREAMBLEDETECT |
tmulrooney 23:273a2f93ae99 1191 RF_IRQFLAGS1_SYNCADDRESSMATCH );
tmulrooney 23:273a2f93ae99 1192 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
tmulrooney 23:273a2f93ae99 1193
tmulrooney 23:273a2f93ae99 1194 if( this->settings.Fsk.RxContinuous == false )
tmulrooney 23:273a2f93ae99 1195 {
tmulrooney 23:273a2f93ae99 1196 this->settings.State = RF_IDLE;
tmulrooney 23:273a2f93ae99 1197 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
tmulrooney 23:273a2f93ae99 1198 ( ( Read( REG_SYNCCONFIG ) &
tmulrooney 23:273a2f93ae99 1199 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
tmulrooney 23:273a2f93ae99 1200 1.0 ) + 10.0 ) /
tmulrooney 23:273a2f93ae99 1201 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
tmulrooney 23:273a2f93ae99 1202 }
tmulrooney 23:273a2f93ae99 1203 else
tmulrooney 23:273a2f93ae99 1204 {
tmulrooney 23:273a2f93ae99 1205 // Continuous mode restart Rx chain
tmulrooney 23:273a2f93ae99 1206 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
tmulrooney 23:273a2f93ae99 1207 }
tmulrooney 23:273a2f93ae99 1208 rxTimeoutTimer.detach( );
tmulrooney 23:273a2f93ae99 1209
tmulrooney 23:273a2f93ae99 1210 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
tmulrooney 23:273a2f93ae99 1211 {
tmulrooney 23:273a2f93ae99 1212 this->RadioEvents->RxError( );
tmulrooney 23:273a2f93ae99 1213 }
tmulrooney 23:273a2f93ae99 1214 this->settings.FskPacketHandler.PreambleDetected = false;
tmulrooney 23:273a2f93ae99 1215 this->settings.FskPacketHandler.SyncWordDetected = false;
tmulrooney 23:273a2f93ae99 1216 this->settings.FskPacketHandler.NbBytes = 0;
tmulrooney 23:273a2f93ae99 1217 this->settings.FskPacketHandler.Size = 0;
tmulrooney 23:273a2f93ae99 1218 break;
tmulrooney 23:273a2f93ae99 1219 }
tmulrooney 23:273a2f93ae99 1220 }
tmulrooney 23:273a2f93ae99 1221
tmulrooney 23:273a2f93ae99 1222 // Read received packet size
tmulrooney 23:273a2f93ae99 1223 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
tmulrooney 23:273a2f93ae99 1224 {
tmulrooney 23:273a2f93ae99 1225 if( this->settings.Fsk.FixLen == false )
tmulrooney 23:273a2f93ae99 1226 {
tmulrooney 23:273a2f93ae99 1227 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
tmulrooney 23:273a2f93ae99 1228 }
tmulrooney 23:273a2f93ae99 1229 else
tmulrooney 23:273a2f93ae99 1230 {
tmulrooney 23:273a2f93ae99 1231 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
tmulrooney 23:273a2f93ae99 1232 }
tmulrooney 23:273a2f93ae99 1233 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:273a2f93ae99 1234 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:273a2f93ae99 1235 }
tmulrooney 23:273a2f93ae99 1236 else
tmulrooney 23:273a2f93ae99 1237 {
tmulrooney 23:273a2f93ae99 1238 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:273a2f93ae99 1239 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:273a2f93ae99 1240 }
tmulrooney 23:273a2f93ae99 1241
tmulrooney 23:273a2f93ae99 1242 if( this->settings.Fsk.RxContinuous == false )
tmulrooney 23:273a2f93ae99 1243 {
tmulrooney 23:273a2f93ae99 1244 this->settings.State = RF_IDLE;
tmulrooney 23:273a2f93ae99 1245 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
tmulrooney 23:273a2f93ae99 1246 ( ( Read( REG_SYNCCONFIG ) &
tmulrooney 23:273a2f93ae99 1247 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
tmulrooney 23:273a2f93ae99 1248 1.0 ) + 10.0 ) /
tmulrooney 23:273a2f93ae99 1249 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
tmulrooney 23:273a2f93ae99 1250 }
tmulrooney 23:273a2f93ae99 1251 else
tmulrooney 23:273a2f93ae99 1252 {
tmulrooney 23:273a2f93ae99 1253 // Continuous mode restart Rx chain
tmulrooney 23:273a2f93ae99 1254 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
tmulrooney 23:273a2f93ae99 1255 }
tmulrooney 23:273a2f93ae99 1256 rxTimeoutTimer.detach( );
tmulrooney 23:273a2f93ae99 1257
tmulrooney 23:273a2f93ae99 1258 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
tmulrooney 23:273a2f93ae99 1259 {
tmulrooney 23:273a2f93ae99 1260 this->RadioEvents->RxDone( rxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
tmulrooney 23:273a2f93ae99 1261 }
tmulrooney 23:273a2f93ae99 1262 this->settings.FskPacketHandler.PreambleDetected = false;
tmulrooney 23:273a2f93ae99 1263 this->settings.FskPacketHandler.SyncWordDetected = false;
tmulrooney 23:273a2f93ae99 1264 this->settings.FskPacketHandler.NbBytes = 0;
tmulrooney 23:273a2f93ae99 1265 this->settings.FskPacketHandler.Size = 0;
tmulrooney 23:273a2f93ae99 1266 break;
tmulrooney 23:273a2f93ae99 1267 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1268 {
tmulrooney 23:273a2f93ae99 1269 int8_t snr = 0;
tmulrooney 23:273a2f93ae99 1270
tmulrooney 23:273a2f93ae99 1271 // Clear Irq
tmulrooney 23:273a2f93ae99 1272 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
tmulrooney 23:273a2f93ae99 1273
tmulrooney 23:273a2f93ae99 1274 irqFlags = Read( REG_LR_IRQFLAGS );
tmulrooney 23:273a2f93ae99 1275 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
tmulrooney 23:273a2f93ae99 1276 {
tmulrooney 23:273a2f93ae99 1277 // Clear Irq
tmulrooney 23:273a2f93ae99 1278 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
tmulrooney 23:273a2f93ae99 1279
tmulrooney 23:273a2f93ae99 1280 if( this->settings.LoRa.RxContinuous == false )
tmulrooney 23:273a2f93ae99 1281 {
tmulrooney 23:273a2f93ae99 1282 this->settings.State = RF_IDLE;
tmulrooney 23:273a2f93ae99 1283 }
tmulrooney 23:273a2f93ae99 1284 rxTimeoutTimer.detach( );
tmulrooney 23:273a2f93ae99 1285
tmulrooney 23:273a2f93ae99 1286 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
tmulrooney 23:273a2f93ae99 1287 {
tmulrooney 23:273a2f93ae99 1288 this->RadioEvents->RxError( );
tmulrooney 23:273a2f93ae99 1289 }
tmulrooney 23:273a2f93ae99 1290 break;
tmulrooney 23:273a2f93ae99 1291 }
tmulrooney 23:273a2f93ae99 1292
tmulrooney 23:273a2f93ae99 1293 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
tmulrooney 23:273a2f93ae99 1294 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
tmulrooney 23:273a2f93ae99 1295 {
tmulrooney 23:273a2f93ae99 1296 // Invert and divide by 4
tmulrooney 23:273a2f93ae99 1297 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
tmulrooney 23:273a2f93ae99 1298 snr = -snr;
tmulrooney 23:273a2f93ae99 1299 }
tmulrooney 23:273a2f93ae99 1300 else
tmulrooney 23:273a2f93ae99 1301 {
tmulrooney 23:273a2f93ae99 1302 // Divide by 4
tmulrooney 23:273a2f93ae99 1303 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
tmulrooney 23:273a2f93ae99 1304 }
tmulrooney 23:273a2f93ae99 1305
tmulrooney 23:273a2f93ae99 1306 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
tmulrooney 23:273a2f93ae99 1307 if( snr < 0 )
tmulrooney 23:273a2f93ae99 1308 {
tmulrooney 23:273a2f93ae99 1309 if( this->settings.Channel > RF_MID_BAND_THRESH )
tmulrooney 23:273a2f93ae99 1310 {
tmulrooney 23:273a2f93ae99 1311 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
tmulrooney 23:273a2f93ae99 1312 snr;
tmulrooney 23:273a2f93ae99 1313 }
tmulrooney 23:273a2f93ae99 1314 else
tmulrooney 23:273a2f93ae99 1315 {
tmulrooney 23:273a2f93ae99 1316 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
tmulrooney 23:273a2f93ae99 1317 snr;
tmulrooney 23:273a2f93ae99 1318 }
tmulrooney 23:273a2f93ae99 1319 }
tmulrooney 23:273a2f93ae99 1320 else
tmulrooney 23:273a2f93ae99 1321 {
tmulrooney 23:273a2f93ae99 1322 if( this->settings.Channel > RF_MID_BAND_THRESH )
tmulrooney 23:273a2f93ae99 1323 {
tmulrooney 23:273a2f93ae99 1324 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
tmulrooney 23:273a2f93ae99 1325 }
tmulrooney 23:273a2f93ae99 1326 else
tmulrooney 23:273a2f93ae99 1327 {
tmulrooney 23:273a2f93ae99 1328 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
tmulrooney 23:273a2f93ae99 1329 }
tmulrooney 23:273a2f93ae99 1330 }
tmulrooney 23:273a2f93ae99 1331
tmulrooney 23:273a2f93ae99 1332 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
tmulrooney 23:273a2f93ae99 1333 ReadFifo( rxBuffer, this->settings.LoRaPacketHandler.Size );
tmulrooney 23:273a2f93ae99 1334
tmulrooney 23:273a2f93ae99 1335 if( this->settings.LoRa.RxContinuous == false )
tmulrooney 23:273a2f93ae99 1336 {
tmulrooney 23:273a2f93ae99 1337 this->settings.State = RF_IDLE;
tmulrooney 23:273a2f93ae99 1338 }
tmulrooney 23:273a2f93ae99 1339 rxTimeoutTimer.detach( );
tmulrooney 23:273a2f93ae99 1340
tmulrooney 23:273a2f93ae99 1341 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
tmulrooney 23:273a2f93ae99 1342 {
tmulrooney 23:273a2f93ae99 1343 this->RadioEvents->RxDone( rxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
tmulrooney 23:273a2f93ae99 1344 }
tmulrooney 23:273a2f93ae99 1345 }
tmulrooney 23:273a2f93ae99 1346 break;
tmulrooney 23:273a2f93ae99 1347 default:
tmulrooney 23:273a2f93ae99 1348 break;
tmulrooney 23:273a2f93ae99 1349 }
tmulrooney 23:273a2f93ae99 1350 break;
tmulrooney 23:273a2f93ae99 1351 case RF_TX_RUNNING:
tmulrooney 23:273a2f93ae99 1352 txTimeoutTimer.detach( );
tmulrooney 23:273a2f93ae99 1353 // TxDone interrupt
tmulrooney 23:273a2f93ae99 1354 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 1355 {
tmulrooney 23:273a2f93ae99 1356 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1357 // Clear Irq
tmulrooney 23:273a2f93ae99 1358 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
tmulrooney 23:273a2f93ae99 1359 // Intentional fall through
tmulrooney 23:273a2f93ae99 1360 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1361 default:
tmulrooney 23:273a2f93ae99 1362 this->settings.State = RF_IDLE;
tmulrooney 23:273a2f93ae99 1363 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) )
tmulrooney 23:273a2f93ae99 1364 {
tmulrooney 23:273a2f93ae99 1365 this->RadioEvents->TxDone( );
tmulrooney 23:273a2f93ae99 1366 }
tmulrooney 23:273a2f93ae99 1367 break;
tmulrooney 23:273a2f93ae99 1368 }
tmulrooney 23:273a2f93ae99 1369 break;
tmulrooney 23:273a2f93ae99 1370 default:
tmulrooney 23:273a2f93ae99 1371 break;
tmulrooney 23:273a2f93ae99 1372 }
tmulrooney 23:273a2f93ae99 1373 }
tmulrooney 23:273a2f93ae99 1374
tmulrooney 23:273a2f93ae99 1375 void SX1272::OnDio1Irq( void )
tmulrooney 23:273a2f93ae99 1376 {
tmulrooney 23:273a2f93ae99 1377 debug("OnDio1Irq\r\n");
tmulrooney 23:273a2f93ae99 1378 switch( this->settings.State )
tmulrooney 23:273a2f93ae99 1379 {
tmulrooney 23:273a2f93ae99 1380 case RF_RX_RUNNING:
tmulrooney 23:273a2f93ae99 1381 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 1382 {
tmulrooney 23:273a2f93ae99 1383 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1384 // FifoLevel interrupt
tmulrooney 23:273a2f93ae99 1385 // Read received packet size
tmulrooney 23:273a2f93ae99 1386 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
tmulrooney 23:273a2f93ae99 1387 {
tmulrooney 23:273a2f93ae99 1388 if( this->settings.Fsk.FixLen == false )
tmulrooney 23:273a2f93ae99 1389 {
tmulrooney 23:273a2f93ae99 1390 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
tmulrooney 23:273a2f93ae99 1391 }
tmulrooney 23:273a2f93ae99 1392 else
tmulrooney 23:273a2f93ae99 1393 {
tmulrooney 23:273a2f93ae99 1394 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
tmulrooney 23:273a2f93ae99 1395 }
tmulrooney 23:273a2f93ae99 1396 }
tmulrooney 23:273a2f93ae99 1397
tmulrooney 23:273a2f93ae99 1398 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
tmulrooney 23:273a2f93ae99 1399 {
tmulrooney 23:273a2f93ae99 1400 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
tmulrooney 23:273a2f93ae99 1401 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
tmulrooney 23:273a2f93ae99 1402 }
tmulrooney 23:273a2f93ae99 1403 else
tmulrooney 23:273a2f93ae99 1404 {
tmulrooney 23:273a2f93ae99 1405 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:273a2f93ae99 1406 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:273a2f93ae99 1407 }
tmulrooney 23:273a2f93ae99 1408 break;
tmulrooney 23:273a2f93ae99 1409 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1410 // Sync time out
tmulrooney 23:273a2f93ae99 1411 rxTimeoutTimer.detach( );
tmulrooney 23:273a2f93ae99 1412 this->settings.State = RF_IDLE;
tmulrooney 23:273a2f93ae99 1413 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
tmulrooney 23:273a2f93ae99 1414 {
tmulrooney 23:273a2f93ae99 1415 this->RadioEvents->RxTimeout( );
tmulrooney 23:273a2f93ae99 1416 }
tmulrooney 23:273a2f93ae99 1417 break;
tmulrooney 23:273a2f93ae99 1418 default:
tmulrooney 23:273a2f93ae99 1419 break;
tmulrooney 23:273a2f93ae99 1420 }
tmulrooney 23:273a2f93ae99 1421 break;
tmulrooney 23:273a2f93ae99 1422 case RF_TX_RUNNING:
tmulrooney 23:273a2f93ae99 1423 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 1424 {
tmulrooney 23:273a2f93ae99 1425 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1426 // FifoLevel interrupt
tmulrooney 23:273a2f93ae99 1427 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
tmulrooney 23:273a2f93ae99 1428 {
tmulrooney 23:273a2f93ae99 1429 WriteFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
tmulrooney 23:273a2f93ae99 1430 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
tmulrooney 23:273a2f93ae99 1431 }
tmulrooney 23:273a2f93ae99 1432 else
tmulrooney 23:273a2f93ae99 1433 {
tmulrooney 23:273a2f93ae99 1434 // Write the last chunk of data
tmulrooney 23:273a2f93ae99 1435 WriteFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:273a2f93ae99 1436 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
tmulrooney 23:273a2f93ae99 1437 }
tmulrooney 23:273a2f93ae99 1438 break;
tmulrooney 23:273a2f93ae99 1439 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1440 break;
tmulrooney 23:273a2f93ae99 1441 default:
tmulrooney 23:273a2f93ae99 1442 break;
tmulrooney 23:273a2f93ae99 1443 }
tmulrooney 23:273a2f93ae99 1444 break;
tmulrooney 23:273a2f93ae99 1445 default:
tmulrooney 23:273a2f93ae99 1446 break;
tmulrooney 23:273a2f93ae99 1447 }
tmulrooney 23:273a2f93ae99 1448 }
tmulrooney 23:273a2f93ae99 1449
tmulrooney 23:273a2f93ae99 1450 void SX1272::OnDio2Irq( void )
tmulrooney 23:273a2f93ae99 1451 {
tmulrooney 23:273a2f93ae99 1452 debug("OnDio2Irq\r\n");
tmulrooney 23:273a2f93ae99 1453 switch( this->settings.State )
tmulrooney 23:273a2f93ae99 1454 {
tmulrooney 23:273a2f93ae99 1455 case RF_RX_RUNNING:
tmulrooney 23:273a2f93ae99 1456 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 1457 {
tmulrooney 23:273a2f93ae99 1458 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1459 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
tmulrooney 23:273a2f93ae99 1460 {
tmulrooney 23:273a2f93ae99 1461 rxTimeoutSyncWord.detach( );
tmulrooney 23:273a2f93ae99 1462
tmulrooney 23:273a2f93ae99 1463 this->settings.FskPacketHandler.SyncWordDetected = true;
tmulrooney 23:273a2f93ae99 1464
tmulrooney 23:273a2f93ae99 1465 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
tmulrooney 23:273a2f93ae99 1466
tmulrooney 23:273a2f93ae99 1467 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
tmulrooney 23:273a2f93ae99 1468 ( uint16_t )Read( REG_AFCLSB ) ) *
tmulrooney 23:273a2f93ae99 1469 ( double )FREQ_STEP;
tmulrooney 23:273a2f93ae99 1470 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
tmulrooney 23:273a2f93ae99 1471 }
tmulrooney 23:273a2f93ae99 1472 break;
tmulrooney 23:273a2f93ae99 1473 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1474 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:273a2f93ae99 1475 {
tmulrooney 23:273a2f93ae99 1476 // Clear Irq
tmulrooney 23:273a2f93ae99 1477 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
tmulrooney 23:273a2f93ae99 1478
tmulrooney 23:273a2f93ae99 1479 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
tmulrooney 23:273a2f93ae99 1480 {
tmulrooney 23:273a2f93ae99 1481 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
tmulrooney 23:273a2f93ae99 1482 }
tmulrooney 23:273a2f93ae99 1483 }
tmulrooney 23:273a2f93ae99 1484 break;
tmulrooney 23:273a2f93ae99 1485 default:
tmulrooney 23:273a2f93ae99 1486 break;
tmulrooney 23:273a2f93ae99 1487 }
tmulrooney 23:273a2f93ae99 1488 break;
tmulrooney 23:273a2f93ae99 1489 case RF_TX_RUNNING:
tmulrooney 23:273a2f93ae99 1490 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 1491 {
tmulrooney 23:273a2f93ae99 1492 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1493 break;
tmulrooney 23:273a2f93ae99 1494 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1495 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:273a2f93ae99 1496 {
tmulrooney 23:273a2f93ae99 1497 // Clear Irq
tmulrooney 23:273a2f93ae99 1498 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
tmulrooney 23:273a2f93ae99 1499
tmulrooney 23:273a2f93ae99 1500 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
tmulrooney 23:273a2f93ae99 1501 {
tmulrooney 23:273a2f93ae99 1502 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
tmulrooney 23:273a2f93ae99 1503 }
tmulrooney 23:273a2f93ae99 1504 }
tmulrooney 23:273a2f93ae99 1505 break;
tmulrooney 23:273a2f93ae99 1506 default:
tmulrooney 23:273a2f93ae99 1507 break;
tmulrooney 23:273a2f93ae99 1508 }
tmulrooney 23:273a2f93ae99 1509 break;
tmulrooney 23:273a2f93ae99 1510 default:
tmulrooney 23:273a2f93ae99 1511 break;
tmulrooney 23:273a2f93ae99 1512 }
tmulrooney 23:273a2f93ae99 1513 }
tmulrooney 23:273a2f93ae99 1514
tmulrooney 23:273a2f93ae99 1515 void SX1272::OnDio3Irq( void )
tmulrooney 23:273a2f93ae99 1516 {
tmulrooney 23:273a2f93ae99 1517 debug("OnDio3Irq\r\n");
tmulrooney 23:273a2f93ae99 1518 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 1519 {
tmulrooney 23:273a2f93ae99 1520 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1521 break;
tmulrooney 23:273a2f93ae99 1522 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1523 if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
tmulrooney 23:273a2f93ae99 1524 {
tmulrooney 23:273a2f93ae99 1525 // Clear Irq
tmulrooney 23:273a2f93ae99 1526 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
tmulrooney 23:273a2f93ae99 1527 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
tmulrooney 23:273a2f93ae99 1528 {
tmulrooney 23:273a2f93ae99 1529 this->RadioEvents->CadDone( true );
tmulrooney 23:273a2f93ae99 1530 }
tmulrooney 23:273a2f93ae99 1531 }
tmulrooney 23:273a2f93ae99 1532 else
tmulrooney 23:273a2f93ae99 1533 {
tmulrooney 23:273a2f93ae99 1534 // Clear Irq
tmulrooney 23:273a2f93ae99 1535 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
tmulrooney 23:273a2f93ae99 1536 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
tmulrooney 23:273a2f93ae99 1537 {
tmulrooney 23:273a2f93ae99 1538 this->RadioEvents->CadDone( false );
tmulrooney 23:273a2f93ae99 1539 }
tmulrooney 23:273a2f93ae99 1540 }
tmulrooney 23:273a2f93ae99 1541 break;
tmulrooney 23:273a2f93ae99 1542 default:
tmulrooney 23:273a2f93ae99 1543 break;
tmulrooney 23:273a2f93ae99 1544 }
tmulrooney 23:273a2f93ae99 1545 }
tmulrooney 23:273a2f93ae99 1546
tmulrooney 23:273a2f93ae99 1547 void SX1272::OnDio4Irq( void )
tmulrooney 23:273a2f93ae99 1548 {
tmulrooney 23:273a2f93ae99 1549 debug("OnDio4Irq\r\n");
tmulrooney 23:273a2f93ae99 1550 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 1551 {
tmulrooney 23:273a2f93ae99 1552 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1553 {
tmulrooney 23:273a2f93ae99 1554 if( this->settings.FskPacketHandler.PreambleDetected == false )
tmulrooney 23:273a2f93ae99 1555 {
tmulrooney 23:273a2f93ae99 1556 this->settings.FskPacketHandler.PreambleDetected = true;
tmulrooney 23:273a2f93ae99 1557 }
tmulrooney 23:273a2f93ae99 1558 }
tmulrooney 23:273a2f93ae99 1559 break;
tmulrooney 23:273a2f93ae99 1560 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1561 break;
tmulrooney 23:273a2f93ae99 1562 default:
tmulrooney 23:273a2f93ae99 1563 break;
tmulrooney 23:273a2f93ae99 1564 }
tmulrooney 23:273a2f93ae99 1565 }
tmulrooney 23:273a2f93ae99 1566
tmulrooney 23:273a2f93ae99 1567 void SX1272::OnDio5Irq( void )
tmulrooney 23:273a2f93ae99 1568 {
tmulrooney 23:273a2f93ae99 1569 debug("OnDio5Irq\r\n");
tmulrooney 23:273a2f93ae99 1570 switch( this->settings.Modem )
tmulrooney 23:273a2f93ae99 1571 {
tmulrooney 23:273a2f93ae99 1572 case MODEM_FSK:
tmulrooney 23:273a2f93ae99 1573 break;
tmulrooney 23:273a2f93ae99 1574 case MODEM_LORA:
tmulrooney 23:273a2f93ae99 1575 break;
tmulrooney 23:273a2f93ae99 1576 default:
tmulrooney 23:273a2f93ae99 1577 break;
tmulrooney 23:273a2f93ae99 1578 }
tmulrooney 23:273a2f93ae99 1579 }