Junichi Katsu / Mbed 2 deprecated WallbotR4

Test Ver

Dependencies:   mbed FatFileSystem

PowerControl/EthernetPowerControl.cpp@0:269589d8d2c2, 2012-11-17 (annotated)

Committer:
jksoft
Date:
Sat Nov 17 13:22:00 2012 +0000
Revision:
0:269589d8d2c2
Test Program

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jksoft 0:269589d8d2c2 1 #include "EthernetPowerControl.h"
jksoft 0:269589d8d2c2 2
jksoft 0:269589d8d2c2 3 static void write_PHY (unsigned int PhyReg, unsigned short Value) {
jksoft 0:269589d8d2c2 4 /* Write a data 'Value' to PHY register 'PhyReg'. */
jksoft 0:269589d8d2c2 5 unsigned int tout;
jksoft 0:269589d8d2c2 6 /* Hardware MII Management for LPC176x devices. */
jksoft 0:269589d8d2c2 7 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
jksoft 0:269589d8d2c2 8 LPC_EMAC->MWTD = Value;
jksoft 0:269589d8d2c2 9
jksoft 0:269589d8d2c2 10 /* Wait utill operation completed */
jksoft 0:269589d8d2c2 11 for (tout = 0; tout < MII_WR_TOUT; tout++) {
jksoft 0:269589d8d2c2 12 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
jksoft 0:269589d8d2c2 13 break;
jksoft 0:269589d8d2c2 14 }
jksoft 0:269589d8d2c2 15 }
jksoft 0:269589d8d2c2 16 }
jksoft 0:269589d8d2c2 17
jksoft 0:269589d8d2c2 18 static unsigned short read_PHY (unsigned int PhyReg) {
jksoft 0:269589d8d2c2 19 /* Read a PHY register 'PhyReg'. */
jksoft 0:269589d8d2c2 20 unsigned int tout, val;
jksoft 0:269589d8d2c2 21
jksoft 0:269589d8d2c2 22 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
jksoft 0:269589d8d2c2 23 LPC_EMAC->MCMD = MCMD_READ;
jksoft 0:269589d8d2c2 24
jksoft 0:269589d8d2c2 25 /* Wait until operation completed */
jksoft 0:269589d8d2c2 26 for (tout = 0; tout < MII_RD_TOUT; tout++) {
jksoft 0:269589d8d2c2 27 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
jksoft 0:269589d8d2c2 28 break;
jksoft 0:269589d8d2c2 29 }
jksoft 0:269589d8d2c2 30 }
jksoft 0:269589d8d2c2 31 LPC_EMAC->MCMD = 0;
jksoft 0:269589d8d2c2 32 val = LPC_EMAC->MRDD;
jksoft 0:269589d8d2c2 33
jksoft 0:269589d8d2c2 34 return (val);
jksoft 0:269589d8d2c2 35 }
jksoft 0:269589d8d2c2 36
jksoft 0:269589d8d2c2 37 void EMAC_Init()
jksoft 0:269589d8d2c2 38 {
jksoft 0:269589d8d2c2 39 unsigned int tout,regv;
jksoft 0:269589d8d2c2 40 /* Power Up the EMAC controller. */
jksoft 0:269589d8d2c2 41 Peripheral_PowerUp(LPC1768_PCONP_PCENET);
jksoft 0:269589d8d2c2 42
jksoft 0:269589d8d2c2 43 LPC_PINCON->PINSEL2 = 0x50150105;
jksoft 0:269589d8d2c2 44 LPC_PINCON->PINSEL3 &= ~0x0000000F;
jksoft 0:269589d8d2c2 45 LPC_PINCON->PINSEL3 |= 0x00000005;
jksoft 0:269589d8d2c2 46
jksoft 0:269589d8d2c2 47 /* Reset all EMAC internal modules. */
jksoft 0:269589d8d2c2 48 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
jksoft 0:269589d8d2c2 49 MAC1_SIM_RES | MAC1_SOFT_RES;
jksoft 0:269589d8d2c2 50 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
jksoft 0:269589d8d2c2 51
jksoft 0:269589d8d2c2 52 /* A short delay after reset. */
jksoft 0:269589d8d2c2 53 for (tout = 100; tout; tout--);
jksoft 0:269589d8d2c2 54
jksoft 0:269589d8d2c2 55 /* Initialize MAC control registers. */
jksoft 0:269589d8d2c2 56 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
jksoft 0:269589d8d2c2 57 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
jksoft 0:269589d8d2c2 58 LPC_EMAC->MAXF = ETH_MAX_FLEN;
jksoft 0:269589d8d2c2 59 LPC_EMAC->CLRT = CLRT_DEF;
jksoft 0:269589d8d2c2 60 LPC_EMAC->IPGR = IPGR_DEF;
jksoft 0:269589d8d2c2 61
jksoft 0:269589d8d2c2 62 /* Enable Reduced MII interface. */
jksoft 0:269589d8d2c2 63 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
jksoft 0:269589d8d2c2 64
jksoft 0:269589d8d2c2 65 /* Reset Reduced MII Logic. */
jksoft 0:269589d8d2c2 66 LPC_EMAC->SUPP = SUPP_RES_RMII;
jksoft 0:269589d8d2c2 67 for (tout = 100; tout; tout--);
jksoft 0:269589d8d2c2 68 LPC_EMAC->SUPP = 0;
jksoft 0:269589d8d2c2 69
jksoft 0:269589d8d2c2 70 /* Put the DP83848C in reset mode */
jksoft 0:269589d8d2c2 71 write_PHY (PHY_REG_BMCR, 0x8000);
jksoft 0:269589d8d2c2 72
jksoft 0:269589d8d2c2 73 /* Wait for hardware reset to end. */
jksoft 0:269589d8d2c2 74 for (tout = 0; tout < 0x100000; tout++) {
jksoft 0:269589d8d2c2 75 regv = read_PHY (PHY_REG_BMCR);
jksoft 0:269589d8d2c2 76 if (!(regv & 0x8000)) {
jksoft 0:269589d8d2c2 77 /* Reset complete */
jksoft 0:269589d8d2c2 78 break;
jksoft 0:269589d8d2c2 79 }
jksoft 0:269589d8d2c2 80 }
jksoft 0:269589d8d2c2 81 }
jksoft 0:269589d8d2c2 82
jksoft 0:269589d8d2c2 83
jksoft 0:269589d8d2c2 84 void PHY_PowerDown()
jksoft 0:269589d8d2c2 85 {
jksoft 0:269589d8d2c2 86 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
jksoft 0:269589d8d2c2 87 EMAC_Init(); //init EMAC if it is not already init'd
jksoft 0:269589d8d2c2 88
jksoft 0:269589d8d2c2 89 unsigned int regv;
jksoft 0:269589d8d2c2 90 regv = read_PHY(PHY_REG_BMCR);
jksoft 0:269589d8d2c2 91 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
jksoft 0:269589d8d2c2 92 regv = read_PHY(PHY_REG_BMCR);
jksoft 0:269589d8d2c2 93
jksoft 0:269589d8d2c2 94 //shouldn't need the EMAC now.
jksoft 0:269589d8d2c2 95 Peripheral_PowerDown(LPC1768_PCONP_PCENET);
jksoft 0:269589d8d2c2 96
jksoft 0:269589d8d2c2 97 //and turn off the PHY OSC
jksoft 0:269589d8d2c2 98 LPC_GPIO1->FIODIR |= 0x8000000;
jksoft 0:269589d8d2c2 99 LPC_GPIO1->FIOCLR = 0x8000000;
jksoft 0:269589d8d2c2 100 }
jksoft 0:269589d8d2c2 101
jksoft 0:269589d8d2c2 102 void PHY_PowerUp()
jksoft 0:269589d8d2c2 103 {
jksoft 0:269589d8d2c2 104 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
jksoft 0:269589d8d2c2 105 EMAC_Init(); //init EMAC if it is not already init'd
jksoft 0:269589d8d2c2 106
jksoft 0:269589d8d2c2 107 LPC_GPIO1->FIODIR |= 0x8000000;
jksoft 0:269589d8d2c2 108 LPC_GPIO1->FIOSET = 0x8000000;
jksoft 0:269589d8d2c2 109
jksoft 0:269589d8d2c2 110 //wait for osc to be stable
jksoft 0:269589d8d2c2 111 wait_ms(200);
jksoft 0:269589d8d2c2 112
jksoft 0:269589d8d2c2 113 unsigned int regv;
jksoft 0:269589d8d2c2 114 regv = read_PHY(PHY_REG_BMCR);
jksoft 0:269589d8d2c2 115 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
jksoft 0:269589d8d2c2 116 regv = read_PHY(PHY_REG_BMCR);
jksoft 0:269589d8d2c2 117 }
jksoft 0:269589d8d2c2 118
jksoft 0:269589d8d2c2 119 void PHY_EnergyDetect_Enable()
jksoft 0:269589d8d2c2 120 {
jksoft 0:269589d8d2c2 121 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
jksoft 0:269589d8d2c2 122 EMAC_Init(); //init EMAC if it is not already init'd
jksoft 0:269589d8d2c2 123
jksoft 0:269589d8d2c2 124 unsigned int regv;
jksoft 0:269589d8d2c2 125 regv = read_PHY(PHY_REG_EDCR);
jksoft 0:269589d8d2c2 126 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
jksoft 0:269589d8d2c2 127 regv = read_PHY(PHY_REG_EDCR);
jksoft 0:269589d8d2c2 128 }
jksoft 0:269589d8d2c2 129
jksoft 0:269589d8d2c2 130 void PHY_EnergyDetect_Disable()
jksoft 0:269589d8d2c2 131 {
jksoft 0:269589d8d2c2 132 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
jksoft 0:269589d8d2c2 133 EMAC_Init(); //init EMAC if it is not already init'd
jksoft 0:269589d8d2c2 134 unsigned int regv;
jksoft 0:269589d8d2c2 135 regv = read_PHY(PHY_REG_EDCR);
jksoft 0:269589d8d2c2 136 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
jksoft 0:269589d8d2c2 137 regv = read_PHY(PHY_REG_EDCR);
jksoft 0:269589d8d2c2 138 }