EthernetPowerControl.h

00001 /* mbed PowerControl Library
00002   * Copyright (c) 2010 Michael Wei
00003   */ 
00004   
00005 #ifndef MBED_POWERCONTROL_ETH_H 
00006 #define MBED_POWERCONTROL_ETH_H 
00007 
00008 #include "mbed.h"
00009 #include "PowerControl.h"
00010 
00011 #define PHY_REG_BMCR_POWERDOWN    0xB
00012 #define PHY_REG_EDCR_ENABLE       0xF
00013 
00014 
00015 void EMAC_Init();
00016 static unsigned short read_PHY (unsigned int PhyReg);
00017 static void write_PHY (unsigned int PhyReg, unsigned short Value);
00018 
00019 void PHY_PowerDown(void);
00020 void PHY_PowerUp(void);
00021 void PHY_EnergyDetect_Enable(void);
00022 void PHY_EnergyDetect_Disable(void);
00023 
00024 //From NXP Sample Code .... Probably from KEIL sample code
00025 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
00026 #define NUM_RX_FRAG         4           /* Num.of RX Fragments 4*1536= 6.0kB */
00027 #define NUM_TX_FRAG         3           /* Num.of TX Fragments 3*1536= 4.6kB */
00028 #define ETH_FRAG_SIZE       1536        /* Packet Fragment size 1536 Bytes   */
00029 
00030 #define ETH_MAX_FLEN        1536        /* Max. Ethernet Frame Size          */
00031 
00032 /* EMAC variables located in 16K Ethernet SRAM */
00033 #define RX_DESC_BASE        0x20080000
00034 #define RX_STAT_BASE        (RX_DESC_BASE + NUM_RX_FRAG*8)
00035 #define TX_DESC_BASE        (RX_STAT_BASE + NUM_RX_FRAG*8)
00036 #define TX_STAT_BASE        (TX_DESC_BASE + NUM_TX_FRAG*8)
00037 #define RX_BUF_BASE         (TX_STAT_BASE + NUM_TX_FRAG*4)
00038 #define TX_BUF_BASE         (RX_BUF_BASE  + NUM_RX_FRAG*ETH_FRAG_SIZE)
00039 
00040 /* RX and TX descriptor and status definitions. */
00041 #define RX_DESC_PACKET(i)   (*(unsigned int *)(RX_DESC_BASE   + 8*i))
00042 #define RX_DESC_CTRL(i)     (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))
00043 #define RX_STAT_INFO(i)     (*(unsigned int *)(RX_STAT_BASE   + 8*i))
00044 #define RX_STAT_HASHCRC(i)  (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))
00045 #define TX_DESC_PACKET(i)   (*(unsigned int *)(TX_DESC_BASE   + 8*i))
00046 #define TX_DESC_CTRL(i)     (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))
00047 #define TX_STAT_INFO(i)     (*(unsigned int *)(TX_STAT_BASE   + 4*i))
00048 #define RX_BUF(i)           (RX_BUF_BASE + ETH_FRAG_SIZE*i)
00049 #define TX_BUF(i)           (TX_BUF_BASE + ETH_FRAG_SIZE*i)
00050 
00051 /* MAC Configuration Register 1 */
00052 #define MAC1_REC_EN         0x00000001  /* Receive Enable                    */
00053 #define MAC1_PASS_ALL       0x00000002  /* Pass All Receive Frames           */
00054 #define MAC1_RX_FLOWC       0x00000004  /* RX Flow Control                   */
00055 #define MAC1_TX_FLOWC       0x00000008  /* TX Flow Control                   */
00056 #define MAC1_LOOPB          0x00000010  /* Loop Back Mode                    */
00057 #define MAC1_RES_TX         0x00000100  /* Reset TX Logic                    */
00058 #define MAC1_RES_MCS_TX     0x00000200  /* Reset MAC TX Control Sublayer     */
00059 #define MAC1_RES_RX         0x00000400  /* Reset RX Logic                    */
00060 #define MAC1_RES_MCS_RX     0x00000800  /* Reset MAC RX Control Sublayer     */
00061 #define MAC1_SIM_RES        0x00004000  /* Simulation Reset                  */
00062 #define MAC1_SOFT_RES       0x00008000  /* Soft Reset MAC                    */
00063 
00064 /* MAC Configuration Register 2 */
00065 #define MAC2_FULL_DUP       0x00000001  /* Full Duplex Mode                  */
00066 #define MAC2_FRM_LEN_CHK    0x00000002  /* Frame Length Checking             */
00067 #define MAC2_HUGE_FRM_EN    0x00000004  /* Huge Frame Enable                 */
00068 #define MAC2_DLY_CRC        0x00000008  /* Delayed CRC Mode                  */
00069 #define MAC2_CRC_EN         0x00000010  /* Append CRC to every Frame         */
00070 #define MAC2_PAD_EN         0x00000020  /* Pad all Short Frames              */
00071 #define MAC2_VLAN_PAD_EN    0x00000040  /* VLAN Pad Enable                   */
00072 #define MAC2_ADET_PAD_EN    0x00000080  /* Auto Detect Pad Enable            */
00073 #define MAC2_PPREAM_ENF     0x00000100  /* Pure Preamble Enforcement         */
00074 #define MAC2_LPREAM_ENF     0x00000200  /* Long Preamble Enforcement         */
00075 #define MAC2_NO_BACKOFF     0x00001000  /* No Backoff Algorithm              */
00076 #define MAC2_BACK_PRESSURE  0x00002000  /* Backoff Presurre / No Backoff     */
00077 #define MAC2_EXCESS_DEF     0x00004000  /* Excess Defer                      */
00078 
00079 /* Back-to-Back Inter-Packet-Gap Register */
00080 #define IPGT_FULL_DUP       0x00000015  /* Recommended value for Full Duplex */
00081 #define IPGT_HALF_DUP       0x00000012  /* Recommended value for Half Duplex */
00082 
00083 /* Non Back-to-Back Inter-Packet-Gap Register */
00084 #define IPGR_DEF            0x00000012  /* Recommended value                 */
00085 
00086 /* Collision Window/Retry Register */
00087 #define CLRT_DEF            0x0000370F  /* Default value                     */
00088 
00089 /* PHY Support Register */
00090 #define SUPP_SPEED          0x00000100  /* Reduced MII Logic Current Speed   */
00091 #define SUPP_RES_RMII       0x00000800  /* Reset Reduced MII Logic           */
00092 
00093 /* Test Register */
00094 #define TEST_SHCUT_PQUANTA  0x00000001  /* Shortcut Pause Quanta             */
00095 #define TEST_TST_PAUSE      0x00000002  /* Test Pause                        */
00096 #define TEST_TST_BACKP      0x00000004  /* Test Back Pressure                */
00097 
00098 /* MII Management Configuration Register */
00099 #define MCFG_SCAN_INC       0x00000001  /* Scan Increment PHY Address        */
00100 #define MCFG_SUPP_PREAM     0x00000002  /* Suppress Preamble                 */
00101 #define MCFG_CLK_SEL        0x0000001C  /* Clock Select Mask                 */
00102 #define MCFG_RES_MII        0x00008000  /* Reset MII Management Hardware     */
00103 
00104 /* MII Management Command Register */
00105 #define MCMD_READ           0x00000001  /* MII Read                          */
00106 #define MCMD_SCAN           0x00000002  /* MII Scan continuously             */
00107 
00108 #define MII_WR_TOUT         0x00050000  /* MII Write timeout count           */
00109 #define MII_RD_TOUT         0x00050000  /* MII Read timeout count            */
00110 
00111 /* MII Management Address Register */
00112 #define MADR_REG_ADR        0x0000001F  /* MII Register Address Mask         */
00113 #define MADR_PHY_ADR        0x00001F00  /* PHY Address Mask                  */
00114 
00115 /* MII Management Indicators Register */
00116 #define MIND_BUSY           0x00000001  /* MII is Busy                       */
00117 #define MIND_SCAN           0x00000002  /* MII Scanning in Progress          */
00118 #define MIND_NOT_VAL        0x00000004  /* MII Read Data not valid           */
00119 #define MIND_MII_LINK_FAIL  0x00000008  /* MII Link Failed                   */
00120 
00121 /* Command Register */
00122 #define CR_RX_EN            0x00000001  /* Enable Receive                    */
00123 #define CR_TX_EN            0x00000002  /* Enable Transmit                   */
00124 #define CR_REG_RES          0x00000008  /* Reset Host Registers              */
00125 #define CR_TX_RES           0x00000010  /* Reset Transmit Datapath           */
00126 #define CR_RX_RES           0x00000020  /* Reset Receive Datapath            */
00127 #define CR_PASS_RUNT_FRM    0x00000040  /* Pass Runt Frames                  */
00128 #define CR_PASS_RX_FILT     0x00000080  /* Pass RX Filter                    */
00129 #define CR_TX_FLOW_CTRL     0x00000100  /* TX Flow Control                   */
00130 #define CR_RMII             0x00000200  /* Reduced MII Interface             */
00131 #define CR_FULL_DUP         0x00000400  /* Full Duplex                       */
00132 
00133 /* Status Register */
00134 #define SR_RX_EN            0x00000001  /* Enable Receive                    */
00135 #define SR_TX_EN            0x00000002  /* Enable Transmit                   */
00136 
00137 /* Transmit Status Vector 0 Register */
00138 #define TSV0_CRC_ERR        0x00000001  /* CRC error                         */
00139 #define TSV0_LEN_CHKERR     0x00000002  /* Length Check Error                */
00140 #define TSV0_LEN_OUTRNG     0x00000004  /* Length Out of Range               */
00141 #define TSV0_DONE           0x00000008  /* Tramsmission Completed            */
00142 #define TSV0_MCAST          0x00000010  /* Multicast Destination             */
00143 #define TSV0_BCAST          0x00000020  /* Broadcast Destination             */
00144 #define TSV0_PKT_DEFER      0x00000040  /* Packet Deferred                   */
00145 #define TSV0_EXC_DEFER      0x00000080  /* Excessive Packet Deferral         */
00146 #define TSV0_EXC_COLL       0x00000100  /* Excessive Collision               */
00147 #define TSV0_LATE_COLL      0x00000200  /* Late Collision Occured            */
00148 #define TSV0_GIANT          0x00000400  /* Giant Frame                       */
00149 #define TSV0_UNDERRUN       0x00000800  /* Buffer Underrun                   */
00150 #define TSV0_BYTES          0x0FFFF000  /* Total Bytes Transferred           */
00151 #define TSV0_CTRL_FRAME     0x10000000  /* Control Frame                     */
00152 #define TSV0_PAUSE          0x20000000  /* Pause Frame                       */
00153 #define TSV0_BACK_PRESS     0x40000000  /* Backpressure Method Applied       */
00154 #define TSV0_VLAN           0x80000000  /* VLAN Frame                        */
00155 
00156 /* Transmit Status Vector 1 Register */
00157 #define TSV1_BYTE_CNT       0x0000FFFF  /* Transmit Byte Count               */
00158 #define TSV1_COLL_CNT       0x000F0000  /* Transmit Collision Count          */
00159 
00160 /* Receive Status Vector Register */
00161 #define RSV_BYTE_CNT        0x0000FFFF  /* Receive Byte Count                */
00162 #define RSV_PKT_IGNORED     0x00010000  /* Packet Previously Ignored         */
00163 #define RSV_RXDV_SEEN       0x00020000  /* RXDV Event Previously Seen        */
00164 #define RSV_CARR_SEEN       0x00040000  /* Carrier Event Previously Seen     */
00165 #define RSV_REC_CODEV       0x00080000  /* Receive Code Violation            */
00166 #define RSV_CRC_ERR         0x00100000  /* CRC Error                         */
00167 #define RSV_LEN_CHKERR      0x00200000  /* Length Check Error                */
00168 #define RSV_LEN_OUTRNG      0x00400000  /* Length Out of Range               */
00169 #define RSV_REC_OK          0x00800000  /* Frame Received OK                 */
00170 #define RSV_MCAST           0x01000000  /* Multicast Frame                   */
00171 #define RSV_BCAST           0x02000000  /* Broadcast Frame                   */
00172 #define RSV_DRIB_NIBB       0x04000000  /* Dribble Nibble                    */
00173 #define RSV_CTRL_FRAME      0x08000000  /* Control Frame                     */
00174 #define RSV_PAUSE           0x10000000  /* Pause Frame                       */
00175 #define RSV_UNSUPP_OPC      0x20000000  /* Unsupported Opcode                */
00176 #define RSV_VLAN            0x40000000  /* VLAN Frame                        */
00177 
00178 /* Flow Control Counter Register */
00179 #define FCC_MIRR_CNT        0x0000FFFF  /* Mirror Counter                    */
00180 #define FCC_PAUSE_TIM       0xFFFF0000  /* Pause Timer                       */
00181 
00182 /* Flow Control Status Register */
00183 #define FCS_MIRR_CNT        0x0000FFFF  /* Mirror Counter Current            */
00184 
00185 /* Receive Filter Control Register */
00186 #define RFC_UCAST_EN        0x00000001  /* Accept Unicast Frames Enable      */
00187 #define RFC_BCAST_EN        0x00000002  /* Accept Broadcast Frames Enable    */
00188 #define RFC_MCAST_EN        0x00000004  /* Accept Multicast Frames Enable    */
00189 #define RFC_UCAST_HASH_EN   0x00000008  /* Accept Unicast Hash Filter Frames */
00190 #define RFC_MCAST_HASH_EN   0x00000010  /* Accept Multicast Hash Filter Fram.*/
00191 #define RFC_PERFECT_EN      0x00000020  /* Accept Perfect Match Enable       */
00192 #define RFC_MAGP_WOL_EN     0x00001000  /* Magic Packet Filter WoL Enable    */
00193 #define RFC_PFILT_WOL_EN    0x00002000  /* Perfect Filter WoL Enable         */
00194 
00195 /* Receive Filter WoL Status/Clear Registers */
00196 #define WOL_UCAST           0x00000001  /* Unicast Frame caused WoL          */
00197 #define WOL_BCAST           0x00000002  /* Broadcast Frame caused WoL        */
00198 #define WOL_MCAST           0x00000004  /* Multicast Frame caused WoL        */
00199 #define WOL_UCAST_HASH      0x00000008  /* Unicast Hash Filter Frame WoL     */
00200 #define WOL_MCAST_HASH      0x00000010  /* Multicast Hash Filter Frame WoL   */
00201 #define WOL_PERFECT         0x00000020  /* Perfect Filter WoL                */
00202 #define WOL_RX_FILTER       0x00000080  /* RX Filter caused WoL              */
00203 #define WOL_MAG_PACKET      0x00000100  /* Magic Packet Filter caused WoL    */
00204 
00205 /* Interrupt Status/Enable/Clear/Set Registers */
00206 #define INT_RX_OVERRUN      0x00000001  /* Overrun Error in RX Queue         */
00207 #define INT_RX_ERR          0x00000002  /* Receive Error                     */
00208 #define INT_RX_FIN          0x00000004  /* RX Finished Process Descriptors   */
00209 #define INT_RX_DONE         0x00000008  /* Receive Done                      */
00210 #define INT_TX_UNDERRUN     0x00000010  /* Transmit Underrun                 */
00211 #define INT_TX_ERR          0x00000020  /* Transmit Error                    */
00212 #define INT_TX_FIN          0x00000040  /* TX Finished Process Descriptors   */
00213 #define INT_TX_DONE         0x00000080  /* Transmit Done                     */
00214 #define INT_SOFT_INT        0x00001000  /* Software Triggered Interrupt      */
00215 #define INT_WAKEUP          0x00002000  /* Wakeup Event Interrupt            */
00216 
00217 /* Power Down Register */
00218 #define PD_POWER_DOWN       0x80000000  /* Power Down MAC                    */
00219 
00220 /* RX Descriptor Control Word */
00221 #define RCTRL_SIZE          0x000007FF  /* Buffer size mask                  */
00222 #define RCTRL_INT           0x80000000  /* Generate RxDone Interrupt         */
00223 
00224 /* RX Status Hash CRC Word */
00225 #define RHASH_SA            0x000001FF  /* Hash CRC for Source Address       */
00226 #define RHASH_DA            0x001FF000  /* Hash CRC for Destination Address  */
00227 
00228 /* RX Status Information Word */
00229 #define RINFO_SIZE          0x000007FF  /* Data size in bytes                */
00230 #define RINFO_CTRL_FRAME    0x00040000  /* Control Frame                     */
00231 #define RINFO_VLAN          0x00080000  /* VLAN Frame                        */
00232 #define RINFO_FAIL_FILT     0x00100000  /* RX Filter Failed                  */
00233 #define RINFO_MCAST         0x00200000  /* Multicast Frame                   */
00234 #define RINFO_BCAST         0x00400000  /* Broadcast Frame                   */
00235 #define RINFO_CRC_ERR       0x00800000  /* CRC Error in Frame                */
00236 #define RINFO_SYM_ERR       0x01000000  /* Symbol Error from PHY             */
00237 #define RINFO_LEN_ERR       0x02000000  /* Length Error                      */
00238 #define RINFO_RANGE_ERR     0x04000000  /* Range Error (exceeded max. size)  */
00239 #define RINFO_ALIGN_ERR     0x08000000  /* Alignment Error                   */
00240 #define RINFO_OVERRUN       0x10000000  /* Receive overrun                   */
00241 #define RINFO_NO_DESCR      0x20000000  /* No new Descriptor available       */
00242 #define RINFO_LAST_FLAG     0x40000000  /* Last Fragment in Frame            */
00243 #define RINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
00244 
00245 #define RINFO_ERR_MASK     (RINFO_FAIL_FILT | RINFO_CRC_ERR   | RINFO_SYM_ERR | \
00246                             RINFO_LEN_ERR   | RINFO_ALIGN_ERR | RINFO_OVERRUN)
00247 
00248 /* TX Descriptor Control Word */
00249 #define TCTRL_SIZE          0x000007FF  /* Size of data buffer in bytes      */
00250 #define TCTRL_OVERRIDE      0x04000000  /* Override Default MAC Registers    */
00251 #define TCTRL_HUGE          0x08000000  /* Enable Huge Frame                 */
00252 #define TCTRL_PAD           0x10000000  /* Pad short Frames to 64 bytes      */
00253 #define TCTRL_CRC           0x20000000  /* Append a hardware CRC to Frame    */
00254 #define TCTRL_LAST          0x40000000  /* Last Descriptor for TX Frame      */
00255 #define TCTRL_INT           0x80000000  /* Generate TxDone Interrupt         */
00256 
00257 /* TX Status Information Word */
00258 #define TINFO_COL_CNT       0x01E00000  /* Collision Count                   */
00259 #define TINFO_DEFER         0x02000000  /* Packet Deferred (not an error)    */
00260 #define TINFO_EXCESS_DEF    0x04000000  /* Excessive Deferral                */
00261 #define TINFO_EXCESS_COL    0x08000000  /* Excessive Collision               */
00262 #define TINFO_LATE_COL      0x10000000  /* Late Collision Occured            */
00263 #define TINFO_UNDERRUN      0x20000000  /* Transmit Underrun                 */
00264 #define TINFO_NO_DESCR      0x40000000  /* No new Descriptor available       */
00265 #define TINFO_ERR           0x80000000  /* Error Occured (OR of all errors)  */
00266 
00267 /* DP83848C PHY Registers */
00268 #define PHY_REG_BMCR        0x00        /* Basic Mode Control Register       */
00269 #define PHY_REG_BMSR        0x01        /* Basic Mode Status Register        */
00270 #define PHY_REG_IDR1        0x02        /* PHY Identifier 1                  */
00271 #define PHY_REG_IDR2        0x03        /* PHY Identifier 2                  */
00272 #define PHY_REG_ANAR        0x04        /* Auto-Negotiation Advertisement    */
00273 #define PHY_REG_ANLPAR      0x05        /* Auto-Neg. Link Partner Abitily    */
00274 #define PHY_REG_ANER        0x06        /* Auto-Neg. Expansion Register      */
00275 #define PHY_REG_ANNPTR      0x07        /* Auto-Neg. Next Page TX            */
00276 
00277 /* PHY Extended Registers */
00278 #define PHY_REG_STS         0x10        /* Status Register                   */
00279 #define PHY_REG_MICR        0x11        /* MII Interrupt Control Register    */
00280 #define PHY_REG_MISR        0x12        /* MII Interrupt Status Register     */
00281 #define PHY_REG_FCSCR       0x14        /* False Carrier Sense Counter       */
00282 #define PHY_REG_RECR        0x15        /* Receive Error Counter             */
00283 #define PHY_REG_PCSR        0x16        /* PCS Sublayer Config. and Status   */
00284 #define PHY_REG_RBR         0x17        /* RMII and Bypass Register          */
00285 #define PHY_REG_LEDCR       0x18        /* LED Direct Control Register       */
00286 #define PHY_REG_PHYCR       0x19        /* PHY Control Register              */
00287 #define PHY_REG_10BTSCR     0x1A        /* 10Base-T Status/Control Register  */
00288 #define PHY_REG_CDCTRL1     0x1B        /* CD Test Control and BIST Extens.  */
00289 #define PHY_REG_EDCR        0x1D        /* Energy Detect Control Register    */
00290 
00291 #define PHY_FULLD_100M      0x2100      /* Full Duplex 100Mbit               */
00292 #define PHY_HALFD_100M      0x2000      /* Half Duplex 100Mbit               */
00293 #define PHY_FULLD_10M       0x0100      /* Full Duplex 10Mbit                */
00294 #define PHY_HALFD_10M       0x0000      /* Half Duplex 10MBit                */
00295 #define PHY_AUTO_NEG        0x3000      /* Select Auto Negotiation           */
00296 
00297 #define DP83848C_DEF_ADR    0x0100      /* Default PHY device address        */
00298 #define DP83848C_ID         0x20005C90  /* PHY Identifier                    */
00299 #endif