Moved pl_status to public
Fork of lib_mma8451q by
mma8451q.h@1:778b685c3ad0, 2015-05-08 (annotated)
- Committer:
- dudmuck
- Date:
- Fri May 08 01:31:18 2015 +0000
- Revision:
- 1:778b685c3ad0
- Parent:
- 0:cb0046a629c1
- Child:
- 2:4bc96749141e
added interrupt handling
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
dudmuck | 0:cb0046a629c1 | 1 | #include "mbed.h" |
dudmuck | 0:cb0046a629c1 | 2 | |
dudmuck | 0:cb0046a629c1 | 3 | /* Xtrinsic accelerometer */ |
dudmuck | 0:cb0046a629c1 | 4 | |
dudmuck | 0:cb0046a629c1 | 5 | /* |
dudmuck | 0:cb0046a629c1 | 6 | * MMA8451 Registers |
dudmuck | 0:cb0046a629c1 | 7 | */ |
dudmuck | 0:cb0046a629c1 | 8 | #define MMA8451_STATUS 0x00 |
dudmuck | 0:cb0046a629c1 | 9 | #define MMA8451_OUT_X_MSB 0x01 |
dudmuck | 0:cb0046a629c1 | 10 | #define MMA8451_SYSMOD 0x0b // |
dudmuck | 0:cb0046a629c1 | 11 | #define MMA8451_INT_SOURCE 0x0c // |
dudmuck | 0:cb0046a629c1 | 12 | #define MMA8451_ID 0x0d |
dudmuck | 1:778b685c3ad0 | 13 | #define MMA8451_PL_STATUS 0x10 |
dudmuck | 1:778b685c3ad0 | 14 | #define MMA8451_FF_MT_SRC 0x16 |
dudmuck | 0:cb0046a629c1 | 15 | #define MMA8451_TRANSIENT_CFG 0x1d // transient enable |
dudmuck | 0:cb0046a629c1 | 16 | #define MMA8451_TRANSIENT_SRC 0x1e // transient read/clear interrupt |
dudmuck | 0:cb0046a629c1 | 17 | #define MMA8451_TRANSIENT_THS 0x1f // transient threshold |
dudmuck | 0:cb0046a629c1 | 18 | #define MMA8451_TRANSIENT_COUNT 0x20 // transient debounce |
dudmuck | 1:778b685c3ad0 | 19 | #define MMA8451_PULSE_SRC 0x22 |
dudmuck | 0:cb0046a629c1 | 20 | #define MMA8451_CTRL_REG1 0x2a |
dudmuck | 0:cb0046a629c1 | 21 | #define MMA8451_CTRL_REG2 0x2b |
dudmuck | 1:778b685c3ad0 | 22 | #define MMA8451_CTRL_REG3 0x2c // interrupt control |
dudmuck | 0:cb0046a629c1 | 23 | #define MMA8451_CTRL_REG4 0x2d // interrupt enable |
dudmuck | 0:cb0046a629c1 | 24 | #define MMA8451_CTRL_REG5 0x2e // interrupt pin selection |
dudmuck | 0:cb0046a629c1 | 25 | |
dudmuck | 0:cb0046a629c1 | 26 | typedef union { |
dudmuck | 0:cb0046a629c1 | 27 | struct { |
dudmuck | 0:cb0046a629c1 | 28 | int16_t x; |
dudmuck | 0:cb0046a629c1 | 29 | int16_t y; |
dudmuck | 0:cb0046a629c1 | 30 | int16_t z; |
dudmuck | 0:cb0046a629c1 | 31 | } v; |
dudmuck | 0:cb0046a629c1 | 32 | uint8_t octets[6]; |
dudmuck | 0:cb0046a629c1 | 33 | } mma_out_t; |
dudmuck | 0:cb0046a629c1 | 34 | |
dudmuck | 0:cb0046a629c1 | 35 | typedef union { |
dudmuck | 0:cb0046a629c1 | 36 | struct { // at 0x0c |
dudmuck | 0:cb0046a629c1 | 37 | uint8_t SRC_DRDY : 1; // 0 |
dudmuck | 0:cb0046a629c1 | 38 | uint8_t reserved1 : 1; // 1 |
dudmuck | 0:cb0046a629c1 | 39 | uint8_t SRC_FF_MT : 1; // 2 |
dudmuck | 0:cb0046a629c1 | 40 | uint8_t SRC_PULSE : 1; // 3 |
dudmuck | 0:cb0046a629c1 | 41 | uint8_t SRC_LNDPRT : 1; // 4 |
dudmuck | 0:cb0046a629c1 | 42 | uint8_t SRC_TRANS : 1; // 5 |
dudmuck | 0:cb0046a629c1 | 43 | uint8_t reserved6 : 1; // 6 |
dudmuck | 0:cb0046a629c1 | 44 | uint8_t SRC_ASLP : 1; // 7 |
dudmuck | 0:cb0046a629c1 | 45 | } bits; |
dudmuck | 0:cb0046a629c1 | 46 | uint8_t octet; |
dudmuck | 1:778b685c3ad0 | 47 | } mma_int_source_t; |
dudmuck | 0:cb0046a629c1 | 48 | |
dudmuck | 0:cb0046a629c1 | 49 | typedef union { |
dudmuck | 0:cb0046a629c1 | 50 | struct { // at 0x1d |
dudmuck | 0:cb0046a629c1 | 51 | uint8_t HPF_BYP : 1; // 0 |
dudmuck | 0:cb0046a629c1 | 52 | uint8_t XTEFE : 1; // 1 |
dudmuck | 0:cb0046a629c1 | 53 | uint8_t YTEFE : 1; // 2 |
dudmuck | 0:cb0046a629c1 | 54 | uint8_t ZTEFE : 1; // 3 |
dudmuck | 0:cb0046a629c1 | 55 | uint8_t ELE : 1; // 4 |
dudmuck | 0:cb0046a629c1 | 56 | uint8_t pad : 3; // 5,6,7 |
dudmuck | 0:cb0046a629c1 | 57 | } bits; |
dudmuck | 0:cb0046a629c1 | 58 | uint8_t octet; |
dudmuck | 0:cb0046a629c1 | 59 | } transient_cfg_t; |
dudmuck | 0:cb0046a629c1 | 60 | |
dudmuck | 0:cb0046a629c1 | 61 | typedef union { |
dudmuck | 0:cb0046a629c1 | 62 | struct { // at 0x1e |
dudmuck | 0:cb0046a629c1 | 63 | uint8_t X_Trans_Pol : 1; // 0 |
dudmuck | 0:cb0046a629c1 | 64 | uint8_t XTRANSE : 1; // 1 |
dudmuck | 0:cb0046a629c1 | 65 | uint8_t Y_Trans_Pol : 1; // 2 |
dudmuck | 0:cb0046a629c1 | 66 | uint8_t YTRANSE : 1; // 3 |
dudmuck | 0:cb0046a629c1 | 67 | uint8_t Z_Trans_Pol : 1; // 4 |
dudmuck | 0:cb0046a629c1 | 68 | uint8_t ZTRANSE : 1; // 5 |
dudmuck | 0:cb0046a629c1 | 69 | uint8_t EA : 1; // 6 |
dudmuck | 0:cb0046a629c1 | 70 | uint8_t pad : 1; // 7 |
dudmuck | 0:cb0046a629c1 | 71 | } bits; |
dudmuck | 0:cb0046a629c1 | 72 | uint8_t octet; |
dudmuck | 0:cb0046a629c1 | 73 | } transient_src_t; |
dudmuck | 0:cb0046a629c1 | 74 | |
dudmuck | 0:cb0046a629c1 | 75 | typedef union { |
dudmuck | 0:cb0046a629c1 | 76 | struct { // at 0x2a |
dudmuck | 0:cb0046a629c1 | 77 | uint8_t ACTIVE : 1; // 0 |
dudmuck | 0:cb0046a629c1 | 78 | uint8_t F_READ : 1; // 1 |
dudmuck | 0:cb0046a629c1 | 79 | uint8_t LNOISE : 1; // 2 |
dudmuck | 0:cb0046a629c1 | 80 | uint8_t DR : 3; // 3,4,5 |
dudmuck | 0:cb0046a629c1 | 81 | uint8_t ASLP_RATE : 2; // 6,7 |
dudmuck | 0:cb0046a629c1 | 82 | } bits; |
dudmuck | 0:cb0046a629c1 | 83 | uint8_t octet; |
dudmuck | 0:cb0046a629c1 | 84 | } ctrl_reg1_t; |
dudmuck | 0:cb0046a629c1 | 85 | |
dudmuck | 0:cb0046a629c1 | 86 | typedef union { |
dudmuck | 0:cb0046a629c1 | 87 | struct { // at 0x2d |
dudmuck | 0:cb0046a629c1 | 88 | uint8_t INT_EN_DRDY : 1; // 0 |
dudmuck | 0:cb0046a629c1 | 89 | uint8_t reserved1 : 1; // 1 |
dudmuck | 0:cb0046a629c1 | 90 | uint8_t INT_EN_FF_MT : 1; // 2 |
dudmuck | 0:cb0046a629c1 | 91 | uint8_t INT_EN_PULSE : 1; // 3 |
dudmuck | 0:cb0046a629c1 | 92 | uint8_t INT_EN_LNDPRT : 1; // 4 |
dudmuck | 0:cb0046a629c1 | 93 | uint8_t INT_EN_TRANS : 1; // 5 |
dudmuck | 0:cb0046a629c1 | 94 | uint8_t reserved6 : 1; // 6 |
dudmuck | 0:cb0046a629c1 | 95 | uint8_t INT_EN_ASLP : 1; // 7 |
dudmuck | 0:cb0046a629c1 | 96 | } bits; |
dudmuck | 0:cb0046a629c1 | 97 | uint8_t octet; |
dudmuck | 0:cb0046a629c1 | 98 | } ctrl_reg4_t; |
dudmuck | 0:cb0046a629c1 | 99 | |
dudmuck | 0:cb0046a629c1 | 100 | typedef union { |
dudmuck | 0:cb0046a629c1 | 101 | struct { // at 0x2e |
dudmuck | 0:cb0046a629c1 | 102 | uint8_t INT_CFG_DRDY : 1; // 0 |
dudmuck | 0:cb0046a629c1 | 103 | uint8_t reserved1 : 1; // 1 |
dudmuck | 0:cb0046a629c1 | 104 | uint8_t INT_CFG_FF_MT : 1; // 2 |
dudmuck | 0:cb0046a629c1 | 105 | uint8_t INT_CFG_PULSE : 1; // 3 |
dudmuck | 0:cb0046a629c1 | 106 | uint8_t INT_CFG_LNDPRT : 1; // 4 |
dudmuck | 0:cb0046a629c1 | 107 | uint8_t INT_CFG_TRANS : 1; // 5 |
dudmuck | 0:cb0046a629c1 | 108 | uint8_t reserved6 : 1; // 6 |
dudmuck | 0:cb0046a629c1 | 109 | uint8_t INT_CFG_ASLP : 1; // 7 |
dudmuck | 0:cb0046a629c1 | 110 | } bits; |
dudmuck | 0:cb0046a629c1 | 111 | uint8_t octet; |
dudmuck | 0:cb0046a629c1 | 112 | } ctrl_reg5_t; |
dudmuck | 0:cb0046a629c1 | 113 | |
dudmuck | 0:cb0046a629c1 | 114 | class MMA8451Q { |
dudmuck | 0:cb0046a629c1 | 115 | public: |
dudmuck | 1:778b685c3ad0 | 116 | MMA8451Q(I2C& r, DigitalIn& int_pin); |
dudmuck | 0:cb0046a629c1 | 117 | ~MMA8451Q(); |
dudmuck | 0:cb0046a629c1 | 118 | void print_regs(void); |
dudmuck | 0:cb0046a629c1 | 119 | void set_active(char); |
dudmuck | 1:778b685c3ad0 | 120 | bool get_active(void); |
dudmuck | 0:cb0046a629c1 | 121 | |
dudmuck | 0:cb0046a629c1 | 122 | uint8_t read_single(uint8_t addr); |
dudmuck | 0:cb0046a629c1 | 123 | void read(uint8_t addr, uint8_t *dst_buf, int length); |
dudmuck | 0:cb0046a629c1 | 124 | void write(uint8_t addr, uint8_t data); |
dudmuck | 0:cb0046a629c1 | 125 | void transient_detect(void); |
dudmuck | 1:778b685c3ad0 | 126 | void service(void); |
dudmuck | 0:cb0046a629c1 | 127 | |
dudmuck | 0:cb0046a629c1 | 128 | mma_out_t out; |
dudmuck | 0:cb0046a629c1 | 129 | transient_cfg_t transient_cfg; |
dudmuck | 0:cb0046a629c1 | 130 | ctrl_reg1_t ctrl_reg1; |
dudmuck | 0:cb0046a629c1 | 131 | ctrl_reg4_t ctrl_reg4; |
dudmuck | 0:cb0046a629c1 | 132 | ctrl_reg5_t ctrl_reg5; |
dudmuck | 0:cb0046a629c1 | 133 | |
dudmuck | 0:cb0046a629c1 | 134 | private: |
dudmuck | 0:cb0046a629c1 | 135 | I2C& m_i2c; |
dudmuck | 1:778b685c3ad0 | 136 | DigitalIn& m_int_pin; |
dudmuck | 0:cb0046a629c1 | 137 | }; |
dudmuck | 0:cb0046a629c1 | 138 |