jhonatan llanten / Mbed 2 deprecated nfc_targetas_almacenada

Comparador de targetas

Dependencies:   mbed

MFRC522.cpp@0:7e562a9443f6, 2019-06-04 (annotated)

Committer:
jhonatanll
Date:
Tue Jun 04 11:21:09 2019 +0000
Revision:
0:7e562a9443f6
comparador NFC

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jhonatanll 0:7e562a9443f6 1 /*
jhonatanll 0:7e562a9443f6 2 * MFRC522.cpp - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
jhonatanll 0:7e562a9443f6 3 * _Please_ see the comments in MFRC522.h - they give useful hints and background.
jhonatanll 0:7e562a9443f6 4 * Released into the public domain.
jhonatanll 0:7e562a9443f6 5 */
jhonatanll 0:7e562a9443f6 6
jhonatanll 0:7e562a9443f6 7 #include "MFRC522.h"
jhonatanll 0:7e562a9443f6 8
jhonatanll 0:7e562a9443f6 9 static const char* const _TypeNamePICC[] =
jhonatanll 0:7e562a9443f6 10 {
jhonatanll 0:7e562a9443f6 11 "Unknown type",
jhonatanll 0:7e562a9443f6 12 "PICC compliant with ISO/IEC 14443-4",
jhonatanll 0:7e562a9443f6 13 "PICC compliant with ISO/IEC 18092 (NFC)",
jhonatanll 0:7e562a9443f6 14 "MIFARE Mini, 320 bytes",
jhonatanll 0:7e562a9443f6 15 "MIFARE 1KB",
jhonatanll 0:7e562a9443f6 16 "MIFARE 4KB",
jhonatanll 0:7e562a9443f6 17 "MIFARE Ultralight or Ultralight C",
jhonatanll 0:7e562a9443f6 18 "MIFARE Plus",
jhonatanll 0:7e562a9443f6 19 "MIFARE TNP3XXX",
jhonatanll 0:7e562a9443f6 20
jhonatanll 0:7e562a9443f6 21 /* not complete UID */
jhonatanll 0:7e562a9443f6 22 "SAK indicates UID is not complete"
jhonatanll 0:7e562a9443f6 23 };
jhonatanll 0:7e562a9443f6 24
jhonatanll 0:7e562a9443f6 25 static const char* const _ErrorMessage[] =
jhonatanll 0:7e562a9443f6 26 {
jhonatanll 0:7e562a9443f6 27 "Unknown error",
jhonatanll 0:7e562a9443f6 28 "Success",
jhonatanll 0:7e562a9443f6 29 "Error in communication",
jhonatanll 0:7e562a9443f6 30 "Collision detected",
jhonatanll 0:7e562a9443f6 31 "Timeout in communication",
jhonatanll 0:7e562a9443f6 32 "A buffer is not big enough",
jhonatanll 0:7e562a9443f6 33 "Internal error in the code, should not happen",
jhonatanll 0:7e562a9443f6 34 "Invalid argument",
jhonatanll 0:7e562a9443f6 35 "The CRC_A does not match",
jhonatanll 0:7e562a9443f6 36 "A MIFARE PICC responded with NAK"
jhonatanll 0:7e562a9443f6 37 };
jhonatanll 0:7e562a9443f6 38
jhonatanll 0:7e562a9443f6 39 #define MFRC522_MaxPICCs (sizeof(_TypeNamePICC)/sizeof(_TypeNamePICC[0]))
jhonatanll 0:7e562a9443f6 40 #define MFRC522_MaxError (sizeof(_ErrorMessage)/sizeof(_ErrorMessage[0]))
jhonatanll 0:7e562a9443f6 41
jhonatanll 0:7e562a9443f6 42 /////////////////////////////////////////////////////////////////////////////////////
jhonatanll 0:7e562a9443f6 43 // Functions for setting up the driver
jhonatanll 0:7e562a9443f6 44 /////////////////////////////////////////////////////////////////////////////////////
jhonatanll 0:7e562a9443f6 45
jhonatanll 0:7e562a9443f6 46 /**
jhonatanll 0:7e562a9443f6 47 * Constructor.
jhonatanll 0:7e562a9443f6 48 * Prepares the output pins.
jhonatanll 0:7e562a9443f6 49 */
jhonatanll 0:7e562a9443f6 50 MFRC522::MFRC522(PinName mosi,
jhonatanll 0:7e562a9443f6 51 PinName miso,
jhonatanll 0:7e562a9443f6 52 PinName sclk,
jhonatanll 0:7e562a9443f6 53 PinName cs,
jhonatanll 0:7e562a9443f6 54 PinName reset) : m_SPI(mosi, miso, sclk), m_CS(cs), m_RESET(reset)
jhonatanll 0:7e562a9443f6 55 {
jhonatanll 0:7e562a9443f6 56 /* Configure SPI bus */
jhonatanll 0:7e562a9443f6 57 m_SPI.format(8, 0);
jhonatanll 0:7e562a9443f6 58 m_SPI.frequency(8000000);
jhonatanll 0:7e562a9443f6 59
jhonatanll 0:7e562a9443f6 60 /* Release SPI-CS pin */
jhonatanll 0:7e562a9443f6 61 m_CS = 1;
jhonatanll 0:7e562a9443f6 62
jhonatanll 0:7e562a9443f6 63 /* Release RESET pin */
jhonatanll 0:7e562a9443f6 64 m_RESET = 1;
jhonatanll 0:7e562a9443f6 65 } // End constructor
jhonatanll 0:7e562a9443f6 66
jhonatanll 0:7e562a9443f6 67
jhonatanll 0:7e562a9443f6 68 /**
jhonatanll 0:7e562a9443f6 69 * Destructor.
jhonatanll 0:7e562a9443f6 70 */
jhonatanll 0:7e562a9443f6 71 MFRC522::~MFRC522()
jhonatanll 0:7e562a9443f6 72 {
jhonatanll 0:7e562a9443f6 73
jhonatanll 0:7e562a9443f6 74 }
jhonatanll 0:7e562a9443f6 75
jhonatanll 0:7e562a9443f6 76
jhonatanll 0:7e562a9443f6 77 /////////////////////////////////////////////////////////////////////////////////////
jhonatanll 0:7e562a9443f6 78 // Basic interface functions for communicating with the MFRC522
jhonatanll 0:7e562a9443f6 79 /////////////////////////////////////////////////////////////////////////////////////
jhonatanll 0:7e562a9443f6 80
jhonatanll 0:7e562a9443f6 81 /**
jhonatanll 0:7e562a9443f6 82 * Writes a byte to the specified register in the MFRC522 chip.
jhonatanll 0:7e562a9443f6 83 * The interface is described in the datasheet section 8.1.2.
jhonatanll 0:7e562a9443f6 84 */
jhonatanll 0:7e562a9443f6 85 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t value)
jhonatanll 0:7e562a9443f6 86 {
jhonatanll 0:7e562a9443f6 87 m_CS = 0; /* Select SPI Chip MFRC522 */
jhonatanll 0:7e562a9443f6 88
jhonatanll 0:7e562a9443f6 89 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
jhonatanll 0:7e562a9443f6 90 (void) m_SPI.write(reg & 0x7E);
jhonatanll 0:7e562a9443f6 91 (void) m_SPI.write(value);
jhonatanll 0:7e562a9443f6 92
jhonatanll 0:7e562a9443f6 93 m_CS = 1; /* Release SPI Chip MFRC522 */
jhonatanll 0:7e562a9443f6 94 } // End PCD_WriteRegister()
jhonatanll 0:7e562a9443f6 95
jhonatanll 0:7e562a9443f6 96 /**
jhonatanll 0:7e562a9443f6 97 * Writes a number of bytes to the specified register in the MFRC522 chip.
jhonatanll 0:7e562a9443f6 98 * The interface is described in the datasheet section 8.1.2.
jhonatanll 0:7e562a9443f6 99 */
jhonatanll 0:7e562a9443f6 100 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t count, uint8_t *values)
jhonatanll 0:7e562a9443f6 101 {
jhonatanll 0:7e562a9443f6 102 m_CS = 0; /* Select SPI Chip MFRC522 */
jhonatanll 0:7e562a9443f6 103
jhonatanll 0:7e562a9443f6 104 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
jhonatanll 0:7e562a9443f6 105 (void) m_SPI.write(reg & 0x7E);
jhonatanll 0:7e562a9443f6 106 for (uint8_t index = 0; index < count; index++)
jhonatanll 0:7e562a9443f6 107 {
jhonatanll 0:7e562a9443f6 108 (void) m_SPI.write(values[index]);
jhonatanll 0:7e562a9443f6 109 }
jhonatanll 0:7e562a9443f6 110
jhonatanll 0:7e562a9443f6 111 m_CS = 1; /* Release SPI Chip MFRC522 */
jhonatanll 0:7e562a9443f6 112 } // End PCD_WriteRegister()
jhonatanll 0:7e562a9443f6 113
jhonatanll 0:7e562a9443f6 114 /**
jhonatanll 0:7e562a9443f6 115 * Reads a byte from the specified register in the MFRC522 chip.
jhonatanll 0:7e562a9443f6 116 * The interface is described in the datasheet section 8.1.2.
jhonatanll 0:7e562a9443f6 117 */
jhonatanll 0:7e562a9443f6 118 uint8_t MFRC522::PCD_ReadRegister(uint8_t reg)
jhonatanll 0:7e562a9443f6 119 {
jhonatanll 0:7e562a9443f6 120 uint8_t value;
jhonatanll 0:7e562a9443f6 121 m_CS = 0; /* Select SPI Chip MFRC522 */
jhonatanll 0:7e562a9443f6 122
jhonatanll 0:7e562a9443f6 123 // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
jhonatanll 0:7e562a9443f6 124 (void) m_SPI.write(0x80 | reg);
jhonatanll 0:7e562a9443f6 125
jhonatanll 0:7e562a9443f6 126 // Read the value back. Send 0 to stop reading.
jhonatanll 0:7e562a9443f6 127 value = m_SPI.write(0);
jhonatanll 0:7e562a9443f6 128
jhonatanll 0:7e562a9443f6 129 m_CS = 1; /* Release SPI Chip MFRC522 */
jhonatanll 0:7e562a9443f6 130
jhonatanll 0:7e562a9443f6 131 return value;
jhonatanll 0:7e562a9443f6 132 } // End PCD_ReadRegister()
jhonatanll 0:7e562a9443f6 133
jhonatanll 0:7e562a9443f6 134 /**
jhonatanll 0:7e562a9443f6 135 * Reads a number of bytes from the specified register in the MFRC522 chip.
jhonatanll 0:7e562a9443f6 136 * The interface is described in the datasheet section 8.1.2.
jhonatanll 0:7e562a9443f6 137 */
jhonatanll 0:7e562a9443f6 138 void MFRC522::PCD_ReadRegister(uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign)
jhonatanll 0:7e562a9443f6 139 {
jhonatanll 0:7e562a9443f6 140 if (count == 0) { return; }
jhonatanll 0:7e562a9443f6 141
jhonatanll 0:7e562a9443f6 142 uint8_t address = 0x80 | reg; // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
jhonatanll 0:7e562a9443f6 143 uint8_t index = 0; // Index in values array.
jhonatanll 0:7e562a9443f6 144
jhonatanll 0:7e562a9443f6 145 m_CS = 0; /* Select SPI Chip MFRC522 */
jhonatanll 0:7e562a9443f6 146 count--; // One read is performed outside of the loop
jhonatanll 0:7e562a9443f6 147 (void) m_SPI.write(address); // Tell MFRC522 which address we want to read
jhonatanll 0:7e562a9443f6 148
jhonatanll 0:7e562a9443f6 149 while (index < count)
jhonatanll 0:7e562a9443f6 150 {
jhonatanll 0:7e562a9443f6 151 if ((index == 0) && rxAlign) // Only update bit positions rxAlign..7 in values[0]
jhonatanll 0:7e562a9443f6 152 {
jhonatanll 0:7e562a9443f6 153 // Create bit mask for bit positions rxAlign..7
jhonatanll 0:7e562a9443f6 154 uint8_t mask = 0;
jhonatanll 0:7e562a9443f6 155 for (uint8_t i = rxAlign; i <= 7; i++)
jhonatanll 0:7e562a9443f6 156 {
jhonatanll 0:7e562a9443f6 157 mask |= (1 << i);
jhonatanll 0:7e562a9443f6 158 }
jhonatanll 0:7e562a9443f6 159
jhonatanll 0:7e562a9443f6 160 // Read value and tell that we want to read the same address again.
jhonatanll 0:7e562a9443f6 161 uint8_t value = m_SPI.write(address);
jhonatanll 0:7e562a9443f6 162
jhonatanll 0:7e562a9443f6 163 // Apply mask to both current value of values[0] and the new data in value.
jhonatanll 0:7e562a9443f6 164 values[0] = (values[index] & ~mask) | (value & mask);
jhonatanll 0:7e562a9443f6 165 }
jhonatanll 0:7e562a9443f6 166 else
jhonatanll 0:7e562a9443f6 167 {
jhonatanll 0:7e562a9443f6 168 // Read value and tell that we want to read the same address again.
jhonatanll 0:7e562a9443f6 169 values[index] = m_SPI.write(address);
jhonatanll 0:7e562a9443f6 170 }
jhonatanll 0:7e562a9443f6 171
jhonatanll 0:7e562a9443f6 172 index++;
jhonatanll 0:7e562a9443f6 173 }
jhonatanll 0:7e562a9443f6 174
jhonatanll 0:7e562a9443f6 175 values[index] = m_SPI.write(0); // Read the final byte. Send 0 to stop reading.
jhonatanll 0:7e562a9443f6 176
jhonatanll 0:7e562a9443f6 177 m_CS = 1; /* Release SPI Chip MFRC522 */
jhonatanll 0:7e562a9443f6 178 } // End PCD_ReadRegister()
jhonatanll 0:7e562a9443f6 179
jhonatanll 0:7e562a9443f6 180 /**
jhonatanll 0:7e562a9443f6 181 * Sets the bits given in mask in register reg.
jhonatanll 0:7e562a9443f6 182 */
jhonatanll 0:7e562a9443f6 183 void MFRC522::PCD_SetRegisterBits(uint8_t reg, uint8_t mask)
jhonatanll 0:7e562a9443f6 184 {
jhonatanll 0:7e562a9443f6 185 uint8_t tmp = PCD_ReadRegister(reg);
jhonatanll 0:7e562a9443f6 186 PCD_WriteRegister(reg, tmp | mask); // set bit mask
jhonatanll 0:7e562a9443f6 187 } // End PCD_SetRegisterBitMask()
jhonatanll 0:7e562a9443f6 188
jhonatanll 0:7e562a9443f6 189 /**
jhonatanll 0:7e562a9443f6 190 * Clears the bits given in mask from register reg.
jhonatanll 0:7e562a9443f6 191 */
jhonatanll 0:7e562a9443f6 192 void MFRC522::PCD_ClrRegisterBits(uint8_t reg, uint8_t mask)
jhonatanll 0:7e562a9443f6 193 {
jhonatanll 0:7e562a9443f6 194 uint8_t tmp = PCD_ReadRegister(reg);
jhonatanll 0:7e562a9443f6 195 PCD_WriteRegister(reg, tmp & (~mask)); // clear bit mask
jhonatanll 0:7e562a9443f6 196 } // End PCD_ClearRegisterBitMask()
jhonatanll 0:7e562a9443f6 197
jhonatanll 0:7e562a9443f6 198
jhonatanll 0:7e562a9443f6 199 /**
jhonatanll 0:7e562a9443f6 200 * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
jhonatanll 0:7e562a9443f6 201 */
jhonatanll 0:7e562a9443f6 202 uint8_t MFRC522::PCD_CalculateCRC(uint8_t *data, uint8_t length, uint8_t *result)
jhonatanll 0:7e562a9443f6 203 {
jhonatanll 0:7e562a9443f6 204 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
jhonatanll 0:7e562a9443f6 205 PCD_WriteRegister(DivIrqReg, 0x04); // Clear the CRCIRq interrupt request bit
jhonatanll 0:7e562a9443f6 206 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
jhonatanll 0:7e562a9443f6 207 PCD_WriteRegister(FIFODataReg, length, data); // Write data to the FIFO
jhonatanll 0:7e562a9443f6 208 PCD_WriteRegister(CommandReg, PCD_CalcCRC); // Start the calculation
jhonatanll 0:7e562a9443f6 209
jhonatanll 0:7e562a9443f6 210 // Wait for the CRC calculation to complete. Each iteration of the while-loop takes 17.73us.
jhonatanll 0:7e562a9443f6 211 uint16_t i = 5000;
jhonatanll 0:7e562a9443f6 212 uint8_t n;
jhonatanll 0:7e562a9443f6 213 while (1)
jhonatanll 0:7e562a9443f6 214 {
jhonatanll 0:7e562a9443f6 215 n = PCD_ReadRegister(DivIrqReg); // DivIrqReg[7..0] bits are: Set2 reserved reserved MfinActIRq reserved CRCIRq reserved reserved
jhonatanll 0:7e562a9443f6 216 if (n & 0x04)
jhonatanll 0:7e562a9443f6 217 {
jhonatanll 0:7e562a9443f6 218 // CRCIRq bit set - calculation done
jhonatanll 0:7e562a9443f6 219 break;
jhonatanll 0:7e562a9443f6 220 }
jhonatanll 0:7e562a9443f6 221
jhonatanll 0:7e562a9443f6 222 if (--i == 0)
jhonatanll 0:7e562a9443f6 223 {
jhonatanll 0:7e562a9443f6 224 // The emergency break. We will eventually terminate on this one after 89ms.
jhonatanll 0:7e562a9443f6 225 // Communication with the MFRC522 might be down.
jhonatanll 0:7e562a9443f6 226 return STATUS_TIMEOUT;
jhonatanll 0:7e562a9443f6 227 }
jhonatanll 0:7e562a9443f6 228 }
jhonatanll 0:7e562a9443f6 229
jhonatanll 0:7e562a9443f6 230 // Stop calculating CRC for new content in the FIFO.
jhonatanll 0:7e562a9443f6 231 PCD_WriteRegister(CommandReg, PCD_Idle);
jhonatanll 0:7e562a9443f6 232
jhonatanll 0:7e562a9443f6 233 // Transfer the result from the registers to the result buffer
jhonatanll 0:7e562a9443f6 234 result[0] = PCD_ReadRegister(CRCResultRegL);
jhonatanll 0:7e562a9443f6 235 result[1] = PCD_ReadRegister(CRCResultRegH);
jhonatanll 0:7e562a9443f6 236 return STATUS_OK;
jhonatanll 0:7e562a9443f6 237 } // End PCD_CalculateCRC()
jhonatanll 0:7e562a9443f6 238
jhonatanll 0:7e562a9443f6 239
jhonatanll 0:7e562a9443f6 240 /////////////////////////////////////////////////////////////////////////////////////
jhonatanll 0:7e562a9443f6 241 // Functions for manipulating the MFRC522
jhonatanll 0:7e562a9443f6 242 /////////////////////////////////////////////////////////////////////////////////////
jhonatanll 0:7e562a9443f6 243
jhonatanll 0:7e562a9443f6 244 /**
jhonatanll 0:7e562a9443f6 245 * Initializes the MFRC522 chip.
jhonatanll 0:7e562a9443f6 246 */
jhonatanll 0:7e562a9443f6 247 void MFRC522::PCD_Init()
jhonatanll 0:7e562a9443f6 248 {
jhonatanll 0:7e562a9443f6 249 /* Reset MFRC522 */
jhonatanll 0:7e562a9443f6 250 m_RESET = 0;
jhonatanll 0:7e562a9443f6 251 wait_ms(10);
jhonatanll 0:7e562a9443f6 252 m_RESET = 1;
jhonatanll 0:7e562a9443f6 253
jhonatanll 0:7e562a9443f6 254 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
jhonatanll 0:7e562a9443f6 255 wait_ms(50);
jhonatanll 0:7e562a9443f6 256
jhonatanll 0:7e562a9443f6 257 // When communicating with a PICC we need a timeout if something goes wrong.
jhonatanll 0:7e562a9443f6 258 // f_timer = 13.56 MHz / (2*TPreScaler+1) where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo].
jhonatanll 0:7e562a9443f6 259 // TPrescaler_Hi are the four low bits in TModeReg. TPrescaler_Lo is TPrescalerReg.
jhonatanll 0:7e562a9443f6 260 PCD_WriteRegister(TModeReg, 0x80); // TAuto=1; timer starts automatically at the end of the transmission in all communication modes at all speeds
jhonatanll 0:7e562a9443f6 261 PCD_WriteRegister(TPrescalerReg, 0xA9); // TPreScaler = TModeReg[3..0]:TPrescalerReg, ie 0x0A9 = 169 => f_timer=40kHz, ie a timer period of 25us.
jhonatanll 0:7e562a9443f6 262 PCD_WriteRegister(TReloadRegH, 0x03); // Reload timer with 0x3E8 = 1000, ie 25ms before timeout.
jhonatanll 0:7e562a9443f6 263 PCD_WriteRegister(TReloadRegL, 0xE8);
jhonatanll 0:7e562a9443f6 264
jhonatanll 0:7e562a9443f6 265 PCD_WriteRegister(TxASKReg, 0x40); // Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting
jhonatanll 0:7e562a9443f6 266 PCD_WriteRegister(ModeReg, 0x3D); // Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4)
jhonatanll 0:7e562a9443f6 267
jhonatanll 0:7e562a9443f6 268 PCD_WriteRegister(RFCfgReg, (0x07<<4)); // Set Rx Gain to max
jhonatanll 0:7e562a9443f6 269
jhonatanll 0:7e562a9443f6 270 PCD_AntennaOn(); // Enable the antenna driver pins TX1 and TX2 (they were disabled by the reset)
jhonatanll 0:7e562a9443f6 271 } // End PCD_Init()
jhonatanll 0:7e562a9443f6 272
jhonatanll 0:7e562a9443f6 273 /**
jhonatanll 0:7e562a9443f6 274 * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
jhonatanll 0:7e562a9443f6 275 */
jhonatanll 0:7e562a9443f6 276 void MFRC522::PCD_Reset()
jhonatanll 0:7e562a9443f6 277 {
jhonatanll 0:7e562a9443f6 278 PCD_WriteRegister(CommandReg, PCD_SoftReset); // Issue the SoftReset command.
jhonatanll 0:7e562a9443f6 279 // The datasheet does not mention how long the SoftRest command takes to complete.
jhonatanll 0:7e562a9443f6 280 // But the MFRC522 might have been in soft power-down mode (triggered by bit 4 of CommandReg)
jhonatanll 0:7e562a9443f6 281 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
jhonatanll 0:7e562a9443f6 282 wait_ms(50);
jhonatanll 0:7e562a9443f6 283
jhonatanll 0:7e562a9443f6 284 // Wait for the PowerDown bit in CommandReg to be cleared
jhonatanll 0:7e562a9443f6 285 while (PCD_ReadRegister(CommandReg) & (1<<4))
jhonatanll 0:7e562a9443f6 286 {
jhonatanll 0:7e562a9443f6 287 // PCD still restarting - unlikely after waiting 50ms, but better safe than sorry.
jhonatanll 0:7e562a9443f6 288 }
jhonatanll 0:7e562a9443f6 289 } // End PCD_Reset()
jhonatanll 0:7e562a9443f6 290
jhonatanll 0:7e562a9443f6 291 /**
jhonatanll 0:7e562a9443f6 292 * Turns the antenna on by enabling pins TX1 and TX2.
jhonatanll 0:7e562a9443f6 293 * After a reset these pins disabled.
jhonatanll 0:7e562a9443f6 294 */
jhonatanll 0:7e562a9443f6 295 void MFRC522::PCD_AntennaOn()
jhonatanll 0:7e562a9443f6 296 {
jhonatanll 0:7e562a9443f6 297 uint8_t value = PCD_ReadRegister(TxControlReg);
jhonatanll 0:7e562a9443f6 298 if ((value & 0x03) != 0x03)
jhonatanll 0:7e562a9443f6 299 {
jhonatanll 0:7e562a9443f6 300 PCD_WriteRegister(TxControlReg, value | 0x03);
jhonatanll 0:7e562a9443f6 301 }
jhonatanll 0:7e562a9443f6 302 } // End PCD_AntennaOn()
jhonatanll 0:7e562a9443f6 303
jhonatanll 0:7e562a9443f6 304 /////////////////////////////////////////////////////////////////////////////////////
jhonatanll 0:7e562a9443f6 305 // Functions for communicating with PICCs
jhonatanll 0:7e562a9443f6 306 /////////////////////////////////////////////////////////////////////////////////////
jhonatanll 0:7e562a9443f6 307
jhonatanll 0:7e562a9443f6 308 /**
jhonatanll 0:7e562a9443f6 309 * Executes the Transceive command.
jhonatanll 0:7e562a9443f6 310 * CRC validation can only be done if backData and backLen are specified.
jhonatanll 0:7e562a9443f6 311 */
jhonatanll 0:7e562a9443f6 312 uint8_t MFRC522::PCD_TransceiveData(uint8_t *sendData,
jhonatanll 0:7e562a9443f6 313 uint8_t sendLen,
jhonatanll 0:7e562a9443f6 314 uint8_t *backData,
jhonatanll 0:7e562a9443f6 315 uint8_t *backLen,
jhonatanll 0:7e562a9443f6 316 uint8_t *validBits,
jhonatanll 0:7e562a9443f6 317 uint8_t rxAlign,
jhonatanll 0:7e562a9443f6 318 bool checkCRC)
jhonatanll 0:7e562a9443f6 319 {
jhonatanll 0:7e562a9443f6 320 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
jhonatanll 0:7e562a9443f6 321 return PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, sendData, sendLen, backData, backLen, validBits, rxAlign, checkCRC);
jhonatanll 0:7e562a9443f6 322 } // End PCD_TransceiveData()
jhonatanll 0:7e562a9443f6 323
jhonatanll 0:7e562a9443f6 324 /**
jhonatanll 0:7e562a9443f6 325 * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
jhonatanll 0:7e562a9443f6 326 * CRC validation can only be done if backData and backLen are specified.
jhonatanll 0:7e562a9443f6 327 */
jhonatanll 0:7e562a9443f6 328 uint8_t MFRC522::PCD_CommunicateWithPICC(uint8_t command,
jhonatanll 0:7e562a9443f6 329 uint8_t waitIRq,
jhonatanll 0:7e562a9443f6 330 uint8_t *sendData,
jhonatanll 0:7e562a9443f6 331 uint8_t sendLen,
jhonatanll 0:7e562a9443f6 332 uint8_t *backData,
jhonatanll 0:7e562a9443f6 333 uint8_t *backLen,
jhonatanll 0:7e562a9443f6 334 uint8_t *validBits,
jhonatanll 0:7e562a9443f6 335 uint8_t rxAlign,
jhonatanll 0:7e562a9443f6 336 bool checkCRC)
jhonatanll 0:7e562a9443f6 337 {
jhonatanll 0:7e562a9443f6 338 uint8_t n, _validBits = 0;
jhonatanll 0:7e562a9443f6 339 uint32_t i;
jhonatanll 0:7e562a9443f6 340
jhonatanll 0:7e562a9443f6 341 // Prepare values for BitFramingReg
jhonatanll 0:7e562a9443f6 342 uint8_t txLastBits = validBits ? *validBits : 0;
jhonatanll 0:7e562a9443f6 343 uint8_t bitFraming = (rxAlign << 4) + txLastBits; // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
jhonatanll 0:7e562a9443f6 344
jhonatanll 0:7e562a9443f6 345 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
jhonatanll 0:7e562a9443f6 346 PCD_WriteRegister(ComIrqReg, 0x7F); // Clear all seven interrupt request bits
jhonatanll 0:7e562a9443f6 347 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
jhonatanll 0:7e562a9443f6 348 PCD_WriteRegister(FIFODataReg, sendLen, sendData); // Write sendData to the FIFO
jhonatanll 0:7e562a9443f6 349 PCD_WriteRegister(BitFramingReg, bitFraming); // Bit adjustments
jhonatanll 0:7e562a9443f6 350 PCD_WriteRegister(CommandReg, command); // Execute the command
jhonatanll 0:7e562a9443f6 351 if (command == PCD_Transceive)
jhonatanll 0:7e562a9443f6 352 {
jhonatanll 0:7e562a9443f6 353 PCD_SetRegisterBits(BitFramingReg, 0x80); // StartSend=1, transmission of data starts
jhonatanll 0:7e562a9443f6 354 }
jhonatanll 0:7e562a9443f6 355
jhonatanll 0:7e562a9443f6 356 // Wait for the command to complete.
jhonatanll 0:7e562a9443f6 357 // In PCD_Init() we set the TAuto flag in TModeReg. This means the timer automatically starts when the PCD stops transmitting.
jhonatanll 0:7e562a9443f6 358 // Each iteration of the do-while-loop takes 17.86us.
jhonatanll 0:7e562a9443f6 359 i = 2000;
jhonatanll 0:7e562a9443f6 360 while (1)
jhonatanll 0:7e562a9443f6 361 {
jhonatanll 0:7e562a9443f6 362 n = PCD_ReadRegister(ComIrqReg); // ComIrqReg[7..0] bits are: Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq
jhonatanll 0:7e562a9443f6 363 if (n & waitIRq)
jhonatanll 0:7e562a9443f6 364 { // One of the interrupts that signal success has been set.
jhonatanll 0:7e562a9443f6 365 break;
jhonatanll 0:7e562a9443f6 366 }
jhonatanll 0:7e562a9443f6 367
jhonatanll 0:7e562a9443f6 368 if (n & 0x01)
jhonatanll 0:7e562a9443f6 369 { // Timer interrupt - nothing received in 25ms
jhonatanll 0:7e562a9443f6 370 return STATUS_TIMEOUT;
jhonatanll 0:7e562a9443f6 371 }
jhonatanll 0:7e562a9443f6 372
jhonatanll 0:7e562a9443f6 373 if (--i == 0)
jhonatanll 0:7e562a9443f6 374 { // The emergency break. If all other condions fail we will eventually terminate on this one after 35.7ms. Communication with the MFRC522 might be down.
jhonatanll 0:7e562a9443f6 375 return STATUS_TIMEOUT;
jhonatanll 0:7e562a9443f6 376 }
jhonatanll 0:7e562a9443f6 377 }
jhonatanll 0:7e562a9443f6 378
jhonatanll 0:7e562a9443f6 379 // Stop now if any errors except collisions were detected.
jhonatanll 0:7e562a9443f6 380 uint8_t errorRegValue = PCD_ReadRegister(ErrorReg); // ErrorReg[7..0] bits are: WrErr TempErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr
jhonatanll 0:7e562a9443f6 381 if (errorRegValue & 0x13)
jhonatanll 0:7e562a9443f6 382 { // BufferOvfl ParityErr ProtocolErr
jhonatanll 0:7e562a9443f6 383 return STATUS_ERROR;
jhonatanll 0:7e562a9443f6 384 }
jhonatanll 0:7e562a9443f6 385
jhonatanll 0:7e562a9443f6 386 // If the caller wants data back, get it from the MFRC522.
jhonatanll 0:7e562a9443f6 387 if (backData && backLen)
jhonatanll 0:7e562a9443f6 388 {
jhonatanll 0:7e562a9443f6 389 n = PCD_ReadRegister(FIFOLevelReg); // Number of bytes in the FIFO
jhonatanll 0:7e562a9443f6 390 if (n > *backLen)
jhonatanll 0:7e562a9443f6 391 {
jhonatanll 0:7e562a9443f6 392 return STATUS_NO_ROOM;
jhonatanll 0:7e562a9443f6 393 }
jhonatanll 0:7e562a9443f6 394
jhonatanll 0:7e562a9443f6 395 *backLen = n; // Number of bytes returned
jhonatanll 0:7e562a9443f6 396 PCD_ReadRegister(FIFODataReg, n, backData, rxAlign); // Get received data from FIFO
jhonatanll 0:7e562a9443f6 397 _validBits = PCD_ReadRegister(ControlReg) & 0x07; // RxLastBits[2:0] indicates the number of valid bits in the last received byte. If this value is 000b, the whole byte is valid.
jhonatanll 0:7e562a9443f6 398 if (validBits)
jhonatanll 0:7e562a9443f6 399 {
jhonatanll 0:7e562a9443f6 400 *validBits = _validBits;
jhonatanll 0:7e562a9443f6 401 }
jhonatanll 0:7e562a9443f6 402 }
jhonatanll 0:7e562a9443f6 403
jhonatanll 0:7e562a9443f6 404 // Tell about collisions
jhonatanll 0:7e562a9443f6 405 if (errorRegValue & 0x08)
jhonatanll 0:7e562a9443f6 406 { // CollErr
jhonatanll 0:7e562a9443f6 407 return STATUS_COLLISION;
jhonatanll 0:7e562a9443f6 408 }
jhonatanll 0:7e562a9443f6 409
jhonatanll 0:7e562a9443f6 410 // Perform CRC_A validation if requested.
jhonatanll 0:7e562a9443f6 411 if (backData && backLen && checkCRC)
jhonatanll 0:7e562a9443f6 412 {
jhonatanll 0:7e562a9443f6 413 // In this case a MIFARE Classic NAK is not OK.
jhonatanll 0:7e562a9443f6 414 if ((*backLen == 1) && (_validBits == 4))
jhonatanll 0:7e562a9443f6 415 {
jhonatanll 0:7e562a9443f6 416 return STATUS_MIFARE_NACK;
jhonatanll 0:7e562a9443f6 417 }
jhonatanll 0:7e562a9443f6 418
jhonatanll 0:7e562a9443f6 419 // We need at least the CRC_A value and all 8 bits of the last byte must be received.
jhonatanll 0:7e562a9443f6 420 if ((*backLen < 2) || (_validBits != 0))
jhonatanll 0:7e562a9443f6 421 {
jhonatanll 0:7e562a9443f6 422 return STATUS_CRC_WRONG;
jhonatanll 0:7e562a9443f6 423 }
jhonatanll 0:7e562a9443f6 424
jhonatanll 0:7e562a9443f6 425 // Verify CRC_A - do our own calculation and store the control in controlBuffer.
jhonatanll 0:7e562a9443f6 426 uint8_t controlBuffer[2];
jhonatanll 0:7e562a9443f6 427 n = PCD_CalculateCRC(&backData[0], *backLen - 2, &controlBuffer[0]);
jhonatanll 0:7e562a9443f6 428 if (n != STATUS_OK)
jhonatanll 0:7e562a9443f6 429 {
jhonatanll 0:7e562a9443f6 430 return n;
jhonatanll 0:7e562a9443f6 431 }
jhonatanll 0:7e562a9443f6 432
jhonatanll 0:7e562a9443f6 433 if ((backData[*backLen - 2] != controlBuffer[0]) || (backData[*backLen - 1] != controlBuffer[1]))
jhonatanll 0:7e562a9443f6 434 {
jhonatanll 0:7e562a9443f6 435 return STATUS_CRC_WRONG;
jhonatanll 0:7e562a9443f6 436 }
jhonatanll 0:7e562a9443f6 437 }
jhonatanll 0:7e562a9443f6 438
jhonatanll 0:7e562a9443f6 439 return STATUS_OK;
jhonatanll 0:7e562a9443f6 440 } // End PCD_CommunicateWithPICC()
jhonatanll 0:7e562a9443f6 441
jhonatanll 0:7e562a9443f6 442 /*
jhonatanll 0:7e562a9443f6 443 * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
jhonatanll 0:7e562a9443f6 444 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
jhonatanll 0:7e562a9443f6 445 */
jhonatanll 0:7e562a9443f6 446 uint8_t MFRC522::PICC_RequestA(uint8_t *bufferATQA, uint8_t *bufferSize)
jhonatanll 0:7e562a9443f6 447 {
jhonatanll 0:7e562a9443f6 448 return PICC_REQA_or_WUPA(PICC_CMD_REQA, bufferATQA, bufferSize);
jhonatanll 0:7e562a9443f6 449 } // End PICC_RequestA()
jhonatanll 0:7e562a9443f6 450
jhonatanll 0:7e562a9443f6 451 /**
jhonatanll 0:7e562a9443f6 452 * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
jhonatanll 0:7e562a9443f6 453 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
jhonatanll 0:7e562a9443f6 454 */
jhonatanll 0:7e562a9443f6 455 uint8_t MFRC522::PICC_WakeupA(uint8_t *bufferATQA, uint8_t *bufferSize)
jhonatanll 0:7e562a9443f6 456 {
jhonatanll 0:7e562a9443f6 457 return PICC_REQA_or_WUPA(PICC_CMD_WUPA, bufferATQA, bufferSize);
jhonatanll 0:7e562a9443f6 458 } // End PICC_WakeupA()
jhonatanll 0:7e562a9443f6 459
jhonatanll 0:7e562a9443f6 460 /*
jhonatanll 0:7e562a9443f6 461 * Transmits REQA or WUPA commands.
jhonatanll 0:7e562a9443f6 462 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
jhonatanll 0:7e562a9443f6 463 */
jhonatanll 0:7e562a9443f6 464 uint8_t MFRC522::PICC_REQA_or_WUPA(uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize)
jhonatanll 0:7e562a9443f6 465 {
jhonatanll 0:7e562a9443f6 466 uint8_t validBits;
jhonatanll 0:7e562a9443f6 467 uint8_t status;
jhonatanll 0:7e562a9443f6 468
jhonatanll 0:7e562a9443f6 469 if (bufferATQA == NULL || *bufferSize < 2)
jhonatanll 0:7e562a9443f6 470 { // The ATQA response is 2 bytes long.
jhonatanll 0:7e562a9443f6 471 return STATUS_NO_ROOM;
jhonatanll 0:7e562a9443f6 472 }
jhonatanll 0:7e562a9443f6 473
jhonatanll 0:7e562a9443f6 474 // ValuesAfterColl=1 => Bits received after collision are cleared.
jhonatanll 0:7e562a9443f6 475 PCD_ClrRegisterBits(CollReg, 0x80);
jhonatanll 0:7e562a9443f6 476
jhonatanll 0:7e562a9443f6 477 // For REQA and WUPA we need the short frame format
jhonatanll 0:7e562a9443f6 478 // - transmit only 7 bits of the last (and only) byte. TxLastBits = BitFramingReg[2..0]
jhonatanll 0:7e562a9443f6 479 validBits = 7;
jhonatanll 0:7e562a9443f6 480
jhonatanll 0:7e562a9443f6 481 status = PCD_TransceiveData(&command, 1, bufferATQA, bufferSize, &validBits);
jhonatanll 0:7e562a9443f6 482 if (status != STATUS_OK)
jhonatanll 0:7e562a9443f6 483 {
jhonatanll 0:7e562a9443f6 484 return status;
jhonatanll 0:7e562a9443f6 485 }
jhonatanll 0:7e562a9443f6 486
jhonatanll 0:7e562a9443f6 487 if ((*bufferSize != 2) || (validBits != 0))
jhonatanll 0:7e562a9443f6 488 { // ATQA must be exactly 16 bits.
jhonatanll 0:7e562a9443f6 489 return STATUS_ERROR;
jhonatanll 0:7e562a9443f6 490 }
jhonatanll 0:7e562a9443f6 491
jhonatanll 0:7e562a9443f6 492 return STATUS_OK;
jhonatanll 0:7e562a9443f6 493 } // End PICC_REQA_or_WUPA()
jhonatanll 0:7e562a9443f6 494
jhonatanll 0:7e562a9443f6 495 /*
jhonatanll 0:7e562a9443f6 496 * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
jhonatanll 0:7e562a9443f6 497 */
jhonatanll 0:7e562a9443f6 498 uint8_t MFRC522::PICC_Select(Uid *uid, uint8_t validBits)
jhonatanll 0:7e562a9443f6 499 {
jhonatanll 0:7e562a9443f6 500 bool uidComplete;
jhonatanll 0:7e562a9443f6 501 bool selectDone;
jhonatanll 0:7e562a9443f6 502 bool useCascadeTag;
jhonatanll 0:7e562a9443f6 503 uint8_t cascadeLevel = 1;
jhonatanll 0:7e562a9443f6 504 uint8_t result;
jhonatanll 0:7e562a9443f6 505 uint8_t count;
jhonatanll 0:7e562a9443f6 506 uint8_t index;
jhonatanll 0:7e562a9443f6 507 uint8_t uidIndex; // The first index in uid->uidByte[] that is used in the current Cascade Level.
jhonatanll 0:7e562a9443f6 508 uint8_t currentLevelKnownBits; // The number of known UID bits in the current Cascade Level.
jhonatanll 0:7e562a9443f6 509 uint8_t buffer[9]; // The SELECT/ANTICOLLISION commands uses a 7 byte standard frame + 2 bytes CRC_A
jhonatanll 0:7e562a9443f6 510 uint8_t bufferUsed; // The number of bytes used in the buffer, ie the number of bytes to transfer to the FIFO.
jhonatanll 0:7e562a9443f6 511 uint8_t rxAlign; // Used in BitFramingReg. Defines the bit position for the first bit received.
jhonatanll 0:7e562a9443f6 512 uint8_t txLastBits; // Used in BitFramingReg. The number of valid bits in the last transmitted byte.
jhonatanll 0:7e562a9443f6 513 uint8_t *responseBuffer;
jhonatanll 0:7e562a9443f6 514 uint8_t responseLength;
jhonatanll 0:7e562a9443f6 515
jhonatanll 0:7e562a9443f6 516 // Description of buffer structure:
jhonatanll 0:7e562a9443f6 517 // Byte 0: SEL Indicates the Cascade Level: PICC_CMD_SEL_CL1, PICC_CMD_SEL_CL2 or PICC_CMD_SEL_CL3
jhonatanll 0:7e562a9443f6 518 // Byte 1: NVB Number of Valid Bits (in complete command, not just the UID): High nibble: complete bytes, Low nibble: Extra bits.
jhonatanll 0:7e562a9443f6 519 // Byte 2: UID-data or CT See explanation below. CT means Cascade Tag.
jhonatanll 0:7e562a9443f6 520 // Byte 3: UID-data
jhonatanll 0:7e562a9443f6 521 // Byte 4: UID-data
jhonatanll 0:7e562a9443f6 522 // Byte 5: UID-data
jhonatanll 0:7e562a9443f6 523 // Byte 6: BCC Block Check Character - XOR of bytes 2-5
jhonatanll 0:7e562a9443f6 524 // Byte 7: CRC_A
jhonatanll 0:7e562a9443f6 525 // Byte 8: CRC_A
jhonatanll 0:7e562a9443f6 526 // The BCC and CRC_A is only transmitted if we know all the UID bits of the current Cascade Level.
jhonatanll 0:7e562a9443f6 527 //
jhonatanll 0:7e562a9443f6 528 // Description of bytes 2-5: (Section 6.5.4 of the ISO/IEC 14443-3 draft: UID contents and cascade levels)
jhonatanll 0:7e562a9443f6 529 // UID size Cascade level Byte2 Byte3 Byte4 Byte5
jhonatanll 0:7e562a9443f6 530 // ======== ============= ===== ===== ===== =====
jhonatanll 0:7e562a9443f6 531 // 4 bytes 1 uid0 uid1 uid2 uid3
jhonatanll 0:7e562a9443f6 532 // 7 bytes 1 CT uid0 uid1 uid2
jhonatanll 0:7e562a9443f6 533 // 2 uid3 uid4 uid5 uid6
jhonatanll 0:7e562a9443f6 534 // 10 bytes 1 CT uid0 uid1 uid2
jhonatanll 0:7e562a9443f6 535 // 2 CT uid3 uid4 uid5
jhonatanll 0:7e562a9443f6 536 // 3 uid6 uid7 uid8 uid9
jhonatanll 0:7e562a9443f6 537
jhonatanll 0:7e562a9443f6 538 // Sanity checks
jhonatanll 0:7e562a9443f6 539 if (validBits > 80)
jhonatanll 0:7e562a9443f6 540 {
jhonatanll 0:7e562a9443f6 541 return STATUS_INVALID;
jhonatanll 0:7e562a9443f6 542 }
jhonatanll 0:7e562a9443f6 543
jhonatanll 0:7e562a9443f6 544 // Prepare MFRC522
jhonatanll 0:7e562a9443f6 545 // ValuesAfterColl=1 => Bits received after collision are cleared.
jhonatanll 0:7e562a9443f6 546 PCD_ClrRegisterBits(CollReg, 0x80);
jhonatanll 0:7e562a9443f6 547
jhonatanll 0:7e562a9443f6 548 // Repeat Cascade Level loop until we have a complete UID.
jhonatanll 0:7e562a9443f6 549 uidComplete = false;
jhonatanll 0:7e562a9443f6 550 while ( ! uidComplete)
jhonatanll 0:7e562a9443f6 551 {
jhonatanll 0:7e562a9443f6 552 // Set the Cascade Level in the SEL byte, find out if we need to use the Cascade Tag in byte 2.
jhonatanll 0:7e562a9443f6 553 switch (cascadeLevel)
jhonatanll 0:7e562a9443f6 554 {
jhonatanll 0:7e562a9443f6 555 case 1:
jhonatanll 0:7e562a9443f6 556 buffer[0] = PICC_CMD_SEL_CL1;
jhonatanll 0:7e562a9443f6 557 uidIndex = 0;
jhonatanll 0:7e562a9443f6 558 useCascadeTag = validBits && (uid->size > 4); // When we know that the UID has more than 4 bytes
jhonatanll 0:7e562a9443f6 559 break;
jhonatanll 0:7e562a9443f6 560
jhonatanll 0:7e562a9443f6 561 case 2:
jhonatanll 0:7e562a9443f6 562 buffer[0] = PICC_CMD_SEL_CL2;
jhonatanll 0:7e562a9443f6 563 uidIndex = 3;
jhonatanll 0:7e562a9443f6 564 useCascadeTag = validBits && (uid->size > 7); // When we know that the UID has more than 7 bytes
jhonatanll 0:7e562a9443f6 565 break;
jhonatanll 0:7e562a9443f6 566
jhonatanll 0:7e562a9443f6 567 case 3:
jhonatanll 0:7e562a9443f6 568 buffer[0] = PICC_CMD_SEL_CL3;
jhonatanll 0:7e562a9443f6 569 uidIndex = 6;
jhonatanll 0:7e562a9443f6 570 useCascadeTag = false; // Never used in CL3.
jhonatanll 0:7e562a9443f6 571 break;
jhonatanll 0:7e562a9443f6 572
jhonatanll 0:7e562a9443f6 573 default:
jhonatanll 0:7e562a9443f6 574 return STATUS_INTERNAL_ERROR;
jhonatanll 0:7e562a9443f6 575 //break;
jhonatanll 0:7e562a9443f6 576 }
jhonatanll 0:7e562a9443f6 577
jhonatanll 0:7e562a9443f6 578 // How many UID bits are known in this Cascade Level?
jhonatanll 0:7e562a9443f6 579 if(validBits > (8 * uidIndex))
jhonatanll 0:7e562a9443f6 580 {
jhonatanll 0:7e562a9443f6 581 currentLevelKnownBits = validBits - (8 * uidIndex);
jhonatanll 0:7e562a9443f6 582 }
jhonatanll 0:7e562a9443f6 583 else
jhonatanll 0:7e562a9443f6 584 {
jhonatanll 0:7e562a9443f6 585 currentLevelKnownBits = 0;
jhonatanll 0:7e562a9443f6 586 }
jhonatanll 0:7e562a9443f6 587
jhonatanll 0:7e562a9443f6 588 // Copy the known bits from uid->uidByte[] to buffer[]
jhonatanll 0:7e562a9443f6 589 index = 2; // destination index in buffer[]
jhonatanll 0:7e562a9443f6 590 if (useCascadeTag)
jhonatanll 0:7e562a9443f6 591 {
jhonatanll 0:7e562a9443f6 592 buffer[index++] = PICC_CMD_CT;
jhonatanll 0:7e562a9443f6 593 }
jhonatanll 0:7e562a9443f6 594
jhonatanll 0:7e562a9443f6 595 uint8_t bytesToCopy = currentLevelKnownBits / 8 + (currentLevelKnownBits % 8 ? 1 : 0); // The number of bytes needed to represent the known bits for this level.
jhonatanll 0:7e562a9443f6 596 if (bytesToCopy)
jhonatanll 0:7e562a9443f6 597 {
jhonatanll 0:7e562a9443f6 598 // Max 4 bytes in each Cascade Level. Only 3 left if we use the Cascade Tag
jhonatanll 0:7e562a9443f6 599 uint8_t maxBytes = useCascadeTag ? 3 : 4;
jhonatanll 0:7e562a9443f6 600 if (bytesToCopy > maxBytes)
jhonatanll 0:7e562a9443f6 601 {
jhonatanll 0:7e562a9443f6 602 bytesToCopy = maxBytes;
jhonatanll 0:7e562a9443f6 603 }
jhonatanll 0:7e562a9443f6 604
jhonatanll 0:7e562a9443f6 605 for (count = 0; count < bytesToCopy; count++)
jhonatanll 0:7e562a9443f6 606 {
jhonatanll 0:7e562a9443f6 607 buffer[index++] = uid->uidByte[uidIndex + count];
jhonatanll 0:7e562a9443f6 608 }
jhonatanll 0:7e562a9443f6 609 }
jhonatanll 0:7e562a9443f6 610
jhonatanll 0:7e562a9443f6 611 // Now that the data has been copied we need to include the 8 bits in CT in currentLevelKnownBits
jhonatanll 0:7e562a9443f6 612 if (useCascadeTag)
jhonatanll 0:7e562a9443f6 613 {
jhonatanll 0:7e562a9443f6 614 currentLevelKnownBits += 8;
jhonatanll 0:7e562a9443f6 615 }
jhonatanll 0:7e562a9443f6 616
jhonatanll 0:7e562a9443f6 617 // Repeat anti collision loop until we can transmit all UID bits + BCC and receive a SAK - max 32 iterations.
jhonatanll 0:7e562a9443f6 618 selectDone = false;
jhonatanll 0:7e562a9443f6 619 while ( ! selectDone)
jhonatanll 0:7e562a9443f6 620 {
jhonatanll 0:7e562a9443f6 621 // Find out how many bits and bytes to send and receive.
jhonatanll 0:7e562a9443f6 622 if (currentLevelKnownBits >= 32)
jhonatanll 0:7e562a9443f6 623 { // All UID bits in this Cascade Level are known. This is a SELECT.
jhonatanll 0:7e562a9443f6 624 //Serial.print("SELECT: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
jhonatanll 0:7e562a9443f6 625 buffer[1] = 0x70; // NVB - Number of Valid Bits: Seven whole bytes
jhonatanll 0:7e562a9443f6 626
jhonatanll 0:7e562a9443f6 627 // Calulate BCC - Block Check Character
jhonatanll 0:7e562a9443f6 628 buffer[6] = buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5];
jhonatanll 0:7e562a9443f6 629
jhonatanll 0:7e562a9443f6 630 // Calculate CRC_A
jhonatanll 0:7e562a9443f6 631 result = PCD_CalculateCRC(buffer, 7, &buffer[7]);
jhonatanll 0:7e562a9443f6 632 if (result != STATUS_OK)
jhonatanll 0:7e562a9443f6 633 {
jhonatanll 0:7e562a9443f6 634 return result;
jhonatanll 0:7e562a9443f6 635 }
jhonatanll 0:7e562a9443f6 636
jhonatanll 0:7e562a9443f6 637 txLastBits = 0; // 0 => All 8 bits are valid.
jhonatanll 0:7e562a9443f6 638 bufferUsed = 9;
jhonatanll 0:7e562a9443f6 639
jhonatanll 0:7e562a9443f6 640 // Store response in the last 3 bytes of buffer (BCC and CRC_A - not needed after tx)
jhonatanll 0:7e562a9443f6 641 responseBuffer = &buffer[6];
jhonatanll 0:7e562a9443f6 642 responseLength = 3;
jhonatanll 0:7e562a9443f6 643 }
jhonatanll 0:7e562a9443f6 644 else
jhonatanll 0:7e562a9443f6 645 { // This is an ANTICOLLISION.
jhonatanll 0:7e562a9443f6 646 //Serial.print("ANTICOLLISION: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
jhonatanll 0:7e562a9443f6 647 txLastBits = currentLevelKnownBits % 8;
jhonatanll 0:7e562a9443f6 648 count = currentLevelKnownBits / 8; // Number of whole bytes in the UID part.
jhonatanll 0:7e562a9443f6 649 index = 2 + count; // Number of whole bytes: SEL + NVB + UIDs
jhonatanll 0:7e562a9443f6 650 buffer[1] = (index << 4) + txLastBits; // NVB - Number of Valid Bits
jhonatanll 0:7e562a9443f6 651 bufferUsed = index + (txLastBits ? 1 : 0);
jhonatanll 0:7e562a9443f6 652
jhonatanll 0:7e562a9443f6 653 // Store response in the unused part of buffer
jhonatanll 0:7e562a9443f6 654 responseBuffer = &buffer[index];
jhonatanll 0:7e562a9443f6 655 responseLength = sizeof(buffer) - index;
jhonatanll 0:7e562a9443f6 656 }
jhonatanll 0:7e562a9443f6 657
jhonatanll 0:7e562a9443f6 658 // Set bit adjustments
jhonatanll 0:7e562a9443f6 659 rxAlign = txLastBits; // Having a seperate variable is overkill. But it makes the next line easier to read.
jhonatanll 0:7e562a9443f6 660 PCD_WriteRegister(BitFramingReg, (rxAlign << 4) + txLastBits); // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
jhonatanll 0:7e562a9443f6 661
jhonatanll 0:7e562a9443f6 662 // Transmit the buffer and receive the response.
jhonatanll 0:7e562a9443f6 663 result = PCD_TransceiveData(buffer, bufferUsed, responseBuffer, &responseLength, &txLastBits, rxAlign);
jhonatanll 0:7e562a9443f6 664 if (result == STATUS_COLLISION)
jhonatanll 0:7e562a9443f6 665 { // More than one PICC in the field => collision.
jhonatanll 0:7e562a9443f6 666 result = PCD_ReadRegister(CollReg); // CollReg[7..0] bits are: ValuesAfterColl reserved CollPosNotValid CollPos[4:0]
jhonatanll 0:7e562a9443f6 667 if (result & 0x20)
jhonatanll 0:7e562a9443f6 668 { // CollPosNotValid
jhonatanll 0:7e562a9443f6 669 return STATUS_COLLISION; // Without a valid collision position we cannot continue
jhonatanll 0:7e562a9443f6 670 }
jhonatanll 0:7e562a9443f6 671
jhonatanll 0:7e562a9443f6 672 uint8_t collisionPos = result & 0x1F; // Values 0-31, 0 means bit 32.
jhonatanll 0:7e562a9443f6 673 if (collisionPos == 0)
jhonatanll 0:7e562a9443f6 674 {
jhonatanll 0:7e562a9443f6 675 collisionPos = 32;
jhonatanll 0:7e562a9443f6 676 }
jhonatanll 0:7e562a9443f6 677
jhonatanll 0:7e562a9443f6 678 if (collisionPos <= currentLevelKnownBits)
jhonatanll 0:7e562a9443f6 679 { // No progress - should not happen
jhonatanll 0:7e562a9443f6 680 return STATUS_INTERNAL_ERROR;
jhonatanll 0:7e562a9443f6 681 }
jhonatanll 0:7e562a9443f6 682
jhonatanll 0:7e562a9443f6 683 // Choose the PICC with the bit set.
jhonatanll 0:7e562a9443f6 684 currentLevelKnownBits = collisionPos;
jhonatanll 0:7e562a9443f6 685 count = (currentLevelKnownBits - 1) % 8; // The bit to modify
jhonatanll 0:7e562a9443f6 686 index = 1 + (currentLevelKnownBits / 8) + (count ? 1 : 0); // First byte is index 0.
jhonatanll 0:7e562a9443f6 687 buffer[index] |= (1 << count);
jhonatanll 0:7e562a9443f6 688 }
jhonatanll 0:7e562a9443f6 689 else if (result != STATUS_OK)
jhonatanll 0:7e562a9443f6 690 {
jhonatanll 0:7e562a9443f6 691 return result;
jhonatanll 0:7e562a9443f6 692 }
jhonatanll 0:7e562a9443f6 693 else
jhonatanll 0:7e562a9443f6 694 { // STATUS_OK
jhonatanll 0:7e562a9443f6 695 if (currentLevelKnownBits >= 32)
jhonatanll 0:7e562a9443f6 696 { // This was a SELECT.
jhonatanll 0:7e562a9443f6 697 selectDone = true; // No more anticollision
jhonatanll 0:7e562a9443f6 698 // We continue below outside the while.
jhonatanll 0:7e562a9443f6 699 }
jhonatanll 0:7e562a9443f6 700 else
jhonatanll 0:7e562a9443f6 701 { // This was an ANTICOLLISION.
jhonatanll 0:7e562a9443f6 702 // We now have all 32 bits of the UID in this Cascade Level
jhonatanll 0:7e562a9443f6 703 currentLevelKnownBits = 32;
jhonatanll 0:7e562a9443f6 704 // Run loop again to do the SELECT.
jhonatanll 0:7e562a9443f6 705 }
jhonatanll 0:7e562a9443f6 706 }
jhonatanll 0:7e562a9443f6 707 } // End of while ( ! selectDone)
jhonatanll 0:7e562a9443f6 708
jhonatanll 0:7e562a9443f6 709 // We do not check the CBB - it was constructed by us above.
jhonatanll 0:7e562a9443f6 710
jhonatanll 0:7e562a9443f6 711 // Copy the found UID bytes from buffer[] to uid->uidByte[]
jhonatanll 0:7e562a9443f6 712 index = (buffer[2] == PICC_CMD_CT) ? 3 : 2; // source index in buffer[]
jhonatanll 0:7e562a9443f6 713 bytesToCopy = (buffer[2] == PICC_CMD_CT) ? 3 : 4;
jhonatanll 0:7e562a9443f6 714 for (count = 0; count < bytesToCopy; count++)
jhonatanll 0:7e562a9443f6 715 {
jhonatanll 0:7e562a9443f6 716 uid->uidByte[uidIndex + count] = buffer[index++];
jhonatanll 0:7e562a9443f6 717 }
jhonatanll 0:7e562a9443f6 718
jhonatanll 0:7e562a9443f6 719 // Check response SAK (Select Acknowledge)
jhonatanll 0:7e562a9443f6 720 if (responseLength != 3 || txLastBits != 0)
jhonatanll 0:7e562a9443f6 721 { // SAK must be exactly 24 bits (1 byte + CRC_A).
jhonatanll 0:7e562a9443f6 722 return STATUS_ERROR;
jhonatanll 0:7e562a9443f6 723 }
jhonatanll 0:7e562a9443f6 724
jhonatanll 0:7e562a9443f6 725 // Verify CRC_A - do our own calculation and store the control in buffer[2..3] - those bytes are not needed anymore.
jhonatanll 0:7e562a9443f6 726 result = PCD_CalculateCRC(responseBuffer, 1, &buffer[2]);
jhonatanll 0:7e562a9443f6 727 if (result != STATUS_OK)
jhonatanll 0:7e562a9443f6 728 {
jhonatanll 0:7e562a9443f6 729 return result;
jhonatanll 0:7e562a9443f6 730 }
jhonatanll 0:7e562a9443f6 731
jhonatanll 0:7e562a9443f6 732 if ((buffer[2] != responseBuffer[1]) || (buffer[3] != responseBuffer[2]))
jhonatanll 0:7e562a9443f6 733 {
jhonatanll 0:7e562a9443f6 734 return STATUS_CRC_WRONG;
jhonatanll 0:7e562a9443f6 735 }
jhonatanll 0:7e562a9443f6 736
jhonatanll 0:7e562a9443f6 737 if (responseBuffer[0] & 0x04)
jhonatanll 0:7e562a9443f6 738 { // Cascade bit set - UID not complete yes
jhonatanll 0:7e562a9443f6 739 cascadeLevel++;
jhonatanll 0:7e562a9443f6 740 }
jhonatanll 0:7e562a9443f6 741 else
jhonatanll 0:7e562a9443f6 742 {
jhonatanll 0:7e562a9443f6 743 uidComplete = true;
jhonatanll 0:7e562a9443f6 744 uid->sak = responseBuffer[0];
jhonatanll 0:7e562a9443f6 745 }
jhonatanll 0:7e562a9443f6 746 } // End of while ( ! uidComplete)
jhonatanll 0:7e562a9443f6 747
jhonatanll 0:7e562a9443f6 748 // Set correct uid->size
jhonatanll 0:7e562a9443f6 749 uid->size = 3 * cascadeLevel + 1;
jhonatanll 0:7e562a9443f6 750
jhonatanll 0:7e562a9443f6 751 return STATUS_OK;
jhonatanll 0:7e562a9443f6 752 } // End PICC_Select()
jhonatanll 0:7e562a9443f6 753
jhonatanll 0:7e562a9443f6 754 /*
jhonatanll 0:7e562a9443f6 755 * Instructs a PICC in state ACTIVE(*) to go to state HALT.
jhonatanll 0:7e562a9443f6 756 */
jhonatanll 0:7e562a9443f6 757 uint8_t MFRC522::PICC_HaltA()
jhonatanll 0:7e562a9443f6 758 {
jhonatanll 0:7e562a9443f6 759 uint8_t result;
jhonatanll 0:7e562a9443f6 760 uint8_t buffer[4];
jhonatanll 0:7e562a9443f6 761
jhonatanll 0:7e562a9443f6 762 // Build command buffer
jhonatanll 0:7e562a9443f6 763 buffer[0] = PICC_CMD_HLTA;
jhonatanll 0:7e562a9443f6 764 buffer[1] = 0;
jhonatanll 0:7e562a9443f6 765
jhonatanll 0:7e562a9443f6 766 // Calculate CRC_A
jhonatanll 0:7e562a9443f6 767 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
jhonatanll 0:7e562a9443f6 768 if (result == STATUS_OK)
jhonatanll 0:7e562a9443f6 769 {
jhonatanll 0:7e562a9443f6 770 // Send the command.
jhonatanll 0:7e562a9443f6 771 // The standard says:
jhonatanll 0:7e562a9443f6 772 // If the PICC responds with any modulation during a period of 1 ms after the end of the frame containing the
jhonatanll 0:7e562a9443f6 773 // HLTA command, this response shall be interpreted as 'not acknowledge'.
jhonatanll 0:7e562a9443f6 774 // We interpret that this way: Only STATUS_TIMEOUT is an success.
jhonatanll 0:7e562a9443f6 775 result = PCD_TransceiveData(buffer, sizeof(buffer), NULL, 0);
jhonatanll 0:7e562a9443f6 776 if (result == STATUS_TIMEOUT)
jhonatanll 0:7e562a9443f6 777 {
jhonatanll 0:7e562a9443f6 778 result = STATUS_OK;
jhonatanll 0:7e562a9443f6 779 }
jhonatanll 0:7e562a9443f6 780 else if (result == STATUS_OK)
jhonatanll 0:7e562a9443f6 781 { // That is ironically NOT ok in this case ;-)
jhonatanll 0:7e562a9443f6 782 result = STATUS_ERROR;
jhonatanll 0:7e562a9443f6 783 }
jhonatanll 0:7e562a9443f6 784 }
jhonatanll 0:7e562a9443f6 785
jhonatanll 0:7e562a9443f6 786 return result;
jhonatanll 0:7e562a9443f6 787 } // End PICC_HaltA()
jhonatanll 0:7e562a9443f6 788
jhonatanll 0:7e562a9443f6 789
jhonatanll 0:7e562a9443f6 790 /////////////////////////////////////////////////////////////////////////////////////
jhonatanll 0:7e562a9443f6 791 // Functions for communicating with MIFARE PICCs
jhonatanll 0:7e562a9443f6 792 /////////////////////////////////////////////////////////////////////////////////////
jhonatanll 0:7e562a9443f6 793
jhonatanll 0:7e562a9443f6 794 /*
jhonatanll 0:7e562a9443f6 795 * Executes the MFRC522 MFAuthent command.
jhonatanll 0:7e562a9443f6 796 */
jhonatanll 0:7e562a9443f6 797 uint8_t MFRC522::PCD_Authenticate(uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid)
jhonatanll 0:7e562a9443f6 798 {
jhonatanll 0:7e562a9443f6 799 uint8_t i, waitIRq = 0x10; // IdleIRq
jhonatanll 0:7e562a9443f6 800
jhonatanll 0:7e562a9443f6 801 // Build command buffer
jhonatanll 0:7e562a9443f6 802 uint8_t sendData[12];
jhonatanll 0:7e562a9443f6 803 sendData[0] = command;
jhonatanll 0:7e562a9443f6 804 sendData[1] = blockAddr;
jhonatanll 0:7e562a9443f6 805
jhonatanll 0:7e562a9443f6 806 for (i = 0; i < MF_KEY_SIZE; i++)
jhonatanll 0:7e562a9443f6 807 { // 6 key bytes
jhonatanll 0:7e562a9443f6 808 sendData[2+i] = key->keyByte[i];
jhonatanll 0:7e562a9443f6 809 }
jhonatanll 0:7e562a9443f6 810
jhonatanll 0:7e562a9443f6 811 for (i = 0; i < 4; i++)
jhonatanll 0:7e562a9443f6 812 { // The first 4 bytes of the UID
jhonatanll 0:7e562a9443f6 813 sendData[8+i] = uid->uidByte[i];
jhonatanll 0:7e562a9443f6 814 }
jhonatanll 0:7e562a9443f6 815
jhonatanll 0:7e562a9443f6 816 // Start the authentication.
jhonatanll 0:7e562a9443f6 817 return PCD_CommunicateWithPICC(PCD_MFAuthent, waitIRq, &sendData[0], sizeof(sendData));
jhonatanll 0:7e562a9443f6 818 } // End PCD_Authenticate()
jhonatanll 0:7e562a9443f6 819
jhonatanll 0:7e562a9443f6 820 /*
jhonatanll 0:7e562a9443f6 821 * Used to exit the PCD from its authenticated state.
jhonatanll 0:7e562a9443f6 822 * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
jhonatanll 0:7e562a9443f6 823 */
jhonatanll 0:7e562a9443f6 824 void MFRC522::PCD_StopCrypto1()
jhonatanll 0:7e562a9443f6 825 {
jhonatanll 0:7e562a9443f6 826 // Clear MFCrypto1On bit
jhonatanll 0:7e562a9443f6 827 PCD_ClrRegisterBits(Status2Reg, 0x08); // Status2Reg[7..0] bits are: TempSensClear I2CForceHS reserved reserved MFCrypto1On ModemState[2:0]
jhonatanll 0:7e562a9443f6 828 } // End PCD_StopCrypto1()
jhonatanll 0:7e562a9443f6 829
jhonatanll 0:7e562a9443f6 830 /*
jhonatanll 0:7e562a9443f6 831 * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
jhonatanll 0:7e562a9443f6 832 */
jhonatanll 0:7e562a9443f6 833 uint8_t MFRC522::MIFARE_Read(uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize)
jhonatanll 0:7e562a9443f6 834 {
jhonatanll 0:7e562a9443f6 835 uint8_t result = STATUS_NO_ROOM;
jhonatanll 0:7e562a9443f6 836
jhonatanll 0:7e562a9443f6 837 // Sanity check
jhonatanll 0:7e562a9443f6 838 if ((buffer == NULL) || (*bufferSize < 18))
jhonatanll 0:7e562a9443f6 839 {
jhonatanll 0:7e562a9443f6 840 return result;
jhonatanll 0:7e562a9443f6 841 }
jhonatanll 0:7e562a9443f6 842
jhonatanll 0:7e562a9443f6 843 // Build command buffer
jhonatanll 0:7e562a9443f6 844 buffer[0] = PICC_CMD_MF_READ;
jhonatanll 0:7e562a9443f6 845 buffer[1] = blockAddr;
jhonatanll 0:7e562a9443f6 846
jhonatanll 0:7e562a9443f6 847 // Calculate CRC_A
jhonatanll 0:7e562a9443f6 848 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
jhonatanll 0:7e562a9443f6 849 if (result != STATUS_OK)
jhonatanll 0:7e562a9443f6 850 {
jhonatanll 0:7e562a9443f6 851 return result;
jhonatanll 0:7e562a9443f6 852 }
jhonatanll 0:7e562a9443f6 853
jhonatanll 0:7e562a9443f6 854 // Transmit the buffer and receive the response, validate CRC_A.
jhonatanll 0:7e562a9443f6 855 return PCD_TransceiveData(buffer, 4, buffer, bufferSize, NULL, 0, true);
jhonatanll 0:7e562a9443f6 856 } // End MIFARE_Read()
jhonatanll 0:7e562a9443f6 857
jhonatanll 0:7e562a9443f6 858 /*
jhonatanll 0:7e562a9443f6 859 * Writes 16 bytes to the active PICC.
jhonatanll 0:7e562a9443f6 860 */
jhonatanll 0:7e562a9443f6 861 uint8_t MFRC522::MIFARE_Write(uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize)
jhonatanll 0:7e562a9443f6 862 {
jhonatanll 0:7e562a9443f6 863 uint8_t result;
jhonatanll 0:7e562a9443f6 864
jhonatanll 0:7e562a9443f6 865 // Sanity check
jhonatanll 0:7e562a9443f6 866 if (buffer == NULL || bufferSize < 16)
jhonatanll 0:7e562a9443f6 867 {
jhonatanll 0:7e562a9443f6 868 return STATUS_INVALID;
jhonatanll 0:7e562a9443f6 869 }
jhonatanll 0:7e562a9443f6 870
jhonatanll 0:7e562a9443f6 871 // Mifare Classic protocol requires two communications to perform a write.
jhonatanll 0:7e562a9443f6 872 // Step 1: Tell the PICC we want to write to block blockAddr.
jhonatanll 0:7e562a9443f6 873 uint8_t cmdBuffer[2];
jhonatanll 0:7e562a9443f6 874 cmdBuffer[0] = PICC_CMD_MF_WRITE;
jhonatanll 0:7e562a9443f6 875 cmdBuffer[1] = blockAddr;
jhonatanll 0:7e562a9443f6 876 // Adds CRC_A and checks that the response is MF_ACK.
jhonatanll 0:7e562a9443f6 877 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
jhonatanll 0:7e562a9443f6 878 if (result != STATUS_OK)
jhonatanll 0:7e562a9443f6 879 {
jhonatanll 0:7e562a9443f6 880 return result;
jhonatanll 0:7e562a9443f6 881 }
jhonatanll 0:7e562a9443f6 882
jhonatanll 0:7e562a9443f6 883 // Step 2: Transfer the data
jhonatanll 0:7e562a9443f6 884 // Adds CRC_A and checks that the response is MF_ACK.
jhonatanll 0:7e562a9443f6 885 result = PCD_MIFARE_Transceive(buffer, bufferSize);
jhonatanll 0:7e562a9443f6 886 if (result != STATUS_OK)
jhonatanll 0:7e562a9443f6 887 {
jhonatanll 0:7e562a9443f6 888 return result;
jhonatanll 0:7e562a9443f6 889 }
jhonatanll 0:7e562a9443f6 890
jhonatanll 0:7e562a9443f6 891 return STATUS_OK;
jhonatanll 0:7e562a9443f6 892 } // End MIFARE_Write()
jhonatanll 0:7e562a9443f6 893
jhonatanll 0:7e562a9443f6 894 /*
jhonatanll 0:7e562a9443f6 895 * Writes a 4 byte page to the active MIFARE Ultralight PICC.
jhonatanll 0:7e562a9443f6 896 */
jhonatanll 0:7e562a9443f6 897 uint8_t MFRC522::MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize)
jhonatanll 0:7e562a9443f6 898 {
jhonatanll 0:7e562a9443f6 899 uint8_t result;
jhonatanll 0:7e562a9443f6 900
jhonatanll 0:7e562a9443f6 901 // Sanity check
jhonatanll 0:7e562a9443f6 902 if (buffer == NULL || bufferSize < 4)
jhonatanll 0:7e562a9443f6 903 {
jhonatanll 0:7e562a9443f6 904 return STATUS_INVALID;
jhonatanll 0:7e562a9443f6 905 }
jhonatanll 0:7e562a9443f6 906
jhonatanll 0:7e562a9443f6 907 // Build commmand buffer
jhonatanll 0:7e562a9443f6 908 uint8_t cmdBuffer[6];
jhonatanll 0:7e562a9443f6 909 cmdBuffer[0] = PICC_CMD_UL_WRITE;
jhonatanll 0:7e562a9443f6 910 cmdBuffer[1] = page;
jhonatanll 0:7e562a9443f6 911 memcpy(&cmdBuffer[2], buffer, 4);
jhonatanll 0:7e562a9443f6 912
jhonatanll 0:7e562a9443f6 913 // Perform the write
jhonatanll 0:7e562a9443f6 914 result = PCD_MIFARE_Transceive(cmdBuffer, 6); // Adds CRC_A and checks that the response is MF_ACK.
jhonatanll 0:7e562a9443f6 915 if (result != STATUS_OK)
jhonatanll 0:7e562a9443f6 916 {
jhonatanll 0:7e562a9443f6 917 return result;
jhonatanll 0:7e562a9443f6 918 }
jhonatanll 0:7e562a9443f6 919
jhonatanll 0:7e562a9443f6 920 return STATUS_OK;
jhonatanll 0:7e562a9443f6 921 } // End MIFARE_Ultralight_Write()
jhonatanll 0:7e562a9443f6 922
jhonatanll 0:7e562a9443f6 923 /*
jhonatanll 0:7e562a9443f6 924 * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
jhonatanll 0:7e562a9443f6 925 */
jhonatanll 0:7e562a9443f6 926 uint8_t MFRC522::MIFARE_Decrement(uint8_t blockAddr, uint32_t delta)
jhonatanll 0:7e562a9443f6 927 {
jhonatanll 0:7e562a9443f6 928 return MIFARE_TwoStepHelper(PICC_CMD_MF_DECREMENT, blockAddr, delta);
jhonatanll 0:7e562a9443f6 929 } // End MIFARE_Decrement()
jhonatanll 0:7e562a9443f6 930
jhonatanll 0:7e562a9443f6 931 /*
jhonatanll 0:7e562a9443f6 932 * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
jhonatanll 0:7e562a9443f6 933 */
jhonatanll 0:7e562a9443f6 934 uint8_t MFRC522::MIFARE_Increment(uint8_t blockAddr, uint32_t delta)
jhonatanll 0:7e562a9443f6 935 {
jhonatanll 0:7e562a9443f6 936 return MIFARE_TwoStepHelper(PICC_CMD_MF_INCREMENT, blockAddr, delta);
jhonatanll 0:7e562a9443f6 937 } // End MIFARE_Increment()
jhonatanll 0:7e562a9443f6 938
jhonatanll 0:7e562a9443f6 939 /**
jhonatanll 0:7e562a9443f6 940 * MIFARE Restore copies the value of the addressed block into a volatile memory.
jhonatanll 0:7e562a9443f6 941 */
jhonatanll 0:7e562a9443f6 942 uint8_t MFRC522::MIFARE_Restore(uint8_t blockAddr)
jhonatanll 0:7e562a9443f6 943 {
jhonatanll 0:7e562a9443f6 944 // The datasheet describes Restore as a two step operation, but does not explain what data to transfer in step 2.
jhonatanll 0:7e562a9443f6 945 // Doing only a single step does not work, so I chose to transfer 0L in step two.
jhonatanll 0:7e562a9443f6 946 return MIFARE_TwoStepHelper(PICC_CMD_MF_RESTORE, blockAddr, 0L);
jhonatanll 0:7e562a9443f6 947 } // End MIFARE_Restore()
jhonatanll 0:7e562a9443f6 948
jhonatanll 0:7e562a9443f6 949 /*
jhonatanll 0:7e562a9443f6 950 * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
jhonatanll 0:7e562a9443f6 951 */
jhonatanll 0:7e562a9443f6 952 uint8_t MFRC522::MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data)
jhonatanll 0:7e562a9443f6 953 {
jhonatanll 0:7e562a9443f6 954 uint8_t result;
jhonatanll 0:7e562a9443f6 955 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
jhonatanll 0:7e562a9443f6 956
jhonatanll 0:7e562a9443f6 957 // Step 1: Tell the PICC the command and block address
jhonatanll 0:7e562a9443f6 958 cmdBuffer[0] = command;
jhonatanll 0:7e562a9443f6 959 cmdBuffer[1] = blockAddr;
jhonatanll 0:7e562a9443f6 960
jhonatanll 0:7e562a9443f6 961 // Adds CRC_A and checks that the response is MF_ACK.
jhonatanll 0:7e562a9443f6 962 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
jhonatanll 0:7e562a9443f6 963 if (result != STATUS_OK)
jhonatanll 0:7e562a9443f6 964 {
jhonatanll 0:7e562a9443f6 965 return result;
jhonatanll 0:7e562a9443f6 966 }
jhonatanll 0:7e562a9443f6 967
jhonatanll 0:7e562a9443f6 968 // Step 2: Transfer the data
jhonatanll 0:7e562a9443f6 969 // Adds CRC_A and accept timeout as success.
jhonatanll 0:7e562a9443f6 970 result = PCD_MIFARE_Transceive((uint8_t *) &data, 4, true);
jhonatanll 0:7e562a9443f6 971 if (result != STATUS_OK)
jhonatanll 0:7e562a9443f6 972 {
jhonatanll 0:7e562a9443f6 973 return result;
jhonatanll 0:7e562a9443f6 974 }
jhonatanll 0:7e562a9443f6 975
jhonatanll 0:7e562a9443f6 976 return STATUS_OK;
jhonatanll 0:7e562a9443f6 977 } // End MIFARE_TwoStepHelper()
jhonatanll 0:7e562a9443f6 978
jhonatanll 0:7e562a9443f6 979 /*
jhonatanll 0:7e562a9443f6 980 * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
jhonatanll 0:7e562a9443f6 981 */
jhonatanll 0:7e562a9443f6 982 uint8_t MFRC522::MIFARE_Transfer(uint8_t blockAddr)
jhonatanll 0:7e562a9443f6 983 {
jhonatanll 0:7e562a9443f6 984 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
jhonatanll 0:7e562a9443f6 985
jhonatanll 0:7e562a9443f6 986 // Tell the PICC we want to transfer the result into block blockAddr.
jhonatanll 0:7e562a9443f6 987 cmdBuffer[0] = PICC_CMD_MF_TRANSFER;
jhonatanll 0:7e562a9443f6 988 cmdBuffer[1] = blockAddr;
jhonatanll 0:7e562a9443f6 989
jhonatanll 0:7e562a9443f6 990 // Adds CRC_A and checks that the response is MF_ACK.
jhonatanll 0:7e562a9443f6 991 return PCD_MIFARE_Transceive(cmdBuffer, 2);
jhonatanll 0:7e562a9443f6 992 } // End MIFARE_Transfer()
jhonatanll 0:7e562a9443f6 993
jhonatanll 0:7e562a9443f6 994
jhonatanll 0:7e562a9443f6 995 /////////////////////////////////////////////////////////////////////////////////////
jhonatanll 0:7e562a9443f6 996 // Support functions
jhonatanll 0:7e562a9443f6 997 /////////////////////////////////////////////////////////////////////////////////////
jhonatanll 0:7e562a9443f6 998
jhonatanll 0:7e562a9443f6 999 /*
jhonatanll 0:7e562a9443f6 1000 * Wrapper for MIFARE protocol communication.
jhonatanll 0:7e562a9443f6 1001 * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
jhonatanll 0:7e562a9443f6 1002 */
jhonatanll 0:7e562a9443f6 1003 uint8_t MFRC522::PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout)
jhonatanll 0:7e562a9443f6 1004 {
jhonatanll 0:7e562a9443f6 1005 uint8_t result;
jhonatanll 0:7e562a9443f6 1006 uint8_t cmdBuffer[18]; // We need room for 16 bytes data and 2 bytes CRC_A.
jhonatanll 0:7e562a9443f6 1007
jhonatanll 0:7e562a9443f6 1008 // Sanity check
jhonatanll 0:7e562a9443f6 1009 if (sendData == NULL || sendLen > 16)
jhonatanll 0:7e562a9443f6 1010 {
jhonatanll 0:7e562a9443f6 1011 return STATUS_INVALID;
jhonatanll 0:7e562a9443f6 1012 }
jhonatanll 0:7e562a9443f6 1013
jhonatanll 0:7e562a9443f6 1014 // Copy sendData[] to cmdBuffer[] and add CRC_A
jhonatanll 0:7e562a9443f6 1015 memcpy(cmdBuffer, sendData, sendLen);
jhonatanll 0:7e562a9443f6 1016 result = PCD_CalculateCRC(cmdBuffer, sendLen, &cmdBuffer[sendLen]);
jhonatanll 0:7e562a9443f6 1017 if (result != STATUS_OK)
jhonatanll 0:7e562a9443f6 1018 {
jhonatanll 0:7e562a9443f6 1019 return result;
jhonatanll 0:7e562a9443f6 1020 }
jhonatanll 0:7e562a9443f6 1021
jhonatanll 0:7e562a9443f6 1022 sendLen += 2;
jhonatanll 0:7e562a9443f6 1023
jhonatanll 0:7e562a9443f6 1024 // Transceive the data, store the reply in cmdBuffer[]
jhonatanll 0:7e562a9443f6 1025 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
jhonatanll 0:7e562a9443f6 1026 uint8_t cmdBufferSize = sizeof(cmdBuffer);
jhonatanll 0:7e562a9443f6 1027 uint8_t validBits = 0;
jhonatanll 0:7e562a9443f6 1028 result = PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, cmdBuffer, sendLen, cmdBuffer, &cmdBufferSize, &validBits);
jhonatanll 0:7e562a9443f6 1029 if (acceptTimeout && result == STATUS_TIMEOUT)
jhonatanll 0:7e562a9443f6 1030 {
jhonatanll 0:7e562a9443f6 1031 return STATUS_OK;
jhonatanll 0:7e562a9443f6 1032 }
jhonatanll 0:7e562a9443f6 1033
jhonatanll 0:7e562a9443f6 1034 if (result != STATUS_OK)
jhonatanll 0:7e562a9443f6 1035 {
jhonatanll 0:7e562a9443f6 1036 return result;
jhonatanll 0:7e562a9443f6 1037 }
jhonatanll 0:7e562a9443f6 1038
jhonatanll 0:7e562a9443f6 1039 // The PICC must reply with a 4 bit ACK
jhonatanll 0:7e562a9443f6 1040 if (cmdBufferSize != 1 || validBits != 4)
jhonatanll 0:7e562a9443f6 1041 {
jhonatanll 0:7e562a9443f6 1042 return STATUS_ERROR;
jhonatanll 0:7e562a9443f6 1043 }
jhonatanll 0:7e562a9443f6 1044
jhonatanll 0:7e562a9443f6 1045 if (cmdBuffer[0] != MF_ACK)
jhonatanll 0:7e562a9443f6 1046 {
jhonatanll 0:7e562a9443f6 1047 return STATUS_MIFARE_NACK;
jhonatanll 0:7e562a9443f6 1048 }
jhonatanll 0:7e562a9443f6 1049
jhonatanll 0:7e562a9443f6 1050 return STATUS_OK;
jhonatanll 0:7e562a9443f6 1051 } // End PCD_MIFARE_Transceive()
jhonatanll 0:7e562a9443f6 1052
jhonatanll 0:7e562a9443f6 1053
jhonatanll 0:7e562a9443f6 1054 /*
jhonatanll 0:7e562a9443f6 1055 * Translates the SAK (Select Acknowledge) to a PICC type.
jhonatanll 0:7e562a9443f6 1056 */
jhonatanll 0:7e562a9443f6 1057 uint8_t MFRC522::PICC_GetType(uint8_t sak)
jhonatanll 0:7e562a9443f6 1058 {
jhonatanll 0:7e562a9443f6 1059 uint8_t retType = PICC_TYPE_UNKNOWN;
jhonatanll 0:7e562a9443f6 1060
jhonatanll 0:7e562a9443f6 1061 if (sak & 0x04)
jhonatanll 0:7e562a9443f6 1062 { // UID not complete
jhonatanll 0:7e562a9443f6 1063 retType = PICC_TYPE_NOT_COMPLETE;
jhonatanll 0:7e562a9443f6 1064 }
jhonatanll 0:7e562a9443f6 1065 else
jhonatanll 0:7e562a9443f6 1066 {
jhonatanll 0:7e562a9443f6 1067 switch (sak)
jhonatanll 0:7e562a9443f6 1068 {
jhonatanll 0:7e562a9443f6 1069 case 0x09: retType = PICC_TYPE_MIFARE_MINI; break;
jhonatanll 0:7e562a9443f6 1070 case 0x08: retType = PICC_TYPE_MIFARE_1K; break;
jhonatanll 0:7e562a9443f6 1071 case 0x18: retType = PICC_TYPE_MIFARE_4K; break;
jhonatanll 0:7e562a9443f6 1072 case 0x00: retType = PICC_TYPE_MIFARE_UL; break;
jhonatanll 0:7e562a9443f6 1073 case 0x10:
jhonatanll 0:7e562a9443f6 1074 case 0x11: retType = PICC_TYPE_MIFARE_PLUS; break;
jhonatanll 0:7e562a9443f6 1075 case 0x01: retType = PICC_TYPE_TNP3XXX; break;
jhonatanll 0:7e562a9443f6 1076 default:
jhonatanll 0:7e562a9443f6 1077 if (sak & 0x20)
jhonatanll 0:7e562a9443f6 1078 {
jhonatanll 0:7e562a9443f6 1079 retType = PICC_TYPE_ISO_14443_4;
jhonatanll 0:7e562a9443f6 1080 }
jhonatanll 0:7e562a9443f6 1081 else if (sak & 0x40)
jhonatanll 0:7e562a9443f6 1082 {
jhonatanll 0:7e562a9443f6 1083 retType = PICC_TYPE_ISO_18092;
jhonatanll 0:7e562a9443f6 1084 }
jhonatanll 0:7e562a9443f6 1085 break;
jhonatanll 0:7e562a9443f6 1086 }
jhonatanll 0:7e562a9443f6 1087 }
jhonatanll 0:7e562a9443f6 1088
jhonatanll 0:7e562a9443f6 1089 return (retType);
jhonatanll 0:7e562a9443f6 1090 } // End PICC_GetType()
jhonatanll 0:7e562a9443f6 1091
jhonatanll 0:7e562a9443f6 1092 /*
jhonatanll 0:7e562a9443f6 1093 * Returns a string pointer to the PICC type name.
jhonatanll 0:7e562a9443f6 1094 */
jhonatanll 0:7e562a9443f6 1095 char* MFRC522::PICC_GetTypeName(uint8_t piccType)
jhonatanll 0:7e562a9443f6 1096 {
jhonatanll 0:7e562a9443f6 1097 if(piccType == PICC_TYPE_NOT_COMPLETE)
jhonatanll 0:7e562a9443f6 1098 {
jhonatanll 0:7e562a9443f6 1099 piccType = MFRC522_MaxPICCs - 1;
jhonatanll 0:7e562a9443f6 1100 }
jhonatanll 0:7e562a9443f6 1101
jhonatanll 0:7e562a9443f6 1102 return((char *) _TypeNamePICC[piccType]);
jhonatanll 0:7e562a9443f6 1103 } // End PICC_GetTypeName()
jhonatanll 0:7e562a9443f6 1104
jhonatanll 0:7e562a9443f6 1105 /*
jhonatanll 0:7e562a9443f6 1106 * Returns a string pointer to a status code name.
jhonatanll 0:7e562a9443f6 1107 */
jhonatanll 0:7e562a9443f6 1108 char* MFRC522::GetStatusCodeName(uint8_t code)
jhonatanll 0:7e562a9443f6 1109 {
jhonatanll 0:7e562a9443f6 1110 return((char *) _ErrorMessage[code]);
jhonatanll 0:7e562a9443f6 1111 } // End GetStatusCodeName()
jhonatanll 0:7e562a9443f6 1112
jhonatanll 0:7e562a9443f6 1113 /*
jhonatanll 0:7e562a9443f6 1114 * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
jhonatanll 0:7e562a9443f6 1115 */
jhonatanll 0:7e562a9443f6 1116 void MFRC522::MIFARE_SetAccessBits(uint8_t *accessBitBuffer,
jhonatanll 0:7e562a9443f6 1117 uint8_t g0,
jhonatanll 0:7e562a9443f6 1118 uint8_t g1,
jhonatanll 0:7e562a9443f6 1119 uint8_t g2,
jhonatanll 0:7e562a9443f6 1120 uint8_t g3)
jhonatanll 0:7e562a9443f6 1121 {
jhonatanll 0:7e562a9443f6 1122 uint8_t c1 = ((g3 & 4) << 1) | ((g2 & 4) << 0) | ((g1 & 4) >> 1) | ((g0 & 4) >> 2);
jhonatanll 0:7e562a9443f6 1123 uint8_t c2 = ((g3 & 2) << 2) | ((g2 & 2) << 1) | ((g1 & 2) << 0) | ((g0 & 2) >> 1);
jhonatanll 0:7e562a9443f6 1124 uint8_t c3 = ((g3 & 1) << 3) | ((g2 & 1) << 2) | ((g1 & 1) << 1) | ((g0 & 1) << 0);
jhonatanll 0:7e562a9443f6 1125
jhonatanll 0:7e562a9443f6 1126 accessBitBuffer[0] = (~c2 & 0xF) << 4 | (~c1 & 0xF);
jhonatanll 0:7e562a9443f6 1127 accessBitBuffer[1] = c1 << 4 | (~c3 & 0xF);
jhonatanll 0:7e562a9443f6 1128 accessBitBuffer[2] = c3 << 4 | c2;
jhonatanll 0:7e562a9443f6 1129 } // End MIFARE_SetAccessBits()
jhonatanll 0:7e562a9443f6 1130
jhonatanll 0:7e562a9443f6 1131 /////////////////////////////////////////////////////////////////////////////////////
jhonatanll 0:7e562a9443f6 1132 // Convenience functions - does not add extra functionality
jhonatanll 0:7e562a9443f6 1133 /////////////////////////////////////////////////////////////////////////////////////
jhonatanll 0:7e562a9443f6 1134
jhonatanll 0:7e562a9443f6 1135 /*
jhonatanll 0:7e562a9443f6 1136 * Returns true if a PICC responds to PICC_CMD_REQA.
jhonatanll 0:7e562a9443f6 1137 * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
jhonatanll 0:7e562a9443f6 1138 */
jhonatanll 0:7e562a9443f6 1139 bool MFRC522::PICC_IsNewCardPresent(void)
jhonatanll 0:7e562a9443f6 1140 {
jhonatanll 0:7e562a9443f6 1141 uint8_t bufferATQA[2];
jhonatanll 0:7e562a9443f6 1142 uint8_t bufferSize = sizeof(bufferATQA);
jhonatanll 0:7e562a9443f6 1143 uint8_t result = PICC_RequestA(bufferATQA, &bufferSize);
jhonatanll 0:7e562a9443f6 1144 return ((result == STATUS_OK) || (result == STATUS_COLLISION));
jhonatanll 0:7e562a9443f6 1145 } // End PICC_IsNewCardPresent()
jhonatanll 0:7e562a9443f6 1146
jhonatanll 0:7e562a9443f6 1147 /*
jhonatanll 0:7e562a9443f6 1148 * Simple wrapper around PICC_Select.
jhonatanll 0:7e562a9443f6 1149 */
jhonatanll 0:7e562a9443f6 1150 bool MFRC522::PICC_ReadCardSerial(void)
jhonatanll 0:7e562a9443f6 1151 {
jhonatanll 0:7e562a9443f6 1152 uint8_t result = PICC_Select(&uid);
jhonatanll 0:7e562a9443f6 1153 return (result == STATUS_OK);
jhonatanll 0:7e562a9443f6 1154 } // End PICC_ReadCardSerial()