I2C_EEPROM - I2C_EEPROM

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I2C_EEPROM

TARGET_NUCLEO_F072RB/stm32f072xb.h@0:ac8863619623, 2015-08-13 (annotated)

Committer:: jhon309
Date:: Thu Aug 13 00:23:16 2015 +0000
Revision:: 0:ac8863619623

I2C

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User	Revision	Line number	New contents of line
jhon309	0:ac8863619623	1	/**
jhon309	0:ac8863619623	2	******************************************************************************
jhon309	0:ac8863619623	3	* @file stm32f072xb.h
jhon309	0:ac8863619623	4	* @author MCD Application Team
jhon309	0:ac8863619623	5	* @version V2.2.0
jhon309	0:ac8863619623	6	* @date 05-December-2014
jhon309	0:ac8863619623	7	* @brief CMSIS STM32F072x8/STM32F072xB devices Peripheral Access Layer Header File.
jhon309	0:ac8863619623	8	*
jhon309	0:ac8863619623	9	* This file contains:
jhon309	0:ac8863619623	10	* - Data structures and the address mapping for all peripherals
jhon309	0:ac8863619623	11	* - Peripheral's registers declarations and bits definition
jhon309	0:ac8863619623	12	* - Macros to access peripherals registers hardware
jhon309	0:ac8863619623	13	*
jhon309	0:ac8863619623	14	******************************************************************************
jhon309	0:ac8863619623	15	* @attention
jhon309	0:ac8863619623	16	*
jhon309	0:ac8863619623	17	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
jhon309	0:ac8863619623	18	*
jhon309	0:ac8863619623	19	* Redistribution and use in source and binary forms, with or without modification,
jhon309	0:ac8863619623	20	* are permitted provided that the following conditions are met:
jhon309	0:ac8863619623	21	* 1. Redistributions of source code must retain the above copyright notice,
jhon309	0:ac8863619623	22	* this list of conditions and the following disclaimer.
jhon309	0:ac8863619623	23	* 2. Redistributions in binary form must reproduce the above copyright notice,
jhon309	0:ac8863619623	24	* this list of conditions and the following disclaimer in the documentation
jhon309	0:ac8863619623	25	* and/or other materials provided with the distribution.
jhon309	0:ac8863619623	26	* 3. Neither the name of STMicroelectronics nor the names of its contributors
jhon309	0:ac8863619623	27	* may be used to endorse or promote products derived from this software
jhon309	0:ac8863619623	28	* without specific prior written permission.
jhon309	0:ac8863619623	29	*
jhon309	0:ac8863619623	30	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jhon309	0:ac8863619623	31	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jhon309	0:ac8863619623	32	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
jhon309	0:ac8863619623	33	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
jhon309	0:ac8863619623	34	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
jhon309	0:ac8863619623	35	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
jhon309	0:ac8863619623	36	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
jhon309	0:ac8863619623	37	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
jhon309	0:ac8863619623	38	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
jhon309	0:ac8863619623	39	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
jhon309	0:ac8863619623	40	*
jhon309	0:ac8863619623	41	******************************************************************************
jhon309	0:ac8863619623	42	*/
jhon309	0:ac8863619623	43
jhon309	0:ac8863619623	44	/** @addtogroup CMSIS_Device
jhon309	0:ac8863619623	45	* @{
jhon309	0:ac8863619623	46	*/
jhon309	0:ac8863619623	47
jhon309	0:ac8863619623	48	/** @addtogroup stm32f072xb
jhon309	0:ac8863619623	49	* @{
jhon309	0:ac8863619623	50	*/
jhon309	0:ac8863619623	51
jhon309	0:ac8863619623	52	#ifndef __STM32F072xB_H
jhon309	0:ac8863619623	53	#define __STM32F072xB_H
jhon309	0:ac8863619623	54
jhon309	0:ac8863619623	55	#ifdef __cplusplus
jhon309	0:ac8863619623	56	extern "C" {
jhon309	0:ac8863619623	57	#endif /* __cplusplus */
jhon309	0:ac8863619623	58
jhon309	0:ac8863619623	59	/** @addtogroup Configuration_section_for_CMSIS
jhon309	0:ac8863619623	60	* @{
jhon309	0:ac8863619623	61	*/
jhon309	0:ac8863619623	62
jhon309	0:ac8863619623	63	/**
jhon309	0:ac8863619623	64	* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
jhon309	0:ac8863619623	65	*/
jhon309	0:ac8863619623	66	#define __CM0_REV 0 /!< Core Revision r0p0 /
jhon309	0:ac8863619623	67	#define __MPU_PRESENT 0 /!< STM32F0xx do not provide MPU /
jhon309	0:ac8863619623	68	#define __NVIC_PRIO_BITS 2 /!< STM32F0xx uses 2 Bits for the Priority Levels /
jhon309	0:ac8863619623	69	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
jhon309	0:ac8863619623	70
jhon309	0:ac8863619623	71	/**
jhon309	0:ac8863619623	72	* @}
jhon309	0:ac8863619623	73	*/
jhon309	0:ac8863619623	74
jhon309	0:ac8863619623	75	/** @addtogroup Peripheral_interrupt_number_definition
jhon309	0:ac8863619623	76	* @{
jhon309	0:ac8863619623	77	*/
jhon309	0:ac8863619623	78
jhon309	0:ac8863619623	79	/**
jhon309	0:ac8863619623	80	* @brief STM32F072x8/STM32F072xB device Interrupt Number Definition
jhon309	0:ac8863619623	81	*/
jhon309	0:ac8863619623	82	typedef enum
jhon309	0:ac8863619623	83	{
jhon309	0:ac8863619623	84	/**** Cortex-M0 Processor Exceptions Numbers ************************************************************/
jhon309	0:ac8863619623	85	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
jhon309	0:ac8863619623	86	HardFault_IRQn = -13, /!< 3 Cortex-M0 Hard Fault Interrupt /
jhon309	0:ac8863619623	87	SVC_IRQn = -5, /!< 11 Cortex-M0 SV Call Interrupt /
jhon309	0:ac8863619623	88	PendSV_IRQn = -2, /!< 14 Cortex-M0 Pend SV Interrupt /
jhon309	0:ac8863619623	89	SysTick_IRQn = -1, /!< 15 Cortex-M0 System Tick Interrupt /
jhon309	0:ac8863619623	90
jhon309	0:ac8863619623	91	/**** STM32F072x8/STM32F072xB specific Interrupt Numbers ************************************************/
jhon309	0:ac8863619623	92	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
jhon309	0:ac8863619623	93	PVD_VDDIO2_IRQn = 1, /!< PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31 /
jhon309	0:ac8863619623	94	RTC_IRQn = 2, /!< RTC Interrupt through EXTI Lines 17, 19 and 20 /
jhon309	0:ac8863619623	95	FLASH_IRQn = 3, /!< FLASH global Interrupt /
jhon309	0:ac8863619623	96	RCC_CRS_IRQn = 4, /!< RCC & CRS global Interrupts /
jhon309	0:ac8863619623	97	EXTI0_1_IRQn = 5, /!< EXTI Line 0 and 1 Interrupts /
jhon309	0:ac8863619623	98	EXTI2_3_IRQn = 6, /!< EXTI Line 2 and 3 Interrupts /
jhon309	0:ac8863619623	99	EXTI4_15_IRQn = 7, /!< EXTI Line 4 to 15 Interrupts /
jhon309	0:ac8863619623	100	TSC_IRQn = 8, /!< Touch Sensing Controller Interrupts /
jhon309	0:ac8863619623	101	DMA1_Channel1_IRQn = 9, /!< DMA1 Channel 1 Interrupt /
jhon309	0:ac8863619623	102	DMA1_Channel2_3_IRQn = 10, /!< DMA1 Channel 2 and Channel 3 Interrupts /
jhon309	0:ac8863619623	103	DMA1_Channel4_5_6_7_IRQn = 11, /!< DMA1 Channel 4 to Channel 7 Interrupts /
jhon309	0:ac8863619623	104	ADC1_COMP_IRQn = 12, /!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 /
jhon309	0:ac8863619623	105	TIM1_BRK_UP_TRG_COM_IRQn = 13, /!< TIM1 Break, Update, Trigger and Commutation Interrupts /
jhon309	0:ac8863619623	106	TIM1_CC_IRQn = 14, /!< TIM1 Capture Compare Interrupt /
jhon309	0:ac8863619623	107	TIM2_IRQn = 15, /!< TIM2 global Interrupt /
jhon309	0:ac8863619623	108	TIM3_IRQn = 16, /!< TIM3 global Interrupt /
jhon309	0:ac8863619623	109	TIM6_DAC_IRQn = 17, /!< TIM6 global and DAC channel underrun error Interrupts /
jhon309	0:ac8863619623	110	TIM7_IRQn = 18, /!< TIM7 global Interrupt /
jhon309	0:ac8863619623	111	TIM14_IRQn = 19, /!< TIM14 global Interrupt /
jhon309	0:ac8863619623	112	TIM15_IRQn = 20, /!< TIM15 global Interrupt /
jhon309	0:ac8863619623	113	TIM16_IRQn = 21, /!< TIM16 global Interrupt /
jhon309	0:ac8863619623	114	TIM17_IRQn = 22, /!< TIM17 global Interrupt /
jhon309	0:ac8863619623	115	I2C1_IRQn = 23, /!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) /
jhon309	0:ac8863619623	116	I2C2_IRQn = 24, /!< I2C2 Event Interrupt /
jhon309	0:ac8863619623	117	SPI1_IRQn = 25, /!< SPI1 global Interrupt /
jhon309	0:ac8863619623	118	SPI2_IRQn = 26, /!< SPI2 global Interrupt /
jhon309	0:ac8863619623	119	USART1_IRQn = 27, /!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) /
jhon309	0:ac8863619623	120	USART2_IRQn = 28, /!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) /
jhon309	0:ac8863619623	121	USART3_4_IRQn = 29, /!< USART3 and USART4 global Interrupts /
jhon309	0:ac8863619623	122	CEC_CAN_IRQn = 30, /!< CEC and CAN global Interrupts & EXTI Line27 Interrupt /
jhon309	0:ac8863619623	123	USB_IRQn = 31 /!< USB global Interrupts & EXTI Line18 Interrupt /
jhon309	0:ac8863619623	124	} IRQn_Type;
jhon309	0:ac8863619623	125
jhon309	0:ac8863619623	126	/**
jhon309	0:ac8863619623	127	* @}
jhon309	0:ac8863619623	128	*/
jhon309	0:ac8863619623	129
jhon309	0:ac8863619623	130	#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
jhon309	0:ac8863619623	131	#include "system_stm32f0xx.h" /* STM32F0xx System Header */
jhon309	0:ac8863619623	132	#include <stdint.h>
jhon309	0:ac8863619623	133
jhon309	0:ac8863619623	134	/** @addtogroup Peripheral_registers_structures
jhon309	0:ac8863619623	135	* @{
jhon309	0:ac8863619623	136	*/
jhon309	0:ac8863619623	137
jhon309	0:ac8863619623	138	/**
jhon309	0:ac8863619623	139	* @brief Analog to Digital Converter
jhon309	0:ac8863619623	140	*/
jhon309	0:ac8863619623	141
jhon309	0:ac8863619623	142	typedef struct
jhon309	0:ac8863619623	143	{
jhon309	0:ac8863619623	144	__IO uint32_t ISR; /!< ADC Interrupt and Status register, Address offset:0x00 /
jhon309	0:ac8863619623	145	__IO uint32_t IER; /!< ADC Interrupt Enable register, Address offset:0x04 /
jhon309	0:ac8863619623	146	__IO uint32_t CR; /!< ADC Control register, Address offset:0x08 /
jhon309	0:ac8863619623	147	__IO uint32_t CFGR1; /!< ADC Configuration register 1, Address offset:0x0C /
jhon309	0:ac8863619623	148	__IO uint32_t CFGR2; /!< ADC Configuration register 2, Address offset:0x10 /
jhon309	0:ac8863619623	149	__IO uint32_t SMPR; /!< ADC Sampling time register, Address offset:0x14 /
jhon309	0:ac8863619623	150	uint32_t RESERVED1; /!< Reserved, 0x18 /
jhon309	0:ac8863619623	151	uint32_t RESERVED2; /!< Reserved, 0x1C /
jhon309	0:ac8863619623	152	__IO uint32_t TR; /!< ADC watchdog threshold register, Address offset:0x20 /
jhon309	0:ac8863619623	153	uint32_t RESERVED3; /!< Reserved, 0x24 /
jhon309	0:ac8863619623	154	__IO uint32_t CHSELR; /!< ADC channel selection register, Address offset:0x28 /
jhon309	0:ac8863619623	155	uint32_t RESERVED4[5]; /!< Reserved, 0x2C /
jhon309	0:ac8863619623	156	__IO uint32_t DR; /!< ADC data register, Address offset:0x40 /
jhon309	0:ac8863619623	157	}ADC_TypeDef;
jhon309	0:ac8863619623	158
jhon309	0:ac8863619623	159	typedef struct
jhon309	0:ac8863619623	160	{
jhon309	0:ac8863619623	161	__IO uint32_t CCR;
jhon309	0:ac8863619623	162	}ADC_Common_TypeDef;
jhon309	0:ac8863619623	163
jhon309	0:ac8863619623	164	/**
jhon309	0:ac8863619623	165	* @brief Controller Area Network TxMailBox
jhon309	0:ac8863619623	166	*/
jhon309	0:ac8863619623	167	typedef struct
jhon309	0:ac8863619623	168	{
jhon309	0:ac8863619623	169	__IO uint32_t TIR; /!< CAN TX mailbox identifier register /
jhon309	0:ac8863619623	170	__IO uint32_t TDTR; /!< CAN mailbox data length control and time stamp register /
jhon309	0:ac8863619623	171	__IO uint32_t TDLR; /!< CAN mailbox data low register /
jhon309	0:ac8863619623	172	__IO uint32_t TDHR; /!< CAN mailbox data high register /
jhon309	0:ac8863619623	173	}CAN_TxMailBox_TypeDef;
jhon309	0:ac8863619623	174
jhon309	0:ac8863619623	175	/**
jhon309	0:ac8863619623	176	* @brief Controller Area Network FIFOMailBox
jhon309	0:ac8863619623	177	*/
jhon309	0:ac8863619623	178	typedef struct
jhon309	0:ac8863619623	179	{
jhon309	0:ac8863619623	180	__IO uint32_t RIR; /!< CAN receive FIFO mailbox identifier register /
jhon309	0:ac8863619623	181	__IO uint32_t RDTR; /!< CAN receive FIFO mailbox data length control and time stamp register /
jhon309	0:ac8863619623	182	__IO uint32_t RDLR; /!< CAN receive FIFO mailbox data low register /
jhon309	0:ac8863619623	183	__IO uint32_t RDHR; /!< CAN receive FIFO mailbox data high register /
jhon309	0:ac8863619623	184	}CAN_FIFOMailBox_TypeDef;
jhon309	0:ac8863619623	185
jhon309	0:ac8863619623	186	/**
jhon309	0:ac8863619623	187	* @brief Controller Area Network FilterRegister
jhon309	0:ac8863619623	188	*/
jhon309	0:ac8863619623	189	typedef struct
jhon309	0:ac8863619623	190	{
jhon309	0:ac8863619623	191	__IO uint32_t FR1; /!< CAN Filter bank register 1 /
jhon309	0:ac8863619623	192	__IO uint32_t FR2; /!< CAN Filter bank register 1 /
jhon309	0:ac8863619623	193	}CAN_FilterRegister_TypeDef;
jhon309	0:ac8863619623	194
jhon309	0:ac8863619623	195	/**
jhon309	0:ac8863619623	196	* @brief Controller Area Network
jhon309	0:ac8863619623	197	*/
jhon309	0:ac8863619623	198	typedef struct
jhon309	0:ac8863619623	199	{
jhon309	0:ac8863619623	200	__IO uint32_t MCR; /!< CAN master control register, Address offset: 0x00 /
jhon309	0:ac8863619623	201	__IO uint32_t MSR; /!< CAN master status register, Address offset: 0x04 /
jhon309	0:ac8863619623	202	__IO uint32_t TSR; /!< CAN transmit status register, Address offset: 0x08 /
jhon309	0:ac8863619623	203	__IO uint32_t RF0R; /!< CAN receive FIFO 0 register, Address offset: 0x0C /
jhon309	0:ac8863619623	204	__IO uint32_t RF1R; /!< CAN receive FIFO 1 register, Address offset: 0x10 /
jhon309	0:ac8863619623	205	__IO uint32_t IER; /!< CAN interrupt enable register, Address offset: 0x14 /
jhon309	0:ac8863619623	206	__IO uint32_t ESR; /!< CAN error status register, Address offset: 0x18 /
jhon309	0:ac8863619623	207	__IO uint32_t BTR; /!< CAN bit timing register, Address offset: 0x1C /
jhon309	0:ac8863619623	208	uint32_t RESERVED0[88]; /!< Reserved, 0x020 - 0x17F /
jhon309	0:ac8863619623	209	CAN_TxMailBox_TypeDef sTxMailBox[3]; /!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC /
jhon309	0:ac8863619623	210	CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC /
jhon309	0:ac8863619623	211	uint32_t RESERVED1[12]; /!< Reserved, 0x1D0 - 0x1FF /
jhon309	0:ac8863619623	212	__IO uint32_t FMR; /!< CAN filter master register, Address offset: 0x200 /
jhon309	0:ac8863619623	213	__IO uint32_t FM1R; /!< CAN filter mode register, Address offset: 0x204 /
jhon309	0:ac8863619623	214	uint32_t RESERVED2; /!< Reserved, 0x208 /
jhon309	0:ac8863619623	215	__IO uint32_t FS1R; /!< CAN filter scale register, Address offset: 0x20C /
jhon309	0:ac8863619623	216	uint32_t RESERVED3; /!< Reserved, 0x210 /
jhon309	0:ac8863619623	217	__IO uint32_t FFA1R; /!< CAN filter FIFO assignment register, Address offset: 0x214 /
jhon309	0:ac8863619623	218	uint32_t RESERVED4; /!< Reserved, 0x218 /
jhon309	0:ac8863619623	219	__IO uint32_t FA1R; /!< CAN filter activation register, Address offset: 0x21C /
jhon309	0:ac8863619623	220	uint32_t RESERVED5[8]; /!< Reserved, 0x220-0x23F /
jhon309	0:ac8863619623	221	CAN_FilterRegister_TypeDef sFilterRegister[28]; /!< CAN Filter Register, Address offset: 0x240-0x31C /
jhon309	0:ac8863619623	222	}CAN_TypeDef;
jhon309	0:ac8863619623	223
jhon309	0:ac8863619623	224	/**
jhon309	0:ac8863619623	225	* @brief HDMI-CEC
jhon309	0:ac8863619623	226	*/
jhon309	0:ac8863619623	227
jhon309	0:ac8863619623	228	typedef struct
jhon309	0:ac8863619623	229	{
jhon309	0:ac8863619623	230	__IO uint32_t CR; /!< CEC control register, Address offset:0x00 /
jhon309	0:ac8863619623	231	__IO uint32_t CFGR; /!< CEC configuration register, Address offset:0x04 /
jhon309	0:ac8863619623	232	__IO uint32_t TXDR; /!< CEC Tx data register , Address offset:0x08 /
jhon309	0:ac8863619623	233	__IO uint32_t RXDR; /!< CEC Rx Data Register, Address offset:0x0C /
jhon309	0:ac8863619623	234	__IO uint32_t ISR; /!< CEC Interrupt and Status Register, Address offset:0x10 /
jhon309	0:ac8863619623	235	__IO uint32_t IER; /!< CEC interrupt enable register, Address offset:0x14 /
jhon309	0:ac8863619623	236	}CEC_TypeDef;
jhon309	0:ac8863619623	237
jhon309	0:ac8863619623	238	/**
jhon309	0:ac8863619623	239	* @brief Comparator
jhon309	0:ac8863619623	240	*/
jhon309	0:ac8863619623	241
jhon309	0:ac8863619623	242	typedef struct
jhon309	0:ac8863619623	243	{
jhon309	0:ac8863619623	244	__IO uint32_t CSR; /!< Comparator 1 & 2 control Status register, Address offset: 0x00 /
jhon309	0:ac8863619623	245	}COMP1_2_TypeDef;
jhon309	0:ac8863619623	246
jhon309	0:ac8863619623	247	typedef struct
jhon309	0:ac8863619623	248	{
jhon309	0:ac8863619623	249	__IO uint16_t CSR; /!< Comparator control Status register, Address offset: 0x00 /
jhon309	0:ac8863619623	250	}COMP_TypeDef;
jhon309	0:ac8863619623	251
jhon309	0:ac8863619623	252	/**
jhon309	0:ac8863619623	253	* @brief CRC calculation unit
jhon309	0:ac8863619623	254	*/
jhon309	0:ac8863619623	255
jhon309	0:ac8863619623	256	typedef struct
jhon309	0:ac8863619623	257	{
jhon309	0:ac8863619623	258	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
jhon309	0:ac8863619623	259	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
jhon309	0:ac8863619623	260	uint8_t RESERVED0; /!< Reserved, 0x05 /
jhon309	0:ac8863619623	261	uint16_t RESERVED1; /!< Reserved, 0x06 /
jhon309	0:ac8863619623	262	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
jhon309	0:ac8863619623	263	uint32_t RESERVED2; /!< Reserved, 0x0C /
jhon309	0:ac8863619623	264	__IO uint32_t INIT; /!< Initial CRC value register, Address offset: 0x10 /
jhon309	0:ac8863619623	265	__IO uint32_t POL; /!< CRC polynomial register, Address offset: 0x14 /
jhon309	0:ac8863619623	266	}CRC_TypeDef;
jhon309	0:ac8863619623	267
jhon309	0:ac8863619623	268	/**
jhon309	0:ac8863619623	269	* @brief Clock Recovery System
jhon309	0:ac8863619623	270	*/
jhon309	0:ac8863619623	271	typedef struct
jhon309	0:ac8863619623	272	{
jhon309	0:ac8863619623	273	__IO uint32_t CR; /!< CRS ccontrol register, Address offset: 0x00 /
jhon309	0:ac8863619623	274	__IO uint32_t CFGR; /!< CRS configuration register, Address offset: 0x04 /
jhon309	0:ac8863619623	275	__IO uint32_t ISR; /!< CRS interrupt and status register, Address offset: 0x08 /
jhon309	0:ac8863619623	276	__IO uint32_t ICR; /!< CRS interrupt flag clear register, Address offset: 0x0C /
jhon309	0:ac8863619623	277	}CRS_TypeDef;
jhon309	0:ac8863619623	278
jhon309	0:ac8863619623	279	/**
jhon309	0:ac8863619623	280	* @brief Digital to Analog Converter
jhon309	0:ac8863619623	281	*/
jhon309	0:ac8863619623	282
jhon309	0:ac8863619623	283	typedef struct
jhon309	0:ac8863619623	284	{
jhon309	0:ac8863619623	285	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
jhon309	0:ac8863619623	286	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
jhon309	0:ac8863619623	287	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
jhon309	0:ac8863619623	288	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
jhon309	0:ac8863619623	289	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
jhon309	0:ac8863619623	290	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
jhon309	0:ac8863619623	291	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
jhon309	0:ac8863619623	292	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
jhon309	0:ac8863619623	293	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
jhon309	0:ac8863619623	294	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
jhon309	0:ac8863619623	295	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
jhon309	0:ac8863619623	296	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
jhon309	0:ac8863619623	297	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
jhon309	0:ac8863619623	298	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
jhon309	0:ac8863619623	299	}DAC_TypeDef;
jhon309	0:ac8863619623	300
jhon309	0:ac8863619623	301	/**
jhon309	0:ac8863619623	302	* @brief Debug MCU
jhon309	0:ac8863619623	303	*/
jhon309	0:ac8863619623	304
jhon309	0:ac8863619623	305	typedef struct
jhon309	0:ac8863619623	306	{
jhon309	0:ac8863619623	307	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
jhon309	0:ac8863619623	308	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
jhon309	0:ac8863619623	309	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
jhon309	0:ac8863619623	310	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
jhon309	0:ac8863619623	311	}DBGMCU_TypeDef;
jhon309	0:ac8863619623	312
jhon309	0:ac8863619623	313	/**
jhon309	0:ac8863619623	314	* @brief DMA Controller
jhon309	0:ac8863619623	315	*/
jhon309	0:ac8863619623	316
jhon309	0:ac8863619623	317	typedef struct
jhon309	0:ac8863619623	318	{
jhon309	0:ac8863619623	319	__IO uint32_t CCR; /!< DMA channel x configuration register /
jhon309	0:ac8863619623	320	__IO uint32_t CNDTR; /!< DMA channel x number of data register /
jhon309	0:ac8863619623	321	__IO uint32_t CPAR; /!< DMA channel x peripheral address register /
jhon309	0:ac8863619623	322	__IO uint32_t CMAR; /!< DMA channel x memory address register /
jhon309	0:ac8863619623	323	}DMA_Channel_TypeDef;
jhon309	0:ac8863619623	324
jhon309	0:ac8863619623	325	typedef struct
jhon309	0:ac8863619623	326	{
jhon309	0:ac8863619623	327	__IO uint32_t ISR; /!< DMA interrupt status register, Address offset: 0x00 /
jhon309	0:ac8863619623	328	__IO uint32_t IFCR; /!< DMA interrupt flag clear register, Address offset: 0x04 /
jhon309	0:ac8863619623	329	}DMA_TypeDef;
jhon309	0:ac8863619623	330
jhon309	0:ac8863619623	331	/**
jhon309	0:ac8863619623	332	* @brief External Interrupt/Event Controller
jhon309	0:ac8863619623	333	*/
jhon309	0:ac8863619623	334
jhon309	0:ac8863619623	335	typedef struct
jhon309	0:ac8863619623	336	{
jhon309	0:ac8863619623	337	__IO uint32_t IMR; /!<EXTI Interrupt mask register, Address offset: 0x00 /
jhon309	0:ac8863619623	338	__IO uint32_t EMR; /!<EXTI Event mask register, Address offset: 0x04 /
jhon309	0:ac8863619623	339	__IO uint32_t RTSR; /!<EXTI Rising trigger selection register , Address offset: 0x08 /
jhon309	0:ac8863619623	340	__IO uint32_t FTSR; /!<EXTI Falling trigger selection register, Address offset: 0x0C /
jhon309	0:ac8863619623	341	__IO uint32_t SWIER; /!<EXTI Software interrupt event register, Address offset: 0x10 /
jhon309	0:ac8863619623	342	__IO uint32_t PR; /!<EXTI Pending register, Address offset: 0x14 /
jhon309	0:ac8863619623	343	}EXTI_TypeDef;
jhon309	0:ac8863619623	344
jhon309	0:ac8863619623	345	/**
jhon309	0:ac8863619623	346	* @brief FLASH Registers
jhon309	0:ac8863619623	347	*/
jhon309	0:ac8863619623	348	typedef struct
jhon309	0:ac8863619623	349	{
jhon309	0:ac8863619623	350	__IO uint32_t ACR; /!<FLASH access control register, Address offset: 0x00 /
jhon309	0:ac8863619623	351	__IO uint32_t KEYR; /!<FLASH key register, Address offset: 0x04 /
jhon309	0:ac8863619623	352	__IO uint32_t OPTKEYR; /!<FLASH OPT key register, Address offset: 0x08 /
jhon309	0:ac8863619623	353	__IO uint32_t SR; /!<FLASH status register, Address offset: 0x0C /
jhon309	0:ac8863619623	354	__IO uint32_t CR; /!<FLASH control register, Address offset: 0x10 /
jhon309	0:ac8863619623	355	__IO uint32_t AR; /!<FLASH address register, Address offset: 0x14 /
jhon309	0:ac8863619623	356	__IO uint32_t RESERVED; /!< Reserved, 0x18 /
jhon309	0:ac8863619623	357	__IO uint32_t OBR; /!<FLASH option bytes register, Address offset: 0x1C /
jhon309	0:ac8863619623	358	__IO uint32_t WRPR; /!<FLASH option bytes register, Address offset: 0x20 /
jhon309	0:ac8863619623	359	}FLASH_TypeDef;
jhon309	0:ac8863619623	360
jhon309	0:ac8863619623	361
jhon309	0:ac8863619623	362	/**
jhon309	0:ac8863619623	363	* @brief Option Bytes Registers
jhon309	0:ac8863619623	364	*/
jhon309	0:ac8863619623	365	typedef struct
jhon309	0:ac8863619623	366	{
jhon309	0:ac8863619623	367	__IO uint16_t RDP; /!< FLASH option byte Read protection, Address offset: 0x00 /
jhon309	0:ac8863619623	368	__IO uint16_t USER; /!< FLASH option byte user options, Address offset: 0x02 /
jhon309	0:ac8863619623	369	__IO uint16_t DATA0; /!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 /
jhon309	0:ac8863619623	370	__IO uint16_t DATA1; /!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 /
jhon309	0:ac8863619623	371	__IO uint16_t WRP0; /!< FLASH option byte write protection 0, Address offset: 0x08 /
jhon309	0:ac8863619623	372	__IO uint16_t WRP1; /!< FLASH option byte write protection 1, Address offset: 0x0A /
jhon309	0:ac8863619623	373	__IO uint16_t WRP2; /!< FLASH option byte write protection 2, Address offset: 0x0C /
jhon309	0:ac8863619623	374	__IO uint16_t WRP3; /!< FLASH option byte write protection 3, Address offset: 0x0E /
jhon309	0:ac8863619623	375	}OB_TypeDef;
jhon309	0:ac8863619623	376
jhon309	0:ac8863619623	377	/**
jhon309	0:ac8863619623	378	* @brief General Purpose I/O
jhon309	0:ac8863619623	379	*/
jhon309	0:ac8863619623	380
jhon309	0:ac8863619623	381	typedef struct
jhon309	0:ac8863619623	382	{
jhon309	0:ac8863619623	383	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
jhon309	0:ac8863619623	384	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
jhon309	0:ac8863619623	385	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
jhon309	0:ac8863619623	386	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
jhon309	0:ac8863619623	387	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
jhon309	0:ac8863619623	388	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
jhon309	0:ac8863619623	389	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x1A /
jhon309	0:ac8863619623	390	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
jhon309	0:ac8863619623	391	__IO uint32_t AFR[2]; /!< GPIO alternate function low register, Address offset: 0x20-0x24 /
jhon309	0:ac8863619623	392	__IO uint32_t BRR; /!< GPIO bit reset register, Address offset: 0x28 /
jhon309	0:ac8863619623	393	}GPIO_TypeDef;
jhon309	0:ac8863619623	394
jhon309	0:ac8863619623	395	/**
jhon309	0:ac8863619623	396	* @brief SysTem Configuration
jhon309	0:ac8863619623	397	*/
jhon309	0:ac8863619623	398
jhon309	0:ac8863619623	399	typedef struct
jhon309	0:ac8863619623	400	{
jhon309	0:ac8863619623	401	__IO uint32_t CFGR1; /!< SYSCFG configuration register 1, Address offset: 0x00 /
jhon309	0:ac8863619623	402	uint32_t RESERVED; /!< Reserved, 0x04 /
jhon309	0:ac8863619623	403	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 /
jhon309	0:ac8863619623	404	__IO uint32_t CFGR2; /!< SYSCFG configuration register 2, Address offset: 0x18 /
jhon309	0:ac8863619623	405	}SYSCFG_TypeDef;
jhon309	0:ac8863619623	406
jhon309	0:ac8863619623	407	/**
jhon309	0:ac8863619623	408	* @brief Inter-integrated Circuit Interface
jhon309	0:ac8863619623	409	*/
jhon309	0:ac8863619623	410
jhon309	0:ac8863619623	411	typedef struct
jhon309	0:ac8863619623	412	{
jhon309	0:ac8863619623	413	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
jhon309	0:ac8863619623	414	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
jhon309	0:ac8863619623	415	__IO uint32_t OAR1; /!< I2C Own address 1 register, Address offset: 0x08 /
jhon309	0:ac8863619623	416	__IO uint32_t OAR2; /!< I2C Own address 2 register, Address offset: 0x0C /
jhon309	0:ac8863619623	417	__IO uint32_t TIMINGR; /!< I2C Timing register, Address offset: 0x10 /
jhon309	0:ac8863619623	418	__IO uint32_t TIMEOUTR; /!< I2C Timeout register, Address offset: 0x14 /
jhon309	0:ac8863619623	419	__IO uint32_t ISR; /!< I2C Interrupt and status register, Address offset: 0x18 /
jhon309	0:ac8863619623	420	__IO uint32_t ICR; /!< I2C Interrupt clear register, Address offset: 0x1C /
jhon309	0:ac8863619623	421	__IO uint32_t PECR; /!< I2C PEC register, Address offset: 0x20 /
jhon309	0:ac8863619623	422	__IO uint32_t RXDR; /!< I2C Receive data register, Address offset: 0x24 /
jhon309	0:ac8863619623	423	__IO uint32_t TXDR; /!< I2C Transmit data register, Address offset: 0x28 /
jhon309	0:ac8863619623	424	}I2C_TypeDef;
jhon309	0:ac8863619623	425
jhon309	0:ac8863619623	426	/**
jhon309	0:ac8863619623	427	* @brief Independent WATCHDOG
jhon309	0:ac8863619623	428	*/
jhon309	0:ac8863619623	429
jhon309	0:ac8863619623	430	typedef struct
jhon309	0:ac8863619623	431	{
jhon309	0:ac8863619623	432	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
jhon309	0:ac8863619623	433	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
jhon309	0:ac8863619623	434	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
jhon309	0:ac8863619623	435	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
jhon309	0:ac8863619623	436	__IO uint32_t WINR; /!< IWDG Window register, Address offset: 0x10 /
jhon309	0:ac8863619623	437	}IWDG_TypeDef;
jhon309	0:ac8863619623	438
jhon309	0:ac8863619623	439	/**
jhon309	0:ac8863619623	440	* @brief Power Control
jhon309	0:ac8863619623	441	*/
jhon309	0:ac8863619623	442
jhon309	0:ac8863619623	443	typedef struct
jhon309	0:ac8863619623	444	{
jhon309	0:ac8863619623	445	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
jhon309	0:ac8863619623	446	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
jhon309	0:ac8863619623	447	}PWR_TypeDef;
jhon309	0:ac8863619623	448
jhon309	0:ac8863619623	449	/**
jhon309	0:ac8863619623	450	* @brief Reset and Clock Control
jhon309	0:ac8863619623	451	*/
jhon309	0:ac8863619623	452	typedef struct
jhon309	0:ac8863619623	453	{
jhon309	0:ac8863619623	454	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
jhon309	0:ac8863619623	455	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x04 /
jhon309	0:ac8863619623	456	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x08 /
jhon309	0:ac8863619623	457	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x0C /
jhon309	0:ac8863619623	458	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x10 /
jhon309	0:ac8863619623	459	__IO uint32_t AHBENR; /!< RCC AHB peripheral clock register, Address offset: 0x14 /
jhon309	0:ac8863619623	460	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x18 /
jhon309	0:ac8863619623	461	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x1C /
jhon309	0:ac8863619623	462	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x20 /
jhon309	0:ac8863619623	463	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x24 /
jhon309	0:ac8863619623	464	__IO uint32_t AHBRSTR; /!< RCC AHB peripheral reset register, Address offset: 0x28 /
jhon309	0:ac8863619623	465	__IO uint32_t CFGR2; /!< RCC clock configuration register 2, Address offset: 0x2C /
jhon309	0:ac8863619623	466	__IO uint32_t CFGR3; /!< RCC clock configuration register 3, Address offset: 0x30 /
jhon309	0:ac8863619623	467	__IO uint32_t CR2; /!< RCC clock control register 2, Address offset: 0x34 /
jhon309	0:ac8863619623	468	}RCC_TypeDef;
jhon309	0:ac8863619623	469
jhon309	0:ac8863619623	470	/**
jhon309	0:ac8863619623	471	* @brief Real-Time Clock
jhon309	0:ac8863619623	472	*/
jhon309	0:ac8863619623	473
jhon309	0:ac8863619623	474	typedef struct
jhon309	0:ac8863619623	475	{
jhon309	0:ac8863619623	476	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
jhon309	0:ac8863619623	477	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
jhon309	0:ac8863619623	478	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
jhon309	0:ac8863619623	479	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
jhon309	0:ac8863619623	480	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
jhon309	0:ac8863619623	481	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
jhon309	0:ac8863619623	482	uint32_t RESERVED1; /!< Reserved, Address offset: 0x18 /
jhon309	0:ac8863619623	483	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
jhon309	0:ac8863619623	484	uint32_t RESERVED2; /!< Reserved, Address offset: 0x20 /
jhon309	0:ac8863619623	485	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
jhon309	0:ac8863619623	486	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
jhon309	0:ac8863619623	487	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
jhon309	0:ac8863619623	488	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
jhon309	0:ac8863619623	489	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
jhon309	0:ac8863619623	490	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
jhon309	0:ac8863619623	491	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
jhon309	0:ac8863619623	492	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
jhon309	0:ac8863619623	493	__IO uint32_t ALRMASSR; /!< RTC alarm A sub second register, Address offset: 0x44 /
jhon309	0:ac8863619623	494	uint32_t RESERVED3; /!< Reserved, Address offset: 0x48 /
jhon309	0:ac8863619623	495	uint32_t RESERVED4; /!< Reserved, Address offset: 0x4C /
jhon309	0:ac8863619623	496	__IO uint32_t BKP0R; /!< RTC backup register 0, Address offset: 0x50 /
jhon309	0:ac8863619623	497	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
jhon309	0:ac8863619623	498	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
jhon309	0:ac8863619623	499	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
jhon309	0:ac8863619623	500	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
jhon309	0:ac8863619623	501	}RTC_TypeDef;
jhon309	0:ac8863619623	502
jhon309	0:ac8863619623	503	/**
jhon309	0:ac8863619623	504	* @brief Serial Peripheral Interface
jhon309	0:ac8863619623	505	*/
jhon309	0:ac8863619623	506
jhon309	0:ac8863619623	507	typedef struct
jhon309	0:ac8863619623	508	{
jhon309	0:ac8863619623	509	__IO uint32_t CR1; /!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 /
jhon309	0:ac8863619623	510	__IO uint32_t CR2; /!< SPI Control register 2, Address offset: 0x04 /
jhon309	0:ac8863619623	511	__IO uint32_t SR; /!< SPI Status register, Address offset: 0x08 /
jhon309	0:ac8863619623	512	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
jhon309	0:ac8863619623	513	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
jhon309	0:ac8863619623	514	__IO uint32_t RXCRCR; /!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 /
jhon309	0:ac8863619623	515	__IO uint32_t TXCRCR; /!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 /
jhon309	0:ac8863619623	516	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
jhon309	0:ac8863619623	517	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
jhon309	0:ac8863619623	518	}SPI_TypeDef;
jhon309	0:ac8863619623	519
jhon309	0:ac8863619623	520	/**
jhon309	0:ac8863619623	521	* @brief TIM
jhon309	0:ac8863619623	522	*/
jhon309	0:ac8863619623	523	typedef struct
jhon309	0:ac8863619623	524	{
jhon309	0:ac8863619623	525	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
jhon309	0:ac8863619623	526	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
jhon309	0:ac8863619623	527	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
jhon309	0:ac8863619623	528	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
jhon309	0:ac8863619623	529	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
jhon309	0:ac8863619623	530	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
jhon309	0:ac8863619623	531	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
jhon309	0:ac8863619623	532	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
jhon309	0:ac8863619623	533	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
jhon309	0:ac8863619623	534	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
jhon309	0:ac8863619623	535	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
jhon309	0:ac8863619623	536	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
jhon309	0:ac8863619623	537	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
jhon309	0:ac8863619623	538	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
jhon309	0:ac8863619623	539	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
jhon309	0:ac8863619623	540	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
jhon309	0:ac8863619623	541	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
jhon309	0:ac8863619623	542	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
jhon309	0:ac8863619623	543	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
jhon309	0:ac8863619623	544	__IO uint32_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
jhon309	0:ac8863619623	545	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
jhon309	0:ac8863619623	546	}TIM_TypeDef;
jhon309	0:ac8863619623	547
jhon309	0:ac8863619623	548	/**
jhon309	0:ac8863619623	549	* @brief Touch Sensing Controller (TSC)
jhon309	0:ac8863619623	550	*/
jhon309	0:ac8863619623	551	typedef struct
jhon309	0:ac8863619623	552	{
jhon309	0:ac8863619623	553	__IO uint32_t CR; /!< TSC control register, Address offset: 0x00 /
jhon309	0:ac8863619623	554	__IO uint32_t IER; /!< TSC interrupt enable register, Address offset: 0x04 /
jhon309	0:ac8863619623	555	__IO uint32_t ICR; /!< TSC interrupt clear register, Address offset: 0x08 /
jhon309	0:ac8863619623	556	__IO uint32_t ISR; /!< TSC interrupt status register, Address offset: 0x0C /
jhon309	0:ac8863619623	557	__IO uint32_t IOHCR; /!< TSC I/O hysteresis control register, Address offset: 0x10 /
jhon309	0:ac8863619623	558	uint32_t RESERVED1; /!< Reserved, Address offset: 0x14 /
jhon309	0:ac8863619623	559	__IO uint32_t IOASCR; /!< TSC I/O analog switch control register, Address offset: 0x18 /
jhon309	0:ac8863619623	560	uint32_t RESERVED2; /!< Reserved, Address offset: 0x1C /
jhon309	0:ac8863619623	561	__IO uint32_t IOSCR; /!< TSC I/O sampling control register, Address offset: 0x20 /
jhon309	0:ac8863619623	562	uint32_t RESERVED3; /!< Reserved, Address offset: 0x24 /
jhon309	0:ac8863619623	563	__IO uint32_t IOCCR; /!< TSC I/O channel control register, Address offset: 0x28 /
jhon309	0:ac8863619623	564	uint32_t RESERVED4; /!< Reserved, Address offset: 0x2C /
jhon309	0:ac8863619623	565	__IO uint32_t IOGCSR; /!< TSC I/O group control status register, Address offset: 0x30 /
jhon309	0:ac8863619623	566	__IO uint32_t IOGXCR[8]; /!< TSC I/O group x counter register, Address offset: 0x34-50 /
jhon309	0:ac8863619623	567	}TSC_TypeDef;
jhon309	0:ac8863619623	568
jhon309	0:ac8863619623	569	/**
jhon309	0:ac8863619623	570	* @brief Universal Synchronous Asynchronous Receiver Transmitter
jhon309	0:ac8863619623	571	*/
jhon309	0:ac8863619623	572
jhon309	0:ac8863619623	573	typedef struct
jhon309	0:ac8863619623	574	{
jhon309	0:ac8863619623	575	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x00 /
jhon309	0:ac8863619623	576	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x04 /
jhon309	0:ac8863619623	577	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x08 /
jhon309	0:ac8863619623	578	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x0C /
jhon309	0:ac8863619623	579	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x10 /
jhon309	0:ac8863619623	580	__IO uint32_t RTOR; /!< USART Receiver Time Out register, Address offset: 0x14 /
jhon309	0:ac8863619623	581	__IO uint32_t RQR; /!< USART Request register, Address offset: 0x18 /
jhon309	0:ac8863619623	582	__IO uint32_t ISR; /!< USART Interrupt and status register, Address offset: 0x1C /
jhon309	0:ac8863619623	583	__IO uint32_t ICR; /!< USART Interrupt flag Clear register, Address offset: 0x20 /
jhon309	0:ac8863619623	584	__IO uint16_t RDR; /!< USART Receive Data register, Address offset: 0x24 /
jhon309	0:ac8863619623	585	uint16_t RESERVED1; /!< Reserved, 0x26 /
jhon309	0:ac8863619623	586	__IO uint16_t TDR; /!< USART Transmit Data register, Address offset: 0x28 /
jhon309	0:ac8863619623	587	uint16_t RESERVED2; /!< Reserved, 0x2A /
jhon309	0:ac8863619623	588	}USART_TypeDef;
jhon309	0:ac8863619623	589
jhon309	0:ac8863619623	590	/**
jhon309	0:ac8863619623	591	* @brief Universal Serial Bus Full Speed Device
jhon309	0:ac8863619623	592	*/
jhon309	0:ac8863619623	593
jhon309	0:ac8863619623	594	typedef struct
jhon309	0:ac8863619623	595	{
jhon309	0:ac8863619623	596	__IO uint16_t EP0R; /!< USB Endpoint 0 register, Address offset: 0x00 /
jhon309	0:ac8863619623	597	__IO uint16_t RESERVED0; /!< Reserved /
jhon309	0:ac8863619623	598	__IO uint16_t EP1R; /!< USB Endpoint 1 register, Address offset: 0x04 /
jhon309	0:ac8863619623	599	__IO uint16_t RESERVED1; /!< Reserved /
jhon309	0:ac8863619623	600	__IO uint16_t EP2R; /!< USB Endpoint 2 register, Address offset: 0x08 /
jhon309	0:ac8863619623	601	__IO uint16_t RESERVED2; /!< Reserved /
jhon309	0:ac8863619623	602	__IO uint16_t EP3R; /!< USB Endpoint 3 register, Address offset: 0x0C /
jhon309	0:ac8863619623	603	__IO uint16_t RESERVED3; /!< Reserved /
jhon309	0:ac8863619623	604	__IO uint16_t EP4R; /!< USB Endpoint 4 register, Address offset: 0x10 /
jhon309	0:ac8863619623	605	__IO uint16_t RESERVED4; /!< Reserved /
jhon309	0:ac8863619623	606	__IO uint16_t EP5R; /!< USB Endpoint 5 register, Address offset: 0x14 /
jhon309	0:ac8863619623	607	__IO uint16_t RESERVED5; /!< Reserved /
jhon309	0:ac8863619623	608	__IO uint16_t EP6R; /!< USB Endpoint 6 register, Address offset: 0x18 /
jhon309	0:ac8863619623	609	__IO uint16_t RESERVED6; /!< Reserved /
jhon309	0:ac8863619623	610	__IO uint16_t EP7R; /!< USB Endpoint 7 register, Address offset: 0x1C /
jhon309	0:ac8863619623	611	__IO uint16_t RESERVED7[17]; /!< Reserved /
jhon309	0:ac8863619623	612	__IO uint16_t CNTR; /!< Control register, Address offset: 0x40 /
jhon309	0:ac8863619623	613	__IO uint16_t RESERVED8; /!< Reserved /
jhon309	0:ac8863619623	614	__IO uint16_t ISTR; /!< Interrupt status register, Address offset: 0x44 /
jhon309	0:ac8863619623	615	__IO uint16_t RESERVED9; /!< Reserved /
jhon309	0:ac8863619623	616	__IO uint16_t FNR; /!< Frame number register, Address offset: 0x48 /
jhon309	0:ac8863619623	617	__IO uint16_t RESERVEDA; /!< Reserved /
jhon309	0:ac8863619623	618	__IO uint16_t DADDR; /!< Device address register, Address offset: 0x4C /
jhon309	0:ac8863619623	619	__IO uint16_t RESERVEDB; /!< Reserved /
jhon309	0:ac8863619623	620	__IO uint16_t BTABLE; /!< Buffer Table address register, Address offset: 0x50 /
jhon309	0:ac8863619623	621	__IO uint16_t RESERVEDC; /!< Reserved /
jhon309	0:ac8863619623	622	__IO uint16_t LPMCSR; /!< LPM Control and Status register, Address offset: 0x54 /
jhon309	0:ac8863619623	623	__IO uint16_t RESERVEDD; /!< Reserved /
jhon309	0:ac8863619623	624	__IO uint16_t BCDR; /!< Battery Charging detector register, Address offset: 0x58 /
jhon309	0:ac8863619623	625	__IO uint16_t RESERVEDE; /!< Reserved /
jhon309	0:ac8863619623	626	}USB_TypeDef;
jhon309	0:ac8863619623	627
jhon309	0:ac8863619623	628	/**
jhon309	0:ac8863619623	629	* @brief Window WATCHDOG
jhon309	0:ac8863619623	630	*/
jhon309	0:ac8863619623	631	typedef struct
jhon309	0:ac8863619623	632	{
jhon309	0:ac8863619623	633	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
jhon309	0:ac8863619623	634	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
jhon309	0:ac8863619623	635	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
jhon309	0:ac8863619623	636	}WWDG_TypeDef;
jhon309	0:ac8863619623	637
jhon309	0:ac8863619623	638	/**
jhon309	0:ac8863619623	639	* @}
jhon309	0:ac8863619623	640	*/
jhon309	0:ac8863619623	641
jhon309	0:ac8863619623	642	/** @addtogroup Peripheral_memory_map
jhon309	0:ac8863619623	643	* @{
jhon309	0:ac8863619623	644	*/
jhon309	0:ac8863619623	645
jhon309	0:ac8863619623	646	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
jhon309	0:ac8863619623	647	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
jhon309	0:ac8863619623	648	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
jhon309	0:ac8863619623	649
jhon309	0:ac8863619623	650	/!< Peripheral memory map /
jhon309	0:ac8863619623	651	#define APBPERIPH_BASE PERIPH_BASE
jhon309	0:ac8863619623	652	#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
jhon309	0:ac8863619623	653	#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
jhon309	0:ac8863619623	654
jhon309	0:ac8863619623	655	#define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
jhon309	0:ac8863619623	656	#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
jhon309	0:ac8863619623	657	#define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
jhon309	0:ac8863619623	658	#define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
jhon309	0:ac8863619623	659	#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
jhon309	0:ac8863619623	660	#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
jhon309	0:ac8863619623	661	#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
jhon309	0:ac8863619623	662	#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
jhon309	0:ac8863619623	663	#define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
jhon309	0:ac8863619623	664	#define USART2_BASE (APBPERIPH_BASE + 0x00004400)
jhon309	0:ac8863619623	665	#define USART3_BASE (APBPERIPH_BASE + 0x00004800)
jhon309	0:ac8863619623	666	#define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
jhon309	0:ac8863619623	667	#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
jhon309	0:ac8863619623	668	#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
jhon309	0:ac8863619623	669	#define USB_BASE (APBPERIPH_BASE + 0x00005C00) /!< USB_IP Peripheral Registers base address /
jhon309	0:ac8863619623	670	#define USB_PMAADDR (APBPERIPH_BASE + 0x00006000) /!< USB_IP Packet Memory Area base address /
jhon309	0:ac8863619623	671	#define CAN_BASE (APBPERIPH_BASE + 0x00006400)
jhon309	0:ac8863619623	672	#define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
jhon309	0:ac8863619623	673	#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
jhon309	0:ac8863619623	674	#define DAC_BASE (APBPERIPH_BASE + 0x00007400)
jhon309	0:ac8863619623	675	#define CEC_BASE (APBPERIPH_BASE + 0x00007800)
jhon309	0:ac8863619623	676
jhon309	0:ac8863619623	677	#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
jhon309	0:ac8863619623	678	#define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
jhon309	0:ac8863619623	679	#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
jhon309	0:ac8863619623	680	#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
jhon309	0:ac8863619623	681	#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
jhon309	0:ac8863619623	682	#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
jhon309	0:ac8863619623	683	#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
jhon309	0:ac8863619623	684	#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
jhon309	0:ac8863619623	685	#define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
jhon309	0:ac8863619623	686	#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
jhon309	0:ac8863619623	687	#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
jhon309	0:ac8863619623	688	#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
jhon309	0:ac8863619623	689
jhon309	0:ac8863619623	690	#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
jhon309	0:ac8863619623	691	#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
jhon309	0:ac8863619623	692	#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
jhon309	0:ac8863619623	693	#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
jhon309	0:ac8863619623	694	#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
jhon309	0:ac8863619623	695	#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
jhon309	0:ac8863619623	696	#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
jhon309	0:ac8863619623	697	#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
jhon309	0:ac8863619623	698
jhon309	0:ac8863619623	699	#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
jhon309	0:ac8863619623	700	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /!< FLASH registers base address /
jhon309	0:ac8863619623	701	#define OB_BASE ((uint32_t)0x1FFFF800) /!< FLASH Option Bytes base address /
jhon309	0:ac8863619623	702	#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
jhon309	0:ac8863619623	703	#define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
jhon309	0:ac8863619623	704
jhon309	0:ac8863619623	705	#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
jhon309	0:ac8863619623	706	#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
jhon309	0:ac8863619623	707	#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
jhon309	0:ac8863619623	708	#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
jhon309	0:ac8863619623	709	#define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
jhon309	0:ac8863619623	710	#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
jhon309	0:ac8863619623	711
jhon309	0:ac8863619623	712	/**
jhon309	0:ac8863619623	713	* @}
jhon309	0:ac8863619623	714	*/
jhon309	0:ac8863619623	715
jhon309	0:ac8863619623	716	/** @addtogroup Peripheral_declaration
jhon309	0:ac8863619623	717	* @{
jhon309	0:ac8863619623	718	*/
jhon309	0:ac8863619623	719
jhon309	0:ac8863619623	720	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
jhon309	0:ac8863619623	721	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
jhon309	0:ac8863619623	722	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
jhon309	0:ac8863619623	723	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
jhon309	0:ac8863619623	724	#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
jhon309	0:ac8863619623	725	#define RTC ((RTC_TypeDef *) RTC_BASE)
jhon309	0:ac8863619623	726	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
jhon309	0:ac8863619623	727	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
jhon309	0:ac8863619623	728	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
jhon309	0:ac8863619623	729	#define USART2 ((USART_TypeDef *) USART2_BASE)
jhon309	0:ac8863619623	730	#define USART3 ((USART_TypeDef *) USART3_BASE)
jhon309	0:ac8863619623	731	#define USART4 ((USART_TypeDef *) USART4_BASE)
jhon309	0:ac8863619623	732	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
jhon309	0:ac8863619623	733	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
jhon309	0:ac8863619623	734	#define CAN ((CAN_TypeDef *) CAN_BASE)
jhon309	0:ac8863619623	735	#define CRS ((CRS_TypeDef *) CRS_BASE)
jhon309	0:ac8863619623	736	#define PWR ((PWR_TypeDef *) PWR_BASE)
jhon309	0:ac8863619623	737	#define DAC ((DAC_TypeDef *) DAC_BASE)
jhon309	0:ac8863619623	738	#define CEC ((CEC_TypeDef *) CEC_BASE)
jhon309	0:ac8863619623	739	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
jhon309	0:ac8863619623	740	#define COMP ((COMP1_2_TypeDef *) COMP_BASE)
jhon309	0:ac8863619623	741	#define COMP1 ((COMP_TypeDef *) COMP_BASE)
jhon309	0:ac8863619623	742	#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000002))
jhon309	0:ac8863619623	743	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
jhon309	0:ac8863619623	744	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
jhon309	0:ac8863619623	745	#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
jhon309	0:ac8863619623	746	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
jhon309	0:ac8863619623	747	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
jhon309	0:ac8863619623	748	#define USART1 ((USART_TypeDef *) USART1_BASE)
jhon309	0:ac8863619623	749	#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
jhon309	0:ac8863619623	750	#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
jhon309	0:ac8863619623	751	#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
jhon309	0:ac8863619623	752	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
jhon309	0:ac8863619623	753	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
jhon309	0:ac8863619623	754	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
jhon309	0:ac8863619623	755	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
jhon309	0:ac8863619623	756	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
jhon309	0:ac8863619623	757	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
jhon309	0:ac8863619623	758	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
jhon309	0:ac8863619623	759	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
jhon309	0:ac8863619623	760	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
jhon309	0:ac8863619623	761	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
jhon309	0:ac8863619623	762	#define OB ((OB_TypeDef *) OB_BASE)
jhon309	0:ac8863619623	763	#define RCC ((RCC_TypeDef *) RCC_BASE)
jhon309	0:ac8863619623	764	#define CRC ((CRC_TypeDef *) CRC_BASE)
jhon309	0:ac8863619623	765	#define TSC ((TSC_TypeDef *) TSC_BASE)
jhon309	0:ac8863619623	766	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
jhon309	0:ac8863619623	767	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
jhon309	0:ac8863619623	768	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
jhon309	0:ac8863619623	769	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
jhon309	0:ac8863619623	770	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
jhon309	0:ac8863619623	771	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
jhon309	0:ac8863619623	772	#define USB ((USB_TypeDef *) USB_BASE)
jhon309	0:ac8863619623	773	/**
jhon309	0:ac8863619623	774	* @}
jhon309	0:ac8863619623	775	*/
jhon309	0:ac8863619623	776
jhon309	0:ac8863619623	777	/** @addtogroup Exported_constants
jhon309	0:ac8863619623	778	* @{
jhon309	0:ac8863619623	779	*/
jhon309	0:ac8863619623	780
jhon309	0:ac8863619623	781	/** @addtogroup Peripheral_Registers_Bits_Definition
jhon309	0:ac8863619623	782	* @{
jhon309	0:ac8863619623	783	*/
jhon309	0:ac8863619623	784
jhon309	0:ac8863619623	785	/******************************************************************************/
jhon309	0:ac8863619623	786	/* Peripheral Registers Bits Definition */
jhon309	0:ac8863619623	787	/******************************************************************************/
jhon309	0:ac8863619623	788	/******************************************************************************/
jhon309	0:ac8863619623	789	/* */
jhon309	0:ac8863619623	790	/* Analog to Digital Converter (ADC) */
jhon309	0:ac8863619623	791	/* */
jhon309	0:ac8863619623	792	/******************************************************************************/
jhon309	0:ac8863619623	793	/****************** Bits definition for ADC_ISR register ****************/
jhon309	0:ac8863619623	794	#define ADC_ISR_AWD ((uint32_t)0x00000080) /!< Analog watchdog flag /
jhon309	0:ac8863619623	795	#define ADC_ISR_OVR ((uint32_t)0x00000010) /!< Overrun flag /
jhon309	0:ac8863619623	796	#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /!< End of Sequence flag /
jhon309	0:ac8863619623	797	#define ADC_ISR_EOC ((uint32_t)0x00000004) /!< End of Conversion /
jhon309	0:ac8863619623	798	#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /!< End of sampling flag /
jhon309	0:ac8863619623	799	#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /!< ADC Ready /
jhon309	0:ac8863619623	800
jhon309	0:ac8863619623	801	/* Old EOSEQ bit definition, maintained for legacy purpose */
jhon309	0:ac8863619623	802	#define ADC_ISR_EOS ADC_ISR_EOSEQ
jhon309	0:ac8863619623	803
jhon309	0:ac8863619623	804	/****************** Bits definition for ADC_IER register ****************/
jhon309	0:ac8863619623	805	#define ADC_IER_AWDIE ((uint32_t)0x00000080) /!< Analog Watchdog interrupt enable /
jhon309	0:ac8863619623	806	#define ADC_IER_OVRIE ((uint32_t)0x00000010) /!< Overrun interrupt enable /
jhon309	0:ac8863619623	807	#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /!< End of Sequence of conversion interrupt enable /
jhon309	0:ac8863619623	808	#define ADC_IER_EOCIE ((uint32_t)0x00000004) /!< End of Conversion interrupt enable /
jhon309	0:ac8863619623	809	#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /!< End of sampling interrupt enable /
jhon309	0:ac8863619623	810	#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /!< ADC Ready interrupt enable /
jhon309	0:ac8863619623	811
jhon309	0:ac8863619623	812	/* Old EOSEQIE bit definition, maintained for legacy purpose */
jhon309	0:ac8863619623	813	#define ADC_IER_EOSIE ADC_IER_EOSEQIE
jhon309	0:ac8863619623	814
jhon309	0:ac8863619623	815	/****************** Bits definition for ADC_CR register *****************/
jhon309	0:ac8863619623	816	#define ADC_CR_ADCAL ((uint32_t)0x80000000) /!< ADC calibration /
jhon309	0:ac8863619623	817	#define ADC_CR_ADSTP ((uint32_t)0x00000010) /!< ADC stop of conversion command /
jhon309	0:ac8863619623	818	#define ADC_CR_ADSTART ((uint32_t)0x00000004) /!< ADC start of conversion /
jhon309	0:ac8863619623	819	#define ADC_CR_ADDIS ((uint32_t)0x00000002) /!< ADC disable command /
jhon309	0:ac8863619623	820	#define ADC_CR_ADEN ((uint32_t)0x00000001) /!< ADC enable control /
jhon309	0:ac8863619623	821
jhon309	0:ac8863619623	822	/***************** Bits definition for ADC_CFGR1 register ***************/
jhon309	0:ac8863619623	823	#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /!< AWDCH[4:0] bits (Analog watchdog channel select bits) /
jhon309	0:ac8863619623	824	#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /!< Bit 0 /
jhon309	0:ac8863619623	825	#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /!< Bit 1 /
jhon309	0:ac8863619623	826	#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /!< Bit 2 /
jhon309	0:ac8863619623	827	#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /!< Bit 3 /
jhon309	0:ac8863619623	828	#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /!< Bit 4 /
jhon309	0:ac8863619623	829	#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /!< Analog watchdog enable on regular channels /
jhon309	0:ac8863619623	830	#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /!< Enable the watchdog on a single channel or on all channels /
jhon309	0:ac8863619623	831	#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /!< Discontinuous mode on regular channels /
jhon309	0:ac8863619623	832	#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /!< ADC auto power off /
jhon309	0:ac8863619623	833	#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /!< ADC wait conversion mode /
jhon309	0:ac8863619623	834	#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /!< Continuous Conversion /
jhon309	0:ac8863619623	835	#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /!< Overrun mode /
jhon309	0:ac8863619623	836	#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) /
jhon309	0:ac8863619623	837	#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /!< Bit 0 /
jhon309	0:ac8863619623	838	#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /!< Bit 1 /
jhon309	0:ac8863619623	839	#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /!< EXTSEL[2:0] bits (External Event Select for regular group) /
jhon309	0:ac8863619623	840	#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /!< Bit 0 /
jhon309	0:ac8863619623	841	#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /!< Bit 1 /
jhon309	0:ac8863619623	842	#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /!< Bit 2 /
jhon309	0:ac8863619623	843	#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /!< Data Alignment /
jhon309	0:ac8863619623	844	#define ADC_CFGR1_RES ((uint32_t)0x00000018) /!< RES[1:0] bits (Resolution) /
jhon309	0:ac8863619623	845	#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /!< Bit 0 /
jhon309	0:ac8863619623	846	#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /!< Bit 1 /
jhon309	0:ac8863619623	847	#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /!< Sequence scan direction /
jhon309	0:ac8863619623	848	#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /!< Direct memory access configuration /
jhon309	0:ac8863619623	849	#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /!< Direct memory access enable /
jhon309	0:ac8863619623	850
jhon309	0:ac8863619623	851	/* Old WAIT bit definition, maintained for legacy purpose */
jhon309	0:ac8863619623	852	#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
jhon309	0:ac8863619623	853
jhon309	0:ac8863619623	854	/***************** Bits definition for ADC_CFGR2 register ***************/
jhon309	0:ac8863619623	855	#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /!< ADC clock mode /
jhon309	0:ac8863619623	856	#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /!< ADC clocked by PCLK div4 /
jhon309	0:ac8863619623	857	#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /!< ADC clocked by PCLK div2 /
jhon309	0:ac8863619623	858
jhon309	0:ac8863619623	859	/* Old bit definition, maintained for legacy purpose */
jhon309	0:ac8863619623	860	#define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /!< ADC clocked by PCLK div4 /
jhon309	0:ac8863619623	861	#define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /!< ADC clocked by PCLK div2 /
jhon309	0:ac8863619623	862
jhon309	0:ac8863619623	863	/**************** Bit definition for ADC_SMPR register ******************/
jhon309	0:ac8863619623	864	#define ADC_SMPR_SMP ((uint32_t)0x00000007) /!< SMP[2:0] bits (Sampling time selection) /
jhon309	0:ac8863619623	865	#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /!< Bit 0 /
jhon309	0:ac8863619623	866	#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /!< Bit 1 /
jhon309	0:ac8863619623	867	#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /!< Bit 2 /
jhon309	0:ac8863619623	868
jhon309	0:ac8863619623	869	/* Old bit definition, maintained for legacy purpose */
jhon309	0:ac8863619623	870	#define ADC_SMPR1_SMPR ADC_SMPR_SMP /!< SMP[2:0] bits (Sampling time selection) /
jhon309	0:ac8863619623	871	#define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /!< Bit 0 /
jhon309	0:ac8863619623	872	#define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /!< Bit 1 /
jhon309	0:ac8863619623	873	#define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /!< Bit 2 /
jhon309	0:ac8863619623	874
jhon309	0:ac8863619623	875	/***************** Bit definition for ADC_TR register ******************/
jhon309	0:ac8863619623	876	#define ADC_TR_HT ((uint32_t)0x0FFF0000) /!< Analog watchdog high threshold /
jhon309	0:ac8863619623	877	#define ADC_TR_LT ((uint32_t)0x00000FFF) /!< Analog watchdog low threshold /
jhon309	0:ac8863619623	878
jhon309	0:ac8863619623	879	/* Old bit definition, maintained for legacy purpose */
jhon309	0:ac8863619623	880	#define ADC_HTR_HT ADC_TR_HT /!< Analog watchdog high threshold /
jhon309	0:ac8863619623	881	#define ADC_LTR_LT ADC_TR_LT /!< Analog watchdog low threshold /
jhon309	0:ac8863619623	882
jhon309	0:ac8863619623	883	/**************** Bit definition for ADC_CHSELR register ****************/
jhon309	0:ac8863619623	884	#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /!< Channel 18 selection /
jhon309	0:ac8863619623	885	#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /!< Channel 17 selection /
jhon309	0:ac8863619623	886	#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /!< Channel 16 selection /
jhon309	0:ac8863619623	887	#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /!< Channel 15 selection /
jhon309	0:ac8863619623	888	#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /!< Channel 14 selection /
jhon309	0:ac8863619623	889	#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /!< Channel 13 selection /
jhon309	0:ac8863619623	890	#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /!< Channel 12 selection /
jhon309	0:ac8863619623	891	#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /!< Channel 11 selection /
jhon309	0:ac8863619623	892	#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /!< Channel 10 selection /
jhon309	0:ac8863619623	893	#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /!< Channel 9 selection /
jhon309	0:ac8863619623	894	#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /!< Channel 8 selection /
jhon309	0:ac8863619623	895	#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /!< Channel 7 selection /
jhon309	0:ac8863619623	896	#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /!< Channel 6 selection /
jhon309	0:ac8863619623	897	#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /!< Channel 5 selection /
jhon309	0:ac8863619623	898	#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /!< Channel 4 selection /
jhon309	0:ac8863619623	899	#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /!< Channel 3 selection /
jhon309	0:ac8863619623	900	#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /!< Channel 2 selection /
jhon309	0:ac8863619623	901	#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /!< Channel 1 selection /
jhon309	0:ac8863619623	902	#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /!< Channel 0 selection /
jhon309	0:ac8863619623	903
jhon309	0:ac8863619623	904	/****************** Bit definition for ADC_DR register ******************/
jhon309	0:ac8863619623	905	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!< Regular data /
jhon309	0:ac8863619623	906
jhon309	0:ac8863619623	907	/***************** Bit definition for ADC_CCR register ******************/
jhon309	0:ac8863619623	908	#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /!< Voltage battery enable /
jhon309	0:ac8863619623	909	#define ADC_CCR_TSEN ((uint32_t)0x00800000) /!< Tempurature sensore enable /
jhon309	0:ac8863619623	910	#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /!< Vrefint enable /
jhon309	0:ac8863619623	911
jhon309	0:ac8863619623	912	/******************************************************************************/
jhon309	0:ac8863619623	913	/* */
jhon309	0:ac8863619623	914	/* Controller Area Network (CAN ) */
jhon309	0:ac8863619623	915	/* */
jhon309	0:ac8863619623	916	/******************************************************************************/
jhon309	0:ac8863619623	917	/!<CAN control and status registers /
jhon309	0:ac8863619623	918	/***************** Bit definition for CAN_MCR register ******************/
jhon309	0:ac8863619623	919	#define CAN_MCR_INRQ ((uint32_t)0x00000001) /!<Initialization Request /
jhon309	0:ac8863619623	920	#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /!<Sleep Mode Request /
jhon309	0:ac8863619623	921	#define CAN_MCR_TXFP ((uint32_t)0x00000004) /!<Transmit FIFO Priority /
jhon309	0:ac8863619623	922	#define CAN_MCR_RFLM ((uint32_t)0x00000008) /!<Receive FIFO Locked Mode /
jhon309	0:ac8863619623	923	#define CAN_MCR_NART ((uint32_t)0x00000010) /!<No Automatic Retransmission /
jhon309	0:ac8863619623	924	#define CAN_MCR_AWUM ((uint32_t)0x00000020) /!<Automatic Wakeup Mode /
jhon309	0:ac8863619623	925	#define CAN_MCR_ABOM ((uint32_t)0x00000040) /!<Automatic Bus-Off Management /
jhon309	0:ac8863619623	926	#define CAN_MCR_TTCM ((uint32_t)0x00000080) /!<Time Triggered Communication Mode /
jhon309	0:ac8863619623	927	#define CAN_MCR_RESET ((uint32_t)0x00008000) /!<bxCAN software master reset /
jhon309	0:ac8863619623	928
jhon309	0:ac8863619623	929	/***************** Bit definition for CAN_MSR register ******************/
jhon309	0:ac8863619623	930	#define CAN_MSR_INAK ((uint32_t)0x00000001) /!<Initialization Acknowledge /
jhon309	0:ac8863619623	931	#define CAN_MSR_SLAK ((uint32_t)0x00000002) /!<Sleep Acknowledge /
jhon309	0:ac8863619623	932	#define CAN_MSR_ERRI ((uint32_t)0x00000004) /!<Error Interrupt /
jhon309	0:ac8863619623	933	#define CAN_MSR_WKUI ((uint32_t)0x00000008) /!<Wakeup Interrupt /
jhon309	0:ac8863619623	934	#define CAN_MSR_SLAKI ((uint32_t)0x00000010) /!<Sleep Acknowledge Interrupt /
jhon309	0:ac8863619623	935	#define CAN_MSR_TXM ((uint32_t)0x00000100) /!<Transmit Mode /
jhon309	0:ac8863619623	936	#define CAN_MSR_RXM ((uint32_t)0x00000200) /!<Receive Mode /
jhon309	0:ac8863619623	937	#define CAN_MSR_SAMP ((uint32_t)0x00000400) /!<Last Sample Point /
jhon309	0:ac8863619623	938	#define CAN_MSR_RX ((uint32_t)0x00000800) /!<CAN Rx Signal /
jhon309	0:ac8863619623	939
jhon309	0:ac8863619623	940	/***************** Bit definition for CAN_TSR register ******************/
jhon309	0:ac8863619623	941	#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /!<Request Completed Mailbox0 /
jhon309	0:ac8863619623	942	#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /!<Transmission OK of Mailbox0 /
jhon309	0:ac8863619623	943	#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /!<Arbitration Lost for Mailbox0 /
jhon309	0:ac8863619623	944	#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /!<Transmission Error of Mailbox0 /
jhon309	0:ac8863619623	945	#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /!<Abort Request for Mailbox0 /
jhon309	0:ac8863619623	946	#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /!<Request Completed Mailbox1 /
jhon309	0:ac8863619623	947	#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /!<Transmission OK of Mailbox1 /
jhon309	0:ac8863619623	948	#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /!<Arbitration Lost for Mailbox1 /
jhon309	0:ac8863619623	949	#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /!<Transmission Error of Mailbox1 /
jhon309	0:ac8863619623	950	#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /!<Abort Request for Mailbox 1 /
jhon309	0:ac8863619623	951	#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /!<Request Completed Mailbox2 /
jhon309	0:ac8863619623	952	#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /!<Transmission OK of Mailbox 2 /
jhon309	0:ac8863619623	953	#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /!<Arbitration Lost for mailbox 2 /
jhon309	0:ac8863619623	954	#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /!<Transmission Error of Mailbox 2 /
jhon309	0:ac8863619623	955	#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /!<Abort Request for Mailbox 2 /
jhon309	0:ac8863619623	956	#define CAN_TSR_CODE ((uint32_t)0x03000000) /!<Mailbox Code /
jhon309	0:ac8863619623	957
jhon309	0:ac8863619623	958	#define CAN_TSR_TME ((uint32_t)0x1C000000) /!<TME[2:0] bits /
jhon309	0:ac8863619623	959	#define CAN_TSR_TME0 ((uint32_t)0x04000000) /!<Transmit Mailbox 0 Empty /
jhon309	0:ac8863619623	960	#define CAN_TSR_TME1 ((uint32_t)0x08000000) /!<Transmit Mailbox 1 Empty /
jhon309	0:ac8863619623	961	#define CAN_TSR_TME2 ((uint32_t)0x10000000) /!<Transmit Mailbox 2 Empty /
jhon309	0:ac8863619623	962
jhon309	0:ac8863619623	963	#define CAN_TSR_LOW ((uint32_t)0xE0000000) /!<LOW[2:0] bits /
jhon309	0:ac8863619623	964	#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /!<Lowest Priority Flag for Mailbox 0 /
jhon309	0:ac8863619623	965	#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /!<Lowest Priority Flag for Mailbox 1 /
jhon309	0:ac8863619623	966	#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /!<Lowest Priority Flag for Mailbox 2 /
jhon309	0:ac8863619623	967
jhon309	0:ac8863619623	968	/***************** Bit definition for CAN_RF0R register *****************/
jhon309	0:ac8863619623	969	#define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /!<FIFO 0 Message Pending /
jhon309	0:ac8863619623	970	#define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /!<FIFO 0 Full /
jhon309	0:ac8863619623	971	#define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /!<FIFO 0 Overrun /
jhon309	0:ac8863619623	972	#define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /!<Release FIFO 0 Output Mailbox /
jhon309	0:ac8863619623	973
jhon309	0:ac8863619623	974	/***************** Bit definition for CAN_RF1R register *****************/
jhon309	0:ac8863619623	975	#define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /!<FIFO 1 Message Pending /
jhon309	0:ac8863619623	976	#define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /!<FIFO 1 Full /
jhon309	0:ac8863619623	977	#define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /!<FIFO 1 Overrun /
jhon309	0:ac8863619623	978	#define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /!<Release FIFO 1 Output Mailbox /
jhon309	0:ac8863619623	979
jhon309	0:ac8863619623	980	/****************** Bit definition for CAN_IER register *****************/
jhon309	0:ac8863619623	981	#define CAN_IER_TMEIE ((uint32_t)0x00000001) /!<Transmit Mailbox Empty Interrupt Enable /
jhon309	0:ac8863619623	982	#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /!<FIFO Message Pending Interrupt Enable /
jhon309	0:ac8863619623	983	#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /!<FIFO Full Interrupt Enable /
jhon309	0:ac8863619623	984	#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /!<FIFO Overrun Interrupt Enable /
jhon309	0:ac8863619623	985	#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /!<FIFO Message Pending Interrupt Enable /
jhon309	0:ac8863619623	986	#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /!<FIFO Full Interrupt Enable /
jhon309	0:ac8863619623	987	#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /!<FIFO Overrun Interrupt Enable /
jhon309	0:ac8863619623	988	#define CAN_IER_EWGIE ((uint32_t)0x00000100) /!<Error Warning Interrupt Enable /
jhon309	0:ac8863619623	989	#define CAN_IER_EPVIE ((uint32_t)0x00000200) /!<Error Passive Interrupt Enable /
jhon309	0:ac8863619623	990	#define CAN_IER_BOFIE ((uint32_t)0x00000400) /!<Bus-Off Interrupt Enable /
jhon309	0:ac8863619623	991	#define CAN_IER_LECIE ((uint32_t)0x00000800) /!<Last Error Code Interrupt Enable /
jhon309	0:ac8863619623	992	#define CAN_IER_ERRIE ((uint32_t)0x00008000) /!<Error Interrupt Enable /
jhon309	0:ac8863619623	993	#define CAN_IER_WKUIE ((uint32_t)0x00010000) /!<Wakeup Interrupt Enable /
jhon309	0:ac8863619623	994	#define CAN_IER_SLKIE ((uint32_t)0x00020000) /!<Sleep Interrupt Enable /
jhon309	0:ac8863619623	995
jhon309	0:ac8863619623	996	/****************** Bit definition for CAN_ESR register *****************/
jhon309	0:ac8863619623	997	#define CAN_ESR_EWGF ((uint32_t)0x00000001) /!<Error Warning Flag /
jhon309	0:ac8863619623	998	#define CAN_ESR_EPVF ((uint32_t)0x00000002) /!<Error Passive Flag /
jhon309	0:ac8863619623	999	#define CAN_ESR_BOFF ((uint32_t)0x00000004) /!<Bus-Off Flag /
jhon309	0:ac8863619623	1000
jhon309	0:ac8863619623	1001	#define CAN_ESR_LEC ((uint32_t)0x00000070) /!<LEC[2:0] bits (Last Error Code) /
jhon309	0:ac8863619623	1002	#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /!<Bit 0 /
jhon309	0:ac8863619623	1003	#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /!<Bit 1 /
jhon309	0:ac8863619623	1004	#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /!<Bit 2 /
jhon309	0:ac8863619623	1005
jhon309	0:ac8863619623	1006	#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /!<Least significant byte of the 9-bit Transmit Error Counter /
jhon309	0:ac8863619623	1007	#define CAN_ESR_REC ((uint32_t)0xFF000000) /!<Receive Error Counter /
jhon309	0:ac8863619623	1008
jhon309	0:ac8863619623	1009	/***************** Bit definition for CAN_BTR register ******************/
jhon309	0:ac8863619623	1010	#define CAN_BTR_BRP ((uint32_t)0x000003FF) /!<Baud Rate Prescaler /
jhon309	0:ac8863619623	1011	#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /!<Time Segment 1 /
jhon309	0:ac8863619623	1012	#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /!<Time Segment 1 (Bit 0) /
jhon309	0:ac8863619623	1013	#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /!<Time Segment 1 (Bit 1) /
jhon309	0:ac8863619623	1014	#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /!<Time Segment 1 (Bit 2) /
jhon309	0:ac8863619623	1015	#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /!<Time Segment 1 (Bit 3) /
jhon309	0:ac8863619623	1016	#define CAN_BTR_TS2 ((uint32_t)0x00700000) /!<Time Segment 2 /
jhon309	0:ac8863619623	1017	#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /!<Time Segment 2 (Bit 0) /
jhon309	0:ac8863619623	1018	#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /!<Time Segment 2 (Bit 1) /
jhon309	0:ac8863619623	1019	#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /!<Time Segment 2 (Bit 2) /
jhon309	0:ac8863619623	1020	#define CAN_BTR_SJW ((uint32_t)0x03000000) /!<Resynchronization Jump Width /
jhon309	0:ac8863619623	1021	#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /!<Resynchronization Jump Width (Bit 0) /
jhon309	0:ac8863619623	1022	#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /!<Resynchronization Jump Width (Bit 1) /
jhon309	0:ac8863619623	1023	#define CAN_BTR_LBKM ((uint32_t)0x40000000) /!<Loop Back Mode (Debug) /
jhon309	0:ac8863619623	1024	#define CAN_BTR_SILM ((uint32_t)0x80000000) /!<Silent Mode /
jhon309	0:ac8863619623	1025
jhon309	0:ac8863619623	1026	/!<Mailbox registers /
jhon309	0:ac8863619623	1027	/**************** Bit definition for CAN_TI0R register ******************/
jhon309	0:ac8863619623	1028	#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
jhon309	0:ac8863619623	1029	#define CAN_TI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
jhon309	0:ac8863619623	1030	#define CAN_TI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
jhon309	0:ac8863619623	1031	#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
jhon309	0:ac8863619623	1032	#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
jhon309	0:ac8863619623	1033
jhon309	0:ac8863619623	1034	/**************** Bit definition for CAN_TDT0R register *****************/
jhon309	0:ac8863619623	1035	#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
jhon309	0:ac8863619623	1036	#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
jhon309	0:ac8863619623	1037	#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
jhon309	0:ac8863619623	1038
jhon309	0:ac8863619623	1039	/**************** Bit definition for CAN_TDL0R register *****************/
jhon309	0:ac8863619623	1040	#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
jhon309	0:ac8863619623	1041	#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
jhon309	0:ac8863619623	1042	#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
jhon309	0:ac8863619623	1043	#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
jhon309	0:ac8863619623	1044
jhon309	0:ac8863619623	1045	/**************** Bit definition for CAN_TDH0R register *****************/
jhon309	0:ac8863619623	1046	#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
jhon309	0:ac8863619623	1047	#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
jhon309	0:ac8863619623	1048	#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
jhon309	0:ac8863619623	1049	#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
jhon309	0:ac8863619623	1050
jhon309	0:ac8863619623	1051	/***************** Bit definition for CAN_TI1R register *****************/
jhon309	0:ac8863619623	1052	#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
jhon309	0:ac8863619623	1053	#define CAN_TI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
jhon309	0:ac8863619623	1054	#define CAN_TI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
jhon309	0:ac8863619623	1055	#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
jhon309	0:ac8863619623	1056	#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
jhon309	0:ac8863619623	1057
jhon309	0:ac8863619623	1058	/***************** Bit definition for CAN_TDT1R register ****************/
jhon309	0:ac8863619623	1059	#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
jhon309	0:ac8863619623	1060	#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
jhon309	0:ac8863619623	1061	#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
jhon309	0:ac8863619623	1062
jhon309	0:ac8863619623	1063	/***************** Bit definition for CAN_TDL1R register ****************/
jhon309	0:ac8863619623	1064	#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
jhon309	0:ac8863619623	1065	#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
jhon309	0:ac8863619623	1066	#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
jhon309	0:ac8863619623	1067	#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
jhon309	0:ac8863619623	1068
jhon309	0:ac8863619623	1069	/***************** Bit definition for CAN_TDH1R register ****************/
jhon309	0:ac8863619623	1070	#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
jhon309	0:ac8863619623	1071	#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
jhon309	0:ac8863619623	1072	#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
jhon309	0:ac8863619623	1073	#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
jhon309	0:ac8863619623	1074
jhon309	0:ac8863619623	1075	/***************** Bit definition for CAN_TI2R register *****************/
jhon309	0:ac8863619623	1076	#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
jhon309	0:ac8863619623	1077	#define CAN_TI2R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
jhon309	0:ac8863619623	1078	#define CAN_TI2R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
jhon309	0:ac8863619623	1079	#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
jhon309	0:ac8863619623	1080	#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
jhon309	0:ac8863619623	1081
jhon309	0:ac8863619623	1082	/***************** Bit definition for CAN_TDT2R register ****************/
jhon309	0:ac8863619623	1083	#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
jhon309	0:ac8863619623	1084	#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
jhon309	0:ac8863619623	1085	#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
jhon309	0:ac8863619623	1086
jhon309	0:ac8863619623	1087	/***************** Bit definition for CAN_TDL2R register ****************/
jhon309	0:ac8863619623	1088	#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
jhon309	0:ac8863619623	1089	#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
jhon309	0:ac8863619623	1090	#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
jhon309	0:ac8863619623	1091	#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
jhon309	0:ac8863619623	1092
jhon309	0:ac8863619623	1093	/***************** Bit definition for CAN_TDH2R register ****************/
jhon309	0:ac8863619623	1094	#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
jhon309	0:ac8863619623	1095	#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
jhon309	0:ac8863619623	1096	#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
jhon309	0:ac8863619623	1097	#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
jhon309	0:ac8863619623	1098
jhon309	0:ac8863619623	1099	/***************** Bit definition for CAN_RI0R register *****************/
jhon309	0:ac8863619623	1100	#define CAN_RI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
jhon309	0:ac8863619623	1101	#define CAN_RI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
jhon309	0:ac8863619623	1102	#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
jhon309	0:ac8863619623	1103	#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
jhon309	0:ac8863619623	1104
jhon309	0:ac8863619623	1105	/***************** Bit definition for CAN_RDT0R register ****************/
jhon309	0:ac8863619623	1106	#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
jhon309	0:ac8863619623	1107	#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
jhon309	0:ac8863619623	1108	#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
jhon309	0:ac8863619623	1109
jhon309	0:ac8863619623	1110	/***************** Bit definition for CAN_RDL0R register ****************/
jhon309	0:ac8863619623	1111	#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
jhon309	0:ac8863619623	1112	#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
jhon309	0:ac8863619623	1113	#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
jhon309	0:ac8863619623	1114	#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
jhon309	0:ac8863619623	1115
jhon309	0:ac8863619623	1116	/***************** Bit definition for CAN_RDH0R register ****************/
jhon309	0:ac8863619623	1117	#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
jhon309	0:ac8863619623	1118	#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
jhon309	0:ac8863619623	1119	#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
jhon309	0:ac8863619623	1120	#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
jhon309	0:ac8863619623	1121
jhon309	0:ac8863619623	1122	/***************** Bit definition for CAN_RI1R register *****************/
jhon309	0:ac8863619623	1123	#define CAN_RI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
jhon309	0:ac8863619623	1124	#define CAN_RI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
jhon309	0:ac8863619623	1125	#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
jhon309	0:ac8863619623	1126	#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
jhon309	0:ac8863619623	1127
jhon309	0:ac8863619623	1128	/***************** Bit definition for CAN_RDT1R register ****************/
jhon309	0:ac8863619623	1129	#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
jhon309	0:ac8863619623	1130	#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
jhon309	0:ac8863619623	1131	#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
jhon309	0:ac8863619623	1132
jhon309	0:ac8863619623	1133	/***************** Bit definition for CAN_RDL1R register ****************/
jhon309	0:ac8863619623	1134	#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
jhon309	0:ac8863619623	1135	#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
jhon309	0:ac8863619623	1136	#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
jhon309	0:ac8863619623	1137	#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
jhon309	0:ac8863619623	1138
jhon309	0:ac8863619623	1139	/***************** Bit definition for CAN_RDH1R register ****************/
jhon309	0:ac8863619623	1140	#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
jhon309	0:ac8863619623	1141	#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
jhon309	0:ac8863619623	1142	#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
jhon309	0:ac8863619623	1143	#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
jhon309	0:ac8863619623	1144
jhon309	0:ac8863619623	1145	/!<CAN filter registers /
jhon309	0:ac8863619623	1146	/***************** Bit definition for CAN_FMR register ******************/
jhon309	0:ac8863619623	1147	#define CAN_FMR_FINIT ((uint32_t)0x00000001) /!<Filter Init Mode /
jhon309	0:ac8863619623	1148
jhon309	0:ac8863619623	1149	/***************** Bit definition for CAN_FM1R register *****************/
jhon309	0:ac8863619623	1150	#define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /!<Filter Mode /
jhon309	0:ac8863619623	1151	#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /!<Filter Init Mode bit 0 /
jhon309	0:ac8863619623	1152	#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /!<Filter Init Mode bit 1 /
jhon309	0:ac8863619623	1153	#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /!<Filter Init Mode bit 2 /
jhon309	0:ac8863619623	1154	#define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /!<Filter Init Mode bit 3 /
jhon309	0:ac8863619623	1155	#define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /!<Filter Init Mode bit 4 /
jhon309	0:ac8863619623	1156	#define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /!<Filter Init Mode bit 5 /
jhon309	0:ac8863619623	1157	#define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /!<Filter Init Mode bit 6 /
jhon309	0:ac8863619623	1158	#define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /!<Filter Init Mode bit 7 /
jhon309	0:ac8863619623	1159	#define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /!<Filter Init Mode bit 8 /
jhon309	0:ac8863619623	1160	#define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /!<Filter Init Mode bit 9 /
jhon309	0:ac8863619623	1161	#define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /!<Filter Init Mode bit 10 /
jhon309	0:ac8863619623	1162	#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /!<Filter Init Mode bit 11 /
jhon309	0:ac8863619623	1163	#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /!<Filter Init Mode bit 12 /
jhon309	0:ac8863619623	1164	#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /!<Filter Init Mode bit 13 /
jhon309	0:ac8863619623	1165
jhon309	0:ac8863619623	1166	/***************** Bit definition for CAN_FS1R register *****************/
jhon309	0:ac8863619623	1167	#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /!<Filter Scale Configuration /
jhon309	0:ac8863619623	1168	#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /!<Filter Scale Configuration bit 0 /
jhon309	0:ac8863619623	1169	#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /!<Filter Scale Configuration bit 1 /
jhon309	0:ac8863619623	1170	#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /!<Filter Scale Configuration bit 2 /
jhon309	0:ac8863619623	1171	#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /!<Filter Scale Configuration bit 3 /
jhon309	0:ac8863619623	1172	#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /!<Filter Scale Configuration bit 4 /
jhon309	0:ac8863619623	1173	#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /!<Filter Scale Configuration bit 5 /
jhon309	0:ac8863619623	1174	#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /!<Filter Scale Configuration bit 6 /
jhon309	0:ac8863619623	1175	#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /!<Filter Scale Configuration bit 7 /
jhon309	0:ac8863619623	1176	#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /!<Filter Scale Configuration bit 8 /
jhon309	0:ac8863619623	1177	#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /!<Filter Scale Configuration bit 9 /
jhon309	0:ac8863619623	1178	#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /!<Filter Scale Configuration bit 10 /
jhon309	0:ac8863619623	1179	#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /!<Filter Scale Configuration bit 11 /
jhon309	0:ac8863619623	1180	#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /!<Filter Scale Configuration bit 12 /
jhon309	0:ac8863619623	1181	#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /!<Filter Scale Configuration bit 13 /
jhon309	0:ac8863619623	1182
jhon309	0:ac8863619623	1183	/**************** Bit definition for CAN_FFA1R register *****************/
jhon309	0:ac8863619623	1184	#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /!<Filter FIFO Assignment /
jhon309	0:ac8863619623	1185	#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /!<Filter FIFO Assignment for Filter 0 /
jhon309	0:ac8863619623	1186	#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /!<Filter FIFO Assignment for Filter 1 /
jhon309	0:ac8863619623	1187	#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /!<Filter FIFO Assignment for Filter 2 /
jhon309	0:ac8863619623	1188	#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /!<Filter FIFO Assignment for Filter 3 /
jhon309	0:ac8863619623	1189	#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /!<Filter FIFO Assignment for Filter 4 /
jhon309	0:ac8863619623	1190	#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /!<Filter FIFO Assignment for Filter 5 /
jhon309	0:ac8863619623	1191	#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /!<Filter FIFO Assignment for Filter 6 /
jhon309	0:ac8863619623	1192	#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /!<Filter FIFO Assignment for Filter 7 /
jhon309	0:ac8863619623	1193	#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /!<Filter FIFO Assignment for Filter 8 /
jhon309	0:ac8863619623	1194	#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /!<Filter FIFO Assignment for Filter 9 /
jhon309	0:ac8863619623	1195	#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /!<Filter FIFO Assignment for Filter 10 /
jhon309	0:ac8863619623	1196	#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /!<Filter FIFO Assignment for Filter 11 /
jhon309	0:ac8863619623	1197	#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /!<Filter FIFO Assignment for Filter 12 /
jhon309	0:ac8863619623	1198	#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /!<Filter FIFO Assignment for Filter 13 /
jhon309	0:ac8863619623	1199
jhon309	0:ac8863619623	1200	/***************** Bit definition for CAN_FA1R register *****************/
jhon309	0:ac8863619623	1201	#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /!<Filter Active /
jhon309	0:ac8863619623	1202	#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /!<Filter 0 Active /
jhon309	0:ac8863619623	1203	#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /!<Filter 1 Active /
jhon309	0:ac8863619623	1204	#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /!<Filter 2 Active /
jhon309	0:ac8863619623	1205	#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /!<Filter 3 Active /
jhon309	0:ac8863619623	1206	#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /!<Filter 4 Active /
jhon309	0:ac8863619623	1207	#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /!<Filter 5 Active /
jhon309	0:ac8863619623	1208	#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /!<Filter 6 Active /
jhon309	0:ac8863619623	1209	#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /!<Filter 7 Active /
jhon309	0:ac8863619623	1210	#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /!<Filter 8 Active /
jhon309	0:ac8863619623	1211	#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /!<Filter 9 Active /
jhon309	0:ac8863619623	1212	#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /!<Filter 10 Active /
jhon309	0:ac8863619623	1213	#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /!<Filter 11 Active /
jhon309	0:ac8863619623	1214	#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /!<Filter 12 Active /
jhon309	0:ac8863619623	1215	#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /!<Filter 13 Active /
jhon309	0:ac8863619623	1216
jhon309	0:ac8863619623	1217	/***************** Bit definition for CAN_F0R1 register *****************/
jhon309	0:ac8863619623	1218	#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	1219	#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	1220	#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	1221	#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	1222	#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	1223	#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	1224	#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	1225	#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	1226	#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	1227	#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	1228	#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	1229	#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	1230	#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	1231	#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	1232	#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	1233	#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	1234	#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	1235	#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	1236	#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	1237	#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	1238	#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	1239	#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	1240	#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	1241	#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	1242	#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	1243	#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	1244	#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	1245	#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	1246	#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	1247	#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	1248	#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	1249	#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	1250
jhon309	0:ac8863619623	1251	/***************** Bit definition for CAN_F1R1 register *****************/
jhon309	0:ac8863619623	1252	#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	1253	#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	1254	#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	1255	#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	1256	#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	1257	#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	1258	#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	1259	#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	1260	#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	1261	#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	1262	#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	1263	#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	1264	#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	1265	#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	1266	#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	1267	#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	1268	#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	1269	#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	1270	#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	1271	#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	1272	#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	1273	#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	1274	#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	1275	#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	1276	#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	1277	#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	1278	#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	1279	#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	1280	#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	1281	#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	1282	#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	1283	#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	1284
jhon309	0:ac8863619623	1285	/***************** Bit definition for CAN_F2R1 register *****************/
jhon309	0:ac8863619623	1286	#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	1287	#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	1288	#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	1289	#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	1290	#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	1291	#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	1292	#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	1293	#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	1294	#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	1295	#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	1296	#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	1297	#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	1298	#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	1299	#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	1300	#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	1301	#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	1302	#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	1303	#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	1304	#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	1305	#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	1306	#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	1307	#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	1308	#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	1309	#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	1310	#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	1311	#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	1312	#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	1313	#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	1314	#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	1315	#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	1316	#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	1317	#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	1318
jhon309	0:ac8863619623	1319	/***************** Bit definition for CAN_F3R1 register *****************/
jhon309	0:ac8863619623	1320	#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	1321	#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	1322	#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	1323	#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	1324	#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	1325	#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	1326	#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	1327	#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	1328	#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	1329	#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	1330	#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	1331	#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	1332	#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	1333	#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	1334	#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	1335	#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	1336	#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	1337	#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	1338	#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	1339	#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	1340	#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	1341	#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	1342	#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	1343	#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	1344	#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	1345	#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	1346	#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	1347	#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	1348	#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	1349	#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	1350	#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	1351	#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	1352
jhon309	0:ac8863619623	1353	/***************** Bit definition for CAN_F4R1 register *****************/
jhon309	0:ac8863619623	1354	#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	1355	#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	1356	#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	1357	#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	1358	#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	1359	#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	1360	#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	1361	#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	1362	#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	1363	#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	1364	#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	1365	#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	1366	#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	1367	#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	1368	#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	1369	#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	1370	#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	1371	#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	1372	#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	1373	#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	1374	#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	1375	#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	1376	#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	1377	#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	1378	#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	1379	#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	1380	#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	1381	#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	1382	#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	1383	#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	1384	#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	1385	#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	1386
jhon309	0:ac8863619623	1387	/***************** Bit definition for CAN_F5R1 register *****************/
jhon309	0:ac8863619623	1388	#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	1389	#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	1390	#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	1391	#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	1392	#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	1393	#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	1394	#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	1395	#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	1396	#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	1397	#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	1398	#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	1399	#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	1400	#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	1401	#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	1402	#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	1403	#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	1404	#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	1405	#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	1406	#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	1407	#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	1408	#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	1409	#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	1410	#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	1411	#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	1412	#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	1413	#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	1414	#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	1415	#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	1416	#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	1417	#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	1418	#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	1419	#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	1420
jhon309	0:ac8863619623	1421	/***************** Bit definition for CAN_F6R1 register *****************/
jhon309	0:ac8863619623	1422	#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	1423	#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	1424	#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	1425	#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	1426	#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	1427	#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	1428	#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	1429	#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	1430	#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	1431	#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	1432	#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	1433	#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	1434	#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	1435	#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	1436	#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	1437	#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	1438	#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	1439	#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	1440	#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	1441	#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	1442	#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	1443	#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	1444	#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	1445	#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	1446	#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	1447	#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	1448	#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	1449	#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	1450	#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	1451	#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	1452	#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	1453	#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	1454
jhon309	0:ac8863619623	1455	/***************** Bit definition for CAN_F7R1 register *****************/
jhon309	0:ac8863619623	1456	#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	1457	#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	1458	#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	1459	#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	1460	#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	1461	#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	1462	#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	1463	#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	1464	#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	1465	#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	1466	#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	1467	#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	1468	#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	1469	#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	1470	#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	1471	#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	1472	#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	1473	#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	1474	#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	1475	#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	1476	#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	1477	#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	1478	#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	1479	#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	1480	#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	1481	#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	1482	#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	1483	#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	1484	#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	1485	#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	1486	#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	1487	#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	1488
jhon309	0:ac8863619623	1489	/***************** Bit definition for CAN_F8R1 register *****************/
jhon309	0:ac8863619623	1490	#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	1491	#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	1492	#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	1493	#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	1494	#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	1495	#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	1496	#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	1497	#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	1498	#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	1499	#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	1500	#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	1501	#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	1502	#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	1503	#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	1504	#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	1505	#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	1506	#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	1507	#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	1508	#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	1509	#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	1510	#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	1511	#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	1512	#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	1513	#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	1514	#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	1515	#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	1516	#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	1517	#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	1518	#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	1519	#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	1520	#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	1521	#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	1522
jhon309	0:ac8863619623	1523	/***************** Bit definition for CAN_F9R1 register *****************/
jhon309	0:ac8863619623	1524	#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	1525	#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	1526	#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	1527	#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	1528	#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	1529	#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	1530	#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	1531	#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	1532	#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	1533	#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	1534	#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	1535	#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	1536	#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	1537	#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	1538	#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	1539	#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	1540	#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	1541	#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	1542	#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	1543	#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	1544	#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	1545	#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	1546	#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	1547	#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	1548	#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	1549	#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	1550	#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	1551	#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	1552	#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	1553	#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	1554	#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	1555	#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	1556
jhon309	0:ac8863619623	1557	/***************** Bit definition for CAN_F10R1 register ****************/
jhon309	0:ac8863619623	1558	#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	1559	#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	1560	#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	1561	#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	1562	#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	1563	#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	1564	#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	1565	#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	1566	#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	1567	#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	1568	#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	1569	#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	1570	#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	1571	#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	1572	#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	1573	#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	1574	#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	1575	#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	1576	#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	1577	#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	1578	#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	1579	#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	1580	#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	1581	#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	1582	#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	1583	#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	1584	#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	1585	#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	1586	#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	1587	#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	1588	#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	1589	#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	1590
jhon309	0:ac8863619623	1591	/***************** Bit definition for CAN_F11R1 register ****************/
jhon309	0:ac8863619623	1592	#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	1593	#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	1594	#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	1595	#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	1596	#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	1597	#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	1598	#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	1599	#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	1600	#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	1601	#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	1602	#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	1603	#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	1604	#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	1605	#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	1606	#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	1607	#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	1608	#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	1609	#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	1610	#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	1611	#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	1612	#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	1613	#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	1614	#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	1615	#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	1616	#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	1617	#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	1618	#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	1619	#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	1620	#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	1621	#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	1622	#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	1623	#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	1624
jhon309	0:ac8863619623	1625	/***************** Bit definition for CAN_F12R1 register ****************/
jhon309	0:ac8863619623	1626	#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	1627	#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	1628	#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	1629	#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	1630	#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	1631	#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	1632	#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	1633	#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	1634	#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	1635	#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	1636	#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	1637	#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	1638	#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	1639	#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	1640	#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	1641	#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	1642	#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	1643	#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	1644	#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	1645	#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	1646	#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	1647	#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	1648	#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	1649	#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	1650	#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	1651	#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	1652	#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	1653	#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	1654	#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	1655	#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	1656	#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	1657	#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	1658
jhon309	0:ac8863619623	1659	/***************** Bit definition for CAN_F13R1 register ****************/
jhon309	0:ac8863619623	1660	#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	1661	#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	1662	#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	1663	#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	1664	#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	1665	#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	1666	#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	1667	#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	1668	#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	1669	#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	1670	#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	1671	#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	1672	#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	1673	#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	1674	#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	1675	#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	1676	#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	1677	#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	1678	#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	1679	#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	1680	#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	1681	#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	1682	#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	1683	#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	1684	#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	1685	#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	1686	#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	1687	#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	1688	#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	1689	#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	1690	#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	1691	#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	1692
jhon309	0:ac8863619623	1693	/***************** Bit definition for CAN_F0R2 register *****************/
jhon309	0:ac8863619623	1694	#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	1695	#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	1696	#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	1697	#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	1698	#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	1699	#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	1700	#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	1701	#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	1702	#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	1703	#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	1704	#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	1705	#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	1706	#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	1707	#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	1708	#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	1709	#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	1710	#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	1711	#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	1712	#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	1713	#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	1714	#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	1715	#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	1716	#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	1717	#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	1718	#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	1719	#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	1720	#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	1721	#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	1722	#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	1723	#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	1724	#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	1725	#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	1726
jhon309	0:ac8863619623	1727	/***************** Bit definition for CAN_F1R2 register *****************/
jhon309	0:ac8863619623	1728	#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	1729	#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	1730	#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	1731	#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	1732	#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	1733	#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	1734	#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	1735	#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	1736	#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	1737	#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	1738	#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	1739	#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	1740	#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	1741	#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	1742	#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	1743	#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	1744	#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	1745	#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	1746	#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	1747	#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	1748	#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	1749	#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	1750	#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	1751	#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	1752	#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	1753	#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	1754	#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	1755	#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	1756	#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	1757	#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	1758	#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	1759	#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	1760
jhon309	0:ac8863619623	1761	/***************** Bit definition for CAN_F2R2 register *****************/
jhon309	0:ac8863619623	1762	#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	1763	#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	1764	#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	1765	#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	1766	#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	1767	#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	1768	#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	1769	#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	1770	#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	1771	#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	1772	#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	1773	#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	1774	#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	1775	#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	1776	#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	1777	#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	1778	#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	1779	#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	1780	#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	1781	#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	1782	#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	1783	#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	1784	#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	1785	#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	1786	#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	1787	#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	1788	#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	1789	#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	1790	#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	1791	#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	1792	#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	1793	#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	1794
jhon309	0:ac8863619623	1795	/***************** Bit definition for CAN_F3R2 register *****************/
jhon309	0:ac8863619623	1796	#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	1797	#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	1798	#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	1799	#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	1800	#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	1801	#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	1802	#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	1803	#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	1804	#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	1805	#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	1806	#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	1807	#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	1808	#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	1809	#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	1810	#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	1811	#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	1812	#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	1813	#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	1814	#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	1815	#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	1816	#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	1817	#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	1818	#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	1819	#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	1820	#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	1821	#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	1822	#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	1823	#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	1824	#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	1825	#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	1826	#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	1827	#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	1828
jhon309	0:ac8863619623	1829	/***************** Bit definition for CAN_F4R2 register *****************/
jhon309	0:ac8863619623	1830	#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	1831	#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	1832	#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	1833	#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	1834	#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	1835	#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	1836	#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	1837	#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	1838	#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	1839	#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	1840	#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	1841	#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	1842	#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	1843	#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	1844	#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	1845	#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	1846	#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	1847	#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	1848	#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	1849	#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	1850	#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	1851	#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	1852	#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	1853	#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	1854	#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	1855	#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	1856	#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	1857	#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	1858	#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	1859	#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	1860	#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	1861	#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	1862
jhon309	0:ac8863619623	1863	/***************** Bit definition for CAN_F5R2 register *****************/
jhon309	0:ac8863619623	1864	#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	1865	#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	1866	#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	1867	#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	1868	#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	1869	#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	1870	#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	1871	#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	1872	#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	1873	#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	1874	#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	1875	#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	1876	#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	1877	#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	1878	#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	1879	#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	1880	#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	1881	#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	1882	#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	1883	#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	1884	#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	1885	#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	1886	#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	1887	#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	1888	#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	1889	#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	1890	#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	1891	#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	1892	#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	1893	#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	1894	#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	1895	#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	1896
jhon309	0:ac8863619623	1897	/***************** Bit definition for CAN_F6R2 register *****************/
jhon309	0:ac8863619623	1898	#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	1899	#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	1900	#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	1901	#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	1902	#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	1903	#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	1904	#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	1905	#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	1906	#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	1907	#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	1908	#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	1909	#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	1910	#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	1911	#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	1912	#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	1913	#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	1914	#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	1915	#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	1916	#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	1917	#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	1918	#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	1919	#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	1920	#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	1921	#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	1922	#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	1923	#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	1924	#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	1925	#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	1926	#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	1927	#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	1928	#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	1929	#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	1930
jhon309	0:ac8863619623	1931	/***************** Bit definition for CAN_F7R2 register *****************/
jhon309	0:ac8863619623	1932	#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	1933	#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	1934	#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	1935	#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	1936	#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	1937	#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	1938	#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	1939	#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	1940	#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	1941	#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	1942	#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	1943	#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	1944	#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	1945	#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	1946	#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	1947	#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	1948	#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	1949	#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	1950	#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	1951	#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	1952	#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	1953	#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	1954	#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	1955	#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	1956	#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	1957	#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	1958	#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	1959	#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	1960	#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	1961	#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	1962	#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	1963	#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	1964
jhon309	0:ac8863619623	1965	/***************** Bit definition for CAN_F8R2 register *****************/
jhon309	0:ac8863619623	1966	#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	1967	#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	1968	#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	1969	#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	1970	#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	1971	#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	1972	#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	1973	#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	1974	#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	1975	#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	1976	#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	1977	#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	1978	#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	1979	#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	1980	#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	1981	#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	1982	#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	1983	#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	1984	#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	1985	#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	1986	#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	1987	#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	1988	#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	1989	#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	1990	#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	1991	#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	1992	#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	1993	#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	1994	#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	1995	#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	1996	#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	1997	#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	1998
jhon309	0:ac8863619623	1999	/***************** Bit definition for CAN_F9R2 register *****************/
jhon309	0:ac8863619623	2000	#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	2001	#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	2002	#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	2003	#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	2004	#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	2005	#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	2006	#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	2007	#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	2008	#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	2009	#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	2010	#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	2011	#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	2012	#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	2013	#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	2014	#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	2015	#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	2016	#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	2017	#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	2018	#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	2019	#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	2020	#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	2021	#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	2022	#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	2023	#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	2024	#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	2025	#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	2026	#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	2027	#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	2028	#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	2029	#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	2030	#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	2031	#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	2032
jhon309	0:ac8863619623	2033	/***************** Bit definition for CAN_F10R2 register ****************/
jhon309	0:ac8863619623	2034	#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	2035	#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	2036	#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	2037	#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	2038	#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	2039	#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	2040	#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	2041	#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	2042	#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	2043	#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	2044	#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	2045	#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	2046	#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	2047	#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	2048	#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	2049	#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	2050	#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	2051	#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	2052	#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	2053	#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	2054	#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	2055	#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	2056	#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	2057	#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	2058	#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	2059	#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	2060	#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	2061	#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	2062	#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	2063	#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	2064	#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	2065	#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	2066
jhon309	0:ac8863619623	2067	/***************** Bit definition for CAN_F11R2 register ****************/
jhon309	0:ac8863619623	2068	#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	2069	#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	2070	#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	2071	#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	2072	#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	2073	#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	2074	#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	2075	#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	2076	#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	2077	#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	2078	#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	2079	#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	2080	#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	2081	#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	2082	#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	2083	#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	2084	#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	2085	#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	2086	#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	2087	#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	2088	#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	2089	#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	2090	#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	2091	#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	2092	#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	2093	#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	2094	#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	2095	#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	2096	#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	2097	#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	2098	#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	2099	#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	2100
jhon309	0:ac8863619623	2101	/***************** Bit definition for CAN_F12R2 register ****************/
jhon309	0:ac8863619623	2102	#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	2103	#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	2104	#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	2105	#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	2106	#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	2107	#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	2108	#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	2109	#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	2110	#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	2111	#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	2112	#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	2113	#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	2114	#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	2115	#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	2116	#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	2117	#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	2118	#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	2119	#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	2120	#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	2121	#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	2122	#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	2123	#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	2124	#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	2125	#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	2126	#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	2127	#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	2128	#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	2129	#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	2130	#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	2131	#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	2132	#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	2133	#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	2134
jhon309	0:ac8863619623	2135	/***************** Bit definition for CAN_F13R2 register ****************/
jhon309	0:ac8863619623	2136	#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
jhon309	0:ac8863619623	2137	#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
jhon309	0:ac8863619623	2138	#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
jhon309	0:ac8863619623	2139	#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
jhon309	0:ac8863619623	2140	#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
jhon309	0:ac8863619623	2141	#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
jhon309	0:ac8863619623	2142	#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
jhon309	0:ac8863619623	2143	#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
jhon309	0:ac8863619623	2144	#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
jhon309	0:ac8863619623	2145	#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
jhon309	0:ac8863619623	2146	#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
jhon309	0:ac8863619623	2147	#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
jhon309	0:ac8863619623	2148	#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
jhon309	0:ac8863619623	2149	#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
jhon309	0:ac8863619623	2150	#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
jhon309	0:ac8863619623	2151	#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
jhon309	0:ac8863619623	2152	#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
jhon309	0:ac8863619623	2153	#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
jhon309	0:ac8863619623	2154	#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
jhon309	0:ac8863619623	2155	#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
jhon309	0:ac8863619623	2156	#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
jhon309	0:ac8863619623	2157	#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
jhon309	0:ac8863619623	2158	#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
jhon309	0:ac8863619623	2159	#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
jhon309	0:ac8863619623	2160	#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
jhon309	0:ac8863619623	2161	#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
jhon309	0:ac8863619623	2162	#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
jhon309	0:ac8863619623	2163	#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
jhon309	0:ac8863619623	2164	#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
jhon309	0:ac8863619623	2165	#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
jhon309	0:ac8863619623	2166	#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
jhon309	0:ac8863619623	2167	#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
jhon309	0:ac8863619623	2168
jhon309	0:ac8863619623	2169	/******************************************************************************/
jhon309	0:ac8863619623	2170	/* */
jhon309	0:ac8863619623	2171	/* HDMI-CEC (CEC) */
jhon309	0:ac8863619623	2172	/* */
jhon309	0:ac8863619623	2173	/******************************************************************************/
jhon309	0:ac8863619623	2174
jhon309	0:ac8863619623	2175	/***************** Bit definition for CEC_CR register *******************/
jhon309	0:ac8863619623	2176	#define CEC_CR_CECEN ((uint32_t)0x00000001) /!< CEC Enable /
jhon309	0:ac8863619623	2177	#define CEC_CR_TXSOM ((uint32_t)0x00000002) /!< CEC Tx Start Of Message /
jhon309	0:ac8863619623	2178	#define CEC_CR_TXEOM ((uint32_t)0x00000004) /!< CEC Tx End Of Message /
jhon309	0:ac8863619623	2179
jhon309	0:ac8863619623	2180	/***************** Bit definition for CEC_CFGR register *****************/
jhon309	0:ac8863619623	2181	#define CEC_CFGR_SFT ((uint32_t)0x00000007) /!< CEC Signal Free Time /
jhon309	0:ac8863619623	2182	#define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /!< CEC Tolerance /
jhon309	0:ac8863619623	2183	#define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /!< CEC Rx Stop /
jhon309	0:ac8863619623	2184	#define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /!< CEC Bit Rising Error generation /
jhon309	0:ac8863619623	2185	#define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /!< CEC Long Bit Period Error gener. /
jhon309	0:ac8863619623	2186	#define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /!< CEC Broadcast No Error generation /
jhon309	0:ac8863619623	2187	#define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /!< CEC Signal Free Time optional /
jhon309	0:ac8863619623	2188	#define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /!< CEC Own Address /
jhon309	0:ac8863619623	2189	#define CEC_CFGR_LSTN ((uint32_t)0x80000000) /!< CEC Listen mode /
jhon309	0:ac8863619623	2190
jhon309	0:ac8863619623	2191	/***************** Bit definition for CEC_TXDR register *****************/
jhon309	0:ac8863619623	2192	#define CEC_TXDR_TXD ((uint32_t)0x000000FF) /!< CEC Tx Data /
jhon309	0:ac8863619623	2193
jhon309	0:ac8863619623	2194	/***************** Bit definition for CEC_RXDR register *****************/
jhon309	0:ac8863619623	2195	#define CEC_TXDR_RXD ((uint32_t)0x000000FF) /!< CEC Rx Data /
jhon309	0:ac8863619623	2196
jhon309	0:ac8863619623	2197	/***************** Bit definition for CEC_ISR register ******************/
jhon309	0:ac8863619623	2198	#define CEC_ISR_RXBR ((uint32_t)0x00000001) /!< CEC Rx-Byte Received /
jhon309	0:ac8863619623	2199	#define CEC_ISR_RXEND ((uint32_t)0x00000002) /!< CEC End Of Reception /
jhon309	0:ac8863619623	2200	#define CEC_ISR_RXOVR ((uint32_t)0x00000004) /!< CEC Rx-Overrun /
jhon309	0:ac8863619623	2201	#define CEC_ISR_BRE ((uint32_t)0x00000008) /!< CEC Rx Bit Rising Error /
jhon309	0:ac8863619623	2202	#define CEC_ISR_SBPE ((uint32_t)0x00000010) /!< CEC Rx Short Bit period Error /
jhon309	0:ac8863619623	2203	#define CEC_ISR_LBPE ((uint32_t)0x00000020) /!< CEC Rx Long Bit period Error /
jhon309	0:ac8863619623	2204	#define CEC_ISR_RXACKE ((uint32_t)0x00000040) /!< CEC Rx Missing Acknowledge /
jhon309	0:ac8863619623	2205	#define CEC_ISR_ARBLST ((uint32_t)0x00000080) /!< CEC Arbitration Lost /
jhon309	0:ac8863619623	2206	#define CEC_ISR_TXBR ((uint32_t)0x00000100) /!< CEC Tx Byte Request /
jhon309	0:ac8863619623	2207	#define CEC_ISR_TXEND ((uint32_t)0x00000200) /!< CEC End of Transmission /
jhon309	0:ac8863619623	2208	#define CEC_ISR_TXUDR ((uint32_t)0x00000400) /!< CEC Tx-Buffer Underrun /
jhon309	0:ac8863619623	2209	#define CEC_ISR_TXERR ((uint32_t)0x00000800) /!< CEC Tx-Error /
jhon309	0:ac8863619623	2210	#define CEC_ISR_TXACKE ((uint32_t)0x00001000) /!< CEC Tx Missing Acknowledge /
jhon309	0:ac8863619623	2211
jhon309	0:ac8863619623	2212	/***************** Bit definition for CEC_IER register ******************/
jhon309	0:ac8863619623	2213	#define CEC_IER_RXBRIE ((uint32_t)0x00000001) /!< CEC Rx-Byte Received IT Enable /
jhon309	0:ac8863619623	2214	#define CEC_IER_RXENDIE ((uint32_t)0x00000002) /!< CEC End Of Reception IT Enable /
jhon309	0:ac8863619623	2215	#define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /!< CEC Rx-Overrun IT Enable /
jhon309	0:ac8863619623	2216	#define CEC_IER_BREIE ((uint32_t)0x00000008) /!< CEC Rx Bit Rising Error IT Enable /
jhon309	0:ac8863619623	2217	#define CEC_IER_SBPEIE ((uint32_t)0x00000010) /!< CEC Rx Short Bit period Error IT Enable/
jhon309	0:ac8863619623	2218	#define CEC_IER_LBPEIE ((uint32_t)0x00000020) /!< CEC Rx Long Bit period Error IT Enable /
jhon309	0:ac8863619623	2219	#define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /!< CEC Rx Missing Acknowledge IT Enable /
jhon309	0:ac8863619623	2220	#define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /!< CEC Arbitration Lost IT Enable /
jhon309	0:ac8863619623	2221	#define CEC_IER_TXBRIE ((uint32_t)0x00000100) /!< CEC Tx Byte Request IT Enable /
jhon309	0:ac8863619623	2222	#define CEC_IER_TXENDIE ((uint32_t)0x00000200) /!< CEC End of Transmission IT Enable /
jhon309	0:ac8863619623	2223	#define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /!< CEC Tx-Buffer Underrun IT Enable /
jhon309	0:ac8863619623	2224	#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /!< CEC Tx-Error IT Enable /
jhon309	0:ac8863619623	2225	#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /!< CEC Tx Missing Acknowledge IT Enable /
jhon309	0:ac8863619623	2226
jhon309	0:ac8863619623	2227
jhon309	0:ac8863619623	2228	/******************************************************************************/
jhon309	0:ac8863619623	2229	/* */
jhon309	0:ac8863619623	2230	/* Analog Comparators (COMP) */
jhon309	0:ac8863619623	2231	/* */
jhon309	0:ac8863619623	2232	/******************************************************************************/
jhon309	0:ac8863619623	2233	/********************* Bit definition for COMP_CSR register *************/
jhon309	0:ac8863619623	2234	/* COMP1 bits definition */
jhon309	0:ac8863619623	2235	#define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /!< COMP1 enable /
jhon309	0:ac8863619623	2236	#define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /!< SW1 switch control /
jhon309	0:ac8863619623	2237	#define COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) /!< COMP1 power mode /
jhon309	0:ac8863619623	2238	#define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /!< COMP1 power mode bit 0 /
jhon309	0:ac8863619623	2239	#define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /!< COMP1 power mode bit 1 /
jhon309	0:ac8863619623	2240	#define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) /!< COMP1 inverting input select /
jhon309	0:ac8863619623	2241	#define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /!< COMP1 inverting input select bit 0 /
jhon309	0:ac8863619623	2242	#define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /!< COMP1 inverting input select bit 1 /
jhon309	0:ac8863619623	2243	#define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /!< COMP1 inverting input select bit 2 /
jhon309	0:ac8863619623	2244	#define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) /!< COMP1 output select /
jhon309	0:ac8863619623	2245	#define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) /!< COMP1 output select bit 0 /
jhon309	0:ac8863619623	2246	#define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) /!< COMP1 output select bit 1 /
jhon309	0:ac8863619623	2247	#define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) /!< COMP1 output select bit 2 /
jhon309	0:ac8863619623	2248	#define COMP_CSR_COMP1POL ((uint32_t)0x00000800) /!< COMP1 output polarity /
jhon309	0:ac8863619623	2249	#define COMP_CSR_COMP1HYST ((uint32_t)0x00003000) /!< COMP1 hysteresis /
jhon309	0:ac8863619623	2250	#define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) /!< COMP1 hysteresis bit 0 /
jhon309	0:ac8863619623	2251	#define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) /!< COMP1 hysteresis bit 1 /
jhon309	0:ac8863619623	2252	#define COMP_CSR_COMP1OUT ((uint32_t)0x00004000) /!< COMP1 output level /
jhon309	0:ac8863619623	2253	#define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) /!< COMP1 lock /
jhon309	0:ac8863619623	2254	/* COMP2 bits definition */
jhon309	0:ac8863619623	2255	#define COMP_CSR_COMP2EN ((uint32_t)0x00010000) /!< COMP2 enable /
jhon309	0:ac8863619623	2256	#define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) /!< COMP2 power mode /
jhon309	0:ac8863619623	2257	#define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) /!< COMP2 power mode bit 0 /
jhon309	0:ac8863619623	2258	#define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) /!< COMP2 power mode bit 1 /
jhon309	0:ac8863619623	2259	#define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) /!< COMP2 inverting input select /
jhon309	0:ac8863619623	2260	#define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) /!< COMP2 inverting input select bit 0 /
jhon309	0:ac8863619623	2261	#define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) /!< COMP2 inverting input select bit 1 /
jhon309	0:ac8863619623	2262	#define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) /!< COMP2 inverting input select bit 2 /
jhon309	0:ac8863619623	2263	#define COMP_CSR_WNDWEN ((uint32_t)0x00800000) /!< Comparators window mode enable /
jhon309	0:ac8863619623	2264	#define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) /!< COMP2 output select /
jhon309	0:ac8863619623	2265	#define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) /!< COMP2 output select bit 0 /
jhon309	0:ac8863619623	2266	#define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) /!< COMP2 output select bit 1 /
jhon309	0:ac8863619623	2267	#define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) /!< COMP2 output select bit 2 /
jhon309	0:ac8863619623	2268	#define COMP_CSR_COMP2POL ((uint32_t)0x08000000) /!< COMP2 output polarity /
jhon309	0:ac8863619623	2269	#define COMP_CSR_COMP2HYST ((uint32_t)0x30000000) /!< COMP2 hysteresis /
jhon309	0:ac8863619623	2270	#define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) /!< COMP2 hysteresis bit 0 /
jhon309	0:ac8863619623	2271	#define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) /!< COMP2 hysteresis bit 1 /
jhon309	0:ac8863619623	2272	#define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /!< COMP2 output level /
jhon309	0:ac8863619623	2273	#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /!< COMP2 lock /
jhon309	0:ac8863619623	2274	/* COMPx bits definition */
jhon309	0:ac8863619623	2275	#define COMP_CSR_COMPxEN ((uint16_t)0x0001) /!< COMPx enable /
jhon309	0:ac8863619623	2276	#define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /!< COMPx power mode /
jhon309	0:ac8863619623	2277	#define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /!< COMPx power mode bit 0 /
jhon309	0:ac8863619623	2278	#define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /!< COMPx power mode bit 1 /
jhon309	0:ac8863619623	2279	#define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /!< COMPx inverting input select /
jhon309	0:ac8863619623	2280	#define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /!< COMPx inverting input select bit 0 /
jhon309	0:ac8863619623	2281	#define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /!< COMPx inverting input select bit 1 /
jhon309	0:ac8863619623	2282	#define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /!< COMPx inverting input select bit 2 /
jhon309	0:ac8863619623	2283	#define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /!< COMPx output select /
jhon309	0:ac8863619623	2284	#define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /!< COMPx output select bit 0 /
jhon309	0:ac8863619623	2285	#define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /!< COMPx output select bit 1 /
jhon309	0:ac8863619623	2286	#define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /!< COMPx output select bit 2 /
jhon309	0:ac8863619623	2287	#define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /!< COMPx output polarity /
jhon309	0:ac8863619623	2288	#define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /!< COMPx hysteresis /
jhon309	0:ac8863619623	2289	#define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /!< COMPx hysteresis bit 0 /
jhon309	0:ac8863619623	2290	#define COMP_CSR_COMPxHYST_1 ((uint16_t)0x2000) /!< COMPx hysteresis bit 1 /
jhon309	0:ac8863619623	2291	#define COMP_CSR_COMPxOUT ((uint16_t)0x4000) /!< COMPx output level /
jhon309	0:ac8863619623	2292	#define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /!< COMPx lock /
jhon309	0:ac8863619623	2293
jhon309	0:ac8863619623	2294	/******************************************************************************/
jhon309	0:ac8863619623	2295	/* */
jhon309	0:ac8863619623	2296	/* CRC calculation unit (CRC) */
jhon309	0:ac8863619623	2297	/* */
jhon309	0:ac8863619623	2298	/******************************************************************************/
jhon309	0:ac8863619623	2299	/***************** Bit definition for CRC_DR register *******************/
jhon309	0:ac8863619623	2300	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
jhon309	0:ac8863619623	2301
jhon309	0:ac8863619623	2302	/***************** Bit definition for CRC_IDR register ******************/
jhon309	0:ac8863619623	2303	#define CRC_IDR_IDR ((uint8_t)0xFF) /!< General-purpose 8-bit data register bits /
jhon309	0:ac8863619623	2304
jhon309	0:ac8863619623	2305	/****************** Bit definition for CRC_CR register ******************/
jhon309	0:ac8863619623	2306	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET the CRC computation unit bit /
jhon309	0:ac8863619623	2307	#define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /!< Polynomial size bits /
jhon309	0:ac8863619623	2308	#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /!< Polynomial size bit 0 /
jhon309	0:ac8863619623	2309	#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /!< Polynomial size bit 1 /
jhon309	0:ac8863619623	2310	#define CRC_CR_REV_IN ((uint32_t)0x00000060) /!< REV_IN Reverse Input Data bits /
jhon309	0:ac8863619623	2311	#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /!< REV_IN Bit 0 /
jhon309	0:ac8863619623	2312	#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /!< REV_IN Bit 1 /
jhon309	0:ac8863619623	2313	#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /!< REV_OUT Reverse Output Data bits /
jhon309	0:ac8863619623	2314
jhon309	0:ac8863619623	2315	/***************** Bit definition for CRC_INIT register *****************/
jhon309	0:ac8863619623	2316	#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /!< Initial CRC value bits /
jhon309	0:ac8863619623	2317
jhon309	0:ac8863619623	2318	/***************** Bit definition for CRC_POL register ******************/
jhon309	0:ac8863619623	2319	#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /!< Coefficients of the polynomial /
jhon309	0:ac8863619623	2320
jhon309	0:ac8863619623	2321	/******************************************************************************/
jhon309	0:ac8863619623	2322	/* */
jhon309	0:ac8863619623	2323	/* CRS Clock Recovery System */
jhon309	0:ac8863619623	2324	/******************************************************************************/
jhon309	0:ac8863619623	2325
jhon309	0:ac8863619623	2326	/***************** Bit definition for CRS_CR register *******************/
jhon309	0:ac8863619623	2327	#define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
jhon309	0:ac8863619623	2328	#define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
jhon309	0:ac8863619623	2329	#define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
jhon309	0:ac8863619623	2330	#define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
jhon309	0:ac8863619623	2331	#define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
jhon309	0:ac8863619623	2332	#define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
jhon309	0:ac8863619623	2333	#define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
jhon309	0:ac8863619623	2334	#define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
jhon309	0:ac8863619623	2335
jhon309	0:ac8863619623	2336	/***************** Bit definition for CRS_CFGR register *******************/
jhon309	0:ac8863619623	2337	#define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
jhon309	0:ac8863619623	2338	#define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
jhon309	0:ac8863619623	2339
jhon309	0:ac8863619623	2340	#define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
jhon309	0:ac8863619623	2341	#define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
jhon309	0:ac8863619623	2342	#define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
jhon309	0:ac8863619623	2343	#define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
jhon309	0:ac8863619623	2344
jhon309	0:ac8863619623	2345	#define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
jhon309	0:ac8863619623	2346	#define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
jhon309	0:ac8863619623	2347	#define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
jhon309	0:ac8863619623	2348
jhon309	0:ac8863619623	2349	#define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
jhon309	0:ac8863619623	2350
jhon309	0:ac8863619623	2351	/***************** Bit definition for CRS_ISR register *******************/
jhon309	0:ac8863619623	2352	#define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
jhon309	0:ac8863619623	2353	#define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
jhon309	0:ac8863619623	2354	#define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
jhon309	0:ac8863619623	2355	#define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
jhon309	0:ac8863619623	2356	#define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
jhon309	0:ac8863619623	2357	#define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
jhon309	0:ac8863619623	2358	#define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
jhon309	0:ac8863619623	2359	#define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
jhon309	0:ac8863619623	2360	#define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
jhon309	0:ac8863619623	2361
jhon309	0:ac8863619623	2362	/***************** Bit definition for CRS_ICR register *******************/
jhon309	0:ac8863619623	2363	#define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
jhon309	0:ac8863619623	2364	#define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
jhon309	0:ac8863619623	2365	#define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
jhon309	0:ac8863619623	2366	#define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
jhon309	0:ac8863619623	2367
jhon309	0:ac8863619623	2368	/******************************************************************************/
jhon309	0:ac8863619623	2369	/* */
jhon309	0:ac8863619623	2370	/* Digital to Analog Converter (DAC) */
jhon309	0:ac8863619623	2371	/* */
jhon309	0:ac8863619623	2372	/******************************************************************************/
jhon309	0:ac8863619623	2373	/****************** Bit definition for DAC_CR register ******************/
jhon309	0:ac8863619623	2374	#define DAC_CR_EN1 ((uint32_t)0x00000001) /!< DAC channel1 enable /
jhon309	0:ac8863619623	2375	#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /!< DAC channel1 output buffer disable /
jhon309	0:ac8863619623	2376	#define DAC_CR_TEN1 ((uint32_t)0x00000004) /!< DAC channel1 Trigger enable /
jhon309	0:ac8863619623	2377
jhon309	0:ac8863619623	2378	#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /!< TSEL1[2:0] (DAC channel1 Trigger selection) /
jhon309	0:ac8863619623	2379	#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /!< Bit 0 /
jhon309	0:ac8863619623	2380	#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /!< Bit 1 /
jhon309	0:ac8863619623	2381	#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /!< Bit 2 /
jhon309	0:ac8863619623	2382
jhon309	0:ac8863619623	2383	#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
jhon309	0:ac8863619623	2384	#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /!< Bit 0 /
jhon309	0:ac8863619623	2385	#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /!< Bit 1 /
jhon309	0:ac8863619623	2386
jhon309	0:ac8863619623	2387	#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
jhon309	0:ac8863619623	2388	#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /!< Bit 0 /
jhon309	0:ac8863619623	2389	#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /!< Bit 1 /
jhon309	0:ac8863619623	2390	#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /!< Bit 2 /
jhon309	0:ac8863619623	2391	#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /!< Bit 3 /
jhon309	0:ac8863619623	2392
jhon309	0:ac8863619623	2393	#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /!< DAC channel1 DMA enable /
jhon309	0:ac8863619623	2394	#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /!< DAC channel1 DMA Underrun Interrupt enable /
jhon309	0:ac8863619623	2395
jhon309	0:ac8863619623	2396	#define DAC_CR_EN2 ((uint32_t)0x00010000) /!< DAC channel2 enable /
jhon309	0:ac8863619623	2397	#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /!< DAC channel2 output buffer disable /
jhon309	0:ac8863619623	2398	#define DAC_CR_TEN2 ((uint32_t)0x00040000) /!< DAC channel2 Trigger enable /
jhon309	0:ac8863619623	2399
jhon309	0:ac8863619623	2400	#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /!< TSEL2[2:0] (DAC channel2 Trigger selection) /
jhon309	0:ac8863619623	2401	#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /!< Bit 0 /
jhon309	0:ac8863619623	2402	#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /!< Bit 1 /
jhon309	0:ac8863619623	2403	#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /!< Bit 2 /
jhon309	0:ac8863619623	2404
jhon309	0:ac8863619623	2405	#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
jhon309	0:ac8863619623	2406	#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /!< Bit 0 /
jhon309	0:ac8863619623	2407	#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /!< Bit 1 /
jhon309	0:ac8863619623	2408
jhon309	0:ac8863619623	2409	#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
jhon309	0:ac8863619623	2410	#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /!< Bit 0 /
jhon309	0:ac8863619623	2411	#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /!< Bit 1 /
jhon309	0:ac8863619623	2412	#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /!< Bit 2 /
jhon309	0:ac8863619623	2413	#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /!< Bit 3 /
jhon309	0:ac8863619623	2414
jhon309	0:ac8863619623	2415	#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /!< DAC channel2 DMA enabled /
jhon309	0:ac8863619623	2416	#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /!< DAC channel2 DMA Underrun Interrupt enable /
jhon309	0:ac8863619623	2417
jhon309	0:ac8863619623	2418	/*************** Bit definition for DAC_SWTRIGR register ****************/
jhon309	0:ac8863619623	2419	#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /!< DAC channel1 software trigger /
jhon309	0:ac8863619623	2420	#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /!< DAC channel2 software trigger /
jhon309	0:ac8863619623	2421
jhon309	0:ac8863619623	2422	/*************** Bit definition for DAC_DHR12R1 register ****************/
jhon309	0:ac8863619623	2423	#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /!< DAC channel1 12-bit Right aligned data /
jhon309	0:ac8863619623	2424
jhon309	0:ac8863619623	2425	/*************** Bit definition for DAC_DHR12L1 register ****************/
jhon309	0:ac8863619623	2426	#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /!< DAC channel1 12-bit Left aligned data /
jhon309	0:ac8863619623	2427
jhon309	0:ac8863619623	2428	/**************** Bit definition for DAC_DHR8R1 register ****************/
jhon309	0:ac8863619623	2429	#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /!< DAC channel1 8-bit Right aligned data /
jhon309	0:ac8863619623	2430
jhon309	0:ac8863619623	2431	/*************** Bit definition for DAC_DHR12R2 register ****************/
jhon309	0:ac8863619623	2432	#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /!< DAC channel2 12-bit Right aligned data /
jhon309	0:ac8863619623	2433
jhon309	0:ac8863619623	2434	/*************** Bit definition for DAC_DHR12L2 register ****************/
jhon309	0:ac8863619623	2435	#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /!< DAC channel2 12-bit Left aligned data /
jhon309	0:ac8863619623	2436
jhon309	0:ac8863619623	2437	/**************** Bit definition for DAC_DHR8R2 register ****************/
jhon309	0:ac8863619623	2438	#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /!< DAC channel2 8-bit Right aligned data /
jhon309	0:ac8863619623	2439
jhon309	0:ac8863619623	2440	/*************** Bit definition for DAC_DHR12RD register ****************/
jhon309	0:ac8863619623	2441	#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /!< DAC channel1 12-bit Right aligned data /
jhon309	0:ac8863619623	2442	#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /!< DAC channel2 12-bit Right aligned data /
jhon309	0:ac8863619623	2443
jhon309	0:ac8863619623	2444	/*************** Bit definition for DAC_DHR12LD register ****************/
jhon309	0:ac8863619623	2445	#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /!< DAC channel1 12-bit Left aligned data /
jhon309	0:ac8863619623	2446	#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /!< DAC channel2 12-bit Left aligned data /
jhon309	0:ac8863619623	2447
jhon309	0:ac8863619623	2448	/**************** Bit definition for DAC_DHR8RD register ****************/
jhon309	0:ac8863619623	2449	#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /!< DAC channel1 8-bit Right aligned data /
jhon309	0:ac8863619623	2450	#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /!< DAC channel2 8-bit Right aligned data /
jhon309	0:ac8863619623	2451
jhon309	0:ac8863619623	2452	/***************** Bit definition for DAC_DOR1 register *****************/
jhon309	0:ac8863619623	2453	#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /!< DAC channel1 data output /
jhon309	0:ac8863619623	2454
jhon309	0:ac8863619623	2455	/***************** Bit definition for DAC_DOR2 register *****************/
jhon309	0:ac8863619623	2456	#define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /!< DAC channel2 data output /
jhon309	0:ac8863619623	2457
jhon309	0:ac8863619623	2458	/****************** Bit definition for DAC_SR register ******************/
jhon309	0:ac8863619623	2459	#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /!< DAC channel1 DMA underrun flag /
jhon309	0:ac8863619623	2460	#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /!< DAC channel2 DMA underrun flag /
jhon309	0:ac8863619623	2461
jhon309	0:ac8863619623	2462	/******************************************************************************/
jhon309	0:ac8863619623	2463	/* */
jhon309	0:ac8863619623	2464	/* Debug MCU (DBGMCU) */
jhon309	0:ac8863619623	2465	/* */
jhon309	0:ac8863619623	2466	/******************************************************************************/
jhon309	0:ac8863619623	2467
jhon309	0:ac8863619623	2468	/************** Bit definition for DBGMCU_IDCODE register ***************/
jhon309	0:ac8863619623	2469	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /!< Device Identifier /
jhon309	0:ac8863619623	2470
jhon309	0:ac8863619623	2471	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /!< REV_ID[15:0] bits (Revision Identifier) /
jhon309	0:ac8863619623	2472	#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /!< Bit 0 /
jhon309	0:ac8863619623	2473	#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /!< Bit 1 /
jhon309	0:ac8863619623	2474	#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /!< Bit 2 /
jhon309	0:ac8863619623	2475	#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /!< Bit 3 /
jhon309	0:ac8863619623	2476	#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /!< Bit 4 /
jhon309	0:ac8863619623	2477	#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /!< Bit 5 /
jhon309	0:ac8863619623	2478	#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /!< Bit 6 /
jhon309	0:ac8863619623	2479	#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /!< Bit 7 /
jhon309	0:ac8863619623	2480	#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /!< Bit 8 /
jhon309	0:ac8863619623	2481	#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /!< Bit 9 /
jhon309	0:ac8863619623	2482	#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /!< Bit 10 /
jhon309	0:ac8863619623	2483	#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /!< Bit 11 /
jhon309	0:ac8863619623	2484	#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /!< Bit 12 /
jhon309	0:ac8863619623	2485	#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /!< Bit 13 /
jhon309	0:ac8863619623	2486	#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /!< Bit 14 /
jhon309	0:ac8863619623	2487	#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /!< Bit 15 /
jhon309	0:ac8863619623	2488
jhon309	0:ac8863619623	2489	/**************** Bit definition for DBGMCU_CR register *****************/
jhon309	0:ac8863619623	2490	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /!< Debug Stop Mode /
jhon309	0:ac8863619623	2491	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /!< Debug Standby mode /
jhon309	0:ac8863619623	2492
jhon309	0:ac8863619623	2493	/**************** Bit definition for DBGMCU_APB1_FZ register ************/
jhon309	0:ac8863619623	2494	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /!< TIM2 counter stopped when core is halted /
jhon309	0:ac8863619623	2495	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /!< TIM3 counter stopped when core is halted /
jhon309	0:ac8863619623	2496	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /!< TIM6 counter stopped when core is halted /
jhon309	0:ac8863619623	2497	#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /!< TIM7 counter stopped when core is halted /
jhon309	0:ac8863619623	2498	#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /!< TIM14 counter stopped when core is halted /
jhon309	0:ac8863619623	2499	#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /!< RTC Calendar frozen when core is halted /
jhon309	0:ac8863619623	2500	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /!< Debug Window Watchdog stopped when Core is halted /
jhon309	0:ac8863619623	2501	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /!< Debug Independent Watchdog stopped when Core is halted /
jhon309	0:ac8863619623	2502	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /!< I2C1 SMBUS timeout mode stopped when Core is halted /
jhon309	0:ac8863619623	2503	#define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000) /!< CAN debug stopped when Core is halted /
jhon309	0:ac8863619623	2504
jhon309	0:ac8863619623	2505	/**************** Bit definition for DBGMCU_APB2_FZ register ************/
jhon309	0:ac8863619623	2506	#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /!< TIM1 counter stopped when core is halted /
jhon309	0:ac8863619623	2507	#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /!< TIM15 counter stopped when core is halted /
jhon309	0:ac8863619623	2508	#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /!< TIM16 counter stopped when core is halted /
jhon309	0:ac8863619623	2509	#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /!< TIM17 counter stopped when core is halted /
jhon309	0:ac8863619623	2510
jhon309	0:ac8863619623	2511	/******************************************************************************/
jhon309	0:ac8863619623	2512	/* */
jhon309	0:ac8863619623	2513	/* DMA Controller (DMA) */
jhon309	0:ac8863619623	2514	/* */
jhon309	0:ac8863619623	2515	/******************************************************************************/
jhon309	0:ac8863619623	2516	/***************** Bit definition for DMA_ISR register ******************/
jhon309	0:ac8863619623	2517	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
jhon309	0:ac8863619623	2518	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
jhon309	0:ac8863619623	2519	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
jhon309	0:ac8863619623	2520	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
jhon309	0:ac8863619623	2521	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
jhon309	0:ac8863619623	2522	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
jhon309	0:ac8863619623	2523	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
jhon309	0:ac8863619623	2524	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
jhon309	0:ac8863619623	2525	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
jhon309	0:ac8863619623	2526	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
jhon309	0:ac8863619623	2527	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
jhon309	0:ac8863619623	2528	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
jhon309	0:ac8863619623	2529	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
jhon309	0:ac8863619623	2530	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
jhon309	0:ac8863619623	2531	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
jhon309	0:ac8863619623	2532	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
jhon309	0:ac8863619623	2533	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
jhon309	0:ac8863619623	2534	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
jhon309	0:ac8863619623	2535	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
jhon309	0:ac8863619623	2536	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
jhon309	0:ac8863619623	2537	#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt flag /
jhon309	0:ac8863619623	2538	#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete flag /
jhon309	0:ac8863619623	2539	#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer flag /
jhon309	0:ac8863619623	2540	#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error flag /
jhon309	0:ac8863619623	2541	#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt flag /
jhon309	0:ac8863619623	2542	#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete flag /
jhon309	0:ac8863619623	2543	#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer flag /
jhon309	0:ac8863619623	2544	#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error flag /
jhon309	0:ac8863619623	2545
jhon309	0:ac8863619623	2546	/***************** Bit definition for DMA_IFCR register *****************/
jhon309	0:ac8863619623	2547	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clear /
jhon309	0:ac8863619623	2548	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
jhon309	0:ac8863619623	2549	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
jhon309	0:ac8863619623	2550	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
jhon309	0:ac8863619623	2551	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
jhon309	0:ac8863619623	2552	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
jhon309	0:ac8863619623	2553	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
jhon309	0:ac8863619623	2554	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
jhon309	0:ac8863619623	2555	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
jhon309	0:ac8863619623	2556	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
jhon309	0:ac8863619623	2557	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
jhon309	0:ac8863619623	2558	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
jhon309	0:ac8863619623	2559	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
jhon309	0:ac8863619623	2560	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
jhon309	0:ac8863619623	2561	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
jhon309	0:ac8863619623	2562	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
jhon309	0:ac8863619623	2563	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
jhon309	0:ac8863619623	2564	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
jhon309	0:ac8863619623	2565	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
jhon309	0:ac8863619623	2566	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
jhon309	0:ac8863619623	2567	#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt clear /
jhon309	0:ac8863619623	2568	#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete clear /
jhon309	0:ac8863619623	2569	#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer clear /
jhon309	0:ac8863619623	2570	#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error clear /
jhon309	0:ac8863619623	2571	#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt clear /
jhon309	0:ac8863619623	2572	#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete clear /
jhon309	0:ac8863619623	2573	#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer clear /
jhon309	0:ac8863619623	2574	#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error clear /
jhon309	0:ac8863619623	2575
jhon309	0:ac8863619623	2576	/***************** Bit definition for DMA_CCR register ******************/
jhon309	0:ac8863619623	2577	#define DMA_CCR_EN ((uint32_t)0x00000001) /!< Channel enable /
jhon309	0:ac8863619623	2578	#define DMA_CCR_TCIE ((uint32_t)0x00000002) /!< Transfer complete interrupt enable /
jhon309	0:ac8863619623	2579	#define DMA_CCR_HTIE ((uint32_t)0x00000004) /!< Half Transfer interrupt enable /
jhon309	0:ac8863619623	2580	#define DMA_CCR_TEIE ((uint32_t)0x00000008) /!< Transfer error interrupt enable /
jhon309	0:ac8863619623	2581	#define DMA_CCR_DIR ((uint32_t)0x00000010) /!< Data transfer direction /
jhon309	0:ac8863619623	2582	#define DMA_CCR_CIRC ((uint32_t)0x00000020) /!< Circular mode /
jhon309	0:ac8863619623	2583	#define DMA_CCR_PINC ((uint32_t)0x00000040) /!< Peripheral increment mode /
jhon309	0:ac8863619623	2584	#define DMA_CCR_MINC ((uint32_t)0x00000080) /!< Memory increment mode /
jhon309	0:ac8863619623	2585
jhon309	0:ac8863619623	2586	#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /!< PSIZE[1:0] bits (Peripheral size) /
jhon309	0:ac8863619623	2587	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /!< Bit 0 /
jhon309	0:ac8863619623	2588	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /!< Bit 1 /
jhon309	0:ac8863619623	2589
jhon309	0:ac8863619623	2590	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /!< MSIZE[1:0] bits (Memory size) /
jhon309	0:ac8863619623	2591	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /!< Bit 0 /
jhon309	0:ac8863619623	2592	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /!< Bit 1 /
jhon309	0:ac8863619623	2593
jhon309	0:ac8863619623	2594	#define DMA_CCR_PL ((uint32_t)0x00003000) /!< PL[1:0] bits(Channel Priority level)/
jhon309	0:ac8863619623	2595	#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /!< Bit 0 /
jhon309	0:ac8863619623	2596	#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /!< Bit 1 /
jhon309	0:ac8863619623	2597
jhon309	0:ac8863619623	2598	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /!< Memory to memory mode /
jhon309	0:ac8863619623	2599
jhon309	0:ac8863619623	2600	/**************** Bit definition for DMA_CNDTR register *****************/
jhon309	0:ac8863619623	2601	#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
jhon309	0:ac8863619623	2602
jhon309	0:ac8863619623	2603	/**************** Bit definition for DMA_CPAR register ******************/
jhon309	0:ac8863619623	2604	#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
jhon309	0:ac8863619623	2605
jhon309	0:ac8863619623	2606	/**************** Bit definition for DMA_CMAR register ******************/
jhon309	0:ac8863619623	2607	#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
jhon309	0:ac8863619623	2608
jhon309	0:ac8863619623	2609	/******************************************************************************/
jhon309	0:ac8863619623	2610	/* */
jhon309	0:ac8863619623	2611	/* External Interrupt/Event Controller (EXTI) */
jhon309	0:ac8863619623	2612	/* */
jhon309	0:ac8863619623	2613	/******************************************************************************/
jhon309	0:ac8863619623	2614	/***************** Bit definition for EXTI_IMR register *****************/
jhon309	0:ac8863619623	2615	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
jhon309	0:ac8863619623	2616	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
jhon309	0:ac8863619623	2617	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
jhon309	0:ac8863619623	2618	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
jhon309	0:ac8863619623	2619	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
jhon309	0:ac8863619623	2620	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
jhon309	0:ac8863619623	2621	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
jhon309	0:ac8863619623	2622	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
jhon309	0:ac8863619623	2623	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
jhon309	0:ac8863619623	2624	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
jhon309	0:ac8863619623	2625	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
jhon309	0:ac8863619623	2626	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
jhon309	0:ac8863619623	2627	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
jhon309	0:ac8863619623	2628	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
jhon309	0:ac8863619623	2629	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
jhon309	0:ac8863619623	2630	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
jhon309	0:ac8863619623	2631	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
jhon309	0:ac8863619623	2632	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
jhon309	0:ac8863619623	2633	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
jhon309	0:ac8863619623	2634	#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /!< Interrupt Mask on line 21 /
jhon309	0:ac8863619623	2635	#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /!< Interrupt Mask on line 22 /
jhon309	0:ac8863619623	2636	#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /!< Interrupt Mask on line 23 /
jhon309	0:ac8863619623	2637	#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /!< Interrupt Mask on line 25 /
jhon309	0:ac8863619623	2638	#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /!< Interrupt Mask on line 27 /
jhon309	0:ac8863619623	2639
jhon309	0:ac8863619623	2640	/**************** Bit definition for EXTI_EMR register ******************/
jhon309	0:ac8863619623	2641	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
jhon309	0:ac8863619623	2642	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
jhon309	0:ac8863619623	2643	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
jhon309	0:ac8863619623	2644	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
jhon309	0:ac8863619623	2645	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
jhon309	0:ac8863619623	2646	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
jhon309	0:ac8863619623	2647	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
jhon309	0:ac8863619623	2648	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
jhon309	0:ac8863619623	2649	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
jhon309	0:ac8863619623	2650	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
jhon309	0:ac8863619623	2651	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
jhon309	0:ac8863619623	2652	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
jhon309	0:ac8863619623	2653	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
jhon309	0:ac8863619623	2654	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
jhon309	0:ac8863619623	2655	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
jhon309	0:ac8863619623	2656	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
jhon309	0:ac8863619623	2657	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
jhon309	0:ac8863619623	2658	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
jhon309	0:ac8863619623	2659	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
jhon309	0:ac8863619623	2660	#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /!< Event Mask on line 21 /
jhon309	0:ac8863619623	2661	#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /!< Event Mask on line 22 /
jhon309	0:ac8863619623	2662	#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /!< Event Mask on line 23 /
jhon309	0:ac8863619623	2663	#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /!< Event Mask on line 25 /
jhon309	0:ac8863619623	2664	#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /!< Event Mask on line 27 /
jhon309	0:ac8863619623	2665
jhon309	0:ac8863619623	2666	/***************** Bit definition for EXTI_RTSR register ****************/
jhon309	0:ac8863619623	2667	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
jhon309	0:ac8863619623	2668	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
jhon309	0:ac8863619623	2669	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
jhon309	0:ac8863619623	2670	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
jhon309	0:ac8863619623	2671	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
jhon309	0:ac8863619623	2672	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
jhon309	0:ac8863619623	2673	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
jhon309	0:ac8863619623	2674	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
jhon309	0:ac8863619623	2675	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
jhon309	0:ac8863619623	2676	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
jhon309	0:ac8863619623	2677	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
jhon309	0:ac8863619623	2678	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
jhon309	0:ac8863619623	2679	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
jhon309	0:ac8863619623	2680	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
jhon309	0:ac8863619623	2681	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
jhon309	0:ac8863619623	2682	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
jhon309	0:ac8863619623	2683	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
jhon309	0:ac8863619623	2684	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
jhon309	0:ac8863619623	2685	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
jhon309	0:ac8863619623	2686
jhon309	0:ac8863619623	2687	/***************** Bit definition for EXTI_FTSR register *****************/
jhon309	0:ac8863619623	2688	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
jhon309	0:ac8863619623	2689	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
jhon309	0:ac8863619623	2690	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
jhon309	0:ac8863619623	2691	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
jhon309	0:ac8863619623	2692	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
jhon309	0:ac8863619623	2693	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
jhon309	0:ac8863619623	2694	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
jhon309	0:ac8863619623	2695	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
jhon309	0:ac8863619623	2696	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
jhon309	0:ac8863619623	2697	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
jhon309	0:ac8863619623	2698	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
jhon309	0:ac8863619623	2699	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
jhon309	0:ac8863619623	2700	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
jhon309	0:ac8863619623	2701	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
jhon309	0:ac8863619623	2702	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
jhon309	0:ac8863619623	2703	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
jhon309	0:ac8863619623	2704	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
jhon309	0:ac8863619623	2705	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
jhon309	0:ac8863619623	2706	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
jhon309	0:ac8863619623	2707
jhon309	0:ac8863619623	2708	/***************** Bit definition for EXTI_SWIER register *****************/
jhon309	0:ac8863619623	2709	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
jhon309	0:ac8863619623	2710	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
jhon309	0:ac8863619623	2711	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
jhon309	0:ac8863619623	2712	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
jhon309	0:ac8863619623	2713	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
jhon309	0:ac8863619623	2714	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
jhon309	0:ac8863619623	2715	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
jhon309	0:ac8863619623	2716	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
jhon309	0:ac8863619623	2717	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
jhon309	0:ac8863619623	2718	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
jhon309	0:ac8863619623	2719	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
jhon309	0:ac8863619623	2720	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
jhon309	0:ac8863619623	2721	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
jhon309	0:ac8863619623	2722	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
jhon309	0:ac8863619623	2723	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
jhon309	0:ac8863619623	2724	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
jhon309	0:ac8863619623	2725	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
jhon309	0:ac8863619623	2726	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
jhon309	0:ac8863619623	2727	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
jhon309	0:ac8863619623	2728
jhon309	0:ac8863619623	2729	/**************** Bit definition for EXTI_PR register *******************/
jhon309	0:ac8863619623	2730	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit 0 /
jhon309	0:ac8863619623	2731	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit 1 /
jhon309	0:ac8863619623	2732	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit 2 /
jhon309	0:ac8863619623	2733	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit 3 /
jhon309	0:ac8863619623	2734	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit 4 /
jhon309	0:ac8863619623	2735	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit 5 /
jhon309	0:ac8863619623	2736	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit 6 /
jhon309	0:ac8863619623	2737	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit 7 /
jhon309	0:ac8863619623	2738	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit 8 /
jhon309	0:ac8863619623	2739	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit 9 /
jhon309	0:ac8863619623	2740	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit 10 /
jhon309	0:ac8863619623	2741	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit 11 /
jhon309	0:ac8863619623	2742	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit 12 /
jhon309	0:ac8863619623	2743	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit 13 /
jhon309	0:ac8863619623	2744	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit 14 /
jhon309	0:ac8863619623	2745	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit 15 /
jhon309	0:ac8863619623	2746	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit 16 /
jhon309	0:ac8863619623	2747	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit 17 /
jhon309	0:ac8863619623	2748	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit 19 /
jhon309	0:ac8863619623	2749
jhon309	0:ac8863619623	2750	/******************************************************************************/
jhon309	0:ac8863619623	2751	/* */
jhon309	0:ac8863619623	2752	/* FLASH and Option Bytes Registers */
jhon309	0:ac8863619623	2753	/* */
jhon309	0:ac8863619623	2754	/******************************************************************************/
jhon309	0:ac8863619623	2755
jhon309	0:ac8863619623	2756	/***************** Bit definition for FLASH_ACR register ****************/
jhon309	0:ac8863619623	2757	#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /!< LATENCY bit (Latency) /
jhon309	0:ac8863619623	2758
jhon309	0:ac8863619623	2759	#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /!< Prefetch Buffer Enable /
jhon309	0:ac8863619623	2760	#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /!< Prefetch Buffer Status /
jhon309	0:ac8863619623	2761
jhon309	0:ac8863619623	2762	/**************** Bit definition for FLASH_KEYR register ****************/
jhon309	0:ac8863619623	2763	#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /!< FPEC Key /
jhon309	0:ac8863619623	2764
jhon309	0:ac8863619623	2765	/*************** Bit definition for FLASH_OPTKEYR register **************/
jhon309	0:ac8863619623	2766	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /!< Option Byte Key /
jhon309	0:ac8863619623	2767
jhon309	0:ac8863619623	2768	/**************** FLASH Keys ********************************************/
jhon309	0:ac8863619623	2769	#define FLASH_FKEY1 ((uint32_t)0x45670123) /!< Flash program erase key1 /
jhon309	0:ac8863619623	2770	#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
jhon309	0:ac8863619623	2771	to unlock the write access to the FPEC. */
jhon309	0:ac8863619623	2772
jhon309	0:ac8863619623	2773	#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /!< Flash option key1 /
jhon309	0:ac8863619623	2774	#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
jhon309	0:ac8863619623	2775	unlock the write access to the option byte block */
jhon309	0:ac8863619623	2776
jhon309	0:ac8863619623	2777	/**************** Bit definition for FLASH_SR register *****************/
jhon309	0:ac8863619623	2778	#define FLASH_SR_BSY ((uint32_t)0x00000001) /!< Busy /
jhon309	0:ac8863619623	2779	#define FLASH_SR_PGERR ((uint32_t)0x00000004) /!< Programming Error /
jhon309	0:ac8863619623	2780	#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /!< Write Protection Error /
jhon309	0:ac8863619623	2781	#define FLASH_SR_EOP ((uint32_t)0x00000020) /!< End of operation /
jhon309	0:ac8863619623	2782	#define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /!< Legacy of Write Protection Error /
jhon309	0:ac8863619623	2783
jhon309	0:ac8863619623	2784	/***************** Bit definition for FLASH_CR register *****************/
jhon309	0:ac8863619623	2785	#define FLASH_CR_PG ((uint32_t)0x00000001) /!< Programming /
jhon309	0:ac8863619623	2786	#define FLASH_CR_PER ((uint32_t)0x00000002) /!< Page Erase /
jhon309	0:ac8863619623	2787	#define FLASH_CR_MER ((uint32_t)0x00000004) /!< Mass Erase /
jhon309	0:ac8863619623	2788	#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /!< Option Byte Programming /
jhon309	0:ac8863619623	2789	#define FLASH_CR_OPTER ((uint32_t)0x00000020) /!< Option Byte Erase /
jhon309	0:ac8863619623	2790	#define FLASH_CR_STRT ((uint32_t)0x00000040) /!< Start /
jhon309	0:ac8863619623	2791	#define FLASH_CR_LOCK ((uint32_t)0x00000080) /!< Lock /
jhon309	0:ac8863619623	2792	#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /!< Option Bytes Write Enable /
jhon309	0:ac8863619623	2793	#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /!< Error Interrupt Enable /
jhon309	0:ac8863619623	2794	#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /!< End of operation interrupt enable /
jhon309	0:ac8863619623	2795	#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /!< Option Bytes Loader Launch /
jhon309	0:ac8863619623	2796
jhon309	0:ac8863619623	2797	/***************** Bit definition for FLASH_AR register *****************/
jhon309	0:ac8863619623	2798	#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /!< Flash Address /
jhon309	0:ac8863619623	2799
jhon309	0:ac8863619623	2800	/**************** Bit definition for FLASH_OBR register *****************/
jhon309	0:ac8863619623	2801	#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /!< Option Byte Error /
jhon309	0:ac8863619623	2802	#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /!< Read protection Level 1 /
jhon309	0:ac8863619623	2803	#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /!< Read protection Level 2 /
jhon309	0:ac8863619623	2804
jhon309	0:ac8863619623	2805	#define FLASH_OBR_USER ((uint32_t)0x00003700) /!< User Option Bytes /
jhon309	0:ac8863619623	2806	#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /!< IWDG SW /
jhon309	0:ac8863619623	2807	#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /!< nRST_STOP /
jhon309	0:ac8863619623	2808	#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /!< nRST_STDBY /
jhon309	0:ac8863619623	2809	#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /!< nBOOT1 /
jhon309	0:ac8863619623	2810	#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /!< VDDA power supply supervisor /
jhon309	0:ac8863619623	2811
jhon309	0:ac8863619623	2812	/* Old BOOT1 bit definition, maintained for legacy purpose */
jhon309	0:ac8863619623	2813	#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
jhon309	0:ac8863619623	2814
jhon309	0:ac8863619623	2815	/* Old OBR_VDDA bit definition, maintained for legacy purpose */
jhon309	0:ac8863619623	2816	#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
jhon309	0:ac8863619623	2817
jhon309	0:ac8863619623	2818	/**************** Bit definition for FLASH_WRPR register ****************/
jhon309	0:ac8863619623	2819	#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /!< Write Protect /
jhon309	0:ac8863619623	2820
jhon309	0:ac8863619623	2821	/----------------------------------------------------------------------------/
jhon309	0:ac8863619623	2822
jhon309	0:ac8863619623	2823	/**************** Bit definition for OB_RDP register ********************/
jhon309	0:ac8863619623	2824	#define OB_RDP_RDP ((uint32_t)0x000000FF) /!< Read protection option byte /
jhon309	0:ac8863619623	2825	#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /!< Read protection complemented option byte /
jhon309	0:ac8863619623	2826
jhon309	0:ac8863619623	2827	/**************** Bit definition for OB_USER register *******************/
jhon309	0:ac8863619623	2828	#define OB_USER_USER ((uint32_t)0x00FF0000) /!< User option byte /
jhon309	0:ac8863619623	2829	#define OB_USER_nUSER ((uint32_t)0xFF000000) /!< User complemented option byte /
jhon309	0:ac8863619623	2830
jhon309	0:ac8863619623	2831	/**************** Bit definition for OB_WRP0 register *******************/
jhon309	0:ac8863619623	2832	#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
jhon309	0:ac8863619623	2833	#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
jhon309	0:ac8863619623	2834
jhon309	0:ac8863619623	2835	/**************** Bit definition for OB_WRP1 register *******************/
jhon309	0:ac8863619623	2836	#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
jhon309	0:ac8863619623	2837	#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
jhon309	0:ac8863619623	2838
jhon309	0:ac8863619623	2839	/**************** Bit definition for OB_WRP2 register *******************/
jhon309	0:ac8863619623	2840	#define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
jhon309	0:ac8863619623	2841	#define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
jhon309	0:ac8863619623	2842
jhon309	0:ac8863619623	2843	/**************** Bit definition for OB_WRP3 register *******************/
jhon309	0:ac8863619623	2844	#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
jhon309	0:ac8863619623	2845	#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
jhon309	0:ac8863619623	2846
jhon309	0:ac8863619623	2847	/******************************************************************************/
jhon309	0:ac8863619623	2848	/* */
jhon309	0:ac8863619623	2849	/* General Purpose IOs (GPIO) */
jhon309	0:ac8863619623	2850	/* */
jhon309	0:ac8863619623	2851	/******************************************************************************/
jhon309	0:ac8863619623	2852	/***************** Bit definition for GPIO_MODER register ***************/
jhon309	0:ac8863619623	2853	#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
jhon309	0:ac8863619623	2854	#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
jhon309	0:ac8863619623	2855	#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
jhon309	0:ac8863619623	2856	#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
jhon309	0:ac8863619623	2857	#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
jhon309	0:ac8863619623	2858	#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
jhon309	0:ac8863619623	2859	#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
jhon309	0:ac8863619623	2860	#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
jhon309	0:ac8863619623	2861	#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
jhon309	0:ac8863619623	2862	#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
jhon309	0:ac8863619623	2863	#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
jhon309	0:ac8863619623	2864	#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
jhon309	0:ac8863619623	2865	#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
jhon309	0:ac8863619623	2866	#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
jhon309	0:ac8863619623	2867	#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
jhon309	0:ac8863619623	2868	#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
jhon309	0:ac8863619623	2869	#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
jhon309	0:ac8863619623	2870	#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
jhon309	0:ac8863619623	2871	#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
jhon309	0:ac8863619623	2872	#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
jhon309	0:ac8863619623	2873	#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
jhon309	0:ac8863619623	2874	#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
jhon309	0:ac8863619623	2875	#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
jhon309	0:ac8863619623	2876	#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
jhon309	0:ac8863619623	2877	#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
jhon309	0:ac8863619623	2878	#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
jhon309	0:ac8863619623	2879	#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
jhon309	0:ac8863619623	2880	#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
jhon309	0:ac8863619623	2881	#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
jhon309	0:ac8863619623	2882	#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
jhon309	0:ac8863619623	2883	#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
jhon309	0:ac8863619623	2884	#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
jhon309	0:ac8863619623	2885	#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
jhon309	0:ac8863619623	2886	#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
jhon309	0:ac8863619623	2887	#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
jhon309	0:ac8863619623	2888	#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
jhon309	0:ac8863619623	2889	#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
jhon309	0:ac8863619623	2890	#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
jhon309	0:ac8863619623	2891	#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
jhon309	0:ac8863619623	2892	#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
jhon309	0:ac8863619623	2893	#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
jhon309	0:ac8863619623	2894	#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
jhon309	0:ac8863619623	2895	#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
jhon309	0:ac8863619623	2896	#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
jhon309	0:ac8863619623	2897	#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
jhon309	0:ac8863619623	2898	#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
jhon309	0:ac8863619623	2899	#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
jhon309	0:ac8863619623	2900	#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
jhon309	0:ac8863619623	2901
jhon309	0:ac8863619623	2902	/**************** Bit definition for GPIO_OTYPER register ***************/
jhon309	0:ac8863619623	2903	#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
jhon309	0:ac8863619623	2904	#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
jhon309	0:ac8863619623	2905	#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
jhon309	0:ac8863619623	2906	#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
jhon309	0:ac8863619623	2907	#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
jhon309	0:ac8863619623	2908	#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
jhon309	0:ac8863619623	2909	#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
jhon309	0:ac8863619623	2910	#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
jhon309	0:ac8863619623	2911	#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
jhon309	0:ac8863619623	2912	#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
jhon309	0:ac8863619623	2913	#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
jhon309	0:ac8863619623	2914	#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
jhon309	0:ac8863619623	2915	#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
jhon309	0:ac8863619623	2916	#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
jhon309	0:ac8863619623	2917	#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
jhon309	0:ac8863619623	2918	#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
jhon309	0:ac8863619623	2919
jhon309	0:ac8863619623	2920	/************** Bit definition for GPIO_OSPEEDR register ****************/
jhon309	0:ac8863619623	2921	#define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
jhon309	0:ac8863619623	2922	#define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
jhon309	0:ac8863619623	2923	#define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
jhon309	0:ac8863619623	2924	#define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
jhon309	0:ac8863619623	2925	#define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
jhon309	0:ac8863619623	2926	#define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
jhon309	0:ac8863619623	2927	#define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
jhon309	0:ac8863619623	2928	#define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
jhon309	0:ac8863619623	2929	#define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
jhon309	0:ac8863619623	2930	#define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
jhon309	0:ac8863619623	2931	#define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
jhon309	0:ac8863619623	2932	#define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
jhon309	0:ac8863619623	2933	#define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
jhon309	0:ac8863619623	2934	#define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
jhon309	0:ac8863619623	2935	#define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
jhon309	0:ac8863619623	2936	#define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
jhon309	0:ac8863619623	2937	#define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
jhon309	0:ac8863619623	2938	#define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
jhon309	0:ac8863619623	2939	#define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
jhon309	0:ac8863619623	2940	#define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
jhon309	0:ac8863619623	2941	#define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
jhon309	0:ac8863619623	2942	#define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
jhon309	0:ac8863619623	2943	#define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
jhon309	0:ac8863619623	2944	#define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
jhon309	0:ac8863619623	2945	#define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
jhon309	0:ac8863619623	2946	#define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
jhon309	0:ac8863619623	2947	#define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
jhon309	0:ac8863619623	2948	#define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
jhon309	0:ac8863619623	2949	#define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
jhon309	0:ac8863619623	2950	#define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
jhon309	0:ac8863619623	2951	#define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
jhon309	0:ac8863619623	2952	#define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
jhon309	0:ac8863619623	2953	#define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
jhon309	0:ac8863619623	2954	#define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
jhon309	0:ac8863619623	2955	#define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
jhon309	0:ac8863619623	2956	#define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
jhon309	0:ac8863619623	2957	#define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
jhon309	0:ac8863619623	2958	#define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
jhon309	0:ac8863619623	2959	#define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
jhon309	0:ac8863619623	2960	#define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
jhon309	0:ac8863619623	2961	#define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
jhon309	0:ac8863619623	2962	#define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
jhon309	0:ac8863619623	2963	#define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
jhon309	0:ac8863619623	2964	#define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
jhon309	0:ac8863619623	2965	#define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
jhon309	0:ac8863619623	2966	#define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
jhon309	0:ac8863619623	2967	#define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
jhon309	0:ac8863619623	2968	#define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
jhon309	0:ac8863619623	2969
jhon309	0:ac8863619623	2970	/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
jhon309	0:ac8863619623	2971	#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
jhon309	0:ac8863619623	2972	#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
jhon309	0:ac8863619623	2973	#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
jhon309	0:ac8863619623	2974	#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
jhon309	0:ac8863619623	2975	#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
jhon309	0:ac8863619623	2976	#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
jhon309	0:ac8863619623	2977	#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
jhon309	0:ac8863619623	2978	#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
jhon309	0:ac8863619623	2979	#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
jhon309	0:ac8863619623	2980	#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
jhon309	0:ac8863619623	2981	#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
jhon309	0:ac8863619623	2982	#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
jhon309	0:ac8863619623	2983	#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
jhon309	0:ac8863619623	2984	#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
jhon309	0:ac8863619623	2985	#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
jhon309	0:ac8863619623	2986	#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
jhon309	0:ac8863619623	2987	#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
jhon309	0:ac8863619623	2988	#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
jhon309	0:ac8863619623	2989	#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
jhon309	0:ac8863619623	2990	#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
jhon309	0:ac8863619623	2991	#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
jhon309	0:ac8863619623	2992	#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
jhon309	0:ac8863619623	2993	#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
jhon309	0:ac8863619623	2994	#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
jhon309	0:ac8863619623	2995	#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
jhon309	0:ac8863619623	2996	#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
jhon309	0:ac8863619623	2997	#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
jhon309	0:ac8863619623	2998	#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
jhon309	0:ac8863619623	2999	#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
jhon309	0:ac8863619623	3000	#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
jhon309	0:ac8863619623	3001	#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
jhon309	0:ac8863619623	3002	#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
jhon309	0:ac8863619623	3003	#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
jhon309	0:ac8863619623	3004	#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
jhon309	0:ac8863619623	3005	#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
jhon309	0:ac8863619623	3006	#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
jhon309	0:ac8863619623	3007	#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
jhon309	0:ac8863619623	3008	#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
jhon309	0:ac8863619623	3009	#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
jhon309	0:ac8863619623	3010	#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
jhon309	0:ac8863619623	3011	#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
jhon309	0:ac8863619623	3012	#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
jhon309	0:ac8863619623	3013	#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
jhon309	0:ac8863619623	3014	#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
jhon309	0:ac8863619623	3015	#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
jhon309	0:ac8863619623	3016	#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
jhon309	0:ac8863619623	3017	#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
jhon309	0:ac8863619623	3018	#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
jhon309	0:ac8863619623	3019
jhon309	0:ac8863619623	3020	/***************** Bit definition for GPIO_PUPDR register ****************/
jhon309	0:ac8863619623	3021	#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
jhon309	0:ac8863619623	3022	#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
jhon309	0:ac8863619623	3023	#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
jhon309	0:ac8863619623	3024	#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
jhon309	0:ac8863619623	3025	#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
jhon309	0:ac8863619623	3026	#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
jhon309	0:ac8863619623	3027	#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
jhon309	0:ac8863619623	3028	#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
jhon309	0:ac8863619623	3029	#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
jhon309	0:ac8863619623	3030	#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
jhon309	0:ac8863619623	3031	#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
jhon309	0:ac8863619623	3032	#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
jhon309	0:ac8863619623	3033	#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
jhon309	0:ac8863619623	3034	#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
jhon309	0:ac8863619623	3035	#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
jhon309	0:ac8863619623	3036	#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
jhon309	0:ac8863619623	3037	#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
jhon309	0:ac8863619623	3038	#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
jhon309	0:ac8863619623	3039	#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
jhon309	0:ac8863619623	3040	#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
jhon309	0:ac8863619623	3041	#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
jhon309	0:ac8863619623	3042	#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
jhon309	0:ac8863619623	3043	#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
jhon309	0:ac8863619623	3044	#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
jhon309	0:ac8863619623	3045	#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
jhon309	0:ac8863619623	3046	#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
jhon309	0:ac8863619623	3047	#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
jhon309	0:ac8863619623	3048	#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
jhon309	0:ac8863619623	3049	#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
jhon309	0:ac8863619623	3050	#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
jhon309	0:ac8863619623	3051	#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
jhon309	0:ac8863619623	3052	#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
jhon309	0:ac8863619623	3053	#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
jhon309	0:ac8863619623	3054	#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
jhon309	0:ac8863619623	3055	#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
jhon309	0:ac8863619623	3056	#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
jhon309	0:ac8863619623	3057	#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
jhon309	0:ac8863619623	3058	#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
jhon309	0:ac8863619623	3059	#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
jhon309	0:ac8863619623	3060	#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
jhon309	0:ac8863619623	3061	#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
jhon309	0:ac8863619623	3062	#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
jhon309	0:ac8863619623	3063	#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
jhon309	0:ac8863619623	3064	#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
jhon309	0:ac8863619623	3065	#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
jhon309	0:ac8863619623	3066	#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
jhon309	0:ac8863619623	3067	#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
jhon309	0:ac8863619623	3068	#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
jhon309	0:ac8863619623	3069
jhon309	0:ac8863619623	3070	/***************** Bit definition for GPIO_IDR register *****************/
jhon309	0:ac8863619623	3071	#define GPIO_IDR_0 ((uint32_t)0x00000001)
jhon309	0:ac8863619623	3072	#define GPIO_IDR_1 ((uint32_t)0x00000002)
jhon309	0:ac8863619623	3073	#define GPIO_IDR_2 ((uint32_t)0x00000004)
jhon309	0:ac8863619623	3074	#define GPIO_IDR_3 ((uint32_t)0x00000008)
jhon309	0:ac8863619623	3075	#define GPIO_IDR_4 ((uint32_t)0x00000010)
jhon309	0:ac8863619623	3076	#define GPIO_IDR_5 ((uint32_t)0x00000020)
jhon309	0:ac8863619623	3077	#define GPIO_IDR_6 ((uint32_t)0x00000040)
jhon309	0:ac8863619623	3078	#define GPIO_IDR_7 ((uint32_t)0x00000080)
jhon309	0:ac8863619623	3079	#define GPIO_IDR_8 ((uint32_t)0x00000100)
jhon309	0:ac8863619623	3080	#define GPIO_IDR_9 ((uint32_t)0x00000200)
jhon309	0:ac8863619623	3081	#define GPIO_IDR_10 ((uint32_t)0x00000400)
jhon309	0:ac8863619623	3082	#define GPIO_IDR_11 ((uint32_t)0x00000800)
jhon309	0:ac8863619623	3083	#define GPIO_IDR_12 ((uint32_t)0x00001000)
jhon309	0:ac8863619623	3084	#define GPIO_IDR_13 ((uint32_t)0x00002000)
jhon309	0:ac8863619623	3085	#define GPIO_IDR_14 ((uint32_t)0x00004000)
jhon309	0:ac8863619623	3086	#define GPIO_IDR_15 ((uint32_t)0x00008000)
jhon309	0:ac8863619623	3087
jhon309	0:ac8863619623	3088	/**************** Bit definition for GPIO_ODR register ******************/
jhon309	0:ac8863619623	3089	#define GPIO_ODR_0 ((uint32_t)0x00000001)
jhon309	0:ac8863619623	3090	#define GPIO_ODR_1 ((uint32_t)0x00000002)
jhon309	0:ac8863619623	3091	#define GPIO_ODR_2 ((uint32_t)0x00000004)
jhon309	0:ac8863619623	3092	#define GPIO_ODR_3 ((uint32_t)0x00000008)
jhon309	0:ac8863619623	3093	#define GPIO_ODR_4 ((uint32_t)0x00000010)
jhon309	0:ac8863619623	3094	#define GPIO_ODR_5 ((uint32_t)0x00000020)
jhon309	0:ac8863619623	3095	#define GPIO_ODR_6 ((uint32_t)0x00000040)
jhon309	0:ac8863619623	3096	#define GPIO_ODR_7 ((uint32_t)0x00000080)
jhon309	0:ac8863619623	3097	#define GPIO_ODR_8 ((uint32_t)0x00000100)
jhon309	0:ac8863619623	3098	#define GPIO_ODR_9 ((uint32_t)0x00000200)
jhon309	0:ac8863619623	3099	#define GPIO_ODR_10 ((uint32_t)0x00000400)
jhon309	0:ac8863619623	3100	#define GPIO_ODR_11 ((uint32_t)0x00000800)
jhon309	0:ac8863619623	3101	#define GPIO_ODR_12 ((uint32_t)0x00001000)
jhon309	0:ac8863619623	3102	#define GPIO_ODR_13 ((uint32_t)0x00002000)
jhon309	0:ac8863619623	3103	#define GPIO_ODR_14 ((uint32_t)0x00004000)
jhon309	0:ac8863619623	3104	#define GPIO_ODR_15 ((uint32_t)0x00008000)
jhon309	0:ac8863619623	3105
jhon309	0:ac8863619623	3106	/**************** Bit definition for GPIO_BSRR register ******************/
jhon309	0:ac8863619623	3107	#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
jhon309	0:ac8863619623	3108	#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
jhon309	0:ac8863619623	3109	#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
jhon309	0:ac8863619623	3110	#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
jhon309	0:ac8863619623	3111	#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
jhon309	0:ac8863619623	3112	#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
jhon309	0:ac8863619623	3113	#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
jhon309	0:ac8863619623	3114	#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
jhon309	0:ac8863619623	3115	#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
jhon309	0:ac8863619623	3116	#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
jhon309	0:ac8863619623	3117	#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
jhon309	0:ac8863619623	3118	#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
jhon309	0:ac8863619623	3119	#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
jhon309	0:ac8863619623	3120	#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
jhon309	0:ac8863619623	3121	#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
jhon309	0:ac8863619623	3122	#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
jhon309	0:ac8863619623	3123	#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
jhon309	0:ac8863619623	3124	#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
jhon309	0:ac8863619623	3125	#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
jhon309	0:ac8863619623	3126	#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
jhon309	0:ac8863619623	3127	#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
jhon309	0:ac8863619623	3128	#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
jhon309	0:ac8863619623	3129	#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
jhon309	0:ac8863619623	3130	#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
jhon309	0:ac8863619623	3131	#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
jhon309	0:ac8863619623	3132	#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
jhon309	0:ac8863619623	3133	#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
jhon309	0:ac8863619623	3134	#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
jhon309	0:ac8863619623	3135	#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
jhon309	0:ac8863619623	3136	#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
jhon309	0:ac8863619623	3137	#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
jhon309	0:ac8863619623	3138	#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
jhon309	0:ac8863619623	3139
jhon309	0:ac8863619623	3140	/**************** Bit definition for GPIO_LCKR register ******************/
jhon309	0:ac8863619623	3141	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
jhon309	0:ac8863619623	3142	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
jhon309	0:ac8863619623	3143	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
jhon309	0:ac8863619623	3144	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
jhon309	0:ac8863619623	3145	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
jhon309	0:ac8863619623	3146	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
jhon309	0:ac8863619623	3147	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
jhon309	0:ac8863619623	3148	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
jhon309	0:ac8863619623	3149	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
jhon309	0:ac8863619623	3150	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
jhon309	0:ac8863619623	3151	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
jhon309	0:ac8863619623	3152	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
jhon309	0:ac8863619623	3153	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
jhon309	0:ac8863619623	3154	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
jhon309	0:ac8863619623	3155	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
jhon309	0:ac8863619623	3156	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
jhon309	0:ac8863619623	3157	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
jhon309	0:ac8863619623	3158
jhon309	0:ac8863619623	3159	/**************** Bit definition for GPIO_AFRL register ******************/
jhon309	0:ac8863619623	3160	#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
jhon309	0:ac8863619623	3161	#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
jhon309	0:ac8863619623	3162	#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
jhon309	0:ac8863619623	3163	#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
jhon309	0:ac8863619623	3164	#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
jhon309	0:ac8863619623	3165	#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
jhon309	0:ac8863619623	3166	#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
jhon309	0:ac8863619623	3167	#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
jhon309	0:ac8863619623	3168
jhon309	0:ac8863619623	3169	/**************** Bit definition for GPIO_AFRH register ******************/
jhon309	0:ac8863619623	3170	#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
jhon309	0:ac8863619623	3171	#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
jhon309	0:ac8863619623	3172	#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
jhon309	0:ac8863619623	3173	#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
jhon309	0:ac8863619623	3174	#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
jhon309	0:ac8863619623	3175	#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
jhon309	0:ac8863619623	3176	#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
jhon309	0:ac8863619623	3177	#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
jhon309	0:ac8863619623	3178
jhon309	0:ac8863619623	3179	/**************** Bit definition for GPIO_BRR register *******************/
jhon309	0:ac8863619623	3180	#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
jhon309	0:ac8863619623	3181	#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
jhon309	0:ac8863619623	3182	#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
jhon309	0:ac8863619623	3183	#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
jhon309	0:ac8863619623	3184	#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
jhon309	0:ac8863619623	3185	#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
jhon309	0:ac8863619623	3186	#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
jhon309	0:ac8863619623	3187	#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
jhon309	0:ac8863619623	3188	#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
jhon309	0:ac8863619623	3189	#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
jhon309	0:ac8863619623	3190	#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
jhon309	0:ac8863619623	3191	#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
jhon309	0:ac8863619623	3192	#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
jhon309	0:ac8863619623	3193	#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
jhon309	0:ac8863619623	3194	#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
jhon309	0:ac8863619623	3195	#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
jhon309	0:ac8863619623	3196
jhon309	0:ac8863619623	3197	/******************************************************************************/
jhon309	0:ac8863619623	3198	/* */
jhon309	0:ac8863619623	3199	/* Inter-integrated Circuit Interface (I2C) */
jhon309	0:ac8863619623	3200	/* */
jhon309	0:ac8863619623	3201	/******************************************************************************/
jhon309	0:ac8863619623	3202
jhon309	0:ac8863619623	3203	/***************** Bit definition for I2C_CR1 register *****************/
jhon309	0:ac8863619623	3204	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral enable /
jhon309	0:ac8863619623	3205	#define I2C_CR1_TXIE ((uint32_t)0x00000002) /!< TX interrupt enable /
jhon309	0:ac8863619623	3206	#define I2C_CR1_RXIE ((uint32_t)0x00000004) /!< RX interrupt enable /
jhon309	0:ac8863619623	3207	#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /!< Address match interrupt enable /
jhon309	0:ac8863619623	3208	#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /!< NACK received interrupt enable /
jhon309	0:ac8863619623	3209	#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /!< STOP detection interrupt enable /
jhon309	0:ac8863619623	3210	#define I2C_CR1_TCIE ((uint32_t)0x00000040) /!< Transfer complete interrupt enable /
jhon309	0:ac8863619623	3211	#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /!< Errors interrupt enable /
jhon309	0:ac8863619623	3212	#define I2C_CR1_DFN ((uint32_t)0x00000F00) /!< Digital noise filter /
jhon309	0:ac8863619623	3213	#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /!< Analog noise filter OFF /
jhon309	0:ac8863619623	3214	#define I2C_CR1_SWRST ((uint32_t)0x00002000) /!< Software reset /
jhon309	0:ac8863619623	3215	#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /!< DMA transmission requests enable /
jhon309	0:ac8863619623	3216	#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /!< DMA reception requests enable /
jhon309	0:ac8863619623	3217	#define I2C_CR1_SBC ((uint32_t)0x00010000) /!< Slave byte control /
jhon309	0:ac8863619623	3218	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /!< Clock stretching disable /
jhon309	0:ac8863619623	3219	#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /!< Wakeup from STOP enable /
jhon309	0:ac8863619623	3220	#define I2C_CR1_GCEN ((uint32_t)0x00080000) /!< General call enable /
jhon309	0:ac8863619623	3221	#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /!< SMBus host address enable /
jhon309	0:ac8863619623	3222	#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /!< SMBus device default address enable /
jhon309	0:ac8863619623	3223	#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /!< SMBus alert enable /
jhon309	0:ac8863619623	3224	#define I2C_CR1_PECEN ((uint32_t)0x00800000) /!< PEC enable /
jhon309	0:ac8863619623	3225
jhon309	0:ac8863619623	3226	/**************** Bit definition for I2C_CR2 register ******************/
jhon309	0:ac8863619623	3227	#define I2C_CR2_SADD ((uint32_t)0x000003FF) /!< Slave address (master mode) /
jhon309	0:ac8863619623	3228	#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /!< Transfer direction (master mode) /
jhon309	0:ac8863619623	3229	#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /!< 10-bit addressing mode (master mode) /
jhon309	0:ac8863619623	3230	#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /!< 10-bit address header only read direction (master mode) /
jhon309	0:ac8863619623	3231	#define I2C_CR2_START ((uint32_t)0x00002000) /!< START generation /
jhon309	0:ac8863619623	3232	#define I2C_CR2_STOP ((uint32_t)0x00004000) /!< STOP generation (master mode) /
jhon309	0:ac8863619623	3233	#define I2C_CR2_NACK ((uint32_t)0x00008000) /!< NACK generation (slave mode) /
jhon309	0:ac8863619623	3234	#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /!< Number of bytes /
jhon309	0:ac8863619623	3235	#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /!< NBYTES reload mode /
jhon309	0:ac8863619623	3236	#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /!< Automatic end mode (master mode) /
jhon309	0:ac8863619623	3237	#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /!< Packet error checking byte /
jhon309	0:ac8863619623	3238
jhon309	0:ac8863619623	3239	/***************** Bit definition for I2C_OAR1 register ****************/
jhon309	0:ac8863619623	3240	#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /!< Interface own address 1 /
jhon309	0:ac8863619623	3241	#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /!< Own address 1 10-bit mode /
jhon309	0:ac8863619623	3242	#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /!< Own address 1 enable /
jhon309	0:ac8863619623	3243
jhon309	0:ac8863619623	3244	/***************** Bit definition for I2C_OAR2 register ****************/
jhon309	0:ac8863619623	3245	#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /!< Interface own address 2 /
jhon309	0:ac8863619623	3246	#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /!< Own address 2 masks /
jhon309	0:ac8863619623	3247	#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /!< Own address 2 enable /
jhon309	0:ac8863619623	3248
jhon309	0:ac8863619623	3249	/***************** Bit definition for I2C_TIMINGR register **************/
jhon309	0:ac8863619623	3250	#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /!< SCL low period (master mode) /
jhon309	0:ac8863619623	3251	#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /!< SCL high period (master mode) /
jhon309	0:ac8863619623	3252	#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /!< Data hold time /
jhon309	0:ac8863619623	3253	#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /!< Data setup time /
jhon309	0:ac8863619623	3254	#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /!< Timings prescaler /
jhon309	0:ac8863619623	3255
jhon309	0:ac8863619623	3256	/***************** Bit definition for I2C_TIMEOUTR register **************/
jhon309	0:ac8863619623	3257	#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /!< Bus timeout A /
jhon309	0:ac8863619623	3258	#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /!< Idle clock timeout detection /
jhon309	0:ac8863619623	3259	#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /!< Clock timeout enable /
jhon309	0:ac8863619623	3260	#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /!< Bus timeout B/
jhon309	0:ac8863619623	3261	#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /!< Extended clock timeout enable /
jhon309	0:ac8863619623	3262
jhon309	0:ac8863619623	3263	/**************** Bit definition for I2C_ISR register ******************/
jhon309	0:ac8863619623	3264	#define I2C_ISR_TXE ((uint32_t)0x00000001) /!< Transmit data register empty /
jhon309	0:ac8863619623	3265	#define I2C_ISR_TXIS ((uint32_t)0x00000002) /!< Transmit interrupt status /
jhon309	0:ac8863619623	3266	#define I2C_ISR_RXNE ((uint32_t)0x00000004) /!< Receive data register not empty /
jhon309	0:ac8863619623	3267	#define I2C_ISR_ADDR ((uint32_t)0x00000008) /!< Address matched (slave mode)/
jhon309	0:ac8863619623	3268	#define I2C_ISR_NACKF ((uint32_t)0x00000010) /!< NACK received flag /
jhon309	0:ac8863619623	3269	#define I2C_ISR_STOPF ((uint32_t)0x00000020) /!< STOP detection flag /
jhon309	0:ac8863619623	3270	#define I2C_ISR_TC ((uint32_t)0x00000040) /!< Transfer complete (master mode) /
jhon309	0:ac8863619623	3271	#define I2C_ISR_TCR ((uint32_t)0x00000080) /!< Transfer complete reload /
jhon309	0:ac8863619623	3272	#define I2C_ISR_BERR ((uint32_t)0x00000100) /!< Bus error /
jhon309	0:ac8863619623	3273	#define I2C_ISR_ARLO ((uint32_t)0x00000200) /!< Arbitration lost /
jhon309	0:ac8863619623	3274	#define I2C_ISR_OVR ((uint32_t)0x00000400) /!< Overrun/Underrun /
jhon309	0:ac8863619623	3275	#define I2C_ISR_PECERR ((uint32_t)0x00000800) /!< PEC error in reception /
jhon309	0:ac8863619623	3276	#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /!< Timeout or Tlow detection flag /
jhon309	0:ac8863619623	3277	#define I2C_ISR_ALERT ((uint32_t)0x00002000) /!< SMBus alert /
jhon309	0:ac8863619623	3278	#define I2C_ISR_BUSY ((uint32_t)0x00008000) /!< Bus busy /
jhon309	0:ac8863619623	3279	#define I2C_ISR_DIR ((uint32_t)0x00010000) /!< Transfer direction (slave mode) /
jhon309	0:ac8863619623	3280	#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /!< Address match code (slave mode) /
jhon309	0:ac8863619623	3281
jhon309	0:ac8863619623	3282	/**************** Bit definition for I2C_ICR register ******************/
jhon309	0:ac8863619623	3283	#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /!< Address matched clear flag /
jhon309	0:ac8863619623	3284	#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /!< NACK clear flag /
jhon309	0:ac8863619623	3285	#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /!< STOP detection clear flag /
jhon309	0:ac8863619623	3286	#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /!< Bus error clear flag /
jhon309	0:ac8863619623	3287	#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /!< Arbitration lost clear flag /
jhon309	0:ac8863619623	3288	#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /!< Overrun/Underrun clear flag /
jhon309	0:ac8863619623	3289	#define I2C_ICR_PECCF ((uint32_t)0x00000800) /!< PAC error clear flag /
jhon309	0:ac8863619623	3290	#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /!< Timeout clear flag /
jhon309	0:ac8863619623	3291	#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /!< Alert clear flag /
jhon309	0:ac8863619623	3292
jhon309	0:ac8863619623	3293	/**************** Bit definition for I2C_PECR register *****************/
jhon309	0:ac8863619623	3294	#define I2C_PECR_PEC ((uint32_t)0x000000FF) /!< PEC register /
jhon309	0:ac8863619623	3295
jhon309	0:ac8863619623	3296	/**************** Bit definition for I2C_RXDR register *******************/
jhon309	0:ac8863619623	3297	#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /!< 8-bit receive data /
jhon309	0:ac8863619623	3298
jhon309	0:ac8863619623	3299	/**************** Bit definition for I2C_TXDR register *****************/
jhon309	0:ac8863619623	3300	#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /!< 8-bit transmit data /
jhon309	0:ac8863619623	3301
jhon309	0:ac8863619623	3302	/*****************************************************************************/
jhon309	0:ac8863619623	3303	/* */
jhon309	0:ac8863619623	3304	/* Independent WATCHDOG (IWDG) */
jhon309	0:ac8863619623	3305	/* */
jhon309	0:ac8863619623	3306	/*****************************************************************************/
jhon309	0:ac8863619623	3307	/***************** Bit definition for IWDG_KR register *****************/
jhon309	0:ac8863619623	3308	#define IWDG_KR_KEY ((uint32_t)0xFFFF) /!< Key value (write only, read 0000h) /
jhon309	0:ac8863619623	3309
jhon309	0:ac8863619623	3310	/***************** Bit definition for IWDG_PR register *****************/
jhon309	0:ac8863619623	3311	#define IWDG_PR_PR ((uint32_t)0x07) /!< PR[2:0] (Prescaler divider) /
jhon309	0:ac8863619623	3312	#define IWDG_PR_PR_0 ((uint32_t)0x01) /!< Bit 0 /
jhon309	0:ac8863619623	3313	#define IWDG_PR_PR_1 ((uint32_t)0x02) /!< Bit 1 /
jhon309	0:ac8863619623	3314	#define IWDG_PR_PR_2 ((uint32_t)0x04) /!< Bit 2 /
jhon309	0:ac8863619623	3315
jhon309	0:ac8863619623	3316	/***************** Bit definition for IWDG_RLR register ****************/
jhon309	0:ac8863619623	3317	#define IWDG_RLR_RL ((uint32_t)0x0FFF) /!< Watchdog counter reload value /
jhon309	0:ac8863619623	3318
jhon309	0:ac8863619623	3319	/***************** Bit definition for IWDG_SR register *****************/
jhon309	0:ac8863619623	3320	#define IWDG_SR_PVU ((uint32_t)0x01) /!< Watchdog prescaler value update /
jhon309	0:ac8863619623	3321	#define IWDG_SR_RVU ((uint32_t)0x02) /!< Watchdog counter reload value update /
jhon309	0:ac8863619623	3322	#define IWDG_SR_WVU ((uint32_t)0x04) /!< Watchdog counter window value update /
jhon309	0:ac8863619623	3323
jhon309	0:ac8863619623	3324	/***************** Bit definition for IWDG_KR register *****************/
jhon309	0:ac8863619623	3325	#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /!< Watchdog counter window value /
jhon309	0:ac8863619623	3326
jhon309	0:ac8863619623	3327	/*****************************************************************************/
jhon309	0:ac8863619623	3328	/* */
jhon309	0:ac8863619623	3329	/* Power Control (PWR) */
jhon309	0:ac8863619623	3330	/* */
jhon309	0:ac8863619623	3331	/*****************************************************************************/
jhon309	0:ac8863619623	3332
jhon309	0:ac8863619623	3333	/****************** Bit definition for PWR_CR register *****************/
jhon309	0:ac8863619623	3334	#define PWR_CR_LPDS ((uint32_t)0x00000001) /!< Low-power Deepsleep /
jhon309	0:ac8863619623	3335	#define PWR_CR_PDDS ((uint32_t)0x00000002) /!< Power Down Deepsleep /
jhon309	0:ac8863619623	3336	#define PWR_CR_CWUF ((uint32_t)0x00000004) /!< Clear Wakeup Flag /
jhon309	0:ac8863619623	3337	#define PWR_CR_CSBF ((uint32_t)0x00000008) /!< Clear Standby Flag /
jhon309	0:ac8863619623	3338	#define PWR_CR_PVDE ((uint32_t)0x00000010) /!< Power Voltage Detector Enable /
jhon309	0:ac8863619623	3339
jhon309	0:ac8863619623	3340	#define PWR_CR_PLS ((uint32_t)0x000000E0) /!< PLS[2:0] bits (PVD Level Selection) /
jhon309	0:ac8863619623	3341	#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /!< Bit 0 /
jhon309	0:ac8863619623	3342	#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /!< Bit 1 /
jhon309	0:ac8863619623	3343	#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /!< Bit 2 /
jhon309	0:ac8863619623	3344
jhon309	0:ac8863619623	3345	/!< PVD level configuration /
jhon309	0:ac8863619623	3346	#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /!< PVD level 0 /
jhon309	0:ac8863619623	3347	#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /!< PVD level 1 /
jhon309	0:ac8863619623	3348	#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /!< PVD level 2 /
jhon309	0:ac8863619623	3349	#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /!< PVD level 3 /
jhon309	0:ac8863619623	3350	#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /!< PVD level 4 /
jhon309	0:ac8863619623	3351	#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /!< PVD level 5 /
jhon309	0:ac8863619623	3352	#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /!< PVD level 6 /
jhon309	0:ac8863619623	3353	#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /!< PVD level 7 /
jhon309	0:ac8863619623	3354
jhon309	0:ac8863619623	3355	#define PWR_CR_DBP ((uint32_t)0x00000100) /!< Disable Backup Domain write protection /
jhon309	0:ac8863619623	3356
jhon309	0:ac8863619623	3357	/***************** Bit definition for PWR_CSR register *****************/
jhon309	0:ac8863619623	3358	#define PWR_CSR_WUF ((uint32_t)0x00000001) /!< Wakeup Flag /
jhon309	0:ac8863619623	3359	#define PWR_CSR_SBF ((uint32_t)0x00000002) /!< Standby Flag /
jhon309	0:ac8863619623	3360	#define PWR_CSR_PVDO ((uint32_t)0x00000004) /!< PVD Output /
jhon309	0:ac8863619623	3361	#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /!< Internal voltage reference (VREFINT) ready flag /
jhon309	0:ac8863619623	3362
jhon309	0:ac8863619623	3363	#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /!< Enable WKUP pin 1 /
jhon309	0:ac8863619623	3364	#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /!< Enable WKUP pin 2 /
jhon309	0:ac8863619623	3365	#define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /!< Enable WKUP pin 3 /
jhon309	0:ac8863619623	3366	#define PWR_CSR_EWUP4 ((uint32_t)0x00000800) /!< Enable WKUP pin 4 /
jhon309	0:ac8863619623	3367	#define PWR_CSR_EWUP5 ((uint32_t)0x00001000) /!< Enable WKUP pin 5 /
jhon309	0:ac8863619623	3368	#define PWR_CSR_EWUP6 ((uint32_t)0x00002000) /!< Enable WKUP pin 6 /
jhon309	0:ac8863619623	3369	#define PWR_CSR_EWUP7 ((uint32_t)0x00004000) /!< Enable WKUP pin 7 /
jhon309	0:ac8863619623	3370	#define PWR_CSR_EWUP8 ((uint32_t)0x00008000) /!< Enable WKUP pin 8 /
jhon309	0:ac8863619623	3371
jhon309	0:ac8863619623	3372	/*****************************************************************************/
jhon309	0:ac8863619623	3373	/* */
jhon309	0:ac8863619623	3374	/* Reset and Clock Control */
jhon309	0:ac8863619623	3375	/* */
jhon309	0:ac8863619623	3376	/*****************************************************************************/
jhon309	0:ac8863619623	3377
jhon309	0:ac8863619623	3378	/****************** Bit definition for RCC_CR register *****************/
jhon309	0:ac8863619623	3379	#define RCC_CR_HSION ((uint32_t)0x00000001) /!< Internal High Speed clock enable /
jhon309	0:ac8863619623	3380	#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /!< Internal High Speed clock ready flag /
jhon309	0:ac8863619623	3381
jhon309	0:ac8863619623	3382	#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /!< Internal High Speed clock trimming /
jhon309	0:ac8863619623	3383	#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /!<Bit 0 /
jhon309	0:ac8863619623	3384	#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /!<Bit 1 /
jhon309	0:ac8863619623	3385	#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /!<Bit 2 /
jhon309	0:ac8863619623	3386	#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /!<Bit 3 /
jhon309	0:ac8863619623	3387	#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /!<Bit 4 /
jhon309	0:ac8863619623	3388
jhon309	0:ac8863619623	3389	#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /!< Internal High Speed clock Calibration /
jhon309	0:ac8863619623	3390	#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /!<Bit 0 /
jhon309	0:ac8863619623	3391	#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /!<Bit 1 /
jhon309	0:ac8863619623	3392	#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /!<Bit 2 /
jhon309	0:ac8863619623	3393	#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /!<Bit 3 /
jhon309	0:ac8863619623	3394	#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /!<Bit 4 /
jhon309	0:ac8863619623	3395	#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /!<Bit 5 /
jhon309	0:ac8863619623	3396	#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /!<Bit 6 /
jhon309	0:ac8863619623	3397	#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /!<Bit 7 /
jhon309	0:ac8863619623	3398
jhon309	0:ac8863619623	3399	#define RCC_CR_HSEON ((uint32_t)0x00010000) /!< External High Speed clock enable /
jhon309	0:ac8863619623	3400	#define RCC_CR_HSERDY ((uint32_t)0x00020000) /!< External High Speed clock ready flag /
jhon309	0:ac8863619623	3401	#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /!< External High Speed clock Bypass /
jhon309	0:ac8863619623	3402	#define RCC_CR_CSSON ((uint32_t)0x00080000) /!< Clock Security System enable /
jhon309	0:ac8863619623	3403	#define RCC_CR_PLLON ((uint32_t)0x01000000) /!< PLL enable /
jhon309	0:ac8863619623	3404	#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /!< PLL clock ready flag /
jhon309	0:ac8863619623	3405
jhon309	0:ac8863619623	3406	/****************** Bit definition for RCC_CFGR register ***************/
jhon309	0:ac8863619623	3407	/!< SW configuration /
jhon309	0:ac8863619623	3408	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
jhon309	0:ac8863619623	3409	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
jhon309	0:ac8863619623	3410	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
jhon309	0:ac8863619623	3411
jhon309	0:ac8863619623	3412	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
jhon309	0:ac8863619623	3413	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
jhon309	0:ac8863619623	3414	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
jhon309	0:ac8863619623	3415	#define RCC_CFGR_SW_HSI48 ((uint32_t)0x00000003) /!< HSI48 selected as system clock /
jhon309	0:ac8863619623	3416
jhon309	0:ac8863619623	3417	/!< SWS configuration /
jhon309	0:ac8863619623	3418	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
jhon309	0:ac8863619623	3419	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
jhon309	0:ac8863619623	3420	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
jhon309	0:ac8863619623	3421
jhon309	0:ac8863619623	3422	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
jhon309	0:ac8863619623	3423	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
jhon309	0:ac8863619623	3424	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
jhon309	0:ac8863619623	3425	#define RCC_CFGR_SWS_HSI48 ((uint32_t)0x0000000C) /!< HSI48 oscillator used as system clock /
jhon309	0:ac8863619623	3426
jhon309	0:ac8863619623	3427	/!< HPRE configuration /
jhon309	0:ac8863619623	3428	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
jhon309	0:ac8863619623	3429	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
jhon309	0:ac8863619623	3430	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
jhon309	0:ac8863619623	3431	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
jhon309	0:ac8863619623	3432	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
jhon309	0:ac8863619623	3433
jhon309	0:ac8863619623	3434	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
jhon309	0:ac8863619623	3435	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
jhon309	0:ac8863619623	3436	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
jhon309	0:ac8863619623	3437	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
jhon309	0:ac8863619623	3438	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
jhon309	0:ac8863619623	3439	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
jhon309	0:ac8863619623	3440	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
jhon309	0:ac8863619623	3441	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
jhon309	0:ac8863619623	3442	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
jhon309	0:ac8863619623	3443
jhon309	0:ac8863619623	3444	/!< PPRE configuration /
jhon309	0:ac8863619623	3445	#define RCC_CFGR_PPRE ((uint32_t)0x00000700) /!< PRE[2:0] bits (APB prescaler) /
jhon309	0:ac8863619623	3446	#define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /!< Bit 0 /
jhon309	0:ac8863619623	3447	#define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /!< Bit 1 /
jhon309	0:ac8863619623	3448	#define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /!< Bit 2 /
jhon309	0:ac8863619623	3449
jhon309	0:ac8863619623	3450	#define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
jhon309	0:ac8863619623	3451	#define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
jhon309	0:ac8863619623	3452	#define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
jhon309	0:ac8863619623	3453	#define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
jhon309	0:ac8863619623	3454	#define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
jhon309	0:ac8863619623	3455
jhon309	0:ac8863619623	3456	/!< ADCPPRE configuration /
jhon309	0:ac8863619623	3457	#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /!< ADCPRE bit (ADC prescaler) /
jhon309	0:ac8863619623	3458
jhon309	0:ac8863619623	3459	#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /!< PCLK divided by 2 /
jhon309	0:ac8863619623	3460	#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /!< PCLK divided by 4 /
jhon309	0:ac8863619623	3461
jhon309	0:ac8863619623	3462	#define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /!< PLL entry clock source /
jhon309	0:ac8863619623	3463	#define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /!< HSI clock divided by 2 selected as PLL entry clock source /
jhon309	0:ac8863619623	3464	#define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /!< HSI/PREDIV clock selected as PLL entry clock source /
jhon309	0:ac8863619623	3465	#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /!< HSE/PREDIV clock selected as PLL entry clock source /
jhon309	0:ac8863619623	3466	#define RCC_CFGR_PLLSRC_HSI48_PREDIV ((uint32_t)0x00018000) /!< HSI48/PREDIV clock selected as PLL entry clock source /
jhon309	0:ac8863619623	3467
jhon309	0:ac8863619623	3468	#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /!< HSE divider for PLL entry /
jhon309	0:ac8863619623	3469	#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /!< HSE/PREDIV clock not divided for PLL entry /
jhon309	0:ac8863619623	3470	#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /!< HSE/PREDIV clock divided by 2 for PLL entry /
jhon309	0:ac8863619623	3471
jhon309	0:ac8863619623	3472	/!< PLLMUL configuration /
jhon309	0:ac8863619623	3473	#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
jhon309	0:ac8863619623	3474	#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /!< Bit 0 /
jhon309	0:ac8863619623	3475	#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /!< Bit 1 /
jhon309	0:ac8863619623	3476	#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /!< Bit 2 /
jhon309	0:ac8863619623	3477	#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /!< Bit 3 /
jhon309	0:ac8863619623	3478
jhon309	0:ac8863619623	3479	#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /!< PLL input clock2 */
jhon309	0:ac8863619623	3480	#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /!< PLL input clock3 */
jhon309	0:ac8863619623	3481	#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /!< PLL input clock4 */
jhon309	0:ac8863619623	3482	#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /!< PLL input clock5 */
jhon309	0:ac8863619623	3483	#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /!< PLL input clock6 */
jhon309	0:ac8863619623	3484	#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /!< PLL input clock7 */
jhon309	0:ac8863619623	3485	#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /!< PLL input clock8 */
jhon309	0:ac8863619623	3486	#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /!< PLL input clock9 */
jhon309	0:ac8863619623	3487	#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /!< PLL input clock10 /
jhon309	0:ac8863619623	3488	#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /!< PLL input clock11 */
jhon309	0:ac8863619623	3489	#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /!< PLL input clock12 */
jhon309	0:ac8863619623	3490	#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /!< PLL input clock13 */
jhon309	0:ac8863619623	3491	#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /!< PLL input clock14 */
jhon309	0:ac8863619623	3492	#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /!< PLL input clock15 */
jhon309	0:ac8863619623	3493	#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /!< PLL input clock16 */
jhon309	0:ac8863619623	3494
jhon309	0:ac8863619623	3495	/!< USB configuration /
jhon309	0:ac8863619623	3496	#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /!< USB prescaler /
jhon309	0:ac8863619623	3497
jhon309	0:ac8863619623	3498	/!< MCO configuration /
jhon309	0:ac8863619623	3499	#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /!< MCO[3:0] bits (Microcontroller Clock Output) /
jhon309	0:ac8863619623	3500	#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /!< Bit 0 /
jhon309	0:ac8863619623	3501	#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /!< Bit 1 /
jhon309	0:ac8863619623	3502	#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /!< Bit 2 /
jhon309	0:ac8863619623	3503	#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /!< Bit 3 /
jhon309	0:ac8863619623	3504
jhon309	0:ac8863619623	3505	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
jhon309	0:ac8863619623	3506	#define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /!< HSI14 clock selected as MCO source /
jhon309	0:ac8863619623	3507	#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /!< LSI clock selected as MCO source /
jhon309	0:ac8863619623	3508	#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /!< LSE clock selected as MCO source /
jhon309	0:ac8863619623	3509	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /!< System clock selected as MCO source /
jhon309	0:ac8863619623	3510	#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /!< HSI clock selected as MCO source /
jhon309	0:ac8863619623	3511	#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /!< HSE clock selected as MCO source /
jhon309	0:ac8863619623	3512	#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /!< PLL clock divided by 2 selected as MCO source /
jhon309	0:ac8863619623	3513	#define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /!< HSI48 clock selected as MCO source /
jhon309	0:ac8863619623	3514
jhon309	0:ac8863619623	3515	#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /!< MCO prescaler /
jhon309	0:ac8863619623	3516	#define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /!< MCO is divided by 1 /
jhon309	0:ac8863619623	3517	#define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /!< MCO is divided by 2 /
jhon309	0:ac8863619623	3518	#define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /!< MCO is divided by 4 /
jhon309	0:ac8863619623	3519	#define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /!< MCO is divided by 8 /
jhon309	0:ac8863619623	3520	#define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /!< MCO is divided by 16 /
jhon309	0:ac8863619623	3521	#define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /!< MCO is divided by 32 /
jhon309	0:ac8863619623	3522	#define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /!< MCO is divided by 64 /
jhon309	0:ac8863619623	3523	#define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /!< MCO is divided by 128 /
jhon309	0:ac8863619623	3524
jhon309	0:ac8863619623	3525	#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /!< PLL is not divided to MCO /
jhon309	0:ac8863619623	3526
jhon309	0:ac8863619623	3527	/!<*************** Bit definition for RCC_CIR register ***************/
jhon309	0:ac8863619623	3528	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
jhon309	0:ac8863619623	3529	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
jhon309	0:ac8863619623	3530	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /!< HSI Ready Interrupt flag /
jhon309	0:ac8863619623	3531	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /!< HSE Ready Interrupt flag /
jhon309	0:ac8863619623	3532	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /!< PLL Ready Interrupt flag /
jhon309	0:ac8863619623	3533	#define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /!< HSI14 Ready Interrupt flag /
jhon309	0:ac8863619623	3534	#define RCC_CIR_HSI48RDYF ((uint32_t)0x00000040) /!< HSI48 Ready Interrupt flag /
jhon309	0:ac8863619623	3535	#define RCC_CIR_CSSF ((uint32_t)0x00000080) /!< Clock Security System Interrupt flag /
jhon309	0:ac8863619623	3536	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /!< LSI Ready Interrupt Enable /
jhon309	0:ac8863619623	3537	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /!< LSE Ready Interrupt Enable /
jhon309	0:ac8863619623	3538	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /!< HSI Ready Interrupt Enable /
jhon309	0:ac8863619623	3539	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /!< HSE Ready Interrupt Enable /
jhon309	0:ac8863619623	3540	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /!< PLL Ready Interrupt Enable /
jhon309	0:ac8863619623	3541	#define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /!< HSI14 Ready Interrupt Enable /
jhon309	0:ac8863619623	3542	#define RCC_CIR_HSI48RDYIE ((uint32_t)0x00004000) /!< HSI48 Ready Interrupt Enable /
jhon309	0:ac8863619623	3543	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /!< LSI Ready Interrupt Clear /
jhon309	0:ac8863619623	3544	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /!< LSE Ready Interrupt Clear /
jhon309	0:ac8863619623	3545	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /!< HSI Ready Interrupt Clear /
jhon309	0:ac8863619623	3546	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /!< HSE Ready Interrupt Clear /
jhon309	0:ac8863619623	3547	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /!< PLL Ready Interrupt Clear /
jhon309	0:ac8863619623	3548	#define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /!< HSI14 Ready Interrupt Clear /
jhon309	0:ac8863619623	3549	#define RCC_CIR_HSI48RDYC ((uint32_t)0x00400000) /!< HSI48 Ready Interrupt Clear /
jhon309	0:ac8863619623	3550	#define RCC_CIR_CSSC ((uint32_t)0x00800000) /!< Clock Security System Interrupt Clear /
jhon309	0:ac8863619623	3551
jhon309	0:ac8863619623	3552	/*************** Bit definition for RCC_APB2RSTR register **************/
jhon309	0:ac8863619623	3553	#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /!< SYSCFG clock reset /
jhon309	0:ac8863619623	3554	#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /!< ADC clock reset /
jhon309	0:ac8863619623	3555	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /!< TIM1 clock reset /
jhon309	0:ac8863619623	3556	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /!< SPI1 clock reset /
jhon309	0:ac8863619623	3557	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /!< USART1 clock reset /
jhon309	0:ac8863619623	3558	#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /!< TIM15 clock reset /
jhon309	0:ac8863619623	3559	#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /!< TIM16 clock reset /
jhon309	0:ac8863619623	3560	#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /!< TIM17 clock reset /
jhon309	0:ac8863619623	3561	#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /!< DBGMCU clock reset /
jhon309	0:ac8863619623	3562
jhon309	0:ac8863619623	3563	/!< Old ADC1 clock reset bit definition maintained for legacy purpose /
jhon309	0:ac8863619623	3564	#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
jhon309	0:ac8863619623	3565
jhon309	0:ac8863619623	3566	/*************** Bit definition for RCC_APB1RSTR register **************/
jhon309	0:ac8863619623	3567	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /!< Timer 2 clock reset /
jhon309	0:ac8863619623	3568	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /!< Timer 3 clock reset /
jhon309	0:ac8863619623	3569	#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /!< Timer 6 clock reset /
jhon309	0:ac8863619623	3570	#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /!< Timer 7 clock reset /
jhon309	0:ac8863619623	3571	#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /!< Timer 14 clock reset /
jhon309	0:ac8863619623	3572	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /!< Window Watchdog clock reset /
jhon309	0:ac8863619623	3573	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /!< SPI2 clock reset /
jhon309	0:ac8863619623	3574	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /!< USART 2 clock reset /
jhon309	0:ac8863619623	3575	#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /!< USART 3 clock reset /
jhon309	0:ac8863619623	3576	#define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /!< USART 4 clock reset /
jhon309	0:ac8863619623	3577	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /!< I2C 1 clock reset /
jhon309	0:ac8863619623	3578	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /!< I2C 2 clock reset /
jhon309	0:ac8863619623	3579	#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /!< USB clock reset /
jhon309	0:ac8863619623	3580	#define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /!< CAN clock reset /
jhon309	0:ac8863619623	3581	#define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /!< CRS clock reset /
jhon309	0:ac8863619623	3582	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /!< PWR clock reset /
jhon309	0:ac8863619623	3583	#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /!< DAC clock reset /
jhon309	0:ac8863619623	3584	#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /!< CEC clock reset /
jhon309	0:ac8863619623	3585
jhon309	0:ac8863619623	3586	/**************** Bit definition for RCC_AHBENR register ***************/
jhon309	0:ac8863619623	3587	#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /!< DMA1 clock enable /
jhon309	0:ac8863619623	3588	#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /!< SRAM interface clock enable /
jhon309	0:ac8863619623	3589	#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /!< FLITF clock enable /
jhon309	0:ac8863619623	3590	#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /!< CRC clock enable /
jhon309	0:ac8863619623	3591	#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /!< GPIOA clock enable /
jhon309	0:ac8863619623	3592	#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /!< GPIOB clock enable /
jhon309	0:ac8863619623	3593	#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /!< GPIOC clock enable /
jhon309	0:ac8863619623	3594	#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /!< GPIOD clock enable /
jhon309	0:ac8863619623	3595	#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /!< GPIOE clock enable /
jhon309	0:ac8863619623	3596	#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /!< GPIOF clock enable /
jhon309	0:ac8863619623	3597	#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /!< TS controller clock enable /
jhon309	0:ac8863619623	3598
jhon309	0:ac8863619623	3599	/* Old Bit definition maintained for legacy purpose */
jhon309	0:ac8863619623	3600	#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /!< DMA1 clock enable /
jhon309	0:ac8863619623	3601	#define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /!< TS clock enable /
jhon309	0:ac8863619623	3602
jhon309	0:ac8863619623	3603	/*************** Bit definition for RCC_APB2ENR register ***************/
jhon309	0:ac8863619623	3604	#define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /!< SYSCFG and comparator clock enable /
jhon309	0:ac8863619623	3605	#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /!< ADC1 clock enable /
jhon309	0:ac8863619623	3606	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /!< TIM1 clock enable /
jhon309	0:ac8863619623	3607	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /!< SPI1 clock enable /
jhon309	0:ac8863619623	3608	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /!< USART1 clock enable /
jhon309	0:ac8863619623	3609	#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /!< TIM15 clock enable /
jhon309	0:ac8863619623	3610	#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /!< TIM16 clock enable /
jhon309	0:ac8863619623	3611	#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /!< TIM17 clock enable /
jhon309	0:ac8863619623	3612	#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /!< DBGMCU clock enable /
jhon309	0:ac8863619623	3613
jhon309	0:ac8863619623	3614	/* Old Bit definition maintained for legacy purpose */
jhon309	0:ac8863619623	3615	#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /!< SYSCFG clock enable /
jhon309	0:ac8863619623	3616	#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /!< ADC1 clock enable /
jhon309	0:ac8863619623	3617
jhon309	0:ac8863619623	3618	/*************** Bit definition for RCC_APB1ENR register ***************/
jhon309	0:ac8863619623	3619	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /!< Timer 2 clock enable /
jhon309	0:ac8863619623	3620	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /!< Timer 3 clock enable /
jhon309	0:ac8863619623	3621	#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /!< Timer 6 clock enable /
jhon309	0:ac8863619623	3622	#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /!< Timer 7 clock enable /
jhon309	0:ac8863619623	3623	#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /!< Timer 14 clock enable /
jhon309	0:ac8863619623	3624	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /!< Window Watchdog clock enable /
jhon309	0:ac8863619623	3625	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /!< SPI2 clock enable /
jhon309	0:ac8863619623	3626	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /!< USART2 clock enable /
jhon309	0:ac8863619623	3627	#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /!< USART3 clock enable /
jhon309	0:ac8863619623	3628	#define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /!< USART4 clock enable /
jhon309	0:ac8863619623	3629	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /!< I2C1 clock enable /
jhon309	0:ac8863619623	3630	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /!< I2C2 clock enable /
jhon309	0:ac8863619623	3631	#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /!< USB clock enable /
jhon309	0:ac8863619623	3632	#define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /!< CAN clock enable /
jhon309	0:ac8863619623	3633	#define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /!< CRS clock enable /
jhon309	0:ac8863619623	3634	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /!< PWR clock enable /
jhon309	0:ac8863619623	3635	#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /!< DAC clock enable /
jhon309	0:ac8863619623	3636	#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /!< CEC clock enable /
jhon309	0:ac8863619623	3637
jhon309	0:ac8863619623	3638	/***************** Bit definition for RCC_BDCR register ****************/
jhon309	0:ac8863619623	3639	#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /!< External Low Speed oscillator enable /
jhon309	0:ac8863619623	3640	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /!< External Low Speed oscillator Ready /
jhon309	0:ac8863619623	3641	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /!< External Low Speed oscillator Bypass /
jhon309	0:ac8863619623	3642
jhon309	0:ac8863619623	3643	#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /!< LSEDRV[1:0] bits (LSE Osc. drive capability) /
jhon309	0:ac8863619623	3644	#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /!< Bit 0 /
jhon309	0:ac8863619623	3645	#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /!< Bit 1 /
jhon309	0:ac8863619623	3646
jhon309	0:ac8863619623	3647	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /!< RTCSEL[1:0] bits (RTC clock source selection) /
jhon309	0:ac8863619623	3648	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
jhon309	0:ac8863619623	3649	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
jhon309	0:ac8863619623	3650
jhon309	0:ac8863619623	3651	/!< RTC configuration /
jhon309	0:ac8863619623	3652	#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
jhon309	0:ac8863619623	3653	#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /!< LSE oscillator clock used as RTC clock /
jhon309	0:ac8863619623	3654	#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /!< LSI oscillator clock used as RTC clock /
jhon309	0:ac8863619623	3655	#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /!< HSE oscillator clock divided by 128 used as RTC clock /
jhon309	0:ac8863619623	3656
jhon309	0:ac8863619623	3657	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /!< RTC clock enable /
jhon309	0:ac8863619623	3658	#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /!< Backup domain software reset /
jhon309	0:ac8863619623	3659
jhon309	0:ac8863619623	3660	/***************** Bit definition for RCC_CSR register *****************/
jhon309	0:ac8863619623	3661	#define RCC_CSR_LSION ((uint32_t)0x00000001) /!< Internal Low Speed oscillator enable /
jhon309	0:ac8863619623	3662	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /!< Internal Low Speed oscillator Ready /
jhon309	0:ac8863619623	3663	#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /!< V1.8 power domain reset flag /
jhon309	0:ac8863619623	3664	#define RCC_CSR_RMVF ((uint32_t)0x01000000) /!< Remove reset flag /
jhon309	0:ac8863619623	3665	#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /!< OBL reset flag /
jhon309	0:ac8863619623	3666	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /!< PIN reset flag /
jhon309	0:ac8863619623	3667	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /!< POR/PDR reset flag /
jhon309	0:ac8863619623	3668	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /!< Software Reset flag /
jhon309	0:ac8863619623	3669	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /!< Independent Watchdog reset flag /
jhon309	0:ac8863619623	3670	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /!< Window watchdog reset flag /
jhon309	0:ac8863619623	3671	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /!< Low-Power reset flag /
jhon309	0:ac8863619623	3672
jhon309	0:ac8863619623	3673	/* Old Bit definition maintained for legacy purpose */
jhon309	0:ac8863619623	3674	#define RCC_CSR_OBL RCC_CSR_OBLRSTF /!< OBL reset flag /
jhon309	0:ac8863619623	3675
jhon309	0:ac8863619623	3676	/***************** Bit definition for RCC_AHBRSTR register *************/
jhon309	0:ac8863619623	3677	#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /!< GPIOA clock reset /
jhon309	0:ac8863619623	3678	#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /!< GPIOB clock reset /
jhon309	0:ac8863619623	3679	#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /!< GPIOC clock reset /
jhon309	0:ac8863619623	3680	#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /!< GPIOD clock reset /
jhon309	0:ac8863619623	3681	#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00200000) /!< GPIOE clock reset /
jhon309	0:ac8863619623	3682	#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /!< GPIOF clock reset /
jhon309	0:ac8863619623	3683	#define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /!< TS clock reset /
jhon309	0:ac8863619623	3684
jhon309	0:ac8863619623	3685	/* Old Bit definition maintained for legacy purpose */
jhon309	0:ac8863619623	3686	#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /!< TS clock reset /
jhon309	0:ac8863619623	3687
jhon309	0:ac8863619623	3688	/***************** Bit definition for RCC_CFGR2 register ***************/
jhon309	0:ac8863619623	3689	/!< PREDIV configuration /
jhon309	0:ac8863619623	3690	#define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /!< PREDIV[3:0] bits /
jhon309	0:ac8863619623	3691	#define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /!< Bit 0 /
jhon309	0:ac8863619623	3692	#define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /!< Bit 1 /
jhon309	0:ac8863619623	3693	#define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /!< Bit 2 /
jhon309	0:ac8863619623	3694	#define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /!< Bit 3 /
jhon309	0:ac8863619623	3695
jhon309	0:ac8863619623	3696	#define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /!< PREDIV input clock not divided /
jhon309	0:ac8863619623	3697	#define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /!< PREDIV input clock divided by 2 /
jhon309	0:ac8863619623	3698	#define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /!< PREDIV input clock divided by 3 /
jhon309	0:ac8863619623	3699	#define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /!< PREDIV input clock divided by 4 /
jhon309	0:ac8863619623	3700	#define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /!< PREDIV input clock divided by 5 /
jhon309	0:ac8863619623	3701	#define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /!< PREDIV input clock divided by 6 /
jhon309	0:ac8863619623	3702	#define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /!< PREDIV input clock divided by 7 /
jhon309	0:ac8863619623	3703	#define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /!< PREDIV input clock divided by 8 /
jhon309	0:ac8863619623	3704	#define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /!< PREDIV input clock divided by 9 /
jhon309	0:ac8863619623	3705	#define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /!< PREDIV input clock divided by 10 /
jhon309	0:ac8863619623	3706	#define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /!< PREDIV input clock divided by 11 /
jhon309	0:ac8863619623	3707	#define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /!< PREDIV input clock divided by 12 /
jhon309	0:ac8863619623	3708	#define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /!< PREDIV input clock divided by 13 /
jhon309	0:ac8863619623	3709	#define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /!< PREDIV input clock divided by 14 /
jhon309	0:ac8863619623	3710	#define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /!< PREDIV input clock divided by 15 /
jhon309	0:ac8863619623	3711	#define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /!< PREDIV input clock divided by 16 /
jhon309	0:ac8863619623	3712
jhon309	0:ac8863619623	3713	/***************** Bit definition for RCC_CFGR3 register ***************/
jhon309	0:ac8863619623	3714	/!< USART1 Clock source selection /
jhon309	0:ac8863619623	3715	#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /!< USART1SW[1:0] bits /
jhon309	0:ac8863619623	3716	#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
jhon309	0:ac8863619623	3717	#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
jhon309	0:ac8863619623	3718
jhon309	0:ac8863619623	3719	#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /!< PCLK clock used as USART1 clock source /
jhon309	0:ac8863619623	3720	#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /!< System clock selected as USART1 clock source /
jhon309	0:ac8863619623	3721	#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /!< LSE oscillator clock used as USART1 clock source /
jhon309	0:ac8863619623	3722	#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /!< HSI oscillator clock used as USART1 clock source /
jhon309	0:ac8863619623	3723
jhon309	0:ac8863619623	3724	/!< I2C1 Clock source selection /
jhon309	0:ac8863619623	3725	#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /!< I2C1SW bits /
jhon309	0:ac8863619623	3726
jhon309	0:ac8863619623	3727	#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /!< HSI oscillator clock used as I2C1 clock source /
jhon309	0:ac8863619623	3728	#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /!< System clock selected as I2C1 clock source /
jhon309	0:ac8863619623	3729
jhon309	0:ac8863619623	3730	/!< CEC Clock source selection /
jhon309	0:ac8863619623	3731	#define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /!< CECSW bits /
jhon309	0:ac8863619623	3732
jhon309	0:ac8863619623	3733	#define RCC_CFGR3_CECSW_HSI_DIV244 ((uint32_t)0x00000000) /!< HSI clock divided by 244 selected as HDMI CEC entry clock source /
jhon309	0:ac8863619623	3734	#define RCC_CFGR3_CECSW_LSE ((uint32_t)0x00000040) /!< LSE clock selected as HDMI CEC entry clock source /
jhon309	0:ac8863619623	3735
jhon309	0:ac8863619623	3736	/!< USB Clock source selection /
jhon309	0:ac8863619623	3737	#define RCC_CFGR3_USBSW ((uint32_t)0x00000080) /!< USBSW bits /
jhon309	0:ac8863619623	3738
jhon309	0:ac8863619623	3739	#define RCC_CFGR3_USBSW_HSI48 ((uint32_t)0x00000000) /!< HSI48 oscillator clock used as USB clock source /
jhon309	0:ac8863619623	3740	#define RCC_CFGR3_USBSW_PLLCLK ((uint32_t)0x00000080) /!< PLLCLK selected as USB clock source /
jhon309	0:ac8863619623	3741
jhon309	0:ac8863619623	3742	/!< USART2 Clock source selection /
jhon309	0:ac8863619623	3743	#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /!< USART2SW[1:0] bits /
jhon309	0:ac8863619623	3744	#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /!< Bit 0 /
jhon309	0:ac8863619623	3745	#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /!< Bit 1 /
jhon309	0:ac8863619623	3746
jhon309	0:ac8863619623	3747	#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /!< PCLK clock used as USART2 clock source /
jhon309	0:ac8863619623	3748	#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /!< System clock selected as USART2 clock source /
jhon309	0:ac8863619623	3749	#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /!< LSE oscillator clock used as USART2 clock source /
jhon309	0:ac8863619623	3750	#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /!< HSI oscillator clock used as USART2 clock source /
jhon309	0:ac8863619623	3751
jhon309	0:ac8863619623	3752	/***************** Bit definition for RCC_CR2 register *****************/
jhon309	0:ac8863619623	3753	#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /!< Internal High Speed 14MHz clock enable /
jhon309	0:ac8863619623	3754	#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /!< Internal High Speed 14MHz clock ready flag /
jhon309	0:ac8863619623	3755	#define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /!< Internal High Speed 14MHz clock disable /
jhon309	0:ac8863619623	3756	#define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /!< Internal High Speed 14MHz clock trimming /
jhon309	0:ac8863619623	3757	#define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /!< Internal High Speed 14MHz clock Calibration /
jhon309	0:ac8863619623	3758	#define RCC_CR2_HSI48ON ((uint32_t)0x00010000) /!< Internal High Speed 48MHz clock enable /
jhon309	0:ac8863619623	3759	#define RCC_CR2_HSI48RDY ((uint32_t)0x00020000) /!< Internal High Speed 48MHz clock ready flag /
jhon309	0:ac8863619623	3760	#define RCC_CR2_HSI48CAL ((uint32_t)0xFF000000) /!< Internal High Speed 48MHz clock Calibration /
jhon309	0:ac8863619623	3761
jhon309	0:ac8863619623	3762	/*****************************************************************************/
jhon309	0:ac8863619623	3763	/* */
jhon309	0:ac8863619623	3764	/* Real-Time Clock (RTC) */
jhon309	0:ac8863619623	3765	/* */
jhon309	0:ac8863619623	3766	/*****************************************************************************/
jhon309	0:ac8863619623	3767	/****************** Bits definition for RTC_TR register ****************/
jhon309	0:ac8863619623	3768	#define RTC_TR_PM ((uint32_t)0x00400000)
jhon309	0:ac8863619623	3769	#define RTC_TR_HT ((uint32_t)0x00300000)
jhon309	0:ac8863619623	3770	#define RTC_TR_HT_0 ((uint32_t)0x00100000)
jhon309	0:ac8863619623	3771	#define RTC_TR_HT_1 ((uint32_t)0x00200000)
jhon309	0:ac8863619623	3772	#define RTC_TR_HU ((uint32_t)0x000F0000)
jhon309	0:ac8863619623	3773	#define RTC_TR_HU_0 ((uint32_t)0x00010000)
jhon309	0:ac8863619623	3774	#define RTC_TR_HU_1 ((uint32_t)0x00020000)
jhon309	0:ac8863619623	3775	#define RTC_TR_HU_2 ((uint32_t)0x00040000)
jhon309	0:ac8863619623	3776	#define RTC_TR_HU_3 ((uint32_t)0x00080000)
jhon309	0:ac8863619623	3777	#define RTC_TR_MNT ((uint32_t)0x00007000)
jhon309	0:ac8863619623	3778	#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
jhon309	0:ac8863619623	3779	#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
jhon309	0:ac8863619623	3780	#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
jhon309	0:ac8863619623	3781	#define RTC_TR_MNU ((uint32_t)0x00000F00)
jhon309	0:ac8863619623	3782	#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
jhon309	0:ac8863619623	3783	#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
jhon309	0:ac8863619623	3784	#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
jhon309	0:ac8863619623	3785	#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
jhon309	0:ac8863619623	3786	#define RTC_TR_ST ((uint32_t)0x00000070)
jhon309	0:ac8863619623	3787	#define RTC_TR_ST_0 ((uint32_t)0x00000010)
jhon309	0:ac8863619623	3788	#define RTC_TR_ST_1 ((uint32_t)0x00000020)
jhon309	0:ac8863619623	3789	#define RTC_TR_ST_2 ((uint32_t)0x00000040)
jhon309	0:ac8863619623	3790	#define RTC_TR_SU ((uint32_t)0x0000000F)
jhon309	0:ac8863619623	3791	#define RTC_TR_SU_0 ((uint32_t)0x00000001)
jhon309	0:ac8863619623	3792	#define RTC_TR_SU_1 ((uint32_t)0x00000002)
jhon309	0:ac8863619623	3793	#define RTC_TR_SU_2 ((uint32_t)0x00000004)
jhon309	0:ac8863619623	3794	#define RTC_TR_SU_3 ((uint32_t)0x00000008)
jhon309	0:ac8863619623	3795
jhon309	0:ac8863619623	3796	/****************** Bits definition for RTC_DR register ****************/
jhon309	0:ac8863619623	3797	#define RTC_DR_YT ((uint32_t)0x00F00000)
jhon309	0:ac8863619623	3798	#define RTC_DR_YT_0 ((uint32_t)0x00100000)
jhon309	0:ac8863619623	3799	#define RTC_DR_YT_1 ((uint32_t)0x00200000)
jhon309	0:ac8863619623	3800	#define RTC_DR_YT_2 ((uint32_t)0x00400000)
jhon309	0:ac8863619623	3801	#define RTC_DR_YT_3 ((uint32_t)0x00800000)
jhon309	0:ac8863619623	3802	#define RTC_DR_YU ((uint32_t)0x000F0000)
jhon309	0:ac8863619623	3803	#define RTC_DR_YU_0 ((uint32_t)0x00010000)
jhon309	0:ac8863619623	3804	#define RTC_DR_YU_1 ((uint32_t)0x00020000)
jhon309	0:ac8863619623	3805	#define RTC_DR_YU_2 ((uint32_t)0x00040000)
jhon309	0:ac8863619623	3806	#define RTC_DR_YU_3 ((uint32_t)0x00080000)
jhon309	0:ac8863619623	3807	#define RTC_DR_WDU ((uint32_t)0x0000E000)
jhon309	0:ac8863619623	3808	#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
jhon309	0:ac8863619623	3809	#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
jhon309	0:ac8863619623	3810	#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
jhon309	0:ac8863619623	3811	#define RTC_DR_MT ((uint32_t)0x00001000)
jhon309	0:ac8863619623	3812	#define RTC_DR_MU ((uint32_t)0x00000F00)
jhon309	0:ac8863619623	3813	#define RTC_DR_MU_0 ((uint32_t)0x00000100)
jhon309	0:ac8863619623	3814	#define RTC_DR_MU_1 ((uint32_t)0x00000200)
jhon309	0:ac8863619623	3815	#define RTC_DR_MU_2 ((uint32_t)0x00000400)
jhon309	0:ac8863619623	3816	#define RTC_DR_MU_3 ((uint32_t)0x00000800)
jhon309	0:ac8863619623	3817	#define RTC_DR_DT ((uint32_t)0x00000030)
jhon309	0:ac8863619623	3818	#define RTC_DR_DT_0 ((uint32_t)0x00000010)
jhon309	0:ac8863619623	3819	#define RTC_DR_DT_1 ((uint32_t)0x00000020)
jhon309	0:ac8863619623	3820	#define RTC_DR_DU ((uint32_t)0x0000000F)
jhon309	0:ac8863619623	3821	#define RTC_DR_DU_0 ((uint32_t)0x00000001)
jhon309	0:ac8863619623	3822	#define RTC_DR_DU_1 ((uint32_t)0x00000002)
jhon309	0:ac8863619623	3823	#define RTC_DR_DU_2 ((uint32_t)0x00000004)
jhon309	0:ac8863619623	3824	#define RTC_DR_DU_3 ((uint32_t)0x00000008)
jhon309	0:ac8863619623	3825
jhon309	0:ac8863619623	3826	/****************** Bits definition for RTC_CR register ****************/
jhon309	0:ac8863619623	3827	#define RTC_CR_COE ((uint32_t)0x00800000)
jhon309	0:ac8863619623	3828	#define RTC_CR_OSEL ((uint32_t)0x00600000)
jhon309	0:ac8863619623	3829	#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
jhon309	0:ac8863619623	3830	#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
jhon309	0:ac8863619623	3831	#define RTC_CR_POL ((uint32_t)0x00100000)
jhon309	0:ac8863619623	3832	#define RTC_CR_COSEL ((uint32_t)0x00080000)
jhon309	0:ac8863619623	3833	#define RTC_CR_BCK ((uint32_t)0x00040000)
jhon309	0:ac8863619623	3834	#define RTC_CR_SUB1H ((uint32_t)0x00020000)
jhon309	0:ac8863619623	3835	#define RTC_CR_ADD1H ((uint32_t)0x00010000)
jhon309	0:ac8863619623	3836	#define RTC_CR_TSIE ((uint32_t)0x00008000)
jhon309	0:ac8863619623	3837	#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
jhon309	0:ac8863619623	3838	#define RTC_CR_TSE ((uint32_t)0x00000800)
jhon309	0:ac8863619623	3839	#define RTC_CR_WUTE ((uint32_t)0x00000400)
jhon309	0:ac8863619623	3840	#define RTC_CR_ALRAE ((uint32_t)0x00000100)
jhon309	0:ac8863619623	3841	#define RTC_CR_FMT ((uint32_t)0x00000040)
jhon309	0:ac8863619623	3842	#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
jhon309	0:ac8863619623	3843	#define RTC_CR_REFCKON ((uint32_t)0x00000010)
jhon309	0:ac8863619623	3844	#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
jhon309	0:ac8863619623	3845	#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
jhon309	0:ac8863619623	3846	#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
jhon309	0:ac8863619623	3847	#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
jhon309	0:ac8863619623	3848	#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
jhon309	0:ac8863619623	3849
jhon309	0:ac8863619623	3850	/****************** Bits definition for RTC_ISR register ***************/
jhon309	0:ac8863619623	3851	#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
jhon309	0:ac8863619623	3852	#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
jhon309	0:ac8863619623	3853	#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
jhon309	0:ac8863619623	3854	#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
jhon309	0:ac8863619623	3855	#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
jhon309	0:ac8863619623	3856	#define RTC_ISR_TSF ((uint32_t)0x00000800)
jhon309	0:ac8863619623	3857	#define RTC_ISR_WUTF ((uint32_t)0x00000400)
jhon309	0:ac8863619623	3858	#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
jhon309	0:ac8863619623	3859	#define RTC_ISR_INIT ((uint32_t)0x00000080)
jhon309	0:ac8863619623	3860	#define RTC_ISR_INITF ((uint32_t)0x00000040)
jhon309	0:ac8863619623	3861	#define RTC_ISR_RSF ((uint32_t)0x00000020)
jhon309	0:ac8863619623	3862	#define RTC_ISR_INITS ((uint32_t)0x00000010)
jhon309	0:ac8863619623	3863	#define RTC_ISR_SHPF ((uint32_t)0x00000008)
jhon309	0:ac8863619623	3864	#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
jhon309	0:ac8863619623	3865	#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
jhon309	0:ac8863619623	3866
jhon309	0:ac8863619623	3867	/****************** Bits definition for RTC_PRER register **************/
jhon309	0:ac8863619623	3868	#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
jhon309	0:ac8863619623	3869	#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
jhon309	0:ac8863619623	3870
jhon309	0:ac8863619623	3871	/****************** Bits definition for RTC_WUTR register **************/
jhon309	0:ac8863619623	3872	#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
jhon309	0:ac8863619623	3873
jhon309	0:ac8863619623	3874	/****************** Bits definition for RTC_ALRMAR register ************/
jhon309	0:ac8863619623	3875	#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
jhon309	0:ac8863619623	3876	#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
jhon309	0:ac8863619623	3877	#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
jhon309	0:ac8863619623	3878	#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
jhon309	0:ac8863619623	3879	#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
jhon309	0:ac8863619623	3880	#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
jhon309	0:ac8863619623	3881	#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
jhon309	0:ac8863619623	3882	#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
jhon309	0:ac8863619623	3883	#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
jhon309	0:ac8863619623	3884	#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
jhon309	0:ac8863619623	3885	#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
jhon309	0:ac8863619623	3886	#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
jhon309	0:ac8863619623	3887	#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
jhon309	0:ac8863619623	3888	#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
jhon309	0:ac8863619623	3889	#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
jhon309	0:ac8863619623	3890	#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
jhon309	0:ac8863619623	3891	#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
jhon309	0:ac8863619623	3892	#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
jhon309	0:ac8863619623	3893	#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
jhon309	0:ac8863619623	3894	#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
jhon309	0:ac8863619623	3895	#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
jhon309	0:ac8863619623	3896	#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
jhon309	0:ac8863619623	3897	#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
jhon309	0:ac8863619623	3898	#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
jhon309	0:ac8863619623	3899	#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
jhon309	0:ac8863619623	3900	#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
jhon309	0:ac8863619623	3901	#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
jhon309	0:ac8863619623	3902	#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
jhon309	0:ac8863619623	3903	#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
jhon309	0:ac8863619623	3904	#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
jhon309	0:ac8863619623	3905	#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
jhon309	0:ac8863619623	3906	#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
jhon309	0:ac8863619623	3907	#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
jhon309	0:ac8863619623	3908	#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
jhon309	0:ac8863619623	3909	#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
jhon309	0:ac8863619623	3910	#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
jhon309	0:ac8863619623	3911	#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
jhon309	0:ac8863619623	3912	#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
jhon309	0:ac8863619623	3913	#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
jhon309	0:ac8863619623	3914	#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
jhon309	0:ac8863619623	3915
jhon309	0:ac8863619623	3916	/****************** Bits definition for RTC_WPR register ***************/
jhon309	0:ac8863619623	3917	#define RTC_WPR_KEY ((uint32_t)0x000000FF)
jhon309	0:ac8863619623	3918
jhon309	0:ac8863619623	3919	/****************** Bits definition for RTC_SSR register ***************/
jhon309	0:ac8863619623	3920	#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
jhon309	0:ac8863619623	3921
jhon309	0:ac8863619623	3922	/****************** Bits definition for RTC_SHIFTR register ************/
jhon309	0:ac8863619623	3923	#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
jhon309	0:ac8863619623	3924	#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
jhon309	0:ac8863619623	3925
jhon309	0:ac8863619623	3926	/****************** Bits definition for RTC_TSTR register **************/
jhon309	0:ac8863619623	3927	#define RTC_TSTR_PM ((uint32_t)0x00400000)
jhon309	0:ac8863619623	3928	#define RTC_TSTR_HT ((uint32_t)0x00300000)
jhon309	0:ac8863619623	3929	#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
jhon309	0:ac8863619623	3930	#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
jhon309	0:ac8863619623	3931	#define RTC_TSTR_HU ((uint32_t)0x000F0000)
jhon309	0:ac8863619623	3932	#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
jhon309	0:ac8863619623	3933	#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
jhon309	0:ac8863619623	3934	#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
jhon309	0:ac8863619623	3935	#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
jhon309	0:ac8863619623	3936	#define RTC_TSTR_MNT ((uint32_t)0x00007000)
jhon309	0:ac8863619623	3937	#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
jhon309	0:ac8863619623	3938	#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
jhon309	0:ac8863619623	3939	#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
jhon309	0:ac8863619623	3940	#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
jhon309	0:ac8863619623	3941	#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
jhon309	0:ac8863619623	3942	#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
jhon309	0:ac8863619623	3943	#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
jhon309	0:ac8863619623	3944	#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
jhon309	0:ac8863619623	3945	#define RTC_TSTR_ST ((uint32_t)0x00000070)
jhon309	0:ac8863619623	3946	#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
jhon309	0:ac8863619623	3947	#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
jhon309	0:ac8863619623	3948	#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
jhon309	0:ac8863619623	3949	#define RTC_TSTR_SU ((uint32_t)0x0000000F)
jhon309	0:ac8863619623	3950	#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
jhon309	0:ac8863619623	3951	#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
jhon309	0:ac8863619623	3952	#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
jhon309	0:ac8863619623	3953	#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
jhon309	0:ac8863619623	3954
jhon309	0:ac8863619623	3955	/****************** Bits definition for RTC_TSDR register **************/
jhon309	0:ac8863619623	3956	#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
jhon309	0:ac8863619623	3957	#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
jhon309	0:ac8863619623	3958	#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
jhon309	0:ac8863619623	3959	#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
jhon309	0:ac8863619623	3960	#define RTC_TSDR_MT ((uint32_t)0x00001000)
jhon309	0:ac8863619623	3961	#define RTC_TSDR_MU ((uint32_t)0x00000F00)
jhon309	0:ac8863619623	3962	#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
jhon309	0:ac8863619623	3963	#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
jhon309	0:ac8863619623	3964	#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
jhon309	0:ac8863619623	3965	#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
jhon309	0:ac8863619623	3966	#define RTC_TSDR_DT ((uint32_t)0x00000030)
jhon309	0:ac8863619623	3967	#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
jhon309	0:ac8863619623	3968	#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
jhon309	0:ac8863619623	3969	#define RTC_TSDR_DU ((uint32_t)0x0000000F)
jhon309	0:ac8863619623	3970	#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
jhon309	0:ac8863619623	3971	#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
jhon309	0:ac8863619623	3972	#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
jhon309	0:ac8863619623	3973	#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
jhon309	0:ac8863619623	3974
jhon309	0:ac8863619623	3975	/****************** Bits definition for RTC_TSSSR register *************/
jhon309	0:ac8863619623	3976	#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
jhon309	0:ac8863619623	3977
jhon309	0:ac8863619623	3978	/****************** Bits definition for RTC_CALR register **************/
jhon309	0:ac8863619623	3979	#define RTC_CALR_CALP ((uint32_t)0x00008000)
jhon309	0:ac8863619623	3980	#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
jhon309	0:ac8863619623	3981	#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
jhon309	0:ac8863619623	3982	#define RTC_CALR_CALM ((uint32_t)0x000001FF)
jhon309	0:ac8863619623	3983	#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
jhon309	0:ac8863619623	3984	#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
jhon309	0:ac8863619623	3985	#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
jhon309	0:ac8863619623	3986	#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
jhon309	0:ac8863619623	3987	#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
jhon309	0:ac8863619623	3988	#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
jhon309	0:ac8863619623	3989	#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
jhon309	0:ac8863619623	3990	#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
jhon309	0:ac8863619623	3991	#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
jhon309	0:ac8863619623	3992
jhon309	0:ac8863619623	3993	/****************** Bits definition for RTC_TAFCR register *************/
jhon309	0:ac8863619623	3994	#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
jhon309	0:ac8863619623	3995	#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
jhon309	0:ac8863619623	3996	#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
jhon309	0:ac8863619623	3997	#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
jhon309	0:ac8863619623	3998	#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
jhon309	0:ac8863619623	3999	#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
jhon309	0:ac8863619623	4000	#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
jhon309	0:ac8863619623	4001	#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
jhon309	0:ac8863619623	4002	#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
jhon309	0:ac8863619623	4003	#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
jhon309	0:ac8863619623	4004	#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
jhon309	0:ac8863619623	4005	#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
jhon309	0:ac8863619623	4006	#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
jhon309	0:ac8863619623	4007	#define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
jhon309	0:ac8863619623	4008	#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
jhon309	0:ac8863619623	4009	#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
jhon309	0:ac8863619623	4010	#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
jhon309	0:ac8863619623	4011	#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
jhon309	0:ac8863619623	4012	#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
jhon309	0:ac8863619623	4013	#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
jhon309	0:ac8863619623	4014
jhon309	0:ac8863619623	4015	/****************** Bits definition for RTC_ALRMASSR register **********/
jhon309	0:ac8863619623	4016	#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
jhon309	0:ac8863619623	4017	#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
jhon309	0:ac8863619623	4018	#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
jhon309	0:ac8863619623	4019	#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
jhon309	0:ac8863619623	4020	#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
jhon309	0:ac8863619623	4021	#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
jhon309	0:ac8863619623	4022
jhon309	0:ac8863619623	4023	/****************** Bits definition for RTC_BKP0R register *************/
jhon309	0:ac8863619623	4024	#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
jhon309	0:ac8863619623	4025
jhon309	0:ac8863619623	4026	/****************** Bits definition for RTC_BKP1R register *************/
jhon309	0:ac8863619623	4027	#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
jhon309	0:ac8863619623	4028
jhon309	0:ac8863619623	4029	/****************** Bits definition for RTC_BKP2R register *************/
jhon309	0:ac8863619623	4030	#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
jhon309	0:ac8863619623	4031
jhon309	0:ac8863619623	4032	/****************** Bits definition for RTC_BKP3R register *************/
jhon309	0:ac8863619623	4033	#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
jhon309	0:ac8863619623	4034
jhon309	0:ac8863619623	4035	/****************** Bits definition for RTC_BKP4R register *************/
jhon309	0:ac8863619623	4036	#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
jhon309	0:ac8863619623	4037
jhon309	0:ac8863619623	4038	/****************** Number of backup registers ****************************/
jhon309	0:ac8863619623	4039	#define RTC_BKP_NUMBER ((uint32_t)0x00000005)
jhon309	0:ac8863619623	4040
jhon309	0:ac8863619623	4041	/*****************************************************************************/
jhon309	0:ac8863619623	4042	/* */
jhon309	0:ac8863619623	4043	/* Serial Peripheral Interface (SPI) */
jhon309	0:ac8863619623	4044	/* */
jhon309	0:ac8863619623	4045	/*****************************************************************************/
jhon309	0:ac8863619623	4046	/***************** Bit definition for SPI_CR1 register *****************/
jhon309	0:ac8863619623	4047	#define SPI_CR1_CPHA ((uint32_t)0x00000001) /!< Clock Phase /
jhon309	0:ac8863619623	4048	#define SPI_CR1_CPOL ((uint32_t)0x00000002) /!< Clock Polarity /
jhon309	0:ac8863619623	4049	#define SPI_CR1_MSTR ((uint32_t)0x00000004) /!< Master Selection /
jhon309	0:ac8863619623	4050	#define SPI_CR1_BR ((uint32_t)0x00000038) /!< BR[2:0] bits (Baud Rate Control) /
jhon309	0:ac8863619623	4051	#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /!< Bit 0 /
jhon309	0:ac8863619623	4052	#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /!< Bit 1 /
jhon309	0:ac8863619623	4053	#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /!< Bit 2 /
jhon309	0:ac8863619623	4054	#define SPI_CR1_SPE ((uint32_t)0x00000040) /!< SPI Enable /
jhon309	0:ac8863619623	4055	#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /!< Frame Format /
jhon309	0:ac8863619623	4056	#define SPI_CR1_SSI ((uint32_t)0x00000100) /!< Internal slave select /
jhon309	0:ac8863619623	4057	#define SPI_CR1_SSM ((uint32_t)0x00000200) /!< Software slave management /
jhon309	0:ac8863619623	4058	#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /!< Receive only /
jhon309	0:ac8863619623	4059	#define SPI_CR1_CRCL ((uint32_t)0x00000800) /!< CRC Length /
jhon309	0:ac8863619623	4060	#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /!< Transmit CRC next /
jhon309	0:ac8863619623	4061	#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /!< Hardware CRC calculation enable /
jhon309	0:ac8863619623	4062	#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /!< Output enable in bidirectional mode /
jhon309	0:ac8863619623	4063	#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /!< Bidirectional data mode enable /
jhon309	0:ac8863619623	4064
jhon309	0:ac8863619623	4065	/***************** Bit definition for SPI_CR2 register *****************/
jhon309	0:ac8863619623	4066	#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /!< Rx Buffer DMA Enable /
jhon309	0:ac8863619623	4067	#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /!< Tx Buffer DMA Enable /
jhon309	0:ac8863619623	4068	#define SPI_CR2_SSOE ((uint32_t)0x00000004) /!< SS Output Enable /
jhon309	0:ac8863619623	4069	#define SPI_CR2_NSSP ((uint32_t)0x00000008) /!< NSS pulse management Enable /
jhon309	0:ac8863619623	4070	#define SPI_CR2_FRF ((uint32_t)0x00000010) /!< Frame Format Enable /
jhon309	0:ac8863619623	4071	#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /!< Error Interrupt Enable /
jhon309	0:ac8863619623	4072	#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /!< RX buffer Not Empty Interrupt Enable /
jhon309	0:ac8863619623	4073	#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /!< Tx buffer Empty Interrupt Enable /
jhon309	0:ac8863619623	4074	#define SPI_CR2_DS ((uint32_t)0x00000F00) /!< DS[3:0] Data Size /
jhon309	0:ac8863619623	4075	#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /!< Bit 0 /
jhon309	0:ac8863619623	4076	#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /!< Bit 1 /
jhon309	0:ac8863619623	4077	#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /!< Bit 2 /
jhon309	0:ac8863619623	4078	#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /!< Bit 3 /
jhon309	0:ac8863619623	4079	#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /!< FIFO reception Threshold /
jhon309	0:ac8863619623	4080	#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /!< Last DMA transfer for reception /
jhon309	0:ac8863619623	4081	#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /!< Last DMA transfer for transmission /
jhon309	0:ac8863619623	4082
jhon309	0:ac8863619623	4083	/****************** Bit definition for SPI_SR register *****************/
jhon309	0:ac8863619623	4084	#define SPI_SR_RXNE ((uint32_t)0x00000001) /!< Receive buffer Not Empty /
jhon309	0:ac8863619623	4085	#define SPI_SR_TXE ((uint32_t)0x00000002) /!< Transmit buffer Empty /
jhon309	0:ac8863619623	4086	#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /!< Channel side /
jhon309	0:ac8863619623	4087	#define SPI_SR_UDR ((uint32_t)0x00000008) /!< Underrun flag /
jhon309	0:ac8863619623	4088	#define SPI_SR_CRCERR ((uint32_t)0x00000010) /!< CRC Error flag /
jhon309	0:ac8863619623	4089	#define SPI_SR_MODF ((uint32_t)0x00000020) /!< Mode fault /
jhon309	0:ac8863619623	4090	#define SPI_SR_OVR ((uint32_t)0x00000040) /!< Overrun flag /
jhon309	0:ac8863619623	4091	#define SPI_SR_BSY ((uint32_t)0x00000080) /!< Busy flag /
jhon309	0:ac8863619623	4092	#define SPI_SR_FRE ((uint32_t)0x00000100) /!< TI frame format error /
jhon309	0:ac8863619623	4093	#define SPI_SR_FRLVL ((uint32_t)0x00000600) /!< FIFO Reception Level /
jhon309	0:ac8863619623	4094	#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /!< Bit 0 /
jhon309	0:ac8863619623	4095	#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /!< Bit 1 /
jhon309	0:ac8863619623	4096	#define SPI_SR_FTLVL ((uint32_t)0x00001800) /!< FIFO Transmission Level /
jhon309	0:ac8863619623	4097	#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /!< Bit 0 /
jhon309	0:ac8863619623	4098	#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /!< Bit 1 /
jhon309	0:ac8863619623	4099
jhon309	0:ac8863619623	4100	/****************** Bit definition for SPI_DR register *****************/
jhon309	0:ac8863619623	4101	#define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data Register /
jhon309	0:ac8863619623	4102
jhon309	0:ac8863619623	4103	/***************** Bit definition for SPI_CRCPR register ***************/
jhon309	0:ac8863619623	4104	#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /!< CRC polynomial register /
jhon309	0:ac8863619623	4105
jhon309	0:ac8863619623	4106	/**************** Bit definition for SPI_RXCRCR register ***************/
jhon309	0:ac8863619623	4107	#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /!< Rx CRC Register /
jhon309	0:ac8863619623	4108
jhon309	0:ac8863619623	4109	/**************** Bit definition for SPI_TXCRCR register ***************/
jhon309	0:ac8863619623	4110	#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /!< Tx CRC Register /
jhon309	0:ac8863619623	4111
jhon309	0:ac8863619623	4112	/**************** Bit definition for SPI_I2SCFGR register **************/
jhon309	0:ac8863619623	4113	#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /!<Channel length (number of bits per audio channel) /
jhon309	0:ac8863619623	4114	#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /!<DATLEN[1:0] bits (Data length to be transferred) /
jhon309	0:ac8863619623	4115	#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /!<Bit 0 /
jhon309	0:ac8863619623	4116	#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /!<Bit 1 /
jhon309	0:ac8863619623	4117	#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /!<steady state clock polarity /
jhon309	0:ac8863619623	4118	#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /!<I2SSTD[1:0] bits (I2S standard selection) /
jhon309	0:ac8863619623	4119	#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /!<Bit 0 /
jhon309	0:ac8863619623	4120	#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /!<Bit 1 /
jhon309	0:ac8863619623	4121	#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /!<PCM frame synchronization /
jhon309	0:ac8863619623	4122	#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /!<I2SCFG[1:0] bits (I2S configuration mode) /
jhon309	0:ac8863619623	4123	#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /!<Bit 0 /
jhon309	0:ac8863619623	4124	#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /!<Bit 1 /
jhon309	0:ac8863619623	4125	#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /!<I2S Enable /
jhon309	0:ac8863619623	4126	#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /!<I2S mode selection /
jhon309	0:ac8863619623	4127
jhon309	0:ac8863619623	4128	/**************** Bit definition for SPI_I2SPR register ****************/
jhon309	0:ac8863619623	4129	#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /!<I2S Linear prescaler /
jhon309	0:ac8863619623	4130	#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /!<Odd factor for the prescaler /
jhon309	0:ac8863619623	4131	#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /!<Master Clock Output Enable /
jhon309	0:ac8863619623	4132
jhon309	0:ac8863619623	4133	/*****************************************************************************/
jhon309	0:ac8863619623	4134	/* */
jhon309	0:ac8863619623	4135	/* System Configuration (SYSCFG) */
jhon309	0:ac8863619623	4136	/* */
jhon309	0:ac8863619623	4137	/*****************************************************************************/
jhon309	0:ac8863619623	4138	/*************** Bit definition for SYSCFG_CFGR1 register **************/
jhon309	0:ac8863619623	4139	#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /!< SYSCFG_Memory Remap Config /
jhon309	0:ac8863619623	4140	#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /!< SYSCFG_Memory Remap Config Bit 0 /
jhon309	0:ac8863619623	4141	#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /!< SYSCFG_Memory Remap Config Bit 1 /
jhon309	0:ac8863619623	4142
jhon309	0:ac8863619623	4143	#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x7F007F00) /!< DMA remap mask /
jhon309	0:ac8863619623	4144	#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /!< ADC DMA remap /
jhon309	0:ac8863619623	4145	#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /!< USART1 TX DMA remap /
jhon309	0:ac8863619623	4146	#define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /!< USART1 RX DMA remap /
jhon309	0:ac8863619623	4147	#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /!< Timer 16 DMA remap /
jhon309	0:ac8863619623	4148	#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /!< Timer 17 DMA remap /
jhon309	0:ac8863619623	4149	#define SYSCFG_CFGR1_TIM16_DMA_RMP2 ((uint32_t)0x00002000) /!< Timer 16 DMA remap 2 /
jhon309	0:ac8863619623	4150	#define SYSCFG_CFGR1_TIM17_DMA_RMP2 ((uint32_t)0x00004000) /!< Timer 17 DMA remap 2 /
jhon309	0:ac8863619623	4151	#define SYSCFG_CFGR1_SPI2_DMA_RMP ((uint32_t)0x01000000) /!< SPI2 DMA remap /
jhon309	0:ac8863619623	4152	#define SYSCFG_CFGR1_USART2_DMA_RMP ((uint32_t)0x02000000) /!< USART2 DMA remap /
jhon309	0:ac8863619623	4153	#define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /!< USART3 DMA remap /
jhon309	0:ac8863619623	4154	#define SYSCFG_CFGR1_I2C1_DMA_RMP ((uint32_t)0x08000000) /!< I2C1 DMA remap /
jhon309	0:ac8863619623	4155	#define SYSCFG_CFGR1_TIM1_DMA_RMP ((uint32_t)0x10000000) /!< TIM1 DMA remap /
jhon309	0:ac8863619623	4156	#define SYSCFG_CFGR1_TIM2_DMA_RMP ((uint32_t)0x20000000) /!< TIM2 DMA remap /
jhon309	0:ac8863619623	4157	#define SYSCFG_CFGR1_TIM3_DMA_RMP ((uint32_t)0x40000000) /!< TIM3 DMA remap /
jhon309	0:ac8863619623	4158
jhon309	0:ac8863619623	4159	#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /!< I2C PB6 Fast mode plus /
jhon309	0:ac8863619623	4160	#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /!< I2C PB7 Fast mode plus /
jhon309	0:ac8863619623	4161	#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /!< I2C PB8 Fast mode plus /
jhon309	0:ac8863619623	4162	#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /!< I2C PB9 Fast mode plus /
jhon309	0:ac8863619623	4163	#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 /
jhon309	0:ac8863619623	4164	#define SYSCFG_CFGR1_I2C_FMP_I2C2 ((uint32_t)0x00200000) /!< Enable I2C2 Fast mode plus /
jhon309	0:ac8863619623	4165
jhon309	0:ac8863619623	4166	/*************** Bit definition for SYSCFG_EXTICR1 register ************/
jhon309	0:ac8863619623	4167	#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /!< EXTI 0 configuration /
jhon309	0:ac8863619623	4168	#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /!< EXTI 1 configuration /
jhon309	0:ac8863619623	4169	#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /!< EXTI 2 configuration /
jhon309	0:ac8863619623	4170	#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /!< EXTI 3 configuration /
jhon309	0:ac8863619623	4171
jhon309	0:ac8863619623	4172	/**
jhon309	0:ac8863619623	4173	* @brief EXTI0 configuration
jhon309	0:ac8863619623	4174	*/
jhon309	0:ac8863619623	4175	#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /!< PA[0] pin /
jhon309	0:ac8863619623	4176	#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /!< PB[0] pin /
jhon309	0:ac8863619623	4177	#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /!< PC[0] pin /
jhon309	0:ac8863619623	4178	#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /!< PD[0] pin /
jhon309	0:ac8863619623	4179	#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /!< PE[0] pin /
jhon309	0:ac8863619623	4180	#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /!< PF[0] pin /
jhon309	0:ac8863619623	4181
jhon309	0:ac8863619623	4182	/**
jhon309	0:ac8863619623	4183	* @brief EXTI1 configuration
jhon309	0:ac8863619623	4184	*/
jhon309	0:ac8863619623	4185	#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /!< PA[1] pin /
jhon309	0:ac8863619623	4186	#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /!< PB[1] pin /
jhon309	0:ac8863619623	4187	#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /!< PC[1] pin /
jhon309	0:ac8863619623	4188	#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /!< PD[1] pin /
jhon309	0:ac8863619623	4189	#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /!< PE[1] pin /
jhon309	0:ac8863619623	4190	#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /!< PF[1] pin /
jhon309	0:ac8863619623	4191
jhon309	0:ac8863619623	4192	/**
jhon309	0:ac8863619623	4193	* @brief EXTI2 configuration
jhon309	0:ac8863619623	4194	*/
jhon309	0:ac8863619623	4195	#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /!< PA[2] pin /
jhon309	0:ac8863619623	4196	#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /!< PB[2] pin /
jhon309	0:ac8863619623	4197	#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /!< PC[2] pin /
jhon309	0:ac8863619623	4198	#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /!< PD[2] pin /
jhon309	0:ac8863619623	4199	#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /!< PE[2] pin /
jhon309	0:ac8863619623	4200	#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /!< PF[2] pin /
jhon309	0:ac8863619623	4201
jhon309	0:ac8863619623	4202	/**
jhon309	0:ac8863619623	4203	* @brief EXTI3 configuration
jhon309	0:ac8863619623	4204	*/
jhon309	0:ac8863619623	4205	#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /!< PA[3] pin /
jhon309	0:ac8863619623	4206	#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /!< PB[3] pin /
jhon309	0:ac8863619623	4207	#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /!< PC[3] pin /
jhon309	0:ac8863619623	4208	#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /!< PD[3] pin /
jhon309	0:ac8863619623	4209	#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /!< PE[3] pin /
jhon309	0:ac8863619623	4210	#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /!< PF[3] pin /
jhon309	0:ac8863619623	4211
jhon309	0:ac8863619623	4212	/*************** Bit definition for SYSCFG_EXTICR2 register ************/
jhon309	0:ac8863619623	4213	#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /!< EXTI 4 configuration /
jhon309	0:ac8863619623	4214	#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /!< EXTI 5 configuration /
jhon309	0:ac8863619623	4215	#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /!< EXTI 6 configuration /
jhon309	0:ac8863619623	4216	#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /!< EXTI 7 configuration /
jhon309	0:ac8863619623	4217
jhon309	0:ac8863619623	4218	/**
jhon309	0:ac8863619623	4219	* @brief EXTI4 configuration
jhon309	0:ac8863619623	4220	*/
jhon309	0:ac8863619623	4221	#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /!< PA[4] pin /
jhon309	0:ac8863619623	4222	#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /!< PB[4] pin /
jhon309	0:ac8863619623	4223	#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /!< PC[4] pin /
jhon309	0:ac8863619623	4224	#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /!< PD[4] pin /
jhon309	0:ac8863619623	4225	#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /!< PE[4] pin /
jhon309	0:ac8863619623	4226	#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /!< PF[4] pin /
jhon309	0:ac8863619623	4227
jhon309	0:ac8863619623	4228	/**
jhon309	0:ac8863619623	4229	* @brief EXTI5 configuration
jhon309	0:ac8863619623	4230	*/
jhon309	0:ac8863619623	4231	#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /!< PA[5] pin /
jhon309	0:ac8863619623	4232	#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /!< PB[5] pin /
jhon309	0:ac8863619623	4233	#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /!< PC[5] pin /
jhon309	0:ac8863619623	4234	#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /!< PD[5] pin /
jhon309	0:ac8863619623	4235	#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /!< PE[5] pin /
jhon309	0:ac8863619623	4236	#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /!< PF[5] pin /
jhon309	0:ac8863619623	4237
jhon309	0:ac8863619623	4238	/**
jhon309	0:ac8863619623	4239	* @brief EXTI6 configuration
jhon309	0:ac8863619623	4240	*/
jhon309	0:ac8863619623	4241	#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /!< PA[6] pin /
jhon309	0:ac8863619623	4242	#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /!< PB[6] pin /
jhon309	0:ac8863619623	4243	#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /!< PC[6] pin /
jhon309	0:ac8863619623	4244	#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /!< PD[6] pin /
jhon309	0:ac8863619623	4245	#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /!< PE[6] pin /
jhon309	0:ac8863619623	4246	#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /!< PF[6] pin /
jhon309	0:ac8863619623	4247
jhon309	0:ac8863619623	4248	/**
jhon309	0:ac8863619623	4249	* @brief EXTI7 configuration
jhon309	0:ac8863619623	4250	*/
jhon309	0:ac8863619623	4251	#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /!< PA[7] pin /
jhon309	0:ac8863619623	4252	#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /!< PB[7] pin /
jhon309	0:ac8863619623	4253	#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /!< PC[7] pin /
jhon309	0:ac8863619623	4254	#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /!< PD[7] pin /
jhon309	0:ac8863619623	4255	#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /!< PE[7] pin /
jhon309	0:ac8863619623	4256	#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /!< PF[7] pin /
jhon309	0:ac8863619623	4257
jhon309	0:ac8863619623	4258	/*************** Bit definition for SYSCFG_EXTICR3 register ************/
jhon309	0:ac8863619623	4259	#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /!< EXTI 8 configuration /
jhon309	0:ac8863619623	4260	#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /!< EXTI 9 configuration /
jhon309	0:ac8863619623	4261	#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /!< EXTI 10 configuration /
jhon309	0:ac8863619623	4262	#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /!< EXTI 11 configuration /
jhon309	0:ac8863619623	4263
jhon309	0:ac8863619623	4264	/**
jhon309	0:ac8863619623	4265	* @brief EXTI8 configuration
jhon309	0:ac8863619623	4266	*/
jhon309	0:ac8863619623	4267	#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /!< PA[8] pin /
jhon309	0:ac8863619623	4268	#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /!< PB[8] pin /
jhon309	0:ac8863619623	4269	#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /!< PC[8] pin /
jhon309	0:ac8863619623	4270	#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /!< PD[8] pin /
jhon309	0:ac8863619623	4271	#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /!< PE[8] pin /
jhon309	0:ac8863619623	4272
jhon309	0:ac8863619623	4273	/**
jhon309	0:ac8863619623	4274	* @brief EXTI9 configuration
jhon309	0:ac8863619623	4275	*/
jhon309	0:ac8863619623	4276	#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /!< PA[9] pin /
jhon309	0:ac8863619623	4277	#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /!< PB[9] pin /
jhon309	0:ac8863619623	4278	#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /!< PC[9] pin /
jhon309	0:ac8863619623	4279	#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /!< PD[9] pin /
jhon309	0:ac8863619623	4280	#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /!< PE[9] pin /
jhon309	0:ac8863619623	4281	#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /!< PF[9] pin /
jhon309	0:ac8863619623	4282
jhon309	0:ac8863619623	4283	/**
jhon309	0:ac8863619623	4284	* @brief EXTI10 configuration
jhon309	0:ac8863619623	4285	*/
jhon309	0:ac8863619623	4286	#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /!< PA[10] pin /
jhon309	0:ac8863619623	4287	#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /!< PB[10] pin /
jhon309	0:ac8863619623	4288	#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /!< PC[10] pin /
jhon309	0:ac8863619623	4289	#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /!< PE[10] pin /
jhon309	0:ac8863619623	4290	#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /!< PD[10] pin /
jhon309	0:ac8863619623	4291	#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /!< PF[10] pin /
jhon309	0:ac8863619623	4292
jhon309	0:ac8863619623	4293	/**
jhon309	0:ac8863619623	4294	* @brief EXTI11 configuration
jhon309	0:ac8863619623	4295	*/
jhon309	0:ac8863619623	4296	#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /!< PA[11] pin /
jhon309	0:ac8863619623	4297	#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /!< PB[11] pin /
jhon309	0:ac8863619623	4298	#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /!< PC[11] pin /
jhon309	0:ac8863619623	4299	#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /!< PD[11] pin /
jhon309	0:ac8863619623	4300	#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /!< PE[11] pin /
jhon309	0:ac8863619623	4301
jhon309	0:ac8863619623	4302	/*************** Bit definition for SYSCFG_EXTICR4 register ************/
jhon309	0:ac8863619623	4303	#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /!< EXTI 12 configuration /
jhon309	0:ac8863619623	4304	#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /!< EXTI 13 configuration /
jhon309	0:ac8863619623	4305	#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /!< EXTI 14 configuration /
jhon309	0:ac8863619623	4306	#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /!< EXTI 15 configuration /
jhon309	0:ac8863619623	4307
jhon309	0:ac8863619623	4308	/**
jhon309	0:ac8863619623	4309	* @brief EXTI12 configuration
jhon309	0:ac8863619623	4310	*/
jhon309	0:ac8863619623	4311	#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /!< PA[12] pin /
jhon309	0:ac8863619623	4312	#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /!< PB[12] pin /
jhon309	0:ac8863619623	4313	#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /!< PC[12] pin /
jhon309	0:ac8863619623	4314	#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /!< PD[12] pin /
jhon309	0:ac8863619623	4315	#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /!< PE[12] pin /
jhon309	0:ac8863619623	4316
jhon309	0:ac8863619623	4317	/**
jhon309	0:ac8863619623	4318	* @brief EXTI13 configuration
jhon309	0:ac8863619623	4319	*/
jhon309	0:ac8863619623	4320	#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /!< PA[13] pin /
jhon309	0:ac8863619623	4321	#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /!< PB[13] pin /
jhon309	0:ac8863619623	4322	#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /!< PC[13] pin /
jhon309	0:ac8863619623	4323	#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /!< PD[13] pin /
jhon309	0:ac8863619623	4324	#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /!< PE[13] pin /
jhon309	0:ac8863619623	4325
jhon309	0:ac8863619623	4326	/**
jhon309	0:ac8863619623	4327	* @brief EXTI14 configuration
jhon309	0:ac8863619623	4328	*/
jhon309	0:ac8863619623	4329	#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /!< PA[14] pin /
jhon309	0:ac8863619623	4330	#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /!< PB[14] pin /
jhon309	0:ac8863619623	4331	#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /!< PC[14] pin /
jhon309	0:ac8863619623	4332	#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /!< PD[14] pin /
jhon309	0:ac8863619623	4333	#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /!< PE[14] pin /
jhon309	0:ac8863619623	4334
jhon309	0:ac8863619623	4335	/**
jhon309	0:ac8863619623	4336	* @brief EXTI15 configuration
jhon309	0:ac8863619623	4337	*/
jhon309	0:ac8863619623	4338	#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /!< PA[15] pin /
jhon309	0:ac8863619623	4339	#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /!< PB[15] pin /
jhon309	0:ac8863619623	4340	#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /!< PC[15] pin /
jhon309	0:ac8863619623	4341	#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /!< PD[15] pin /
jhon309	0:ac8863619623	4342	#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /!< PE[15] pin /
jhon309	0:ac8863619623	4343
jhon309	0:ac8863619623	4344	/*************** Bit definition for SYSCFG_CFGR2 register **************/
jhon309	0:ac8863619623	4345	#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 /
jhon309	0:ac8863619623	4346	#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 /
jhon309	0:ac8863619623	4347	#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface /
jhon309	0:ac8863619623	4348	#define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /!< SRAM Parity error flag /
jhon309	0:ac8863619623	4349	#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /!< SRAM Parity error flag (define maintained for legacy purpose) /
jhon309	0:ac8863619623	4350
jhon309	0:ac8863619623	4351	/*****************************************************************************/
jhon309	0:ac8863619623	4352	/* */
jhon309	0:ac8863619623	4353	/* Timers (TIM) */
jhon309	0:ac8863619623	4354	/* */
jhon309	0:ac8863619623	4355	/*****************************************************************************/
jhon309	0:ac8863619623	4356	/***************** Bit definition for TIM_CR1 register *****************/
jhon309	0:ac8863619623	4357	#define TIM_CR1_CEN ((uint32_t)0x00000001) /!<Counter enable /
jhon309	0:ac8863619623	4358	#define TIM_CR1_UDIS ((uint32_t)0x00000002) /!<Update disable /
jhon309	0:ac8863619623	4359	#define TIM_CR1_URS ((uint32_t)0x00000004) /!<Update request source /
jhon309	0:ac8863619623	4360	#define TIM_CR1_OPM ((uint32_t)0x00000008) /!<One pulse mode /
jhon309	0:ac8863619623	4361	#define TIM_CR1_DIR ((uint32_t)0x00000010) /!<Direction /
jhon309	0:ac8863619623	4362
jhon309	0:ac8863619623	4363	#define TIM_CR1_CMS ((uint32_t)0x00000060) /!<CMS[1:0] bits (Center-aligned mode selection) /
jhon309	0:ac8863619623	4364	#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /!<Bit 0 /
jhon309	0:ac8863619623	4365	#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /!<Bit 1 /
jhon309	0:ac8863619623	4366
jhon309	0:ac8863619623	4367	#define TIM_CR1_ARPE ((uint32_t)0x00000080) /!<Auto-reload preload enable /
jhon309	0:ac8863619623	4368
jhon309	0:ac8863619623	4369	#define TIM_CR1_CKD ((uint32_t)0x00000300) /!<CKD[1:0] bits (clock division) /
jhon309	0:ac8863619623	4370	#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /!<Bit 0 /
jhon309	0:ac8863619623	4371	#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /!<Bit 1 /
jhon309	0:ac8863619623	4372
jhon309	0:ac8863619623	4373	/***************** Bit definition for TIM_CR2 register *****************/
jhon309	0:ac8863619623	4374	#define TIM_CR2_CCPC ((uint32_t)0x00000001) /!<Capture/Compare Preloaded Control /
jhon309	0:ac8863619623	4375	#define TIM_CR2_CCUS ((uint32_t)0x00000004) /!<Capture/Compare Control Update Selection /
jhon309	0:ac8863619623	4376	#define TIM_CR2_CCDS ((uint32_t)0x00000008) /!<Capture/Compare DMA Selection /
jhon309	0:ac8863619623	4377
jhon309	0:ac8863619623	4378	#define TIM_CR2_MMS ((uint32_t)0x00000070) /!<MMS[2:0] bits (Master Mode Selection) /
jhon309	0:ac8863619623	4379	#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /!<Bit 0 /
jhon309	0:ac8863619623	4380	#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /!<Bit 1 /
jhon309	0:ac8863619623	4381	#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /!<Bit 2 /
jhon309	0:ac8863619623	4382
jhon309	0:ac8863619623	4383	#define TIM_CR2_TI1S ((uint32_t)0x00000080) /!<TI1 Selection /
jhon309	0:ac8863619623	4384	#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /!<Output Idle state 1 (OC1 output) /
jhon309	0:ac8863619623	4385	#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /!<Output Idle state 1 (OC1N output) /
jhon309	0:ac8863619623	4386	#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /!<Output Idle state 2 (OC2 output) /
jhon309	0:ac8863619623	4387	#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /!<Output Idle state 2 (OC2N output) /
jhon309	0:ac8863619623	4388	#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /!<Output Idle state 3 (OC3 output) /
jhon309	0:ac8863619623	4389	#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /!<Output Idle state 3 (OC3N output) /
jhon309	0:ac8863619623	4390	#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /!<Output Idle state 4 (OC4 output) /
jhon309	0:ac8863619623	4391
jhon309	0:ac8863619623	4392	/***************** Bit definition for TIM_SMCR register ****************/
jhon309	0:ac8863619623	4393	#define TIM_SMCR_SMS ((uint32_t)0x00000007) /!<SMS[2:0] bits (Slave mode selection) /
jhon309	0:ac8863619623	4394	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /!<Bit 0 /
jhon309	0:ac8863619623	4395	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /!<Bit 1 /
jhon309	0:ac8863619623	4396	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /!<Bit 2 /
jhon309	0:ac8863619623	4397
jhon309	0:ac8863619623	4398	#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /!< OCREF clear selection /
jhon309	0:ac8863619623	4399
jhon309	0:ac8863619623	4400	#define TIM_SMCR_TS ((uint32_t)0x00000070) /!<TS[2:0] bits (Trigger selection) /
jhon309	0:ac8863619623	4401	#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /!<Bit 0 /
jhon309	0:ac8863619623	4402	#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /!<Bit 1 /
jhon309	0:ac8863619623	4403	#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /!<Bit 2 /
jhon309	0:ac8863619623	4404
jhon309	0:ac8863619623	4405	#define TIM_SMCR_MSM ((uint32_t)0x00000080) /!<Master/slave mode /
jhon309	0:ac8863619623	4406
jhon309	0:ac8863619623	4407	#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /!<ETF[3:0] bits (External trigger filter) /
jhon309	0:ac8863619623	4408	#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /!<Bit 0 /
jhon309	0:ac8863619623	4409	#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /!<Bit 1 /
jhon309	0:ac8863619623	4410	#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /!<Bit 2 /
jhon309	0:ac8863619623	4411	#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /!<Bit 3 /
jhon309	0:ac8863619623	4412
jhon309	0:ac8863619623	4413	#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /!<ETPS[1:0] bits (External trigger prescaler) /
jhon309	0:ac8863619623	4414	#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /!<Bit 0 /
jhon309	0:ac8863619623	4415	#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /!<Bit 1 /
jhon309	0:ac8863619623	4416
jhon309	0:ac8863619623	4417	#define TIM_SMCR_ECE ((uint32_t)0x00004000) /!<External clock enable /
jhon309	0:ac8863619623	4418	#define TIM_SMCR_ETP ((uint32_t)0x00008000) /!<External trigger polarity /
jhon309	0:ac8863619623	4419
jhon309	0:ac8863619623	4420	/***************** Bit definition for TIM_DIER register ****************/
jhon309	0:ac8863619623	4421	#define TIM_DIER_UIE ((uint32_t)0x00000001) /!<Update interrupt enable /
jhon309	0:ac8863619623	4422	#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt enable /
jhon309	0:ac8863619623	4423	#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt enable /
jhon309	0:ac8863619623	4424	#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt enable /
jhon309	0:ac8863619623	4425	#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt enable /
jhon309	0:ac8863619623	4426	#define TIM_DIER_COMIE ((uint32_t)0x00000020) /!<COM interrupt enable /
jhon309	0:ac8863619623	4427	#define TIM_DIER_TIE ((uint32_t)0x00000040) /!<Trigger interrupt enable /
jhon309	0:ac8863619623	4428	#define TIM_DIER_BIE ((uint32_t)0x00000080) /!<Break interrupt enable /
jhon309	0:ac8863619623	4429	#define TIM_DIER_UDE ((uint32_t)0x00000100) /!<Update DMA request enable /
jhon309	0:ac8863619623	4430	#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /!<Capture/Compare 1 DMA request enable /
jhon309	0:ac8863619623	4431	#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /!<Capture/Compare 2 DMA request enable /
jhon309	0:ac8863619623	4432	#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /!<Capture/Compare 3 DMA request enable /
jhon309	0:ac8863619623	4433	#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /!<Capture/Compare 4 DMA request enable /
jhon309	0:ac8863619623	4434	#define TIM_DIER_COMDE ((uint32_t)0x00002000) /!<COM DMA request enable /
jhon309	0:ac8863619623	4435	#define TIM_DIER_TDE ((uint32_t)0x00004000) /!<Trigger DMA request enable /
jhon309	0:ac8863619623	4436
jhon309	0:ac8863619623	4437	/****************** Bit definition for TIM_SR register *****************/
jhon309	0:ac8863619623	4438	#define TIM_SR_UIF ((uint32_t)0x00000001) /!<Update interrupt Flag /
jhon309	0:ac8863619623	4439	#define TIM_SR_CC1IF ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt Flag /
jhon309	0:ac8863619623	4440	#define TIM_SR_CC2IF ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt Flag /
jhon309	0:ac8863619623	4441	#define TIM_SR_CC3IF ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt Flag /
jhon309	0:ac8863619623	4442	#define TIM_SR_CC4IF ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt Flag /
jhon309	0:ac8863619623	4443	#define TIM_SR_COMIF ((uint32_t)0x00000020) /!<COM interrupt Flag /
jhon309	0:ac8863619623	4444	#define TIM_SR_TIF ((uint32_t)0x00000040) /!<Trigger interrupt Flag /
jhon309	0:ac8863619623	4445	#define TIM_SR_BIF ((uint32_t)0x00000080) /!<Break interrupt Flag /
jhon309	0:ac8863619623	4446	#define TIM_SR_CC1OF ((uint32_t)0x00000200) /!<Capture/Compare 1 Overcapture Flag /
jhon309	0:ac8863619623	4447	#define TIM_SR_CC2OF ((uint32_t)0x00000400) /!<Capture/Compare 2 Overcapture Flag /
jhon309	0:ac8863619623	4448	#define TIM_SR_CC3OF ((uint32_t)0x00000800) /!<Capture/Compare 3 Overcapture Flag /
jhon309	0:ac8863619623	4449	#define TIM_SR_CC4OF ((uint32_t)0x00001000) /!<Capture/Compare 4 Overcapture Flag /
jhon309	0:ac8863619623	4450
jhon309	0:ac8863619623	4451	/***************** Bit definition for TIM_EGR register *****************/
jhon309	0:ac8863619623	4452	#define TIM_EGR_UG ((uint32_t)0x00000001) /!<Update Generation /
jhon309	0:ac8863619623	4453	#define TIM_EGR_CC1G ((uint32_t)0x00000002) /!<Capture/Compare 1 Generation /
jhon309	0:ac8863619623	4454	#define TIM_EGR_CC2G ((uint32_t)0x00000004) /!<Capture/Compare 2 Generation /
jhon309	0:ac8863619623	4455	#define TIM_EGR_CC3G ((uint32_t)0x00000008) /!<Capture/Compare 3 Generation /
jhon309	0:ac8863619623	4456	#define TIM_EGR_CC4G ((uint32_t)0x00000010) /!<Capture/Compare 4 Generation /
jhon309	0:ac8863619623	4457	#define TIM_EGR_COMG ((uint32_t)0x00000020) /!<Capture/Compare Control Update Generation /
jhon309	0:ac8863619623	4458	#define TIM_EGR_TG ((uint32_t)0x00000040) /!<Trigger Generation /
jhon309	0:ac8863619623	4459	#define TIM_EGR_BG ((uint32_t)0x00000080) /!<Break Generation /
jhon309	0:ac8863619623	4460
jhon309	0:ac8863619623	4461	/**************** Bit definition for TIM_CCMR1 register ****************/
jhon309	0:ac8863619623	4462	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
jhon309	0:ac8863619623	4463	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /!<Bit 0 /
jhon309	0:ac8863619623	4464	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /!<Bit 1 /
jhon309	0:ac8863619623	4465
jhon309	0:ac8863619623	4466	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /!<Output Compare 1 Fast enable /
jhon309	0:ac8863619623	4467	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /!<Output Compare 1 Preload enable /
jhon309	0:ac8863619623	4468
jhon309	0:ac8863619623	4469	#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
jhon309	0:ac8863619623	4470	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /!<Bit 0 /
jhon309	0:ac8863619623	4471	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /!<Bit 1 /
jhon309	0:ac8863619623	4472	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /!<Bit 2 /
jhon309	0:ac8863619623	4473
jhon309	0:ac8863619623	4474	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /!<Output Compare 1Clear Enable /
jhon309	0:ac8863619623	4475
jhon309	0:ac8863619623	4476	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
jhon309	0:ac8863619623	4477	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /!<Bit 0 /
jhon309	0:ac8863619623	4478	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /!<Bit 1 /
jhon309	0:ac8863619623	4479
jhon309	0:ac8863619623	4480	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /!<Output Compare 2 Fast enable /
jhon309	0:ac8863619623	4481	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /!<Output Compare 2 Preload enable /
jhon309	0:ac8863619623	4482
jhon309	0:ac8863619623	4483	#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
jhon309	0:ac8863619623	4484	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /!<Bit 0 /
jhon309	0:ac8863619623	4485	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /!<Bit 1 /
jhon309	0:ac8863619623	4486	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /!<Bit 2 /
jhon309	0:ac8863619623	4487
jhon309	0:ac8863619623	4488	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /!<Output Compare 2 Clear Enable /
jhon309	0:ac8863619623	4489
jhon309	0:ac8863619623	4490	/---------------------------------------------------------------------------/
jhon309	0:ac8863619623	4491
jhon309	0:ac8863619623	4492	#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
jhon309	0:ac8863619623	4493	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
jhon309	0:ac8863619623	4494	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
jhon309	0:ac8863619623	4495
jhon309	0:ac8863619623	4496	#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
jhon309	0:ac8863619623	4497	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /!<Bit 0 /
jhon309	0:ac8863619623	4498	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /!<Bit 1 /
jhon309	0:ac8863619623	4499	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /!<Bit 2 /
jhon309	0:ac8863619623	4500	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /!<Bit 3 /
jhon309	0:ac8863619623	4501
jhon309	0:ac8863619623	4502	#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
jhon309	0:ac8863619623	4503	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
jhon309	0:ac8863619623	4504	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
jhon309	0:ac8863619623	4505
jhon309	0:ac8863619623	4506	#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
jhon309	0:ac8863619623	4507	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /!<Bit 0 /
jhon309	0:ac8863619623	4508	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /!<Bit 1 /
jhon309	0:ac8863619623	4509	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /!<Bit 2 /
jhon309	0:ac8863619623	4510	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /!<Bit 3 /
jhon309	0:ac8863619623	4511
jhon309	0:ac8863619623	4512	/**************** Bit definition for TIM_CCMR2 register ****************/
jhon309	0:ac8863619623	4513	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
jhon309	0:ac8863619623	4514	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /!<Bit 0 /
jhon309	0:ac8863619623	4515	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /!<Bit 1 /
jhon309	0:ac8863619623	4516
jhon309	0:ac8863619623	4517	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /!<Output Compare 3 Fast enable /
jhon309	0:ac8863619623	4518	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /!<Output Compare 3 Preload enable /
jhon309	0:ac8863619623	4519
jhon309	0:ac8863619623	4520	#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
jhon309	0:ac8863619623	4521	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /!<Bit 0 /
jhon309	0:ac8863619623	4522	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /!<Bit 1 /
jhon309	0:ac8863619623	4523	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /!<Bit 2 /
jhon309	0:ac8863619623	4524
jhon309	0:ac8863619623	4525	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /!<Output Compare 3 Clear Enable /
jhon309	0:ac8863619623	4526
jhon309	0:ac8863619623	4527	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
jhon309	0:ac8863619623	4528	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /!<Bit 0 /
jhon309	0:ac8863619623	4529	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /!<Bit 1 /
jhon309	0:ac8863619623	4530
jhon309	0:ac8863619623	4531	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
jhon309	0:ac8863619623	4532	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
jhon309	0:ac8863619623	4533
jhon309	0:ac8863619623	4534	#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
jhon309	0:ac8863619623	4535	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /!<Bit 0 /
jhon309	0:ac8863619623	4536	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /!<Bit 1 /
jhon309	0:ac8863619623	4537	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /!<Bit 2 /
jhon309	0:ac8863619623	4538
jhon309	0:ac8863619623	4539	#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
jhon309	0:ac8863619623	4540
jhon309	0:ac8863619623	4541	/---------------------------------------------------------------------------/
jhon309	0:ac8863619623	4542
jhon309	0:ac8863619623	4543	#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
jhon309	0:ac8863619623	4544	#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
jhon309	0:ac8863619623	4545	#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
jhon309	0:ac8863619623	4546
jhon309	0:ac8863619623	4547	#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
jhon309	0:ac8863619623	4548	#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /!<Bit 0 /
jhon309	0:ac8863619623	4549	#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /!<Bit 1 /
jhon309	0:ac8863619623	4550	#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /!<Bit 2 /
jhon309	0:ac8863619623	4551	#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /!<Bit 3 /
jhon309	0:ac8863619623	4552
jhon309	0:ac8863619623	4553	#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
jhon309	0:ac8863619623	4554	#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
jhon309	0:ac8863619623	4555	#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
jhon309	0:ac8863619623	4556
jhon309	0:ac8863619623	4557	#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
jhon309	0:ac8863619623	4558	#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /!<Bit 0 /
jhon309	0:ac8863619623	4559	#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /!<Bit 1 /
jhon309	0:ac8863619623	4560	#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /!<Bit 2 /
jhon309	0:ac8863619623	4561	#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /!<Bit 3 /
jhon309	0:ac8863619623	4562
jhon309	0:ac8863619623	4563	/***************** Bit definition for TIM_CCER register ****************/
jhon309	0:ac8863619623	4564	#define TIM_CCER_CC1E ((uint32_t)0x00000001) /!<Capture/Compare 1 output enable /
jhon309	0:ac8863619623	4565	#define TIM_CCER_CC1P ((uint32_t)0x00000002) /!<Capture/Compare 1 output Polarity /
jhon309	0:ac8863619623	4566	#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /!<Capture/Compare 1 Complementary output enable /
jhon309	0:ac8863619623	4567	#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /!<Capture/Compare 1 Complementary output Polarity /
jhon309	0:ac8863619623	4568	#define TIM_CCER_CC2E ((uint32_t)0x00000010) /!<Capture/Compare 2 output enable /
jhon309	0:ac8863619623	4569	#define TIM_CCER_CC2P ((uint32_t)0x00000020) /!<Capture/Compare 2 output Polarity /
jhon309	0:ac8863619623	4570	#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /!<Capture/Compare 2 Complementary output enable /
jhon309	0:ac8863619623	4571	#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /!<Capture/Compare 2 Complementary output Polarity /
jhon309	0:ac8863619623	4572	#define TIM_CCER_CC3E ((uint32_t)0x00000100) /!<Capture/Compare 3 output enable /
jhon309	0:ac8863619623	4573	#define TIM_CCER_CC3P ((uint32_t)0x00000200) /!<Capture/Compare 3 output Polarity /
jhon309	0:ac8863619623	4574	#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /!<Capture/Compare 3 Complementary output enable /
jhon309	0:ac8863619623	4575	#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /!<Capture/Compare 3 Complementary output Polarity /
jhon309	0:ac8863619623	4576	#define TIM_CCER_CC4E ((uint32_t)0x00001000) /!<Capture/Compare 4 output enable /
jhon309	0:ac8863619623	4577	#define TIM_CCER_CC4P ((uint32_t)0x00002000) /!<Capture/Compare 4 output Polarity /
jhon309	0:ac8863619623	4578	#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /!<Capture/Compare 4 Complementary output Polarity /
jhon309	0:ac8863619623	4579
jhon309	0:ac8863619623	4580	/***************** Bit definition for TIM_CNT register *****************/
jhon309	0:ac8863619623	4581	#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /!<Counter Value /
jhon309	0:ac8863619623	4582
jhon309	0:ac8863619623	4583	/***************** Bit definition for TIM_PSC register *****************/
jhon309	0:ac8863619623	4584	#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /!<Prescaler Value /
jhon309	0:ac8863619623	4585
jhon309	0:ac8863619623	4586	/***************** Bit definition for TIM_ARR register *****************/
jhon309	0:ac8863619623	4587	#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /!<actual auto-reload Value /
jhon309	0:ac8863619623	4588
jhon309	0:ac8863619623	4589	/***************** Bit definition for TIM_RCR register *****************/
jhon309	0:ac8863619623	4590	#define TIM_RCR_REP ((uint32_t)0x000000FF) /!<Repetition Counter Value /
jhon309	0:ac8863619623	4591
jhon309	0:ac8863619623	4592	/***************** Bit definition for TIM_CCR1 register ****************/
jhon309	0:ac8863619623	4593	#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /!<Capture/Compare 1 Value /
jhon309	0:ac8863619623	4594
jhon309	0:ac8863619623	4595	/***************** Bit definition for TIM_CCR2 register ****************/
jhon309	0:ac8863619623	4596	#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /!<Capture/Compare 2 Value /
jhon309	0:ac8863619623	4597
jhon309	0:ac8863619623	4598	/***************** Bit definition for TIM_CCR3 register ****************/
jhon309	0:ac8863619623	4599	#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /!<Capture/Compare 3 Value /
jhon309	0:ac8863619623	4600
jhon309	0:ac8863619623	4601	/***************** Bit definition for TIM_CCR4 register ****************/
jhon309	0:ac8863619623	4602	#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /!<Capture/Compare 4 Value /
jhon309	0:ac8863619623	4603
jhon309	0:ac8863619623	4604	/***************** Bit definition for TIM_BDTR register ****************/
jhon309	0:ac8863619623	4605	#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
jhon309	0:ac8863619623	4606	#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /!<Bit 0 /
jhon309	0:ac8863619623	4607	#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /!<Bit 1 /
jhon309	0:ac8863619623	4608	#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /!<Bit 2 /
jhon309	0:ac8863619623	4609	#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /!<Bit 3 /
jhon309	0:ac8863619623	4610	#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /!<Bit 4 /
jhon309	0:ac8863619623	4611	#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /!<Bit 5 /
jhon309	0:ac8863619623	4612	#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /!<Bit 6 /
jhon309	0:ac8863619623	4613	#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /!<Bit 7 /
jhon309	0:ac8863619623	4614
jhon309	0:ac8863619623	4615	#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /!<LOCK[1:0] bits (Lock Configuration) /
jhon309	0:ac8863619623	4616	#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /!<Bit 0 /
jhon309	0:ac8863619623	4617	#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /!<Bit 1 /
jhon309	0:ac8863619623	4618
jhon309	0:ac8863619623	4619	#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /!<Off-State Selection for Idle mode /
jhon309	0:ac8863619623	4620	#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /!<Off-State Selection for Run mode /
jhon309	0:ac8863619623	4621	#define TIM_BDTR_BKE ((uint32_t)0x00001000) /!<Break enable /
jhon309	0:ac8863619623	4622	#define TIM_BDTR_BKP ((uint32_t)0x00002000) /!<Break Polarity /
jhon309	0:ac8863619623	4623	#define TIM_BDTR_AOE ((uint32_t)0x00004000) /!<Automatic Output enable /
jhon309	0:ac8863619623	4624	#define TIM_BDTR_MOE ((uint32_t)0x00008000) /!<Main Output enable /
jhon309	0:ac8863619623	4625
jhon309	0:ac8863619623	4626	/***************** Bit definition for TIM_DCR register *****************/
jhon309	0:ac8863619623	4627	#define TIM_DCR_DBA ((uint32_t)0x0000001F) /!<DBA[4:0] bits (DMA Base Address) /
jhon309	0:ac8863619623	4628	#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /!<Bit 0 /
jhon309	0:ac8863619623	4629	#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /!<Bit 1 /
jhon309	0:ac8863619623	4630	#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /!<Bit 2 /
jhon309	0:ac8863619623	4631	#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /!<Bit 3 /
jhon309	0:ac8863619623	4632	#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /!<Bit 4 /
jhon309	0:ac8863619623	4633
jhon309	0:ac8863619623	4634	#define TIM_DCR_DBL ((uint32_t)0x00001F00) /!<DBL[4:0] bits (DMA Burst Length) /
jhon309	0:ac8863619623	4635	#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /!<Bit 0 /
jhon309	0:ac8863619623	4636	#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /!<Bit 1 /
jhon309	0:ac8863619623	4637	#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /!<Bit 2 /
jhon309	0:ac8863619623	4638	#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /!<Bit 3 /
jhon309	0:ac8863619623	4639	#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /!<Bit 4 /
jhon309	0:ac8863619623	4640
jhon309	0:ac8863619623	4641	/***************** Bit definition for TIM_DMAR register ****************/
jhon309	0:ac8863619623	4642	#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /!<DMA register for burst accesses /
jhon309	0:ac8863619623	4643
jhon309	0:ac8863619623	4644	/***************** Bit definition for TIM14_OR register ******************/
jhon309	0:ac8863619623	4645	#define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) /
jhon309	0:ac8863619623	4646	#define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /!<Bit 0 /
jhon309	0:ac8863619623	4647	#define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /!<Bit 1 /
jhon309	0:ac8863619623	4648
jhon309	0:ac8863619623	4649	/******************************************************************************/
jhon309	0:ac8863619623	4650	/* */
jhon309	0:ac8863619623	4651	/* Touch Sensing Controller (TSC) */
jhon309	0:ac8863619623	4652	/* */
jhon309	0:ac8863619623	4653	/******************************************************************************/
jhon309	0:ac8863619623	4654	/***************** Bit definition for TSC_CR register *******************/
jhon309	0:ac8863619623	4655	#define TSC_CR_TSCE ((uint32_t)0x00000001) /!<Touch sensing controller enable /
jhon309	0:ac8863619623	4656	#define TSC_CR_START ((uint32_t)0x00000002) /!<Start acquisition /
jhon309	0:ac8863619623	4657	#define TSC_CR_AM ((uint32_t)0x00000004) /!<Acquisition mode /
jhon309	0:ac8863619623	4658	#define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /!<Synchronization pin polarity /
jhon309	0:ac8863619623	4659	#define TSC_CR_IODEF ((uint32_t)0x00000010) /!<IO default mode /
jhon309	0:ac8863619623	4660
jhon309	0:ac8863619623	4661	#define TSC_CR_MCV ((uint32_t)0x000000E0) /!<MCV[2:0] bits (Max Count Value) /
jhon309	0:ac8863619623	4662	#define TSC_CR_MCV_0 ((uint32_t)0x00000020) /!<Bit 0 /
jhon309	0:ac8863619623	4663	#define TSC_CR_MCV_1 ((uint32_t)0x00000040) /!<Bit 1 /
jhon309	0:ac8863619623	4664	#define TSC_CR_MCV_2 ((uint32_t)0x00000080) /!<Bit 2 /
jhon309	0:ac8863619623	4665
jhon309	0:ac8863619623	4666	#define TSC_CR_PGPSC ((uint32_t)0x00007000) /!<PGPSC[2:0] bits (Pulse Generator Prescaler) /
jhon309	0:ac8863619623	4667	#define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /!<Bit 0 /
jhon309	0:ac8863619623	4668	#define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /!<Bit 1 /
jhon309	0:ac8863619623	4669	#define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /!<Bit 2 /
jhon309	0:ac8863619623	4670
jhon309	0:ac8863619623	4671	#define TSC_CR_SSPSC ((uint32_t)0x00008000) /!<Spread Spectrum Prescaler /
jhon309	0:ac8863619623	4672	#define TSC_CR_SSE ((uint32_t)0x00010000) /!<Spread Spectrum Enable /
jhon309	0:ac8863619623	4673
jhon309	0:ac8863619623	4674	#define TSC_CR_SSD ((uint32_t)0x00FE0000) /!<SSD[6:0] bits (Spread Spectrum Deviation) /
jhon309	0:ac8863619623	4675	#define TSC_CR_SSD_0 ((uint32_t)0x00020000) /!<Bit 0 /
jhon309	0:ac8863619623	4676	#define TSC_CR_SSD_1 ((uint32_t)0x00040000) /!<Bit 1 /
jhon309	0:ac8863619623	4677	#define TSC_CR_SSD_2 ((uint32_t)0x00080000) /!<Bit 2 /
jhon309	0:ac8863619623	4678	#define TSC_CR_SSD_3 ((uint32_t)0x00100000) /!<Bit 3 /
jhon309	0:ac8863619623	4679	#define TSC_CR_SSD_4 ((uint32_t)0x00200000) /!<Bit 4 /
jhon309	0:ac8863619623	4680	#define TSC_CR_SSD_5 ((uint32_t)0x00400000) /!<Bit 5 /
jhon309	0:ac8863619623	4681	#define TSC_CR_SSD_6 ((uint32_t)0x00800000) /!<Bit 6 /
jhon309	0:ac8863619623	4682
jhon309	0:ac8863619623	4683	#define TSC_CR_CTPL ((uint32_t)0x0F000000) /!<CTPL[3:0] bits (Charge Transfer pulse low) /
jhon309	0:ac8863619623	4684	#define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /!<Bit 0 /
jhon309	0:ac8863619623	4685	#define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /!<Bit 1 /
jhon309	0:ac8863619623	4686	#define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /!<Bit 2 /
jhon309	0:ac8863619623	4687	#define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /!<Bit 3 /
jhon309	0:ac8863619623	4688
jhon309	0:ac8863619623	4689	#define TSC_CR_CTPH ((uint32_t)0xF0000000) /!<CTPH[3:0] bits (Charge Transfer pulse high) /
jhon309	0:ac8863619623	4690	#define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /!<Bit 0 /
jhon309	0:ac8863619623	4691	#define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /!<Bit 1 /
jhon309	0:ac8863619623	4692	#define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /!<Bit 2 /
jhon309	0:ac8863619623	4693	#define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /!<Bit 3 /
jhon309	0:ac8863619623	4694
jhon309	0:ac8863619623	4695	/***************** Bit definition for TSC_IER register ******************/
jhon309	0:ac8863619623	4696	#define TSC_IER_EOAIE ((uint32_t)0x00000001) /!<End of acquisition interrupt enable /
jhon309	0:ac8863619623	4697	#define TSC_IER_MCEIE ((uint32_t)0x00000002) /!<Max count error interrupt enable /
jhon309	0:ac8863619623	4698
jhon309	0:ac8863619623	4699	/***************** Bit definition for TSC_ICR register ******************/
jhon309	0:ac8863619623	4700	#define TSC_ICR_EOAIC ((uint32_t)0x00000001) /!<End of acquisition interrupt clear /
jhon309	0:ac8863619623	4701	#define TSC_ICR_MCEIC ((uint32_t)0x00000002) /!<Max count error interrupt clear /
jhon309	0:ac8863619623	4702
jhon309	0:ac8863619623	4703	/***************** Bit definition for TSC_ISR register ******************/
jhon309	0:ac8863619623	4704	#define TSC_ISR_EOAF ((uint32_t)0x00000001) /!<End of acquisition flag /
jhon309	0:ac8863619623	4705	#define TSC_ISR_MCEF ((uint32_t)0x00000002) /!<Max count error flag /
jhon309	0:ac8863619623	4706
jhon309	0:ac8863619623	4707	/***************** Bit definition for TSC_IOHCR register ****************/
jhon309	0:ac8863619623	4708	#define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4709	#define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4710	#define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4711	#define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4712	#define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4713	#define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4714	#define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4715	#define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4716	#define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4717	#define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4718	#define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4719	#define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4720	#define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4721	#define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4722	#define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4723	#define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4724	#define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4725	#define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4726	#define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4727	#define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4728	#define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4729	#define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4730	#define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4731	#define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4732	#define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4733	#define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4734	#define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4735	#define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4736	#define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4737	#define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4738	#define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4739	#define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 schmitt trigger hysteresis mode /
jhon309	0:ac8863619623	4740
jhon309	0:ac8863619623	4741	/***************** Bit definition for TSC_IOASCR register ***************/
jhon309	0:ac8863619623	4742	#define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 analog switch enable /
jhon309	0:ac8863619623	4743	#define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 analog switch enable /
jhon309	0:ac8863619623	4744	#define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 analog switch enable /
jhon309	0:ac8863619623	4745	#define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 analog switch enable /
jhon309	0:ac8863619623	4746	#define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 analog switch enable /
jhon309	0:ac8863619623	4747	#define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 analog switch enable /
jhon309	0:ac8863619623	4748	#define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 analog switch enable /
jhon309	0:ac8863619623	4749	#define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 analog switch enable /
jhon309	0:ac8863619623	4750	#define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 analog switch enable /
jhon309	0:ac8863619623	4751	#define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 analog switch enable /
jhon309	0:ac8863619623	4752	#define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 analog switch enable /
jhon309	0:ac8863619623	4753	#define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 analog switch enable /
jhon309	0:ac8863619623	4754	#define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 analog switch enable /
jhon309	0:ac8863619623	4755	#define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 analog switch enable /
jhon309	0:ac8863619623	4756	#define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 analog switch enable /
jhon309	0:ac8863619623	4757	#define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 analog switch enable /
jhon309	0:ac8863619623	4758	#define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 analog switch enable /
jhon309	0:ac8863619623	4759	#define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 analog switch enable /
jhon309	0:ac8863619623	4760	#define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 analog switch enable /
jhon309	0:ac8863619623	4761	#define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 analog switch enable /
jhon309	0:ac8863619623	4762	#define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 analog switch enable /
jhon309	0:ac8863619623	4763	#define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 analog switch enable /
jhon309	0:ac8863619623	4764	#define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 analog switch enable /
jhon309	0:ac8863619623	4765	#define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 analog switch enable /
jhon309	0:ac8863619623	4766	#define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 analog switch enable /
jhon309	0:ac8863619623	4767	#define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 analog switch enable /
jhon309	0:ac8863619623	4768	#define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 analog switch enable /
jhon309	0:ac8863619623	4769	#define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 analog switch enable /
jhon309	0:ac8863619623	4770	#define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 analog switch enable /
jhon309	0:ac8863619623	4771	#define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 analog switch enable /
jhon309	0:ac8863619623	4772	#define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 analog switch enable /
jhon309	0:ac8863619623	4773	#define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 analog switch enable /
jhon309	0:ac8863619623	4774
jhon309	0:ac8863619623	4775	/***************** Bit definition for TSC_IOSCR register ****************/
jhon309	0:ac8863619623	4776	#define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 sampling mode /
jhon309	0:ac8863619623	4777	#define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 sampling mode /
jhon309	0:ac8863619623	4778	#define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 sampling mode /
jhon309	0:ac8863619623	4779	#define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 sampling mode /
jhon309	0:ac8863619623	4780	#define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 sampling mode /
jhon309	0:ac8863619623	4781	#define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 sampling mode /
jhon309	0:ac8863619623	4782	#define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 sampling mode /
jhon309	0:ac8863619623	4783	#define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 sampling mode /
jhon309	0:ac8863619623	4784	#define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 sampling mode /
jhon309	0:ac8863619623	4785	#define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 sampling mode /
jhon309	0:ac8863619623	4786	#define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 sampling mode /
jhon309	0:ac8863619623	4787	#define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 sampling mode /
jhon309	0:ac8863619623	4788	#define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 sampling mode /
jhon309	0:ac8863619623	4789	#define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 sampling mode /
jhon309	0:ac8863619623	4790	#define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 sampling mode /
jhon309	0:ac8863619623	4791	#define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 sampling mode /
jhon309	0:ac8863619623	4792	#define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 sampling mode /
jhon309	0:ac8863619623	4793	#define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 sampling mode /
jhon309	0:ac8863619623	4794	#define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 sampling mode /
jhon309	0:ac8863619623	4795	#define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 sampling mode /
jhon309	0:ac8863619623	4796	#define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 sampling mode /
jhon309	0:ac8863619623	4797	#define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 sampling mode /
jhon309	0:ac8863619623	4798	#define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 sampling mode /
jhon309	0:ac8863619623	4799	#define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 sampling mode /
jhon309	0:ac8863619623	4800	#define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 sampling mode /
jhon309	0:ac8863619623	4801	#define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 sampling mode /
jhon309	0:ac8863619623	4802	#define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 sampling mode /
jhon309	0:ac8863619623	4803	#define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 sampling mode /
jhon309	0:ac8863619623	4804	#define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 sampling mode /
jhon309	0:ac8863619623	4805	#define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 sampling mode /
jhon309	0:ac8863619623	4806	#define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 sampling mode /
jhon309	0:ac8863619623	4807	#define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 sampling mode /
jhon309	0:ac8863619623	4808
jhon309	0:ac8863619623	4809	/***************** Bit definition for TSC_IOCCR register ****************/
jhon309	0:ac8863619623	4810	#define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 channel mode /
jhon309	0:ac8863619623	4811	#define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 channel mode /
jhon309	0:ac8863619623	4812	#define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 channel mode /
jhon309	0:ac8863619623	4813	#define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 channel mode /
jhon309	0:ac8863619623	4814	#define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 channel mode /
jhon309	0:ac8863619623	4815	#define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 channel mode /
jhon309	0:ac8863619623	4816	#define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 channel mode /
jhon309	0:ac8863619623	4817	#define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 channel mode /
jhon309	0:ac8863619623	4818	#define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 channel mode /
jhon309	0:ac8863619623	4819	#define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 channel mode /
jhon309	0:ac8863619623	4820	#define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 channel mode /
jhon309	0:ac8863619623	4821	#define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 channel mode /
jhon309	0:ac8863619623	4822	#define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 channel mode /
jhon309	0:ac8863619623	4823	#define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 channel mode /
jhon309	0:ac8863619623	4824	#define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 channel mode /
jhon309	0:ac8863619623	4825	#define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 channel mode /
jhon309	0:ac8863619623	4826	#define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 channel mode /
jhon309	0:ac8863619623	4827	#define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 channel mode /
jhon309	0:ac8863619623	4828	#define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 channel mode /
jhon309	0:ac8863619623	4829	#define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 channel mode /
jhon309	0:ac8863619623	4830	#define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 channel mode /
jhon309	0:ac8863619623	4831	#define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 channel mode /
jhon309	0:ac8863619623	4832	#define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 channel mode /
jhon309	0:ac8863619623	4833	#define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 channel mode /
jhon309	0:ac8863619623	4834	#define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 channel mode /
jhon309	0:ac8863619623	4835	#define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 channel mode /
jhon309	0:ac8863619623	4836	#define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 channel mode /
jhon309	0:ac8863619623	4837	#define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 channel mode /
jhon309	0:ac8863619623	4838	#define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 channel mode /
jhon309	0:ac8863619623	4839	#define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 channel mode /
jhon309	0:ac8863619623	4840	#define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 channel mode /
jhon309	0:ac8863619623	4841	#define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 channel mode /
jhon309	0:ac8863619623	4842
jhon309	0:ac8863619623	4843	/***************** Bit definition for TSC_IOGCSR register ***************/
jhon309	0:ac8863619623	4844	#define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /!<Analog IO GROUP1 enable /
jhon309	0:ac8863619623	4845	#define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /!<Analog IO GROUP2 enable /
jhon309	0:ac8863619623	4846	#define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /!<Analog IO GROUP3 enable /
jhon309	0:ac8863619623	4847	#define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /!<Analog IO GROUP4 enable /
jhon309	0:ac8863619623	4848	#define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /!<Analog IO GROUP5 enable /
jhon309	0:ac8863619623	4849	#define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /!<Analog IO GROUP6 enable /
jhon309	0:ac8863619623	4850	#define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /!<Analog IO GROUP7 enable /
jhon309	0:ac8863619623	4851	#define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /!<Analog IO GROUP8 enable /
jhon309	0:ac8863619623	4852	#define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /!<Analog IO GROUP1 status /
jhon309	0:ac8863619623	4853	#define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /!<Analog IO GROUP2 status /
jhon309	0:ac8863619623	4854	#define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /!<Analog IO GROUP3 status /
jhon309	0:ac8863619623	4855	#define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /!<Analog IO GROUP4 status /
jhon309	0:ac8863619623	4856	#define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /!<Analog IO GROUP5 status /
jhon309	0:ac8863619623	4857	#define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /!<Analog IO GROUP6 status /
jhon309	0:ac8863619623	4858	#define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /!<Analog IO GROUP7 status /
jhon309	0:ac8863619623	4859	#define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /!<Analog IO GROUP8 status /
jhon309	0:ac8863619623	4860
jhon309	0:ac8863619623	4861	/***************** Bit definition for TSC_IOGXCR register ***************/
jhon309	0:ac8863619623	4862	#define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /!<CNT[13:0] bits (Counter value) /
jhon309	0:ac8863619623	4863
jhon309	0:ac8863619623	4864	/******************************************************************************/
jhon309	0:ac8863619623	4865	/* */
jhon309	0:ac8863619623	4866	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
jhon309	0:ac8863619623	4867	/* */
jhon309	0:ac8863619623	4868	/******************************************************************************/
jhon309	0:ac8863619623	4869	/**************** Bit definition for USART_CR1 register *****************/
jhon309	0:ac8863619623	4870	#define USART_CR1_UE ((uint32_t)0x00000001) /!< USART Enable /
jhon309	0:ac8863619623	4871	#define USART_CR1_UESM ((uint32_t)0x00000002) /!< USART Enable in STOP Mode /
jhon309	0:ac8863619623	4872	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
jhon309	0:ac8863619623	4873	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
jhon309	0:ac8863619623	4874	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
jhon309	0:ac8863619623	4875	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
jhon309	0:ac8863619623	4876	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
jhon309	0:ac8863619623	4877	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< TXE Interrupt Enable /
jhon309	0:ac8863619623	4878	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
jhon309	0:ac8863619623	4879	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
jhon309	0:ac8863619623	4880	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
jhon309	0:ac8863619623	4881	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Receiver Wakeup method /
jhon309	0:ac8863619623	4882	#define USART_CR1_M0 ((uint32_t)0x00001000) /!< Word length bit 0 /
jhon309	0:ac8863619623	4883	#define USART_CR1_MME ((uint32_t)0x00002000) /!< Mute Mode Enable /
jhon309	0:ac8863619623	4884	#define USART_CR1_CMIE ((uint32_t)0x00004000) /!< Character match interrupt enable /
jhon309	0:ac8863619623	4885	#define USART_CR1_OVER8 ((uint32_t)0x00008000) /!< Oversampling by 8-bit or 16-bit mode /
jhon309	0:ac8863619623	4886	#define USART_CR1_DEDT ((uint32_t)0x001F0000) /!< DEDT[4:0] bits (Driver Enable Deassertion Time) /
jhon309	0:ac8863619623	4887	#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /!< Bit 0 /
jhon309	0:ac8863619623	4888	#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /!< Bit 1 /
jhon309	0:ac8863619623	4889	#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /!< Bit 2 /
jhon309	0:ac8863619623	4890	#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /!< Bit 3 /
jhon309	0:ac8863619623	4891	#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /!< Bit 4 /
jhon309	0:ac8863619623	4892	#define USART_CR1_DEAT ((uint32_t)0x03E00000) /!< DEAT[4:0] bits (Driver Enable Assertion Time) /
jhon309	0:ac8863619623	4893	#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /!< Bit 0 /
jhon309	0:ac8863619623	4894	#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /!< Bit 1 /
jhon309	0:ac8863619623	4895	#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /!< Bit 2 /
jhon309	0:ac8863619623	4896	#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /!< Bit 3 /
jhon309	0:ac8863619623	4897	#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /!< Bit 4 /
jhon309	0:ac8863619623	4898	#define USART_CR1_RTOIE ((uint32_t)0x04000000) /!< Receive Time Out interrupt enable /
jhon309	0:ac8863619623	4899	#define USART_CR1_EOBIE ((uint32_t)0x08000000) /!< End of Block interrupt enable /
jhon309	0:ac8863619623	4900	#define USART_CR1_M1 ((uint32_t)0x10000000) /!< Word length bit 1 /
jhon309	0:ac8863619623	4901	#define USART_CR1_M ((uint32_t)0x10001000) /!< [M1:M0] Word length /
jhon309	0:ac8863619623	4902
jhon309	0:ac8863619623	4903	/**************** Bit definition for USART_CR2 register *****************/
jhon309	0:ac8863619623	4904	#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /!< 7-bit or 4-bit Address Detection /
jhon309	0:ac8863619623	4905	#define USART_CR2_LBDL ((uint32_t)0x00000020) /!< LIN Break Detection Length /
jhon309	0:ac8863619623	4906	#define USART_CR2_LBDIE ((uint32_t)0x00000040) /!< LIN Break Detection Interrupt Enable /
jhon309	0:ac8863619623	4907	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
jhon309	0:ac8863619623	4908	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
jhon309	0:ac8863619623	4909	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
jhon309	0:ac8863619623	4910	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
jhon309	0:ac8863619623	4911	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
jhon309	0:ac8863619623	4912	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
jhon309	0:ac8863619623	4913	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
jhon309	0:ac8863619623	4914	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< LIN mode enable /
jhon309	0:ac8863619623	4915	#define USART_CR2_SWAP ((uint32_t)0x00008000) /!< SWAP TX/RX pins /
jhon309	0:ac8863619623	4916	#define USART_CR2_RXINV ((uint32_t)0x00010000) /!< RX pin active level inversion /
jhon309	0:ac8863619623	4917	#define USART_CR2_TXINV ((uint32_t)0x00020000) /!< TX pin active level inversion /
jhon309	0:ac8863619623	4918	#define USART_CR2_DATAINV ((uint32_t)0x00040000) /!< Binary data inversion /
jhon309	0:ac8863619623	4919	#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /!< Most Significant Bit First /
jhon309	0:ac8863619623	4920	#define USART_CR2_ABREN ((uint32_t)0x00100000) /!< Auto Baud-Rate Enable/
jhon309	0:ac8863619623	4921	#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) /
jhon309	0:ac8863619623	4922	#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /!< Bit 0 /
jhon309	0:ac8863619623	4923	#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /!< Bit 1 /
jhon309	0:ac8863619623	4924	#define USART_CR2_RTOEN ((uint32_t)0x00800000) /!< Receiver Time-Out enable /
jhon309	0:ac8863619623	4925	#define USART_CR2_ADD ((uint32_t)0xFF000000) /!< Address of the USART node /
jhon309	0:ac8863619623	4926
jhon309	0:ac8863619623	4927	/**************** Bit definition for USART_CR3 register *****************/
jhon309	0:ac8863619623	4928	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
jhon309	0:ac8863619623	4929	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< IrDA mode Enable /
jhon309	0:ac8863619623	4930	#define USART_CR3_IRLP ((uint32_t)0x00000004) /!< IrDA Low-Power /
jhon309	0:ac8863619623	4931	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
jhon309	0:ac8863619623	4932	#define USART_CR3_NACK ((uint32_t)0x00000010) /!< SmartCard NACK enable /
jhon309	0:ac8863619623	4933	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< SmartCard mode enable /
jhon309	0:ac8863619623	4934	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
jhon309	0:ac8863619623	4935	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
jhon309	0:ac8863619623	4936	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
jhon309	0:ac8863619623	4937	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
jhon309	0:ac8863619623	4938	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
jhon309	0:ac8863619623	4939	#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /!< One sample bit method enable /
jhon309	0:ac8863619623	4940	#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /!< Overrun Disable /
jhon309	0:ac8863619623	4941	#define USART_CR3_DDRE ((uint32_t)0x00002000) /!< DMA Disable on Reception Error /
jhon309	0:ac8863619623	4942	#define USART_CR3_DEM ((uint32_t)0x00004000) /!< Driver Enable Mode /
jhon309	0:ac8863619623	4943	#define USART_CR3_DEP ((uint32_t)0x00008000) /!< Driver Enable Polarity Selection /
jhon309	0:ac8863619623	4944	#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) /
jhon309	0:ac8863619623	4945	#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /!< Bit 0 /
jhon309	0:ac8863619623	4946	#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /!< Bit 1 /
jhon309	0:ac8863619623	4947	#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /!< Bit 2 /
jhon309	0:ac8863619623	4948	#define USART_CR3_WUS ((uint32_t)0x00300000) /!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) /
jhon309	0:ac8863619623	4949	#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /!< Bit 0 /
jhon309	0:ac8863619623	4950	#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /!< Bit 1 /
jhon309	0:ac8863619623	4951	#define USART_CR3_WUFIE ((uint32_t)0x00400000) /!< Wake Up Interrupt Enable /
jhon309	0:ac8863619623	4952
jhon309	0:ac8863619623	4953	/**************** Bit definition for USART_BRR register *****************/
jhon309	0:ac8863619623	4954	#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /!< Fraction of USARTDIV /
jhon309	0:ac8863619623	4955	#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /!< Mantissa of USARTDIV /
jhon309	0:ac8863619623	4956
jhon309	0:ac8863619623	4957	/**************** Bit definition for USART_GTPR register ****************/
jhon309	0:ac8863619623	4958	#define USART_GTPR_PSC ((uint32_t)0x000000FF) /!< PSC[7:0] bits (Prescaler value) /
jhon309	0:ac8863619623	4959	#define USART_GTPR_GT ((uint32_t)0x0000FF00) /!< GT[7:0] bits (Guard time value) /
jhon309	0:ac8863619623	4960
jhon309	0:ac8863619623	4961
jhon309	0:ac8863619623	4962	/***************** Bit definition for USART_RTOR register ***************/
jhon309	0:ac8863619623	4963	#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /!< Receiver Time Out Value /
jhon309	0:ac8863619623	4964	#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /!< Block Length /
jhon309	0:ac8863619623	4965
jhon309	0:ac8863619623	4966	/***************** Bit definition for USART_RQR register ****************/
jhon309	0:ac8863619623	4967	#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /!< Auto-Baud Rate Request /
jhon309	0:ac8863619623	4968	#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /!< Send Break Request /
jhon309	0:ac8863619623	4969	#define USART_RQR_MMRQ ((uint32_t)0x00000004) /!< Mute Mode Request /
jhon309	0:ac8863619623	4970	#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /!< Receive Data flush Request /
jhon309	0:ac8863619623	4971	#define USART_RQR_TXFRQ ((uint32_t)0x00000010) /!< Transmit data flush Request /
jhon309	0:ac8863619623	4972
jhon309	0:ac8863619623	4973	/***************** Bit definition for USART_ISR register ****************/
jhon309	0:ac8863619623	4974	#define USART_ISR_PE ((uint32_t)0x00000001) /!< Parity Error /
jhon309	0:ac8863619623	4975	#define USART_ISR_FE ((uint32_t)0x00000002) /!< Framing Error /
jhon309	0:ac8863619623	4976	#define USART_ISR_NE ((uint32_t)0x00000004) /!< Noise detected Flag /
jhon309	0:ac8863619623	4977	#define USART_ISR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
jhon309	0:ac8863619623	4978	#define USART_ISR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
jhon309	0:ac8863619623	4979	#define USART_ISR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
jhon309	0:ac8863619623	4980	#define USART_ISR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
jhon309	0:ac8863619623	4981	#define USART_ISR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
jhon309	0:ac8863619623	4982	#define USART_ISR_LBDF ((uint32_t)0x00000100) /!< LIN Break Detection Flag /
jhon309	0:ac8863619623	4983	#define USART_ISR_CTSIF ((uint32_t)0x00000200) /!< CTS interrupt flag /
jhon309	0:ac8863619623	4984	#define USART_ISR_CTS ((uint32_t)0x00000400) /!< CTS flag /
jhon309	0:ac8863619623	4985	#define USART_ISR_RTOF ((uint32_t)0x00000800) /!< Receiver Time Out /
jhon309	0:ac8863619623	4986	#define USART_ISR_EOBF ((uint32_t)0x00001000) /!< End Of Block Flag /
jhon309	0:ac8863619623	4987	#define USART_ISR_ABRE ((uint32_t)0x00004000) /!< Auto-Baud Rate Error /
jhon309	0:ac8863619623	4988	#define USART_ISR_ABRF ((uint32_t)0x00008000) /!< Auto-Baud Rate Flag /
jhon309	0:ac8863619623	4989	#define USART_ISR_BUSY ((uint32_t)0x00010000) /!< Busy Flag /
jhon309	0:ac8863619623	4990	#define USART_ISR_CMF ((uint32_t)0x00020000) /!< Character Match Flag /
jhon309	0:ac8863619623	4991	#define USART_ISR_SBKF ((uint32_t)0x00040000) /!< Send Break Flag /
jhon309	0:ac8863619623	4992	#define USART_ISR_RWU ((uint32_t)0x00080000) /!< Receive Wake Up from mute mode Flag /
jhon309	0:ac8863619623	4993	#define USART_ISR_WUF ((uint32_t)0x00100000) /!< Wake Up from stop mode Flag /
jhon309	0:ac8863619623	4994	#define USART_ISR_TEACK ((uint32_t)0x00200000) /!< Transmit Enable Acknowledge Flag /
jhon309	0:ac8863619623	4995	#define USART_ISR_REACK ((uint32_t)0x00400000) /!< Receive Enable Acknowledge Flag /
jhon309	0:ac8863619623	4996
jhon309	0:ac8863619623	4997	/***************** Bit definition for USART_ICR register ****************/
jhon309	0:ac8863619623	4998	#define USART_ICR_PECF ((uint32_t)0x00000001) /!< Parity Error Clear Flag /
jhon309	0:ac8863619623	4999	#define USART_ICR_FECF ((uint32_t)0x00000002) /!< Framing Error Clear Flag /
jhon309	0:ac8863619623	5000	#define USART_ICR_NCF ((uint32_t)0x00000004) /!< Noise detected Clear Flag /
jhon309	0:ac8863619623	5001	#define USART_ICR_ORECF ((uint32_t)0x00000008) /!< OverRun Error Clear Flag /
jhon309	0:ac8863619623	5002	#define USART_ICR_IDLECF ((uint32_t)0x00000010) /!< IDLE line detected Clear Flag /
jhon309	0:ac8863619623	5003	#define USART_ICR_TCCF ((uint32_t)0x00000040) /!< Transmission Complete Clear Flag /
jhon309	0:ac8863619623	5004	#define USART_ICR_LBDCF ((uint32_t)0x00000100) /!< LIN Break Detection Clear Flag /
jhon309	0:ac8863619623	5005	#define USART_ICR_CTSCF ((uint32_t)0x00000200) /!< CTS Interrupt Clear Flag /
jhon309	0:ac8863619623	5006	#define USART_ICR_RTOCF ((uint32_t)0x00000800) /!< Receiver Time Out Clear Flag /
jhon309	0:ac8863619623	5007	#define USART_ICR_EOBCF ((uint32_t)0x00001000) /!< End Of Block Clear Flag /
jhon309	0:ac8863619623	5008	#define USART_ICR_CMCF ((uint32_t)0x00020000) /!< Character Match Clear Flag /
jhon309	0:ac8863619623	5009	#define USART_ICR_WUCF ((uint32_t)0x00100000) /!< Wake Up from stop mode Clear Flag /
jhon309	0:ac8863619623	5010
jhon309	0:ac8863619623	5011	/***************** Bit definition for USART_RDR register ****************/
jhon309	0:ac8863619623	5012	#define USART_RDR_RDR ((uint16_t)0x01FF) /!< RDR[8:0] bits (Receive Data value) /
jhon309	0:ac8863619623	5013
jhon309	0:ac8863619623	5014	/***************** Bit definition for USART_TDR register ****************/
jhon309	0:ac8863619623	5015	#define USART_TDR_TDR ((uint16_t)0x01FF) /!< TDR[8:0] bits (Transmit Data value) /
jhon309	0:ac8863619623	5016
jhon309	0:ac8863619623	5017	/******************************************************************************/
jhon309	0:ac8863619623	5018	/* */
jhon309	0:ac8863619623	5019	/* USB Device General registers */
jhon309	0:ac8863619623	5020	/* */
jhon309	0:ac8863619623	5021	/******************************************************************************/
jhon309	0:ac8863619623	5022	#define USB_CNTR (USB_BASE + 0x40) /!< Control register /
jhon309	0:ac8863619623	5023	#define USB_ISTR (USB_BASE + 0x44) /!< Interrupt status register /
jhon309	0:ac8863619623	5024	#define USB_FNR (USB_BASE + 0x48) /!< Frame number register /
jhon309	0:ac8863619623	5025	#define USB_DADDR (USB_BASE + 0x4C) /!< Device address register /
jhon309	0:ac8863619623	5026	#define USB_BTABLE (USB_BASE + 0x50) /!< Buffer Table address register /
jhon309	0:ac8863619623	5027	#define USB_LPMCSR (USB_BASE + 0x54) /!< LPM Control and Status register /
jhon309	0:ac8863619623	5028	#define USB_BCDR (USB_BASE + 0x58) /!< Battery Charging detector register/
jhon309	0:ac8863619623	5029
jhon309	0:ac8863619623	5030	/************************** ISTR interrupt events ***********************/
jhon309	0:ac8863619623	5031	#define USB_ISTR_CTR ((uint16_t)0x8000) /!< Correct TRansfer (clear-only bit) /
jhon309	0:ac8863619623	5032	#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /!< DMA OVeR/underrun (clear-only bit) /
jhon309	0:ac8863619623	5033	#define USB_ISTR_ERR ((uint16_t)0x2000) /!< ERRor (clear-only bit) /
jhon309	0:ac8863619623	5034	#define USB_ISTR_WKUP ((uint16_t)0x1000) /!< WaKe UP (clear-only bit) /
jhon309	0:ac8863619623	5035	#define USB_ISTR_SUSP ((uint16_t)0x0800) /!< SUSPend (clear-only bit) /
jhon309	0:ac8863619623	5036	#define USB_ISTR_RESET ((uint16_t)0x0400) /!< RESET (clear-only bit) /
jhon309	0:ac8863619623	5037	#define USB_ISTR_SOF ((uint16_t)0x0200) /!< Start Of Frame (clear-only bit) /
jhon309	0:ac8863619623	5038	#define USB_ISTR_ESOF ((uint16_t)0x0100) /!< Expected Start Of Frame (clear-only bit) /
jhon309	0:ac8863619623	5039	#define USB_ISTR_L1REQ ((uint16_t)0x0080) /!< LPM L1 state request /
jhon309	0:ac8863619623	5040	#define USB_ISTR_DIR ((uint16_t)0x0010) /!< DIRection of transaction (read-only bit) /
jhon309	0:ac8863619623	5041	#define USB_ISTR_EP_ID ((uint16_t)0x000F) /!< EndPoint IDentifier (read-only bit) /
jhon309	0:ac8863619623	5042
jhon309	0:ac8863619623	5043	#define USB_CLR_CTR (~USB_ISTR_CTR) /!< clear Correct TRansfer bit /
jhon309	0:ac8863619623	5044	#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /!< clear DMA OVeR/underrun bit/
jhon309	0:ac8863619623	5045	#define USB_CLR_ERR (~USB_ISTR_ERR) /!< clear ERRor bit /
jhon309	0:ac8863619623	5046	#define USB_CLR_WKUP (~USB_ISTR_WKUP) /!< clear WaKe UP bit /
jhon309	0:ac8863619623	5047	#define USB_CLR_SUSP (~USB_ISTR_SUSP) /!< clear SUSPend bit /
jhon309	0:ac8863619623	5048	#define USB_CLR_RESET (~USB_ISTR_RESET) /!< clear RESET bit /
jhon309	0:ac8863619623	5049	#define USB_CLR_SOF (~USB_ISTR_SOF) /!< clear Start Of Frame bit /
jhon309	0:ac8863619623	5050	#define USB_CLR_ESOF (~USB_ISTR_ESOF) /!< clear Expected Start Of Frame bit /
jhon309	0:ac8863619623	5051	#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /!< clear LPM L1 bit /
jhon309	0:ac8863619623	5052
jhon309	0:ac8863619623	5053	/*********************** CNTR control register bits definitions *********/
jhon309	0:ac8863619623	5054	#define USB_CNTR_CTRM ((uint16_t)0x8000) /!< Correct TRansfer Mask /
jhon309	0:ac8863619623	5055	#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /!< DMA OVeR/underrun Mask /
jhon309	0:ac8863619623	5056	#define USB_CNTR_ERRM ((uint16_t)0x2000) /!< ERRor Mask /
jhon309	0:ac8863619623	5057	#define USB_CNTR_WKUPM ((uint16_t)0x1000) /!< WaKe UP Mask /
jhon309	0:ac8863619623	5058	#define USB_CNTR_SUSPM ((uint16_t)0x0800) /!< SUSPend Mask /
jhon309	0:ac8863619623	5059	#define USB_CNTR_RESETM ((uint16_t)0x0400) /!< RESET Mask /
jhon309	0:ac8863619623	5060	#define USB_CNTR_SOFM ((uint16_t)0x0200) /!< Start Of Frame Mask /
jhon309	0:ac8863619623	5061	#define USB_CNTR_ESOFM ((uint16_t)0x0100) /!< Expected Start Of Frame Mask /
jhon309	0:ac8863619623	5062	#define USB_CNTR_L1REQM ((uint16_t)0x0080) /!< LPM L1 state request interrupt mask /
jhon309	0:ac8863619623	5063	#define USB_CNTR_L1RESUME ((uint16_t)0x0020) /!< LPM L1 Resume request /
jhon309	0:ac8863619623	5064	#define USB_CNTR_RESUME ((uint16_t)0x0010) /!< RESUME request /
jhon309	0:ac8863619623	5065	#define USB_CNTR_FSUSP ((uint16_t)0x0008) /!< Force SUSPend /
jhon309	0:ac8863619623	5066	#define USB_CNTR_LPMODE ((uint16_t)0x0004) /!< Low-power MODE /
jhon309	0:ac8863619623	5067	#define USB_CNTR_PDWN ((uint16_t)0x0002) /!< Power DoWN /
jhon309	0:ac8863619623	5068	#define USB_CNTR_FRES ((uint16_t)0x0001) /!< Force USB RESet /
jhon309	0:ac8863619623	5069
jhon309	0:ac8863619623	5070	/*********************** BCDR control register bits definitions *********/
jhon309	0:ac8863619623	5071	#define USB_BCDR_DPPU ((uint16_t)0x8000) /!< DP Pull-up Enable /
jhon309	0:ac8863619623	5072	#define USB_BCDR_PS2DET ((uint16_t)0x0080) /!< PS2 port or proprietary charger detected /
jhon309	0:ac8863619623	5073	#define USB_BCDR_SDET ((uint16_t)0x0040) /!< Secondary detection (SD) status /
jhon309	0:ac8863619623	5074	#define USB_BCDR_PDET ((uint16_t)0x0020) /!< Primary detection (PD) status /
jhon309	0:ac8863619623	5075	#define USB_BCDR_DCDET ((uint16_t)0x0010) /!< Data contact detection (DCD) status /
jhon309	0:ac8863619623	5076	#define USB_BCDR_SDEN ((uint16_t)0x0008) /!< Secondary detection (SD) mode enable /
jhon309	0:ac8863619623	5077	#define USB_BCDR_PDEN ((uint16_t)0x0004) /!< Primary detection (PD) mode enable /
jhon309	0:ac8863619623	5078	#define USB_BCDR_DCDEN ((uint16_t)0x0002) /!< Data contact detection (DCD) mode enable /
jhon309	0:ac8863619623	5079	#define USB_BCDR_BCDEN ((uint16_t)0x0001) /!< Battery charging detector (BCD) enable /
jhon309	0:ac8863619623	5080
jhon309	0:ac8863619623	5081	/************************* LPM register bits definitions ****************/
jhon309	0:ac8863619623	5082	#define USB_LPMCSR_BESL ((uint16_t)0x00F0) /!< BESL value received with last ACKed LPM Token /
jhon309	0:ac8863619623	5083	#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /!< bRemoteWake value received with last ACKed LPM Token /
jhon309	0:ac8863619623	5084	#define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /!< LPM Token acknowledge enable/
jhon309	0:ac8863619623	5085	#define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /!< LPM support enable /
jhon309	0:ac8863619623	5086
jhon309	0:ac8863619623	5087	/****************** FNR Frame Number Register bit definitions **********/
jhon309	0:ac8863619623	5088	#define USB_FNR_RXDP ((uint16_t)0x8000) /!< status of D+ data line /
jhon309	0:ac8863619623	5089	#define USB_FNR_RXDM ((uint16_t)0x4000) /!< status of D- data line /
jhon309	0:ac8863619623	5090	#define USB_FNR_LCK ((uint16_t)0x2000) /!< LoCKed /
jhon309	0:ac8863619623	5091	#define USB_FNR_LSOF ((uint16_t)0x1800) /!< Lost SOF /
jhon309	0:ac8863619623	5092	#define USB_FNR_FN ((uint16_t)0x07FF) /!< Frame Number /
jhon309	0:ac8863619623	5093
jhon309	0:ac8863619623	5094	/****************** DADDR Device ADDRess bit definitions **************/
jhon309	0:ac8863619623	5095	#define USB_DADDR_EF ((uint8_t)0x80) /!< USB device address Enable Function /
jhon309	0:ac8863619623	5096	#define USB_DADDR_ADD ((uint8_t)0x7F) /!< USB device address /
jhon309	0:ac8863619623	5097
jhon309	0:ac8863619623	5098	/**************************** Endpoint register ***********************/
jhon309	0:ac8863619623	5099	#define USB_EP0R USB_BASE /!< endpoint 0 register address /
jhon309	0:ac8863619623	5100	#define USB_EP1R (USB_BASE + 0x04) /!< endpoint 1 register address /
jhon309	0:ac8863619623	5101	#define USB_EP2R (USB_BASE + 0x08) /!< endpoint 2 register address /
jhon309	0:ac8863619623	5102	#define USB_EP3R (USB_BASE + 0x0C) /!< endpoint 3 register address /
jhon309	0:ac8863619623	5103	#define USB_EP4R (USB_BASE + 0x10) /!< endpoint 4 register address /
jhon309	0:ac8863619623	5104	#define USB_EP5R (USB_BASE + 0x14) /!< endpoint 5 register address /
jhon309	0:ac8863619623	5105	#define USB_EP6R (USB_BASE + 0x18) /!< endpoint 6 register address /
jhon309	0:ac8863619623	5106	#define USB_EP7R (USB_BASE + 0x1C) /!< endpoint 7 register address /
jhon309	0:ac8863619623	5107	/* bit positions */
jhon309	0:ac8863619623	5108	#define USB_EP_CTR_RX ((uint16_t)0x8000) /!< EndPoint Correct TRansfer RX /
jhon309	0:ac8863619623	5109	#define USB_EP_DTOG_RX ((uint16_t)0x4000) /!< EndPoint Data TOGGLE RX /
jhon309	0:ac8863619623	5110	#define USB_EPRX_STAT ((uint16_t)0x3000) /!< EndPoint RX STATus bit field /
jhon309	0:ac8863619623	5111	#define USB_EP_SETUP ((uint16_t)0x0800) /!< EndPoint SETUP /
jhon309	0:ac8863619623	5112	#define USB_EP_T_FIELD ((uint16_t)0x0600) /!< EndPoint TYPE /
jhon309	0:ac8863619623	5113	#define USB_EP_KIND ((uint16_t)0x0100) /!< EndPoint KIND /
jhon309	0:ac8863619623	5114	#define USB_EP_CTR_TX ((uint16_t)0x0080) /!< EndPoint Correct TRansfer TX /
jhon309	0:ac8863619623	5115	#define USB_EP_DTOG_TX ((uint16_t)0x0040) /!< EndPoint Data TOGGLE TX /
jhon309	0:ac8863619623	5116	#define USB_EPTX_STAT ((uint16_t)0x0030) /!< EndPoint TX STATus bit field /
jhon309	0:ac8863619623	5117	#define USB_EPADDR_FIELD ((uint16_t)0x000F) /!< EndPoint ADDRess FIELD /
jhon309	0:ac8863619623	5118
jhon309	0:ac8863619623	5119	/* EndPoint REGister MASK (no toggle fields) */
jhon309	0:ac8863619623	5120	#define USB_EPREG_MASK (USB_EP_CTR_RX\|USB_EP_SETUP\|USB_EP_T_FIELD\|USB_EP_KIND\|USB_EP_CTR_TX\|USB_EPADDR_FIELD)
jhon309	0:ac8863619623	5121	/!< EP_TYPE[1:0] EndPoint TYPE /
jhon309	0:ac8863619623	5122	#define USB_EP_TYPE_MASK ((uint16_t)0x0600) /!< EndPoint TYPE Mask /
jhon309	0:ac8863619623	5123	#define USB_EP_BULK ((uint16_t)0x0000) /!< EndPoint BULK /
jhon309	0:ac8863619623	5124	#define USB_EP_CONTROL ((uint16_t)0x0200) /!< EndPoint CONTROL /
jhon309	0:ac8863619623	5125	#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /!< EndPoint ISOCHRONOUS /
jhon309	0:ac8863619623	5126	#define USB_EP_INTERRUPT ((uint16_t)0x0600) /!< EndPoint INTERRUPT /
jhon309	0:ac8863619623	5127	#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
jhon309	0:ac8863619623	5128
jhon309	0:ac8863619623	5129	#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /!< EP_KIND EndPoint KIND /
jhon309	0:ac8863619623	5130	/!< STAT_TX[1:0] STATus for TX transfer /
jhon309	0:ac8863619623	5131	#define USB_EP_TX_DIS ((uint16_t)0x0000) /!< EndPoint TX DISabled /
jhon309	0:ac8863619623	5132	#define USB_EP_TX_STALL ((uint16_t)0x0010) /!< EndPoint TX STALLed /
jhon309	0:ac8863619623	5133	#define USB_EP_TX_NAK ((uint16_t)0x0020) /!< EndPoint TX NAKed /
jhon309	0:ac8863619623	5134	#define USB_EP_TX_VALID ((uint16_t)0x0030) /!< EndPoint TX VALID /
jhon309	0:ac8863619623	5135	#define USB_EPTX_DTOG1 ((uint16_t)0x0010) /!< EndPoint TX Data TOGgle bit1 /
jhon309	0:ac8863619623	5136	#define USB_EPTX_DTOG2 ((uint16_t)0x0020) /!< EndPoint TX Data TOGgle bit2 /
jhon309	0:ac8863619623	5137	#define USB_EPTX_DTOGMASK (USB_EPTX_STAT\|USB_EPREG_MASK)
jhon309	0:ac8863619623	5138	/!< STAT_RX[1:0] STATus for RX transfer /
jhon309	0:ac8863619623	5139	#define USB_EP_RX_DIS ((uint16_t)0x0000) /!< EndPoint RX DISabled /
jhon309	0:ac8863619623	5140	#define USB_EP_RX_STALL ((uint16_t)0x1000) /!< EndPoint RX STALLed /
jhon309	0:ac8863619623	5141	#define USB_EP_RX_NAK ((uint16_t)0x2000) /!< EndPoint RX NAKed /
jhon309	0:ac8863619623	5142	#define USB_EP_RX_VALID ((uint16_t)0x3000) /!< EndPoint RX VALID /
jhon309	0:ac8863619623	5143	#define USB_EPRX_DTOG1 ((uint16_t)0x1000) /!< EndPoint RX Data TOGgle bit1 /
jhon309	0:ac8863619623	5144	#define USB_EPRX_DTOG2 ((uint16_t)0x2000) /!< EndPoint RX Data TOGgle bit1 /
jhon309	0:ac8863619623	5145	#define USB_EPRX_DTOGMASK (USB_EPRX_STAT\|USB_EPREG_MASK)
jhon309	0:ac8863619623	5146
jhon309	0:ac8863619623	5147	/******************************************************************************/
jhon309	0:ac8863619623	5148	/* */
jhon309	0:ac8863619623	5149	/* Window WATCHDOG (WWDG) */
jhon309	0:ac8863619623	5150	/* */
jhon309	0:ac8863619623	5151	/******************************************************************************/
jhon309	0:ac8863619623	5152	/***************** Bit definition for WWDG_CR register ******************/
jhon309	0:ac8863619623	5153	#define WWDG_CR_T ((uint32_t)0x7F) /!<T[6:0] bits (7-Bit counter (MSB to LSB)) /
jhon309	0:ac8863619623	5154	#define WWDG_CR_T0 ((uint32_t)0x01) /!<Bit 0 /
jhon309	0:ac8863619623	5155	#define WWDG_CR_T1 ((uint32_t)0x02) /!<Bit 1 /
jhon309	0:ac8863619623	5156	#define WWDG_CR_T2 ((uint32_t)0x04) /!<Bit 2 /
jhon309	0:ac8863619623	5157	#define WWDG_CR_T3 ((uint32_t)0x08) /!<Bit 3 /
jhon309	0:ac8863619623	5158	#define WWDG_CR_T4 ((uint32_t)0x10) /!<Bit 4 /
jhon309	0:ac8863619623	5159	#define WWDG_CR_T5 ((uint32_t)0x20) /!<Bit 5 /
jhon309	0:ac8863619623	5160	#define WWDG_CR_T6 ((uint32_t)0x40) /!<Bit 6 /
jhon309	0:ac8863619623	5161
jhon309	0:ac8863619623	5162	#define WWDG_CR_WDGA ((uint32_t)0x80) /!<Activation bit /
jhon309	0:ac8863619623	5163
jhon309	0:ac8863619623	5164	/***************** Bit definition for WWDG_CFR register *****************/
jhon309	0:ac8863619623	5165	#define WWDG_CFR_W ((uint32_t)0x007F) /!<W[6:0] bits (7-bit window value) /
jhon309	0:ac8863619623	5166	#define WWDG_CFR_W0 ((uint32_t)0x0001) /!<Bit 0 /
jhon309	0:ac8863619623	5167	#define WWDG_CFR_W1 ((uint32_t)0x0002) /!<Bit 1 /
jhon309	0:ac8863619623	5168	#define WWDG_CFR_W2 ((uint32_t)0x0004) /!<Bit 2 /
jhon309	0:ac8863619623	5169	#define WWDG_CFR_W3 ((uint32_t)0x0008) /!<Bit 3 /
jhon309	0:ac8863619623	5170	#define WWDG_CFR_W4 ((uint32_t)0x0010) /!<Bit 4 /
jhon309	0:ac8863619623	5171	#define WWDG_CFR_W5 ((uint32_t)0x0020) /!<Bit 5 /
jhon309	0:ac8863619623	5172	#define WWDG_CFR_W6 ((uint32_t)0x0040) /!<Bit 6 /
jhon309	0:ac8863619623	5173
jhon309	0:ac8863619623	5174	#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /!<WDGTB[1:0] bits (Timer Base) /
jhon309	0:ac8863619623	5175	#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /!<Bit 0 /
jhon309	0:ac8863619623	5176	#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /!<Bit 1 /
jhon309	0:ac8863619623	5177
jhon309	0:ac8863619623	5178	#define WWDG_CFR_EWI ((uint32_t)0x0200) /!<Early Wakeup Interrupt /
jhon309	0:ac8863619623	5179
jhon309	0:ac8863619623	5180	/***************** Bit definition for WWDG_SR register ******************/
jhon309	0:ac8863619623	5181	#define WWDG_SR_EWIF ((uint32_t)0x01) /!<Early Wakeup Interrupt Flag /
jhon309	0:ac8863619623	5182
jhon309	0:ac8863619623	5183	/**
jhon309	0:ac8863619623	5184	* @}
jhon309	0:ac8863619623	5185	*/
jhon309	0:ac8863619623	5186
jhon309	0:ac8863619623	5187	/**
jhon309	0:ac8863619623	5188	* @}
jhon309	0:ac8863619623	5189	*/
jhon309	0:ac8863619623	5190
jhon309	0:ac8863619623	5191
jhon309	0:ac8863619623	5192	/** @addtogroup Exported_macro
jhon309	0:ac8863619623	5193	* @{
jhon309	0:ac8863619623	5194	*/
jhon309	0:ac8863619623	5195
jhon309	0:ac8863619623	5196	/**************************** ADC Instances *******************************/
jhon309	0:ac8863619623	5197	#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
jhon309	0:ac8863619623	5198
jhon309	0:ac8863619623	5199	#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
jhon309	0:ac8863619623	5200
jhon309	0:ac8863619623	5201	/***************************** CAN Instances ******************************/
jhon309	0:ac8863619623	5202	#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
jhon309	0:ac8863619623	5203
jhon309	0:ac8863619623	5204	/**************************** COMP Instances *******************************/
jhon309	0:ac8863619623	5205	#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) \|\| \
jhon309	0:ac8863619623	5206	((INSTANCE) == COMP2))
jhon309	0:ac8863619623	5207
jhon309	0:ac8863619623	5208	#define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
jhon309	0:ac8863619623	5209
jhon309	0:ac8863619623	5210	#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
jhon309	0:ac8863619623	5211
jhon309	0:ac8863619623	5212	/**************************** CEC Instances *******************************/
jhon309	0:ac8863619623	5213	#define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
jhon309	0:ac8863619623	5214
jhon309	0:ac8863619623	5215	/**************************** CRC Instances *******************************/
jhon309	0:ac8863619623	5216	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
jhon309	0:ac8863619623	5217
jhon309	0:ac8863619623	5218	/***************************** DAC Instances ******************************/
jhon309	0:ac8863619623	5219	#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
jhon309	0:ac8863619623	5220
jhon309	0:ac8863619623	5221	/***************************** DMA Instances ****************************/
jhon309	0:ac8863619623	5222	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
jhon309	0:ac8863619623	5223	((INSTANCE) == DMA1_Channel2) \|\| \
jhon309	0:ac8863619623	5224	((INSTANCE) == DMA1_Channel3) \|\| \
jhon309	0:ac8863619623	5225	((INSTANCE) == DMA1_Channel4) \|\| \
jhon309	0:ac8863619623	5226	((INSTANCE) == DMA1_Channel5) \|\| \
jhon309	0:ac8863619623	5227	((INSTANCE) == DMA1_Channel6) \|\| \
jhon309	0:ac8863619623	5228	((INSTANCE) == DMA1_Channel7))
jhon309	0:ac8863619623	5229
jhon309	0:ac8863619623	5230	/**************************** GPIO Instances ******************************/
jhon309	0:ac8863619623	5231	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
jhon309	0:ac8863619623	5232	((INSTANCE) == GPIOB) \|\| \
jhon309	0:ac8863619623	5233	((INSTANCE) == GPIOC) \|\| \
jhon309	0:ac8863619623	5234	((INSTANCE) == GPIOD) \|\| \
jhon309	0:ac8863619623	5235	((INSTANCE) == GPIOE) \|\| \
jhon309	0:ac8863619623	5236	((INSTANCE) == GPIOF))
jhon309	0:ac8863619623	5237
jhon309	0:ac8863619623	5238	#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
jhon309	0:ac8863619623	5239	((INSTANCE) == GPIOB) \|\| \
jhon309	0:ac8863619623	5240	((INSTANCE) == GPIOC) \|\| \
jhon309	0:ac8863619623	5241	((INSTANCE) == GPIOD) \|\| \
jhon309	0:ac8863619623	5242	((INSTANCE) == GPIOE))
jhon309	0:ac8863619623	5243
jhon309	0:ac8863619623	5244	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
jhon309	0:ac8863619623	5245	((INSTANCE) == GPIOB))
jhon309	0:ac8863619623	5246
jhon309	0:ac8863619623	5247	/**************************** I2C Instances *******************************/
jhon309	0:ac8863619623	5248	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
jhon309	0:ac8863619623	5249	((INSTANCE) == I2C2))
jhon309	0:ac8863619623	5250
jhon309	0:ac8863619623	5251	/**************************** I2S Instances *******************************/
jhon309	0:ac8863619623	5252	#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
jhon309	0:ac8863619623	5253	((INSTANCE) == SPI2))
jhon309	0:ac8863619623	5254
jhon309	0:ac8863619623	5255	/**************************** IWDG Instances ******************************/
jhon309	0:ac8863619623	5256	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
jhon309	0:ac8863619623	5257
jhon309	0:ac8863619623	5258	/**************************** RTC Instances *******************************/
jhon309	0:ac8863619623	5259	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
jhon309	0:ac8863619623	5260
jhon309	0:ac8863619623	5261	/**************************** SMBUS Instances *******************************/
jhon309	0:ac8863619623	5262	#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
jhon309	0:ac8863619623	5263
jhon309	0:ac8863619623	5264	/**************************** SPI Instances *******************************/
jhon309	0:ac8863619623	5265	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
jhon309	0:ac8863619623	5266	((INSTANCE) == SPI2))
jhon309	0:ac8863619623	5267
jhon309	0:ac8863619623	5268	/**************************** TIM Instances *******************************/
jhon309	0:ac8863619623	5269	#define IS_TIM_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5270	(((INSTANCE) == TIM1) \|\| \
jhon309	0:ac8863619623	5271	((INSTANCE) == TIM2) \|\| \
jhon309	0:ac8863619623	5272	((INSTANCE) == TIM3) \|\| \
jhon309	0:ac8863619623	5273	((INSTANCE) == TIM6) \|\| \
jhon309	0:ac8863619623	5274	((INSTANCE) == TIM7) \|\| \
jhon309	0:ac8863619623	5275	((INSTANCE) == TIM14) \|\| \
jhon309	0:ac8863619623	5276	((INSTANCE) == TIM15) \|\| \
jhon309	0:ac8863619623	5277	((INSTANCE) == TIM16) \|\| \
jhon309	0:ac8863619623	5278	((INSTANCE) == TIM17))
jhon309	0:ac8863619623	5279
jhon309	0:ac8863619623	5280	#define IS_TIM_CC1_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5281	(((INSTANCE) == TIM1) \|\| \
jhon309	0:ac8863619623	5282	((INSTANCE) == TIM2) \|\| \
jhon309	0:ac8863619623	5283	((INSTANCE) == TIM3) \|\| \
jhon309	0:ac8863619623	5284	((INSTANCE) == TIM14) \|\| \
jhon309	0:ac8863619623	5285	((INSTANCE) == TIM15) \|\| \
jhon309	0:ac8863619623	5286	((INSTANCE) == TIM16) \|\| \
jhon309	0:ac8863619623	5287	((INSTANCE) == TIM17))
jhon309	0:ac8863619623	5288
jhon309	0:ac8863619623	5289	#define IS_TIM_CC2_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5290	(((INSTANCE) == TIM1) \|\| \
jhon309	0:ac8863619623	5291	((INSTANCE) == TIM2) \|\| \
jhon309	0:ac8863619623	5292	((INSTANCE) == TIM3) \|\| \
jhon309	0:ac8863619623	5293	((INSTANCE) == TIM15))
jhon309	0:ac8863619623	5294
jhon309	0:ac8863619623	5295	#define IS_TIM_CC3_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5296	(((INSTANCE) == TIM1) \|\| \
jhon309	0:ac8863619623	5297	((INSTANCE) == TIM2) \|\| \
jhon309	0:ac8863619623	5298	((INSTANCE) == TIM3))
jhon309	0:ac8863619623	5299
jhon309	0:ac8863619623	5300	#define IS_TIM_CC4_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5301	(((INSTANCE) == TIM1) \|\| \
jhon309	0:ac8863619623	5302	((INSTANCE) == TIM2) \|\| \
jhon309	0:ac8863619623	5303	((INSTANCE) == TIM3))
jhon309	0:ac8863619623	5304
jhon309	0:ac8863619623	5305	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5306	(((INSTANCE) == TIM1) \|\| \
jhon309	0:ac8863619623	5307	((INSTANCE) == TIM2) \|\| \
jhon309	0:ac8863619623	5308	((INSTANCE) == TIM3))
jhon309	0:ac8863619623	5309
jhon309	0:ac8863619623	5310	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5311	(((INSTANCE) == TIM1) \|\| \
jhon309	0:ac8863619623	5312	((INSTANCE) == TIM2) \|\| \
jhon309	0:ac8863619623	5313	((INSTANCE) == TIM3))
jhon309	0:ac8863619623	5314
jhon309	0:ac8863619623	5315	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5316	(((INSTANCE) == TIM1) \|\| \
jhon309	0:ac8863619623	5317	((INSTANCE) == TIM2) \|\| \
jhon309	0:ac8863619623	5318	((INSTANCE) == TIM3) \|\| \
jhon309	0:ac8863619623	5319	((INSTANCE) == TIM15))
jhon309	0:ac8863619623	5320
jhon309	0:ac8863619623	5321	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5322	(((INSTANCE) == TIM1) \|\| \
jhon309	0:ac8863619623	5323	((INSTANCE) == TIM2) \|\| \
jhon309	0:ac8863619623	5324	((INSTANCE) == TIM3) \|\| \
jhon309	0:ac8863619623	5325	((INSTANCE) == TIM15))
jhon309	0:ac8863619623	5326
jhon309	0:ac8863619623	5327	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5328	(((INSTANCE) == TIM1) \|\| \
jhon309	0:ac8863619623	5329	((INSTANCE) == TIM2) \|\| \
jhon309	0:ac8863619623	5330	((INSTANCE) == TIM3))
jhon309	0:ac8863619623	5331
jhon309	0:ac8863619623	5332	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5333	(((INSTANCE) == TIM1) \|\| \
jhon309	0:ac8863619623	5334	((INSTANCE) == TIM2) \|\| \
jhon309	0:ac8863619623	5335	((INSTANCE) == TIM3))
jhon309	0:ac8863619623	5336
jhon309	0:ac8863619623	5337	#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5338	(((INSTANCE) == TIM1))
jhon309	0:ac8863619623	5339
jhon309	0:ac8863619623	5340	#define IS_TIM_XOR_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5341	(((INSTANCE) == TIM1) \|\| \
jhon309	0:ac8863619623	5342	((INSTANCE) == TIM2) \|\| \
jhon309	0:ac8863619623	5343	((INSTANCE) == TIM3))
jhon309	0:ac8863619623	5344
jhon309	0:ac8863619623	5345	#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5346	(((INSTANCE) == TIM1) \|\| \
jhon309	0:ac8863619623	5347	((INSTANCE) == TIM2) \|\| \
jhon309	0:ac8863619623	5348	((INSTANCE) == TIM3) \|\| \
jhon309	0:ac8863619623	5349	((INSTANCE) == TIM6) \|\| \
jhon309	0:ac8863619623	5350	((INSTANCE) == TIM7) \|\| \
jhon309	0:ac8863619623	5351	((INSTANCE) == TIM15))
jhon309	0:ac8863619623	5352
jhon309	0:ac8863619623	5353	#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5354	(((INSTANCE) == TIM1) \|\| \
jhon309	0:ac8863619623	5355	((INSTANCE) == TIM2) \|\| \
jhon309	0:ac8863619623	5356	((INSTANCE) == TIM3) \|\| \
jhon309	0:ac8863619623	5357	((INSTANCE) == TIM15))
jhon309	0:ac8863619623	5358
jhon309	0:ac8863619623	5359	#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5360	((INSTANCE) == TIM2)
jhon309	0:ac8863619623	5361
jhon309	0:ac8863619623	5362	#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5363	(((INSTANCE) == TIM1) \|\| \
jhon309	0:ac8863619623	5364	((INSTANCE) == TIM2) \|\| \
jhon309	0:ac8863619623	5365	((INSTANCE) == TIM3) \|\| \
jhon309	0:ac8863619623	5366	((INSTANCE) == TIM15) \|\| \
jhon309	0:ac8863619623	5367	((INSTANCE) == TIM16) \|\| \
jhon309	0:ac8863619623	5368	((INSTANCE) == TIM17))
jhon309	0:ac8863619623	5369
jhon309	0:ac8863619623	5370	#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5371	(((INSTANCE) == TIM1) \|\| \
jhon309	0:ac8863619623	5372	((INSTANCE) == TIM15) \|\| \
jhon309	0:ac8863619623	5373	((INSTANCE) == TIM16) \|\| \
jhon309	0:ac8863619623	5374	((INSTANCE) == TIM17))
jhon309	0:ac8863619623	5375
jhon309	0:ac8863619623	5376	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
jhon309	0:ac8863619623	5377	((((INSTANCE) == TIM1) && \
jhon309	0:ac8863619623	5378	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
jhon309	0:ac8863619623	5379	((CHANNEL) == TIM_CHANNEL_2) \|\| \
jhon309	0:ac8863619623	5380	((CHANNEL) == TIM_CHANNEL_3) \|\| \
jhon309	0:ac8863619623	5381	((CHANNEL) == TIM_CHANNEL_4))) \
jhon309	0:ac8863619623	5382	\|\| \
jhon309	0:ac8863619623	5383	(((INSTANCE) == TIM2) && \
jhon309	0:ac8863619623	5384	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
jhon309	0:ac8863619623	5385	((CHANNEL) == TIM_CHANNEL_2) \|\| \
jhon309	0:ac8863619623	5386	((CHANNEL) == TIM_CHANNEL_3) \|\| \
jhon309	0:ac8863619623	5387	((CHANNEL) == TIM_CHANNEL_4))) \
jhon309	0:ac8863619623	5388	\|\| \
jhon309	0:ac8863619623	5389	(((INSTANCE) == TIM3) && \
jhon309	0:ac8863619623	5390	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
jhon309	0:ac8863619623	5391	((CHANNEL) == TIM_CHANNEL_2) \|\| \
jhon309	0:ac8863619623	5392	((CHANNEL) == TIM_CHANNEL_3) \|\| \
jhon309	0:ac8863619623	5393	((CHANNEL) == TIM_CHANNEL_4))) \
jhon309	0:ac8863619623	5394	\|\| \
jhon309	0:ac8863619623	5395	(((INSTANCE) == TIM14) && \
jhon309	0:ac8863619623	5396	(((CHANNEL) == TIM_CHANNEL_1))) \
jhon309	0:ac8863619623	5397	\|\| \
jhon309	0:ac8863619623	5398	(((INSTANCE) == TIM15) && \
jhon309	0:ac8863619623	5399	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
jhon309	0:ac8863619623	5400	((CHANNEL) == TIM_CHANNEL_2))) \
jhon309	0:ac8863619623	5401	\|\| \
jhon309	0:ac8863619623	5402	(((INSTANCE) == TIM16) && \
jhon309	0:ac8863619623	5403	(((CHANNEL) == TIM_CHANNEL_1))) \
jhon309	0:ac8863619623	5404	\|\| \
jhon309	0:ac8863619623	5405	(((INSTANCE) == TIM17) && \
jhon309	0:ac8863619623	5406	(((CHANNEL) == TIM_CHANNEL_1))))
jhon309	0:ac8863619623	5407
jhon309	0:ac8863619623	5408	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
jhon309	0:ac8863619623	5409	((((INSTANCE) == TIM1) && \
jhon309	0:ac8863619623	5410	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
jhon309	0:ac8863619623	5411	((CHANNEL) == TIM_CHANNEL_2) \|\| \
jhon309	0:ac8863619623	5412	((CHANNEL) == TIM_CHANNEL_3))) \
jhon309	0:ac8863619623	5413	\|\| \
jhon309	0:ac8863619623	5414	(((INSTANCE) == TIM15) && \
jhon309	0:ac8863619623	5415	((CHANNEL) == TIM_CHANNEL_1)) \
jhon309	0:ac8863619623	5416	\|\| \
jhon309	0:ac8863619623	5417	(((INSTANCE) == TIM16) && \
jhon309	0:ac8863619623	5418	((CHANNEL) == TIM_CHANNEL_1)) \
jhon309	0:ac8863619623	5419	\|\| \
jhon309	0:ac8863619623	5420	(((INSTANCE) == TIM17) && \
jhon309	0:ac8863619623	5421	((CHANNEL) == TIM_CHANNEL_1)))
jhon309	0:ac8863619623	5422
jhon309	0:ac8863619623	5423	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5424	(((INSTANCE) == TIM1) \|\| \
jhon309	0:ac8863619623	5425	((INSTANCE) == TIM2) \|\| \
jhon309	0:ac8863619623	5426	((INSTANCE) == TIM3))
jhon309	0:ac8863619623	5427
jhon309	0:ac8863619623	5428	#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5429	(((INSTANCE) == TIM1) \|\| \
jhon309	0:ac8863619623	5430	((INSTANCE) == TIM15) \|\| \
jhon309	0:ac8863619623	5431	((INSTANCE) == TIM16) \|\| \
jhon309	0:ac8863619623	5432	((INSTANCE) == TIM17))
jhon309	0:ac8863619623	5433
jhon309	0:ac8863619623	5434	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5435	(((INSTANCE) == TIM1) \|\| \
jhon309	0:ac8863619623	5436	((INSTANCE) == TIM2) \|\| \
jhon309	0:ac8863619623	5437	((INSTANCE) == TIM3) \|\| \
jhon309	0:ac8863619623	5438	((INSTANCE) == TIM14) \|\| \
jhon309	0:ac8863619623	5439	((INSTANCE) == TIM15) \|\| \
jhon309	0:ac8863619623	5440	((INSTANCE) == TIM16) \|\| \
jhon309	0:ac8863619623	5441	((INSTANCE) == TIM17))
jhon309	0:ac8863619623	5442
jhon309	0:ac8863619623	5443	#define IS_TIM_DMA_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5444	(((INSTANCE) == TIM1) \|\| \
jhon309	0:ac8863619623	5445	((INSTANCE) == TIM2) \|\| \
jhon309	0:ac8863619623	5446	((INSTANCE) == TIM3) \|\| \
jhon309	0:ac8863619623	5447	((INSTANCE) == TIM6) \|\| \
jhon309	0:ac8863619623	5448	((INSTANCE) == TIM7) \|\| \
jhon309	0:ac8863619623	5449	((INSTANCE) == TIM15) \|\| \
jhon309	0:ac8863619623	5450	((INSTANCE) == TIM16) \|\| \
jhon309	0:ac8863619623	5451	((INSTANCE) == TIM17))
jhon309	0:ac8863619623	5452
jhon309	0:ac8863619623	5453	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5454	(((INSTANCE) == TIM1) \|\| \
jhon309	0:ac8863619623	5455	((INSTANCE) == TIM2) \|\| \
jhon309	0:ac8863619623	5456	((INSTANCE) == TIM3) \|\| \
jhon309	0:ac8863619623	5457	((INSTANCE) == TIM15) \|\| \
jhon309	0:ac8863619623	5458	((INSTANCE) == TIM16) \|\| \
jhon309	0:ac8863619623	5459	((INSTANCE) == TIM17))
jhon309	0:ac8863619623	5460
jhon309	0:ac8863619623	5461	#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5462	(((INSTANCE) == TIM1) \|\| \
jhon309	0:ac8863619623	5463	((INSTANCE) == TIM15) \|\| \
jhon309	0:ac8863619623	5464	((INSTANCE) == TIM16) \|\| \
jhon309	0:ac8863619623	5465	((INSTANCE) == TIM17))
jhon309	0:ac8863619623	5466
jhon309	0:ac8863619623	5467	#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
jhon309	0:ac8863619623	5468	((INSTANCE) == TIM14)
jhon309	0:ac8863619623	5469
jhon309	0:ac8863619623	5470	/**************************** TSC Instances *******************************/
jhon309	0:ac8863619623	5471	#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
jhon309	0:ac8863619623	5472
jhon309	0:ac8863619623	5473	/********************* UART Instances : IRDA mode *************************/
jhon309	0:ac8863619623	5474	#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
jhon309	0:ac8863619623	5475	((INSTANCE) == USART2))
jhon309	0:ac8863619623	5476
jhon309	0:ac8863619623	5477	/******************* UART Instances : Smard card mode *********************/
jhon309	0:ac8863619623	5478	#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
jhon309	0:ac8863619623	5479	((INSTANCE) == USART2))
jhon309	0:ac8863619623	5480
jhon309	0:ac8863619623	5481	/****************** USART Instances : Synchronous mode ********************/
jhon309	0:ac8863619623	5482	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
jhon309	0:ac8863619623	5483	((INSTANCE) == USART2) \|\| \
jhon309	0:ac8863619623	5484	((INSTANCE) == USART3) \|\| \
jhon309	0:ac8863619623	5485	((INSTANCE) == USART4))
jhon309	0:ac8863619623	5486
jhon309	0:ac8863619623	5487	/****************** USART Instances : auto Baud rate detection ************/
jhon309	0:ac8863619623	5488	#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
jhon309	0:ac8863619623	5489	((INSTANCE) == USART2))
jhon309	0:ac8863619623	5490
jhon309	0:ac8863619623	5491	/****************** UART Instances : Asynchronous mode ********************/
jhon309	0:ac8863619623	5492	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
jhon309	0:ac8863619623	5493	((INSTANCE) == USART2) \|\| \
jhon309	0:ac8863619623	5494	((INSTANCE) == USART3) \|\| \
jhon309	0:ac8863619623	5495	((INSTANCE) == USART4))
jhon309	0:ac8863619623	5496
jhon309	0:ac8863619623	5497	/****************** UART Instances : Half-Duplex mode ********************/
jhon309	0:ac8863619623	5498	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
jhon309	0:ac8863619623	5499	((INSTANCE) == USART2) \|\| \
jhon309	0:ac8863619623	5500	((INSTANCE) == USART3) \|\| \
jhon309	0:ac8863619623	5501	((INSTANCE) == USART4))
jhon309	0:ac8863619623	5502
jhon309	0:ac8863619623	5503	/**************** UART Instances : Hardware Flow control ******************/
jhon309	0:ac8863619623	5504	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
jhon309	0:ac8863619623	5505	((INSTANCE) == USART2) \|\| \
jhon309	0:ac8863619623	5506	((INSTANCE) == USART3) \|\| \
jhon309	0:ac8863619623	5507	((INSTANCE) == USART4))
jhon309	0:ac8863619623	5508
jhon309	0:ac8863619623	5509	/**************** UART Instances : LIN mode ******************/
jhon309	0:ac8863619623	5510	#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
jhon309	0:ac8863619623	5511	((INSTANCE) == USART2))
jhon309	0:ac8863619623	5512
jhon309	0:ac8863619623	5513	/**************** UART Instances : wakeup from stop mode ******************/
jhon309	0:ac8863619623	5514	#define IS_UART_WAKEUP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
jhon309	0:ac8863619623	5515	((INSTANCE) == USART2))
jhon309	0:ac8863619623	5516
jhon309	0:ac8863619623	5517	/**************** UART Instances : Auto Baud Rate detection ******************/
jhon309	0:ac8863619623	5518	#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
jhon309	0:ac8863619623	5519	((INSTANCE) == USART2))
jhon309	0:ac8863619623	5520
jhon309	0:ac8863619623	5521	/**************** UART Instances : Driver enable detection ******************/
jhon309	0:ac8863619623	5522	#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
jhon309	0:ac8863619623	5523	((INSTANCE) == USART2) \|\| \
jhon309	0:ac8863619623	5524	((INSTANCE) == USART3) \|\| \
jhon309	0:ac8863619623	5525	((INSTANCE) == USART4))
jhon309	0:ac8863619623	5526
jhon309	0:ac8863619623	5527	/**************************** USB Instances ******************************/
jhon309	0:ac8863619623	5528	#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
jhon309	0:ac8863619623	5529
jhon309	0:ac8863619623	5530	/**************************** WWDG Instances ******************************/
jhon309	0:ac8863619623	5531	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
jhon309	0:ac8863619623	5532
jhon309	0:ac8863619623	5533	/**
jhon309	0:ac8863619623	5534	* @}
jhon309	0:ac8863619623	5535	*/
jhon309	0:ac8863619623	5536
jhon309	0:ac8863619623	5537
jhon309	0:ac8863619623	5538	/******************************************************************************/
jhon309	0:ac8863619623	5539	/* For a painless codes migration between the STM32F0xx device product */
jhon309	0:ac8863619623	5540	/* lines, the aliases defined below are put in place to overcome the */
jhon309	0:ac8863619623	5541	/* differences in the interrupt handlers and IRQn definitions. */
jhon309	0:ac8863619623	5542	/* No need to update developed interrupt code when moving across */
jhon309	0:ac8863619623	5543	/* product lines within the same STM32F0 Family */
jhon309	0:ac8863619623	5544	/******************************************************************************/
jhon309	0:ac8863619623	5545
jhon309	0:ac8863619623	5546	/* Aliases for __IRQn */
jhon309	0:ac8863619623	5547	#define PVD_IRQn PVD_VDDIO2_IRQn
jhon309	0:ac8863619623	5548	#define VDDIO2_IRQn PVD_VDDIO2_IRQn
jhon309	0:ac8863619623	5549	#define RCC_IRQn RCC_CRS_IRQn
jhon309	0:ac8863619623	5550	#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
jhon309	0:ac8863619623	5551	#define ADC1_IRQn ADC1_COMP_IRQn
jhon309	0:ac8863619623	5552	#define TIM6_IRQn TIM6_DAC_IRQn
jhon309	0:ac8863619623	5553
jhon309	0:ac8863619623	5554	/* Aliases for __IRQHandler */
jhon309	0:ac8863619623	5555	#define PVD_IRQHandler PVD_VDDIO2_IRQHandler
jhon309	0:ac8863619623	5556	#define VDDIO2_IRQHandler PVD_VDDIO2_IRQHandler
jhon309	0:ac8863619623	5557	#define RCC_IRQHandler RCC_CRS_IRQHandler
jhon309	0:ac8863619623	5558	#define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
jhon309	0:ac8863619623	5559	#define ADC1_IRQHandler ADC1_COMP_IRQHandler
jhon309	0:ac8863619623	5560	#define TIM6_IRQHandler TIM6_DAC_IRQHandler
jhon309	0:ac8863619623	5561
jhon309	0:ac8863619623	5562	#ifdef __cplusplus
jhon309	0:ac8863619623	5563	}
jhon309	0:ac8863619623	5564	#endif /* __cplusplus */
jhon309	0:ac8863619623	5565
jhon309	0:ac8863619623	5566	#endif /* __STM32F072xB_H */
jhon309	0:ac8863619623	5567
jhon309	0:ac8863619623	5568	/**
jhon309	0:ac8863619623	5569	* @}
jhon309	0:ac8863619623	5570	*/
jhon309	0:ac8863619623	5571
jhon309	0:ac8863619623	5572	/**
jhon309	0:ac8863619623	5573	* @}
jhon309	0:ac8863619623	5574	*/
jhon309	0:ac8863619623	5575
jhon309	0:ac8863619623	5576	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	13 Aug 2015
Imports:	61
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	2

TARGET_NUCLEO_F072RB/stm32f072xb.h@0:ac8863619623, 2015-08-13 (annotated)

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