Jhon Plantikow / I2C_EEPROM

I2C_EEPROM

TARGET_NUCLEO_F072RB/core_cm7.h@0:ac8863619623, 2015-08-13 (annotated)

Committer:
jhon309
Date:
Thu Aug 13 00:23:16 2015 +0000
Revision:
0:ac8863619623
I2C

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jhon309 0:ac8863619623 1 /**************************************************************************//**
jhon309 0:ac8863619623 2 * @file core_cm7.h
jhon309 0:ac8863619623 3 * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
jhon309 0:ac8863619623 4 * @version V4.10
jhon309 0:ac8863619623 5 * @date 18. March 2015
jhon309 0:ac8863619623 6 *
jhon309 0:ac8863619623 7 * @note
jhon309 0:ac8863619623 8 *
jhon309 0:ac8863619623 9 ******************************************************************************/
jhon309 0:ac8863619623 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
jhon309 0:ac8863619623 11
jhon309 0:ac8863619623 12 All rights reserved.
jhon309 0:ac8863619623 13 Redistribution and use in source and binary forms, with or without
jhon309 0:ac8863619623 14 modification, are permitted provided that the following conditions are met:
jhon309 0:ac8863619623 15 - Redistributions of source code must retain the above copyright
jhon309 0:ac8863619623 16 notice, this list of conditions and the following disclaimer.
jhon309 0:ac8863619623 17 - Redistributions in binary form must reproduce the above copyright
jhon309 0:ac8863619623 18 notice, this list of conditions and the following disclaimer in the
jhon309 0:ac8863619623 19 documentation and/or other materials provided with the distribution.
jhon309 0:ac8863619623 20 - Neither the name of ARM nor the names of its contributors may be used
jhon309 0:ac8863619623 21 to endorse or promote products derived from this software without
jhon309 0:ac8863619623 22 specific prior written permission.
jhon309 0:ac8863619623 23 *
jhon309 0:ac8863619623 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jhon309 0:ac8863619623 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jhon309 0:ac8863619623 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
jhon309 0:ac8863619623 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
jhon309 0:ac8863619623 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
jhon309 0:ac8863619623 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
jhon309 0:ac8863619623 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
jhon309 0:ac8863619623 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
jhon309 0:ac8863619623 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
jhon309 0:ac8863619623 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
jhon309 0:ac8863619623 34 POSSIBILITY OF SUCH DAMAGE.
jhon309 0:ac8863619623 35 ---------------------------------------------------------------------------*/
jhon309 0:ac8863619623 36
jhon309 0:ac8863619623 37
jhon309 0:ac8863619623 38 #if defined ( __ICCARM__ )
jhon309 0:ac8863619623 39 #pragma system_include /* treat file as system include file for MISRA check */
jhon309 0:ac8863619623 40 #endif
jhon309 0:ac8863619623 41
jhon309 0:ac8863619623 42 #ifndef __CORE_CM7_H_GENERIC
jhon309 0:ac8863619623 43 #define __CORE_CM7_H_GENERIC
jhon309 0:ac8863619623 44
jhon309 0:ac8863619623 45 #ifdef __cplusplus
jhon309 0:ac8863619623 46 extern "C" {
jhon309 0:ac8863619623 47 #endif
jhon309 0:ac8863619623 48
jhon309 0:ac8863619623 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
jhon309 0:ac8863619623 50 CMSIS violates the following MISRA-C:2004 rules:
jhon309 0:ac8863619623 51
jhon309 0:ac8863619623 52 \li Required Rule 8.5, object/function definition in header file.<br>
jhon309 0:ac8863619623 53 Function definitions in header files are used to allow 'inlining'.
jhon309 0:ac8863619623 54
jhon309 0:ac8863619623 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
jhon309 0:ac8863619623 56 Unions are used for effective representation of core registers.
jhon309 0:ac8863619623 57
jhon309 0:ac8863619623 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
jhon309 0:ac8863619623 59 Function-like macros are used to allow more efficient code.
jhon309 0:ac8863619623 60 */
jhon309 0:ac8863619623 61
jhon309 0:ac8863619623 62
jhon309 0:ac8863619623 63 /*******************************************************************************
jhon309 0:ac8863619623 64 * CMSIS definitions
jhon309 0:ac8863619623 65 ******************************************************************************/
jhon309 0:ac8863619623 66 /** \ingroup Cortex_M7
jhon309 0:ac8863619623 67 @{
jhon309 0:ac8863619623 68 */
jhon309 0:ac8863619623 69
jhon309 0:ac8863619623 70 /* CMSIS CM7 definitions */
jhon309 0:ac8863619623 71 #define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
jhon309 0:ac8863619623 72 #define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
jhon309 0:ac8863619623 73 #define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \
jhon309 0:ac8863619623 74 __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
jhon309 0:ac8863619623 75
jhon309 0:ac8863619623 76 #define __CORTEX_M (0x07) /*!< Cortex-M Core */
jhon309 0:ac8863619623 77
jhon309 0:ac8863619623 78
jhon309 0:ac8863619623 79 #if defined ( __CC_ARM )
jhon309 0:ac8863619623 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
jhon309 0:ac8863619623 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
jhon309 0:ac8863619623 82 #define __STATIC_INLINE static __inline
jhon309 0:ac8863619623 83
jhon309 0:ac8863619623 84 #elif defined ( __GNUC__ )
jhon309 0:ac8863619623 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
jhon309 0:ac8863619623 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
jhon309 0:ac8863619623 87 #define __STATIC_INLINE static inline
jhon309 0:ac8863619623 88
jhon309 0:ac8863619623 89 #elif defined ( __ICCARM__ )
jhon309 0:ac8863619623 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
jhon309 0:ac8863619623 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
jhon309 0:ac8863619623 92 #define __STATIC_INLINE static inline
jhon309 0:ac8863619623 93
jhon309 0:ac8863619623 94 #elif defined ( __TMS470__ )
jhon309 0:ac8863619623 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
jhon309 0:ac8863619623 96 #define __STATIC_INLINE static inline
jhon309 0:ac8863619623 97
jhon309 0:ac8863619623 98 #elif defined ( __TASKING__ )
jhon309 0:ac8863619623 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
jhon309 0:ac8863619623 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
jhon309 0:ac8863619623 101 #define __STATIC_INLINE static inline
jhon309 0:ac8863619623 102
jhon309 0:ac8863619623 103 #elif defined ( __CSMC__ )
jhon309 0:ac8863619623 104 #define __packed
jhon309 0:ac8863619623 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
jhon309 0:ac8863619623 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
jhon309 0:ac8863619623 107 #define __STATIC_INLINE static inline
jhon309 0:ac8863619623 108
jhon309 0:ac8863619623 109 #endif
jhon309 0:ac8863619623 110
jhon309 0:ac8863619623 111 /** __FPU_USED indicates whether an FPU is used or not.
jhon309 0:ac8863619623 112 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
jhon309 0:ac8863619623 113 */
jhon309 0:ac8863619623 114 #if defined ( __CC_ARM )
jhon309 0:ac8863619623 115 #if defined __TARGET_FPU_VFP
jhon309 0:ac8863619623 116 #if (__FPU_PRESENT == 1)
jhon309 0:ac8863619623 117 #define __FPU_USED 1
jhon309 0:ac8863619623 118 #else
jhon309 0:ac8863619623 119 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:ac8863619623 120 #define __FPU_USED 0
jhon309 0:ac8863619623 121 #endif
jhon309 0:ac8863619623 122 #else
jhon309 0:ac8863619623 123 #define __FPU_USED 0
jhon309 0:ac8863619623 124 #endif
jhon309 0:ac8863619623 125
jhon309 0:ac8863619623 126 #elif defined ( __GNUC__ )
jhon309 0:ac8863619623 127 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
jhon309 0:ac8863619623 128 #if (__FPU_PRESENT == 1)
jhon309 0:ac8863619623 129 #define __FPU_USED 1
jhon309 0:ac8863619623 130 #else
jhon309 0:ac8863619623 131 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:ac8863619623 132 #define __FPU_USED 0
jhon309 0:ac8863619623 133 #endif
jhon309 0:ac8863619623 134 #else
jhon309 0:ac8863619623 135 #define __FPU_USED 0
jhon309 0:ac8863619623 136 #endif
jhon309 0:ac8863619623 137
jhon309 0:ac8863619623 138 #elif defined ( __ICCARM__ )
jhon309 0:ac8863619623 139 #if defined __ARMVFP__
jhon309 0:ac8863619623 140 #if (__FPU_PRESENT == 1)
jhon309 0:ac8863619623 141 #define __FPU_USED 1
jhon309 0:ac8863619623 142 #else
jhon309 0:ac8863619623 143 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:ac8863619623 144 #define __FPU_USED 0
jhon309 0:ac8863619623 145 #endif
jhon309 0:ac8863619623 146 #else
jhon309 0:ac8863619623 147 #define __FPU_USED 0
jhon309 0:ac8863619623 148 #endif
jhon309 0:ac8863619623 149
jhon309 0:ac8863619623 150 #elif defined ( __TMS470__ )
jhon309 0:ac8863619623 151 #if defined __TI_VFP_SUPPORT__
jhon309 0:ac8863619623 152 #if (__FPU_PRESENT == 1)
jhon309 0:ac8863619623 153 #define __FPU_USED 1
jhon309 0:ac8863619623 154 #else
jhon309 0:ac8863619623 155 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:ac8863619623 156 #define __FPU_USED 0
jhon309 0:ac8863619623 157 #endif
jhon309 0:ac8863619623 158 #else
jhon309 0:ac8863619623 159 #define __FPU_USED 0
jhon309 0:ac8863619623 160 #endif
jhon309 0:ac8863619623 161
jhon309 0:ac8863619623 162 #elif defined ( __TASKING__ )
jhon309 0:ac8863619623 163 #if defined __FPU_VFP__
jhon309 0:ac8863619623 164 #if (__FPU_PRESENT == 1)
jhon309 0:ac8863619623 165 #define __FPU_USED 1
jhon309 0:ac8863619623 166 #else
jhon309 0:ac8863619623 167 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:ac8863619623 168 #define __FPU_USED 0
jhon309 0:ac8863619623 169 #endif
jhon309 0:ac8863619623 170 #else
jhon309 0:ac8863619623 171 #define __FPU_USED 0
jhon309 0:ac8863619623 172 #endif
jhon309 0:ac8863619623 173
jhon309 0:ac8863619623 174 #elif defined ( __CSMC__ ) /* Cosmic */
jhon309 0:ac8863619623 175 #if ( __CSMC__ & 0x400) // FPU present for parser
jhon309 0:ac8863619623 176 #if (__FPU_PRESENT == 1)
jhon309 0:ac8863619623 177 #define __FPU_USED 1
jhon309 0:ac8863619623 178 #else
jhon309 0:ac8863619623 179 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:ac8863619623 180 #define __FPU_USED 0
jhon309 0:ac8863619623 181 #endif
jhon309 0:ac8863619623 182 #else
jhon309 0:ac8863619623 183 #define __FPU_USED 0
jhon309 0:ac8863619623 184 #endif
jhon309 0:ac8863619623 185 #endif
jhon309 0:ac8863619623 186
jhon309 0:ac8863619623 187 #include <stdint.h> /* standard types definitions */
jhon309 0:ac8863619623 188 #include <core_cmInstr.h> /* Core Instruction Access */
jhon309 0:ac8863619623 189 #include <core_cmFunc.h> /* Core Function Access */
jhon309 0:ac8863619623 190 #include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
jhon309 0:ac8863619623 191
jhon309 0:ac8863619623 192 #ifdef __cplusplus
jhon309 0:ac8863619623 193 }
jhon309 0:ac8863619623 194 #endif
jhon309 0:ac8863619623 195
jhon309 0:ac8863619623 196 #endif /* __CORE_CM7_H_GENERIC */
jhon309 0:ac8863619623 197
jhon309 0:ac8863619623 198 #ifndef __CMSIS_GENERIC
jhon309 0:ac8863619623 199
jhon309 0:ac8863619623 200 #ifndef __CORE_CM7_H_DEPENDANT
jhon309 0:ac8863619623 201 #define __CORE_CM7_H_DEPENDANT
jhon309 0:ac8863619623 202
jhon309 0:ac8863619623 203 #ifdef __cplusplus
jhon309 0:ac8863619623 204 extern "C" {
jhon309 0:ac8863619623 205 #endif
jhon309 0:ac8863619623 206
jhon309 0:ac8863619623 207 /* check device defines and use defaults */
jhon309 0:ac8863619623 208 #if defined __CHECK_DEVICE_DEFINES
jhon309 0:ac8863619623 209 #ifndef __CM7_REV
jhon309 0:ac8863619623 210 #define __CM7_REV 0x0000
jhon309 0:ac8863619623 211 #warning "__CM7_REV not defined in device header file; using default!"
jhon309 0:ac8863619623 212 #endif
jhon309 0:ac8863619623 213
jhon309 0:ac8863619623 214 #ifndef __FPU_PRESENT
jhon309 0:ac8863619623 215 #define __FPU_PRESENT 0
jhon309 0:ac8863619623 216 #warning "__FPU_PRESENT not defined in device header file; using default!"
jhon309 0:ac8863619623 217 #endif
jhon309 0:ac8863619623 218
jhon309 0:ac8863619623 219 #ifndef __MPU_PRESENT
jhon309 0:ac8863619623 220 #define __MPU_PRESENT 0
jhon309 0:ac8863619623 221 #warning "__MPU_PRESENT not defined in device header file; using default!"
jhon309 0:ac8863619623 222 #endif
jhon309 0:ac8863619623 223
jhon309 0:ac8863619623 224 #ifndef __ICACHE_PRESENT
jhon309 0:ac8863619623 225 #define __ICACHE_PRESENT 0
jhon309 0:ac8863619623 226 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
jhon309 0:ac8863619623 227 #endif
jhon309 0:ac8863619623 228
jhon309 0:ac8863619623 229 #ifndef __DCACHE_PRESENT
jhon309 0:ac8863619623 230 #define __DCACHE_PRESENT 0
jhon309 0:ac8863619623 231 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
jhon309 0:ac8863619623 232 #endif
jhon309 0:ac8863619623 233
jhon309 0:ac8863619623 234 #ifndef __DTCM_PRESENT
jhon309 0:ac8863619623 235 #define __DTCM_PRESENT 0
jhon309 0:ac8863619623 236 #warning "__DTCM_PRESENT not defined in device header file; using default!"
jhon309 0:ac8863619623 237 #endif
jhon309 0:ac8863619623 238
jhon309 0:ac8863619623 239 #ifndef __NVIC_PRIO_BITS
jhon309 0:ac8863619623 240 #define __NVIC_PRIO_BITS 3
jhon309 0:ac8863619623 241 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
jhon309 0:ac8863619623 242 #endif
jhon309 0:ac8863619623 243
jhon309 0:ac8863619623 244 #ifndef __Vendor_SysTickConfig
jhon309 0:ac8863619623 245 #define __Vendor_SysTickConfig 0
jhon309 0:ac8863619623 246 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
jhon309 0:ac8863619623 247 #endif
jhon309 0:ac8863619623 248 #endif
jhon309 0:ac8863619623 249
jhon309 0:ac8863619623 250 /* IO definitions (access restrictions to peripheral registers) */
jhon309 0:ac8863619623 251 /**
jhon309 0:ac8863619623 252 \defgroup CMSIS_glob_defs CMSIS Global Defines
jhon309 0:ac8863619623 253
jhon309 0:ac8863619623 254 <strong>IO Type Qualifiers</strong> are used
jhon309 0:ac8863619623 255 \li to specify the access to peripheral variables.
jhon309 0:ac8863619623 256 \li for automatic generation of peripheral register debug information.
jhon309 0:ac8863619623 257 */
jhon309 0:ac8863619623 258 #ifdef __cplusplus
jhon309 0:ac8863619623 259 #define __I volatile /*!< Defines 'read only' permissions */
jhon309 0:ac8863619623 260 #else
jhon309 0:ac8863619623 261 #define __I volatile const /*!< Defines 'read only' permissions */
jhon309 0:ac8863619623 262 #endif
jhon309 0:ac8863619623 263 #define __O volatile /*!< Defines 'write only' permissions */
jhon309 0:ac8863619623 264 #define __IO volatile /*!< Defines 'read / write' permissions */
jhon309 0:ac8863619623 265
jhon309 0:ac8863619623 266 /*@} end of group Cortex_M7 */
jhon309 0:ac8863619623 267
jhon309 0:ac8863619623 268
jhon309 0:ac8863619623 269
jhon309 0:ac8863619623 270 /*******************************************************************************
jhon309 0:ac8863619623 271 * Register Abstraction
jhon309 0:ac8863619623 272 Core Register contain:
jhon309 0:ac8863619623 273 - Core Register
jhon309 0:ac8863619623 274 - Core NVIC Register
jhon309 0:ac8863619623 275 - Core SCB Register
jhon309 0:ac8863619623 276 - Core SysTick Register
jhon309 0:ac8863619623 277 - Core Debug Register
jhon309 0:ac8863619623 278 - Core MPU Register
jhon309 0:ac8863619623 279 - Core FPU Register
jhon309 0:ac8863619623 280 ******************************************************************************/
jhon309 0:ac8863619623 281 /** \defgroup CMSIS_core_register Defines and Type Definitions
jhon309 0:ac8863619623 282 \brief Type definitions and defines for Cortex-M processor based devices.
jhon309 0:ac8863619623 283 */
jhon309 0:ac8863619623 284
jhon309 0:ac8863619623 285 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 286 \defgroup CMSIS_CORE Status and Control Registers
jhon309 0:ac8863619623 287 \brief Core Register type definitions.
jhon309 0:ac8863619623 288 @{
jhon309 0:ac8863619623 289 */
jhon309 0:ac8863619623 290
jhon309 0:ac8863619623 291 /** \brief Union type to access the Application Program Status Register (APSR).
jhon309 0:ac8863619623 292 */
jhon309 0:ac8863619623 293 typedef union
jhon309 0:ac8863619623 294 {
jhon309 0:ac8863619623 295 struct
jhon309 0:ac8863619623 296 {
jhon309 0:ac8863619623 297 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
jhon309 0:ac8863619623 298 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
jhon309 0:ac8863619623 299 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
jhon309 0:ac8863619623 300 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
jhon309 0:ac8863619623 301 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
jhon309 0:ac8863619623 302 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
jhon309 0:ac8863619623 303 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
jhon309 0:ac8863619623 304 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
jhon309 0:ac8863619623 305 } b; /*!< Structure used for bit access */
jhon309 0:ac8863619623 306 uint32_t w; /*!< Type used for word access */
jhon309 0:ac8863619623 307 } APSR_Type;
jhon309 0:ac8863619623 308
jhon309 0:ac8863619623 309 /* APSR Register Definitions */
jhon309 0:ac8863619623 310 #define APSR_N_Pos 31 /*!< APSR: N Position */
jhon309 0:ac8863619623 311 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
jhon309 0:ac8863619623 312
jhon309 0:ac8863619623 313 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
jhon309 0:ac8863619623 314 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
jhon309 0:ac8863619623 315
jhon309 0:ac8863619623 316 #define APSR_C_Pos 29 /*!< APSR: C Position */
jhon309 0:ac8863619623 317 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
jhon309 0:ac8863619623 318
jhon309 0:ac8863619623 319 #define APSR_V_Pos 28 /*!< APSR: V Position */
jhon309 0:ac8863619623 320 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
jhon309 0:ac8863619623 321
jhon309 0:ac8863619623 322 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
jhon309 0:ac8863619623 323 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
jhon309 0:ac8863619623 324
jhon309 0:ac8863619623 325 #define APSR_GE_Pos 16 /*!< APSR: GE Position */
jhon309 0:ac8863619623 326 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
jhon309 0:ac8863619623 327
jhon309 0:ac8863619623 328
jhon309 0:ac8863619623 329 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
jhon309 0:ac8863619623 330 */
jhon309 0:ac8863619623 331 typedef union
jhon309 0:ac8863619623 332 {
jhon309 0:ac8863619623 333 struct
jhon309 0:ac8863619623 334 {
jhon309 0:ac8863619623 335 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
jhon309 0:ac8863619623 336 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
jhon309 0:ac8863619623 337 } b; /*!< Structure used for bit access */
jhon309 0:ac8863619623 338 uint32_t w; /*!< Type used for word access */
jhon309 0:ac8863619623 339 } IPSR_Type;
jhon309 0:ac8863619623 340
jhon309 0:ac8863619623 341 /* IPSR Register Definitions */
jhon309 0:ac8863619623 342 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
jhon309 0:ac8863619623 343 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
jhon309 0:ac8863619623 344
jhon309 0:ac8863619623 345
jhon309 0:ac8863619623 346 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
jhon309 0:ac8863619623 347 */
jhon309 0:ac8863619623 348 typedef union
jhon309 0:ac8863619623 349 {
jhon309 0:ac8863619623 350 struct
jhon309 0:ac8863619623 351 {
jhon309 0:ac8863619623 352 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
jhon309 0:ac8863619623 353 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
jhon309 0:ac8863619623 354 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
jhon309 0:ac8863619623 355 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
jhon309 0:ac8863619623 356 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
jhon309 0:ac8863619623 357 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
jhon309 0:ac8863619623 358 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
jhon309 0:ac8863619623 359 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
jhon309 0:ac8863619623 360 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
jhon309 0:ac8863619623 361 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
jhon309 0:ac8863619623 362 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
jhon309 0:ac8863619623 363 } b; /*!< Structure used for bit access */
jhon309 0:ac8863619623 364 uint32_t w; /*!< Type used for word access */
jhon309 0:ac8863619623 365 } xPSR_Type;
jhon309 0:ac8863619623 366
jhon309 0:ac8863619623 367 /* xPSR Register Definitions */
jhon309 0:ac8863619623 368 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
jhon309 0:ac8863619623 369 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
jhon309 0:ac8863619623 370
jhon309 0:ac8863619623 371 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
jhon309 0:ac8863619623 372 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
jhon309 0:ac8863619623 373
jhon309 0:ac8863619623 374 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
jhon309 0:ac8863619623 375 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
jhon309 0:ac8863619623 376
jhon309 0:ac8863619623 377 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
jhon309 0:ac8863619623 378 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
jhon309 0:ac8863619623 379
jhon309 0:ac8863619623 380 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
jhon309 0:ac8863619623 381 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
jhon309 0:ac8863619623 382
jhon309 0:ac8863619623 383 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
jhon309 0:ac8863619623 384 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
jhon309 0:ac8863619623 385
jhon309 0:ac8863619623 386 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
jhon309 0:ac8863619623 387 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
jhon309 0:ac8863619623 388
jhon309 0:ac8863619623 389 #define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
jhon309 0:ac8863619623 390 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
jhon309 0:ac8863619623 391
jhon309 0:ac8863619623 392 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
jhon309 0:ac8863619623 393 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
jhon309 0:ac8863619623 394
jhon309 0:ac8863619623 395
jhon309 0:ac8863619623 396 /** \brief Union type to access the Control Registers (CONTROL).
jhon309 0:ac8863619623 397 */
jhon309 0:ac8863619623 398 typedef union
jhon309 0:ac8863619623 399 {
jhon309 0:ac8863619623 400 struct
jhon309 0:ac8863619623 401 {
jhon309 0:ac8863619623 402 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
jhon309 0:ac8863619623 403 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
jhon309 0:ac8863619623 404 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
jhon309 0:ac8863619623 405 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
jhon309 0:ac8863619623 406 } b; /*!< Structure used for bit access */
jhon309 0:ac8863619623 407 uint32_t w; /*!< Type used for word access */
jhon309 0:ac8863619623 408 } CONTROL_Type;
jhon309 0:ac8863619623 409
jhon309 0:ac8863619623 410 /* CONTROL Register Definitions */
jhon309 0:ac8863619623 411 #define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
jhon309 0:ac8863619623 412 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
jhon309 0:ac8863619623 413
jhon309 0:ac8863619623 414 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
jhon309 0:ac8863619623 415 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
jhon309 0:ac8863619623 416
jhon309 0:ac8863619623 417 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
jhon309 0:ac8863619623 418 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
jhon309 0:ac8863619623 419
jhon309 0:ac8863619623 420 /*@} end of group CMSIS_CORE */
jhon309 0:ac8863619623 421
jhon309 0:ac8863619623 422
jhon309 0:ac8863619623 423 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 424 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
jhon309 0:ac8863619623 425 \brief Type definitions for the NVIC Registers
jhon309 0:ac8863619623 426 @{
jhon309 0:ac8863619623 427 */
jhon309 0:ac8863619623 428
jhon309 0:ac8863619623 429 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
jhon309 0:ac8863619623 430 */
jhon309 0:ac8863619623 431 typedef struct
jhon309 0:ac8863619623 432 {
jhon309 0:ac8863619623 433 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
jhon309 0:ac8863619623 434 uint32_t RESERVED0[24];
jhon309 0:ac8863619623 435 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
jhon309 0:ac8863619623 436 uint32_t RSERVED1[24];
jhon309 0:ac8863619623 437 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
jhon309 0:ac8863619623 438 uint32_t RESERVED2[24];
jhon309 0:ac8863619623 439 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
jhon309 0:ac8863619623 440 uint32_t RESERVED3[24];
jhon309 0:ac8863619623 441 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
jhon309 0:ac8863619623 442 uint32_t RESERVED4[56];
jhon309 0:ac8863619623 443 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
jhon309 0:ac8863619623 444 uint32_t RESERVED5[644];
jhon309 0:ac8863619623 445 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
jhon309 0:ac8863619623 446 } NVIC_Type;
jhon309 0:ac8863619623 447
jhon309 0:ac8863619623 448 /* Software Triggered Interrupt Register Definitions */
jhon309 0:ac8863619623 449 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
jhon309 0:ac8863619623 450 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
jhon309 0:ac8863619623 451
jhon309 0:ac8863619623 452 /*@} end of group CMSIS_NVIC */
jhon309 0:ac8863619623 453
jhon309 0:ac8863619623 454
jhon309 0:ac8863619623 455 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 456 \defgroup CMSIS_SCB System Control Block (SCB)
jhon309 0:ac8863619623 457 \brief Type definitions for the System Control Block Registers
jhon309 0:ac8863619623 458 @{
jhon309 0:ac8863619623 459 */
jhon309 0:ac8863619623 460
jhon309 0:ac8863619623 461 /** \brief Structure type to access the System Control Block (SCB).
jhon309 0:ac8863619623 462 */
jhon309 0:ac8863619623 463 typedef struct
jhon309 0:ac8863619623 464 {
jhon309 0:ac8863619623 465 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
jhon309 0:ac8863619623 466 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
jhon309 0:ac8863619623 467 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
jhon309 0:ac8863619623 468 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
jhon309 0:ac8863619623 469 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
jhon309 0:ac8863619623 470 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
jhon309 0:ac8863619623 471 __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
jhon309 0:ac8863619623 472 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
jhon309 0:ac8863619623 473 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
jhon309 0:ac8863619623 474 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
jhon309 0:ac8863619623 475 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
jhon309 0:ac8863619623 476 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
jhon309 0:ac8863619623 477 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
jhon309 0:ac8863619623 478 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
jhon309 0:ac8863619623 479 __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
jhon309 0:ac8863619623 480 __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
jhon309 0:ac8863619623 481 __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
jhon309 0:ac8863619623 482 __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
jhon309 0:ac8863619623 483 __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
jhon309 0:ac8863619623 484 uint32_t RESERVED0[1];
jhon309 0:ac8863619623 485 __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
jhon309 0:ac8863619623 486 __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
jhon309 0:ac8863619623 487 __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
jhon309 0:ac8863619623 488 __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
jhon309 0:ac8863619623 489 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
jhon309 0:ac8863619623 490 uint32_t RESERVED3[93];
jhon309 0:ac8863619623 491 __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
jhon309 0:ac8863619623 492 uint32_t RESERVED4[15];
jhon309 0:ac8863619623 493 __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
jhon309 0:ac8863619623 494 __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
jhon309 0:ac8863619623 495 __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
jhon309 0:ac8863619623 496 uint32_t RESERVED5[1];
jhon309 0:ac8863619623 497 __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
jhon309 0:ac8863619623 498 uint32_t RESERVED6[1];
jhon309 0:ac8863619623 499 __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
jhon309 0:ac8863619623 500 __O uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
jhon309 0:ac8863619623 501 __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
jhon309 0:ac8863619623 502 __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
jhon309 0:ac8863619623 503 __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
jhon309 0:ac8863619623 504 __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
jhon309 0:ac8863619623 505 __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
jhon309 0:ac8863619623 506 __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
jhon309 0:ac8863619623 507 uint32_t RESERVED7[6];
jhon309 0:ac8863619623 508 __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
jhon309 0:ac8863619623 509 __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
jhon309 0:ac8863619623 510 __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
jhon309 0:ac8863619623 511 __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
jhon309 0:ac8863619623 512 __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
jhon309 0:ac8863619623 513 uint32_t RESERVED8[1];
jhon309 0:ac8863619623 514 __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
jhon309 0:ac8863619623 515 } SCB_Type;
jhon309 0:ac8863619623 516
jhon309 0:ac8863619623 517 /* SCB CPUID Register Definitions */
jhon309 0:ac8863619623 518 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
jhon309 0:ac8863619623 519 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
jhon309 0:ac8863619623 520
jhon309 0:ac8863619623 521 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
jhon309 0:ac8863619623 522 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
jhon309 0:ac8863619623 523
jhon309 0:ac8863619623 524 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
jhon309 0:ac8863619623 525 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
jhon309 0:ac8863619623 526
jhon309 0:ac8863619623 527 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
jhon309 0:ac8863619623 528 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
jhon309 0:ac8863619623 529
jhon309 0:ac8863619623 530 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
jhon309 0:ac8863619623 531 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
jhon309 0:ac8863619623 532
jhon309 0:ac8863619623 533 /* SCB Interrupt Control State Register Definitions */
jhon309 0:ac8863619623 534 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
jhon309 0:ac8863619623 535 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
jhon309 0:ac8863619623 536
jhon309 0:ac8863619623 537 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
jhon309 0:ac8863619623 538 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
jhon309 0:ac8863619623 539
jhon309 0:ac8863619623 540 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
jhon309 0:ac8863619623 541 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
jhon309 0:ac8863619623 542
jhon309 0:ac8863619623 543 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
jhon309 0:ac8863619623 544 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
jhon309 0:ac8863619623 545
jhon309 0:ac8863619623 546 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
jhon309 0:ac8863619623 547 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
jhon309 0:ac8863619623 548
jhon309 0:ac8863619623 549 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
jhon309 0:ac8863619623 550 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
jhon309 0:ac8863619623 551
jhon309 0:ac8863619623 552 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
jhon309 0:ac8863619623 553 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
jhon309 0:ac8863619623 554
jhon309 0:ac8863619623 555 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
jhon309 0:ac8863619623 556 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
jhon309 0:ac8863619623 557
jhon309 0:ac8863619623 558 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
jhon309 0:ac8863619623 559 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
jhon309 0:ac8863619623 560
jhon309 0:ac8863619623 561 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
jhon309 0:ac8863619623 562 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
jhon309 0:ac8863619623 563
jhon309 0:ac8863619623 564 /* SCB Vector Table Offset Register Definitions */
jhon309 0:ac8863619623 565 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
jhon309 0:ac8863619623 566 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
jhon309 0:ac8863619623 567
jhon309 0:ac8863619623 568 /* SCB Application Interrupt and Reset Control Register Definitions */
jhon309 0:ac8863619623 569 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
jhon309 0:ac8863619623 570 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
jhon309 0:ac8863619623 571
jhon309 0:ac8863619623 572 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
jhon309 0:ac8863619623 573 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
jhon309 0:ac8863619623 574
jhon309 0:ac8863619623 575 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
jhon309 0:ac8863619623 576 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
jhon309 0:ac8863619623 577
jhon309 0:ac8863619623 578 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
jhon309 0:ac8863619623 579 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
jhon309 0:ac8863619623 580
jhon309 0:ac8863619623 581 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
jhon309 0:ac8863619623 582 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
jhon309 0:ac8863619623 583
jhon309 0:ac8863619623 584 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
jhon309 0:ac8863619623 585 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
jhon309 0:ac8863619623 586
jhon309 0:ac8863619623 587 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
jhon309 0:ac8863619623 588 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
jhon309 0:ac8863619623 589
jhon309 0:ac8863619623 590 /* SCB System Control Register Definitions */
jhon309 0:ac8863619623 591 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
jhon309 0:ac8863619623 592 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
jhon309 0:ac8863619623 593
jhon309 0:ac8863619623 594 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
jhon309 0:ac8863619623 595 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
jhon309 0:ac8863619623 596
jhon309 0:ac8863619623 597 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
jhon309 0:ac8863619623 598 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
jhon309 0:ac8863619623 599
jhon309 0:ac8863619623 600 /* SCB Configuration Control Register Definitions */
jhon309 0:ac8863619623 601 #define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */
jhon309 0:ac8863619623 602 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
jhon309 0:ac8863619623 603
jhon309 0:ac8863619623 604 #define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */
jhon309 0:ac8863619623 605 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
jhon309 0:ac8863619623 606
jhon309 0:ac8863619623 607 #define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */
jhon309 0:ac8863619623 608 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
jhon309 0:ac8863619623 609
jhon309 0:ac8863619623 610 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
jhon309 0:ac8863619623 611 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
jhon309 0:ac8863619623 612
jhon309 0:ac8863619623 613 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
jhon309 0:ac8863619623 614 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
jhon309 0:ac8863619623 615
jhon309 0:ac8863619623 616 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
jhon309 0:ac8863619623 617 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
jhon309 0:ac8863619623 618
jhon309 0:ac8863619623 619 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
jhon309 0:ac8863619623 620 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
jhon309 0:ac8863619623 621
jhon309 0:ac8863619623 622 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
jhon309 0:ac8863619623 623 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
jhon309 0:ac8863619623 624
jhon309 0:ac8863619623 625 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
jhon309 0:ac8863619623 626 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
jhon309 0:ac8863619623 627
jhon309 0:ac8863619623 628 /* SCB System Handler Control and State Register Definitions */
jhon309 0:ac8863619623 629 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
jhon309 0:ac8863619623 630 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
jhon309 0:ac8863619623 631
jhon309 0:ac8863619623 632 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
jhon309 0:ac8863619623 633 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
jhon309 0:ac8863619623 634
jhon309 0:ac8863619623 635 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
jhon309 0:ac8863619623 636 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
jhon309 0:ac8863619623 637
jhon309 0:ac8863619623 638 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
jhon309 0:ac8863619623 639 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
jhon309 0:ac8863619623 640
jhon309 0:ac8863619623 641 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
jhon309 0:ac8863619623 642 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
jhon309 0:ac8863619623 643
jhon309 0:ac8863619623 644 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
jhon309 0:ac8863619623 645 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
jhon309 0:ac8863619623 646
jhon309 0:ac8863619623 647 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
jhon309 0:ac8863619623 648 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
jhon309 0:ac8863619623 649
jhon309 0:ac8863619623 650 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
jhon309 0:ac8863619623 651 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
jhon309 0:ac8863619623 652
jhon309 0:ac8863619623 653 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
jhon309 0:ac8863619623 654 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
jhon309 0:ac8863619623 655
jhon309 0:ac8863619623 656 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
jhon309 0:ac8863619623 657 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
jhon309 0:ac8863619623 658
jhon309 0:ac8863619623 659 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
jhon309 0:ac8863619623 660 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
jhon309 0:ac8863619623 661
jhon309 0:ac8863619623 662 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
jhon309 0:ac8863619623 663 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
jhon309 0:ac8863619623 664
jhon309 0:ac8863619623 665 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
jhon309 0:ac8863619623 666 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
jhon309 0:ac8863619623 667
jhon309 0:ac8863619623 668 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
jhon309 0:ac8863619623 669 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
jhon309 0:ac8863619623 670
jhon309 0:ac8863619623 671 /* SCB Configurable Fault Status Registers Definitions */
jhon309 0:ac8863619623 672 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
jhon309 0:ac8863619623 673 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
jhon309 0:ac8863619623 674
jhon309 0:ac8863619623 675 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
jhon309 0:ac8863619623 676 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
jhon309 0:ac8863619623 677
jhon309 0:ac8863619623 678 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
jhon309 0:ac8863619623 679 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
jhon309 0:ac8863619623 680
jhon309 0:ac8863619623 681 /* SCB Hard Fault Status Registers Definitions */
jhon309 0:ac8863619623 682 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
jhon309 0:ac8863619623 683 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
jhon309 0:ac8863619623 684
jhon309 0:ac8863619623 685 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
jhon309 0:ac8863619623 686 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
jhon309 0:ac8863619623 687
jhon309 0:ac8863619623 688 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
jhon309 0:ac8863619623 689 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
jhon309 0:ac8863619623 690
jhon309 0:ac8863619623 691 /* SCB Debug Fault Status Register Definitions */
jhon309 0:ac8863619623 692 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
jhon309 0:ac8863619623 693 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
jhon309 0:ac8863619623 694
jhon309 0:ac8863619623 695 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
jhon309 0:ac8863619623 696 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
jhon309 0:ac8863619623 697
jhon309 0:ac8863619623 698 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
jhon309 0:ac8863619623 699 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
jhon309 0:ac8863619623 700
jhon309 0:ac8863619623 701 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
jhon309 0:ac8863619623 702 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
jhon309 0:ac8863619623 703
jhon309 0:ac8863619623 704 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
jhon309 0:ac8863619623 705 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
jhon309 0:ac8863619623 706
jhon309 0:ac8863619623 707 /* Cache Level ID register */
jhon309 0:ac8863619623 708 #define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */
jhon309 0:ac8863619623 709 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
jhon309 0:ac8863619623 710
jhon309 0:ac8863619623 711 #define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */
jhon309 0:ac8863619623 712 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */
jhon309 0:ac8863619623 713
jhon309 0:ac8863619623 714 /* Cache Type register */
jhon309 0:ac8863619623 715 #define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */
jhon309 0:ac8863619623 716 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
jhon309 0:ac8863619623 717
jhon309 0:ac8863619623 718 #define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */
jhon309 0:ac8863619623 719 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
jhon309 0:ac8863619623 720
jhon309 0:ac8863619623 721 #define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */
jhon309 0:ac8863619623 722 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
jhon309 0:ac8863619623 723
jhon309 0:ac8863619623 724 #define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */
jhon309 0:ac8863619623 725 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
jhon309 0:ac8863619623 726
jhon309 0:ac8863619623 727 #define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */
jhon309 0:ac8863619623 728 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
jhon309 0:ac8863619623 729
jhon309 0:ac8863619623 730 /* Cache Size ID Register */
jhon309 0:ac8863619623 731 #define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */
jhon309 0:ac8863619623 732 #define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
jhon309 0:ac8863619623 733
jhon309 0:ac8863619623 734 #define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */
jhon309 0:ac8863619623 735 #define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
jhon309 0:ac8863619623 736
jhon309 0:ac8863619623 737 #define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */
jhon309 0:ac8863619623 738 #define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
jhon309 0:ac8863619623 739
jhon309 0:ac8863619623 740 #define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */
jhon309 0:ac8863619623 741 #define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
jhon309 0:ac8863619623 742
jhon309 0:ac8863619623 743 #define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */
jhon309 0:ac8863619623 744 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
jhon309 0:ac8863619623 745
jhon309 0:ac8863619623 746 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */
jhon309 0:ac8863619623 747 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
jhon309 0:ac8863619623 748
jhon309 0:ac8863619623 749 #define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */
jhon309 0:ac8863619623 750 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
jhon309 0:ac8863619623 751
jhon309 0:ac8863619623 752 /* Cache Size Selection Register */
jhon309 0:ac8863619623 753 #define SCB_CSSELR_LEVEL_Pos 1 /*!< SCB CSSELR: Level Position */
jhon309 0:ac8863619623 754 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
jhon309 0:ac8863619623 755
jhon309 0:ac8863619623 756 #define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */
jhon309 0:ac8863619623 757 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
jhon309 0:ac8863619623 758
jhon309 0:ac8863619623 759 /* SCB Software Triggered Interrupt Register */
jhon309 0:ac8863619623 760 #define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */
jhon309 0:ac8863619623 761 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
jhon309 0:ac8863619623 762
jhon309 0:ac8863619623 763 /* Instruction Tightly-Coupled Memory Control Register*/
jhon309 0:ac8863619623 764 #define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */
jhon309 0:ac8863619623 765 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
jhon309 0:ac8863619623 766
jhon309 0:ac8863619623 767 #define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */
jhon309 0:ac8863619623 768 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
jhon309 0:ac8863619623 769
jhon309 0:ac8863619623 770 #define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */
jhon309 0:ac8863619623 771 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
jhon309 0:ac8863619623 772
jhon309 0:ac8863619623 773 #define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */
jhon309 0:ac8863619623 774 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
jhon309 0:ac8863619623 775
jhon309 0:ac8863619623 776 /* Data Tightly-Coupled Memory Control Registers */
jhon309 0:ac8863619623 777 #define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */
jhon309 0:ac8863619623 778 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
jhon309 0:ac8863619623 779
jhon309 0:ac8863619623 780 #define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */
jhon309 0:ac8863619623 781 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
jhon309 0:ac8863619623 782
jhon309 0:ac8863619623 783 #define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */
jhon309 0:ac8863619623 784 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
jhon309 0:ac8863619623 785
jhon309 0:ac8863619623 786 #define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */
jhon309 0:ac8863619623 787 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
jhon309 0:ac8863619623 788
jhon309 0:ac8863619623 789 /* AHBP Control Register */
jhon309 0:ac8863619623 790 #define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */
jhon309 0:ac8863619623 791 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
jhon309 0:ac8863619623 792
jhon309 0:ac8863619623 793 #define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */
jhon309 0:ac8863619623 794 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
jhon309 0:ac8863619623 795
jhon309 0:ac8863619623 796 /* L1 Cache Control Register */
jhon309 0:ac8863619623 797 #define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */
jhon309 0:ac8863619623 798 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
jhon309 0:ac8863619623 799
jhon309 0:ac8863619623 800 #define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */
jhon309 0:ac8863619623 801 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
jhon309 0:ac8863619623 802
jhon309 0:ac8863619623 803 #define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */
jhon309 0:ac8863619623 804 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
jhon309 0:ac8863619623 805
jhon309 0:ac8863619623 806 /* AHBS control register */
jhon309 0:ac8863619623 807 #define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */
jhon309 0:ac8863619623 808 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
jhon309 0:ac8863619623 809
jhon309 0:ac8863619623 810 #define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */
jhon309 0:ac8863619623 811 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
jhon309 0:ac8863619623 812
jhon309 0:ac8863619623 813 #define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/
jhon309 0:ac8863619623 814 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
jhon309 0:ac8863619623 815
jhon309 0:ac8863619623 816 /* Auxiliary Bus Fault Status Register */
jhon309 0:ac8863619623 817 #define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/
jhon309 0:ac8863619623 818 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
jhon309 0:ac8863619623 819
jhon309 0:ac8863619623 820 #define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/
jhon309 0:ac8863619623 821 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
jhon309 0:ac8863619623 822
jhon309 0:ac8863619623 823 #define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/
jhon309 0:ac8863619623 824 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
jhon309 0:ac8863619623 825
jhon309 0:ac8863619623 826 #define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/
jhon309 0:ac8863619623 827 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
jhon309 0:ac8863619623 828
jhon309 0:ac8863619623 829 #define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/
jhon309 0:ac8863619623 830 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
jhon309 0:ac8863619623 831
jhon309 0:ac8863619623 832 #define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/
jhon309 0:ac8863619623 833 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
jhon309 0:ac8863619623 834
jhon309 0:ac8863619623 835 /*@} end of group CMSIS_SCB */
jhon309 0:ac8863619623 836
jhon309 0:ac8863619623 837
jhon309 0:ac8863619623 838 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 839 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
jhon309 0:ac8863619623 840 \brief Type definitions for the System Control and ID Register not in the SCB
jhon309 0:ac8863619623 841 @{
jhon309 0:ac8863619623 842 */
jhon309 0:ac8863619623 843
jhon309 0:ac8863619623 844 /** \brief Structure type to access the System Control and ID Register not in the SCB.
jhon309 0:ac8863619623 845 */
jhon309 0:ac8863619623 846 typedef struct
jhon309 0:ac8863619623 847 {
jhon309 0:ac8863619623 848 uint32_t RESERVED0[1];
jhon309 0:ac8863619623 849 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
jhon309 0:ac8863619623 850 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
jhon309 0:ac8863619623 851 } SCnSCB_Type;
jhon309 0:ac8863619623 852
jhon309 0:ac8863619623 853 /* Interrupt Controller Type Register Definitions */
jhon309 0:ac8863619623 854 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
jhon309 0:ac8863619623 855 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
jhon309 0:ac8863619623 856
jhon309 0:ac8863619623 857 /* Auxiliary Control Register Definitions */
jhon309 0:ac8863619623 858 #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */
jhon309 0:ac8863619623 859 #define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
jhon309 0:ac8863619623 860
jhon309 0:ac8863619623 861 #define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */
jhon309 0:ac8863619623 862 #define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
jhon309 0:ac8863619623 863
jhon309 0:ac8863619623 864 #define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */
jhon309 0:ac8863619623 865 #define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
jhon309 0:ac8863619623 866
jhon309 0:ac8863619623 867 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
jhon309 0:ac8863619623 868 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
jhon309 0:ac8863619623 869
jhon309 0:ac8863619623 870 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
jhon309 0:ac8863619623 871 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
jhon309 0:ac8863619623 872
jhon309 0:ac8863619623 873 /*@} end of group CMSIS_SCnotSCB */
jhon309 0:ac8863619623 874
jhon309 0:ac8863619623 875
jhon309 0:ac8863619623 876 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 877 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
jhon309 0:ac8863619623 878 \brief Type definitions for the System Timer Registers.
jhon309 0:ac8863619623 879 @{
jhon309 0:ac8863619623 880 */
jhon309 0:ac8863619623 881
jhon309 0:ac8863619623 882 /** \brief Structure type to access the System Timer (SysTick).
jhon309 0:ac8863619623 883 */
jhon309 0:ac8863619623 884 typedef struct
jhon309 0:ac8863619623 885 {
jhon309 0:ac8863619623 886 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
jhon309 0:ac8863619623 887 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
jhon309 0:ac8863619623 888 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
jhon309 0:ac8863619623 889 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
jhon309 0:ac8863619623 890 } SysTick_Type;
jhon309 0:ac8863619623 891
jhon309 0:ac8863619623 892 /* SysTick Control / Status Register Definitions */
jhon309 0:ac8863619623 893 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
jhon309 0:ac8863619623 894 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
jhon309 0:ac8863619623 895
jhon309 0:ac8863619623 896 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
jhon309 0:ac8863619623 897 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
jhon309 0:ac8863619623 898
jhon309 0:ac8863619623 899 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
jhon309 0:ac8863619623 900 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
jhon309 0:ac8863619623 901
jhon309 0:ac8863619623 902 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
jhon309 0:ac8863619623 903 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
jhon309 0:ac8863619623 904
jhon309 0:ac8863619623 905 /* SysTick Reload Register Definitions */
jhon309 0:ac8863619623 906 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
jhon309 0:ac8863619623 907 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
jhon309 0:ac8863619623 908
jhon309 0:ac8863619623 909 /* SysTick Current Register Definitions */
jhon309 0:ac8863619623 910 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
jhon309 0:ac8863619623 911 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
jhon309 0:ac8863619623 912
jhon309 0:ac8863619623 913 /* SysTick Calibration Register Definitions */
jhon309 0:ac8863619623 914 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
jhon309 0:ac8863619623 915 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
jhon309 0:ac8863619623 916
jhon309 0:ac8863619623 917 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
jhon309 0:ac8863619623 918 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
jhon309 0:ac8863619623 919
jhon309 0:ac8863619623 920 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
jhon309 0:ac8863619623 921 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
jhon309 0:ac8863619623 922
jhon309 0:ac8863619623 923 /*@} end of group CMSIS_SysTick */
jhon309 0:ac8863619623 924
jhon309 0:ac8863619623 925
jhon309 0:ac8863619623 926 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 927 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
jhon309 0:ac8863619623 928 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
jhon309 0:ac8863619623 929 @{
jhon309 0:ac8863619623 930 */
jhon309 0:ac8863619623 931
jhon309 0:ac8863619623 932 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
jhon309 0:ac8863619623 933 */
jhon309 0:ac8863619623 934 typedef struct
jhon309 0:ac8863619623 935 {
jhon309 0:ac8863619623 936 __O union
jhon309 0:ac8863619623 937 {
jhon309 0:ac8863619623 938 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
jhon309 0:ac8863619623 939 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
jhon309 0:ac8863619623 940 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
jhon309 0:ac8863619623 941 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
jhon309 0:ac8863619623 942 uint32_t RESERVED0[864];
jhon309 0:ac8863619623 943 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
jhon309 0:ac8863619623 944 uint32_t RESERVED1[15];
jhon309 0:ac8863619623 945 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
jhon309 0:ac8863619623 946 uint32_t RESERVED2[15];
jhon309 0:ac8863619623 947 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
jhon309 0:ac8863619623 948 uint32_t RESERVED3[29];
jhon309 0:ac8863619623 949 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
jhon309 0:ac8863619623 950 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
jhon309 0:ac8863619623 951 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
jhon309 0:ac8863619623 952 uint32_t RESERVED4[43];
jhon309 0:ac8863619623 953 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
jhon309 0:ac8863619623 954 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
jhon309 0:ac8863619623 955 uint32_t RESERVED5[6];
jhon309 0:ac8863619623 956 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
jhon309 0:ac8863619623 957 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
jhon309 0:ac8863619623 958 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
jhon309 0:ac8863619623 959 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
jhon309 0:ac8863619623 960 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
jhon309 0:ac8863619623 961 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
jhon309 0:ac8863619623 962 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
jhon309 0:ac8863619623 963 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
jhon309 0:ac8863619623 964 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
jhon309 0:ac8863619623 965 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
jhon309 0:ac8863619623 966 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
jhon309 0:ac8863619623 967 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
jhon309 0:ac8863619623 968 } ITM_Type;
jhon309 0:ac8863619623 969
jhon309 0:ac8863619623 970 /* ITM Trace Privilege Register Definitions */
jhon309 0:ac8863619623 971 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
jhon309 0:ac8863619623 972 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
jhon309 0:ac8863619623 973
jhon309 0:ac8863619623 974 /* ITM Trace Control Register Definitions */
jhon309 0:ac8863619623 975 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
jhon309 0:ac8863619623 976 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
jhon309 0:ac8863619623 977
jhon309 0:ac8863619623 978 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
jhon309 0:ac8863619623 979 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
jhon309 0:ac8863619623 980
jhon309 0:ac8863619623 981 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
jhon309 0:ac8863619623 982 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
jhon309 0:ac8863619623 983
jhon309 0:ac8863619623 984 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
jhon309 0:ac8863619623 985 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
jhon309 0:ac8863619623 986
jhon309 0:ac8863619623 987 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
jhon309 0:ac8863619623 988 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
jhon309 0:ac8863619623 989
jhon309 0:ac8863619623 990 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
jhon309 0:ac8863619623 991 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
jhon309 0:ac8863619623 992
jhon309 0:ac8863619623 993 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
jhon309 0:ac8863619623 994 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
jhon309 0:ac8863619623 995
jhon309 0:ac8863619623 996 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
jhon309 0:ac8863619623 997 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
jhon309 0:ac8863619623 998
jhon309 0:ac8863619623 999 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
jhon309 0:ac8863619623 1000 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
jhon309 0:ac8863619623 1001
jhon309 0:ac8863619623 1002 /* ITM Integration Write Register Definitions */
jhon309 0:ac8863619623 1003 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
jhon309 0:ac8863619623 1004 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
jhon309 0:ac8863619623 1005
jhon309 0:ac8863619623 1006 /* ITM Integration Read Register Definitions */
jhon309 0:ac8863619623 1007 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
jhon309 0:ac8863619623 1008 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
jhon309 0:ac8863619623 1009
jhon309 0:ac8863619623 1010 /* ITM Integration Mode Control Register Definitions */
jhon309 0:ac8863619623 1011 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
jhon309 0:ac8863619623 1012 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
jhon309 0:ac8863619623 1013
jhon309 0:ac8863619623 1014 /* ITM Lock Status Register Definitions */
jhon309 0:ac8863619623 1015 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
jhon309 0:ac8863619623 1016 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
jhon309 0:ac8863619623 1017
jhon309 0:ac8863619623 1018 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
jhon309 0:ac8863619623 1019 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
jhon309 0:ac8863619623 1020
jhon309 0:ac8863619623 1021 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
jhon309 0:ac8863619623 1022 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
jhon309 0:ac8863619623 1023
jhon309 0:ac8863619623 1024 /*@}*/ /* end of group CMSIS_ITM */
jhon309 0:ac8863619623 1025
jhon309 0:ac8863619623 1026
jhon309 0:ac8863619623 1027 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 1028 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
jhon309 0:ac8863619623 1029 \brief Type definitions for the Data Watchpoint and Trace (DWT)
jhon309 0:ac8863619623 1030 @{
jhon309 0:ac8863619623 1031 */
jhon309 0:ac8863619623 1032
jhon309 0:ac8863619623 1033 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
jhon309 0:ac8863619623 1034 */
jhon309 0:ac8863619623 1035 typedef struct
jhon309 0:ac8863619623 1036 {
jhon309 0:ac8863619623 1037 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
jhon309 0:ac8863619623 1038 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
jhon309 0:ac8863619623 1039 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
jhon309 0:ac8863619623 1040 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
jhon309 0:ac8863619623 1041 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
jhon309 0:ac8863619623 1042 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
jhon309 0:ac8863619623 1043 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
jhon309 0:ac8863619623 1044 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
jhon309 0:ac8863619623 1045 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
jhon309 0:ac8863619623 1046 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
jhon309 0:ac8863619623 1047 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
jhon309 0:ac8863619623 1048 uint32_t RESERVED0[1];
jhon309 0:ac8863619623 1049 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
jhon309 0:ac8863619623 1050 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
jhon309 0:ac8863619623 1051 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
jhon309 0:ac8863619623 1052 uint32_t RESERVED1[1];
jhon309 0:ac8863619623 1053 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
jhon309 0:ac8863619623 1054 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
jhon309 0:ac8863619623 1055 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
jhon309 0:ac8863619623 1056 uint32_t RESERVED2[1];
jhon309 0:ac8863619623 1057 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
jhon309 0:ac8863619623 1058 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
jhon309 0:ac8863619623 1059 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
jhon309 0:ac8863619623 1060 uint32_t RESERVED3[981];
jhon309 0:ac8863619623 1061 __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
jhon309 0:ac8863619623 1062 __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
jhon309 0:ac8863619623 1063 } DWT_Type;
jhon309 0:ac8863619623 1064
jhon309 0:ac8863619623 1065 /* DWT Control Register Definitions */
jhon309 0:ac8863619623 1066 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
jhon309 0:ac8863619623 1067 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
jhon309 0:ac8863619623 1068
jhon309 0:ac8863619623 1069 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
jhon309 0:ac8863619623 1070 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
jhon309 0:ac8863619623 1071
jhon309 0:ac8863619623 1072 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
jhon309 0:ac8863619623 1073 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
jhon309 0:ac8863619623 1074
jhon309 0:ac8863619623 1075 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
jhon309 0:ac8863619623 1076 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
jhon309 0:ac8863619623 1077
jhon309 0:ac8863619623 1078 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
jhon309 0:ac8863619623 1079 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
jhon309 0:ac8863619623 1080
jhon309 0:ac8863619623 1081 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
jhon309 0:ac8863619623 1082 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
jhon309 0:ac8863619623 1083
jhon309 0:ac8863619623 1084 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
jhon309 0:ac8863619623 1085 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
jhon309 0:ac8863619623 1086
jhon309 0:ac8863619623 1087 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
jhon309 0:ac8863619623 1088 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
jhon309 0:ac8863619623 1089
jhon309 0:ac8863619623 1090 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
jhon309 0:ac8863619623 1091 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
jhon309 0:ac8863619623 1092
jhon309 0:ac8863619623 1093 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
jhon309 0:ac8863619623 1094 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
jhon309 0:ac8863619623 1095
jhon309 0:ac8863619623 1096 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
jhon309 0:ac8863619623 1097 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
jhon309 0:ac8863619623 1098
jhon309 0:ac8863619623 1099 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
jhon309 0:ac8863619623 1100 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
jhon309 0:ac8863619623 1101
jhon309 0:ac8863619623 1102 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
jhon309 0:ac8863619623 1103 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
jhon309 0:ac8863619623 1104
jhon309 0:ac8863619623 1105 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
jhon309 0:ac8863619623 1106 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
jhon309 0:ac8863619623 1107
jhon309 0:ac8863619623 1108 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
jhon309 0:ac8863619623 1109 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
jhon309 0:ac8863619623 1110
jhon309 0:ac8863619623 1111 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
jhon309 0:ac8863619623 1112 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
jhon309 0:ac8863619623 1113
jhon309 0:ac8863619623 1114 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
jhon309 0:ac8863619623 1115 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
jhon309 0:ac8863619623 1116
jhon309 0:ac8863619623 1117 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
jhon309 0:ac8863619623 1118 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
jhon309 0:ac8863619623 1119
jhon309 0:ac8863619623 1120 /* DWT CPI Count Register Definitions */
jhon309 0:ac8863619623 1121 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
jhon309 0:ac8863619623 1122 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
jhon309 0:ac8863619623 1123
jhon309 0:ac8863619623 1124 /* DWT Exception Overhead Count Register Definitions */
jhon309 0:ac8863619623 1125 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
jhon309 0:ac8863619623 1126 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
jhon309 0:ac8863619623 1127
jhon309 0:ac8863619623 1128 /* DWT Sleep Count Register Definitions */
jhon309 0:ac8863619623 1129 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
jhon309 0:ac8863619623 1130 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
jhon309 0:ac8863619623 1131
jhon309 0:ac8863619623 1132 /* DWT LSU Count Register Definitions */
jhon309 0:ac8863619623 1133 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
jhon309 0:ac8863619623 1134 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
jhon309 0:ac8863619623 1135
jhon309 0:ac8863619623 1136 /* DWT Folded-instruction Count Register Definitions */
jhon309 0:ac8863619623 1137 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
jhon309 0:ac8863619623 1138 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
jhon309 0:ac8863619623 1139
jhon309 0:ac8863619623 1140 /* DWT Comparator Mask Register Definitions */
jhon309 0:ac8863619623 1141 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
jhon309 0:ac8863619623 1142 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
jhon309 0:ac8863619623 1143
jhon309 0:ac8863619623 1144 /* DWT Comparator Function Register Definitions */
jhon309 0:ac8863619623 1145 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
jhon309 0:ac8863619623 1146 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
jhon309 0:ac8863619623 1147
jhon309 0:ac8863619623 1148 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
jhon309 0:ac8863619623 1149 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
jhon309 0:ac8863619623 1150
jhon309 0:ac8863619623 1151 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
jhon309 0:ac8863619623 1152 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
jhon309 0:ac8863619623 1153
jhon309 0:ac8863619623 1154 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
jhon309 0:ac8863619623 1155 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
jhon309 0:ac8863619623 1156
jhon309 0:ac8863619623 1157 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
jhon309 0:ac8863619623 1158 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
jhon309 0:ac8863619623 1159
jhon309 0:ac8863619623 1160 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
jhon309 0:ac8863619623 1161 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
jhon309 0:ac8863619623 1162
jhon309 0:ac8863619623 1163 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
jhon309 0:ac8863619623 1164 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
jhon309 0:ac8863619623 1165
jhon309 0:ac8863619623 1166 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
jhon309 0:ac8863619623 1167 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
jhon309 0:ac8863619623 1168
jhon309 0:ac8863619623 1169 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
jhon309 0:ac8863619623 1170 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
jhon309 0:ac8863619623 1171
jhon309 0:ac8863619623 1172 /*@}*/ /* end of group CMSIS_DWT */
jhon309 0:ac8863619623 1173
jhon309 0:ac8863619623 1174
jhon309 0:ac8863619623 1175 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 1176 \defgroup CMSIS_TPI Trace Port Interface (TPI)
jhon309 0:ac8863619623 1177 \brief Type definitions for the Trace Port Interface (TPI)
jhon309 0:ac8863619623 1178 @{
jhon309 0:ac8863619623 1179 */
jhon309 0:ac8863619623 1180
jhon309 0:ac8863619623 1181 /** \brief Structure type to access the Trace Port Interface Register (TPI).
jhon309 0:ac8863619623 1182 */
jhon309 0:ac8863619623 1183 typedef struct
jhon309 0:ac8863619623 1184 {
jhon309 0:ac8863619623 1185 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
jhon309 0:ac8863619623 1186 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
jhon309 0:ac8863619623 1187 uint32_t RESERVED0[2];
jhon309 0:ac8863619623 1188 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
jhon309 0:ac8863619623 1189 uint32_t RESERVED1[55];
jhon309 0:ac8863619623 1190 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
jhon309 0:ac8863619623 1191 uint32_t RESERVED2[131];
jhon309 0:ac8863619623 1192 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
jhon309 0:ac8863619623 1193 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
jhon309 0:ac8863619623 1194 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
jhon309 0:ac8863619623 1195 uint32_t RESERVED3[759];
jhon309 0:ac8863619623 1196 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
jhon309 0:ac8863619623 1197 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
jhon309 0:ac8863619623 1198 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
jhon309 0:ac8863619623 1199 uint32_t RESERVED4[1];
jhon309 0:ac8863619623 1200 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
jhon309 0:ac8863619623 1201 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
jhon309 0:ac8863619623 1202 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
jhon309 0:ac8863619623 1203 uint32_t RESERVED5[39];
jhon309 0:ac8863619623 1204 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
jhon309 0:ac8863619623 1205 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
jhon309 0:ac8863619623 1206 uint32_t RESERVED7[8];
jhon309 0:ac8863619623 1207 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
jhon309 0:ac8863619623 1208 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
jhon309 0:ac8863619623 1209 } TPI_Type;
jhon309 0:ac8863619623 1210
jhon309 0:ac8863619623 1211 /* TPI Asynchronous Clock Prescaler Register Definitions */
jhon309 0:ac8863619623 1212 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
jhon309 0:ac8863619623 1213 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
jhon309 0:ac8863619623 1214
jhon309 0:ac8863619623 1215 /* TPI Selected Pin Protocol Register Definitions */
jhon309 0:ac8863619623 1216 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
jhon309 0:ac8863619623 1217 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
jhon309 0:ac8863619623 1218
jhon309 0:ac8863619623 1219 /* TPI Formatter and Flush Status Register Definitions */
jhon309 0:ac8863619623 1220 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
jhon309 0:ac8863619623 1221 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
jhon309 0:ac8863619623 1222
jhon309 0:ac8863619623 1223 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
jhon309 0:ac8863619623 1224 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
jhon309 0:ac8863619623 1225
jhon309 0:ac8863619623 1226 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
jhon309 0:ac8863619623 1227 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
jhon309 0:ac8863619623 1228
jhon309 0:ac8863619623 1229 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
jhon309 0:ac8863619623 1230 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
jhon309 0:ac8863619623 1231
jhon309 0:ac8863619623 1232 /* TPI Formatter and Flush Control Register Definitions */
jhon309 0:ac8863619623 1233 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
jhon309 0:ac8863619623 1234 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
jhon309 0:ac8863619623 1235
jhon309 0:ac8863619623 1236 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
jhon309 0:ac8863619623 1237 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
jhon309 0:ac8863619623 1238
jhon309 0:ac8863619623 1239 /* TPI TRIGGER Register Definitions */
jhon309 0:ac8863619623 1240 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
jhon309 0:ac8863619623 1241 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
jhon309 0:ac8863619623 1242
jhon309 0:ac8863619623 1243 /* TPI Integration ETM Data Register Definitions (FIFO0) */
jhon309 0:ac8863619623 1244 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
jhon309 0:ac8863619623 1245 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
jhon309 0:ac8863619623 1246
jhon309 0:ac8863619623 1247 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
jhon309 0:ac8863619623 1248 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
jhon309 0:ac8863619623 1249
jhon309 0:ac8863619623 1250 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
jhon309 0:ac8863619623 1251 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
jhon309 0:ac8863619623 1252
jhon309 0:ac8863619623 1253 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
jhon309 0:ac8863619623 1254 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
jhon309 0:ac8863619623 1255
jhon309 0:ac8863619623 1256 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
jhon309 0:ac8863619623 1257 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
jhon309 0:ac8863619623 1258
jhon309 0:ac8863619623 1259 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
jhon309 0:ac8863619623 1260 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
jhon309 0:ac8863619623 1261
jhon309 0:ac8863619623 1262 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
jhon309 0:ac8863619623 1263 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
jhon309 0:ac8863619623 1264
jhon309 0:ac8863619623 1265 /* TPI ITATBCTR2 Register Definitions */
jhon309 0:ac8863619623 1266 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
jhon309 0:ac8863619623 1267 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
jhon309 0:ac8863619623 1268
jhon309 0:ac8863619623 1269 /* TPI Integration ITM Data Register Definitions (FIFO1) */
jhon309 0:ac8863619623 1270 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
jhon309 0:ac8863619623 1271 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
jhon309 0:ac8863619623 1272
jhon309 0:ac8863619623 1273 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
jhon309 0:ac8863619623 1274 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
jhon309 0:ac8863619623 1275
jhon309 0:ac8863619623 1276 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
jhon309 0:ac8863619623 1277 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
jhon309 0:ac8863619623 1278
jhon309 0:ac8863619623 1279 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
jhon309 0:ac8863619623 1280 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
jhon309 0:ac8863619623 1281
jhon309 0:ac8863619623 1282 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
jhon309 0:ac8863619623 1283 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
jhon309 0:ac8863619623 1284
jhon309 0:ac8863619623 1285 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
jhon309 0:ac8863619623 1286 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
jhon309 0:ac8863619623 1287
jhon309 0:ac8863619623 1288 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
jhon309 0:ac8863619623 1289 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
jhon309 0:ac8863619623 1290
jhon309 0:ac8863619623 1291 /* TPI ITATBCTR0 Register Definitions */
jhon309 0:ac8863619623 1292 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
jhon309 0:ac8863619623 1293 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
jhon309 0:ac8863619623 1294
jhon309 0:ac8863619623 1295 /* TPI Integration Mode Control Register Definitions */
jhon309 0:ac8863619623 1296 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
jhon309 0:ac8863619623 1297 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
jhon309 0:ac8863619623 1298
jhon309 0:ac8863619623 1299 /* TPI DEVID Register Definitions */
jhon309 0:ac8863619623 1300 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
jhon309 0:ac8863619623 1301 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
jhon309 0:ac8863619623 1302
jhon309 0:ac8863619623 1303 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
jhon309 0:ac8863619623 1304 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
jhon309 0:ac8863619623 1305
jhon309 0:ac8863619623 1306 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
jhon309 0:ac8863619623 1307 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
jhon309 0:ac8863619623 1308
jhon309 0:ac8863619623 1309 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
jhon309 0:ac8863619623 1310 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
jhon309 0:ac8863619623 1311
jhon309 0:ac8863619623 1312 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
jhon309 0:ac8863619623 1313 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
jhon309 0:ac8863619623 1314
jhon309 0:ac8863619623 1315 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
jhon309 0:ac8863619623 1316 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
jhon309 0:ac8863619623 1317
jhon309 0:ac8863619623 1318 /* TPI DEVTYPE Register Definitions */
jhon309 0:ac8863619623 1319 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
jhon309 0:ac8863619623 1320 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
jhon309 0:ac8863619623 1321
jhon309 0:ac8863619623 1322 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
jhon309 0:ac8863619623 1323 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
jhon309 0:ac8863619623 1324
jhon309 0:ac8863619623 1325 /*@}*/ /* end of group CMSIS_TPI */
jhon309 0:ac8863619623 1326
jhon309 0:ac8863619623 1327
jhon309 0:ac8863619623 1328 #if (__MPU_PRESENT == 1)
jhon309 0:ac8863619623 1329 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 1330 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
jhon309 0:ac8863619623 1331 \brief Type definitions for the Memory Protection Unit (MPU)
jhon309 0:ac8863619623 1332 @{
jhon309 0:ac8863619623 1333 */
jhon309 0:ac8863619623 1334
jhon309 0:ac8863619623 1335 /** \brief Structure type to access the Memory Protection Unit (MPU).
jhon309 0:ac8863619623 1336 */
jhon309 0:ac8863619623 1337 typedef struct
jhon309 0:ac8863619623 1338 {
jhon309 0:ac8863619623 1339 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
jhon309 0:ac8863619623 1340 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
jhon309 0:ac8863619623 1341 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
jhon309 0:ac8863619623 1342 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
jhon309 0:ac8863619623 1343 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
jhon309 0:ac8863619623 1344 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
jhon309 0:ac8863619623 1345 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
jhon309 0:ac8863619623 1346 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
jhon309 0:ac8863619623 1347 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
jhon309 0:ac8863619623 1348 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
jhon309 0:ac8863619623 1349 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
jhon309 0:ac8863619623 1350 } MPU_Type;
jhon309 0:ac8863619623 1351
jhon309 0:ac8863619623 1352 /* MPU Type Register */
jhon309 0:ac8863619623 1353 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
jhon309 0:ac8863619623 1354 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
jhon309 0:ac8863619623 1355
jhon309 0:ac8863619623 1356 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
jhon309 0:ac8863619623 1357 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
jhon309 0:ac8863619623 1358
jhon309 0:ac8863619623 1359 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
jhon309 0:ac8863619623 1360 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
jhon309 0:ac8863619623 1361
jhon309 0:ac8863619623 1362 /* MPU Control Register */
jhon309 0:ac8863619623 1363 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
jhon309 0:ac8863619623 1364 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
jhon309 0:ac8863619623 1365
jhon309 0:ac8863619623 1366 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
jhon309 0:ac8863619623 1367 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
jhon309 0:ac8863619623 1368
jhon309 0:ac8863619623 1369 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
jhon309 0:ac8863619623 1370 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
jhon309 0:ac8863619623 1371
jhon309 0:ac8863619623 1372 /* MPU Region Number Register */
jhon309 0:ac8863619623 1373 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
jhon309 0:ac8863619623 1374 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
jhon309 0:ac8863619623 1375
jhon309 0:ac8863619623 1376 /* MPU Region Base Address Register */
jhon309 0:ac8863619623 1377 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
jhon309 0:ac8863619623 1378 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
jhon309 0:ac8863619623 1379
jhon309 0:ac8863619623 1380 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
jhon309 0:ac8863619623 1381 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
jhon309 0:ac8863619623 1382
jhon309 0:ac8863619623 1383 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
jhon309 0:ac8863619623 1384 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
jhon309 0:ac8863619623 1385
jhon309 0:ac8863619623 1386 /* MPU Region Attribute and Size Register */
jhon309 0:ac8863619623 1387 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
jhon309 0:ac8863619623 1388 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
jhon309 0:ac8863619623 1389
jhon309 0:ac8863619623 1390 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
jhon309 0:ac8863619623 1391 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
jhon309 0:ac8863619623 1392
jhon309 0:ac8863619623 1393 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
jhon309 0:ac8863619623 1394 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
jhon309 0:ac8863619623 1395
jhon309 0:ac8863619623 1396 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
jhon309 0:ac8863619623 1397 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
jhon309 0:ac8863619623 1398
jhon309 0:ac8863619623 1399 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
jhon309 0:ac8863619623 1400 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
jhon309 0:ac8863619623 1401
jhon309 0:ac8863619623 1402 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
jhon309 0:ac8863619623 1403 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
jhon309 0:ac8863619623 1404
jhon309 0:ac8863619623 1405 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
jhon309 0:ac8863619623 1406 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
jhon309 0:ac8863619623 1407
jhon309 0:ac8863619623 1408 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
jhon309 0:ac8863619623 1409 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
jhon309 0:ac8863619623 1410
jhon309 0:ac8863619623 1411 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
jhon309 0:ac8863619623 1412 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
jhon309 0:ac8863619623 1413
jhon309 0:ac8863619623 1414 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
jhon309 0:ac8863619623 1415 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
jhon309 0:ac8863619623 1416
jhon309 0:ac8863619623 1417 /*@} end of group CMSIS_MPU */
jhon309 0:ac8863619623 1418 #endif
jhon309 0:ac8863619623 1419
jhon309 0:ac8863619623 1420
jhon309 0:ac8863619623 1421 #if (__FPU_PRESENT == 1)
jhon309 0:ac8863619623 1422 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 1423 \defgroup CMSIS_FPU Floating Point Unit (FPU)
jhon309 0:ac8863619623 1424 \brief Type definitions for the Floating Point Unit (FPU)
jhon309 0:ac8863619623 1425 @{
jhon309 0:ac8863619623 1426 */
jhon309 0:ac8863619623 1427
jhon309 0:ac8863619623 1428 /** \brief Structure type to access the Floating Point Unit (FPU).
jhon309 0:ac8863619623 1429 */
jhon309 0:ac8863619623 1430 typedef struct
jhon309 0:ac8863619623 1431 {
jhon309 0:ac8863619623 1432 uint32_t RESERVED0[1];
jhon309 0:ac8863619623 1433 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
jhon309 0:ac8863619623 1434 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
jhon309 0:ac8863619623 1435 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
jhon309 0:ac8863619623 1436 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
jhon309 0:ac8863619623 1437 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
jhon309 0:ac8863619623 1438 __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
jhon309 0:ac8863619623 1439 } FPU_Type;
jhon309 0:ac8863619623 1440
jhon309 0:ac8863619623 1441 /* Floating-Point Context Control Register */
jhon309 0:ac8863619623 1442 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
jhon309 0:ac8863619623 1443 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
jhon309 0:ac8863619623 1444
jhon309 0:ac8863619623 1445 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
jhon309 0:ac8863619623 1446 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
jhon309 0:ac8863619623 1447
jhon309 0:ac8863619623 1448 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
jhon309 0:ac8863619623 1449 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
jhon309 0:ac8863619623 1450
jhon309 0:ac8863619623 1451 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
jhon309 0:ac8863619623 1452 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
jhon309 0:ac8863619623 1453
jhon309 0:ac8863619623 1454 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
jhon309 0:ac8863619623 1455 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
jhon309 0:ac8863619623 1456
jhon309 0:ac8863619623 1457 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
jhon309 0:ac8863619623 1458 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
jhon309 0:ac8863619623 1459
jhon309 0:ac8863619623 1460 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
jhon309 0:ac8863619623 1461 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
jhon309 0:ac8863619623 1462
jhon309 0:ac8863619623 1463 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
jhon309 0:ac8863619623 1464 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
jhon309 0:ac8863619623 1465
jhon309 0:ac8863619623 1466 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
jhon309 0:ac8863619623 1467 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
jhon309 0:ac8863619623 1468
jhon309 0:ac8863619623 1469 /* Floating-Point Context Address Register */
jhon309 0:ac8863619623 1470 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
jhon309 0:ac8863619623 1471 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
jhon309 0:ac8863619623 1472
jhon309 0:ac8863619623 1473 /* Floating-Point Default Status Control Register */
jhon309 0:ac8863619623 1474 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
jhon309 0:ac8863619623 1475 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
jhon309 0:ac8863619623 1476
jhon309 0:ac8863619623 1477 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
jhon309 0:ac8863619623 1478 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
jhon309 0:ac8863619623 1479
jhon309 0:ac8863619623 1480 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
jhon309 0:ac8863619623 1481 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
jhon309 0:ac8863619623 1482
jhon309 0:ac8863619623 1483 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
jhon309 0:ac8863619623 1484 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
jhon309 0:ac8863619623 1485
jhon309 0:ac8863619623 1486 /* Media and FP Feature Register 0 */
jhon309 0:ac8863619623 1487 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
jhon309 0:ac8863619623 1488 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
jhon309 0:ac8863619623 1489
jhon309 0:ac8863619623 1490 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
jhon309 0:ac8863619623 1491 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
jhon309 0:ac8863619623 1492
jhon309 0:ac8863619623 1493 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
jhon309 0:ac8863619623 1494 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
jhon309 0:ac8863619623 1495
jhon309 0:ac8863619623 1496 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
jhon309 0:ac8863619623 1497 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
jhon309 0:ac8863619623 1498
jhon309 0:ac8863619623 1499 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
jhon309 0:ac8863619623 1500 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
jhon309 0:ac8863619623 1501
jhon309 0:ac8863619623 1502 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
jhon309 0:ac8863619623 1503 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
jhon309 0:ac8863619623 1504
jhon309 0:ac8863619623 1505 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
jhon309 0:ac8863619623 1506 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
jhon309 0:ac8863619623 1507
jhon309 0:ac8863619623 1508 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
jhon309 0:ac8863619623 1509 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
jhon309 0:ac8863619623 1510
jhon309 0:ac8863619623 1511 /* Media and FP Feature Register 1 */
jhon309 0:ac8863619623 1512 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
jhon309 0:ac8863619623 1513 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
jhon309 0:ac8863619623 1514
jhon309 0:ac8863619623 1515 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
jhon309 0:ac8863619623 1516 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
jhon309 0:ac8863619623 1517
jhon309 0:ac8863619623 1518 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
jhon309 0:ac8863619623 1519 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
jhon309 0:ac8863619623 1520
jhon309 0:ac8863619623 1521 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
jhon309 0:ac8863619623 1522 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
jhon309 0:ac8863619623 1523
jhon309 0:ac8863619623 1524 /* Media and FP Feature Register 2 */
jhon309 0:ac8863619623 1525
jhon309 0:ac8863619623 1526 /*@} end of group CMSIS_FPU */
jhon309 0:ac8863619623 1527 #endif
jhon309 0:ac8863619623 1528
jhon309 0:ac8863619623 1529
jhon309 0:ac8863619623 1530 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 1531 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
jhon309 0:ac8863619623 1532 \brief Type definitions for the Core Debug Registers
jhon309 0:ac8863619623 1533 @{
jhon309 0:ac8863619623 1534 */
jhon309 0:ac8863619623 1535
jhon309 0:ac8863619623 1536 /** \brief Structure type to access the Core Debug Register (CoreDebug).
jhon309 0:ac8863619623 1537 */
jhon309 0:ac8863619623 1538 typedef struct
jhon309 0:ac8863619623 1539 {
jhon309 0:ac8863619623 1540 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
jhon309 0:ac8863619623 1541 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
jhon309 0:ac8863619623 1542 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
jhon309 0:ac8863619623 1543 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
jhon309 0:ac8863619623 1544 } CoreDebug_Type;
jhon309 0:ac8863619623 1545
jhon309 0:ac8863619623 1546 /* Debug Halting Control and Status Register */
jhon309 0:ac8863619623 1547 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
jhon309 0:ac8863619623 1548 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
jhon309 0:ac8863619623 1549
jhon309 0:ac8863619623 1550 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
jhon309 0:ac8863619623 1551 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
jhon309 0:ac8863619623 1552
jhon309 0:ac8863619623 1553 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
jhon309 0:ac8863619623 1554 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
jhon309 0:ac8863619623 1555
jhon309 0:ac8863619623 1556 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
jhon309 0:ac8863619623 1557 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
jhon309 0:ac8863619623 1558
jhon309 0:ac8863619623 1559 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
jhon309 0:ac8863619623 1560 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
jhon309 0:ac8863619623 1561
jhon309 0:ac8863619623 1562 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
jhon309 0:ac8863619623 1563 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
jhon309 0:ac8863619623 1564
jhon309 0:ac8863619623 1565 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
jhon309 0:ac8863619623 1566 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
jhon309 0:ac8863619623 1567
jhon309 0:ac8863619623 1568 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
jhon309 0:ac8863619623 1569 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
jhon309 0:ac8863619623 1570
jhon309 0:ac8863619623 1571 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
jhon309 0:ac8863619623 1572 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
jhon309 0:ac8863619623 1573
jhon309 0:ac8863619623 1574 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
jhon309 0:ac8863619623 1575 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
jhon309 0:ac8863619623 1576
jhon309 0:ac8863619623 1577 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
jhon309 0:ac8863619623 1578 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
jhon309 0:ac8863619623 1579
jhon309 0:ac8863619623 1580 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
jhon309 0:ac8863619623 1581 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
jhon309 0:ac8863619623 1582
jhon309 0:ac8863619623 1583 /* Debug Core Register Selector Register */
jhon309 0:ac8863619623 1584 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
jhon309 0:ac8863619623 1585 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
jhon309 0:ac8863619623 1586
jhon309 0:ac8863619623 1587 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
jhon309 0:ac8863619623 1588 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
jhon309 0:ac8863619623 1589
jhon309 0:ac8863619623 1590 /* Debug Exception and Monitor Control Register */
jhon309 0:ac8863619623 1591 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
jhon309 0:ac8863619623 1592 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
jhon309 0:ac8863619623 1593
jhon309 0:ac8863619623 1594 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
jhon309 0:ac8863619623 1595 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
jhon309 0:ac8863619623 1596
jhon309 0:ac8863619623 1597 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
jhon309 0:ac8863619623 1598 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
jhon309 0:ac8863619623 1599
jhon309 0:ac8863619623 1600 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
jhon309 0:ac8863619623 1601 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
jhon309 0:ac8863619623 1602
jhon309 0:ac8863619623 1603 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
jhon309 0:ac8863619623 1604 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
jhon309 0:ac8863619623 1605
jhon309 0:ac8863619623 1606 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
jhon309 0:ac8863619623 1607 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
jhon309 0:ac8863619623 1608
jhon309 0:ac8863619623 1609 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
jhon309 0:ac8863619623 1610 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
jhon309 0:ac8863619623 1611
jhon309 0:ac8863619623 1612 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
jhon309 0:ac8863619623 1613 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
jhon309 0:ac8863619623 1614
jhon309 0:ac8863619623 1615 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
jhon309 0:ac8863619623 1616 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
jhon309 0:ac8863619623 1617
jhon309 0:ac8863619623 1618 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
jhon309 0:ac8863619623 1619 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
jhon309 0:ac8863619623 1620
jhon309 0:ac8863619623 1621 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
jhon309 0:ac8863619623 1622 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
jhon309 0:ac8863619623 1623
jhon309 0:ac8863619623 1624 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
jhon309 0:ac8863619623 1625 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
jhon309 0:ac8863619623 1626
jhon309 0:ac8863619623 1627 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
jhon309 0:ac8863619623 1628 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
jhon309 0:ac8863619623 1629
jhon309 0:ac8863619623 1630 /*@} end of group CMSIS_CoreDebug */
jhon309 0:ac8863619623 1631
jhon309 0:ac8863619623 1632
jhon309 0:ac8863619623 1633 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 1634 \defgroup CMSIS_core_base Core Definitions
jhon309 0:ac8863619623 1635 \brief Definitions for base addresses, unions, and structures.
jhon309 0:ac8863619623 1636 @{
jhon309 0:ac8863619623 1637 */
jhon309 0:ac8863619623 1638
jhon309 0:ac8863619623 1639 /* Memory mapping of Cortex-M4 Hardware */
jhon309 0:ac8863619623 1640 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
jhon309 0:ac8863619623 1641 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
jhon309 0:ac8863619623 1642 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
jhon309 0:ac8863619623 1643 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
jhon309 0:ac8863619623 1644 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
jhon309 0:ac8863619623 1645 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
jhon309 0:ac8863619623 1646 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
jhon309 0:ac8863619623 1647 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
jhon309 0:ac8863619623 1648
jhon309 0:ac8863619623 1649 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
jhon309 0:ac8863619623 1650 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
jhon309 0:ac8863619623 1651 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
jhon309 0:ac8863619623 1652 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
jhon309 0:ac8863619623 1653 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
jhon309 0:ac8863619623 1654 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
jhon309 0:ac8863619623 1655 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
jhon309 0:ac8863619623 1656 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
jhon309 0:ac8863619623 1657
jhon309 0:ac8863619623 1658 #if (__MPU_PRESENT == 1)
jhon309 0:ac8863619623 1659 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
jhon309 0:ac8863619623 1660 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
jhon309 0:ac8863619623 1661 #endif
jhon309 0:ac8863619623 1662
jhon309 0:ac8863619623 1663 #if (__FPU_PRESENT == 1)
jhon309 0:ac8863619623 1664 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
jhon309 0:ac8863619623 1665 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
jhon309 0:ac8863619623 1666 #endif
jhon309 0:ac8863619623 1667
jhon309 0:ac8863619623 1668 /*@} */
jhon309 0:ac8863619623 1669
jhon309 0:ac8863619623 1670
jhon309 0:ac8863619623 1671
jhon309 0:ac8863619623 1672 /*******************************************************************************
jhon309 0:ac8863619623 1673 * Hardware Abstraction Layer
jhon309 0:ac8863619623 1674 Core Function Interface contains:
jhon309 0:ac8863619623 1675 - Core NVIC Functions
jhon309 0:ac8863619623 1676 - Core SysTick Functions
jhon309 0:ac8863619623 1677 - Core Debug Functions
jhon309 0:ac8863619623 1678 - Core Register Access Functions
jhon309 0:ac8863619623 1679 ******************************************************************************/
jhon309 0:ac8863619623 1680 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
jhon309 0:ac8863619623 1681 */
jhon309 0:ac8863619623 1682
jhon309 0:ac8863619623 1683
jhon309 0:ac8863619623 1684
jhon309 0:ac8863619623 1685 /* ########################## NVIC functions #################################### */
jhon309 0:ac8863619623 1686 /** \ingroup CMSIS_Core_FunctionInterface
jhon309 0:ac8863619623 1687 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
jhon309 0:ac8863619623 1688 \brief Functions that manage interrupts and exceptions via the NVIC.
jhon309 0:ac8863619623 1689 @{
jhon309 0:ac8863619623 1690 */
jhon309 0:ac8863619623 1691
jhon309 0:ac8863619623 1692 /** \brief Set Priority Grouping
jhon309 0:ac8863619623 1693
jhon309 0:ac8863619623 1694 The function sets the priority grouping field using the required unlock sequence.
jhon309 0:ac8863619623 1695 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
jhon309 0:ac8863619623 1696 Only values from 0..7 are used.
jhon309 0:ac8863619623 1697 In case of a conflict between priority grouping and available
jhon309 0:ac8863619623 1698 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
jhon309 0:ac8863619623 1699
jhon309 0:ac8863619623 1700 \param [in] PriorityGroup Priority grouping field.
jhon309 0:ac8863619623 1701 */
jhon309 0:ac8863619623 1702 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
jhon309 0:ac8863619623 1703 {
jhon309 0:ac8863619623 1704 uint32_t reg_value;
jhon309 0:ac8863619623 1705 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
jhon309 0:ac8863619623 1706
jhon309 0:ac8863619623 1707 reg_value = SCB->AIRCR; /* read old register configuration */
jhon309 0:ac8863619623 1708 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
jhon309 0:ac8863619623 1709 reg_value = (reg_value |
jhon309 0:ac8863619623 1710 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
jhon309 0:ac8863619623 1711 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
jhon309 0:ac8863619623 1712 SCB->AIRCR = reg_value;
jhon309 0:ac8863619623 1713 }
jhon309 0:ac8863619623 1714
jhon309 0:ac8863619623 1715
jhon309 0:ac8863619623 1716 /** \brief Get Priority Grouping
jhon309 0:ac8863619623 1717
jhon309 0:ac8863619623 1718 The function reads the priority grouping field from the NVIC Interrupt Controller.
jhon309 0:ac8863619623 1719
jhon309 0:ac8863619623 1720 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
jhon309 0:ac8863619623 1721 */
jhon309 0:ac8863619623 1722 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
jhon309 0:ac8863619623 1723 {
jhon309 0:ac8863619623 1724 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
jhon309 0:ac8863619623 1725 }
jhon309 0:ac8863619623 1726
jhon309 0:ac8863619623 1727
jhon309 0:ac8863619623 1728 /** \brief Enable External Interrupt
jhon309 0:ac8863619623 1729
jhon309 0:ac8863619623 1730 The function enables a device-specific interrupt in the NVIC interrupt controller.
jhon309 0:ac8863619623 1731
jhon309 0:ac8863619623 1732 \param [in] IRQn External interrupt number. Value cannot be negative.
jhon309 0:ac8863619623 1733 */
jhon309 0:ac8863619623 1734 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
jhon309 0:ac8863619623 1735 {
jhon309 0:ac8863619623 1736 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
jhon309 0:ac8863619623 1737 }
jhon309 0:ac8863619623 1738
jhon309 0:ac8863619623 1739
jhon309 0:ac8863619623 1740 /** \brief Disable External Interrupt
jhon309 0:ac8863619623 1741
jhon309 0:ac8863619623 1742 The function disables a device-specific interrupt in the NVIC interrupt controller.
jhon309 0:ac8863619623 1743
jhon309 0:ac8863619623 1744 \param [in] IRQn External interrupt number. Value cannot be negative.
jhon309 0:ac8863619623 1745 */
jhon309 0:ac8863619623 1746 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
jhon309 0:ac8863619623 1747 {
jhon309 0:ac8863619623 1748 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
jhon309 0:ac8863619623 1749 }
jhon309 0:ac8863619623 1750
jhon309 0:ac8863619623 1751
jhon309 0:ac8863619623 1752 /** \brief Get Pending Interrupt
jhon309 0:ac8863619623 1753
jhon309 0:ac8863619623 1754 The function reads the pending register in the NVIC and returns the pending bit
jhon309 0:ac8863619623 1755 for the specified interrupt.
jhon309 0:ac8863619623 1756
jhon309 0:ac8863619623 1757 \param [in] IRQn Interrupt number.
jhon309 0:ac8863619623 1758
jhon309 0:ac8863619623 1759 \return 0 Interrupt status is not pending.
jhon309 0:ac8863619623 1760 \return 1 Interrupt status is pending.
jhon309 0:ac8863619623 1761 */
jhon309 0:ac8863619623 1762 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
jhon309 0:ac8863619623 1763 {
jhon309 0:ac8863619623 1764 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
jhon309 0:ac8863619623 1765 }
jhon309 0:ac8863619623 1766
jhon309 0:ac8863619623 1767
jhon309 0:ac8863619623 1768 /** \brief Set Pending Interrupt
jhon309 0:ac8863619623 1769
jhon309 0:ac8863619623 1770 The function sets the pending bit of an external interrupt.
jhon309 0:ac8863619623 1771
jhon309 0:ac8863619623 1772 \param [in] IRQn Interrupt number. Value cannot be negative.
jhon309 0:ac8863619623 1773 */
jhon309 0:ac8863619623 1774 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
jhon309 0:ac8863619623 1775 {
jhon309 0:ac8863619623 1776 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
jhon309 0:ac8863619623 1777 }
jhon309 0:ac8863619623 1778
jhon309 0:ac8863619623 1779
jhon309 0:ac8863619623 1780 /** \brief Clear Pending Interrupt
jhon309 0:ac8863619623 1781
jhon309 0:ac8863619623 1782 The function clears the pending bit of an external interrupt.
jhon309 0:ac8863619623 1783
jhon309 0:ac8863619623 1784 \param [in] IRQn External interrupt number. Value cannot be negative.
jhon309 0:ac8863619623 1785 */
jhon309 0:ac8863619623 1786 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
jhon309 0:ac8863619623 1787 {
jhon309 0:ac8863619623 1788 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
jhon309 0:ac8863619623 1789 }
jhon309 0:ac8863619623 1790
jhon309 0:ac8863619623 1791
jhon309 0:ac8863619623 1792 /** \brief Get Active Interrupt
jhon309 0:ac8863619623 1793
jhon309 0:ac8863619623 1794 The function reads the active register in NVIC and returns the active bit.
jhon309 0:ac8863619623 1795
jhon309 0:ac8863619623 1796 \param [in] IRQn Interrupt number.
jhon309 0:ac8863619623 1797
jhon309 0:ac8863619623 1798 \return 0 Interrupt status is not active.
jhon309 0:ac8863619623 1799 \return 1 Interrupt status is active.
jhon309 0:ac8863619623 1800 */
jhon309 0:ac8863619623 1801 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
jhon309 0:ac8863619623 1802 {
jhon309 0:ac8863619623 1803 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
jhon309 0:ac8863619623 1804 }
jhon309 0:ac8863619623 1805
jhon309 0:ac8863619623 1806
jhon309 0:ac8863619623 1807 /** \brief Set Interrupt Priority
jhon309 0:ac8863619623 1808
jhon309 0:ac8863619623 1809 The function sets the priority of an interrupt.
jhon309 0:ac8863619623 1810
jhon309 0:ac8863619623 1811 \note The priority cannot be set for every core interrupt.
jhon309 0:ac8863619623 1812
jhon309 0:ac8863619623 1813 \param [in] IRQn Interrupt number.
jhon309 0:ac8863619623 1814 \param [in] priority Priority to set.
jhon309 0:ac8863619623 1815 */
jhon309 0:ac8863619623 1816 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
jhon309 0:ac8863619623 1817 {
jhon309 0:ac8863619623 1818 if((int32_t)IRQn < 0) {
jhon309 0:ac8863619623 1819 SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
jhon309 0:ac8863619623 1820 }
jhon309 0:ac8863619623 1821 else {
jhon309 0:ac8863619623 1822 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
jhon309 0:ac8863619623 1823 }
jhon309 0:ac8863619623 1824 }
jhon309 0:ac8863619623 1825
jhon309 0:ac8863619623 1826
jhon309 0:ac8863619623 1827 /** \brief Get Interrupt Priority
jhon309 0:ac8863619623 1828
jhon309 0:ac8863619623 1829 The function reads the priority of an interrupt. The interrupt
jhon309 0:ac8863619623 1830 number can be positive to specify an external (device specific)
jhon309 0:ac8863619623 1831 interrupt, or negative to specify an internal (core) interrupt.
jhon309 0:ac8863619623 1832
jhon309 0:ac8863619623 1833
jhon309 0:ac8863619623 1834 \param [in] IRQn Interrupt number.
jhon309 0:ac8863619623 1835 \return Interrupt Priority. Value is aligned automatically to the implemented
jhon309 0:ac8863619623 1836 priority bits of the microcontroller.
jhon309 0:ac8863619623 1837 */
jhon309 0:ac8863619623 1838 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
jhon309 0:ac8863619623 1839 {
jhon309 0:ac8863619623 1840
jhon309 0:ac8863619623 1841 if((int32_t)IRQn < 0) {
jhon309 0:ac8863619623 1842 return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
jhon309 0:ac8863619623 1843 }
jhon309 0:ac8863619623 1844 else {
jhon309 0:ac8863619623 1845 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
jhon309 0:ac8863619623 1846 }
jhon309 0:ac8863619623 1847 }
jhon309 0:ac8863619623 1848
jhon309 0:ac8863619623 1849
jhon309 0:ac8863619623 1850 /** \brief Encode Priority
jhon309 0:ac8863619623 1851
jhon309 0:ac8863619623 1852 The function encodes the priority for an interrupt with the given priority group,
jhon309 0:ac8863619623 1853 preemptive priority value, and subpriority value.
jhon309 0:ac8863619623 1854 In case of a conflict between priority grouping and available
jhon309 0:ac8863619623 1855 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
jhon309 0:ac8863619623 1856
jhon309 0:ac8863619623 1857 \param [in] PriorityGroup Used priority group.
jhon309 0:ac8863619623 1858 \param [in] PreemptPriority Preemptive priority value (starting from 0).
jhon309 0:ac8863619623 1859 \param [in] SubPriority Subpriority value (starting from 0).
jhon309 0:ac8863619623 1860 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
jhon309 0:ac8863619623 1861 */
jhon309 0:ac8863619623 1862 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
jhon309 0:ac8863619623 1863 {
jhon309 0:ac8863619623 1864 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
jhon309 0:ac8863619623 1865 uint32_t PreemptPriorityBits;
jhon309 0:ac8863619623 1866 uint32_t SubPriorityBits;
jhon309 0:ac8863619623 1867
jhon309 0:ac8863619623 1868 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
jhon309 0:ac8863619623 1869 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
jhon309 0:ac8863619623 1870
jhon309 0:ac8863619623 1871 return (
jhon309 0:ac8863619623 1872 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
jhon309 0:ac8863619623 1873 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
jhon309 0:ac8863619623 1874 );
jhon309 0:ac8863619623 1875 }
jhon309 0:ac8863619623 1876
jhon309 0:ac8863619623 1877
jhon309 0:ac8863619623 1878 /** \brief Decode Priority
jhon309 0:ac8863619623 1879
jhon309 0:ac8863619623 1880 The function decodes an interrupt priority value with a given priority group to
jhon309 0:ac8863619623 1881 preemptive priority value and subpriority value.
jhon309 0:ac8863619623 1882 In case of a conflict between priority grouping and available
jhon309 0:ac8863619623 1883 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
jhon309 0:ac8863619623 1884
jhon309 0:ac8863619623 1885 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
jhon309 0:ac8863619623 1886 \param [in] PriorityGroup Used priority group.
jhon309 0:ac8863619623 1887 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
jhon309 0:ac8863619623 1888 \param [out] pSubPriority Subpriority value (starting from 0).
jhon309 0:ac8863619623 1889 */
jhon309 0:ac8863619623 1890 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
jhon309 0:ac8863619623 1891 {
jhon309 0:ac8863619623 1892 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
jhon309 0:ac8863619623 1893 uint32_t PreemptPriorityBits;
jhon309 0:ac8863619623 1894 uint32_t SubPriorityBits;
jhon309 0:ac8863619623 1895
jhon309 0:ac8863619623 1896 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
jhon309 0:ac8863619623 1897 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
jhon309 0:ac8863619623 1898
jhon309 0:ac8863619623 1899 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
jhon309 0:ac8863619623 1900 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
jhon309 0:ac8863619623 1901 }
jhon309 0:ac8863619623 1902
jhon309 0:ac8863619623 1903
jhon309 0:ac8863619623 1904 /** \brief System Reset
jhon309 0:ac8863619623 1905
jhon309 0:ac8863619623 1906 The function initiates a system reset request to reset the MCU.
jhon309 0:ac8863619623 1907 */
jhon309 0:ac8863619623 1908 __STATIC_INLINE void NVIC_SystemReset(void)
jhon309 0:ac8863619623 1909 {
jhon309 0:ac8863619623 1910 __DSB(); /* Ensure all outstanding memory accesses included
jhon309 0:ac8863619623 1911 buffered write are completed before reset */
jhon309 0:ac8863619623 1912 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
jhon309 0:ac8863619623 1913 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
jhon309 0:ac8863619623 1914 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
jhon309 0:ac8863619623 1915 __DSB(); /* Ensure completion of memory access */
jhon309 0:ac8863619623 1916 while(1) { __NOP(); } /* wait until reset */
jhon309 0:ac8863619623 1917 }
jhon309 0:ac8863619623 1918
jhon309 0:ac8863619623 1919 /*@} end of CMSIS_Core_NVICFunctions */
jhon309 0:ac8863619623 1920
jhon309 0:ac8863619623 1921
jhon309 0:ac8863619623 1922 /* ########################## FPU functions #################################### */
jhon309 0:ac8863619623 1923 /** \ingroup CMSIS_Core_FunctionInterface
jhon309 0:ac8863619623 1924 \defgroup CMSIS_Core_FpuFunctions FPU Functions
jhon309 0:ac8863619623 1925 \brief Function that provides FPU type.
jhon309 0:ac8863619623 1926 @{
jhon309 0:ac8863619623 1927 */
jhon309 0:ac8863619623 1928
jhon309 0:ac8863619623 1929 /**
jhon309 0:ac8863619623 1930 \fn uint32_t SCB_GetFPUType(void)
jhon309 0:ac8863619623 1931 \brief get FPU type
jhon309 0:ac8863619623 1932 \returns
jhon309 0:ac8863619623 1933 - \b 0: No FPU
jhon309 0:ac8863619623 1934 - \b 1: Single precision FPU
jhon309 0:ac8863619623 1935 - \b 2: Double + Single precision FPU
jhon309 0:ac8863619623 1936 */
jhon309 0:ac8863619623 1937 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
jhon309 0:ac8863619623 1938 {
jhon309 0:ac8863619623 1939 uint32_t mvfr0;
jhon309 0:ac8863619623 1940
jhon309 0:ac8863619623 1941 mvfr0 = SCB->MVFR0;
jhon309 0:ac8863619623 1942 if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
jhon309 0:ac8863619623 1943 return 2UL; // Double + Single precision FPU
jhon309 0:ac8863619623 1944 } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
jhon309 0:ac8863619623 1945 return 1UL; // Single precision FPU
jhon309 0:ac8863619623 1946 } else {
jhon309 0:ac8863619623 1947 return 0UL; // No FPU
jhon309 0:ac8863619623 1948 }
jhon309 0:ac8863619623 1949 }
jhon309 0:ac8863619623 1950
jhon309 0:ac8863619623 1951
jhon309 0:ac8863619623 1952 /*@} end of CMSIS_Core_FpuFunctions */
jhon309 0:ac8863619623 1953
jhon309 0:ac8863619623 1954
jhon309 0:ac8863619623 1955
jhon309 0:ac8863619623 1956 /* ########################## Cache functions #################################### */
jhon309 0:ac8863619623 1957 /** \ingroup CMSIS_Core_FunctionInterface
jhon309 0:ac8863619623 1958 \defgroup CMSIS_Core_CacheFunctions Cache Functions
jhon309 0:ac8863619623 1959 \brief Functions that configure Instruction and Data cache.
jhon309 0:ac8863619623 1960 @{
jhon309 0:ac8863619623 1961 */
jhon309 0:ac8863619623 1962
jhon309 0:ac8863619623 1963 /* Cache Size ID Register Macros */
jhon309 0:ac8863619623 1964 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
jhon309 0:ac8863619623 1965 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
jhon309 0:ac8863619623 1966 #define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ )
jhon309 0:ac8863619623 1967
jhon309 0:ac8863619623 1968
jhon309 0:ac8863619623 1969 /** \brief Enable I-Cache
jhon309 0:ac8863619623 1970
jhon309 0:ac8863619623 1971 The function turns on I-Cache
jhon309 0:ac8863619623 1972 */
jhon309 0:ac8863619623 1973 __STATIC_INLINE void SCB_EnableICache (void)
jhon309 0:ac8863619623 1974 {
jhon309 0:ac8863619623 1975 #if (__ICACHE_PRESENT == 1)
jhon309 0:ac8863619623 1976 __DSB();
jhon309 0:ac8863619623 1977 __ISB();
jhon309 0:ac8863619623 1978 SCB->ICIALLU = 0UL; // invalidate I-Cache
jhon309 0:ac8863619623 1979 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
jhon309 0:ac8863619623 1980 __DSB();
jhon309 0:ac8863619623 1981 __ISB();
jhon309 0:ac8863619623 1982 #endif
jhon309 0:ac8863619623 1983 }
jhon309 0:ac8863619623 1984
jhon309 0:ac8863619623 1985
jhon309 0:ac8863619623 1986 /** \brief Disable I-Cache
jhon309 0:ac8863619623 1987
jhon309 0:ac8863619623 1988 The function turns off I-Cache
jhon309 0:ac8863619623 1989 */
jhon309 0:ac8863619623 1990 __STATIC_INLINE void SCB_DisableICache (void)
jhon309 0:ac8863619623 1991 {
jhon309 0:ac8863619623 1992 #if (__ICACHE_PRESENT == 1)
jhon309 0:ac8863619623 1993 __DSB();
jhon309 0:ac8863619623 1994 __ISB();
jhon309 0:ac8863619623 1995 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
jhon309 0:ac8863619623 1996 SCB->ICIALLU = 0UL; // invalidate I-Cache
jhon309 0:ac8863619623 1997 __DSB();
jhon309 0:ac8863619623 1998 __ISB();
jhon309 0:ac8863619623 1999 #endif
jhon309 0:ac8863619623 2000 }
jhon309 0:ac8863619623 2001
jhon309 0:ac8863619623 2002
jhon309 0:ac8863619623 2003 /** \brief Invalidate I-Cache
jhon309 0:ac8863619623 2004
jhon309 0:ac8863619623 2005 The function invalidates I-Cache
jhon309 0:ac8863619623 2006 */
jhon309 0:ac8863619623 2007 __STATIC_INLINE void SCB_InvalidateICache (void)
jhon309 0:ac8863619623 2008 {
jhon309 0:ac8863619623 2009 #if (__ICACHE_PRESENT == 1)
jhon309 0:ac8863619623 2010 __DSB();
jhon309 0:ac8863619623 2011 __ISB();
jhon309 0:ac8863619623 2012 SCB->ICIALLU = 0UL;
jhon309 0:ac8863619623 2013 __DSB();
jhon309 0:ac8863619623 2014 __ISB();
jhon309 0:ac8863619623 2015 #endif
jhon309 0:ac8863619623 2016 }
jhon309 0:ac8863619623 2017
jhon309 0:ac8863619623 2018
jhon309 0:ac8863619623 2019 /** \brief Enable D-Cache
jhon309 0:ac8863619623 2020
jhon309 0:ac8863619623 2021 The function turns on D-Cache
jhon309 0:ac8863619623 2022 */
jhon309 0:ac8863619623 2023 __STATIC_INLINE void SCB_EnableDCache (void)
jhon309 0:ac8863619623 2024 {
jhon309 0:ac8863619623 2025 #if (__DCACHE_PRESENT == 1)
jhon309 0:ac8863619623 2026 uint32_t ccsidr, sshift, wshift, sw;
jhon309 0:ac8863619623 2027 uint32_t sets, ways;
jhon309 0:ac8863619623 2028
jhon309 0:ac8863619623 2029 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
jhon309 0:ac8863619623 2030 ccsidr = SCB->CCSIDR;
jhon309 0:ac8863619623 2031 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
jhon309 0:ac8863619623 2032 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
jhon309 0:ac8863619623 2033 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
jhon309 0:ac8863619623 2034 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
jhon309 0:ac8863619623 2035
jhon309 0:ac8863619623 2036 __DSB();
jhon309 0:ac8863619623 2037
jhon309 0:ac8863619623 2038 do { // invalidate D-Cache
jhon309 0:ac8863619623 2039 uint32_t tmpways = ways;
jhon309 0:ac8863619623 2040 do {
jhon309 0:ac8863619623 2041 sw = ((tmpways << wshift) | (sets << sshift));
jhon309 0:ac8863619623 2042 SCB->DCISW = sw;
jhon309 0:ac8863619623 2043 } while(tmpways--);
jhon309 0:ac8863619623 2044 } while(sets--);
jhon309 0:ac8863619623 2045 __DSB();
jhon309 0:ac8863619623 2046
jhon309 0:ac8863619623 2047 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
jhon309 0:ac8863619623 2048
jhon309 0:ac8863619623 2049 __DSB();
jhon309 0:ac8863619623 2050 __ISB();
jhon309 0:ac8863619623 2051 #endif
jhon309 0:ac8863619623 2052 }
jhon309 0:ac8863619623 2053
jhon309 0:ac8863619623 2054
jhon309 0:ac8863619623 2055 /** \brief Disable D-Cache
jhon309 0:ac8863619623 2056
jhon309 0:ac8863619623 2057 The function turns off D-Cache
jhon309 0:ac8863619623 2058 */
jhon309 0:ac8863619623 2059 __STATIC_INLINE void SCB_DisableDCache (void)
jhon309 0:ac8863619623 2060 {
jhon309 0:ac8863619623 2061 #if (__DCACHE_PRESENT == 1)
jhon309 0:ac8863619623 2062 uint32_t ccsidr, sshift, wshift, sw;
jhon309 0:ac8863619623 2063 uint32_t sets, ways;
jhon309 0:ac8863619623 2064
jhon309 0:ac8863619623 2065 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
jhon309 0:ac8863619623 2066 ccsidr = SCB->CCSIDR;
jhon309 0:ac8863619623 2067 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
jhon309 0:ac8863619623 2068 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
jhon309 0:ac8863619623 2069 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
jhon309 0:ac8863619623 2070 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
jhon309 0:ac8863619623 2071
jhon309 0:ac8863619623 2072 __DSB();
jhon309 0:ac8863619623 2073
jhon309 0:ac8863619623 2074 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
jhon309 0:ac8863619623 2075
jhon309 0:ac8863619623 2076 do { // clean & invalidate D-Cache
jhon309 0:ac8863619623 2077 uint32_t tmpways = ways;
jhon309 0:ac8863619623 2078 do {
jhon309 0:ac8863619623 2079 sw = ((tmpways << wshift) | (sets << sshift));
jhon309 0:ac8863619623 2080 SCB->DCCISW = sw;
jhon309 0:ac8863619623 2081 } while(tmpways--);
jhon309 0:ac8863619623 2082 } while(sets--);
jhon309 0:ac8863619623 2083
jhon309 0:ac8863619623 2084
jhon309 0:ac8863619623 2085 __DSB();
jhon309 0:ac8863619623 2086 __ISB();
jhon309 0:ac8863619623 2087 #endif
jhon309 0:ac8863619623 2088 }
jhon309 0:ac8863619623 2089
jhon309 0:ac8863619623 2090
jhon309 0:ac8863619623 2091 /** \brief Invalidate D-Cache
jhon309 0:ac8863619623 2092
jhon309 0:ac8863619623 2093 The function invalidates D-Cache
jhon309 0:ac8863619623 2094 */
jhon309 0:ac8863619623 2095 __STATIC_INLINE void SCB_InvalidateDCache (void)
jhon309 0:ac8863619623 2096 {
jhon309 0:ac8863619623 2097 #if (__DCACHE_PRESENT == 1)
jhon309 0:ac8863619623 2098 uint32_t ccsidr, sshift, wshift, sw;
jhon309 0:ac8863619623 2099 uint32_t sets, ways;
jhon309 0:ac8863619623 2100
jhon309 0:ac8863619623 2101 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
jhon309 0:ac8863619623 2102 ccsidr = SCB->CCSIDR;
jhon309 0:ac8863619623 2103 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
jhon309 0:ac8863619623 2104 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
jhon309 0:ac8863619623 2105 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
jhon309 0:ac8863619623 2106 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
jhon309 0:ac8863619623 2107
jhon309 0:ac8863619623 2108 __DSB();
jhon309 0:ac8863619623 2109
jhon309 0:ac8863619623 2110 do { // invalidate D-Cache
jhon309 0:ac8863619623 2111 uint32_t tmpways = ways;
jhon309 0:ac8863619623 2112 do {
jhon309 0:ac8863619623 2113 sw = ((tmpways << wshift) | (sets << sshift));
jhon309 0:ac8863619623 2114 SCB->DCISW = sw;
jhon309 0:ac8863619623 2115 } while(tmpways--);
jhon309 0:ac8863619623 2116 } while(sets--);
jhon309 0:ac8863619623 2117
jhon309 0:ac8863619623 2118 __DSB();
jhon309 0:ac8863619623 2119 __ISB();
jhon309 0:ac8863619623 2120 #endif
jhon309 0:ac8863619623 2121 }
jhon309 0:ac8863619623 2122
jhon309 0:ac8863619623 2123
jhon309 0:ac8863619623 2124 /** \brief Clean D-Cache
jhon309 0:ac8863619623 2125
jhon309 0:ac8863619623 2126 The function cleans D-Cache
jhon309 0:ac8863619623 2127 */
jhon309 0:ac8863619623 2128 __STATIC_INLINE void SCB_CleanDCache (void)
jhon309 0:ac8863619623 2129 {
jhon309 0:ac8863619623 2130 #if (__DCACHE_PRESENT == 1)
jhon309 0:ac8863619623 2131 uint32_t ccsidr, sshift, wshift, sw;
jhon309 0:ac8863619623 2132 uint32_t sets, ways;
jhon309 0:ac8863619623 2133
jhon309 0:ac8863619623 2134 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
jhon309 0:ac8863619623 2135 ccsidr = SCB->CCSIDR;
jhon309 0:ac8863619623 2136 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
jhon309 0:ac8863619623 2137 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
jhon309 0:ac8863619623 2138 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
jhon309 0:ac8863619623 2139 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
jhon309 0:ac8863619623 2140
jhon309 0:ac8863619623 2141 __DSB();
jhon309 0:ac8863619623 2142
jhon309 0:ac8863619623 2143 do { // clean D-Cache
jhon309 0:ac8863619623 2144 uint32_t tmpways = ways;
jhon309 0:ac8863619623 2145 do {
jhon309 0:ac8863619623 2146 sw = ((tmpways << wshift) | (sets << sshift));
jhon309 0:ac8863619623 2147 SCB->DCCSW = sw;
jhon309 0:ac8863619623 2148 } while(tmpways--);
jhon309 0:ac8863619623 2149 } while(sets--);
jhon309 0:ac8863619623 2150
jhon309 0:ac8863619623 2151 __DSB();
jhon309 0:ac8863619623 2152 __ISB();
jhon309 0:ac8863619623 2153 #endif
jhon309 0:ac8863619623 2154 }
jhon309 0:ac8863619623 2155
jhon309 0:ac8863619623 2156
jhon309 0:ac8863619623 2157 /** \brief Clean & Invalidate D-Cache
jhon309 0:ac8863619623 2158
jhon309 0:ac8863619623 2159 The function cleans and Invalidates D-Cache
jhon309 0:ac8863619623 2160 */
jhon309 0:ac8863619623 2161 __STATIC_INLINE void SCB_CleanInvalidateDCache (void)
jhon309 0:ac8863619623 2162 {
jhon309 0:ac8863619623 2163 #if (__DCACHE_PRESENT == 1)
jhon309 0:ac8863619623 2164 uint32_t ccsidr, sshift, wshift, sw;
jhon309 0:ac8863619623 2165 uint32_t sets, ways;
jhon309 0:ac8863619623 2166
jhon309 0:ac8863619623 2167 SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
jhon309 0:ac8863619623 2168 ccsidr = SCB->CCSIDR;
jhon309 0:ac8863619623 2169 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
jhon309 0:ac8863619623 2170 sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
jhon309 0:ac8863619623 2171 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
jhon309 0:ac8863619623 2172 wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
jhon309 0:ac8863619623 2173
jhon309 0:ac8863619623 2174 __DSB();
jhon309 0:ac8863619623 2175
jhon309 0:ac8863619623 2176 do { // clean & invalidate D-Cache
jhon309 0:ac8863619623 2177 uint32_t tmpways = ways;
jhon309 0:ac8863619623 2178 do {
jhon309 0:ac8863619623 2179 sw = ((tmpways << wshift) | (sets << sshift));
jhon309 0:ac8863619623 2180 SCB->DCCISW = sw;
jhon309 0:ac8863619623 2181 } while(tmpways--);
jhon309 0:ac8863619623 2182 } while(sets--);
jhon309 0:ac8863619623 2183
jhon309 0:ac8863619623 2184 __DSB();
jhon309 0:ac8863619623 2185 __ISB();
jhon309 0:ac8863619623 2186 #endif
jhon309 0:ac8863619623 2187 }
jhon309 0:ac8863619623 2188
jhon309 0:ac8863619623 2189
jhon309 0:ac8863619623 2190 /**
jhon309 0:ac8863619623 2191 \fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
jhon309 0:ac8863619623 2192 \brief D-Cache Invalidate by address
jhon309 0:ac8863619623 2193 \param[in] addr address (aligned to 32-byte boundary)
jhon309 0:ac8863619623 2194 \param[in] dsize size of memory block (in number of bytes)
jhon309 0:ac8863619623 2195 */
jhon309 0:ac8863619623 2196 __STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
jhon309 0:ac8863619623 2197 {
jhon309 0:ac8863619623 2198 #if (__DCACHE_PRESENT == 1)
jhon309 0:ac8863619623 2199 int32_t op_size = dsize;
jhon309 0:ac8863619623 2200 uint32_t op_addr = (uint32_t)addr;
jhon309 0:ac8863619623 2201 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
jhon309 0:ac8863619623 2202
jhon309 0:ac8863619623 2203 __DSB();
jhon309 0:ac8863619623 2204
jhon309 0:ac8863619623 2205 while (op_size > 0) {
jhon309 0:ac8863619623 2206 SCB->DCIMVAC = op_addr;
jhon309 0:ac8863619623 2207 op_addr += linesize;
jhon309 0:ac8863619623 2208 op_size -= (int32_t)linesize;
jhon309 0:ac8863619623 2209 }
jhon309 0:ac8863619623 2210
jhon309 0:ac8863619623 2211 __DSB();
jhon309 0:ac8863619623 2212 __ISB();
jhon309 0:ac8863619623 2213 #endif
jhon309 0:ac8863619623 2214 }
jhon309 0:ac8863619623 2215
jhon309 0:ac8863619623 2216
jhon309 0:ac8863619623 2217 /**
jhon309 0:ac8863619623 2218 \fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
jhon309 0:ac8863619623 2219 \brief D-Cache Clean by address
jhon309 0:ac8863619623 2220 \param[in] addr address (aligned to 32-byte boundary)
jhon309 0:ac8863619623 2221 \param[in] dsize size of memory block (in number of bytes)
jhon309 0:ac8863619623 2222 */
jhon309 0:ac8863619623 2223 __STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
jhon309 0:ac8863619623 2224 {
jhon309 0:ac8863619623 2225 #if (__DCACHE_PRESENT == 1)
jhon309 0:ac8863619623 2226 int32_t op_size = dsize;
jhon309 0:ac8863619623 2227 uint32_t op_addr = (uint32_t) addr;
jhon309 0:ac8863619623 2228 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
jhon309 0:ac8863619623 2229
jhon309 0:ac8863619623 2230 __DSB();
jhon309 0:ac8863619623 2231
jhon309 0:ac8863619623 2232 while (op_size > 0) {
jhon309 0:ac8863619623 2233 SCB->DCCMVAC = op_addr;
jhon309 0:ac8863619623 2234 op_addr += linesize;
jhon309 0:ac8863619623 2235 op_size -= (int32_t)linesize;
jhon309 0:ac8863619623 2236 }
jhon309 0:ac8863619623 2237
jhon309 0:ac8863619623 2238 __DSB();
jhon309 0:ac8863619623 2239 __ISB();
jhon309 0:ac8863619623 2240 #endif
jhon309 0:ac8863619623 2241 }
jhon309 0:ac8863619623 2242
jhon309 0:ac8863619623 2243
jhon309 0:ac8863619623 2244 /**
jhon309 0:ac8863619623 2245 \fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
jhon309 0:ac8863619623 2246 \brief D-Cache Clean and Invalidate by address
jhon309 0:ac8863619623 2247 \param[in] addr address (aligned to 32-byte boundary)
jhon309 0:ac8863619623 2248 \param[in] dsize size of memory block (in number of bytes)
jhon309 0:ac8863619623 2249 */
jhon309 0:ac8863619623 2250 __STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
jhon309 0:ac8863619623 2251 {
jhon309 0:ac8863619623 2252 #if (__DCACHE_PRESENT == 1)
jhon309 0:ac8863619623 2253 int32_t op_size = dsize;
jhon309 0:ac8863619623 2254 uint32_t op_addr = (uint32_t) addr;
jhon309 0:ac8863619623 2255 uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
jhon309 0:ac8863619623 2256
jhon309 0:ac8863619623 2257 __DSB();
jhon309 0:ac8863619623 2258
jhon309 0:ac8863619623 2259 while (op_size > 0) {
jhon309 0:ac8863619623 2260 SCB->DCCIMVAC = op_addr;
jhon309 0:ac8863619623 2261 op_addr += linesize;
jhon309 0:ac8863619623 2262 op_size -= (int32_t)linesize;
jhon309 0:ac8863619623 2263 }
jhon309 0:ac8863619623 2264
jhon309 0:ac8863619623 2265 __DSB();
jhon309 0:ac8863619623 2266 __ISB();
jhon309 0:ac8863619623 2267 #endif
jhon309 0:ac8863619623 2268 }
jhon309 0:ac8863619623 2269
jhon309 0:ac8863619623 2270
jhon309 0:ac8863619623 2271 /*@} end of CMSIS_Core_CacheFunctions */
jhon309 0:ac8863619623 2272
jhon309 0:ac8863619623 2273
jhon309 0:ac8863619623 2274
jhon309 0:ac8863619623 2275 /* ################################## SysTick function ############################################ */
jhon309 0:ac8863619623 2276 /** \ingroup CMSIS_Core_FunctionInterface
jhon309 0:ac8863619623 2277 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
jhon309 0:ac8863619623 2278 \brief Functions that configure the System.
jhon309 0:ac8863619623 2279 @{
jhon309 0:ac8863619623 2280 */
jhon309 0:ac8863619623 2281
jhon309 0:ac8863619623 2282 #if (__Vendor_SysTickConfig == 0)
jhon309 0:ac8863619623 2283
jhon309 0:ac8863619623 2284 /** \brief System Tick Configuration
jhon309 0:ac8863619623 2285
jhon309 0:ac8863619623 2286 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
jhon309 0:ac8863619623 2287 Counter is in free running mode to generate periodic interrupts.
jhon309 0:ac8863619623 2288
jhon309 0:ac8863619623 2289 \param [in] ticks Number of ticks between two interrupts.
jhon309 0:ac8863619623 2290
jhon309 0:ac8863619623 2291 \return 0 Function succeeded.
jhon309 0:ac8863619623 2292 \return 1 Function failed.
jhon309 0:ac8863619623 2293
jhon309 0:ac8863619623 2294 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
jhon309 0:ac8863619623 2295 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
jhon309 0:ac8863619623 2296 must contain a vendor-specific implementation of this function.
jhon309 0:ac8863619623 2297
jhon309 0:ac8863619623 2298 */
jhon309 0:ac8863619623 2299 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
jhon309 0:ac8863619623 2300 {
jhon309 0:ac8863619623 2301 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
jhon309 0:ac8863619623 2302
jhon309 0:ac8863619623 2303 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
jhon309 0:ac8863619623 2304 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
jhon309 0:ac8863619623 2305 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
jhon309 0:ac8863619623 2306 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
jhon309 0:ac8863619623 2307 SysTick_CTRL_TICKINT_Msk |
jhon309 0:ac8863619623 2308 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
jhon309 0:ac8863619623 2309 return (0UL); /* Function successful */
jhon309 0:ac8863619623 2310 }
jhon309 0:ac8863619623 2311
jhon309 0:ac8863619623 2312 #endif
jhon309 0:ac8863619623 2313
jhon309 0:ac8863619623 2314 /*@} end of CMSIS_Core_SysTickFunctions */
jhon309 0:ac8863619623 2315
jhon309 0:ac8863619623 2316
jhon309 0:ac8863619623 2317
jhon309 0:ac8863619623 2318 /* ##################################### Debug In/Output function ########################################### */
jhon309 0:ac8863619623 2319 /** \ingroup CMSIS_Core_FunctionInterface
jhon309 0:ac8863619623 2320 \defgroup CMSIS_core_DebugFunctions ITM Functions
jhon309 0:ac8863619623 2321 \brief Functions that access the ITM debug interface.
jhon309 0:ac8863619623 2322 @{
jhon309 0:ac8863619623 2323 */
jhon309 0:ac8863619623 2324
jhon309 0:ac8863619623 2325 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
jhon309 0:ac8863619623 2326 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
jhon309 0:ac8863619623 2327
jhon309 0:ac8863619623 2328
jhon309 0:ac8863619623 2329 /** \brief ITM Send Character
jhon309 0:ac8863619623 2330
jhon309 0:ac8863619623 2331 The function transmits a character via the ITM channel 0, and
jhon309 0:ac8863619623 2332 \li Just returns when no debugger is connected that has booked the output.
jhon309 0:ac8863619623 2333 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
jhon309 0:ac8863619623 2334
jhon309 0:ac8863619623 2335 \param [in] ch Character to transmit.
jhon309 0:ac8863619623 2336
jhon309 0:ac8863619623 2337 \returns Character to transmit.
jhon309 0:ac8863619623 2338 */
jhon309 0:ac8863619623 2339 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
jhon309 0:ac8863619623 2340 {
jhon309 0:ac8863619623 2341 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
jhon309 0:ac8863619623 2342 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
jhon309 0:ac8863619623 2343 {
jhon309 0:ac8863619623 2344 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
jhon309 0:ac8863619623 2345 ITM->PORT[0].u8 = (uint8_t)ch;
jhon309 0:ac8863619623 2346 }
jhon309 0:ac8863619623 2347 return (ch);
jhon309 0:ac8863619623 2348 }
jhon309 0:ac8863619623 2349
jhon309 0:ac8863619623 2350
jhon309 0:ac8863619623 2351 /** \brief ITM Receive Character
jhon309 0:ac8863619623 2352
jhon309 0:ac8863619623 2353 The function inputs a character via the external variable \ref ITM_RxBuffer.
jhon309 0:ac8863619623 2354
jhon309 0:ac8863619623 2355 \return Received character.
jhon309 0:ac8863619623 2356 \return -1 No character pending.
jhon309 0:ac8863619623 2357 */
jhon309 0:ac8863619623 2358 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
jhon309 0:ac8863619623 2359 int32_t ch = -1; /* no character available */
jhon309 0:ac8863619623 2360
jhon309 0:ac8863619623 2361 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
jhon309 0:ac8863619623 2362 ch = ITM_RxBuffer;
jhon309 0:ac8863619623 2363 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
jhon309 0:ac8863619623 2364 }
jhon309 0:ac8863619623 2365
jhon309 0:ac8863619623 2366 return (ch);
jhon309 0:ac8863619623 2367 }
jhon309 0:ac8863619623 2368
jhon309 0:ac8863619623 2369
jhon309 0:ac8863619623 2370 /** \brief ITM Check Character
jhon309 0:ac8863619623 2371
jhon309 0:ac8863619623 2372 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
jhon309 0:ac8863619623 2373
jhon309 0:ac8863619623 2374 \return 0 No character available.
jhon309 0:ac8863619623 2375 \return 1 Character available.
jhon309 0:ac8863619623 2376 */
jhon309 0:ac8863619623 2377 __STATIC_INLINE int32_t ITM_CheckChar (void) {
jhon309 0:ac8863619623 2378
jhon309 0:ac8863619623 2379 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
jhon309 0:ac8863619623 2380 return (0); /* no character available */
jhon309 0:ac8863619623 2381 } else {
jhon309 0:ac8863619623 2382 return (1); /* character available */
jhon309 0:ac8863619623 2383 }
jhon309 0:ac8863619623 2384 }
jhon309 0:ac8863619623 2385
jhon309 0:ac8863619623 2386 /*@} end of CMSIS_core_DebugFunctions */
jhon309 0:ac8863619623 2387
jhon309 0:ac8863619623 2388
jhon309 0:ac8863619623 2389
jhon309 0:ac8863619623 2390
jhon309 0:ac8863619623 2391 #ifdef __cplusplus
jhon309 0:ac8863619623 2392 }
jhon309 0:ac8863619623 2393 #endif
jhon309 0:ac8863619623 2394
jhon309 0:ac8863619623 2395 #endif /* __CORE_CM7_H_DEPENDANT */
jhon309 0:ac8863619623 2396
jhon309 0:ac8863619623 2397 #endif /* __CMSIS_GENERIC */