Jhon Plantikow / I2C_EEPROM

I2C_EEPROM

TARGET_NUCLEO_F072RB/core_cm3.h@0:ac8863619623, 2015-08-13 (annotated)

Committer:
jhon309
Date:
Thu Aug 13 00:23:16 2015 +0000
Revision:
0:ac8863619623
I2C

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jhon309 0:ac8863619623 1 /**************************************************************************//**
jhon309 0:ac8863619623 2 * @file core_cm3.h
jhon309 0:ac8863619623 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
jhon309 0:ac8863619623 4 * @version V3.20
jhon309 0:ac8863619623 5 * @date 25. February 2013
jhon309 0:ac8863619623 6 *
jhon309 0:ac8863619623 7 * @note
jhon309 0:ac8863619623 8 *
jhon309 0:ac8863619623 9 ******************************************************************************/
jhon309 0:ac8863619623 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
jhon309 0:ac8863619623 11
jhon309 0:ac8863619623 12 All rights reserved.
jhon309 0:ac8863619623 13 Redistribution and use in source and binary forms, with or without
jhon309 0:ac8863619623 14 modification, are permitted provided that the following conditions are met:
jhon309 0:ac8863619623 15 - Redistributions of source code must retain the above copyright
jhon309 0:ac8863619623 16 notice, this list of conditions and the following disclaimer.
jhon309 0:ac8863619623 17 - Redistributions in binary form must reproduce the above copyright
jhon309 0:ac8863619623 18 notice, this list of conditions and the following disclaimer in the
jhon309 0:ac8863619623 19 documentation and/or other materials provided with the distribution.
jhon309 0:ac8863619623 20 - Neither the name of ARM nor the names of its contributors may be used
jhon309 0:ac8863619623 21 to endorse or promote products derived from this software without
jhon309 0:ac8863619623 22 specific prior written permission.
jhon309 0:ac8863619623 23 *
jhon309 0:ac8863619623 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jhon309 0:ac8863619623 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jhon309 0:ac8863619623 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
jhon309 0:ac8863619623 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
jhon309 0:ac8863619623 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
jhon309 0:ac8863619623 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
jhon309 0:ac8863619623 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
jhon309 0:ac8863619623 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
jhon309 0:ac8863619623 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
jhon309 0:ac8863619623 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
jhon309 0:ac8863619623 34 POSSIBILITY OF SUCH DAMAGE.
jhon309 0:ac8863619623 35 ---------------------------------------------------------------------------*/
jhon309 0:ac8863619623 36
jhon309 0:ac8863619623 37
jhon309 0:ac8863619623 38 #if defined ( __ICCARM__ )
jhon309 0:ac8863619623 39 #pragma system_include /* treat file as system include file for MISRA check */
jhon309 0:ac8863619623 40 #endif
jhon309 0:ac8863619623 41
jhon309 0:ac8863619623 42 #ifdef __cplusplus
jhon309 0:ac8863619623 43 extern "C" {
jhon309 0:ac8863619623 44 #endif
jhon309 0:ac8863619623 45
jhon309 0:ac8863619623 46 #ifndef __CORE_CM3_H_GENERIC
jhon309 0:ac8863619623 47 #define __CORE_CM3_H_GENERIC
jhon309 0:ac8863619623 48
jhon309 0:ac8863619623 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
jhon309 0:ac8863619623 50 CMSIS violates the following MISRA-C:2004 rules:
jhon309 0:ac8863619623 51
jhon309 0:ac8863619623 52 \li Required Rule 8.5, object/function definition in header file.<br>
jhon309 0:ac8863619623 53 Function definitions in header files are used to allow 'inlining'.
jhon309 0:ac8863619623 54
jhon309 0:ac8863619623 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
jhon309 0:ac8863619623 56 Unions are used for effective representation of core registers.
jhon309 0:ac8863619623 57
jhon309 0:ac8863619623 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
jhon309 0:ac8863619623 59 Function-like macros are used to allow more efficient code.
jhon309 0:ac8863619623 60 */
jhon309 0:ac8863619623 61
jhon309 0:ac8863619623 62
jhon309 0:ac8863619623 63 /*******************************************************************************
jhon309 0:ac8863619623 64 * CMSIS definitions
jhon309 0:ac8863619623 65 ******************************************************************************/
jhon309 0:ac8863619623 66 /** \ingroup Cortex_M3
jhon309 0:ac8863619623 67 @{
jhon309 0:ac8863619623 68 */
jhon309 0:ac8863619623 69
jhon309 0:ac8863619623 70 /* CMSIS CM3 definitions */
jhon309 0:ac8863619623 71 #define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
jhon309 0:ac8863619623 72 #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
jhon309 0:ac8863619623 73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
jhon309 0:ac8863619623 74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
jhon309 0:ac8863619623 75
jhon309 0:ac8863619623 76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
jhon309 0:ac8863619623 77
jhon309 0:ac8863619623 78
jhon309 0:ac8863619623 79 #if defined ( __CC_ARM )
jhon309 0:ac8863619623 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
jhon309 0:ac8863619623 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
jhon309 0:ac8863619623 82 #define __STATIC_INLINE static __inline
jhon309 0:ac8863619623 83
jhon309 0:ac8863619623 84 #elif defined ( __ICCARM__ )
jhon309 0:ac8863619623 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
jhon309 0:ac8863619623 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
jhon309 0:ac8863619623 87 #define __STATIC_INLINE static inline
jhon309 0:ac8863619623 88
jhon309 0:ac8863619623 89 #elif defined ( __TMS470__ )
jhon309 0:ac8863619623 90 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
jhon309 0:ac8863619623 91 #define __STATIC_INLINE static inline
jhon309 0:ac8863619623 92
jhon309 0:ac8863619623 93 #elif defined ( __GNUC__ )
jhon309 0:ac8863619623 94 #define __ASM __asm /*!< asm keyword for GNU Compiler */
jhon309 0:ac8863619623 95 #define __INLINE inline /*!< inline keyword for GNU Compiler */
jhon309 0:ac8863619623 96 #define __STATIC_INLINE static inline
jhon309 0:ac8863619623 97
jhon309 0:ac8863619623 98 #elif defined ( __TASKING__ )
jhon309 0:ac8863619623 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
jhon309 0:ac8863619623 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
jhon309 0:ac8863619623 101 #define __STATIC_INLINE static inline
jhon309 0:ac8863619623 102
jhon309 0:ac8863619623 103 #endif
jhon309 0:ac8863619623 104
jhon309 0:ac8863619623 105 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
jhon309 0:ac8863619623 106 */
jhon309 0:ac8863619623 107 #define __FPU_USED 0
jhon309 0:ac8863619623 108
jhon309 0:ac8863619623 109 #if defined ( __CC_ARM )
jhon309 0:ac8863619623 110 #if defined __TARGET_FPU_VFP
jhon309 0:ac8863619623 111 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:ac8863619623 112 #endif
jhon309 0:ac8863619623 113
jhon309 0:ac8863619623 114 #elif defined ( __ICCARM__ )
jhon309 0:ac8863619623 115 #if defined __ARMVFP__
jhon309 0:ac8863619623 116 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:ac8863619623 117 #endif
jhon309 0:ac8863619623 118
jhon309 0:ac8863619623 119 #elif defined ( __TMS470__ )
jhon309 0:ac8863619623 120 #if defined __TI__VFP_SUPPORT____
jhon309 0:ac8863619623 121 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:ac8863619623 122 #endif
jhon309 0:ac8863619623 123
jhon309 0:ac8863619623 124 #elif defined ( __GNUC__ )
jhon309 0:ac8863619623 125 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
jhon309 0:ac8863619623 126 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:ac8863619623 127 #endif
jhon309 0:ac8863619623 128
jhon309 0:ac8863619623 129 #elif defined ( __TASKING__ )
jhon309 0:ac8863619623 130 #if defined __FPU_VFP__
jhon309 0:ac8863619623 131 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:ac8863619623 132 #endif
jhon309 0:ac8863619623 133 #endif
jhon309 0:ac8863619623 134
jhon309 0:ac8863619623 135 #include <stdint.h> /* standard types definitions */
jhon309 0:ac8863619623 136 #include <core_cmInstr.h> /* Core Instruction Access */
jhon309 0:ac8863619623 137 #include <core_cmFunc.h> /* Core Function Access */
jhon309 0:ac8863619623 138
jhon309 0:ac8863619623 139 #endif /* __CORE_CM3_H_GENERIC */
jhon309 0:ac8863619623 140
jhon309 0:ac8863619623 141 #ifndef __CMSIS_GENERIC
jhon309 0:ac8863619623 142
jhon309 0:ac8863619623 143 #ifndef __CORE_CM3_H_DEPENDANT
jhon309 0:ac8863619623 144 #define __CORE_CM3_H_DEPENDANT
jhon309 0:ac8863619623 145
jhon309 0:ac8863619623 146 /* check device defines and use defaults */
jhon309 0:ac8863619623 147 #if defined __CHECK_DEVICE_DEFINES
jhon309 0:ac8863619623 148 #ifndef __CM3_REV
jhon309 0:ac8863619623 149 #define __CM3_REV 0x0200
jhon309 0:ac8863619623 150 #warning "__CM3_REV not defined in device header file; using default!"
jhon309 0:ac8863619623 151 #endif
jhon309 0:ac8863619623 152
jhon309 0:ac8863619623 153 #ifndef __MPU_PRESENT
jhon309 0:ac8863619623 154 #define __MPU_PRESENT 0
jhon309 0:ac8863619623 155 #warning "__MPU_PRESENT not defined in device header file; using default!"
jhon309 0:ac8863619623 156 #endif
jhon309 0:ac8863619623 157
jhon309 0:ac8863619623 158 #ifndef __NVIC_PRIO_BITS
jhon309 0:ac8863619623 159 #define __NVIC_PRIO_BITS 4
jhon309 0:ac8863619623 160 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
jhon309 0:ac8863619623 161 #endif
jhon309 0:ac8863619623 162
jhon309 0:ac8863619623 163 #ifndef __Vendor_SysTickConfig
jhon309 0:ac8863619623 164 #define __Vendor_SysTickConfig 0
jhon309 0:ac8863619623 165 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
jhon309 0:ac8863619623 166 #endif
jhon309 0:ac8863619623 167 #endif
jhon309 0:ac8863619623 168
jhon309 0:ac8863619623 169 /* IO definitions (access restrictions to peripheral registers) */
jhon309 0:ac8863619623 170 /**
jhon309 0:ac8863619623 171 \defgroup CMSIS_glob_defs CMSIS Global Defines
jhon309 0:ac8863619623 172
jhon309 0:ac8863619623 173 <strong>IO Type Qualifiers</strong> are used
jhon309 0:ac8863619623 174 \li to specify the access to peripheral variables.
jhon309 0:ac8863619623 175 \li for automatic generation of peripheral register debug information.
jhon309 0:ac8863619623 176 */
jhon309 0:ac8863619623 177 #ifdef __cplusplus
jhon309 0:ac8863619623 178 #define __I volatile /*!< Defines 'read only' permissions */
jhon309 0:ac8863619623 179 #else
jhon309 0:ac8863619623 180 #define __I volatile const /*!< Defines 'read only' permissions */
jhon309 0:ac8863619623 181 #endif
jhon309 0:ac8863619623 182 #define __O volatile /*!< Defines 'write only' permissions */
jhon309 0:ac8863619623 183 #define __IO volatile /*!< Defines 'read / write' permissions */
jhon309 0:ac8863619623 184
jhon309 0:ac8863619623 185 /*@} end of group Cortex_M3 */
jhon309 0:ac8863619623 186
jhon309 0:ac8863619623 187
jhon309 0:ac8863619623 188
jhon309 0:ac8863619623 189 /*******************************************************************************
jhon309 0:ac8863619623 190 * Register Abstraction
jhon309 0:ac8863619623 191 Core Register contain:
jhon309 0:ac8863619623 192 - Core Register
jhon309 0:ac8863619623 193 - Core NVIC Register
jhon309 0:ac8863619623 194 - Core SCB Register
jhon309 0:ac8863619623 195 - Core SysTick Register
jhon309 0:ac8863619623 196 - Core Debug Register
jhon309 0:ac8863619623 197 - Core MPU Register
jhon309 0:ac8863619623 198 ******************************************************************************/
jhon309 0:ac8863619623 199 /** \defgroup CMSIS_core_register Defines and Type Definitions
jhon309 0:ac8863619623 200 \brief Type definitions and defines for Cortex-M processor based devices.
jhon309 0:ac8863619623 201 */
jhon309 0:ac8863619623 202
jhon309 0:ac8863619623 203 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 204 \defgroup CMSIS_CORE Status and Control Registers
jhon309 0:ac8863619623 205 \brief Core Register type definitions.
jhon309 0:ac8863619623 206 @{
jhon309 0:ac8863619623 207 */
jhon309 0:ac8863619623 208
jhon309 0:ac8863619623 209 /** \brief Union type to access the Application Program Status Register (APSR).
jhon309 0:ac8863619623 210 */
jhon309 0:ac8863619623 211 typedef union
jhon309 0:ac8863619623 212 {
jhon309 0:ac8863619623 213 struct
jhon309 0:ac8863619623 214 {
jhon309 0:ac8863619623 215 #if (__CORTEX_M != 0x04)
jhon309 0:ac8863619623 216 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
jhon309 0:ac8863619623 217 #else
jhon309 0:ac8863619623 218 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
jhon309 0:ac8863619623 219 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
jhon309 0:ac8863619623 220 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
jhon309 0:ac8863619623 221 #endif
jhon309 0:ac8863619623 222 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
jhon309 0:ac8863619623 223 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
jhon309 0:ac8863619623 224 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
jhon309 0:ac8863619623 225 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
jhon309 0:ac8863619623 226 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
jhon309 0:ac8863619623 227 } b; /*!< Structure used for bit access */
jhon309 0:ac8863619623 228 uint32_t w; /*!< Type used for word access */
jhon309 0:ac8863619623 229 } APSR_Type;
jhon309 0:ac8863619623 230
jhon309 0:ac8863619623 231
jhon309 0:ac8863619623 232 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
jhon309 0:ac8863619623 233 */
jhon309 0:ac8863619623 234 typedef union
jhon309 0:ac8863619623 235 {
jhon309 0:ac8863619623 236 struct
jhon309 0:ac8863619623 237 {
jhon309 0:ac8863619623 238 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
jhon309 0:ac8863619623 239 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
jhon309 0:ac8863619623 240 } b; /*!< Structure used for bit access */
jhon309 0:ac8863619623 241 uint32_t w; /*!< Type used for word access */
jhon309 0:ac8863619623 242 } IPSR_Type;
jhon309 0:ac8863619623 243
jhon309 0:ac8863619623 244
jhon309 0:ac8863619623 245 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
jhon309 0:ac8863619623 246 */
jhon309 0:ac8863619623 247 typedef union
jhon309 0:ac8863619623 248 {
jhon309 0:ac8863619623 249 struct
jhon309 0:ac8863619623 250 {
jhon309 0:ac8863619623 251 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
jhon309 0:ac8863619623 252 #if (__CORTEX_M != 0x04)
jhon309 0:ac8863619623 253 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
jhon309 0:ac8863619623 254 #else
jhon309 0:ac8863619623 255 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
jhon309 0:ac8863619623 256 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
jhon309 0:ac8863619623 257 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
jhon309 0:ac8863619623 258 #endif
jhon309 0:ac8863619623 259 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
jhon309 0:ac8863619623 260 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
jhon309 0:ac8863619623 261 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
jhon309 0:ac8863619623 262 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
jhon309 0:ac8863619623 263 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
jhon309 0:ac8863619623 264 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
jhon309 0:ac8863619623 265 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
jhon309 0:ac8863619623 266 } b; /*!< Structure used for bit access */
jhon309 0:ac8863619623 267 uint32_t w; /*!< Type used for word access */
jhon309 0:ac8863619623 268 } xPSR_Type;
jhon309 0:ac8863619623 269
jhon309 0:ac8863619623 270
jhon309 0:ac8863619623 271 /** \brief Union type to access the Control Registers (CONTROL).
jhon309 0:ac8863619623 272 */
jhon309 0:ac8863619623 273 typedef union
jhon309 0:ac8863619623 274 {
jhon309 0:ac8863619623 275 struct
jhon309 0:ac8863619623 276 {
jhon309 0:ac8863619623 277 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
jhon309 0:ac8863619623 278 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
jhon309 0:ac8863619623 279 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
jhon309 0:ac8863619623 280 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
jhon309 0:ac8863619623 281 } b; /*!< Structure used for bit access */
jhon309 0:ac8863619623 282 uint32_t w; /*!< Type used for word access */
jhon309 0:ac8863619623 283 } CONTROL_Type;
jhon309 0:ac8863619623 284
jhon309 0:ac8863619623 285 /*@} end of group CMSIS_CORE */
jhon309 0:ac8863619623 286
jhon309 0:ac8863619623 287
jhon309 0:ac8863619623 288 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 289 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
jhon309 0:ac8863619623 290 \brief Type definitions for the NVIC Registers
jhon309 0:ac8863619623 291 @{
jhon309 0:ac8863619623 292 */
jhon309 0:ac8863619623 293
jhon309 0:ac8863619623 294 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
jhon309 0:ac8863619623 295 */
jhon309 0:ac8863619623 296 typedef struct
jhon309 0:ac8863619623 297 {
jhon309 0:ac8863619623 298 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
jhon309 0:ac8863619623 299 uint32_t RESERVED0[24];
jhon309 0:ac8863619623 300 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
jhon309 0:ac8863619623 301 uint32_t RSERVED1[24];
jhon309 0:ac8863619623 302 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
jhon309 0:ac8863619623 303 uint32_t RESERVED2[24];
jhon309 0:ac8863619623 304 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
jhon309 0:ac8863619623 305 uint32_t RESERVED3[24];
jhon309 0:ac8863619623 306 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
jhon309 0:ac8863619623 307 uint32_t RESERVED4[56];
jhon309 0:ac8863619623 308 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
jhon309 0:ac8863619623 309 uint32_t RESERVED5[644];
jhon309 0:ac8863619623 310 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
jhon309 0:ac8863619623 311 } NVIC_Type;
jhon309 0:ac8863619623 312
jhon309 0:ac8863619623 313 /* Software Triggered Interrupt Register Definitions */
jhon309 0:ac8863619623 314 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
jhon309 0:ac8863619623 315 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
jhon309 0:ac8863619623 316
jhon309 0:ac8863619623 317 /*@} end of group CMSIS_NVIC */
jhon309 0:ac8863619623 318
jhon309 0:ac8863619623 319
jhon309 0:ac8863619623 320 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 321 \defgroup CMSIS_SCB System Control Block (SCB)
jhon309 0:ac8863619623 322 \brief Type definitions for the System Control Block Registers
jhon309 0:ac8863619623 323 @{
jhon309 0:ac8863619623 324 */
jhon309 0:ac8863619623 325
jhon309 0:ac8863619623 326 /** \brief Structure type to access the System Control Block (SCB).
jhon309 0:ac8863619623 327 */
jhon309 0:ac8863619623 328 typedef struct
jhon309 0:ac8863619623 329 {
jhon309 0:ac8863619623 330 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
jhon309 0:ac8863619623 331 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
jhon309 0:ac8863619623 332 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
jhon309 0:ac8863619623 333 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
jhon309 0:ac8863619623 334 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
jhon309 0:ac8863619623 335 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
jhon309 0:ac8863619623 336 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
jhon309 0:ac8863619623 337 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
jhon309 0:ac8863619623 338 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
jhon309 0:ac8863619623 339 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
jhon309 0:ac8863619623 340 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
jhon309 0:ac8863619623 341 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
jhon309 0:ac8863619623 342 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
jhon309 0:ac8863619623 343 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
jhon309 0:ac8863619623 344 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
jhon309 0:ac8863619623 345 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
jhon309 0:ac8863619623 346 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
jhon309 0:ac8863619623 347 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
jhon309 0:ac8863619623 348 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
jhon309 0:ac8863619623 349 uint32_t RESERVED0[5];
jhon309 0:ac8863619623 350 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
jhon309 0:ac8863619623 351 } SCB_Type;
jhon309 0:ac8863619623 352
jhon309 0:ac8863619623 353 /* SCB CPUID Register Definitions */
jhon309 0:ac8863619623 354 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
jhon309 0:ac8863619623 355 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
jhon309 0:ac8863619623 356
jhon309 0:ac8863619623 357 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
jhon309 0:ac8863619623 358 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
jhon309 0:ac8863619623 359
jhon309 0:ac8863619623 360 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
jhon309 0:ac8863619623 361 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
jhon309 0:ac8863619623 362
jhon309 0:ac8863619623 363 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
jhon309 0:ac8863619623 364 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
jhon309 0:ac8863619623 365
jhon309 0:ac8863619623 366 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
jhon309 0:ac8863619623 367 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
jhon309 0:ac8863619623 368
jhon309 0:ac8863619623 369 /* SCB Interrupt Control State Register Definitions */
jhon309 0:ac8863619623 370 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
jhon309 0:ac8863619623 371 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
jhon309 0:ac8863619623 372
jhon309 0:ac8863619623 373 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
jhon309 0:ac8863619623 374 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
jhon309 0:ac8863619623 375
jhon309 0:ac8863619623 376 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
jhon309 0:ac8863619623 377 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
jhon309 0:ac8863619623 378
jhon309 0:ac8863619623 379 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
jhon309 0:ac8863619623 380 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
jhon309 0:ac8863619623 381
jhon309 0:ac8863619623 382 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
jhon309 0:ac8863619623 383 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
jhon309 0:ac8863619623 384
jhon309 0:ac8863619623 385 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
jhon309 0:ac8863619623 386 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
jhon309 0:ac8863619623 387
jhon309 0:ac8863619623 388 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
jhon309 0:ac8863619623 389 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
jhon309 0:ac8863619623 390
jhon309 0:ac8863619623 391 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
jhon309 0:ac8863619623 392 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
jhon309 0:ac8863619623 393
jhon309 0:ac8863619623 394 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
jhon309 0:ac8863619623 395 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
jhon309 0:ac8863619623 396
jhon309 0:ac8863619623 397 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
jhon309 0:ac8863619623 398 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
jhon309 0:ac8863619623 399
jhon309 0:ac8863619623 400 /* SCB Vector Table Offset Register Definitions */
jhon309 0:ac8863619623 401 #if (__CM3_REV < 0x0201) /* core r2p1 */
jhon309 0:ac8863619623 402 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
jhon309 0:ac8863619623 403 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
jhon309 0:ac8863619623 404
jhon309 0:ac8863619623 405 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
jhon309 0:ac8863619623 406 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
jhon309 0:ac8863619623 407 #else
jhon309 0:ac8863619623 408 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
jhon309 0:ac8863619623 409 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
jhon309 0:ac8863619623 410 #endif
jhon309 0:ac8863619623 411
jhon309 0:ac8863619623 412 /* SCB Application Interrupt and Reset Control Register Definitions */
jhon309 0:ac8863619623 413 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
jhon309 0:ac8863619623 414 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
jhon309 0:ac8863619623 415
jhon309 0:ac8863619623 416 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
jhon309 0:ac8863619623 417 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
jhon309 0:ac8863619623 418
jhon309 0:ac8863619623 419 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
jhon309 0:ac8863619623 420 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
jhon309 0:ac8863619623 421
jhon309 0:ac8863619623 422 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
jhon309 0:ac8863619623 423 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
jhon309 0:ac8863619623 424
jhon309 0:ac8863619623 425 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
jhon309 0:ac8863619623 426 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
jhon309 0:ac8863619623 427
jhon309 0:ac8863619623 428 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
jhon309 0:ac8863619623 429 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
jhon309 0:ac8863619623 430
jhon309 0:ac8863619623 431 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
jhon309 0:ac8863619623 432 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
jhon309 0:ac8863619623 433
jhon309 0:ac8863619623 434 /* SCB System Control Register Definitions */
jhon309 0:ac8863619623 435 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
jhon309 0:ac8863619623 436 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
jhon309 0:ac8863619623 437
jhon309 0:ac8863619623 438 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
jhon309 0:ac8863619623 439 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
jhon309 0:ac8863619623 440
jhon309 0:ac8863619623 441 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
jhon309 0:ac8863619623 442 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
jhon309 0:ac8863619623 443
jhon309 0:ac8863619623 444 /* SCB Configuration Control Register Definitions */
jhon309 0:ac8863619623 445 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
jhon309 0:ac8863619623 446 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
jhon309 0:ac8863619623 447
jhon309 0:ac8863619623 448 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
jhon309 0:ac8863619623 449 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
jhon309 0:ac8863619623 450
jhon309 0:ac8863619623 451 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
jhon309 0:ac8863619623 452 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
jhon309 0:ac8863619623 453
jhon309 0:ac8863619623 454 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
jhon309 0:ac8863619623 455 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
jhon309 0:ac8863619623 456
jhon309 0:ac8863619623 457 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
jhon309 0:ac8863619623 458 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
jhon309 0:ac8863619623 459
jhon309 0:ac8863619623 460 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
jhon309 0:ac8863619623 461 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
jhon309 0:ac8863619623 462
jhon309 0:ac8863619623 463 /* SCB System Handler Control and State Register Definitions */
jhon309 0:ac8863619623 464 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
jhon309 0:ac8863619623 465 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
jhon309 0:ac8863619623 466
jhon309 0:ac8863619623 467 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
jhon309 0:ac8863619623 468 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
jhon309 0:ac8863619623 469
jhon309 0:ac8863619623 470 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
jhon309 0:ac8863619623 471 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
jhon309 0:ac8863619623 472
jhon309 0:ac8863619623 473 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
jhon309 0:ac8863619623 474 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
jhon309 0:ac8863619623 475
jhon309 0:ac8863619623 476 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
jhon309 0:ac8863619623 477 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
jhon309 0:ac8863619623 478
jhon309 0:ac8863619623 479 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
jhon309 0:ac8863619623 480 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
jhon309 0:ac8863619623 481
jhon309 0:ac8863619623 482 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
jhon309 0:ac8863619623 483 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
jhon309 0:ac8863619623 484
jhon309 0:ac8863619623 485 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
jhon309 0:ac8863619623 486 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
jhon309 0:ac8863619623 487
jhon309 0:ac8863619623 488 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
jhon309 0:ac8863619623 489 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
jhon309 0:ac8863619623 490
jhon309 0:ac8863619623 491 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
jhon309 0:ac8863619623 492 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
jhon309 0:ac8863619623 493
jhon309 0:ac8863619623 494 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
jhon309 0:ac8863619623 495 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
jhon309 0:ac8863619623 496
jhon309 0:ac8863619623 497 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
jhon309 0:ac8863619623 498 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
jhon309 0:ac8863619623 499
jhon309 0:ac8863619623 500 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
jhon309 0:ac8863619623 501 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
jhon309 0:ac8863619623 502
jhon309 0:ac8863619623 503 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
jhon309 0:ac8863619623 504 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
jhon309 0:ac8863619623 505
jhon309 0:ac8863619623 506 /* SCB Configurable Fault Status Registers Definitions */
jhon309 0:ac8863619623 507 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
jhon309 0:ac8863619623 508 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
jhon309 0:ac8863619623 509
jhon309 0:ac8863619623 510 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
jhon309 0:ac8863619623 511 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
jhon309 0:ac8863619623 512
jhon309 0:ac8863619623 513 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
jhon309 0:ac8863619623 514 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
jhon309 0:ac8863619623 515
jhon309 0:ac8863619623 516 /* SCB Hard Fault Status Registers Definitions */
jhon309 0:ac8863619623 517 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
jhon309 0:ac8863619623 518 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
jhon309 0:ac8863619623 519
jhon309 0:ac8863619623 520 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
jhon309 0:ac8863619623 521 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
jhon309 0:ac8863619623 522
jhon309 0:ac8863619623 523 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
jhon309 0:ac8863619623 524 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
jhon309 0:ac8863619623 525
jhon309 0:ac8863619623 526 /* SCB Debug Fault Status Register Definitions */
jhon309 0:ac8863619623 527 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
jhon309 0:ac8863619623 528 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
jhon309 0:ac8863619623 529
jhon309 0:ac8863619623 530 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
jhon309 0:ac8863619623 531 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
jhon309 0:ac8863619623 532
jhon309 0:ac8863619623 533 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
jhon309 0:ac8863619623 534 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
jhon309 0:ac8863619623 535
jhon309 0:ac8863619623 536 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
jhon309 0:ac8863619623 537 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
jhon309 0:ac8863619623 538
jhon309 0:ac8863619623 539 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
jhon309 0:ac8863619623 540 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
jhon309 0:ac8863619623 541
jhon309 0:ac8863619623 542 /*@} end of group CMSIS_SCB */
jhon309 0:ac8863619623 543
jhon309 0:ac8863619623 544
jhon309 0:ac8863619623 545 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 546 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
jhon309 0:ac8863619623 547 \brief Type definitions for the System Control and ID Register not in the SCB
jhon309 0:ac8863619623 548 @{
jhon309 0:ac8863619623 549 */
jhon309 0:ac8863619623 550
jhon309 0:ac8863619623 551 /** \brief Structure type to access the System Control and ID Register not in the SCB.
jhon309 0:ac8863619623 552 */
jhon309 0:ac8863619623 553 typedef struct
jhon309 0:ac8863619623 554 {
jhon309 0:ac8863619623 555 uint32_t RESERVED0[1];
jhon309 0:ac8863619623 556 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
jhon309 0:ac8863619623 557 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
jhon309 0:ac8863619623 558 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
jhon309 0:ac8863619623 559 #else
jhon309 0:ac8863619623 560 uint32_t RESERVED1[1];
jhon309 0:ac8863619623 561 #endif
jhon309 0:ac8863619623 562 } SCnSCB_Type;
jhon309 0:ac8863619623 563
jhon309 0:ac8863619623 564 /* Interrupt Controller Type Register Definitions */
jhon309 0:ac8863619623 565 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
jhon309 0:ac8863619623 566 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
jhon309 0:ac8863619623 567
jhon309 0:ac8863619623 568 /* Auxiliary Control Register Definitions */
jhon309 0:ac8863619623 569
jhon309 0:ac8863619623 570 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
jhon309 0:ac8863619623 571 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
jhon309 0:ac8863619623 572
jhon309 0:ac8863619623 573 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
jhon309 0:ac8863619623 574 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
jhon309 0:ac8863619623 575
jhon309 0:ac8863619623 576 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
jhon309 0:ac8863619623 577 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
jhon309 0:ac8863619623 578
jhon309 0:ac8863619623 579 /*@} end of group CMSIS_SCnotSCB */
jhon309 0:ac8863619623 580
jhon309 0:ac8863619623 581
jhon309 0:ac8863619623 582 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 583 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
jhon309 0:ac8863619623 584 \brief Type definitions for the System Timer Registers.
jhon309 0:ac8863619623 585 @{
jhon309 0:ac8863619623 586 */
jhon309 0:ac8863619623 587
jhon309 0:ac8863619623 588 /** \brief Structure type to access the System Timer (SysTick).
jhon309 0:ac8863619623 589 */
jhon309 0:ac8863619623 590 typedef struct
jhon309 0:ac8863619623 591 {
jhon309 0:ac8863619623 592 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
jhon309 0:ac8863619623 593 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
jhon309 0:ac8863619623 594 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
jhon309 0:ac8863619623 595 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
jhon309 0:ac8863619623 596 } SysTick_Type;
jhon309 0:ac8863619623 597
jhon309 0:ac8863619623 598 /* SysTick Control / Status Register Definitions */
jhon309 0:ac8863619623 599 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
jhon309 0:ac8863619623 600 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
jhon309 0:ac8863619623 601
jhon309 0:ac8863619623 602 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
jhon309 0:ac8863619623 603 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
jhon309 0:ac8863619623 604
jhon309 0:ac8863619623 605 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
jhon309 0:ac8863619623 606 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
jhon309 0:ac8863619623 607
jhon309 0:ac8863619623 608 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
jhon309 0:ac8863619623 609 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
jhon309 0:ac8863619623 610
jhon309 0:ac8863619623 611 /* SysTick Reload Register Definitions */
jhon309 0:ac8863619623 612 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
jhon309 0:ac8863619623 613 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
jhon309 0:ac8863619623 614
jhon309 0:ac8863619623 615 /* SysTick Current Register Definitions */
jhon309 0:ac8863619623 616 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
jhon309 0:ac8863619623 617 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
jhon309 0:ac8863619623 618
jhon309 0:ac8863619623 619 /* SysTick Calibration Register Definitions */
jhon309 0:ac8863619623 620 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
jhon309 0:ac8863619623 621 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
jhon309 0:ac8863619623 622
jhon309 0:ac8863619623 623 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
jhon309 0:ac8863619623 624 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
jhon309 0:ac8863619623 625
jhon309 0:ac8863619623 626 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
jhon309 0:ac8863619623 627 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
jhon309 0:ac8863619623 628
jhon309 0:ac8863619623 629 /*@} end of group CMSIS_SysTick */
jhon309 0:ac8863619623 630
jhon309 0:ac8863619623 631
jhon309 0:ac8863619623 632 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 633 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
jhon309 0:ac8863619623 634 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
jhon309 0:ac8863619623 635 @{
jhon309 0:ac8863619623 636 */
jhon309 0:ac8863619623 637
jhon309 0:ac8863619623 638 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
jhon309 0:ac8863619623 639 */
jhon309 0:ac8863619623 640 typedef struct
jhon309 0:ac8863619623 641 {
jhon309 0:ac8863619623 642 __O union
jhon309 0:ac8863619623 643 {
jhon309 0:ac8863619623 644 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
jhon309 0:ac8863619623 645 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
jhon309 0:ac8863619623 646 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
jhon309 0:ac8863619623 647 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
jhon309 0:ac8863619623 648 uint32_t RESERVED0[864];
jhon309 0:ac8863619623 649 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
jhon309 0:ac8863619623 650 uint32_t RESERVED1[15];
jhon309 0:ac8863619623 651 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
jhon309 0:ac8863619623 652 uint32_t RESERVED2[15];
jhon309 0:ac8863619623 653 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
jhon309 0:ac8863619623 654 uint32_t RESERVED3[29];
jhon309 0:ac8863619623 655 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
jhon309 0:ac8863619623 656 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
jhon309 0:ac8863619623 657 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
jhon309 0:ac8863619623 658 uint32_t RESERVED4[43];
jhon309 0:ac8863619623 659 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
jhon309 0:ac8863619623 660 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
jhon309 0:ac8863619623 661 uint32_t RESERVED5[6];
jhon309 0:ac8863619623 662 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
jhon309 0:ac8863619623 663 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
jhon309 0:ac8863619623 664 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
jhon309 0:ac8863619623 665 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
jhon309 0:ac8863619623 666 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
jhon309 0:ac8863619623 667 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
jhon309 0:ac8863619623 668 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
jhon309 0:ac8863619623 669 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
jhon309 0:ac8863619623 670 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
jhon309 0:ac8863619623 671 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
jhon309 0:ac8863619623 672 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
jhon309 0:ac8863619623 673 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
jhon309 0:ac8863619623 674 } ITM_Type;
jhon309 0:ac8863619623 675
jhon309 0:ac8863619623 676 /* ITM Trace Privilege Register Definitions */
jhon309 0:ac8863619623 677 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
jhon309 0:ac8863619623 678 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
jhon309 0:ac8863619623 679
jhon309 0:ac8863619623 680 /* ITM Trace Control Register Definitions */
jhon309 0:ac8863619623 681 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
jhon309 0:ac8863619623 682 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
jhon309 0:ac8863619623 683
jhon309 0:ac8863619623 684 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
jhon309 0:ac8863619623 685 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
jhon309 0:ac8863619623 686
jhon309 0:ac8863619623 687 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
jhon309 0:ac8863619623 688 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
jhon309 0:ac8863619623 689
jhon309 0:ac8863619623 690 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
jhon309 0:ac8863619623 691 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
jhon309 0:ac8863619623 692
jhon309 0:ac8863619623 693 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
jhon309 0:ac8863619623 694 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
jhon309 0:ac8863619623 695
jhon309 0:ac8863619623 696 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
jhon309 0:ac8863619623 697 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
jhon309 0:ac8863619623 698
jhon309 0:ac8863619623 699 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
jhon309 0:ac8863619623 700 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
jhon309 0:ac8863619623 701
jhon309 0:ac8863619623 702 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
jhon309 0:ac8863619623 703 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
jhon309 0:ac8863619623 704
jhon309 0:ac8863619623 705 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
jhon309 0:ac8863619623 706 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
jhon309 0:ac8863619623 707
jhon309 0:ac8863619623 708 /* ITM Integration Write Register Definitions */
jhon309 0:ac8863619623 709 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
jhon309 0:ac8863619623 710 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
jhon309 0:ac8863619623 711
jhon309 0:ac8863619623 712 /* ITM Integration Read Register Definitions */
jhon309 0:ac8863619623 713 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
jhon309 0:ac8863619623 714 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
jhon309 0:ac8863619623 715
jhon309 0:ac8863619623 716 /* ITM Integration Mode Control Register Definitions */
jhon309 0:ac8863619623 717 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
jhon309 0:ac8863619623 718 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
jhon309 0:ac8863619623 719
jhon309 0:ac8863619623 720 /* ITM Lock Status Register Definitions */
jhon309 0:ac8863619623 721 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
jhon309 0:ac8863619623 722 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
jhon309 0:ac8863619623 723
jhon309 0:ac8863619623 724 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
jhon309 0:ac8863619623 725 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
jhon309 0:ac8863619623 726
jhon309 0:ac8863619623 727 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
jhon309 0:ac8863619623 728 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
jhon309 0:ac8863619623 729
jhon309 0:ac8863619623 730 /*@}*/ /* end of group CMSIS_ITM */
jhon309 0:ac8863619623 731
jhon309 0:ac8863619623 732
jhon309 0:ac8863619623 733 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 734 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
jhon309 0:ac8863619623 735 \brief Type definitions for the Data Watchpoint and Trace (DWT)
jhon309 0:ac8863619623 736 @{
jhon309 0:ac8863619623 737 */
jhon309 0:ac8863619623 738
jhon309 0:ac8863619623 739 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
jhon309 0:ac8863619623 740 */
jhon309 0:ac8863619623 741 typedef struct
jhon309 0:ac8863619623 742 {
jhon309 0:ac8863619623 743 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
jhon309 0:ac8863619623 744 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
jhon309 0:ac8863619623 745 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
jhon309 0:ac8863619623 746 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
jhon309 0:ac8863619623 747 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
jhon309 0:ac8863619623 748 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
jhon309 0:ac8863619623 749 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
jhon309 0:ac8863619623 750 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
jhon309 0:ac8863619623 751 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
jhon309 0:ac8863619623 752 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
jhon309 0:ac8863619623 753 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
jhon309 0:ac8863619623 754 uint32_t RESERVED0[1];
jhon309 0:ac8863619623 755 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
jhon309 0:ac8863619623 756 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
jhon309 0:ac8863619623 757 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
jhon309 0:ac8863619623 758 uint32_t RESERVED1[1];
jhon309 0:ac8863619623 759 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
jhon309 0:ac8863619623 760 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
jhon309 0:ac8863619623 761 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
jhon309 0:ac8863619623 762 uint32_t RESERVED2[1];
jhon309 0:ac8863619623 763 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
jhon309 0:ac8863619623 764 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
jhon309 0:ac8863619623 765 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
jhon309 0:ac8863619623 766 } DWT_Type;
jhon309 0:ac8863619623 767
jhon309 0:ac8863619623 768 /* DWT Control Register Definitions */
jhon309 0:ac8863619623 769 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
jhon309 0:ac8863619623 770 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
jhon309 0:ac8863619623 771
jhon309 0:ac8863619623 772 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
jhon309 0:ac8863619623 773 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
jhon309 0:ac8863619623 774
jhon309 0:ac8863619623 775 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
jhon309 0:ac8863619623 776 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
jhon309 0:ac8863619623 777
jhon309 0:ac8863619623 778 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
jhon309 0:ac8863619623 779 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
jhon309 0:ac8863619623 780
jhon309 0:ac8863619623 781 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
jhon309 0:ac8863619623 782 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
jhon309 0:ac8863619623 783
jhon309 0:ac8863619623 784 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
jhon309 0:ac8863619623 785 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
jhon309 0:ac8863619623 786
jhon309 0:ac8863619623 787 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
jhon309 0:ac8863619623 788 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
jhon309 0:ac8863619623 789
jhon309 0:ac8863619623 790 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
jhon309 0:ac8863619623 791 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
jhon309 0:ac8863619623 792
jhon309 0:ac8863619623 793 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
jhon309 0:ac8863619623 794 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
jhon309 0:ac8863619623 795
jhon309 0:ac8863619623 796 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
jhon309 0:ac8863619623 797 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
jhon309 0:ac8863619623 798
jhon309 0:ac8863619623 799 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
jhon309 0:ac8863619623 800 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
jhon309 0:ac8863619623 801
jhon309 0:ac8863619623 802 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
jhon309 0:ac8863619623 803 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
jhon309 0:ac8863619623 804
jhon309 0:ac8863619623 805 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
jhon309 0:ac8863619623 806 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
jhon309 0:ac8863619623 807
jhon309 0:ac8863619623 808 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
jhon309 0:ac8863619623 809 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
jhon309 0:ac8863619623 810
jhon309 0:ac8863619623 811 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
jhon309 0:ac8863619623 812 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
jhon309 0:ac8863619623 813
jhon309 0:ac8863619623 814 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
jhon309 0:ac8863619623 815 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
jhon309 0:ac8863619623 816
jhon309 0:ac8863619623 817 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
jhon309 0:ac8863619623 818 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
jhon309 0:ac8863619623 819
jhon309 0:ac8863619623 820 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
jhon309 0:ac8863619623 821 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
jhon309 0:ac8863619623 822
jhon309 0:ac8863619623 823 /* DWT CPI Count Register Definitions */
jhon309 0:ac8863619623 824 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
jhon309 0:ac8863619623 825 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
jhon309 0:ac8863619623 826
jhon309 0:ac8863619623 827 /* DWT Exception Overhead Count Register Definitions */
jhon309 0:ac8863619623 828 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
jhon309 0:ac8863619623 829 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
jhon309 0:ac8863619623 830
jhon309 0:ac8863619623 831 /* DWT Sleep Count Register Definitions */
jhon309 0:ac8863619623 832 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
jhon309 0:ac8863619623 833 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
jhon309 0:ac8863619623 834
jhon309 0:ac8863619623 835 /* DWT LSU Count Register Definitions */
jhon309 0:ac8863619623 836 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
jhon309 0:ac8863619623 837 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
jhon309 0:ac8863619623 838
jhon309 0:ac8863619623 839 /* DWT Folded-instruction Count Register Definitions */
jhon309 0:ac8863619623 840 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
jhon309 0:ac8863619623 841 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
jhon309 0:ac8863619623 842
jhon309 0:ac8863619623 843 /* DWT Comparator Mask Register Definitions */
jhon309 0:ac8863619623 844 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
jhon309 0:ac8863619623 845 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
jhon309 0:ac8863619623 846
jhon309 0:ac8863619623 847 /* DWT Comparator Function Register Definitions */
jhon309 0:ac8863619623 848 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
jhon309 0:ac8863619623 849 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
jhon309 0:ac8863619623 850
jhon309 0:ac8863619623 851 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
jhon309 0:ac8863619623 852 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
jhon309 0:ac8863619623 853
jhon309 0:ac8863619623 854 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
jhon309 0:ac8863619623 855 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
jhon309 0:ac8863619623 856
jhon309 0:ac8863619623 857 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
jhon309 0:ac8863619623 858 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
jhon309 0:ac8863619623 859
jhon309 0:ac8863619623 860 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
jhon309 0:ac8863619623 861 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
jhon309 0:ac8863619623 862
jhon309 0:ac8863619623 863 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
jhon309 0:ac8863619623 864 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
jhon309 0:ac8863619623 865
jhon309 0:ac8863619623 866 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
jhon309 0:ac8863619623 867 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
jhon309 0:ac8863619623 868
jhon309 0:ac8863619623 869 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
jhon309 0:ac8863619623 870 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
jhon309 0:ac8863619623 871
jhon309 0:ac8863619623 872 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
jhon309 0:ac8863619623 873 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
jhon309 0:ac8863619623 874
jhon309 0:ac8863619623 875 /*@}*/ /* end of group CMSIS_DWT */
jhon309 0:ac8863619623 876
jhon309 0:ac8863619623 877
jhon309 0:ac8863619623 878 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 879 \defgroup CMSIS_TPI Trace Port Interface (TPI)
jhon309 0:ac8863619623 880 \brief Type definitions for the Trace Port Interface (TPI)
jhon309 0:ac8863619623 881 @{
jhon309 0:ac8863619623 882 */
jhon309 0:ac8863619623 883
jhon309 0:ac8863619623 884 /** \brief Structure type to access the Trace Port Interface Register (TPI).
jhon309 0:ac8863619623 885 */
jhon309 0:ac8863619623 886 typedef struct
jhon309 0:ac8863619623 887 {
jhon309 0:ac8863619623 888 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
jhon309 0:ac8863619623 889 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
jhon309 0:ac8863619623 890 uint32_t RESERVED0[2];
jhon309 0:ac8863619623 891 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
jhon309 0:ac8863619623 892 uint32_t RESERVED1[55];
jhon309 0:ac8863619623 893 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
jhon309 0:ac8863619623 894 uint32_t RESERVED2[131];
jhon309 0:ac8863619623 895 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
jhon309 0:ac8863619623 896 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
jhon309 0:ac8863619623 897 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
jhon309 0:ac8863619623 898 uint32_t RESERVED3[759];
jhon309 0:ac8863619623 899 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
jhon309 0:ac8863619623 900 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
jhon309 0:ac8863619623 901 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
jhon309 0:ac8863619623 902 uint32_t RESERVED4[1];
jhon309 0:ac8863619623 903 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
jhon309 0:ac8863619623 904 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
jhon309 0:ac8863619623 905 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
jhon309 0:ac8863619623 906 uint32_t RESERVED5[39];
jhon309 0:ac8863619623 907 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
jhon309 0:ac8863619623 908 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
jhon309 0:ac8863619623 909 uint32_t RESERVED7[8];
jhon309 0:ac8863619623 910 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
jhon309 0:ac8863619623 911 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
jhon309 0:ac8863619623 912 } TPI_Type;
jhon309 0:ac8863619623 913
jhon309 0:ac8863619623 914 /* TPI Asynchronous Clock Prescaler Register Definitions */
jhon309 0:ac8863619623 915 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
jhon309 0:ac8863619623 916 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
jhon309 0:ac8863619623 917
jhon309 0:ac8863619623 918 /* TPI Selected Pin Protocol Register Definitions */
jhon309 0:ac8863619623 919 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
jhon309 0:ac8863619623 920 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
jhon309 0:ac8863619623 921
jhon309 0:ac8863619623 922 /* TPI Formatter and Flush Status Register Definitions */
jhon309 0:ac8863619623 923 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
jhon309 0:ac8863619623 924 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
jhon309 0:ac8863619623 925
jhon309 0:ac8863619623 926 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
jhon309 0:ac8863619623 927 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
jhon309 0:ac8863619623 928
jhon309 0:ac8863619623 929 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
jhon309 0:ac8863619623 930 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
jhon309 0:ac8863619623 931
jhon309 0:ac8863619623 932 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
jhon309 0:ac8863619623 933 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
jhon309 0:ac8863619623 934
jhon309 0:ac8863619623 935 /* TPI Formatter and Flush Control Register Definitions */
jhon309 0:ac8863619623 936 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
jhon309 0:ac8863619623 937 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
jhon309 0:ac8863619623 938
jhon309 0:ac8863619623 939 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
jhon309 0:ac8863619623 940 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
jhon309 0:ac8863619623 941
jhon309 0:ac8863619623 942 /* TPI TRIGGER Register Definitions */
jhon309 0:ac8863619623 943 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
jhon309 0:ac8863619623 944 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
jhon309 0:ac8863619623 945
jhon309 0:ac8863619623 946 /* TPI Integration ETM Data Register Definitions (FIFO0) */
jhon309 0:ac8863619623 947 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
jhon309 0:ac8863619623 948 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
jhon309 0:ac8863619623 949
jhon309 0:ac8863619623 950 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
jhon309 0:ac8863619623 951 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
jhon309 0:ac8863619623 952
jhon309 0:ac8863619623 953 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
jhon309 0:ac8863619623 954 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
jhon309 0:ac8863619623 955
jhon309 0:ac8863619623 956 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
jhon309 0:ac8863619623 957 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
jhon309 0:ac8863619623 958
jhon309 0:ac8863619623 959 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
jhon309 0:ac8863619623 960 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
jhon309 0:ac8863619623 961
jhon309 0:ac8863619623 962 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
jhon309 0:ac8863619623 963 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
jhon309 0:ac8863619623 964
jhon309 0:ac8863619623 965 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
jhon309 0:ac8863619623 966 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
jhon309 0:ac8863619623 967
jhon309 0:ac8863619623 968 /* TPI ITATBCTR2 Register Definitions */
jhon309 0:ac8863619623 969 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
jhon309 0:ac8863619623 970 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
jhon309 0:ac8863619623 971
jhon309 0:ac8863619623 972 /* TPI Integration ITM Data Register Definitions (FIFO1) */
jhon309 0:ac8863619623 973 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
jhon309 0:ac8863619623 974 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
jhon309 0:ac8863619623 975
jhon309 0:ac8863619623 976 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
jhon309 0:ac8863619623 977 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
jhon309 0:ac8863619623 978
jhon309 0:ac8863619623 979 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
jhon309 0:ac8863619623 980 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
jhon309 0:ac8863619623 981
jhon309 0:ac8863619623 982 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
jhon309 0:ac8863619623 983 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
jhon309 0:ac8863619623 984
jhon309 0:ac8863619623 985 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
jhon309 0:ac8863619623 986 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
jhon309 0:ac8863619623 987
jhon309 0:ac8863619623 988 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
jhon309 0:ac8863619623 989 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
jhon309 0:ac8863619623 990
jhon309 0:ac8863619623 991 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
jhon309 0:ac8863619623 992 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
jhon309 0:ac8863619623 993
jhon309 0:ac8863619623 994 /* TPI ITATBCTR0 Register Definitions */
jhon309 0:ac8863619623 995 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
jhon309 0:ac8863619623 996 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
jhon309 0:ac8863619623 997
jhon309 0:ac8863619623 998 /* TPI Integration Mode Control Register Definitions */
jhon309 0:ac8863619623 999 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
jhon309 0:ac8863619623 1000 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
jhon309 0:ac8863619623 1001
jhon309 0:ac8863619623 1002 /* TPI DEVID Register Definitions */
jhon309 0:ac8863619623 1003 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
jhon309 0:ac8863619623 1004 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
jhon309 0:ac8863619623 1005
jhon309 0:ac8863619623 1006 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
jhon309 0:ac8863619623 1007 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
jhon309 0:ac8863619623 1008
jhon309 0:ac8863619623 1009 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
jhon309 0:ac8863619623 1010 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
jhon309 0:ac8863619623 1011
jhon309 0:ac8863619623 1012 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
jhon309 0:ac8863619623 1013 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
jhon309 0:ac8863619623 1014
jhon309 0:ac8863619623 1015 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
jhon309 0:ac8863619623 1016 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
jhon309 0:ac8863619623 1017
jhon309 0:ac8863619623 1018 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
jhon309 0:ac8863619623 1019 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
jhon309 0:ac8863619623 1020
jhon309 0:ac8863619623 1021 /* TPI DEVTYPE Register Definitions */
jhon309 0:ac8863619623 1022 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
jhon309 0:ac8863619623 1023 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
jhon309 0:ac8863619623 1024
jhon309 0:ac8863619623 1025 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
jhon309 0:ac8863619623 1026 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
jhon309 0:ac8863619623 1027
jhon309 0:ac8863619623 1028 /*@}*/ /* end of group CMSIS_TPI */
jhon309 0:ac8863619623 1029
jhon309 0:ac8863619623 1030
jhon309 0:ac8863619623 1031 #if (__MPU_PRESENT == 1)
jhon309 0:ac8863619623 1032 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 1033 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
jhon309 0:ac8863619623 1034 \brief Type definitions for the Memory Protection Unit (MPU)
jhon309 0:ac8863619623 1035 @{
jhon309 0:ac8863619623 1036 */
jhon309 0:ac8863619623 1037
jhon309 0:ac8863619623 1038 /** \brief Structure type to access the Memory Protection Unit (MPU).
jhon309 0:ac8863619623 1039 */
jhon309 0:ac8863619623 1040 typedef struct
jhon309 0:ac8863619623 1041 {
jhon309 0:ac8863619623 1042 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
jhon309 0:ac8863619623 1043 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
jhon309 0:ac8863619623 1044 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
jhon309 0:ac8863619623 1045 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
jhon309 0:ac8863619623 1046 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
jhon309 0:ac8863619623 1047 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
jhon309 0:ac8863619623 1048 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
jhon309 0:ac8863619623 1049 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
jhon309 0:ac8863619623 1050 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
jhon309 0:ac8863619623 1051 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
jhon309 0:ac8863619623 1052 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
jhon309 0:ac8863619623 1053 } MPU_Type;
jhon309 0:ac8863619623 1054
jhon309 0:ac8863619623 1055 /* MPU Type Register */
jhon309 0:ac8863619623 1056 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
jhon309 0:ac8863619623 1057 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
jhon309 0:ac8863619623 1058
jhon309 0:ac8863619623 1059 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
jhon309 0:ac8863619623 1060 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
jhon309 0:ac8863619623 1061
jhon309 0:ac8863619623 1062 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
jhon309 0:ac8863619623 1063 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
jhon309 0:ac8863619623 1064
jhon309 0:ac8863619623 1065 /* MPU Control Register */
jhon309 0:ac8863619623 1066 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
jhon309 0:ac8863619623 1067 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
jhon309 0:ac8863619623 1068
jhon309 0:ac8863619623 1069 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
jhon309 0:ac8863619623 1070 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
jhon309 0:ac8863619623 1071
jhon309 0:ac8863619623 1072 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
jhon309 0:ac8863619623 1073 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
jhon309 0:ac8863619623 1074
jhon309 0:ac8863619623 1075 /* MPU Region Number Register */
jhon309 0:ac8863619623 1076 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
jhon309 0:ac8863619623 1077 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
jhon309 0:ac8863619623 1078
jhon309 0:ac8863619623 1079 /* MPU Region Base Address Register */
jhon309 0:ac8863619623 1080 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
jhon309 0:ac8863619623 1081 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
jhon309 0:ac8863619623 1082
jhon309 0:ac8863619623 1083 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
jhon309 0:ac8863619623 1084 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
jhon309 0:ac8863619623 1085
jhon309 0:ac8863619623 1086 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
jhon309 0:ac8863619623 1087 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
jhon309 0:ac8863619623 1088
jhon309 0:ac8863619623 1089 /* MPU Region Attribute and Size Register */
jhon309 0:ac8863619623 1090 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
jhon309 0:ac8863619623 1091 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
jhon309 0:ac8863619623 1092
jhon309 0:ac8863619623 1093 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
jhon309 0:ac8863619623 1094 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
jhon309 0:ac8863619623 1095
jhon309 0:ac8863619623 1096 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
jhon309 0:ac8863619623 1097 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
jhon309 0:ac8863619623 1098
jhon309 0:ac8863619623 1099 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
jhon309 0:ac8863619623 1100 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
jhon309 0:ac8863619623 1101
jhon309 0:ac8863619623 1102 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
jhon309 0:ac8863619623 1103 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
jhon309 0:ac8863619623 1104
jhon309 0:ac8863619623 1105 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
jhon309 0:ac8863619623 1106 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
jhon309 0:ac8863619623 1107
jhon309 0:ac8863619623 1108 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
jhon309 0:ac8863619623 1109 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
jhon309 0:ac8863619623 1110
jhon309 0:ac8863619623 1111 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
jhon309 0:ac8863619623 1112 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
jhon309 0:ac8863619623 1113
jhon309 0:ac8863619623 1114 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
jhon309 0:ac8863619623 1115 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
jhon309 0:ac8863619623 1116
jhon309 0:ac8863619623 1117 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
jhon309 0:ac8863619623 1118 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
jhon309 0:ac8863619623 1119
jhon309 0:ac8863619623 1120 /*@} end of group CMSIS_MPU */
jhon309 0:ac8863619623 1121 #endif
jhon309 0:ac8863619623 1122
jhon309 0:ac8863619623 1123
jhon309 0:ac8863619623 1124 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 1125 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
jhon309 0:ac8863619623 1126 \brief Type definitions for the Core Debug Registers
jhon309 0:ac8863619623 1127 @{
jhon309 0:ac8863619623 1128 */
jhon309 0:ac8863619623 1129
jhon309 0:ac8863619623 1130 /** \brief Structure type to access the Core Debug Register (CoreDebug).
jhon309 0:ac8863619623 1131 */
jhon309 0:ac8863619623 1132 typedef struct
jhon309 0:ac8863619623 1133 {
jhon309 0:ac8863619623 1134 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
jhon309 0:ac8863619623 1135 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
jhon309 0:ac8863619623 1136 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
jhon309 0:ac8863619623 1137 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
jhon309 0:ac8863619623 1138 } CoreDebug_Type;
jhon309 0:ac8863619623 1139
jhon309 0:ac8863619623 1140 /* Debug Halting Control and Status Register */
jhon309 0:ac8863619623 1141 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
jhon309 0:ac8863619623 1142 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
jhon309 0:ac8863619623 1143
jhon309 0:ac8863619623 1144 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
jhon309 0:ac8863619623 1145 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
jhon309 0:ac8863619623 1146
jhon309 0:ac8863619623 1147 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
jhon309 0:ac8863619623 1148 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
jhon309 0:ac8863619623 1149
jhon309 0:ac8863619623 1150 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
jhon309 0:ac8863619623 1151 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
jhon309 0:ac8863619623 1152
jhon309 0:ac8863619623 1153 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
jhon309 0:ac8863619623 1154 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
jhon309 0:ac8863619623 1155
jhon309 0:ac8863619623 1156 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
jhon309 0:ac8863619623 1157 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
jhon309 0:ac8863619623 1158
jhon309 0:ac8863619623 1159 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
jhon309 0:ac8863619623 1160 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
jhon309 0:ac8863619623 1161
jhon309 0:ac8863619623 1162 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
jhon309 0:ac8863619623 1163 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
jhon309 0:ac8863619623 1164
jhon309 0:ac8863619623 1165 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
jhon309 0:ac8863619623 1166 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
jhon309 0:ac8863619623 1167
jhon309 0:ac8863619623 1168 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
jhon309 0:ac8863619623 1169 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
jhon309 0:ac8863619623 1170
jhon309 0:ac8863619623 1171 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
jhon309 0:ac8863619623 1172 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
jhon309 0:ac8863619623 1173
jhon309 0:ac8863619623 1174 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
jhon309 0:ac8863619623 1175 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
jhon309 0:ac8863619623 1176
jhon309 0:ac8863619623 1177 /* Debug Core Register Selector Register */
jhon309 0:ac8863619623 1178 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
jhon309 0:ac8863619623 1179 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
jhon309 0:ac8863619623 1180
jhon309 0:ac8863619623 1181 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
jhon309 0:ac8863619623 1182 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
jhon309 0:ac8863619623 1183
jhon309 0:ac8863619623 1184 /* Debug Exception and Monitor Control Register */
jhon309 0:ac8863619623 1185 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
jhon309 0:ac8863619623 1186 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
jhon309 0:ac8863619623 1187
jhon309 0:ac8863619623 1188 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
jhon309 0:ac8863619623 1189 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
jhon309 0:ac8863619623 1190
jhon309 0:ac8863619623 1191 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
jhon309 0:ac8863619623 1192 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
jhon309 0:ac8863619623 1193
jhon309 0:ac8863619623 1194 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
jhon309 0:ac8863619623 1195 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
jhon309 0:ac8863619623 1196
jhon309 0:ac8863619623 1197 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
jhon309 0:ac8863619623 1198 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
jhon309 0:ac8863619623 1199
jhon309 0:ac8863619623 1200 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
jhon309 0:ac8863619623 1201 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
jhon309 0:ac8863619623 1202
jhon309 0:ac8863619623 1203 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
jhon309 0:ac8863619623 1204 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
jhon309 0:ac8863619623 1205
jhon309 0:ac8863619623 1206 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
jhon309 0:ac8863619623 1207 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
jhon309 0:ac8863619623 1208
jhon309 0:ac8863619623 1209 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
jhon309 0:ac8863619623 1210 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
jhon309 0:ac8863619623 1211
jhon309 0:ac8863619623 1212 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
jhon309 0:ac8863619623 1213 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
jhon309 0:ac8863619623 1214
jhon309 0:ac8863619623 1215 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
jhon309 0:ac8863619623 1216 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
jhon309 0:ac8863619623 1217
jhon309 0:ac8863619623 1218 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
jhon309 0:ac8863619623 1219 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
jhon309 0:ac8863619623 1220
jhon309 0:ac8863619623 1221 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
jhon309 0:ac8863619623 1222 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
jhon309 0:ac8863619623 1223
jhon309 0:ac8863619623 1224 /*@} end of group CMSIS_CoreDebug */
jhon309 0:ac8863619623 1225
jhon309 0:ac8863619623 1226
jhon309 0:ac8863619623 1227 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 1228 \defgroup CMSIS_core_base Core Definitions
jhon309 0:ac8863619623 1229 \brief Definitions for base addresses, unions, and structures.
jhon309 0:ac8863619623 1230 @{
jhon309 0:ac8863619623 1231 */
jhon309 0:ac8863619623 1232
jhon309 0:ac8863619623 1233 /* Memory mapping of Cortex-M3 Hardware */
jhon309 0:ac8863619623 1234 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
jhon309 0:ac8863619623 1235 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
jhon309 0:ac8863619623 1236 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
jhon309 0:ac8863619623 1237 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
jhon309 0:ac8863619623 1238 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
jhon309 0:ac8863619623 1239 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
jhon309 0:ac8863619623 1240 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
jhon309 0:ac8863619623 1241 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
jhon309 0:ac8863619623 1242
jhon309 0:ac8863619623 1243 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
jhon309 0:ac8863619623 1244 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
jhon309 0:ac8863619623 1245 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
jhon309 0:ac8863619623 1246 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
jhon309 0:ac8863619623 1247 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
jhon309 0:ac8863619623 1248 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
jhon309 0:ac8863619623 1249 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
jhon309 0:ac8863619623 1250 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
jhon309 0:ac8863619623 1251
jhon309 0:ac8863619623 1252 #if (__MPU_PRESENT == 1)
jhon309 0:ac8863619623 1253 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
jhon309 0:ac8863619623 1254 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
jhon309 0:ac8863619623 1255 #endif
jhon309 0:ac8863619623 1256
jhon309 0:ac8863619623 1257 /*@} */
jhon309 0:ac8863619623 1258
jhon309 0:ac8863619623 1259
jhon309 0:ac8863619623 1260
jhon309 0:ac8863619623 1261 /*******************************************************************************
jhon309 0:ac8863619623 1262 * Hardware Abstraction Layer
jhon309 0:ac8863619623 1263 Core Function Interface contains:
jhon309 0:ac8863619623 1264 - Core NVIC Functions
jhon309 0:ac8863619623 1265 - Core SysTick Functions
jhon309 0:ac8863619623 1266 - Core Debug Functions
jhon309 0:ac8863619623 1267 - Core Register Access Functions
jhon309 0:ac8863619623 1268 ******************************************************************************/
jhon309 0:ac8863619623 1269 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
jhon309 0:ac8863619623 1270 */
jhon309 0:ac8863619623 1271
jhon309 0:ac8863619623 1272
jhon309 0:ac8863619623 1273
jhon309 0:ac8863619623 1274 /* ########################## NVIC functions #################################### */
jhon309 0:ac8863619623 1275 /** \ingroup CMSIS_Core_FunctionInterface
jhon309 0:ac8863619623 1276 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
jhon309 0:ac8863619623 1277 \brief Functions that manage interrupts and exceptions via the NVIC.
jhon309 0:ac8863619623 1278 @{
jhon309 0:ac8863619623 1279 */
jhon309 0:ac8863619623 1280
jhon309 0:ac8863619623 1281 /** \brief Set Priority Grouping
jhon309 0:ac8863619623 1282
jhon309 0:ac8863619623 1283 The function sets the priority grouping field using the required unlock sequence.
jhon309 0:ac8863619623 1284 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
jhon309 0:ac8863619623 1285 Only values from 0..7 are used.
jhon309 0:ac8863619623 1286 In case of a conflict between priority grouping and available
jhon309 0:ac8863619623 1287 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
jhon309 0:ac8863619623 1288
jhon309 0:ac8863619623 1289 \param [in] PriorityGroup Priority grouping field.
jhon309 0:ac8863619623 1290 */
jhon309 0:ac8863619623 1291 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
jhon309 0:ac8863619623 1292 {
jhon309 0:ac8863619623 1293 uint32_t reg_value;
jhon309 0:ac8863619623 1294 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
jhon309 0:ac8863619623 1295
jhon309 0:ac8863619623 1296 reg_value = SCB->AIRCR; /* read old register configuration */
jhon309 0:ac8863619623 1297 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
jhon309 0:ac8863619623 1298 reg_value = (reg_value |
jhon309 0:ac8863619623 1299 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
jhon309 0:ac8863619623 1300 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
jhon309 0:ac8863619623 1301 SCB->AIRCR = reg_value;
jhon309 0:ac8863619623 1302 }
jhon309 0:ac8863619623 1303
jhon309 0:ac8863619623 1304
jhon309 0:ac8863619623 1305 /** \brief Get Priority Grouping
jhon309 0:ac8863619623 1306
jhon309 0:ac8863619623 1307 The function reads the priority grouping field from the NVIC Interrupt Controller.
jhon309 0:ac8863619623 1308
jhon309 0:ac8863619623 1309 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
jhon309 0:ac8863619623 1310 */
jhon309 0:ac8863619623 1311 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
jhon309 0:ac8863619623 1312 {
jhon309 0:ac8863619623 1313 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
jhon309 0:ac8863619623 1314 }
jhon309 0:ac8863619623 1315
jhon309 0:ac8863619623 1316
jhon309 0:ac8863619623 1317 /** \brief Enable External Interrupt
jhon309 0:ac8863619623 1318
jhon309 0:ac8863619623 1319 The function enables a device-specific interrupt in the NVIC interrupt controller.
jhon309 0:ac8863619623 1320
jhon309 0:ac8863619623 1321 \param [in] IRQn External interrupt number. Value cannot be negative.
jhon309 0:ac8863619623 1322 */
jhon309 0:ac8863619623 1323 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
jhon309 0:ac8863619623 1324 {
jhon309 0:ac8863619623 1325 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
jhon309 0:ac8863619623 1326 }
jhon309 0:ac8863619623 1327
jhon309 0:ac8863619623 1328
jhon309 0:ac8863619623 1329 /** \brief Disable External Interrupt
jhon309 0:ac8863619623 1330
jhon309 0:ac8863619623 1331 The function disables a device-specific interrupt in the NVIC interrupt controller.
jhon309 0:ac8863619623 1332
jhon309 0:ac8863619623 1333 \param [in] IRQn External interrupt number. Value cannot be negative.
jhon309 0:ac8863619623 1334 */
jhon309 0:ac8863619623 1335 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
jhon309 0:ac8863619623 1336 {
jhon309 0:ac8863619623 1337 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
jhon309 0:ac8863619623 1338 }
jhon309 0:ac8863619623 1339
jhon309 0:ac8863619623 1340
jhon309 0:ac8863619623 1341 /** \brief Get Pending Interrupt
jhon309 0:ac8863619623 1342
jhon309 0:ac8863619623 1343 The function reads the pending register in the NVIC and returns the pending bit
jhon309 0:ac8863619623 1344 for the specified interrupt.
jhon309 0:ac8863619623 1345
jhon309 0:ac8863619623 1346 \param [in] IRQn Interrupt number.
jhon309 0:ac8863619623 1347
jhon309 0:ac8863619623 1348 \return 0 Interrupt status is not pending.
jhon309 0:ac8863619623 1349 \return 1 Interrupt status is pending.
jhon309 0:ac8863619623 1350 */
jhon309 0:ac8863619623 1351 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
jhon309 0:ac8863619623 1352 {
jhon309 0:ac8863619623 1353 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
jhon309 0:ac8863619623 1354 }
jhon309 0:ac8863619623 1355
jhon309 0:ac8863619623 1356
jhon309 0:ac8863619623 1357 /** \brief Set Pending Interrupt
jhon309 0:ac8863619623 1358
jhon309 0:ac8863619623 1359 The function sets the pending bit of an external interrupt.
jhon309 0:ac8863619623 1360
jhon309 0:ac8863619623 1361 \param [in] IRQn Interrupt number. Value cannot be negative.
jhon309 0:ac8863619623 1362 */
jhon309 0:ac8863619623 1363 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
jhon309 0:ac8863619623 1364 {
jhon309 0:ac8863619623 1365 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
jhon309 0:ac8863619623 1366 }
jhon309 0:ac8863619623 1367
jhon309 0:ac8863619623 1368
jhon309 0:ac8863619623 1369 /** \brief Clear Pending Interrupt
jhon309 0:ac8863619623 1370
jhon309 0:ac8863619623 1371 The function clears the pending bit of an external interrupt.
jhon309 0:ac8863619623 1372
jhon309 0:ac8863619623 1373 \param [in] IRQn External interrupt number. Value cannot be negative.
jhon309 0:ac8863619623 1374 */
jhon309 0:ac8863619623 1375 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
jhon309 0:ac8863619623 1376 {
jhon309 0:ac8863619623 1377 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
jhon309 0:ac8863619623 1378 }
jhon309 0:ac8863619623 1379
jhon309 0:ac8863619623 1380
jhon309 0:ac8863619623 1381 /** \brief Get Active Interrupt
jhon309 0:ac8863619623 1382
jhon309 0:ac8863619623 1383 The function reads the active register in NVIC and returns the active bit.
jhon309 0:ac8863619623 1384
jhon309 0:ac8863619623 1385 \param [in] IRQn Interrupt number.
jhon309 0:ac8863619623 1386
jhon309 0:ac8863619623 1387 \return 0 Interrupt status is not active.
jhon309 0:ac8863619623 1388 \return 1 Interrupt status is active.
jhon309 0:ac8863619623 1389 */
jhon309 0:ac8863619623 1390 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
jhon309 0:ac8863619623 1391 {
jhon309 0:ac8863619623 1392 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
jhon309 0:ac8863619623 1393 }
jhon309 0:ac8863619623 1394
jhon309 0:ac8863619623 1395
jhon309 0:ac8863619623 1396 /** \brief Set Interrupt Priority
jhon309 0:ac8863619623 1397
jhon309 0:ac8863619623 1398 The function sets the priority of an interrupt.
jhon309 0:ac8863619623 1399
jhon309 0:ac8863619623 1400 \note The priority cannot be set for every core interrupt.
jhon309 0:ac8863619623 1401
jhon309 0:ac8863619623 1402 \param [in] IRQn Interrupt number.
jhon309 0:ac8863619623 1403 \param [in] priority Priority to set.
jhon309 0:ac8863619623 1404 */
jhon309 0:ac8863619623 1405 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
jhon309 0:ac8863619623 1406 {
jhon309 0:ac8863619623 1407 if(IRQn < 0) {
jhon309 0:ac8863619623 1408 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
jhon309 0:ac8863619623 1409 else {
jhon309 0:ac8863619623 1410 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
jhon309 0:ac8863619623 1411 }
jhon309 0:ac8863619623 1412
jhon309 0:ac8863619623 1413
jhon309 0:ac8863619623 1414 /** \brief Get Interrupt Priority
jhon309 0:ac8863619623 1415
jhon309 0:ac8863619623 1416 The function reads the priority of an interrupt. The interrupt
jhon309 0:ac8863619623 1417 number can be positive to specify an external (device specific)
jhon309 0:ac8863619623 1418 interrupt, or negative to specify an internal (core) interrupt.
jhon309 0:ac8863619623 1419
jhon309 0:ac8863619623 1420
jhon309 0:ac8863619623 1421 \param [in] IRQn Interrupt number.
jhon309 0:ac8863619623 1422 \return Interrupt Priority. Value is aligned automatically to the implemented
jhon309 0:ac8863619623 1423 priority bits of the microcontroller.
jhon309 0:ac8863619623 1424 */
jhon309 0:ac8863619623 1425 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
jhon309 0:ac8863619623 1426 {
jhon309 0:ac8863619623 1427
jhon309 0:ac8863619623 1428 if(IRQn < 0) {
jhon309 0:ac8863619623 1429 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
jhon309 0:ac8863619623 1430 else {
jhon309 0:ac8863619623 1431 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
jhon309 0:ac8863619623 1432 }
jhon309 0:ac8863619623 1433
jhon309 0:ac8863619623 1434
jhon309 0:ac8863619623 1435 /** \brief Encode Priority
jhon309 0:ac8863619623 1436
jhon309 0:ac8863619623 1437 The function encodes the priority for an interrupt with the given priority group,
jhon309 0:ac8863619623 1438 preemptive priority value, and subpriority value.
jhon309 0:ac8863619623 1439 In case of a conflict between priority grouping and available
jhon309 0:ac8863619623 1440 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
jhon309 0:ac8863619623 1441
jhon309 0:ac8863619623 1442 \param [in] PriorityGroup Used priority group.
jhon309 0:ac8863619623 1443 \param [in] PreemptPriority Preemptive priority value (starting from 0).
jhon309 0:ac8863619623 1444 \param [in] SubPriority Subpriority value (starting from 0).
jhon309 0:ac8863619623 1445 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
jhon309 0:ac8863619623 1446 */
jhon309 0:ac8863619623 1447 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
jhon309 0:ac8863619623 1448 {
jhon309 0:ac8863619623 1449 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
jhon309 0:ac8863619623 1450 uint32_t PreemptPriorityBits;
jhon309 0:ac8863619623 1451 uint32_t SubPriorityBits;
jhon309 0:ac8863619623 1452
jhon309 0:ac8863619623 1453 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
jhon309 0:ac8863619623 1454 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
jhon309 0:ac8863619623 1455
jhon309 0:ac8863619623 1456 return (
jhon309 0:ac8863619623 1457 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
jhon309 0:ac8863619623 1458 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
jhon309 0:ac8863619623 1459 );
jhon309 0:ac8863619623 1460 }
jhon309 0:ac8863619623 1461
jhon309 0:ac8863619623 1462
jhon309 0:ac8863619623 1463 /** \brief Decode Priority
jhon309 0:ac8863619623 1464
jhon309 0:ac8863619623 1465 The function decodes an interrupt priority value with a given priority group to
jhon309 0:ac8863619623 1466 preemptive priority value and subpriority value.
jhon309 0:ac8863619623 1467 In case of a conflict between priority grouping and available
jhon309 0:ac8863619623 1468 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
jhon309 0:ac8863619623 1469
jhon309 0:ac8863619623 1470 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
jhon309 0:ac8863619623 1471 \param [in] PriorityGroup Used priority group.
jhon309 0:ac8863619623 1472 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
jhon309 0:ac8863619623 1473 \param [out] pSubPriority Subpriority value (starting from 0).
jhon309 0:ac8863619623 1474 */
jhon309 0:ac8863619623 1475 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
jhon309 0:ac8863619623 1476 {
jhon309 0:ac8863619623 1477 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
jhon309 0:ac8863619623 1478 uint32_t PreemptPriorityBits;
jhon309 0:ac8863619623 1479 uint32_t SubPriorityBits;
jhon309 0:ac8863619623 1480
jhon309 0:ac8863619623 1481 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
jhon309 0:ac8863619623 1482 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
jhon309 0:ac8863619623 1483
jhon309 0:ac8863619623 1484 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
jhon309 0:ac8863619623 1485 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
jhon309 0:ac8863619623 1486 }
jhon309 0:ac8863619623 1487
jhon309 0:ac8863619623 1488
jhon309 0:ac8863619623 1489 /** \brief System Reset
jhon309 0:ac8863619623 1490
jhon309 0:ac8863619623 1491 The function initiates a system reset request to reset the MCU.
jhon309 0:ac8863619623 1492 */
jhon309 0:ac8863619623 1493 __STATIC_INLINE void NVIC_SystemReset(void)
jhon309 0:ac8863619623 1494 {
jhon309 0:ac8863619623 1495 __DSB(); /* Ensure all outstanding memory accesses included
jhon309 0:ac8863619623 1496 buffered write are completed before reset */
jhon309 0:ac8863619623 1497 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
jhon309 0:ac8863619623 1498 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
jhon309 0:ac8863619623 1499 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
jhon309 0:ac8863619623 1500 __DSB(); /* Ensure completion of memory access */
jhon309 0:ac8863619623 1501 while(1); /* wait until reset */
jhon309 0:ac8863619623 1502 }
jhon309 0:ac8863619623 1503
jhon309 0:ac8863619623 1504 /*@} end of CMSIS_Core_NVICFunctions */
jhon309 0:ac8863619623 1505
jhon309 0:ac8863619623 1506
jhon309 0:ac8863619623 1507
jhon309 0:ac8863619623 1508 /* ################################## SysTick function ############################################ */
jhon309 0:ac8863619623 1509 /** \ingroup CMSIS_Core_FunctionInterface
jhon309 0:ac8863619623 1510 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
jhon309 0:ac8863619623 1511 \brief Functions that configure the System.
jhon309 0:ac8863619623 1512 @{
jhon309 0:ac8863619623 1513 */
jhon309 0:ac8863619623 1514
jhon309 0:ac8863619623 1515 #if (__Vendor_SysTickConfig == 0)
jhon309 0:ac8863619623 1516
jhon309 0:ac8863619623 1517 /** \brief System Tick Configuration
jhon309 0:ac8863619623 1518
jhon309 0:ac8863619623 1519 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
jhon309 0:ac8863619623 1520 Counter is in free running mode to generate periodic interrupts.
jhon309 0:ac8863619623 1521
jhon309 0:ac8863619623 1522 \param [in] ticks Number of ticks between two interrupts.
jhon309 0:ac8863619623 1523
jhon309 0:ac8863619623 1524 \return 0 Function succeeded.
jhon309 0:ac8863619623 1525 \return 1 Function failed.
jhon309 0:ac8863619623 1526
jhon309 0:ac8863619623 1527 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
jhon309 0:ac8863619623 1528 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
jhon309 0:ac8863619623 1529 must contain a vendor-specific implementation of this function.
jhon309 0:ac8863619623 1530
jhon309 0:ac8863619623 1531 */
jhon309 0:ac8863619623 1532 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
jhon309 0:ac8863619623 1533 {
jhon309 0:ac8863619623 1534 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
jhon309 0:ac8863619623 1535
jhon309 0:ac8863619623 1536 SysTick->LOAD = ticks - 1; /* set reload register */
jhon309 0:ac8863619623 1537 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
jhon309 0:ac8863619623 1538 SysTick->VAL = 0; /* Load the SysTick Counter Value */
jhon309 0:ac8863619623 1539 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
jhon309 0:ac8863619623 1540 SysTick_CTRL_TICKINT_Msk |
jhon309 0:ac8863619623 1541 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
jhon309 0:ac8863619623 1542 return (0); /* Function successful */
jhon309 0:ac8863619623 1543 }
jhon309 0:ac8863619623 1544
jhon309 0:ac8863619623 1545 #endif
jhon309 0:ac8863619623 1546
jhon309 0:ac8863619623 1547 /*@} end of CMSIS_Core_SysTickFunctions */
jhon309 0:ac8863619623 1548
jhon309 0:ac8863619623 1549
jhon309 0:ac8863619623 1550
jhon309 0:ac8863619623 1551 /* ##################################### Debug In/Output function ########################################### */
jhon309 0:ac8863619623 1552 /** \ingroup CMSIS_Core_FunctionInterface
jhon309 0:ac8863619623 1553 \defgroup CMSIS_core_DebugFunctions ITM Functions
jhon309 0:ac8863619623 1554 \brief Functions that access the ITM debug interface.
jhon309 0:ac8863619623 1555 @{
jhon309 0:ac8863619623 1556 */
jhon309 0:ac8863619623 1557
jhon309 0:ac8863619623 1558 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
jhon309 0:ac8863619623 1559 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
jhon309 0:ac8863619623 1560
jhon309 0:ac8863619623 1561
jhon309 0:ac8863619623 1562 /** \brief ITM Send Character
jhon309 0:ac8863619623 1563
jhon309 0:ac8863619623 1564 The function transmits a character via the ITM channel 0, and
jhon309 0:ac8863619623 1565 \li Just returns when no debugger is connected that has booked the output.
jhon309 0:ac8863619623 1566 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
jhon309 0:ac8863619623 1567
jhon309 0:ac8863619623 1568 \param [in] ch Character to transmit.
jhon309 0:ac8863619623 1569
jhon309 0:ac8863619623 1570 \returns Character to transmit.
jhon309 0:ac8863619623 1571 */
jhon309 0:ac8863619623 1572 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
jhon309 0:ac8863619623 1573 {
jhon309 0:ac8863619623 1574 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
jhon309 0:ac8863619623 1575 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
jhon309 0:ac8863619623 1576 {
jhon309 0:ac8863619623 1577 while (ITM->PORT[0].u32 == 0);
jhon309 0:ac8863619623 1578 ITM->PORT[0].u8 = (uint8_t) ch;
jhon309 0:ac8863619623 1579 }
jhon309 0:ac8863619623 1580 return (ch);
jhon309 0:ac8863619623 1581 }
jhon309 0:ac8863619623 1582
jhon309 0:ac8863619623 1583
jhon309 0:ac8863619623 1584 /** \brief ITM Receive Character
jhon309 0:ac8863619623 1585
jhon309 0:ac8863619623 1586 The function inputs a character via the external variable \ref ITM_RxBuffer.
jhon309 0:ac8863619623 1587
jhon309 0:ac8863619623 1588 \return Received character.
jhon309 0:ac8863619623 1589 \return -1 No character pending.
jhon309 0:ac8863619623 1590 */
jhon309 0:ac8863619623 1591 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
jhon309 0:ac8863619623 1592 int32_t ch = -1; /* no character available */
jhon309 0:ac8863619623 1593
jhon309 0:ac8863619623 1594 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
jhon309 0:ac8863619623 1595 ch = ITM_RxBuffer;
jhon309 0:ac8863619623 1596 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
jhon309 0:ac8863619623 1597 }
jhon309 0:ac8863619623 1598
jhon309 0:ac8863619623 1599 return (ch);
jhon309 0:ac8863619623 1600 }
jhon309 0:ac8863619623 1601
jhon309 0:ac8863619623 1602
jhon309 0:ac8863619623 1603 /** \brief ITM Check Character
jhon309 0:ac8863619623 1604
jhon309 0:ac8863619623 1605 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
jhon309 0:ac8863619623 1606
jhon309 0:ac8863619623 1607 \return 0 No character available.
jhon309 0:ac8863619623 1608 \return 1 Character available.
jhon309 0:ac8863619623 1609 */
jhon309 0:ac8863619623 1610 __STATIC_INLINE int32_t ITM_CheckChar (void) {
jhon309 0:ac8863619623 1611
jhon309 0:ac8863619623 1612 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
jhon309 0:ac8863619623 1613 return (0); /* no character available */
jhon309 0:ac8863619623 1614 } else {
jhon309 0:ac8863619623 1615 return (1); /* character available */
jhon309 0:ac8863619623 1616 }
jhon309 0:ac8863619623 1617 }
jhon309 0:ac8863619623 1618
jhon309 0:ac8863619623 1619 /*@} end of CMSIS_core_DebugFunctions */
jhon309 0:ac8863619623 1620
jhon309 0:ac8863619623 1621 #endif /* __CORE_CM3_H_DEPENDANT */
jhon309 0:ac8863619623 1622
jhon309 0:ac8863619623 1623 #endif /* __CMSIS_GENERIC */
jhon309 0:ac8863619623 1624
jhon309 0:ac8863619623 1625 #ifdef __cplusplus
jhon309 0:ac8863619623 1626 }
jhon309 0:ac8863619623 1627 #endif