Jhon Plantikow / I2C_EEPROM

I2C_EEPROM

TARGET_NUCLEO_F072RB/core_cm0.h@0:ac8863619623, 2015-08-13 (annotated)

Committer:
jhon309
Date:
Thu Aug 13 00:23:16 2015 +0000
Revision:
0:ac8863619623
I2C

Who changed what in which revision?

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jhon309 0:ac8863619623 1 /**************************************************************************//**
jhon309 0:ac8863619623 2 * @file core_cm0.h
jhon309 0:ac8863619623 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
jhon309 0:ac8863619623 4 * @version V3.20
jhon309 0:ac8863619623 5 * @date 25. February 2013
jhon309 0:ac8863619623 6 *
jhon309 0:ac8863619623 7 * @note
jhon309 0:ac8863619623 8 *
jhon309 0:ac8863619623 9 ******************************************************************************/
jhon309 0:ac8863619623 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
jhon309 0:ac8863619623 11
jhon309 0:ac8863619623 12 All rights reserved.
jhon309 0:ac8863619623 13 Redistribution and use in source and binary forms, with or without
jhon309 0:ac8863619623 14 modification, are permitted provided that the following conditions are met:
jhon309 0:ac8863619623 15 - Redistributions of source code must retain the above copyright
jhon309 0:ac8863619623 16 notice, this list of conditions and the following disclaimer.
jhon309 0:ac8863619623 17 - Redistributions in binary form must reproduce the above copyright
jhon309 0:ac8863619623 18 notice, this list of conditions and the following disclaimer in the
jhon309 0:ac8863619623 19 documentation and/or other materials provided with the distribution.
jhon309 0:ac8863619623 20 - Neither the name of ARM nor the names of its contributors may be used
jhon309 0:ac8863619623 21 to endorse or promote products derived from this software without
jhon309 0:ac8863619623 22 specific prior written permission.
jhon309 0:ac8863619623 23 *
jhon309 0:ac8863619623 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jhon309 0:ac8863619623 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jhon309 0:ac8863619623 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
jhon309 0:ac8863619623 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
jhon309 0:ac8863619623 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
jhon309 0:ac8863619623 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
jhon309 0:ac8863619623 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
jhon309 0:ac8863619623 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
jhon309 0:ac8863619623 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
jhon309 0:ac8863619623 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
jhon309 0:ac8863619623 34 POSSIBILITY OF SUCH DAMAGE.
jhon309 0:ac8863619623 35 ---------------------------------------------------------------------------*/
jhon309 0:ac8863619623 36
jhon309 0:ac8863619623 37
jhon309 0:ac8863619623 38 #if defined ( __ICCARM__ )
jhon309 0:ac8863619623 39 #pragma system_include /* treat file as system include file for MISRA check */
jhon309 0:ac8863619623 40 #endif
jhon309 0:ac8863619623 41
jhon309 0:ac8863619623 42 #ifdef __cplusplus
jhon309 0:ac8863619623 43 extern "C" {
jhon309 0:ac8863619623 44 #endif
jhon309 0:ac8863619623 45
jhon309 0:ac8863619623 46 #ifndef __CORE_CM0_H_GENERIC
jhon309 0:ac8863619623 47 #define __CORE_CM0_H_GENERIC
jhon309 0:ac8863619623 48
jhon309 0:ac8863619623 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
jhon309 0:ac8863619623 50 CMSIS violates the following MISRA-C:2004 rules:
jhon309 0:ac8863619623 51
jhon309 0:ac8863619623 52 \li Required Rule 8.5, object/function definition in header file.<br>
jhon309 0:ac8863619623 53 Function definitions in header files are used to allow 'inlining'.
jhon309 0:ac8863619623 54
jhon309 0:ac8863619623 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
jhon309 0:ac8863619623 56 Unions are used for effective representation of core registers.
jhon309 0:ac8863619623 57
jhon309 0:ac8863619623 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
jhon309 0:ac8863619623 59 Function-like macros are used to allow more efficient code.
jhon309 0:ac8863619623 60 */
jhon309 0:ac8863619623 61
jhon309 0:ac8863619623 62
jhon309 0:ac8863619623 63 /*******************************************************************************
jhon309 0:ac8863619623 64 * CMSIS definitions
jhon309 0:ac8863619623 65 ******************************************************************************/
jhon309 0:ac8863619623 66 /** \ingroup Cortex_M0
jhon309 0:ac8863619623 67 @{
jhon309 0:ac8863619623 68 */
jhon309 0:ac8863619623 69
jhon309 0:ac8863619623 70 /* CMSIS CM0 definitions */
jhon309 0:ac8863619623 71 #define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
jhon309 0:ac8863619623 72 #define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
jhon309 0:ac8863619623 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
jhon309 0:ac8863619623 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
jhon309 0:ac8863619623 75
jhon309 0:ac8863619623 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
jhon309 0:ac8863619623 77
jhon309 0:ac8863619623 78
jhon309 0:ac8863619623 79 #if defined ( __CC_ARM )
jhon309 0:ac8863619623 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
jhon309 0:ac8863619623 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
jhon309 0:ac8863619623 82 #define __STATIC_INLINE static __inline
jhon309 0:ac8863619623 83
jhon309 0:ac8863619623 84 #elif defined ( __ICCARM__ )
jhon309 0:ac8863619623 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
jhon309 0:ac8863619623 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
jhon309 0:ac8863619623 87 #define __STATIC_INLINE static inline
jhon309 0:ac8863619623 88
jhon309 0:ac8863619623 89 #elif defined ( __GNUC__ )
jhon309 0:ac8863619623 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
jhon309 0:ac8863619623 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
jhon309 0:ac8863619623 92 #define __STATIC_INLINE static inline
jhon309 0:ac8863619623 93
jhon309 0:ac8863619623 94 #elif defined ( __TASKING__ )
jhon309 0:ac8863619623 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
jhon309 0:ac8863619623 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
jhon309 0:ac8863619623 97 #define __STATIC_INLINE static inline
jhon309 0:ac8863619623 98
jhon309 0:ac8863619623 99 #endif
jhon309 0:ac8863619623 100
jhon309 0:ac8863619623 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
jhon309 0:ac8863619623 102 */
jhon309 0:ac8863619623 103 #define __FPU_USED 0
jhon309 0:ac8863619623 104
jhon309 0:ac8863619623 105 #if defined ( __CC_ARM )
jhon309 0:ac8863619623 106 #if defined __TARGET_FPU_VFP
jhon309 0:ac8863619623 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:ac8863619623 108 #endif
jhon309 0:ac8863619623 109
jhon309 0:ac8863619623 110 #elif defined ( __ICCARM__ )
jhon309 0:ac8863619623 111 #if defined __ARMVFP__
jhon309 0:ac8863619623 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:ac8863619623 113 #endif
jhon309 0:ac8863619623 114
jhon309 0:ac8863619623 115 #elif defined ( __GNUC__ )
jhon309 0:ac8863619623 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
jhon309 0:ac8863619623 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:ac8863619623 118 #endif
jhon309 0:ac8863619623 119
jhon309 0:ac8863619623 120 #elif defined ( __TASKING__ )
jhon309 0:ac8863619623 121 #if defined __FPU_VFP__
jhon309 0:ac8863619623 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:ac8863619623 123 #endif
jhon309 0:ac8863619623 124 #endif
jhon309 0:ac8863619623 125
jhon309 0:ac8863619623 126 #include <stdint.h> /* standard types definitions */
jhon309 0:ac8863619623 127 #include <core_cmInstr.h> /* Core Instruction Access */
jhon309 0:ac8863619623 128 #include <core_cmFunc.h> /* Core Function Access */
jhon309 0:ac8863619623 129
jhon309 0:ac8863619623 130 #endif /* __CORE_CM0_H_GENERIC */
jhon309 0:ac8863619623 131
jhon309 0:ac8863619623 132 #ifndef __CMSIS_GENERIC
jhon309 0:ac8863619623 133
jhon309 0:ac8863619623 134 #ifndef __CORE_CM0_H_DEPENDANT
jhon309 0:ac8863619623 135 #define __CORE_CM0_H_DEPENDANT
jhon309 0:ac8863619623 136
jhon309 0:ac8863619623 137 /* check device defines and use defaults */
jhon309 0:ac8863619623 138 #if defined __CHECK_DEVICE_DEFINES
jhon309 0:ac8863619623 139 #ifndef __CM0_REV
jhon309 0:ac8863619623 140 #define __CM0_REV 0x0000
jhon309 0:ac8863619623 141 #warning "__CM0_REV not defined in device header file; using default!"
jhon309 0:ac8863619623 142 #endif
jhon309 0:ac8863619623 143
jhon309 0:ac8863619623 144 #ifndef __NVIC_PRIO_BITS
jhon309 0:ac8863619623 145 #define __NVIC_PRIO_BITS 2
jhon309 0:ac8863619623 146 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
jhon309 0:ac8863619623 147 #endif
jhon309 0:ac8863619623 148
jhon309 0:ac8863619623 149 #ifndef __Vendor_SysTickConfig
jhon309 0:ac8863619623 150 #define __Vendor_SysTickConfig 0
jhon309 0:ac8863619623 151 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
jhon309 0:ac8863619623 152 #endif
jhon309 0:ac8863619623 153 #endif
jhon309 0:ac8863619623 154
jhon309 0:ac8863619623 155 /* IO definitions (access restrictions to peripheral registers) */
jhon309 0:ac8863619623 156 /**
jhon309 0:ac8863619623 157 \defgroup CMSIS_glob_defs CMSIS Global Defines
jhon309 0:ac8863619623 158
jhon309 0:ac8863619623 159 <strong>IO Type Qualifiers</strong> are used
jhon309 0:ac8863619623 160 \li to specify the access to peripheral variables.
jhon309 0:ac8863619623 161 \li for automatic generation of peripheral register debug information.
jhon309 0:ac8863619623 162 */
jhon309 0:ac8863619623 163 #ifdef __cplusplus
jhon309 0:ac8863619623 164 #define __I volatile /*!< Defines 'read only' permissions */
jhon309 0:ac8863619623 165 #else
jhon309 0:ac8863619623 166 #define __I volatile const /*!< Defines 'read only' permissions */
jhon309 0:ac8863619623 167 #endif
jhon309 0:ac8863619623 168 #define __O volatile /*!< Defines 'write only' permissions */
jhon309 0:ac8863619623 169 #define __IO volatile /*!< Defines 'read / write' permissions */
jhon309 0:ac8863619623 170
jhon309 0:ac8863619623 171 /*@} end of group Cortex_M0 */
jhon309 0:ac8863619623 172
jhon309 0:ac8863619623 173
jhon309 0:ac8863619623 174
jhon309 0:ac8863619623 175 /*******************************************************************************
jhon309 0:ac8863619623 176 * Register Abstraction
jhon309 0:ac8863619623 177 Core Register contain:
jhon309 0:ac8863619623 178 - Core Register
jhon309 0:ac8863619623 179 - Core NVIC Register
jhon309 0:ac8863619623 180 - Core SCB Register
jhon309 0:ac8863619623 181 - Core SysTick Register
jhon309 0:ac8863619623 182 ******************************************************************************/
jhon309 0:ac8863619623 183 /** \defgroup CMSIS_core_register Defines and Type Definitions
jhon309 0:ac8863619623 184 \brief Type definitions and defines for Cortex-M processor based devices.
jhon309 0:ac8863619623 185 */
jhon309 0:ac8863619623 186
jhon309 0:ac8863619623 187 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 188 \defgroup CMSIS_CORE Status and Control Registers
jhon309 0:ac8863619623 189 \brief Core Register type definitions.
jhon309 0:ac8863619623 190 @{
jhon309 0:ac8863619623 191 */
jhon309 0:ac8863619623 192
jhon309 0:ac8863619623 193 /** \brief Union type to access the Application Program Status Register (APSR).
jhon309 0:ac8863619623 194 */
jhon309 0:ac8863619623 195 typedef union
jhon309 0:ac8863619623 196 {
jhon309 0:ac8863619623 197 struct
jhon309 0:ac8863619623 198 {
jhon309 0:ac8863619623 199 #if (__CORTEX_M != 0x04)
jhon309 0:ac8863619623 200 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
jhon309 0:ac8863619623 201 #else
jhon309 0:ac8863619623 202 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
jhon309 0:ac8863619623 203 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
jhon309 0:ac8863619623 204 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
jhon309 0:ac8863619623 205 #endif
jhon309 0:ac8863619623 206 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
jhon309 0:ac8863619623 207 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
jhon309 0:ac8863619623 208 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
jhon309 0:ac8863619623 209 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
jhon309 0:ac8863619623 210 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
jhon309 0:ac8863619623 211 } b; /*!< Structure used for bit access */
jhon309 0:ac8863619623 212 uint32_t w; /*!< Type used for word access */
jhon309 0:ac8863619623 213 } APSR_Type;
jhon309 0:ac8863619623 214
jhon309 0:ac8863619623 215
jhon309 0:ac8863619623 216 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
jhon309 0:ac8863619623 217 */
jhon309 0:ac8863619623 218 typedef union
jhon309 0:ac8863619623 219 {
jhon309 0:ac8863619623 220 struct
jhon309 0:ac8863619623 221 {
jhon309 0:ac8863619623 222 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
jhon309 0:ac8863619623 223 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
jhon309 0:ac8863619623 224 } b; /*!< Structure used for bit access */
jhon309 0:ac8863619623 225 uint32_t w; /*!< Type used for word access */
jhon309 0:ac8863619623 226 } IPSR_Type;
jhon309 0:ac8863619623 227
jhon309 0:ac8863619623 228
jhon309 0:ac8863619623 229 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
jhon309 0:ac8863619623 230 */
jhon309 0:ac8863619623 231 typedef union
jhon309 0:ac8863619623 232 {
jhon309 0:ac8863619623 233 struct
jhon309 0:ac8863619623 234 {
jhon309 0:ac8863619623 235 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
jhon309 0:ac8863619623 236 #if (__CORTEX_M != 0x04)
jhon309 0:ac8863619623 237 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
jhon309 0:ac8863619623 238 #else
jhon309 0:ac8863619623 239 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
jhon309 0:ac8863619623 240 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
jhon309 0:ac8863619623 241 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
jhon309 0:ac8863619623 242 #endif
jhon309 0:ac8863619623 243 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
jhon309 0:ac8863619623 244 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
jhon309 0:ac8863619623 245 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
jhon309 0:ac8863619623 246 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
jhon309 0:ac8863619623 247 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
jhon309 0:ac8863619623 248 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
jhon309 0:ac8863619623 249 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
jhon309 0:ac8863619623 250 } b; /*!< Structure used for bit access */
jhon309 0:ac8863619623 251 uint32_t w; /*!< Type used for word access */
jhon309 0:ac8863619623 252 } xPSR_Type;
jhon309 0:ac8863619623 253
jhon309 0:ac8863619623 254
jhon309 0:ac8863619623 255 /** \brief Union type to access the Control Registers (CONTROL).
jhon309 0:ac8863619623 256 */
jhon309 0:ac8863619623 257 typedef union
jhon309 0:ac8863619623 258 {
jhon309 0:ac8863619623 259 struct
jhon309 0:ac8863619623 260 {
jhon309 0:ac8863619623 261 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
jhon309 0:ac8863619623 262 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
jhon309 0:ac8863619623 263 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
jhon309 0:ac8863619623 264 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
jhon309 0:ac8863619623 265 } b; /*!< Structure used for bit access */
jhon309 0:ac8863619623 266 uint32_t w; /*!< Type used for word access */
jhon309 0:ac8863619623 267 } CONTROL_Type;
jhon309 0:ac8863619623 268
jhon309 0:ac8863619623 269 /*@} end of group CMSIS_CORE */
jhon309 0:ac8863619623 270
jhon309 0:ac8863619623 271
jhon309 0:ac8863619623 272 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 273 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
jhon309 0:ac8863619623 274 \brief Type definitions for the NVIC Registers
jhon309 0:ac8863619623 275 @{
jhon309 0:ac8863619623 276 */
jhon309 0:ac8863619623 277
jhon309 0:ac8863619623 278 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
jhon309 0:ac8863619623 279 */
jhon309 0:ac8863619623 280 typedef struct
jhon309 0:ac8863619623 281 {
jhon309 0:ac8863619623 282 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
jhon309 0:ac8863619623 283 uint32_t RESERVED0[31];
jhon309 0:ac8863619623 284 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
jhon309 0:ac8863619623 285 uint32_t RSERVED1[31];
jhon309 0:ac8863619623 286 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
jhon309 0:ac8863619623 287 uint32_t RESERVED2[31];
jhon309 0:ac8863619623 288 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
jhon309 0:ac8863619623 289 uint32_t RESERVED3[31];
jhon309 0:ac8863619623 290 uint32_t RESERVED4[64];
jhon309 0:ac8863619623 291 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
jhon309 0:ac8863619623 292 } NVIC_Type;
jhon309 0:ac8863619623 293
jhon309 0:ac8863619623 294 /*@} end of group CMSIS_NVIC */
jhon309 0:ac8863619623 295
jhon309 0:ac8863619623 296
jhon309 0:ac8863619623 297 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 298 \defgroup CMSIS_SCB System Control Block (SCB)
jhon309 0:ac8863619623 299 \brief Type definitions for the System Control Block Registers
jhon309 0:ac8863619623 300 @{
jhon309 0:ac8863619623 301 */
jhon309 0:ac8863619623 302
jhon309 0:ac8863619623 303 /** \brief Structure type to access the System Control Block (SCB).
jhon309 0:ac8863619623 304 */
jhon309 0:ac8863619623 305 typedef struct
jhon309 0:ac8863619623 306 {
jhon309 0:ac8863619623 307 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
jhon309 0:ac8863619623 308 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
jhon309 0:ac8863619623 309 uint32_t RESERVED0;
jhon309 0:ac8863619623 310 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
jhon309 0:ac8863619623 311 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
jhon309 0:ac8863619623 312 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
jhon309 0:ac8863619623 313 uint32_t RESERVED1;
jhon309 0:ac8863619623 314 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
jhon309 0:ac8863619623 315 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
jhon309 0:ac8863619623 316 } SCB_Type;
jhon309 0:ac8863619623 317
jhon309 0:ac8863619623 318 /* SCB CPUID Register Definitions */
jhon309 0:ac8863619623 319 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
jhon309 0:ac8863619623 320 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
jhon309 0:ac8863619623 321
jhon309 0:ac8863619623 322 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
jhon309 0:ac8863619623 323 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
jhon309 0:ac8863619623 324
jhon309 0:ac8863619623 325 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
jhon309 0:ac8863619623 326 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
jhon309 0:ac8863619623 327
jhon309 0:ac8863619623 328 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
jhon309 0:ac8863619623 329 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
jhon309 0:ac8863619623 330
jhon309 0:ac8863619623 331 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
jhon309 0:ac8863619623 332 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
jhon309 0:ac8863619623 333
jhon309 0:ac8863619623 334 /* SCB Interrupt Control State Register Definitions */
jhon309 0:ac8863619623 335 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
jhon309 0:ac8863619623 336 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
jhon309 0:ac8863619623 337
jhon309 0:ac8863619623 338 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
jhon309 0:ac8863619623 339 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
jhon309 0:ac8863619623 340
jhon309 0:ac8863619623 341 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
jhon309 0:ac8863619623 342 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
jhon309 0:ac8863619623 343
jhon309 0:ac8863619623 344 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
jhon309 0:ac8863619623 345 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
jhon309 0:ac8863619623 346
jhon309 0:ac8863619623 347 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
jhon309 0:ac8863619623 348 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
jhon309 0:ac8863619623 349
jhon309 0:ac8863619623 350 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
jhon309 0:ac8863619623 351 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
jhon309 0:ac8863619623 352
jhon309 0:ac8863619623 353 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
jhon309 0:ac8863619623 354 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
jhon309 0:ac8863619623 355
jhon309 0:ac8863619623 356 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
jhon309 0:ac8863619623 357 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
jhon309 0:ac8863619623 358
jhon309 0:ac8863619623 359 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
jhon309 0:ac8863619623 360 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
jhon309 0:ac8863619623 361
jhon309 0:ac8863619623 362 /* SCB Application Interrupt and Reset Control Register Definitions */
jhon309 0:ac8863619623 363 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
jhon309 0:ac8863619623 364 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
jhon309 0:ac8863619623 365
jhon309 0:ac8863619623 366 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
jhon309 0:ac8863619623 367 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
jhon309 0:ac8863619623 368
jhon309 0:ac8863619623 369 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
jhon309 0:ac8863619623 370 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
jhon309 0:ac8863619623 371
jhon309 0:ac8863619623 372 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
jhon309 0:ac8863619623 373 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
jhon309 0:ac8863619623 374
jhon309 0:ac8863619623 375 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
jhon309 0:ac8863619623 376 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
jhon309 0:ac8863619623 377
jhon309 0:ac8863619623 378 /* SCB System Control Register Definitions */
jhon309 0:ac8863619623 379 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
jhon309 0:ac8863619623 380 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
jhon309 0:ac8863619623 381
jhon309 0:ac8863619623 382 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
jhon309 0:ac8863619623 383 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
jhon309 0:ac8863619623 384
jhon309 0:ac8863619623 385 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
jhon309 0:ac8863619623 386 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
jhon309 0:ac8863619623 387
jhon309 0:ac8863619623 388 /* SCB Configuration Control Register Definitions */
jhon309 0:ac8863619623 389 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
jhon309 0:ac8863619623 390 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
jhon309 0:ac8863619623 391
jhon309 0:ac8863619623 392 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
jhon309 0:ac8863619623 393 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
jhon309 0:ac8863619623 394
jhon309 0:ac8863619623 395 /* SCB System Handler Control and State Register Definitions */
jhon309 0:ac8863619623 396 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
jhon309 0:ac8863619623 397 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
jhon309 0:ac8863619623 398
jhon309 0:ac8863619623 399 /*@} end of group CMSIS_SCB */
jhon309 0:ac8863619623 400
jhon309 0:ac8863619623 401
jhon309 0:ac8863619623 402 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 403 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
jhon309 0:ac8863619623 404 \brief Type definitions for the System Timer Registers.
jhon309 0:ac8863619623 405 @{
jhon309 0:ac8863619623 406 */
jhon309 0:ac8863619623 407
jhon309 0:ac8863619623 408 /** \brief Structure type to access the System Timer (SysTick).
jhon309 0:ac8863619623 409 */
jhon309 0:ac8863619623 410 typedef struct
jhon309 0:ac8863619623 411 {
jhon309 0:ac8863619623 412 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
jhon309 0:ac8863619623 413 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
jhon309 0:ac8863619623 414 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
jhon309 0:ac8863619623 415 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
jhon309 0:ac8863619623 416 } SysTick_Type;
jhon309 0:ac8863619623 417
jhon309 0:ac8863619623 418 /* SysTick Control / Status Register Definitions */
jhon309 0:ac8863619623 419 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
jhon309 0:ac8863619623 420 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
jhon309 0:ac8863619623 421
jhon309 0:ac8863619623 422 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
jhon309 0:ac8863619623 423 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
jhon309 0:ac8863619623 424
jhon309 0:ac8863619623 425 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
jhon309 0:ac8863619623 426 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
jhon309 0:ac8863619623 427
jhon309 0:ac8863619623 428 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
jhon309 0:ac8863619623 429 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
jhon309 0:ac8863619623 430
jhon309 0:ac8863619623 431 /* SysTick Reload Register Definitions */
jhon309 0:ac8863619623 432 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
jhon309 0:ac8863619623 433 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
jhon309 0:ac8863619623 434
jhon309 0:ac8863619623 435 /* SysTick Current Register Definitions */
jhon309 0:ac8863619623 436 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
jhon309 0:ac8863619623 437 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
jhon309 0:ac8863619623 438
jhon309 0:ac8863619623 439 /* SysTick Calibration Register Definitions */
jhon309 0:ac8863619623 440 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
jhon309 0:ac8863619623 441 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
jhon309 0:ac8863619623 442
jhon309 0:ac8863619623 443 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
jhon309 0:ac8863619623 444 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
jhon309 0:ac8863619623 445
jhon309 0:ac8863619623 446 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
jhon309 0:ac8863619623 447 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
jhon309 0:ac8863619623 448
jhon309 0:ac8863619623 449 /*@} end of group CMSIS_SysTick */
jhon309 0:ac8863619623 450
jhon309 0:ac8863619623 451
jhon309 0:ac8863619623 452 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 453 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
jhon309 0:ac8863619623 454 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
jhon309 0:ac8863619623 455 are only accessible over DAP and not via processor. Therefore
jhon309 0:ac8863619623 456 they are not covered by the Cortex-M0 header file.
jhon309 0:ac8863619623 457 @{
jhon309 0:ac8863619623 458 */
jhon309 0:ac8863619623 459 /*@} end of group CMSIS_CoreDebug */
jhon309 0:ac8863619623 460
jhon309 0:ac8863619623 461
jhon309 0:ac8863619623 462 /** \ingroup CMSIS_core_register
jhon309 0:ac8863619623 463 \defgroup CMSIS_core_base Core Definitions
jhon309 0:ac8863619623 464 \brief Definitions for base addresses, unions, and structures.
jhon309 0:ac8863619623 465 @{
jhon309 0:ac8863619623 466 */
jhon309 0:ac8863619623 467
jhon309 0:ac8863619623 468 /* Memory mapping of Cortex-M0 Hardware */
jhon309 0:ac8863619623 469 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
jhon309 0:ac8863619623 470 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
jhon309 0:ac8863619623 471 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
jhon309 0:ac8863619623 472 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
jhon309 0:ac8863619623 473
jhon309 0:ac8863619623 474 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
jhon309 0:ac8863619623 475 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
jhon309 0:ac8863619623 476 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
jhon309 0:ac8863619623 477
jhon309 0:ac8863619623 478
jhon309 0:ac8863619623 479 /*@} */
jhon309 0:ac8863619623 480
jhon309 0:ac8863619623 481
jhon309 0:ac8863619623 482
jhon309 0:ac8863619623 483 /*******************************************************************************
jhon309 0:ac8863619623 484 * Hardware Abstraction Layer
jhon309 0:ac8863619623 485 Core Function Interface contains:
jhon309 0:ac8863619623 486 - Core NVIC Functions
jhon309 0:ac8863619623 487 - Core SysTick Functions
jhon309 0:ac8863619623 488 - Core Register Access Functions
jhon309 0:ac8863619623 489 ******************************************************************************/
jhon309 0:ac8863619623 490 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
jhon309 0:ac8863619623 491 */
jhon309 0:ac8863619623 492
jhon309 0:ac8863619623 493
jhon309 0:ac8863619623 494
jhon309 0:ac8863619623 495 /* ########################## NVIC functions #################################### */
jhon309 0:ac8863619623 496 /** \ingroup CMSIS_Core_FunctionInterface
jhon309 0:ac8863619623 497 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
jhon309 0:ac8863619623 498 \brief Functions that manage interrupts and exceptions via the NVIC.
jhon309 0:ac8863619623 499 @{
jhon309 0:ac8863619623 500 */
jhon309 0:ac8863619623 501
jhon309 0:ac8863619623 502 /* Interrupt Priorities are WORD accessible only under ARMv6M */
jhon309 0:ac8863619623 503 /* The following MACROS handle generation of the register offset and byte masks */
jhon309 0:ac8863619623 504 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
jhon309 0:ac8863619623 505 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
jhon309 0:ac8863619623 506 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
jhon309 0:ac8863619623 507
jhon309 0:ac8863619623 508
jhon309 0:ac8863619623 509 /** \brief Enable External Interrupt
jhon309 0:ac8863619623 510
jhon309 0:ac8863619623 511 The function enables a device-specific interrupt in the NVIC interrupt controller.
jhon309 0:ac8863619623 512
jhon309 0:ac8863619623 513 \param [in] IRQn External interrupt number. Value cannot be negative.
jhon309 0:ac8863619623 514 */
jhon309 0:ac8863619623 515 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
jhon309 0:ac8863619623 516 {
jhon309 0:ac8863619623 517 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
jhon309 0:ac8863619623 518 }
jhon309 0:ac8863619623 519
jhon309 0:ac8863619623 520
jhon309 0:ac8863619623 521 /** \brief Disable External Interrupt
jhon309 0:ac8863619623 522
jhon309 0:ac8863619623 523 The function disables a device-specific interrupt in the NVIC interrupt controller.
jhon309 0:ac8863619623 524
jhon309 0:ac8863619623 525 \param [in] IRQn External interrupt number. Value cannot be negative.
jhon309 0:ac8863619623 526 */
jhon309 0:ac8863619623 527 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
jhon309 0:ac8863619623 528 {
jhon309 0:ac8863619623 529 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
jhon309 0:ac8863619623 530 }
jhon309 0:ac8863619623 531
jhon309 0:ac8863619623 532
jhon309 0:ac8863619623 533 /** \brief Get Pending Interrupt
jhon309 0:ac8863619623 534
jhon309 0:ac8863619623 535 The function reads the pending register in the NVIC and returns the pending bit
jhon309 0:ac8863619623 536 for the specified interrupt.
jhon309 0:ac8863619623 537
jhon309 0:ac8863619623 538 \param [in] IRQn Interrupt number.
jhon309 0:ac8863619623 539
jhon309 0:ac8863619623 540 \return 0 Interrupt status is not pending.
jhon309 0:ac8863619623 541 \return 1 Interrupt status is pending.
jhon309 0:ac8863619623 542 */
jhon309 0:ac8863619623 543 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
jhon309 0:ac8863619623 544 {
jhon309 0:ac8863619623 545 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
jhon309 0:ac8863619623 546 }
jhon309 0:ac8863619623 547
jhon309 0:ac8863619623 548
jhon309 0:ac8863619623 549 /** \brief Set Pending Interrupt
jhon309 0:ac8863619623 550
jhon309 0:ac8863619623 551 The function sets the pending bit of an external interrupt.
jhon309 0:ac8863619623 552
jhon309 0:ac8863619623 553 \param [in] IRQn Interrupt number. Value cannot be negative.
jhon309 0:ac8863619623 554 */
jhon309 0:ac8863619623 555 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
jhon309 0:ac8863619623 556 {
jhon309 0:ac8863619623 557 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
jhon309 0:ac8863619623 558 }
jhon309 0:ac8863619623 559
jhon309 0:ac8863619623 560
jhon309 0:ac8863619623 561 /** \brief Clear Pending Interrupt
jhon309 0:ac8863619623 562
jhon309 0:ac8863619623 563 The function clears the pending bit of an external interrupt.
jhon309 0:ac8863619623 564
jhon309 0:ac8863619623 565 \param [in] IRQn External interrupt number. Value cannot be negative.
jhon309 0:ac8863619623 566 */
jhon309 0:ac8863619623 567 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
jhon309 0:ac8863619623 568 {
jhon309 0:ac8863619623 569 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
jhon309 0:ac8863619623 570 }
jhon309 0:ac8863619623 571
jhon309 0:ac8863619623 572
jhon309 0:ac8863619623 573 /** \brief Set Interrupt Priority
jhon309 0:ac8863619623 574
jhon309 0:ac8863619623 575 The function sets the priority of an interrupt.
jhon309 0:ac8863619623 576
jhon309 0:ac8863619623 577 \note The priority cannot be set for every core interrupt.
jhon309 0:ac8863619623 578
jhon309 0:ac8863619623 579 \param [in] IRQn Interrupt number.
jhon309 0:ac8863619623 580 \param [in] priority Priority to set.
jhon309 0:ac8863619623 581 */
jhon309 0:ac8863619623 582 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
jhon309 0:ac8863619623 583 {
jhon309 0:ac8863619623 584 if(IRQn < 0) {
jhon309 0:ac8863619623 585 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
jhon309 0:ac8863619623 586 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
jhon309 0:ac8863619623 587 else {
jhon309 0:ac8863619623 588 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
jhon309 0:ac8863619623 589 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
jhon309 0:ac8863619623 590 }
jhon309 0:ac8863619623 591
jhon309 0:ac8863619623 592
jhon309 0:ac8863619623 593 /** \brief Get Interrupt Priority
jhon309 0:ac8863619623 594
jhon309 0:ac8863619623 595 The function reads the priority of an interrupt. The interrupt
jhon309 0:ac8863619623 596 number can be positive to specify an external (device specific)
jhon309 0:ac8863619623 597 interrupt, or negative to specify an internal (core) interrupt.
jhon309 0:ac8863619623 598
jhon309 0:ac8863619623 599
jhon309 0:ac8863619623 600 \param [in] IRQn Interrupt number.
jhon309 0:ac8863619623 601 \return Interrupt Priority. Value is aligned automatically to the implemented
jhon309 0:ac8863619623 602 priority bits of the microcontroller.
jhon309 0:ac8863619623 603 */
jhon309 0:ac8863619623 604 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
jhon309 0:ac8863619623 605 {
jhon309 0:ac8863619623 606
jhon309 0:ac8863619623 607 if(IRQn < 0) {
jhon309 0:ac8863619623 608 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
jhon309 0:ac8863619623 609 else {
jhon309 0:ac8863619623 610 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
jhon309 0:ac8863619623 611 }
jhon309 0:ac8863619623 612
jhon309 0:ac8863619623 613
jhon309 0:ac8863619623 614 /** \brief System Reset
jhon309 0:ac8863619623 615
jhon309 0:ac8863619623 616 The function initiates a system reset request to reset the MCU.
jhon309 0:ac8863619623 617 */
jhon309 0:ac8863619623 618 __STATIC_INLINE void NVIC_SystemReset(void)
jhon309 0:ac8863619623 619 {
jhon309 0:ac8863619623 620 __DSB(); /* Ensure all outstanding memory accesses included
jhon309 0:ac8863619623 621 buffered write are completed before reset */
jhon309 0:ac8863619623 622 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
jhon309 0:ac8863619623 623 SCB_AIRCR_SYSRESETREQ_Msk);
jhon309 0:ac8863619623 624 __DSB(); /* Ensure completion of memory access */
jhon309 0:ac8863619623 625 while(1); /* wait until reset */
jhon309 0:ac8863619623 626 }
jhon309 0:ac8863619623 627
jhon309 0:ac8863619623 628 /*@} end of CMSIS_Core_NVICFunctions */
jhon309 0:ac8863619623 629
jhon309 0:ac8863619623 630
jhon309 0:ac8863619623 631
jhon309 0:ac8863619623 632 /* ################################## SysTick function ############################################ */
jhon309 0:ac8863619623 633 /** \ingroup CMSIS_Core_FunctionInterface
jhon309 0:ac8863619623 634 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
jhon309 0:ac8863619623 635 \brief Functions that configure the System.
jhon309 0:ac8863619623 636 @{
jhon309 0:ac8863619623 637 */
jhon309 0:ac8863619623 638
jhon309 0:ac8863619623 639 #if (__Vendor_SysTickConfig == 0)
jhon309 0:ac8863619623 640
jhon309 0:ac8863619623 641 /** \brief System Tick Configuration
jhon309 0:ac8863619623 642
jhon309 0:ac8863619623 643 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
jhon309 0:ac8863619623 644 Counter is in free running mode to generate periodic interrupts.
jhon309 0:ac8863619623 645
jhon309 0:ac8863619623 646 \param [in] ticks Number of ticks between two interrupts.
jhon309 0:ac8863619623 647
jhon309 0:ac8863619623 648 \return 0 Function succeeded.
jhon309 0:ac8863619623 649 \return 1 Function failed.
jhon309 0:ac8863619623 650
jhon309 0:ac8863619623 651 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
jhon309 0:ac8863619623 652 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
jhon309 0:ac8863619623 653 must contain a vendor-specific implementation of this function.
jhon309 0:ac8863619623 654
jhon309 0:ac8863619623 655 */
jhon309 0:ac8863619623 656 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
jhon309 0:ac8863619623 657 {
jhon309 0:ac8863619623 658 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
jhon309 0:ac8863619623 659
jhon309 0:ac8863619623 660 SysTick->LOAD = ticks - 1; /* set reload register */
jhon309 0:ac8863619623 661 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
jhon309 0:ac8863619623 662 SysTick->VAL = 0; /* Load the SysTick Counter Value */
jhon309 0:ac8863619623 663 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
jhon309 0:ac8863619623 664 SysTick_CTRL_TICKINT_Msk |
jhon309 0:ac8863619623 665 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
jhon309 0:ac8863619623 666 return (0); /* Function successful */
jhon309 0:ac8863619623 667 }
jhon309 0:ac8863619623 668
jhon309 0:ac8863619623 669 #endif
jhon309 0:ac8863619623 670
jhon309 0:ac8863619623 671 /*@} end of CMSIS_Core_SysTickFunctions */
jhon309 0:ac8863619623 672
jhon309 0:ac8863619623 673
jhon309 0:ac8863619623 674
jhon309 0:ac8863619623 675
jhon309 0:ac8863619623 676 #endif /* __CORE_CM0_H_DEPENDANT */
jhon309 0:ac8863619623 677
jhon309 0:ac8863619623 678 #endif /* __CMSIS_GENERIC */
jhon309 0:ac8863619623 679
jhon309 0:ac8863619623 680 #ifdef __cplusplus
jhon309 0:ac8863619623 681 }
jhon309 0:ac8863619623 682 #endif