Jhon Plantikow / I2C_EEPROM

I2C_EEPROM

TARGET_NUCLEO_F072RB/core_caFunc.h@0:ac8863619623, 2015-08-13 (annotated)

Committer:
jhon309
Date:
Thu Aug 13 00:23:16 2015 +0000
Revision:
0:ac8863619623
I2C

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jhon309 0:ac8863619623 1 /**************************************************************************//**
jhon309 0:ac8863619623 2 * @file core_caFunc.h
jhon309 0:ac8863619623 3 * @brief CMSIS Cortex-A Core Function Access Header File
jhon309 0:ac8863619623 4 * @version V3.10
jhon309 0:ac8863619623 5 * @date 9 May 2013
jhon309 0:ac8863619623 6 *
jhon309 0:ac8863619623 7 * @note
jhon309 0:ac8863619623 8 *
jhon309 0:ac8863619623 9 ******************************************************************************/
jhon309 0:ac8863619623 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
jhon309 0:ac8863619623 11
jhon309 0:ac8863619623 12 All rights reserved.
jhon309 0:ac8863619623 13 Redistribution and use in source and binary forms, with or without
jhon309 0:ac8863619623 14 modification, are permitted provided that the following conditions are met:
jhon309 0:ac8863619623 15 - Redistributions of source code must retain the above copyright
jhon309 0:ac8863619623 16 notice, this list of conditions and the following disclaimer.
jhon309 0:ac8863619623 17 - Redistributions in binary form must reproduce the above copyright
jhon309 0:ac8863619623 18 notice, this list of conditions and the following disclaimer in the
jhon309 0:ac8863619623 19 documentation and/or other materials provided with the distribution.
jhon309 0:ac8863619623 20 - Neither the name of ARM nor the names of its contributors may be used
jhon309 0:ac8863619623 21 to endorse or promote products derived from this software without
jhon309 0:ac8863619623 22 specific prior written permission.
jhon309 0:ac8863619623 23 *
jhon309 0:ac8863619623 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jhon309 0:ac8863619623 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jhon309 0:ac8863619623 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
jhon309 0:ac8863619623 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
jhon309 0:ac8863619623 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
jhon309 0:ac8863619623 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
jhon309 0:ac8863619623 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
jhon309 0:ac8863619623 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
jhon309 0:ac8863619623 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
jhon309 0:ac8863619623 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
jhon309 0:ac8863619623 34 POSSIBILITY OF SUCH DAMAGE.
jhon309 0:ac8863619623 35 ---------------------------------------------------------------------------*/
jhon309 0:ac8863619623 36
jhon309 0:ac8863619623 37
jhon309 0:ac8863619623 38 #ifndef __CORE_CAFUNC_H__
jhon309 0:ac8863619623 39 #define __CORE_CAFUNC_H__
jhon309 0:ac8863619623 40
jhon309 0:ac8863619623 41
jhon309 0:ac8863619623 42 /* ########################### Core Function Access ########################### */
jhon309 0:ac8863619623 43 /** \ingroup CMSIS_Core_FunctionInterface
jhon309 0:ac8863619623 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
jhon309 0:ac8863619623 45 @{
jhon309 0:ac8863619623 46 */
jhon309 0:ac8863619623 47
jhon309 0:ac8863619623 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
jhon309 0:ac8863619623 49 /* ARM armcc specific functions */
jhon309 0:ac8863619623 50
jhon309 0:ac8863619623 51 #if (__ARMCC_VERSION < 400677)
jhon309 0:ac8863619623 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
jhon309 0:ac8863619623 53 #endif
jhon309 0:ac8863619623 54
jhon309 0:ac8863619623 55 #define MODE_USR 0x10
jhon309 0:ac8863619623 56 #define MODE_FIQ 0x11
jhon309 0:ac8863619623 57 #define MODE_IRQ 0x12
jhon309 0:ac8863619623 58 #define MODE_SVC 0x13
jhon309 0:ac8863619623 59 #define MODE_MON 0x16
jhon309 0:ac8863619623 60 #define MODE_ABT 0x17
jhon309 0:ac8863619623 61 #define MODE_HYP 0x1A
jhon309 0:ac8863619623 62 #define MODE_UND 0x1B
jhon309 0:ac8863619623 63 #define MODE_SYS 0x1F
jhon309 0:ac8863619623 64
jhon309 0:ac8863619623 65 /** \brief Get APSR Register
jhon309 0:ac8863619623 66
jhon309 0:ac8863619623 67 This function returns the content of the APSR Register.
jhon309 0:ac8863619623 68
jhon309 0:ac8863619623 69 \return APSR Register value
jhon309 0:ac8863619623 70 */
jhon309 0:ac8863619623 71 __STATIC_INLINE uint32_t __get_APSR(void)
jhon309 0:ac8863619623 72 {
jhon309 0:ac8863619623 73 register uint32_t __regAPSR __ASM("apsr");
jhon309 0:ac8863619623 74 return(__regAPSR);
jhon309 0:ac8863619623 75 }
jhon309 0:ac8863619623 76
jhon309 0:ac8863619623 77
jhon309 0:ac8863619623 78 /** \brief Get CPSR Register
jhon309 0:ac8863619623 79
jhon309 0:ac8863619623 80 This function returns the content of the CPSR Register.
jhon309 0:ac8863619623 81
jhon309 0:ac8863619623 82 \return CPSR Register value
jhon309 0:ac8863619623 83 */
jhon309 0:ac8863619623 84 __STATIC_INLINE uint32_t __get_CPSR(void)
jhon309 0:ac8863619623 85 {
jhon309 0:ac8863619623 86 register uint32_t __regCPSR __ASM("cpsr");
jhon309 0:ac8863619623 87 return(__regCPSR);
jhon309 0:ac8863619623 88 }
jhon309 0:ac8863619623 89
jhon309 0:ac8863619623 90 /** \brief Set Stack Pointer
jhon309 0:ac8863619623 91
jhon309 0:ac8863619623 92 This function assigns the given value to the current stack pointer.
jhon309 0:ac8863619623 93
jhon309 0:ac8863619623 94 \param [in] topOfStack Stack Pointer value to set
jhon309 0:ac8863619623 95 */
jhon309 0:ac8863619623 96 register uint32_t __regSP __ASM("sp");
jhon309 0:ac8863619623 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
jhon309 0:ac8863619623 98 {
jhon309 0:ac8863619623 99 __regSP = topOfStack;
jhon309 0:ac8863619623 100 }
jhon309 0:ac8863619623 101
jhon309 0:ac8863619623 102
jhon309 0:ac8863619623 103 /** \brief Get link register
jhon309 0:ac8863619623 104
jhon309 0:ac8863619623 105 This function returns the value of the link register
jhon309 0:ac8863619623 106
jhon309 0:ac8863619623 107 \return Value of link register
jhon309 0:ac8863619623 108 */
jhon309 0:ac8863619623 109 register uint32_t __reglr __ASM("lr");
jhon309 0:ac8863619623 110 __STATIC_INLINE uint32_t __get_LR(void)
jhon309 0:ac8863619623 111 {
jhon309 0:ac8863619623 112 return(__reglr);
jhon309 0:ac8863619623 113 }
jhon309 0:ac8863619623 114
jhon309 0:ac8863619623 115 /** \brief Set link register
jhon309 0:ac8863619623 116
jhon309 0:ac8863619623 117 This function sets the value of the link register
jhon309 0:ac8863619623 118
jhon309 0:ac8863619623 119 \param [in] lr LR value to set
jhon309 0:ac8863619623 120 */
jhon309 0:ac8863619623 121 __STATIC_INLINE void __set_LR(uint32_t lr)
jhon309 0:ac8863619623 122 {
jhon309 0:ac8863619623 123 __reglr = lr;
jhon309 0:ac8863619623 124 }
jhon309 0:ac8863619623 125
jhon309 0:ac8863619623 126 /** \brief Set Process Stack Pointer
jhon309 0:ac8863619623 127
jhon309 0:ac8863619623 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
jhon309 0:ac8863619623 129
jhon309 0:ac8863619623 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
jhon309 0:ac8863619623 131 */
jhon309 0:ac8863619623 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
jhon309 0:ac8863619623 133 {
jhon309 0:ac8863619623 134 ARM
jhon309 0:ac8863619623 135 PRESERVE8
jhon309 0:ac8863619623 136
jhon309 0:ac8863619623 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
jhon309 0:ac8863619623 138 MRS R1, CPSR
jhon309 0:ac8863619623 139 CPS #MODE_SYS ;no effect in USR mode
jhon309 0:ac8863619623 140 MOV SP, R0
jhon309 0:ac8863619623 141 MSR CPSR_c, R1 ;no effect in USR mode
jhon309 0:ac8863619623 142 ISB
jhon309 0:ac8863619623 143 BX LR
jhon309 0:ac8863619623 144
jhon309 0:ac8863619623 145 }
jhon309 0:ac8863619623 146
jhon309 0:ac8863619623 147 /** \brief Set User Mode
jhon309 0:ac8863619623 148
jhon309 0:ac8863619623 149 This function changes the processor state to User Mode
jhon309 0:ac8863619623 150
jhon309 0:ac8863619623 151 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
jhon309 0:ac8863619623 152 */
jhon309 0:ac8863619623 153 __STATIC_ASM void __set_CPS_USR(void)
jhon309 0:ac8863619623 154 {
jhon309 0:ac8863619623 155 ARM
jhon309 0:ac8863619623 156
jhon309 0:ac8863619623 157 CPS #MODE_USR
jhon309 0:ac8863619623 158 BX LR
jhon309 0:ac8863619623 159 }
jhon309 0:ac8863619623 160
jhon309 0:ac8863619623 161
jhon309 0:ac8863619623 162 /** \brief Enable FIQ
jhon309 0:ac8863619623 163
jhon309 0:ac8863619623 164 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
jhon309 0:ac8863619623 165 Can only be executed in Privileged modes.
jhon309 0:ac8863619623 166 */
jhon309 0:ac8863619623 167 #define __enable_fault_irq __enable_fiq
jhon309 0:ac8863619623 168
jhon309 0:ac8863619623 169
jhon309 0:ac8863619623 170 /** \brief Disable FIQ
jhon309 0:ac8863619623 171
jhon309 0:ac8863619623 172 This function disables FIQ interrupts by setting the F-bit in the CPSR.
jhon309 0:ac8863619623 173 Can only be executed in Privileged modes.
jhon309 0:ac8863619623 174 */
jhon309 0:ac8863619623 175 #define __disable_fault_irq __disable_fiq
jhon309 0:ac8863619623 176
jhon309 0:ac8863619623 177
jhon309 0:ac8863619623 178 /** \brief Get FPSCR
jhon309 0:ac8863619623 179
jhon309 0:ac8863619623 180 This function returns the current value of the Floating Point Status/Control register.
jhon309 0:ac8863619623 181
jhon309 0:ac8863619623 182 \return Floating Point Status/Control register value
jhon309 0:ac8863619623 183 */
jhon309 0:ac8863619623 184 __STATIC_INLINE uint32_t __get_FPSCR(void)
jhon309 0:ac8863619623 185 {
jhon309 0:ac8863619623 186 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jhon309 0:ac8863619623 187 register uint32_t __regfpscr __ASM("fpscr");
jhon309 0:ac8863619623 188 return(__regfpscr);
jhon309 0:ac8863619623 189 #else
jhon309 0:ac8863619623 190 return(0);
jhon309 0:ac8863619623 191 #endif
jhon309 0:ac8863619623 192 }
jhon309 0:ac8863619623 193
jhon309 0:ac8863619623 194
jhon309 0:ac8863619623 195 /** \brief Set FPSCR
jhon309 0:ac8863619623 196
jhon309 0:ac8863619623 197 This function assigns the given value to the Floating Point Status/Control register.
jhon309 0:ac8863619623 198
jhon309 0:ac8863619623 199 \param [in] fpscr Floating Point Status/Control value to set
jhon309 0:ac8863619623 200 */
jhon309 0:ac8863619623 201 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
jhon309 0:ac8863619623 202 {
jhon309 0:ac8863619623 203 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jhon309 0:ac8863619623 204 register uint32_t __regfpscr __ASM("fpscr");
jhon309 0:ac8863619623 205 __regfpscr = (fpscr);
jhon309 0:ac8863619623 206 #endif
jhon309 0:ac8863619623 207 }
jhon309 0:ac8863619623 208
jhon309 0:ac8863619623 209 /** \brief Get FPEXC
jhon309 0:ac8863619623 210
jhon309 0:ac8863619623 211 This function returns the current value of the Floating Point Exception Control register.
jhon309 0:ac8863619623 212
jhon309 0:ac8863619623 213 \return Floating Point Exception Control register value
jhon309 0:ac8863619623 214 */
jhon309 0:ac8863619623 215 __STATIC_INLINE uint32_t __get_FPEXC(void)
jhon309 0:ac8863619623 216 {
jhon309 0:ac8863619623 217 #if (__FPU_PRESENT == 1)
jhon309 0:ac8863619623 218 register uint32_t __regfpexc __ASM("fpexc");
jhon309 0:ac8863619623 219 return(__regfpexc);
jhon309 0:ac8863619623 220 #else
jhon309 0:ac8863619623 221 return(0);
jhon309 0:ac8863619623 222 #endif
jhon309 0:ac8863619623 223 }
jhon309 0:ac8863619623 224
jhon309 0:ac8863619623 225
jhon309 0:ac8863619623 226 /** \brief Set FPEXC
jhon309 0:ac8863619623 227
jhon309 0:ac8863619623 228 This function assigns the given value to the Floating Point Exception Control register.
jhon309 0:ac8863619623 229
jhon309 0:ac8863619623 230 \param [in] fpscr Floating Point Exception Control value to set
jhon309 0:ac8863619623 231 */
jhon309 0:ac8863619623 232 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
jhon309 0:ac8863619623 233 {
jhon309 0:ac8863619623 234 #if (__FPU_PRESENT == 1)
jhon309 0:ac8863619623 235 register uint32_t __regfpexc __ASM("fpexc");
jhon309 0:ac8863619623 236 __regfpexc = (fpexc);
jhon309 0:ac8863619623 237 #endif
jhon309 0:ac8863619623 238 }
jhon309 0:ac8863619623 239
jhon309 0:ac8863619623 240 /** \brief Get CPACR
jhon309 0:ac8863619623 241
jhon309 0:ac8863619623 242 This function returns the current value of the Coprocessor Access Control register.
jhon309 0:ac8863619623 243
jhon309 0:ac8863619623 244 \return Coprocessor Access Control register value
jhon309 0:ac8863619623 245 */
jhon309 0:ac8863619623 246 __STATIC_INLINE uint32_t __get_CPACR(void)
jhon309 0:ac8863619623 247 {
jhon309 0:ac8863619623 248 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
jhon309 0:ac8863619623 249 return __regCPACR;
jhon309 0:ac8863619623 250 }
jhon309 0:ac8863619623 251
jhon309 0:ac8863619623 252 /** \brief Set CPACR
jhon309 0:ac8863619623 253
jhon309 0:ac8863619623 254 This function assigns the given value to the Coprocessor Access Control register.
jhon309 0:ac8863619623 255
jhon309 0:ac8863619623 256 \param [in] cpacr Coporcessor Acccess Control value to set
jhon309 0:ac8863619623 257 */
jhon309 0:ac8863619623 258 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
jhon309 0:ac8863619623 259 {
jhon309 0:ac8863619623 260 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
jhon309 0:ac8863619623 261 __regCPACR = cpacr;
jhon309 0:ac8863619623 262 __ISB();
jhon309 0:ac8863619623 263 }
jhon309 0:ac8863619623 264
jhon309 0:ac8863619623 265 /** \brief Get CBAR
jhon309 0:ac8863619623 266
jhon309 0:ac8863619623 267 This function returns the value of the Configuration Base Address register.
jhon309 0:ac8863619623 268
jhon309 0:ac8863619623 269 \return Configuration Base Address register value
jhon309 0:ac8863619623 270 */
jhon309 0:ac8863619623 271 __STATIC_INLINE uint32_t __get_CBAR() {
jhon309 0:ac8863619623 272 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
jhon309 0:ac8863619623 273 return(__regCBAR);
jhon309 0:ac8863619623 274 }
jhon309 0:ac8863619623 275
jhon309 0:ac8863619623 276 /** \brief Get TTBR0
jhon309 0:ac8863619623 277
jhon309 0:ac8863619623 278 This function returns the value of the Configuration Base Address register.
jhon309 0:ac8863619623 279
jhon309 0:ac8863619623 280 \return Translation Table Base Register 0 value
jhon309 0:ac8863619623 281 */
jhon309 0:ac8863619623 282 __STATIC_INLINE uint32_t __get_TTBR0() {
jhon309 0:ac8863619623 283 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
jhon309 0:ac8863619623 284 return(__regTTBR0);
jhon309 0:ac8863619623 285 }
jhon309 0:ac8863619623 286
jhon309 0:ac8863619623 287 /** \brief Set TTBR0
jhon309 0:ac8863619623 288
jhon309 0:ac8863619623 289 This function assigns the given value to the Coprocessor Access Control register.
jhon309 0:ac8863619623 290
jhon309 0:ac8863619623 291 \param [in] ttbr0 Translation Table Base Register 0 value to set
jhon309 0:ac8863619623 292 */
jhon309 0:ac8863619623 293 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
jhon309 0:ac8863619623 294 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
jhon309 0:ac8863619623 295 __regTTBR0 = ttbr0;
jhon309 0:ac8863619623 296 __ISB();
jhon309 0:ac8863619623 297 }
jhon309 0:ac8863619623 298
jhon309 0:ac8863619623 299 /** \brief Get DACR
jhon309 0:ac8863619623 300
jhon309 0:ac8863619623 301 This function returns the value of the Domain Access Control Register.
jhon309 0:ac8863619623 302
jhon309 0:ac8863619623 303 \return Domain Access Control Register value
jhon309 0:ac8863619623 304 */
jhon309 0:ac8863619623 305 __STATIC_INLINE uint32_t __get_DACR() {
jhon309 0:ac8863619623 306 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
jhon309 0:ac8863619623 307 return(__regDACR);
jhon309 0:ac8863619623 308 }
jhon309 0:ac8863619623 309
jhon309 0:ac8863619623 310 /** \brief Set DACR
jhon309 0:ac8863619623 311
jhon309 0:ac8863619623 312 This function assigns the given value to the Coprocessor Access Control register.
jhon309 0:ac8863619623 313
jhon309 0:ac8863619623 314 \param [in] dacr Domain Access Control Register value to set
jhon309 0:ac8863619623 315 */
jhon309 0:ac8863619623 316 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
jhon309 0:ac8863619623 317 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
jhon309 0:ac8863619623 318 __regDACR = dacr;
jhon309 0:ac8863619623 319 __ISB();
jhon309 0:ac8863619623 320 }
jhon309 0:ac8863619623 321
jhon309 0:ac8863619623 322 /******************************** Cache and BTAC enable ****************************************************/
jhon309 0:ac8863619623 323
jhon309 0:ac8863619623 324 /** \brief Set SCTLR
jhon309 0:ac8863619623 325
jhon309 0:ac8863619623 326 This function assigns the given value to the System Control Register.
jhon309 0:ac8863619623 327
jhon309 0:ac8863619623 328 \param [in] sctlr System Control Register, value to set
jhon309 0:ac8863619623 329 */
jhon309 0:ac8863619623 330 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
jhon309 0:ac8863619623 331 {
jhon309 0:ac8863619623 332 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
jhon309 0:ac8863619623 333 __regSCTLR = sctlr;
jhon309 0:ac8863619623 334 }
jhon309 0:ac8863619623 335
jhon309 0:ac8863619623 336 /** \brief Get SCTLR
jhon309 0:ac8863619623 337
jhon309 0:ac8863619623 338 This function returns the value of the System Control Register.
jhon309 0:ac8863619623 339
jhon309 0:ac8863619623 340 \return System Control Register value
jhon309 0:ac8863619623 341 */
jhon309 0:ac8863619623 342 __STATIC_INLINE uint32_t __get_SCTLR() {
jhon309 0:ac8863619623 343 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
jhon309 0:ac8863619623 344 return(__regSCTLR);
jhon309 0:ac8863619623 345 }
jhon309 0:ac8863619623 346
jhon309 0:ac8863619623 347 /** \brief Enable Caches
jhon309 0:ac8863619623 348
jhon309 0:ac8863619623 349 Enable Caches
jhon309 0:ac8863619623 350 */
jhon309 0:ac8863619623 351 __STATIC_INLINE void __enable_caches(void) {
jhon309 0:ac8863619623 352 // Set I bit 12 to enable I Cache
jhon309 0:ac8863619623 353 // Set C bit 2 to enable D Cache
jhon309 0:ac8863619623 354 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
jhon309 0:ac8863619623 355 }
jhon309 0:ac8863619623 356
jhon309 0:ac8863619623 357 /** \brief Disable Caches
jhon309 0:ac8863619623 358
jhon309 0:ac8863619623 359 Disable Caches
jhon309 0:ac8863619623 360 */
jhon309 0:ac8863619623 361 __STATIC_INLINE void __disable_caches(void) {
jhon309 0:ac8863619623 362 // Clear I bit 12 to disable I Cache
jhon309 0:ac8863619623 363 // Clear C bit 2 to disable D Cache
jhon309 0:ac8863619623 364 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
jhon309 0:ac8863619623 365 __ISB();
jhon309 0:ac8863619623 366 }
jhon309 0:ac8863619623 367
jhon309 0:ac8863619623 368 /** \brief Enable BTAC
jhon309 0:ac8863619623 369
jhon309 0:ac8863619623 370 Enable BTAC
jhon309 0:ac8863619623 371 */
jhon309 0:ac8863619623 372 __STATIC_INLINE void __enable_btac(void) {
jhon309 0:ac8863619623 373 // Set Z bit 11 to enable branch prediction
jhon309 0:ac8863619623 374 __set_SCTLR( __get_SCTLR() | (1 << 11));
jhon309 0:ac8863619623 375 __ISB();
jhon309 0:ac8863619623 376 }
jhon309 0:ac8863619623 377
jhon309 0:ac8863619623 378 /** \brief Disable BTAC
jhon309 0:ac8863619623 379
jhon309 0:ac8863619623 380 Disable BTAC
jhon309 0:ac8863619623 381 */
jhon309 0:ac8863619623 382 __STATIC_INLINE void __disable_btac(void) {
jhon309 0:ac8863619623 383 // Clear Z bit 11 to disable branch prediction
jhon309 0:ac8863619623 384 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
jhon309 0:ac8863619623 385 }
jhon309 0:ac8863619623 386
jhon309 0:ac8863619623 387
jhon309 0:ac8863619623 388 /** \brief Enable MMU
jhon309 0:ac8863619623 389
jhon309 0:ac8863619623 390 Enable MMU
jhon309 0:ac8863619623 391 */
jhon309 0:ac8863619623 392 __STATIC_INLINE void __enable_mmu(void) {
jhon309 0:ac8863619623 393 // Set M bit 0 to enable the MMU
jhon309 0:ac8863619623 394 // Set AFE bit to enable simplified access permissions model
jhon309 0:ac8863619623 395 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
jhon309 0:ac8863619623 396 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
jhon309 0:ac8863619623 397 __ISB();
jhon309 0:ac8863619623 398 }
jhon309 0:ac8863619623 399
jhon309 0:ac8863619623 400 /** \brief Enable MMU
jhon309 0:ac8863619623 401
jhon309 0:ac8863619623 402 Enable MMU
jhon309 0:ac8863619623 403 */
jhon309 0:ac8863619623 404 __STATIC_INLINE void __disable_mmu(void) {
jhon309 0:ac8863619623 405 // Clear M bit 0 to disable the MMU
jhon309 0:ac8863619623 406 __set_SCTLR( __get_SCTLR() & ~1);
jhon309 0:ac8863619623 407 __ISB();
jhon309 0:ac8863619623 408 }
jhon309 0:ac8863619623 409
jhon309 0:ac8863619623 410 /******************************** TLB maintenance operations ************************************************/
jhon309 0:ac8863619623 411 /** \brief Invalidate the whole tlb
jhon309 0:ac8863619623 412
jhon309 0:ac8863619623 413 TLBIALL. Invalidate the whole tlb
jhon309 0:ac8863619623 414 */
jhon309 0:ac8863619623 415
jhon309 0:ac8863619623 416 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
jhon309 0:ac8863619623 417 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
jhon309 0:ac8863619623 418 __TLBIALL = 0;
jhon309 0:ac8863619623 419 __DSB();
jhon309 0:ac8863619623 420 __ISB();
jhon309 0:ac8863619623 421 }
jhon309 0:ac8863619623 422
jhon309 0:ac8863619623 423 /******************************** BTB maintenance operations ************************************************/
jhon309 0:ac8863619623 424 /** \brief Invalidate entire branch predictor array
jhon309 0:ac8863619623 425
jhon309 0:ac8863619623 426 BPIALL. Branch Predictor Invalidate All.
jhon309 0:ac8863619623 427 */
jhon309 0:ac8863619623 428
jhon309 0:ac8863619623 429 __STATIC_INLINE void __v7_inv_btac(void) {
jhon309 0:ac8863619623 430 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
jhon309 0:ac8863619623 431 __BPIALL = 0;
jhon309 0:ac8863619623 432 __DSB(); //ensure completion of the invalidation
jhon309 0:ac8863619623 433 __ISB(); //ensure instruction fetch path sees new state
jhon309 0:ac8863619623 434 }
jhon309 0:ac8863619623 435
jhon309 0:ac8863619623 436
jhon309 0:ac8863619623 437 /******************************** L1 cache operations ******************************************************/
jhon309 0:ac8863619623 438
jhon309 0:ac8863619623 439 /** \brief Invalidate the whole I$
jhon309 0:ac8863619623 440
jhon309 0:ac8863619623 441 ICIALLU. Instruction Cache Invalidate All to PoU
jhon309 0:ac8863619623 442 */
jhon309 0:ac8863619623 443 __STATIC_INLINE void __v7_inv_icache_all(void) {
jhon309 0:ac8863619623 444 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
jhon309 0:ac8863619623 445 __ICIALLU = 0;
jhon309 0:ac8863619623 446 __DSB(); //ensure completion of the invalidation
jhon309 0:ac8863619623 447 __ISB(); //ensure instruction fetch path sees new I cache state
jhon309 0:ac8863619623 448 }
jhon309 0:ac8863619623 449
jhon309 0:ac8863619623 450 /** \brief Clean D$ by MVA
jhon309 0:ac8863619623 451
jhon309 0:ac8863619623 452 DCCMVAC. Data cache clean by MVA to PoC
jhon309 0:ac8863619623 453 */
jhon309 0:ac8863619623 454 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
jhon309 0:ac8863619623 455 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
jhon309 0:ac8863619623 456 __DCCMVAC = (uint32_t)va;
jhon309 0:ac8863619623 457 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jhon309 0:ac8863619623 458 }
jhon309 0:ac8863619623 459
jhon309 0:ac8863619623 460 /** \brief Invalidate D$ by MVA
jhon309 0:ac8863619623 461
jhon309 0:ac8863619623 462 DCIMVAC. Data cache invalidate by MVA to PoC
jhon309 0:ac8863619623 463 */
jhon309 0:ac8863619623 464 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
jhon309 0:ac8863619623 465 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
jhon309 0:ac8863619623 466 __DCIMVAC = (uint32_t)va;
jhon309 0:ac8863619623 467 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jhon309 0:ac8863619623 468 }
jhon309 0:ac8863619623 469
jhon309 0:ac8863619623 470 /** \brief Clean and Invalidate D$ by MVA
jhon309 0:ac8863619623 471
jhon309 0:ac8863619623 472 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
jhon309 0:ac8863619623 473 */
jhon309 0:ac8863619623 474 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
jhon309 0:ac8863619623 475 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
jhon309 0:ac8863619623 476 __DCCIMVAC = (uint32_t)va;
jhon309 0:ac8863619623 477 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jhon309 0:ac8863619623 478 }
jhon309 0:ac8863619623 479
jhon309 0:ac8863619623 480 /** \brief
jhon309 0:ac8863619623 481 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
jhon309 0:ac8863619623 482 */
jhon309 0:ac8863619623 483 #pragma push
jhon309 0:ac8863619623 484 #pragma arm
jhon309 0:ac8863619623 485 __STATIC_ASM void __v7_all_cache(uint32_t op) {
jhon309 0:ac8863619623 486 ARM
jhon309 0:ac8863619623 487
jhon309 0:ac8863619623 488 PUSH {R4-R11}
jhon309 0:ac8863619623 489
jhon309 0:ac8863619623 490 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
jhon309 0:ac8863619623 491 ANDS R3, R6, #0x07000000 // Extract coherency level
jhon309 0:ac8863619623 492 MOV R3, R3, LSR #23 // Total cache levels << 1
jhon309 0:ac8863619623 493 BEQ Finished // If 0, no need to clean
jhon309 0:ac8863619623 494
jhon309 0:ac8863619623 495 MOV R10, #0 // R10 holds current cache level << 1
jhon309 0:ac8863619623 496 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
jhon309 0:ac8863619623 497 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
jhon309 0:ac8863619623 498 AND R1, R1, #7 // Isolate those lower 3 bits
jhon309 0:ac8863619623 499 CMP R1, #2
jhon309 0:ac8863619623 500 BLT Skip // No cache or only instruction cache at this level
jhon309 0:ac8863619623 501
jhon309 0:ac8863619623 502 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
jhon309 0:ac8863619623 503 ISB // ISB to sync the change to the CacheSizeID reg
jhon309 0:ac8863619623 504 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
jhon309 0:ac8863619623 505 AND R2, R1, #7 // Extract the line length field
jhon309 0:ac8863619623 506 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
jhon309 0:ac8863619623 507 LDR R4, =0x3FF
jhon309 0:ac8863619623 508 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
jhon309 0:ac8863619623 509 CLZ R5, R4 // R5 is the bit position of the way size increment
jhon309 0:ac8863619623 510 LDR R7, =0x7FFF
jhon309 0:ac8863619623 511 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
jhon309 0:ac8863619623 512
jhon309 0:ac8863619623 513 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
jhon309 0:ac8863619623 514
jhon309 0:ac8863619623 515 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
jhon309 0:ac8863619623 516 ORR R11, R11, R7, LSL R2 // Factor in the Set number
jhon309 0:ac8863619623 517 CMP R0, #0
jhon309 0:ac8863619623 518 BNE Dccsw
jhon309 0:ac8863619623 519 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
jhon309 0:ac8863619623 520 B cont
jhon309 0:ac8863619623 521 Dccsw CMP R0, #1
jhon309 0:ac8863619623 522 BNE Dccisw
jhon309 0:ac8863619623 523 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
jhon309 0:ac8863619623 524 B cont
jhon309 0:ac8863619623 525 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way
jhon309 0:ac8863619623 526 cont SUBS R9, R9, #1 // Decrement the Way number
jhon309 0:ac8863619623 527 BGE Loop3
jhon309 0:ac8863619623 528 SUBS R7, R7, #1 // Decrement the Set number
jhon309 0:ac8863619623 529 BGE Loop2
jhon309 0:ac8863619623 530 Skip ADD R10, R10, #2 // increment the cache number
jhon309 0:ac8863619623 531 CMP R3, R10
jhon309 0:ac8863619623 532 BGT Loop1
jhon309 0:ac8863619623 533
jhon309 0:ac8863619623 534 Finished
jhon309 0:ac8863619623 535 DSB
jhon309 0:ac8863619623 536 POP {R4-R11}
jhon309 0:ac8863619623 537 BX lr
jhon309 0:ac8863619623 538
jhon309 0:ac8863619623 539 }
jhon309 0:ac8863619623 540 #pragma pop
jhon309 0:ac8863619623 541
jhon309 0:ac8863619623 542 /** \brief __v7_all_cache - helper function
jhon309 0:ac8863619623 543
jhon309 0:ac8863619623 544 */
jhon309 0:ac8863619623 545
jhon309 0:ac8863619623 546 /** \brief Invalidate the whole D$
jhon309 0:ac8863619623 547
jhon309 0:ac8863619623 548 DCISW. Invalidate by Set/Way
jhon309 0:ac8863619623 549 */
jhon309 0:ac8863619623 550
jhon309 0:ac8863619623 551 __STATIC_INLINE void __v7_inv_dcache_all(void) {
jhon309 0:ac8863619623 552 __v7_all_cache(0);
jhon309 0:ac8863619623 553 }
jhon309 0:ac8863619623 554
jhon309 0:ac8863619623 555 /** \brief Clean the whole D$
jhon309 0:ac8863619623 556
jhon309 0:ac8863619623 557 DCCSW. Clean by Set/Way
jhon309 0:ac8863619623 558 */
jhon309 0:ac8863619623 559
jhon309 0:ac8863619623 560 __STATIC_INLINE void __v7_clean_dcache_all(void) {
jhon309 0:ac8863619623 561 __v7_all_cache(1);
jhon309 0:ac8863619623 562 }
jhon309 0:ac8863619623 563
jhon309 0:ac8863619623 564 /** \brief Clean and invalidate the whole D$
jhon309 0:ac8863619623 565
jhon309 0:ac8863619623 566 DCCISW. Clean and Invalidate by Set/Way
jhon309 0:ac8863619623 567 */
jhon309 0:ac8863619623 568
jhon309 0:ac8863619623 569 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
jhon309 0:ac8863619623 570 __v7_all_cache(2);
jhon309 0:ac8863619623 571 }
jhon309 0:ac8863619623 572
jhon309 0:ac8863619623 573 #include "core_ca_mmu.h"
jhon309 0:ac8863619623 574
jhon309 0:ac8863619623 575 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
jhon309 0:ac8863619623 576
jhon309 0:ac8863619623 577 #error IAR Compiler support not implemented for Cortex-A
jhon309 0:ac8863619623 578
jhon309 0:ac8863619623 579 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
jhon309 0:ac8863619623 580
jhon309 0:ac8863619623 581 /* GNU gcc specific functions */
jhon309 0:ac8863619623 582
jhon309 0:ac8863619623 583 #define MODE_USR 0x10
jhon309 0:ac8863619623 584 #define MODE_FIQ 0x11
jhon309 0:ac8863619623 585 #define MODE_IRQ 0x12
jhon309 0:ac8863619623 586 #define MODE_SVC 0x13
jhon309 0:ac8863619623 587 #define MODE_MON 0x16
jhon309 0:ac8863619623 588 #define MODE_ABT 0x17
jhon309 0:ac8863619623 589 #define MODE_HYP 0x1A
jhon309 0:ac8863619623 590 #define MODE_UND 0x1B
jhon309 0:ac8863619623 591 #define MODE_SYS 0x1F
jhon309 0:ac8863619623 592
jhon309 0:ac8863619623 593
jhon309 0:ac8863619623 594 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
jhon309 0:ac8863619623 595 {
jhon309 0:ac8863619623 596 __ASM volatile ("cpsie i");
jhon309 0:ac8863619623 597 }
jhon309 0:ac8863619623 598
jhon309 0:ac8863619623 599 /** \brief Disable IRQ Interrupts
jhon309 0:ac8863619623 600
jhon309 0:ac8863619623 601 This function disables IRQ interrupts by setting the I-bit in the CPSR.
jhon309 0:ac8863619623 602 Can only be executed in Privileged modes.
jhon309 0:ac8863619623 603 */
jhon309 0:ac8863619623 604 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
jhon309 0:ac8863619623 605 {
jhon309 0:ac8863619623 606 uint32_t result;
jhon309 0:ac8863619623 607
jhon309 0:ac8863619623 608 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
jhon309 0:ac8863619623 609 __ASM volatile ("cpsid i");
jhon309 0:ac8863619623 610 return(result & 0x80);
jhon309 0:ac8863619623 611 }
jhon309 0:ac8863619623 612
jhon309 0:ac8863619623 613
jhon309 0:ac8863619623 614 /** \brief Get APSR Register
jhon309 0:ac8863619623 615
jhon309 0:ac8863619623 616 This function returns the content of the APSR Register.
jhon309 0:ac8863619623 617
jhon309 0:ac8863619623 618 \return APSR Register value
jhon309 0:ac8863619623 619 */
jhon309 0:ac8863619623 620 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
jhon309 0:ac8863619623 621 {
jhon309 0:ac8863619623 622 #if 1
jhon309 0:ac8863619623 623 uint32_t result;
jhon309 0:ac8863619623 624
jhon309 0:ac8863619623 625 __ASM volatile ("mrs %0, apsr" : "=r" (result) );
jhon309 0:ac8863619623 626 return (result);
jhon309 0:ac8863619623 627 #else
jhon309 0:ac8863619623 628 register uint32_t __regAPSR __ASM("apsr");
jhon309 0:ac8863619623 629 return(__regAPSR);
jhon309 0:ac8863619623 630 #endif
jhon309 0:ac8863619623 631 }
jhon309 0:ac8863619623 632
jhon309 0:ac8863619623 633
jhon309 0:ac8863619623 634 /** \brief Get CPSR Register
jhon309 0:ac8863619623 635
jhon309 0:ac8863619623 636 This function returns the content of the CPSR Register.
jhon309 0:ac8863619623 637
jhon309 0:ac8863619623 638 \return CPSR Register value
jhon309 0:ac8863619623 639 */
jhon309 0:ac8863619623 640 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
jhon309 0:ac8863619623 641 {
jhon309 0:ac8863619623 642 #if 1
jhon309 0:ac8863619623 643 register uint32_t __regCPSR;
jhon309 0:ac8863619623 644 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
jhon309 0:ac8863619623 645 #else
jhon309 0:ac8863619623 646 register uint32_t __regCPSR __ASM("cpsr");
jhon309 0:ac8863619623 647 #endif
jhon309 0:ac8863619623 648 return(__regCPSR);
jhon309 0:ac8863619623 649 }
jhon309 0:ac8863619623 650
jhon309 0:ac8863619623 651 #if 0
jhon309 0:ac8863619623 652 /** \brief Set Stack Pointer
jhon309 0:ac8863619623 653
jhon309 0:ac8863619623 654 This function assigns the given value to the current stack pointer.
jhon309 0:ac8863619623 655
jhon309 0:ac8863619623 656 \param [in] topOfStack Stack Pointer value to set
jhon309 0:ac8863619623 657 */
jhon309 0:ac8863619623 658 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
jhon309 0:ac8863619623 659 {
jhon309 0:ac8863619623 660 register uint32_t __regSP __ASM("sp");
jhon309 0:ac8863619623 661 __regSP = topOfStack;
jhon309 0:ac8863619623 662 }
jhon309 0:ac8863619623 663 #endif
jhon309 0:ac8863619623 664
jhon309 0:ac8863619623 665 /** \brief Get link register
jhon309 0:ac8863619623 666
jhon309 0:ac8863619623 667 This function returns the value of the link register
jhon309 0:ac8863619623 668
jhon309 0:ac8863619623 669 \return Value of link register
jhon309 0:ac8863619623 670 */
jhon309 0:ac8863619623 671 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
jhon309 0:ac8863619623 672 {
jhon309 0:ac8863619623 673 register uint32_t __reglr __ASM("lr");
jhon309 0:ac8863619623 674 return(__reglr);
jhon309 0:ac8863619623 675 }
jhon309 0:ac8863619623 676
jhon309 0:ac8863619623 677 #if 0
jhon309 0:ac8863619623 678 /** \brief Set link register
jhon309 0:ac8863619623 679
jhon309 0:ac8863619623 680 This function sets the value of the link register
jhon309 0:ac8863619623 681
jhon309 0:ac8863619623 682 \param [in] lr LR value to set
jhon309 0:ac8863619623 683 */
jhon309 0:ac8863619623 684 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
jhon309 0:ac8863619623 685 {
jhon309 0:ac8863619623 686 register uint32_t __reglr __ASM("lr");
jhon309 0:ac8863619623 687 __reglr = lr;
jhon309 0:ac8863619623 688 }
jhon309 0:ac8863619623 689 #endif
jhon309 0:ac8863619623 690
jhon309 0:ac8863619623 691 /** \brief Set Process Stack Pointer
jhon309 0:ac8863619623 692
jhon309 0:ac8863619623 693 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
jhon309 0:ac8863619623 694
jhon309 0:ac8863619623 695 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
jhon309 0:ac8863619623 696 */
jhon309 0:ac8863619623 697 extern void __set_PSP(uint32_t topOfProcStack);
jhon309 0:ac8863619623 698
jhon309 0:ac8863619623 699 /** \brief Set User Mode
jhon309 0:ac8863619623 700
jhon309 0:ac8863619623 701 This function changes the processor state to User Mode
jhon309 0:ac8863619623 702
jhon309 0:ac8863619623 703 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
jhon309 0:ac8863619623 704 */
jhon309 0:ac8863619623 705 extern void __set_CPS_USR(void);
jhon309 0:ac8863619623 706
jhon309 0:ac8863619623 707 /** \brief Enable FIQ
jhon309 0:ac8863619623 708
jhon309 0:ac8863619623 709 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
jhon309 0:ac8863619623 710 Can only be executed in Privileged modes.
jhon309 0:ac8863619623 711 */
jhon309 0:ac8863619623 712 #define __enable_fault_irq __enable_fiq
jhon309 0:ac8863619623 713
jhon309 0:ac8863619623 714
jhon309 0:ac8863619623 715 /** \brief Disable FIQ
jhon309 0:ac8863619623 716
jhon309 0:ac8863619623 717 This function disables FIQ interrupts by setting the F-bit in the CPSR.
jhon309 0:ac8863619623 718 Can only be executed in Privileged modes.
jhon309 0:ac8863619623 719 */
jhon309 0:ac8863619623 720 #define __disable_fault_irq __disable_fiq
jhon309 0:ac8863619623 721
jhon309 0:ac8863619623 722
jhon309 0:ac8863619623 723 /** \brief Get FPSCR
jhon309 0:ac8863619623 724
jhon309 0:ac8863619623 725 This function returns the current value of the Floating Point Status/Control register.
jhon309 0:ac8863619623 726
jhon309 0:ac8863619623 727 \return Floating Point Status/Control register value
jhon309 0:ac8863619623 728 */
jhon309 0:ac8863619623 729 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
jhon309 0:ac8863619623 730 {
jhon309 0:ac8863619623 731 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jhon309 0:ac8863619623 732 #if 1
jhon309 0:ac8863619623 733 uint32_t result;
jhon309 0:ac8863619623 734
jhon309 0:ac8863619623 735 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
jhon309 0:ac8863619623 736 return (result);
jhon309 0:ac8863619623 737 #else
jhon309 0:ac8863619623 738 register uint32_t __regfpscr __ASM("fpscr");
jhon309 0:ac8863619623 739 return(__regfpscr);
jhon309 0:ac8863619623 740 #endif
jhon309 0:ac8863619623 741 #else
jhon309 0:ac8863619623 742 return(0);
jhon309 0:ac8863619623 743 #endif
jhon309 0:ac8863619623 744 }
jhon309 0:ac8863619623 745
jhon309 0:ac8863619623 746
jhon309 0:ac8863619623 747 /** \brief Set FPSCR
jhon309 0:ac8863619623 748
jhon309 0:ac8863619623 749 This function assigns the given value to the Floating Point Status/Control register.
jhon309 0:ac8863619623 750
jhon309 0:ac8863619623 751 \param [in] fpscr Floating Point Status/Control value to set
jhon309 0:ac8863619623 752 */
jhon309 0:ac8863619623 753 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
jhon309 0:ac8863619623 754 {
jhon309 0:ac8863619623 755 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jhon309 0:ac8863619623 756 #if 1
jhon309 0:ac8863619623 757 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
jhon309 0:ac8863619623 758 #else
jhon309 0:ac8863619623 759 register uint32_t __regfpscr __ASM("fpscr");
jhon309 0:ac8863619623 760 __regfpscr = (fpscr);
jhon309 0:ac8863619623 761 #endif
jhon309 0:ac8863619623 762 #endif
jhon309 0:ac8863619623 763 }
jhon309 0:ac8863619623 764
jhon309 0:ac8863619623 765 /** \brief Get FPEXC
jhon309 0:ac8863619623 766
jhon309 0:ac8863619623 767 This function returns the current value of the Floating Point Exception Control register.
jhon309 0:ac8863619623 768
jhon309 0:ac8863619623 769 \return Floating Point Exception Control register value
jhon309 0:ac8863619623 770 */
jhon309 0:ac8863619623 771 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
jhon309 0:ac8863619623 772 {
jhon309 0:ac8863619623 773 #if (__FPU_PRESENT == 1)
jhon309 0:ac8863619623 774 #if 1
jhon309 0:ac8863619623 775 uint32_t result;
jhon309 0:ac8863619623 776
jhon309 0:ac8863619623 777 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
jhon309 0:ac8863619623 778 return (result);
jhon309 0:ac8863619623 779 #else
jhon309 0:ac8863619623 780 register uint32_t __regfpexc __ASM("fpexc");
jhon309 0:ac8863619623 781 return(__regfpexc);
jhon309 0:ac8863619623 782 #endif
jhon309 0:ac8863619623 783 #else
jhon309 0:ac8863619623 784 return(0);
jhon309 0:ac8863619623 785 #endif
jhon309 0:ac8863619623 786 }
jhon309 0:ac8863619623 787
jhon309 0:ac8863619623 788
jhon309 0:ac8863619623 789 /** \brief Set FPEXC
jhon309 0:ac8863619623 790
jhon309 0:ac8863619623 791 This function assigns the given value to the Floating Point Exception Control register.
jhon309 0:ac8863619623 792
jhon309 0:ac8863619623 793 \param [in] fpscr Floating Point Exception Control value to set
jhon309 0:ac8863619623 794 */
jhon309 0:ac8863619623 795 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
jhon309 0:ac8863619623 796 {
jhon309 0:ac8863619623 797 #if (__FPU_PRESENT == 1)
jhon309 0:ac8863619623 798 #if 1
jhon309 0:ac8863619623 799 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
jhon309 0:ac8863619623 800 #else
jhon309 0:ac8863619623 801 register uint32_t __regfpexc __ASM("fpexc");
jhon309 0:ac8863619623 802 __regfpexc = (fpexc);
jhon309 0:ac8863619623 803 #endif
jhon309 0:ac8863619623 804 #endif
jhon309 0:ac8863619623 805 }
jhon309 0:ac8863619623 806
jhon309 0:ac8863619623 807 /** \brief Get CPACR
jhon309 0:ac8863619623 808
jhon309 0:ac8863619623 809 This function returns the current value of the Coprocessor Access Control register.
jhon309 0:ac8863619623 810
jhon309 0:ac8863619623 811 \return Coprocessor Access Control register value
jhon309 0:ac8863619623 812 */
jhon309 0:ac8863619623 813 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
jhon309 0:ac8863619623 814 {
jhon309 0:ac8863619623 815 #if 1
jhon309 0:ac8863619623 816 register uint32_t __regCPACR;
jhon309 0:ac8863619623 817 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
jhon309 0:ac8863619623 818 #else
jhon309 0:ac8863619623 819 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
jhon309 0:ac8863619623 820 #endif
jhon309 0:ac8863619623 821 return __regCPACR;
jhon309 0:ac8863619623 822 }
jhon309 0:ac8863619623 823
jhon309 0:ac8863619623 824 /** \brief Set CPACR
jhon309 0:ac8863619623 825
jhon309 0:ac8863619623 826 This function assigns the given value to the Coprocessor Access Control register.
jhon309 0:ac8863619623 827
jhon309 0:ac8863619623 828 \param [in] cpacr Coporcessor Acccess Control value to set
jhon309 0:ac8863619623 829 */
jhon309 0:ac8863619623 830 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
jhon309 0:ac8863619623 831 {
jhon309 0:ac8863619623 832 #if 1
jhon309 0:ac8863619623 833 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
jhon309 0:ac8863619623 834 #else
jhon309 0:ac8863619623 835 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
jhon309 0:ac8863619623 836 __regCPACR = cpacr;
jhon309 0:ac8863619623 837 #endif
jhon309 0:ac8863619623 838 __ISB();
jhon309 0:ac8863619623 839 }
jhon309 0:ac8863619623 840
jhon309 0:ac8863619623 841 /** \brief Get CBAR
jhon309 0:ac8863619623 842
jhon309 0:ac8863619623 843 This function returns the value of the Configuration Base Address register.
jhon309 0:ac8863619623 844
jhon309 0:ac8863619623 845 \return Configuration Base Address register value
jhon309 0:ac8863619623 846 */
jhon309 0:ac8863619623 847 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
jhon309 0:ac8863619623 848 #if 1
jhon309 0:ac8863619623 849 register uint32_t __regCBAR;
jhon309 0:ac8863619623 850 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
jhon309 0:ac8863619623 851 #else
jhon309 0:ac8863619623 852 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
jhon309 0:ac8863619623 853 #endif
jhon309 0:ac8863619623 854 return(__regCBAR);
jhon309 0:ac8863619623 855 }
jhon309 0:ac8863619623 856
jhon309 0:ac8863619623 857 /** \brief Get TTBR0
jhon309 0:ac8863619623 858
jhon309 0:ac8863619623 859 This function returns the value of the Configuration Base Address register.
jhon309 0:ac8863619623 860
jhon309 0:ac8863619623 861 \return Translation Table Base Register 0 value
jhon309 0:ac8863619623 862 */
jhon309 0:ac8863619623 863 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
jhon309 0:ac8863619623 864 #if 1
jhon309 0:ac8863619623 865 register uint32_t __regTTBR0;
jhon309 0:ac8863619623 866 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
jhon309 0:ac8863619623 867 #else
jhon309 0:ac8863619623 868 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
jhon309 0:ac8863619623 869 #endif
jhon309 0:ac8863619623 870 return(__regTTBR0);
jhon309 0:ac8863619623 871 }
jhon309 0:ac8863619623 872
jhon309 0:ac8863619623 873 /** \brief Set TTBR0
jhon309 0:ac8863619623 874
jhon309 0:ac8863619623 875 This function assigns the given value to the Coprocessor Access Control register.
jhon309 0:ac8863619623 876
jhon309 0:ac8863619623 877 \param [in] ttbr0 Translation Table Base Register 0 value to set
jhon309 0:ac8863619623 878 */
jhon309 0:ac8863619623 879 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
jhon309 0:ac8863619623 880 #if 1
jhon309 0:ac8863619623 881 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
jhon309 0:ac8863619623 882 #else
jhon309 0:ac8863619623 883 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
jhon309 0:ac8863619623 884 __regTTBR0 = ttbr0;
jhon309 0:ac8863619623 885 #endif
jhon309 0:ac8863619623 886 __ISB();
jhon309 0:ac8863619623 887 }
jhon309 0:ac8863619623 888
jhon309 0:ac8863619623 889 /** \brief Get DACR
jhon309 0:ac8863619623 890
jhon309 0:ac8863619623 891 This function returns the value of the Domain Access Control Register.
jhon309 0:ac8863619623 892
jhon309 0:ac8863619623 893 \return Domain Access Control Register value
jhon309 0:ac8863619623 894 */
jhon309 0:ac8863619623 895 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
jhon309 0:ac8863619623 896 #if 1
jhon309 0:ac8863619623 897 register uint32_t __regDACR;
jhon309 0:ac8863619623 898 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
jhon309 0:ac8863619623 899 #else
jhon309 0:ac8863619623 900 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
jhon309 0:ac8863619623 901 #endif
jhon309 0:ac8863619623 902 return(__regDACR);
jhon309 0:ac8863619623 903 }
jhon309 0:ac8863619623 904
jhon309 0:ac8863619623 905 /** \brief Set DACR
jhon309 0:ac8863619623 906
jhon309 0:ac8863619623 907 This function assigns the given value to the Coprocessor Access Control register.
jhon309 0:ac8863619623 908
jhon309 0:ac8863619623 909 \param [in] dacr Domain Access Control Register value to set
jhon309 0:ac8863619623 910 */
jhon309 0:ac8863619623 911 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
jhon309 0:ac8863619623 912 #if 1
jhon309 0:ac8863619623 913 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
jhon309 0:ac8863619623 914 #else
jhon309 0:ac8863619623 915 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
jhon309 0:ac8863619623 916 __regDACR = dacr;
jhon309 0:ac8863619623 917 #endif
jhon309 0:ac8863619623 918 __ISB();
jhon309 0:ac8863619623 919 }
jhon309 0:ac8863619623 920
jhon309 0:ac8863619623 921 /******************************** Cache and BTAC enable ****************************************************/
jhon309 0:ac8863619623 922
jhon309 0:ac8863619623 923 /** \brief Set SCTLR
jhon309 0:ac8863619623 924
jhon309 0:ac8863619623 925 This function assigns the given value to the System Control Register.
jhon309 0:ac8863619623 926
jhon309 0:ac8863619623 927 \param [in] sctlr System Control Register, value to set
jhon309 0:ac8863619623 928 */
jhon309 0:ac8863619623 929 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
jhon309 0:ac8863619623 930 {
jhon309 0:ac8863619623 931 #if 1
jhon309 0:ac8863619623 932 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
jhon309 0:ac8863619623 933 #else
jhon309 0:ac8863619623 934 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
jhon309 0:ac8863619623 935 __regSCTLR = sctlr;
jhon309 0:ac8863619623 936 #endif
jhon309 0:ac8863619623 937 }
jhon309 0:ac8863619623 938
jhon309 0:ac8863619623 939 /** \brief Get SCTLR
jhon309 0:ac8863619623 940
jhon309 0:ac8863619623 941 This function returns the value of the System Control Register.
jhon309 0:ac8863619623 942
jhon309 0:ac8863619623 943 \return System Control Register value
jhon309 0:ac8863619623 944 */
jhon309 0:ac8863619623 945 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
jhon309 0:ac8863619623 946 #if 1
jhon309 0:ac8863619623 947 register uint32_t __regSCTLR;
jhon309 0:ac8863619623 948 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
jhon309 0:ac8863619623 949 #else
jhon309 0:ac8863619623 950 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
jhon309 0:ac8863619623 951 #endif
jhon309 0:ac8863619623 952 return(__regSCTLR);
jhon309 0:ac8863619623 953 }
jhon309 0:ac8863619623 954
jhon309 0:ac8863619623 955 /** \brief Enable Caches
jhon309 0:ac8863619623 956
jhon309 0:ac8863619623 957 Enable Caches
jhon309 0:ac8863619623 958 */
jhon309 0:ac8863619623 959 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
jhon309 0:ac8863619623 960 // Set I bit 12 to enable I Cache
jhon309 0:ac8863619623 961 // Set C bit 2 to enable D Cache
jhon309 0:ac8863619623 962 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
jhon309 0:ac8863619623 963 }
jhon309 0:ac8863619623 964
jhon309 0:ac8863619623 965 /** \brief Disable Caches
jhon309 0:ac8863619623 966
jhon309 0:ac8863619623 967 Disable Caches
jhon309 0:ac8863619623 968 */
jhon309 0:ac8863619623 969 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
jhon309 0:ac8863619623 970 // Clear I bit 12 to disable I Cache
jhon309 0:ac8863619623 971 // Clear C bit 2 to disable D Cache
jhon309 0:ac8863619623 972 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
jhon309 0:ac8863619623 973 __ISB();
jhon309 0:ac8863619623 974 }
jhon309 0:ac8863619623 975
jhon309 0:ac8863619623 976 /** \brief Enable BTAC
jhon309 0:ac8863619623 977
jhon309 0:ac8863619623 978 Enable BTAC
jhon309 0:ac8863619623 979 */
jhon309 0:ac8863619623 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
jhon309 0:ac8863619623 981 // Set Z bit 11 to enable branch prediction
jhon309 0:ac8863619623 982 __set_SCTLR( __get_SCTLR() | (1 << 11));
jhon309 0:ac8863619623 983 __ISB();
jhon309 0:ac8863619623 984 }
jhon309 0:ac8863619623 985
jhon309 0:ac8863619623 986 /** \brief Disable BTAC
jhon309 0:ac8863619623 987
jhon309 0:ac8863619623 988 Disable BTAC
jhon309 0:ac8863619623 989 */
jhon309 0:ac8863619623 990 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
jhon309 0:ac8863619623 991 // Clear Z bit 11 to disable branch prediction
jhon309 0:ac8863619623 992 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
jhon309 0:ac8863619623 993 }
jhon309 0:ac8863619623 994
jhon309 0:ac8863619623 995
jhon309 0:ac8863619623 996 /** \brief Enable MMU
jhon309 0:ac8863619623 997
jhon309 0:ac8863619623 998 Enable MMU
jhon309 0:ac8863619623 999 */
jhon309 0:ac8863619623 1000 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
jhon309 0:ac8863619623 1001 // Set M bit 0 to enable the MMU
jhon309 0:ac8863619623 1002 // Set AFE bit to enable simplified access permissions model
jhon309 0:ac8863619623 1003 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
jhon309 0:ac8863619623 1004 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
jhon309 0:ac8863619623 1005 __ISB();
jhon309 0:ac8863619623 1006 }
jhon309 0:ac8863619623 1007
jhon309 0:ac8863619623 1008 /** \brief Enable MMU
jhon309 0:ac8863619623 1009
jhon309 0:ac8863619623 1010 Enable MMU
jhon309 0:ac8863619623 1011 */
jhon309 0:ac8863619623 1012 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
jhon309 0:ac8863619623 1013 // Clear M bit 0 to disable the MMU
jhon309 0:ac8863619623 1014 __set_SCTLR( __get_SCTLR() & ~1);
jhon309 0:ac8863619623 1015 __ISB();
jhon309 0:ac8863619623 1016 }
jhon309 0:ac8863619623 1017
jhon309 0:ac8863619623 1018 /******************************** TLB maintenance operations ************************************************/
jhon309 0:ac8863619623 1019 /** \brief Invalidate the whole tlb
jhon309 0:ac8863619623 1020
jhon309 0:ac8863619623 1021 TLBIALL. Invalidate the whole tlb
jhon309 0:ac8863619623 1022 */
jhon309 0:ac8863619623 1023
jhon309 0:ac8863619623 1024 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
jhon309 0:ac8863619623 1025 #if 1
jhon309 0:ac8863619623 1026 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
jhon309 0:ac8863619623 1027 #else
jhon309 0:ac8863619623 1028 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
jhon309 0:ac8863619623 1029 __TLBIALL = 0;
jhon309 0:ac8863619623 1030 #endif
jhon309 0:ac8863619623 1031 __DSB();
jhon309 0:ac8863619623 1032 __ISB();
jhon309 0:ac8863619623 1033 }
jhon309 0:ac8863619623 1034
jhon309 0:ac8863619623 1035 /******************************** BTB maintenance operations ************************************************/
jhon309 0:ac8863619623 1036 /** \brief Invalidate entire branch predictor array
jhon309 0:ac8863619623 1037
jhon309 0:ac8863619623 1038 BPIALL. Branch Predictor Invalidate All.
jhon309 0:ac8863619623 1039 */
jhon309 0:ac8863619623 1040
jhon309 0:ac8863619623 1041 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
jhon309 0:ac8863619623 1042 #if 1
jhon309 0:ac8863619623 1043 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
jhon309 0:ac8863619623 1044 #else
jhon309 0:ac8863619623 1045 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
jhon309 0:ac8863619623 1046 __BPIALL = 0;
jhon309 0:ac8863619623 1047 #endif
jhon309 0:ac8863619623 1048 __DSB(); //ensure completion of the invalidation
jhon309 0:ac8863619623 1049 __ISB(); //ensure instruction fetch path sees new state
jhon309 0:ac8863619623 1050 }
jhon309 0:ac8863619623 1051
jhon309 0:ac8863619623 1052
jhon309 0:ac8863619623 1053 /******************************** L1 cache operations ******************************************************/
jhon309 0:ac8863619623 1054
jhon309 0:ac8863619623 1055 /** \brief Invalidate the whole I$
jhon309 0:ac8863619623 1056
jhon309 0:ac8863619623 1057 ICIALLU. Instruction Cache Invalidate All to PoU
jhon309 0:ac8863619623 1058 */
jhon309 0:ac8863619623 1059 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
jhon309 0:ac8863619623 1060 #if 1
jhon309 0:ac8863619623 1061 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
jhon309 0:ac8863619623 1062 #else
jhon309 0:ac8863619623 1063 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
jhon309 0:ac8863619623 1064 __ICIALLU = 0;
jhon309 0:ac8863619623 1065 #endif
jhon309 0:ac8863619623 1066 __DSB(); //ensure completion of the invalidation
jhon309 0:ac8863619623 1067 __ISB(); //ensure instruction fetch path sees new I cache state
jhon309 0:ac8863619623 1068 }
jhon309 0:ac8863619623 1069
jhon309 0:ac8863619623 1070 /** \brief Clean D$ by MVA
jhon309 0:ac8863619623 1071
jhon309 0:ac8863619623 1072 DCCMVAC. Data cache clean by MVA to PoC
jhon309 0:ac8863619623 1073 */
jhon309 0:ac8863619623 1074 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
jhon309 0:ac8863619623 1075 #if 1
jhon309 0:ac8863619623 1076 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
jhon309 0:ac8863619623 1077 #else
jhon309 0:ac8863619623 1078 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
jhon309 0:ac8863619623 1079 __DCCMVAC = (uint32_t)va;
jhon309 0:ac8863619623 1080 #endif
jhon309 0:ac8863619623 1081 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jhon309 0:ac8863619623 1082 }
jhon309 0:ac8863619623 1083
jhon309 0:ac8863619623 1084 /** \brief Invalidate D$ by MVA
jhon309 0:ac8863619623 1085
jhon309 0:ac8863619623 1086 DCIMVAC. Data cache invalidate by MVA to PoC
jhon309 0:ac8863619623 1087 */
jhon309 0:ac8863619623 1088 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
jhon309 0:ac8863619623 1089 #if 1
jhon309 0:ac8863619623 1090 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
jhon309 0:ac8863619623 1091 #else
jhon309 0:ac8863619623 1092 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
jhon309 0:ac8863619623 1093 __DCIMVAC = (uint32_t)va;
jhon309 0:ac8863619623 1094 #endif
jhon309 0:ac8863619623 1095 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jhon309 0:ac8863619623 1096 }
jhon309 0:ac8863619623 1097
jhon309 0:ac8863619623 1098 /** \brief Clean and Invalidate D$ by MVA
jhon309 0:ac8863619623 1099
jhon309 0:ac8863619623 1100 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
jhon309 0:ac8863619623 1101 */
jhon309 0:ac8863619623 1102 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
jhon309 0:ac8863619623 1103 #if 1
jhon309 0:ac8863619623 1104 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
jhon309 0:ac8863619623 1105 #else
jhon309 0:ac8863619623 1106 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
jhon309 0:ac8863619623 1107 __DCCIMVAC = (uint32_t)va;
jhon309 0:ac8863619623 1108 #endif
jhon309 0:ac8863619623 1109 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jhon309 0:ac8863619623 1110 }
jhon309 0:ac8863619623 1111
jhon309 0:ac8863619623 1112 /** \brief
jhon309 0:ac8863619623 1113 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
jhon309 0:ac8863619623 1114 */
jhon309 0:ac8863619623 1115
jhon309 0:ac8863619623 1116 /** \brief __v7_all_cache - helper function
jhon309 0:ac8863619623 1117
jhon309 0:ac8863619623 1118 */
jhon309 0:ac8863619623 1119
jhon309 0:ac8863619623 1120 extern void __v7_all_cache(uint32_t op);
jhon309 0:ac8863619623 1121
jhon309 0:ac8863619623 1122
jhon309 0:ac8863619623 1123 /** \brief Invalidate the whole D$
jhon309 0:ac8863619623 1124
jhon309 0:ac8863619623 1125 DCISW. Invalidate by Set/Way
jhon309 0:ac8863619623 1126 */
jhon309 0:ac8863619623 1127
jhon309 0:ac8863619623 1128 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
jhon309 0:ac8863619623 1129 __v7_all_cache(0);
jhon309 0:ac8863619623 1130 }
jhon309 0:ac8863619623 1131
jhon309 0:ac8863619623 1132 /** \brief Clean the whole D$
jhon309 0:ac8863619623 1133
jhon309 0:ac8863619623 1134 DCCSW. Clean by Set/Way
jhon309 0:ac8863619623 1135 */
jhon309 0:ac8863619623 1136
jhon309 0:ac8863619623 1137 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
jhon309 0:ac8863619623 1138 __v7_all_cache(1);
jhon309 0:ac8863619623 1139 }
jhon309 0:ac8863619623 1140
jhon309 0:ac8863619623 1141 /** \brief Clean and invalidate the whole D$
jhon309 0:ac8863619623 1142
jhon309 0:ac8863619623 1143 DCCISW. Clean and Invalidate by Set/Way
jhon309 0:ac8863619623 1144 */
jhon309 0:ac8863619623 1145
jhon309 0:ac8863619623 1146 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
jhon309 0:ac8863619623 1147 __v7_all_cache(2);
jhon309 0:ac8863619623 1148 }
jhon309 0:ac8863619623 1149
jhon309 0:ac8863619623 1150 #include "core_ca_mmu.h"
jhon309 0:ac8863619623 1151
jhon309 0:ac8863619623 1152 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
jhon309 0:ac8863619623 1153
jhon309 0:ac8863619623 1154 #error TASKING Compiler support not implemented for Cortex-A
jhon309 0:ac8863619623 1155
jhon309 0:ac8863619623 1156 #endif
jhon309 0:ac8863619623 1157
jhon309 0:ac8863619623 1158 /*@} end of CMSIS_Core_RegAccFunctions */
jhon309 0:ac8863619623 1159
jhon309 0:ac8863619623 1160
jhon309 0:ac8863619623 1161 #endif /* __CORE_CAFUNC_H__ */