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TARGET_NUCLEO_F072RB/stm32f0xx_hal_tim.h@0:c52df770855b, 2015-08-13 (annotated)

Committer:: jhon309
Date:: Thu Aug 13 00:21:57 2015 +0000
Revision:: 0:c52df770855b

DHT11

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jhon309	0:c52df770855b	1	/**
jhon309	0:c52df770855b	2	******************************************************************************
jhon309	0:c52df770855b	3	* @file stm32f0xx_hal_tim.h
jhon309	0:c52df770855b	4	* @author MCD Application Team
jhon309	0:c52df770855b	5	* @version V1.2.0
jhon309	0:c52df770855b	6	* @date 11-December-2014
jhon309	0:c52df770855b	7	* @brief Header file of TIM HAL module.
jhon309	0:c52df770855b	8	******************************************************************************
jhon309	0:c52df770855b	9	* @attention
jhon309	0:c52df770855b	10	*
jhon309	0:c52df770855b	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
jhon309	0:c52df770855b	12	*
jhon309	0:c52df770855b	13	* Redistribution and use in source and binary forms, with or without modification,
jhon309	0:c52df770855b	14	* are permitted provided that the following conditions are met:
jhon309	0:c52df770855b	15	* 1. Redistributions of source code must retain the above copyright notice,
jhon309	0:c52df770855b	16	* this list of conditions and the following disclaimer.
jhon309	0:c52df770855b	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
jhon309	0:c52df770855b	18	* this list of conditions and the following disclaimer in the documentation
jhon309	0:c52df770855b	19	* and/or other materials provided with the distribution.
jhon309	0:c52df770855b	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
jhon309	0:c52df770855b	21	* may be used to endorse or promote products derived from this software
jhon309	0:c52df770855b	22	* without specific prior written permission.
jhon309	0:c52df770855b	23	*
jhon309	0:c52df770855b	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jhon309	0:c52df770855b	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jhon309	0:c52df770855b	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
jhon309	0:c52df770855b	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
jhon309	0:c52df770855b	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
jhon309	0:c52df770855b	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
jhon309	0:c52df770855b	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
jhon309	0:c52df770855b	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
jhon309	0:c52df770855b	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
jhon309	0:c52df770855b	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
jhon309	0:c52df770855b	34	*
jhon309	0:c52df770855b	35	******************************************************************************
jhon309	0:c52df770855b	36	*/
jhon309	0:c52df770855b	37
jhon309	0:c52df770855b	38	/* Define to prevent recursive inclusion -------------------------------------*/
jhon309	0:c52df770855b	39	#ifndef __STM32F0xx_HAL_TIM_H
jhon309	0:c52df770855b	40	#define __STM32F0xx_HAL_TIM_H
jhon309	0:c52df770855b	41
jhon309	0:c52df770855b	42	#ifdef __cplusplus
jhon309	0:c52df770855b	43	extern "C" {
jhon309	0:c52df770855b	44	#endif
jhon309	0:c52df770855b	45
jhon309	0:c52df770855b	46	/* Includes ------------------------------------------------------------------*/
jhon309	0:c52df770855b	47	#include "stm32f0xx_hal_def.h"
jhon309	0:c52df770855b	48
jhon309	0:c52df770855b	49	/** @addtogroup STM32F0xx_HAL_Driver
jhon309	0:c52df770855b	50	* @{
jhon309	0:c52df770855b	51	*/
jhon309	0:c52df770855b	52
jhon309	0:c52df770855b	53	/** @addtogroup TIM
jhon309	0:c52df770855b	54	* @{
jhon309	0:c52df770855b	55	*/
jhon309	0:c52df770855b	56
jhon309	0:c52df770855b	57	/* Exported types ------------------------------------------------------------*/
jhon309	0:c52df770855b	58	/** @defgroup TIM_Exported_Types TIM Exported Types
jhon309	0:c52df770855b	59	* @{
jhon309	0:c52df770855b	60	*/
jhon309	0:c52df770855b	61
jhon309	0:c52df770855b	62	/**
jhon309	0:c52df770855b	63	* @brief TIM Time base Configuration Structure definition
jhon309	0:c52df770855b	64	*/
jhon309	0:c52df770855b	65	typedef struct
jhon309	0:c52df770855b	66	{
jhon309	0:c52df770855b	67	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
jhon309	0:c52df770855b	68	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
jhon309	0:c52df770855b	69
jhon309	0:c52df770855b	70	uint32_t CounterMode; /*!< Specifies the counter mode.
jhon309	0:c52df770855b	71	This parameter can be a value of @ref TIM_Counter_Mode */
jhon309	0:c52df770855b	72
jhon309	0:c52df770855b	73	uint32_t Period; /*!< Specifies the period value to be loaded into the active
jhon309	0:c52df770855b	74	Auto-Reload Register at the next update event.
jhon309	0:c52df770855b	75	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
jhon309	0:c52df770855b	76
jhon309	0:c52df770855b	77	uint32_t ClockDivision; /*!< Specifies the clock division.
jhon309	0:c52df770855b	78	This parameter can be a value of @ref TIM_ClockDivision */
jhon309	0:c52df770855b	79
jhon309	0:c52df770855b	80	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
jhon309	0:c52df770855b	81	reaches zero, an update event is generated and counting restarts
jhon309	0:c52df770855b	82	from the RCR value (N).
jhon309	0:c52df770855b	83	This means in PWM mode that (N+1) corresponds to:
jhon309	0:c52df770855b	84	- the number of PWM periods in edge-aligned mode
jhon309	0:c52df770855b	85	- the number of half PWM period in center-aligned mode
jhon309	0:c52df770855b	86	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
jhon309	0:c52df770855b	87	@note This parameter is valid only for TIM1 and TIM8. */
jhon309	0:c52df770855b	88	} TIM_Base_InitTypeDef;
jhon309	0:c52df770855b	89
jhon309	0:c52df770855b	90	/**
jhon309	0:c52df770855b	91	* @brief TIM Output Compare Configuration Structure definition
jhon309	0:c52df770855b	92	*/
jhon309	0:c52df770855b	93	typedef struct
jhon309	0:c52df770855b	94	{
jhon309	0:c52df770855b	95	uint32_t OCMode; /*!< Specifies the TIM mode.
jhon309	0:c52df770855b	96	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
jhon309	0:c52df770855b	97
jhon309	0:c52df770855b	98	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
jhon309	0:c52df770855b	99	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
jhon309	0:c52df770855b	100
jhon309	0:c52df770855b	101	uint32_t OCPolarity; /*!< Specifies the output polarity.
jhon309	0:c52df770855b	102	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
jhon309	0:c52df770855b	103
jhon309	0:c52df770855b	104	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
jhon309	0:c52df770855b	105	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
jhon309	0:c52df770855b	106	@note This parameter is valid only for TIM1 and TIM8. */
jhon309	0:c52df770855b	107
jhon309	0:c52df770855b	108	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
jhon309	0:c52df770855b	109	This parameter can be a value of @ref TIM_Output_Fast_State
jhon309	0:c52df770855b	110	@note This parameter is valid only in PWM1 and PWM2 mode. */
jhon309	0:c52df770855b	111
jhon309	0:c52df770855b	112
jhon309	0:c52df770855b	113	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
jhon309	0:c52df770855b	114	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
jhon309	0:c52df770855b	115	@note This parameter is valid only for TIM1 and TIM8. */
jhon309	0:c52df770855b	116
jhon309	0:c52df770855b	117	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
jhon309	0:c52df770855b	118	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
jhon309	0:c52df770855b	119	@note This parameter is valid only for TIM1 and TIM8. */
jhon309	0:c52df770855b	120	} TIM_OC_InitTypeDef;
jhon309	0:c52df770855b	121
jhon309	0:c52df770855b	122	/**
jhon309	0:c52df770855b	123	* @brief TIM One Pulse Mode Configuration Structure definition
jhon309	0:c52df770855b	124	*/
jhon309	0:c52df770855b	125	typedef struct
jhon309	0:c52df770855b	126	{
jhon309	0:c52df770855b	127	uint32_t OCMode; /*!< Specifies the TIM mode.
jhon309	0:c52df770855b	128	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
jhon309	0:c52df770855b	129
jhon309	0:c52df770855b	130	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
jhon309	0:c52df770855b	131	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
jhon309	0:c52df770855b	132
jhon309	0:c52df770855b	133	uint32_t OCPolarity; /*!< Specifies the output polarity.
jhon309	0:c52df770855b	134	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
jhon309	0:c52df770855b	135
jhon309	0:c52df770855b	136	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
jhon309	0:c52df770855b	137	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
jhon309	0:c52df770855b	138	@note This parameter is valid only for TIM1 and TIM8. */
jhon309	0:c52df770855b	139
jhon309	0:c52df770855b	140	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
jhon309	0:c52df770855b	141	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
jhon309	0:c52df770855b	142	@note This parameter is valid only for TIM1 and TIM8. */
jhon309	0:c52df770855b	143
jhon309	0:c52df770855b	144	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
jhon309	0:c52df770855b	145	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
jhon309	0:c52df770855b	146	@note This parameter is valid only for TIM1 and TIM8. */
jhon309	0:c52df770855b	147
jhon309	0:c52df770855b	148	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
jhon309	0:c52df770855b	149	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
jhon309	0:c52df770855b	150
jhon309	0:c52df770855b	151	uint32_t ICSelection; /*!< Specifies the input.
jhon309	0:c52df770855b	152	This parameter can be a value of @ref TIM_Input_Capture_Selection */
jhon309	0:c52df770855b	153
jhon309	0:c52df770855b	154	uint32_t ICFilter; /*!< Specifies the input capture filter.
jhon309	0:c52df770855b	155	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
jhon309	0:c52df770855b	156	} TIM_OnePulse_InitTypeDef;
jhon309	0:c52df770855b	157
jhon309	0:c52df770855b	158
jhon309	0:c52df770855b	159	/**
jhon309	0:c52df770855b	160	* @brief TIM Input Capture Configuration Structure definition
jhon309	0:c52df770855b	161	*/
jhon309	0:c52df770855b	162	typedef struct
jhon309	0:c52df770855b	163	{
jhon309	0:c52df770855b	164	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
jhon309	0:c52df770855b	165	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
jhon309	0:c52df770855b	166
jhon309	0:c52df770855b	167	uint32_t ICSelection; /*!< Specifies the input.
jhon309	0:c52df770855b	168	This parameter can be a value of @ref TIM_Input_Capture_Selection */
jhon309	0:c52df770855b	169
jhon309	0:c52df770855b	170	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
jhon309	0:c52df770855b	171	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
jhon309	0:c52df770855b	172
jhon309	0:c52df770855b	173	uint32_t ICFilter; /*!< Specifies the input capture filter.
jhon309	0:c52df770855b	174	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
jhon309	0:c52df770855b	175	} TIM_IC_InitTypeDef;
jhon309	0:c52df770855b	176
jhon309	0:c52df770855b	177	/**
jhon309	0:c52df770855b	178	* @brief TIM Encoder Configuration Structure definition
jhon309	0:c52df770855b	179	*/
jhon309	0:c52df770855b	180	typedef struct
jhon309	0:c52df770855b	181	{
jhon309	0:c52df770855b	182	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
jhon309	0:c52df770855b	183	This parameter can be a value of @ref TIM_Encoder_Mode */
jhon309	0:c52df770855b	184
jhon309	0:c52df770855b	185	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
jhon309	0:c52df770855b	186	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
jhon309	0:c52df770855b	187
jhon309	0:c52df770855b	188	uint32_t IC1Selection; /*!< Specifies the input.
jhon309	0:c52df770855b	189	This parameter can be a value of @ref TIM_Input_Capture_Selection */
jhon309	0:c52df770855b	190
jhon309	0:c52df770855b	191	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
jhon309	0:c52df770855b	192	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
jhon309	0:c52df770855b	193
jhon309	0:c52df770855b	194	uint32_t IC1Filter; /*!< Specifies the input capture filter.
jhon309	0:c52df770855b	195	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
jhon309	0:c52df770855b	196
jhon309	0:c52df770855b	197	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
jhon309	0:c52df770855b	198	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
jhon309	0:c52df770855b	199
jhon309	0:c52df770855b	200	uint32_t IC2Selection; /*!< Specifies the input.
jhon309	0:c52df770855b	201	This parameter can be a value of @ref TIM_Input_Capture_Selection */
jhon309	0:c52df770855b	202
jhon309	0:c52df770855b	203	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
jhon309	0:c52df770855b	204	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
jhon309	0:c52df770855b	205
jhon309	0:c52df770855b	206	uint32_t IC2Filter; /*!< Specifies the input capture filter.
jhon309	0:c52df770855b	207	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
jhon309	0:c52df770855b	208	} TIM_Encoder_InitTypeDef;
jhon309	0:c52df770855b	209
jhon309	0:c52df770855b	210
jhon309	0:c52df770855b	211	/**
jhon309	0:c52df770855b	212	* @brief Clock Configuration Handle Structure definition
jhon309	0:c52df770855b	213	*/
jhon309	0:c52df770855b	214	typedef struct
jhon309	0:c52df770855b	215	{
jhon309	0:c52df770855b	216	uint32_t ClockSource; /*!< TIM clock sources
jhon309	0:c52df770855b	217	This parameter can be a value of @ref TIM_Clock_Source */
jhon309	0:c52df770855b	218	uint32_t ClockPolarity; /*!< TIM clock polarity
jhon309	0:c52df770855b	219	This parameter can be a value of @ref TIM_Clock_Polarity */
jhon309	0:c52df770855b	220	uint32_t ClockPrescaler; /*!< TIM clock prescaler
jhon309	0:c52df770855b	221	This parameter can be a value of @ref TIM_Clock_Prescaler */
jhon309	0:c52df770855b	222	uint32_t ClockFilter; /*!< TIM clock filter
jhon309	0:c52df770855b	223	This parameter can be a value of @ref TIM_Clock_Filter */
jhon309	0:c52df770855b	224	}TIM_ClockConfigTypeDef;
jhon309	0:c52df770855b	225
jhon309	0:c52df770855b	226	/**
jhon309	0:c52df770855b	227	* @brief Clear Input Configuration Handle Structure definition
jhon309	0:c52df770855b	228	*/
jhon309	0:c52df770855b	229	typedef struct
jhon309	0:c52df770855b	230	{
jhon309	0:c52df770855b	231	uint32_t ClearInputState; /*!< TIM clear Input state
jhon309	0:c52df770855b	232	This parameter can be ENABLE or DISABLE */
jhon309	0:c52df770855b	233	uint32_t ClearInputSource; /*!< TIM clear Input sources
jhon309	0:c52df770855b	234	This parameter can be a value of @ref TIM_ClearInput_Source */
jhon309	0:c52df770855b	235	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
jhon309	0:c52df770855b	236	This parameter can be a value of @ref TIM_ClearInput_Polarity */
jhon309	0:c52df770855b	237	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
jhon309	0:c52df770855b	238	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
jhon309	0:c52df770855b	239	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
jhon309	0:c52df770855b	240	This parameter can be a value of @ref TIM_ClearInput_Filter */
jhon309	0:c52df770855b	241	}TIM_ClearInputConfigTypeDef;
jhon309	0:c52df770855b	242
jhon309	0:c52df770855b	243	/**
jhon309	0:c52df770855b	244	* @brief TIM Slave configuration Structure definition
jhon309	0:c52df770855b	245	*/
jhon309	0:c52df770855b	246	typedef struct {
jhon309	0:c52df770855b	247	uint32_t SlaveMode; /*!< Slave mode selection
jhon309	0:c52df770855b	248	This parameter can be a value of @ref TIM_Slave_Mode */
jhon309	0:c52df770855b	249	uint32_t InputTrigger; /*!< Input Trigger source
jhon309	0:c52df770855b	250	This parameter can be a value of @ref TIM_Trigger_Selection */
jhon309	0:c52df770855b	251	uint32_t TriggerPolarity; /*!< Input Trigger polarity
jhon309	0:c52df770855b	252	This parameter can be a value of @ref TIM_Trigger_Polarity */
jhon309	0:c52df770855b	253	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
jhon309	0:c52df770855b	254	This parameter can be a value of @ref TIM_Trigger_Prescaler */
jhon309	0:c52df770855b	255	uint32_t TriggerFilter; /*!< Input trigger filter
jhon309	0:c52df770855b	256	This parameter can be a value of @ref TIM_Trigger_Filter */
jhon309	0:c52df770855b	257
jhon309	0:c52df770855b	258	}TIM_SlaveConfigTypeDef;
jhon309	0:c52df770855b	259
jhon309	0:c52df770855b	260	/**
jhon309	0:c52df770855b	261	* @brief HAL State structures definition
jhon309	0:c52df770855b	262	*/
jhon309	0:c52df770855b	263	typedef enum
jhon309	0:c52df770855b	264	{
jhon309	0:c52df770855b	265	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
jhon309	0:c52df770855b	266	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
jhon309	0:c52df770855b	267	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
jhon309	0:c52df770855b	268	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
jhon309	0:c52df770855b	269	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
jhon309	0:c52df770855b	270	}HAL_TIM_StateTypeDef;
jhon309	0:c52df770855b	271
jhon309	0:c52df770855b	272	/**
jhon309	0:c52df770855b	273	* @brief HAL Active channel structures definition
jhon309	0:c52df770855b	274	*/
jhon309	0:c52df770855b	275	typedef enum
jhon309	0:c52df770855b	276	{
jhon309	0:c52df770855b	277	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
jhon309	0:c52df770855b	278	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
jhon309	0:c52df770855b	279	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
jhon309	0:c52df770855b	280	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
jhon309	0:c52df770855b	281	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
jhon309	0:c52df770855b	282	}HAL_TIM_ActiveChannel;
jhon309	0:c52df770855b	283
jhon309	0:c52df770855b	284	/**
jhon309	0:c52df770855b	285	* @brief TIM Time Base Handle Structure definition
jhon309	0:c52df770855b	286	*/
jhon309	0:c52df770855b	287	typedef struct
jhon309	0:c52df770855b	288	{
jhon309	0:c52df770855b	289	TIM_TypeDef Instance; /!< Register base address */
jhon309	0:c52df770855b	290	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
jhon309	0:c52df770855b	291	HAL_TIM_ActiveChannel Channel; /!< Active channel /
jhon309	0:c52df770855b	292	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
jhon309	0:c52df770855b	293	This array is accessed by a @ref TIM_DMA_Handle_index */
jhon309	0:c52df770855b	294	HAL_LockTypeDef Lock; /!< Locking object /
jhon309	0:c52df770855b	295	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
jhon309	0:c52df770855b	296	}TIM_HandleTypeDef;
jhon309	0:c52df770855b	297
jhon309	0:c52df770855b	298	/**
jhon309	0:c52df770855b	299	* @}
jhon309	0:c52df770855b	300	*/
jhon309	0:c52df770855b	301
jhon309	0:c52df770855b	302	/* Exported constants --------------------------------------------------------*/
jhon309	0:c52df770855b	303	/** @defgroup TIM_Exported_Constants TIM Exported Constants
jhon309	0:c52df770855b	304	* @{
jhon309	0:c52df770855b	305	*/
jhon309	0:c52df770855b	306
jhon309	0:c52df770855b	307	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
jhon309	0:c52df770855b	308	* @{
jhon309	0:c52df770855b	309	*/
jhon309	0:c52df770855b	310	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
jhon309	0:c52df770855b	311	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
jhon309	0:c52df770855b	312	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
jhon309	0:c52df770855b	313	/**
jhon309	0:c52df770855b	314	* @}
jhon309	0:c52df770855b	315	*/
jhon309	0:c52df770855b	316
jhon309	0:c52df770855b	317	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
jhon309	0:c52df770855b	318	* @{
jhon309	0:c52df770855b	319	*/
jhon309	0:c52df770855b	320	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
jhon309	0:c52df770855b	321	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
jhon309	0:c52df770855b	322	/**
jhon309	0:c52df770855b	323	* @}
jhon309	0:c52df770855b	324	*/
jhon309	0:c52df770855b	325
jhon309	0:c52df770855b	326	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
jhon309	0:c52df770855b	327	* @{
jhon309	0:c52df770855b	328	*/
jhon309	0:c52df770855b	329	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
jhon309	0:c52df770855b	330	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
jhon309	0:c52df770855b	331	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
jhon309	0:c52df770855b	332	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
jhon309	0:c52df770855b	333	/**
jhon309	0:c52df770855b	334	* @}
jhon309	0:c52df770855b	335	*/
jhon309	0:c52df770855b	336
jhon309	0:c52df770855b	337	/** @defgroup TIM_Counter_Mode TIM Counter Mode
jhon309	0:c52df770855b	338	* @{
jhon309	0:c52df770855b	339	*/
jhon309	0:c52df770855b	340
jhon309	0:c52df770855b	341	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
jhon309	0:c52df770855b	342	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
jhon309	0:c52df770855b	343	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
jhon309	0:c52df770855b	344	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
jhon309	0:c52df770855b	345	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
jhon309	0:c52df770855b	346
jhon309	0:c52df770855b	347	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
jhon309	0:c52df770855b	348	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
jhon309	0:c52df770855b	349	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
jhon309	0:c52df770855b	350	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
jhon309	0:c52df770855b	351	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
jhon309	0:c52df770855b	352	/**
jhon309	0:c52df770855b	353	* @}
jhon309	0:c52df770855b	354	*/
jhon309	0:c52df770855b	355
jhon309	0:c52df770855b	356	/** @defgroup TIM_ClockDivision TIM Clock Division
jhon309	0:c52df770855b	357	* @{
jhon309	0:c52df770855b	358	*/
jhon309	0:c52df770855b	359
jhon309	0:c52df770855b	360	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
jhon309	0:c52df770855b	361	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
jhon309	0:c52df770855b	362	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
jhon309	0:c52df770855b	363
jhon309	0:c52df770855b	364	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
jhon309	0:c52df770855b	365	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
jhon309	0:c52df770855b	366	((DIV) == TIM_CLOCKDIVISION_DIV4))
jhon309	0:c52df770855b	367	/**
jhon309	0:c52df770855b	368	* @}
jhon309	0:c52df770855b	369	*/
jhon309	0:c52df770855b	370
jhon309	0:c52df770855b	371	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare & PWM modes
jhon309	0:c52df770855b	372	* @{
jhon309	0:c52df770855b	373	*/
jhon309	0:c52df770855b	374
jhon309	0:c52df770855b	375	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
jhon309	0:c52df770855b	376	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
jhon309	0:c52df770855b	377	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
jhon309	0:c52df770855b	378	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
jhon309	0:c52df770855b	379	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
jhon309	0:c52df770855b	380	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
jhon309	0:c52df770855b	381	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
jhon309	0:c52df770855b	382	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
jhon309	0:c52df770855b	383
jhon309	0:c52df770855b	384	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
jhon309	0:c52df770855b	385	((MODE) == TIM_OCMODE_PWM2))
jhon309	0:c52df770855b	386
jhon309	0:c52df770855b	387	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
jhon309	0:c52df770855b	388	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
jhon309	0:c52df770855b	389	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
jhon309	0:c52df770855b	390	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
jhon309	0:c52df770855b	391	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
jhon309	0:c52df770855b	392	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
jhon309	0:c52df770855b	393	/**
jhon309	0:c52df770855b	394	* @}
jhon309	0:c52df770855b	395	*/
jhon309	0:c52df770855b	396
jhon309	0:c52df770855b	397	/** @defgroup TIM_Output_Compare_State TIM Output Compare State
jhon309	0:c52df770855b	398	* @{
jhon309	0:c52df770855b	399	*/
jhon309	0:c52df770855b	400
jhon309	0:c52df770855b	401	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
jhon309	0:c52df770855b	402	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
jhon309	0:c52df770855b	403
jhon309	0:c52df770855b	404	#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) \|\| \
jhon309	0:c52df770855b	405	((STATE) == TIM_OUTPUTSTATE_ENABLE))
jhon309	0:c52df770855b	406	/**
jhon309	0:c52df770855b	407	* @}
jhon309	0:c52df770855b	408	*/
jhon309	0:c52df770855b	409	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
jhon309	0:c52df770855b	410	* @{
jhon309	0:c52df770855b	411	*/
jhon309	0:c52df770855b	412	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
jhon309	0:c52df770855b	413	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
jhon309	0:c52df770855b	414
jhon309	0:c52df770855b	415	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
jhon309	0:c52df770855b	416	((STATE) == TIM_OCFAST_ENABLE))
jhon309	0:c52df770855b	417	/**
jhon309	0:c52df770855b	418	* @}
jhon309	0:c52df770855b	419	*/
jhon309	0:c52df770855b	420	/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
jhon309	0:c52df770855b	421	* @{
jhon309	0:c52df770855b	422	*/
jhon309	0:c52df770855b	423
jhon309	0:c52df770855b	424	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
jhon309	0:c52df770855b	425	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
jhon309	0:c52df770855b	426
jhon309	0:c52df770855b	427	#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) \|\| \
jhon309	0:c52df770855b	428	((STATE) == TIM_OUTPUTNSTATE_ENABLE))
jhon309	0:c52df770855b	429	/**
jhon309	0:c52df770855b	430	* @}
jhon309	0:c52df770855b	431	*/
jhon309	0:c52df770855b	432
jhon309	0:c52df770855b	433	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
jhon309	0:c52df770855b	434	* @{
jhon309	0:c52df770855b	435	*/
jhon309	0:c52df770855b	436
jhon309	0:c52df770855b	437	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
jhon309	0:c52df770855b	438	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
jhon309	0:c52df770855b	439
jhon309	0:c52df770855b	440	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
jhon309	0:c52df770855b	441	((POLARITY) == TIM_OCPOLARITY_LOW))
jhon309	0:c52df770855b	442	/**
jhon309	0:c52df770855b	443	* @}
jhon309	0:c52df770855b	444	*/
jhon309	0:c52df770855b	445
jhon309	0:c52df770855b	446	/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
jhon309	0:c52df770855b	447	* @{
jhon309	0:c52df770855b	448	*/
jhon309	0:c52df770855b	449
jhon309	0:c52df770855b	450	#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
jhon309	0:c52df770855b	451	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
jhon309	0:c52df770855b	452
jhon309	0:c52df770855b	453	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
jhon309	0:c52df770855b	454	((POLARITY) == TIM_OCNPOLARITY_LOW))
jhon309	0:c52df770855b	455	/**
jhon309	0:c52df770855b	456	* @}
jhon309	0:c52df770855b	457	*/
jhon309	0:c52df770855b	458
jhon309	0:c52df770855b	459	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
jhon309	0:c52df770855b	460	* @{
jhon309	0:c52df770855b	461	*/
jhon309	0:c52df770855b	462
jhon309	0:c52df770855b	463	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
jhon309	0:c52df770855b	464	#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
jhon309	0:c52df770855b	465	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
jhon309	0:c52df770855b	466	((STATE) == TIM_OCIDLESTATE_RESET))
jhon309	0:c52df770855b	467	/**
jhon309	0:c52df770855b	468	* @}
jhon309	0:c52df770855b	469	*/
jhon309	0:c52df770855b	470
jhon309	0:c52df770855b	471	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
jhon309	0:c52df770855b	472	* @{
jhon309	0:c52df770855b	473	*/
jhon309	0:c52df770855b	474
jhon309	0:c52df770855b	475	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
jhon309	0:c52df770855b	476	#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
jhon309	0:c52df770855b	477	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
jhon309	0:c52df770855b	478	((STATE) == TIM_OCNIDLESTATE_RESET))
jhon309	0:c52df770855b	479	/**
jhon309	0:c52df770855b	480	* @}
jhon309	0:c52df770855b	481	*/
jhon309	0:c52df770855b	482
jhon309	0:c52df770855b	483	/** @defgroup TIM_Channel TIM Channel
jhon309	0:c52df770855b	484	* @{
jhon309	0:c52df770855b	485	*/
jhon309	0:c52df770855b	486	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
jhon309	0:c52df770855b	487	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
jhon309	0:c52df770855b	488	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
jhon309	0:c52df770855b	489	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
jhon309	0:c52df770855b	490	#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
jhon309	0:c52df770855b	491
jhon309	0:c52df770855b	492	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
jhon309	0:c52df770855b	493	((CHANNEL) == TIM_CHANNEL_2) \|\| \
jhon309	0:c52df770855b	494	((CHANNEL) == TIM_CHANNEL_3) \|\| \
jhon309	0:c52df770855b	495	((CHANNEL) == TIM_CHANNEL_4) \|\| \
jhon309	0:c52df770855b	496	((CHANNEL) == TIM_CHANNEL_ALL))
jhon309	0:c52df770855b	497
jhon309	0:c52df770855b	498	#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
jhon309	0:c52df770855b	499	((CHANNEL) == TIM_CHANNEL_2))
jhon309	0:c52df770855b	500
jhon309	0:c52df770855b	501	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
jhon309	0:c52df770855b	502	((CHANNEL) == TIM_CHANNEL_2))
jhon309	0:c52df770855b	503
jhon309	0:c52df770855b	504	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
jhon309	0:c52df770855b	505	((CHANNEL) == TIM_CHANNEL_2) \|\| \
jhon309	0:c52df770855b	506	((CHANNEL) == TIM_CHANNEL_3))
jhon309	0:c52df770855b	507	/**
jhon309	0:c52df770855b	508	* @}
jhon309	0:c52df770855b	509	*/
jhon309	0:c52df770855b	510
jhon309	0:c52df770855b	511	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
jhon309	0:c52df770855b	512	* @{
jhon309	0:c52df770855b	513	*/
jhon309	0:c52df770855b	514
jhon309	0:c52df770855b	515	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
jhon309	0:c52df770855b	516	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
jhon309	0:c52df770855b	517	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
jhon309	0:c52df770855b	518
jhon309	0:c52df770855b	519	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
jhon309	0:c52df770855b	520	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
jhon309	0:c52df770855b	521	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
jhon309	0:c52df770855b	522	/**
jhon309	0:c52df770855b	523	* @}
jhon309	0:c52df770855b	524	*/
jhon309	0:c52df770855b	525
jhon309	0:c52df770855b	526	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
jhon309	0:c52df770855b	527	* @{
jhon309	0:c52df770855b	528	*/
jhon309	0:c52df770855b	529
jhon309	0:c52df770855b	530	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
jhon309	0:c52df770855b	531	connected to IC1, IC2, IC3 or IC4, respectively */
jhon309	0:c52df770855b	532	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
jhon309	0:c52df770855b	533	connected to IC2, IC1, IC4 or IC3, respectively */
jhon309	0:c52df770855b	534	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
jhon309	0:c52df770855b	535
jhon309	0:c52df770855b	536	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
jhon309	0:c52df770855b	537	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
jhon309	0:c52df770855b	538	((SELECTION) == TIM_ICSELECTION_TRC))
jhon309	0:c52df770855b	539	/**
jhon309	0:c52df770855b	540	* @}
jhon309	0:c52df770855b	541	*/
jhon309	0:c52df770855b	542
jhon309	0:c52df770855b	543	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
jhon309	0:c52df770855b	544	* @{
jhon309	0:c52df770855b	545	*/
jhon309	0:c52df770855b	546
jhon309	0:c52df770855b	547	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
jhon309	0:c52df770855b	548	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
jhon309	0:c52df770855b	549	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
jhon309	0:c52df770855b	550	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
jhon309	0:c52df770855b	551
jhon309	0:c52df770855b	552	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
jhon309	0:c52df770855b	553	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
jhon309	0:c52df770855b	554	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
jhon309	0:c52df770855b	555	((PRESCALER) == TIM_ICPSC_DIV8))
jhon309	0:c52df770855b	556	/**
jhon309	0:c52df770855b	557	* @}
jhon309	0:c52df770855b	558	*/
jhon309	0:c52df770855b	559
jhon309	0:c52df770855b	560	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
jhon309	0:c52df770855b	561	* @{
jhon309	0:c52df770855b	562	*/
jhon309	0:c52df770855b	563
jhon309	0:c52df770855b	564	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
jhon309	0:c52df770855b	565	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
jhon309	0:c52df770855b	566
jhon309	0:c52df770855b	567	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
jhon309	0:c52df770855b	568	((MODE) == TIM_OPMODE_REPETITIVE))
jhon309	0:c52df770855b	569	/**
jhon309	0:c52df770855b	570	* @}
jhon309	0:c52df770855b	571	*/
jhon309	0:c52df770855b	572	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
jhon309	0:c52df770855b	573	* @{
jhon309	0:c52df770855b	574	*/
jhon309	0:c52df770855b	575	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
jhon309	0:c52df770855b	576	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
jhon309	0:c52df770855b	577	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
jhon309	0:c52df770855b	578
jhon309	0:c52df770855b	579	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
jhon309	0:c52df770855b	580	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
jhon309	0:c52df770855b	581	((MODE) == TIM_ENCODERMODE_TI12))
jhon309	0:c52df770855b	582	/**
jhon309	0:c52df770855b	583	* @}
jhon309	0:c52df770855b	584	*/
jhon309	0:c52df770855b	585	/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
jhon309	0:c52df770855b	586	* @{
jhon309	0:c52df770855b	587	*/
jhon309	0:c52df770855b	588	#define TIM_IT_UPDATE (TIM_DIER_UIE)
jhon309	0:c52df770855b	589	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
jhon309	0:c52df770855b	590	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
jhon309	0:c52df770855b	591	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
jhon309	0:c52df770855b	592	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
jhon309	0:c52df770855b	593	#define TIM_IT_COM (TIM_DIER_COMIE)
jhon309	0:c52df770855b	594	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
jhon309	0:c52df770855b	595	#define TIM_IT_BREAK (TIM_DIER_BIE)
jhon309	0:c52df770855b	596	/**
jhon309	0:c52df770855b	597	* @}
jhon309	0:c52df770855b	598	*/
jhon309	0:c52df770855b	599
jhon309	0:c52df770855b	600	/** @defgroup TIM_COMMUTATION TIM Commutation
jhon309	0:c52df770855b	601	* @{
jhon309	0:c52df770855b	602	*/
jhon309	0:c52df770855b	603	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
jhon309	0:c52df770855b	604	#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
jhon309	0:c52df770855b	605
jhon309	0:c52df770855b	606	/**
jhon309	0:c52df770855b	607	* @}
jhon309	0:c52df770855b	608	*/
jhon309	0:c52df770855b	609	/** @defgroup TIM_DMA_sources TIM DMA Sources
jhon309	0:c52df770855b	610	* @{
jhon309	0:c52df770855b	611	*/
jhon309	0:c52df770855b	612
jhon309	0:c52df770855b	613	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
jhon309	0:c52df770855b	614	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
jhon309	0:c52df770855b	615	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
jhon309	0:c52df770855b	616	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
jhon309	0:c52df770855b	617	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
jhon309	0:c52df770855b	618	#define TIM_DMA_COM (TIM_DIER_COMDE)
jhon309	0:c52df770855b	619	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
jhon309	0:c52df770855b	620
jhon309	0:c52df770855b	621	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
jhon309	0:c52df770855b	622	/**
jhon309	0:c52df770855b	623	* @}
jhon309	0:c52df770855b	624	*/
jhon309	0:c52df770855b	625
jhon309	0:c52df770855b	626	/** @defgroup TIM_Event_Source TIM Event Source
jhon309	0:c52df770855b	627	* @{
jhon309	0:c52df770855b	628	*/
jhon309	0:c52df770855b	629	#define TIM_EventSource_Update TIM_EGR_UG
jhon309	0:c52df770855b	630	#define TIM_EventSource_CC1 TIM_EGR_CC1G
jhon309	0:c52df770855b	631	#define TIM_EventSource_CC2 TIM_EGR_CC2G
jhon309	0:c52df770855b	632	#define TIM_EventSource_CC3 TIM_EGR_CC3G
jhon309	0:c52df770855b	633	#define TIM_EventSource_CC4 TIM_EGR_CC4G
jhon309	0:c52df770855b	634	#define TIM_EventSource_COM TIM_EGR_COMG
jhon309	0:c52df770855b	635	#define TIM_EventSource_Trigger TIM_EGR_TG
jhon309	0:c52df770855b	636	#define TIM_EventSource_Break TIM_EGR_BG
jhon309	0:c52df770855b	637
jhon309	0:c52df770855b	638	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
jhon309	0:c52df770855b	639	/**
jhon309	0:c52df770855b	640	* @}
jhon309	0:c52df770855b	641	*/
jhon309	0:c52df770855b	642
jhon309	0:c52df770855b	643	/** @defgroup TIM_Flag_definition TIM Flag Definition
jhon309	0:c52df770855b	644	* @{
jhon309	0:c52df770855b	645	*/
jhon309	0:c52df770855b	646
jhon309	0:c52df770855b	647	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
jhon309	0:c52df770855b	648	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
jhon309	0:c52df770855b	649	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
jhon309	0:c52df770855b	650	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
jhon309	0:c52df770855b	651	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
jhon309	0:c52df770855b	652	#define TIM_FLAG_COM (TIM_SR_COMIF)
jhon309	0:c52df770855b	653	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
jhon309	0:c52df770855b	654	#define TIM_FLAG_BREAK (TIM_SR_BIF)
jhon309	0:c52df770855b	655	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
jhon309	0:c52df770855b	656	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
jhon309	0:c52df770855b	657	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
jhon309	0:c52df770855b	658	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
jhon309	0:c52df770855b	659
jhon309	0:c52df770855b	660	#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) \|\| \
jhon309	0:c52df770855b	661	((FLAG) == TIM_FLAG_CC1) \|\| \
jhon309	0:c52df770855b	662	((FLAG) == TIM_FLAG_CC2) \|\| \
jhon309	0:c52df770855b	663	((FLAG) == TIM_FLAG_CC3) \|\| \
jhon309	0:c52df770855b	664	((FLAG) == TIM_FLAG_CC4) \|\| \
jhon309	0:c52df770855b	665	((FLAG) == TIM_FLAG_COM) \|\| \
jhon309	0:c52df770855b	666	((FLAG) == TIM_FLAG_TRIGGER) \|\| \
jhon309	0:c52df770855b	667	((FLAG) == TIM_FLAG_BREAK) \|\| \
jhon309	0:c52df770855b	668	((FLAG) == TIM_FLAG_CC1OF) \|\| \
jhon309	0:c52df770855b	669	((FLAG) == TIM_FLAG_CC2OF) \|\| \
jhon309	0:c52df770855b	670	((FLAG) == TIM_FLAG_CC3OF) \|\| \
jhon309	0:c52df770855b	671	((FLAG) == TIM_FLAG_CC4OF))
jhon309	0:c52df770855b	672	/**
jhon309	0:c52df770855b	673	* @}
jhon309	0:c52df770855b	674	*/
jhon309	0:c52df770855b	675
jhon309	0:c52df770855b	676	/** @defgroup TIM_Clock_Source TIM Clock Source
jhon309	0:c52df770855b	677	* @{
jhon309	0:c52df770855b	678	*/
jhon309	0:c52df770855b	679	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
jhon309	0:c52df770855b	680	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
jhon309	0:c52df770855b	681	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
jhon309	0:c52df770855b	682	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
jhon309	0:c52df770855b	683	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
jhon309	0:c52df770855b	684	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
jhon309	0:c52df770855b	685	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
jhon309	0:c52df770855b	686	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
jhon309	0:c52df770855b	687	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
jhon309	0:c52df770855b	688	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
jhon309	0:c52df770855b	689
jhon309	0:c52df770855b	690	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
jhon309	0:c52df770855b	691	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
jhon309	0:c52df770855b	692	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
jhon309	0:c52df770855b	693	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
jhon309	0:c52df770855b	694	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
jhon309	0:c52df770855b	695	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
jhon309	0:c52df770855b	696	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
jhon309	0:c52df770855b	697	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
jhon309	0:c52df770855b	698	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
jhon309	0:c52df770855b	699	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
jhon309	0:c52df770855b	700	/**
jhon309	0:c52df770855b	701	* @}
jhon309	0:c52df770855b	702	*/
jhon309	0:c52df770855b	703
jhon309	0:c52df770855b	704	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
jhon309	0:c52df770855b	705	* @{
jhon309	0:c52df770855b	706	*/
jhon309	0:c52df770855b	707	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
jhon309	0:c52df770855b	708	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
jhon309	0:c52df770855b	709	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
jhon309	0:c52df770855b	710	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
jhon309	0:c52df770855b	711	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
jhon309	0:c52df770855b	712
jhon309	0:c52df770855b	713	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
jhon309	0:c52df770855b	714	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
jhon309	0:c52df770855b	715	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
jhon309	0:c52df770855b	716	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
jhon309	0:c52df770855b	717	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
jhon309	0:c52df770855b	718	/**
jhon309	0:c52df770855b	719	* @}
jhon309	0:c52df770855b	720	*/
jhon309	0:c52df770855b	721	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
jhon309	0:c52df770855b	722	* @{
jhon309	0:c52df770855b	723	*/
jhon309	0:c52df770855b	724	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
jhon309	0:c52df770855b	725	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
jhon309	0:c52df770855b	726	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
jhon309	0:c52df770855b	727	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
jhon309	0:c52df770855b	728
jhon309	0:c52df770855b	729	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
jhon309	0:c52df770855b	730	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
jhon309	0:c52df770855b	731	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
jhon309	0:c52df770855b	732	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
jhon309	0:c52df770855b	733	/**
jhon309	0:c52df770855b	734	* @}
jhon309	0:c52df770855b	735	*/
jhon309	0:c52df770855b	736	/** @defgroup TIM_Clock_Filter TIM Clock Filter
jhon309	0:c52df770855b	737	* @{
jhon309	0:c52df770855b	738	*/
jhon309	0:c52df770855b	739
jhon309	0:c52df770855b	740	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
jhon309	0:c52df770855b	741	/**
jhon309	0:c52df770855b	742	* @}
jhon309	0:c52df770855b	743	*/
jhon309	0:c52df770855b	744
jhon309	0:c52df770855b	745	/** @defgroup TIM_ClearInput_Source TIM ClearInput Source
jhon309	0:c52df770855b	746	* @{
jhon309	0:c52df770855b	747	*/
jhon309	0:c52df770855b	748	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
jhon309	0:c52df770855b	749	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
jhon309	0:c52df770855b	750
jhon309	0:c52df770855b	751	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
jhon309	0:c52df770855b	752	((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
jhon309	0:c52df770855b	753	/**
jhon309	0:c52df770855b	754	* @}
jhon309	0:c52df770855b	755	*/
jhon309	0:c52df770855b	756
jhon309	0:c52df770855b	757	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
jhon309	0:c52df770855b	758	* @{
jhon309	0:c52df770855b	759	*/
jhon309	0:c52df770855b	760	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
jhon309	0:c52df770855b	761	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
jhon309	0:c52df770855b	762
jhon309	0:c52df770855b	763
jhon309	0:c52df770855b	764	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
jhon309	0:c52df770855b	765	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
jhon309	0:c52df770855b	766	/**
jhon309	0:c52df770855b	767	* @}
jhon309	0:c52df770855b	768	*/
jhon309	0:c52df770855b	769
jhon309	0:c52df770855b	770	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
jhon309	0:c52df770855b	771	* @{
jhon309	0:c52df770855b	772	*/
jhon309	0:c52df770855b	773	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
jhon309	0:c52df770855b	774	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
jhon309	0:c52df770855b	775	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
jhon309	0:c52df770855b	776	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
jhon309	0:c52df770855b	777
jhon309	0:c52df770855b	778	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
jhon309	0:c52df770855b	779	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
jhon309	0:c52df770855b	780	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
jhon309	0:c52df770855b	781	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
jhon309	0:c52df770855b	782	/**
jhon309	0:c52df770855b	783	* @}
jhon309	0:c52df770855b	784	*/
jhon309	0:c52df770855b	785
jhon309	0:c52df770855b	786	/** @defgroup TIM_ClearInput_Filter TIM Clear Input Filter
jhon309	0:c52df770855b	787	* @{
jhon309	0:c52df770855b	788	*/
jhon309	0:c52df770855b	789
jhon309	0:c52df770855b	790	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
jhon309	0:c52df770855b	791	/**
jhon309	0:c52df770855b	792	* @}
jhon309	0:c52df770855b	793	*/
jhon309	0:c52df770855b	794
jhon309	0:c52df770855b	795	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM Off-state Selection for Run Mode
jhon309	0:c52df770855b	796	* @{
jhon309	0:c52df770855b	797	*/
jhon309	0:c52df770855b	798	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
jhon309	0:c52df770855b	799	#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
jhon309	0:c52df770855b	800
jhon309	0:c52df770855b	801	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
jhon309	0:c52df770855b	802	((STATE) == TIM_OSSR_DISABLE))
jhon309	0:c52df770855b	803	/**
jhon309	0:c52df770855b	804	* @}
jhon309	0:c52df770855b	805	*/
jhon309	0:c52df770855b	806
jhon309	0:c52df770855b	807	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM Off-state Selection for Idle Mode
jhon309	0:c52df770855b	808	* @{
jhon309	0:c52df770855b	809	*/
jhon309	0:c52df770855b	810	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
jhon309	0:c52df770855b	811	#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
jhon309	0:c52df770855b	812
jhon309	0:c52df770855b	813	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
jhon309	0:c52df770855b	814	((STATE) == TIM_OSSI_DISABLE))
jhon309	0:c52df770855b	815	/**
jhon309	0:c52df770855b	816	* @}
jhon309	0:c52df770855b	817	*/
jhon309	0:c52df770855b	818	/** @defgroup TIM_Lock_level TIM Lock Configuration
jhon309	0:c52df770855b	819	* @{
jhon309	0:c52df770855b	820	*/
jhon309	0:c52df770855b	821	#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
jhon309	0:c52df770855b	822	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
jhon309	0:c52df770855b	823	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
jhon309	0:c52df770855b	824	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
jhon309	0:c52df770855b	825
jhon309	0:c52df770855b	826	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
jhon309	0:c52df770855b	827	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
jhon309	0:c52df770855b	828	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
jhon309	0:c52df770855b	829	((LEVEL) == TIM_LOCKLEVEL_3))
jhon309	0:c52df770855b	830	/**
jhon309	0:c52df770855b	831	* @}
jhon309	0:c52df770855b	832	*/
jhon309	0:c52df770855b	833	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
jhon309	0:c52df770855b	834	* @{
jhon309	0:c52df770855b	835	*/
jhon309	0:c52df770855b	836	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
jhon309	0:c52df770855b	837	#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
jhon309	0:c52df770855b	838
jhon309	0:c52df770855b	839	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
jhon309	0:c52df770855b	840	((STATE) == TIM_BREAK_DISABLE))
jhon309	0:c52df770855b	841	/**
jhon309	0:c52df770855b	842	* @}
jhon309	0:c52df770855b	843	*/
jhon309	0:c52df770855b	844	/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
jhon309	0:c52df770855b	845	* @{
jhon309	0:c52df770855b	846	*/
jhon309	0:c52df770855b	847	#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
jhon309	0:c52df770855b	848	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
jhon309	0:c52df770855b	849
jhon309	0:c52df770855b	850	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
jhon309	0:c52df770855b	851	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
jhon309	0:c52df770855b	852	/**
jhon309	0:c52df770855b	853	* @}
jhon309	0:c52df770855b	854	*/
jhon309	0:c52df770855b	855	/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
jhon309	0:c52df770855b	856	* @{
jhon309	0:c52df770855b	857	*/
jhon309	0:c52df770855b	858	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
jhon309	0:c52df770855b	859	#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
jhon309	0:c52df770855b	860
jhon309	0:c52df770855b	861	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
jhon309	0:c52df770855b	862	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
jhon309	0:c52df770855b	863	/**
jhon309	0:c52df770855b	864	* @}
jhon309	0:c52df770855b	865	*/
jhon309	0:c52df770855b	866
jhon309	0:c52df770855b	867	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
jhon309	0:c52df770855b	868	* @{
jhon309	0:c52df770855b	869	*/
jhon309	0:c52df770855b	870	#define TIM_TRGO_RESET ((uint32_t)0x0000)
jhon309	0:c52df770855b	871	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
jhon309	0:c52df770855b	872	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
jhon309	0:c52df770855b	873	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
jhon309	0:c52df770855b	874	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
jhon309	0:c52df770855b	875	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
jhon309	0:c52df770855b	876	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
jhon309	0:c52df770855b	877	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
jhon309	0:c52df770855b	878
jhon309	0:c52df770855b	879	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
jhon309	0:c52df770855b	880	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
jhon309	0:c52df770855b	881	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
jhon309	0:c52df770855b	882	((SOURCE) == TIM_TRGO_OC1) \|\| \
jhon309	0:c52df770855b	883	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
jhon309	0:c52df770855b	884	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
jhon309	0:c52df770855b	885	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
jhon309	0:c52df770855b	886	((SOURCE) == TIM_TRGO_OC4REF))
jhon309	0:c52df770855b	887
jhon309	0:c52df770855b	888
jhon309	0:c52df770855b	889	/**
jhon309	0:c52df770855b	890	* @}
jhon309	0:c52df770855b	891	*/
jhon309	0:c52df770855b	892
jhon309	0:c52df770855b	893	/** @defgroup TIM_Slave_Mode TIM Slave Mode
jhon309	0:c52df770855b	894	* @{
jhon309	0:c52df770855b	895	*/
jhon309	0:c52df770855b	896
jhon309	0:c52df770855b	897	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
jhon309	0:c52df770855b	898	#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
jhon309	0:c52df770855b	899	#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
jhon309	0:c52df770855b	900	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
jhon309	0:c52df770855b	901	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
jhon309	0:c52df770855b	902
jhon309	0:c52df770855b	903	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
jhon309	0:c52df770855b	904	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
jhon309	0:c52df770855b	905	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
jhon309	0:c52df770855b	906	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
jhon309	0:c52df770855b	907	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
jhon309	0:c52df770855b	908	/**
jhon309	0:c52df770855b	909	* @}
jhon309	0:c52df770855b	910	*/
jhon309	0:c52df770855b	911
jhon309	0:c52df770855b	912	/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
jhon309	0:c52df770855b	913	* @{
jhon309	0:c52df770855b	914	*/
jhon309	0:c52df770855b	915
jhon309	0:c52df770855b	916	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
jhon309	0:c52df770855b	917	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
jhon309	0:c52df770855b	918
jhon309	0:c52df770855b	919	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
jhon309	0:c52df770855b	920	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
jhon309	0:c52df770855b	921	/**
jhon309	0:c52df770855b	922	* @}
jhon309	0:c52df770855b	923	*/
jhon309	0:c52df770855b	924	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
jhon309	0:c52df770855b	925	* @{
jhon309	0:c52df770855b	926	*/
jhon309	0:c52df770855b	927
jhon309	0:c52df770855b	928	#define TIM_TS_ITR0 ((uint32_t)0x0000)
jhon309	0:c52df770855b	929	#define TIM_TS_ITR1 ((uint32_t)0x0010)
jhon309	0:c52df770855b	930	#define TIM_TS_ITR2 ((uint32_t)0x0020)
jhon309	0:c52df770855b	931	#define TIM_TS_ITR3 ((uint32_t)0x0030)
jhon309	0:c52df770855b	932	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
jhon309	0:c52df770855b	933	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
jhon309	0:c52df770855b	934	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
jhon309	0:c52df770855b	935	#define TIM_TS_ETRF ((uint32_t)0x0070)
jhon309	0:c52df770855b	936	#define TIM_TS_NONE ((uint32_t)0xFFFF)
jhon309	0:c52df770855b	937
jhon309	0:c52df770855b	938	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
jhon309	0:c52df770855b	939	((SELECTION) == TIM_TS_ITR1) \|\| \
jhon309	0:c52df770855b	940	((SELECTION) == TIM_TS_ITR2) \|\| \
jhon309	0:c52df770855b	941	((SELECTION) == TIM_TS_ITR3) \|\| \
jhon309	0:c52df770855b	942	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
jhon309	0:c52df770855b	943	((SELECTION) == TIM_TS_TI1FP1) \|\| \
jhon309	0:c52df770855b	944	((SELECTION) == TIM_TS_TI2FP2) \|\| \
jhon309	0:c52df770855b	945	((SELECTION) == TIM_TS_ETRF))
jhon309	0:c52df770855b	946
jhon309	0:c52df770855b	947	#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
jhon309	0:c52df770855b	948	((SELECTION) == TIM_TS_ITR1) \|\| \
jhon309	0:c52df770855b	949	((SELECTION) == TIM_TS_ITR2) \|\| \
jhon309	0:c52df770855b	950	((SELECTION) == TIM_TS_ITR3))
jhon309	0:c52df770855b	951
jhon309	0:c52df770855b	952	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
jhon309	0:c52df770855b	953	((SELECTION) == TIM_TS_ITR1) \|\| \
jhon309	0:c52df770855b	954	((SELECTION) == TIM_TS_ITR2) \|\| \
jhon309	0:c52df770855b	955	((SELECTION) == TIM_TS_ITR3) \|\| \
jhon309	0:c52df770855b	956	((SELECTION) == TIM_TS_NONE))
jhon309	0:c52df770855b	957	/**
jhon309	0:c52df770855b	958	* @}
jhon309	0:c52df770855b	959	*/
jhon309	0:c52df770855b	960
jhon309	0:c52df770855b	961	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
jhon309	0:c52df770855b	962	* @{
jhon309	0:c52df770855b	963	*/
jhon309	0:c52df770855b	964	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
jhon309	0:c52df770855b	965	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
jhon309	0:c52df770855b	966	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
jhon309	0:c52df770855b	967	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
jhon309	0:c52df770855b	968	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
jhon309	0:c52df770855b	969
jhon309	0:c52df770855b	970	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
jhon309	0:c52df770855b	971	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
jhon309	0:c52df770855b	972	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
jhon309	0:c52df770855b	973	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
jhon309	0:c52df770855b	974	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
jhon309	0:c52df770855b	975	/**
jhon309	0:c52df770855b	976	* @}
jhon309	0:c52df770855b	977	*/
jhon309	0:c52df770855b	978
jhon309	0:c52df770855b	979	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
jhon309	0:c52df770855b	980	* @{
jhon309	0:c52df770855b	981	*/
jhon309	0:c52df770855b	982	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
jhon309	0:c52df770855b	983	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
jhon309	0:c52df770855b	984	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
jhon309	0:c52df770855b	985	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
jhon309	0:c52df770855b	986
jhon309	0:c52df770855b	987	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
jhon309	0:c52df770855b	988	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
jhon309	0:c52df770855b	989	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
jhon309	0:c52df770855b	990	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
jhon309	0:c52df770855b	991	/**
jhon309	0:c52df770855b	992	* @}
jhon309	0:c52df770855b	993	*/
jhon309	0:c52df770855b	994
jhon309	0:c52df770855b	995	/** @defgroup TIM_Trigger_Filter TIM Trigger Filter
jhon309	0:c52df770855b	996	* @{
jhon309	0:c52df770855b	997	*/
jhon309	0:c52df770855b	998
jhon309	0:c52df770855b	999	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
jhon309	0:c52df770855b	1000	/**
jhon309	0:c52df770855b	1001	* @}
jhon309	0:c52df770855b	1002	*/
jhon309	0:c52df770855b	1003
jhon309	0:c52df770855b	1004	/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
jhon309	0:c52df770855b	1005	* @{
jhon309	0:c52df770855b	1006	*/
jhon309	0:c52df770855b	1007
jhon309	0:c52df770855b	1008	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
jhon309	0:c52df770855b	1009	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
jhon309	0:c52df770855b	1010
jhon309	0:c52df770855b	1011	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
jhon309	0:c52df770855b	1012	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
jhon309	0:c52df770855b	1013
jhon309	0:c52df770855b	1014	/**
jhon309	0:c52df770855b	1015	* @}
jhon309	0:c52df770855b	1016	*/
jhon309	0:c52df770855b	1017
jhon309	0:c52df770855b	1018	/** @defgroup TIM_DMA_Base_address TIM DMA Base address
jhon309	0:c52df770855b	1019	* @{
jhon309	0:c52df770855b	1020	*/
jhon309	0:c52df770855b	1021	#define TIM_DMABase_CR1 (0x00000000)
jhon309	0:c52df770855b	1022	#define TIM_DMABase_CR2 (0x00000001)
jhon309	0:c52df770855b	1023	#define TIM_DMABase_SMCR (0x00000002)
jhon309	0:c52df770855b	1024	#define TIM_DMABase_DIER (0x00000003)
jhon309	0:c52df770855b	1025	#define TIM_DMABase_SR (0x00000004)
jhon309	0:c52df770855b	1026	#define TIM_DMABase_EGR (0x00000005)
jhon309	0:c52df770855b	1027	#define TIM_DMABase_CCMR1 (0x00000006)
jhon309	0:c52df770855b	1028	#define TIM_DMABase_CCMR2 (0x00000007)
jhon309	0:c52df770855b	1029	#define TIM_DMABase_CCER (0x00000008)
jhon309	0:c52df770855b	1030	#define TIM_DMABase_CNT (0x00000009)
jhon309	0:c52df770855b	1031	#define TIM_DMABase_PSC (0x0000000A)
jhon309	0:c52df770855b	1032	#define TIM_DMABase_ARR (0x0000000B)
jhon309	0:c52df770855b	1033	#define TIM_DMABase_RCR (0x0000000C)
jhon309	0:c52df770855b	1034	#define TIM_DMABase_CCR1 (0x0000000D)
jhon309	0:c52df770855b	1035	#define TIM_DMABase_CCR2 (0x0000000E)
jhon309	0:c52df770855b	1036	#define TIM_DMABase_CCR3 (0x0000000F)
jhon309	0:c52df770855b	1037	#define TIM_DMABase_CCR4 (0x00000010)
jhon309	0:c52df770855b	1038	#define TIM_DMABase_BDTR (0x00000011)
jhon309	0:c52df770855b	1039	#define TIM_DMABase_DCR (0x00000012)
jhon309	0:c52df770855b	1040	#define TIM_DMABase_OR (0x00000013)
jhon309	0:c52df770855b	1041
jhon309	0:c52df770855b	1042	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) \|\| \
jhon309	0:c52df770855b	1043	((BASE) == TIM_DMABase_CR2) \|\| \
jhon309	0:c52df770855b	1044	((BASE) == TIM_DMABase_SMCR) \|\| \
jhon309	0:c52df770855b	1045	((BASE) == TIM_DMABase_DIER) \|\| \
jhon309	0:c52df770855b	1046	((BASE) == TIM_DMABase_SR) \|\| \
jhon309	0:c52df770855b	1047	((BASE) == TIM_DMABase_EGR) \|\| \
jhon309	0:c52df770855b	1048	((BASE) == TIM_DMABase_CCMR1) \|\| \
jhon309	0:c52df770855b	1049	((BASE) == TIM_DMABase_CCMR2) \|\| \
jhon309	0:c52df770855b	1050	((BASE) == TIM_DMABase_CCER) \|\| \
jhon309	0:c52df770855b	1051	((BASE) == TIM_DMABase_CNT) \|\| \
jhon309	0:c52df770855b	1052	((BASE) == TIM_DMABase_PSC) \|\| \
jhon309	0:c52df770855b	1053	((BASE) == TIM_DMABase_ARR) \|\| \
jhon309	0:c52df770855b	1054	((BASE) == TIM_DMABase_RCR) \|\| \
jhon309	0:c52df770855b	1055	((BASE) == TIM_DMABase_CCR1) \|\| \
jhon309	0:c52df770855b	1056	((BASE) == TIM_DMABase_CCR2) \|\| \
jhon309	0:c52df770855b	1057	((BASE) == TIM_DMABase_CCR3) \|\| \
jhon309	0:c52df770855b	1058	((BASE) == TIM_DMABase_CCR4) \|\| \
jhon309	0:c52df770855b	1059	((BASE) == TIM_DMABase_BDTR) \|\| \
jhon309	0:c52df770855b	1060	((BASE) == TIM_DMABase_DCR) \|\| \
jhon309	0:c52df770855b	1061	((BASE) == TIM_DMABase_OR))
jhon309	0:c52df770855b	1062	/**
jhon309	0:c52df770855b	1063	* @}
jhon309	0:c52df770855b	1064	*/
jhon309	0:c52df770855b	1065
jhon309	0:c52df770855b	1066	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
jhon309	0:c52df770855b	1067	* @{
jhon309	0:c52df770855b	1068	*/
jhon309	0:c52df770855b	1069
jhon309	0:c52df770855b	1070	#define TIM_DMABurstLength_1Transfer (0x00000000)
jhon309	0:c52df770855b	1071	#define TIM_DMABurstLength_2Transfers (0x00000100)
jhon309	0:c52df770855b	1072	#define TIM_DMABurstLength_3Transfers (0x00000200)
jhon309	0:c52df770855b	1073	#define TIM_DMABurstLength_4Transfers (0x00000300)
jhon309	0:c52df770855b	1074	#define TIM_DMABurstLength_5Transfers (0x00000400)
jhon309	0:c52df770855b	1075	#define TIM_DMABurstLength_6Transfers (0x00000500)
jhon309	0:c52df770855b	1076	#define TIM_DMABurstLength_7Transfers (0x00000600)
jhon309	0:c52df770855b	1077	#define TIM_DMABurstLength_8Transfers (0x00000700)
jhon309	0:c52df770855b	1078	#define TIM_DMABurstLength_9Transfers (0x00000800)
jhon309	0:c52df770855b	1079	#define TIM_DMABurstLength_10Transfers (0x00000900)
jhon309	0:c52df770855b	1080	#define TIM_DMABurstLength_11Transfers (0x00000A00)
jhon309	0:c52df770855b	1081	#define TIM_DMABurstLength_12Transfers (0x00000B00)
jhon309	0:c52df770855b	1082	#define TIM_DMABurstLength_13Transfers (0x00000C00)
jhon309	0:c52df770855b	1083	#define TIM_DMABurstLength_14Transfers (0x00000D00)
jhon309	0:c52df770855b	1084	#define TIM_DMABurstLength_15Transfers (0x00000E00)
jhon309	0:c52df770855b	1085	#define TIM_DMABurstLength_16Transfers (0x00000F00)
jhon309	0:c52df770855b	1086	#define TIM_DMABurstLength_17Transfers (0x00001000)
jhon309	0:c52df770855b	1087	#define TIM_DMABurstLength_18Transfers (0x00001100)
jhon309	0:c52df770855b	1088
jhon309	0:c52df770855b	1089	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) \|\| \
jhon309	0:c52df770855b	1090	((LENGTH) == TIM_DMABurstLength_2Transfers) \|\| \
jhon309	0:c52df770855b	1091	((LENGTH) == TIM_DMABurstLength_3Transfers) \|\| \
jhon309	0:c52df770855b	1092	((LENGTH) == TIM_DMABurstLength_4Transfers) \|\| \
jhon309	0:c52df770855b	1093	((LENGTH) == TIM_DMABurstLength_5Transfers) \|\| \
jhon309	0:c52df770855b	1094	((LENGTH) == TIM_DMABurstLength_6Transfers) \|\| \
jhon309	0:c52df770855b	1095	((LENGTH) == TIM_DMABurstLength_7Transfers) \|\| \
jhon309	0:c52df770855b	1096	((LENGTH) == TIM_DMABurstLength_8Transfers) \|\| \
jhon309	0:c52df770855b	1097	((LENGTH) == TIM_DMABurstLength_9Transfers) \|\| \
jhon309	0:c52df770855b	1098	((LENGTH) == TIM_DMABurstLength_10Transfers) \|\| \
jhon309	0:c52df770855b	1099	((LENGTH) == TIM_DMABurstLength_11Transfers) \|\| \
jhon309	0:c52df770855b	1100	((LENGTH) == TIM_DMABurstLength_12Transfers) \|\| \
jhon309	0:c52df770855b	1101	((LENGTH) == TIM_DMABurstLength_13Transfers) \|\| \
jhon309	0:c52df770855b	1102	((LENGTH) == TIM_DMABurstLength_14Transfers) \|\| \
jhon309	0:c52df770855b	1103	((LENGTH) == TIM_DMABurstLength_15Transfers) \|\| \
jhon309	0:c52df770855b	1104	((LENGTH) == TIM_DMABurstLength_16Transfers) \|\| \
jhon309	0:c52df770855b	1105	((LENGTH) == TIM_DMABurstLength_17Transfers) \|\| \
jhon309	0:c52df770855b	1106	((LENGTH) == TIM_DMABurstLength_18Transfers))
jhon309	0:c52df770855b	1107	/**
jhon309	0:c52df770855b	1108	* @}
jhon309	0:c52df770855b	1109	*/
jhon309	0:c52df770855b	1110
jhon309	0:c52df770855b	1111	/** @defgroup TIM_Input_Capture_Filer_Value TIM Input Capture Value
jhon309	0:c52df770855b	1112	* @{
jhon309	0:c52df770855b	1113	*/
jhon309	0:c52df770855b	1114
jhon309	0:c52df770855b	1115	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
jhon309	0:c52df770855b	1116	/**
jhon309	0:c52df770855b	1117	* @}
jhon309	0:c52df770855b	1118	*/
jhon309	0:c52df770855b	1119
jhon309	0:c52df770855b	1120	/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
jhon309	0:c52df770855b	1121	* @{
jhon309	0:c52df770855b	1122	*/
jhon309	0:c52df770855b	1123	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
jhon309	0:c52df770855b	1124	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
jhon309	0:c52df770855b	1125	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
jhon309	0:c52df770855b	1126	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
jhon309	0:c52df770855b	1127	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
jhon309	0:c52df770855b	1128	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /!< Index of the DMA handle used for Commutation DMA requests /
jhon309	0:c52df770855b	1129	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /!< Index of the DMA handle used for Trigger DMA requests /
jhon309	0:c52df770855b	1130	/**
jhon309	0:c52df770855b	1131	* @}
jhon309	0:c52df770855b	1132	*/
jhon309	0:c52df770855b	1133
jhon309	0:c52df770855b	1134	/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
jhon309	0:c52df770855b	1135	* @{
jhon309	0:c52df770855b	1136	*/
jhon309	0:c52df770855b	1137	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
jhon309	0:c52df770855b	1138	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
jhon309	0:c52df770855b	1139	#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
jhon309	0:c52df770855b	1140	#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
jhon309	0:c52df770855b	1141	/**
jhon309	0:c52df770855b	1142	* @}
jhon309	0:c52df770855b	1143	*/
jhon309	0:c52df770855b	1144
jhon309	0:c52df770855b	1145	/**
jhon309	0:c52df770855b	1146	* @}
jhon309	0:c52df770855b	1147	*/
jhon309	0:c52df770855b	1148
jhon309	0:c52df770855b	1149	/* Exported macros -----------------------------------------------------------*/
jhon309	0:c52df770855b	1150	/** @defgroup TIM_Exported_Macros TIM Exported Macros
jhon309	0:c52df770855b	1151	* @{
jhon309	0:c52df770855b	1152	*/
jhon309	0:c52df770855b	1153
jhon309	0:c52df770855b	1154	/** @brief Reset TIM handle state
jhon309	0:c52df770855b	1155	* @param __HANDLE__: TIM handle.
jhon309	0:c52df770855b	1156	* @retval None
jhon309	0:c52df770855b	1157	*/
jhon309	0:c52df770855b	1158	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
jhon309	0:c52df770855b	1159
jhon309	0:c52df770855b	1160	/**
jhon309	0:c52df770855b	1161	* @brief Enable the TIM peripheral.
jhon309	0:c52df770855b	1162	* @param __HANDLE__: TIM handle
jhon309	0:c52df770855b	1163	* @retval None
jhon309	0:c52df770855b	1164	*/
jhon309	0:c52df770855b	1165	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
jhon309	0:c52df770855b	1166
jhon309	0:c52df770855b	1167	/**
jhon309	0:c52df770855b	1168	* @brief Enable the TIM main Output.
jhon309	0:c52df770855b	1169	* @param __HANDLE__: TIM handle
jhon309	0:c52df770855b	1170	* @retval None
jhon309	0:c52df770855b	1171	*/
jhon309	0:c52df770855b	1172	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
jhon309	0:c52df770855b	1173
jhon309	0:c52df770855b	1174	/**
jhon309	0:c52df770855b	1175	* @brief Disable the TIM peripheral.
jhon309	0:c52df770855b	1176	* @param __HANDLE__: TIM handle
jhon309	0:c52df770855b	1177	* @retval None
jhon309	0:c52df770855b	1178	*/
jhon309	0:c52df770855b	1179	#define __HAL_TIM_DISABLE(__HANDLE__) \
jhon309	0:c52df770855b	1180	do { \
jhon309	0:c52df770855b	1181	if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
jhon309	0:c52df770855b	1182	{ \
jhon309	0:c52df770855b	1183	if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
jhon309	0:c52df770855b	1184	{ \
jhon309	0:c52df770855b	1185	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
jhon309	0:c52df770855b	1186	} \
jhon309	0:c52df770855b	1187	} \
jhon309	0:c52df770855b	1188	} while(0)
jhon309	0:c52df770855b	1189	/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
jhon309	0:c52df770855b	1190	channels have been disabled */
jhon309	0:c52df770855b	1191	/**
jhon309	0:c52df770855b	1192	* @brief Disable the TIM main Output.
jhon309	0:c52df770855b	1193	* @param __HANDLE__: TIM handle
jhon309	0:c52df770855b	1194	* @retval None
jhon309	0:c52df770855b	1195	*/
jhon309	0:c52df770855b	1196	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
jhon309	0:c52df770855b	1197	do { \
jhon309	0:c52df770855b	1198	if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
jhon309	0:c52df770855b	1199	{ \
jhon309	0:c52df770855b	1200	if(((__HANDLE__)->Instance->CCER & CCER_CCxNE_MASK) == 0) \
jhon309	0:c52df770855b	1201	{ \
jhon309	0:c52df770855b	1202	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
jhon309	0:c52df770855b	1203	} \
jhon309	0:c52df770855b	1204	} \
jhon309	0:c52df770855b	1205	} while(0)
jhon309	0:c52df770855b	1206
jhon309	0:c52df770855b	1207	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
jhon309	0:c52df770855b	1208	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
jhon309	0:c52df770855b	1209	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
jhon309	0:c52df770855b	1210	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
jhon309	0:c52df770855b	1211	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
jhon309	0:c52df770855b	1212	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
jhon309	0:c52df770855b	1213
jhon309	0:c52df770855b	1214	#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
jhon309	0:c52df770855b	1215	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
jhon309	0:c52df770855b	1216
jhon309	0:c52df770855b	1217	#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
jhon309	0:c52df770855b	1218	#define __HAL_TIM_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
jhon309	0:c52df770855b	1219
jhon309	0:c52df770855b	1220	#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
jhon309	0:c52df770855b	1221	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
jhon309	0:c52df770855b	1222	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
jhon309	0:c52df770855b	1223	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
jhon309	0:c52df770855b	1224	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
jhon309	0:c52df770855b	1225
jhon309	0:c52df770855b	1226	#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
jhon309	0:c52df770855b	1227	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
jhon309	0:c52df770855b	1228	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
jhon309	0:c52df770855b	1229	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
jhon309	0:c52df770855b	1230	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
jhon309	0:c52df770855b	1231
jhon309	0:c52df770855b	1232	/**
jhon309	0:c52df770855b	1233	* @brief Sets the TIM Capture Compare Register value on runtime without
jhon309	0:c52df770855b	1234	* calling another time ConfigChannel function.
jhon309	0:c52df770855b	1235	* @param __HANDLE__: TIM handle.
jhon309	0:c52df770855b	1236	* @param __CHANNEL__ : TIM Channels to be configured.
jhon309	0:c52df770855b	1237	* This parameter can be one of the following values:
jhon309	0:c52df770855b	1238	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
jhon309	0:c52df770855b	1239	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
jhon309	0:c52df770855b	1240	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
jhon309	0:c52df770855b	1241	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
jhon309	0:c52df770855b	1242	* @param __COMPARE__: specifies the Capture Compare register new value.
jhon309	0:c52df770855b	1243	* @retval None
jhon309	0:c52df770855b	1244	*/
jhon309	0:c52df770855b	1245	#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
jhon309	0:c52df770855b	1246	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
jhon309	0:c52df770855b	1247
jhon309	0:c52df770855b	1248	/**
jhon309	0:c52df770855b	1249	* @brief Gets the TIM Capture Compare Register value on runtime
jhon309	0:c52df770855b	1250	* @param __HANDLE__: TIM handle.
jhon309	0:c52df770855b	1251	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
jhon309	0:c52df770855b	1252	* This parameter can be one of the following values:
jhon309	0:c52df770855b	1253	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
jhon309	0:c52df770855b	1254	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
jhon309	0:c52df770855b	1255	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
jhon309	0:c52df770855b	1256	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
jhon309	0:c52df770855b	1257	* @retval None
jhon309	0:c52df770855b	1258	*/
jhon309	0:c52df770855b	1259	#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
jhon309	0:c52df770855b	1260	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
jhon309	0:c52df770855b	1261
jhon309	0:c52df770855b	1262	/**
jhon309	0:c52df770855b	1263	* @brief Sets the TIM Counter Register value on runtime.
jhon309	0:c52df770855b	1264	* @param __HANDLE__: TIM handle.
jhon309	0:c52df770855b	1265	* @param __COUNTER__: specifies the Counter register new value.
jhon309	0:c52df770855b	1266	* @retval None
jhon309	0:c52df770855b	1267	*/
jhon309	0:c52df770855b	1268	#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
jhon309	0:c52df770855b	1269
jhon309	0:c52df770855b	1270	/**
jhon309	0:c52df770855b	1271	* @brief Gets the TIM Counter Register value on runtime.
jhon309	0:c52df770855b	1272	* @param __HANDLE__: TIM handle.
jhon309	0:c52df770855b	1273	* @retval None
jhon309	0:c52df770855b	1274	*/
jhon309	0:c52df770855b	1275	#define __HAL_TIM_GetCounter(__HANDLE__) \
jhon309	0:c52df770855b	1276	((__HANDLE__)->Instance->CNT)
jhon309	0:c52df770855b	1277
jhon309	0:c52df770855b	1278	/**
jhon309	0:c52df770855b	1279	* @brief Sets the TIM Autoreload Register value on runtime without calling
jhon309	0:c52df770855b	1280	* another time any Init function.
jhon309	0:c52df770855b	1281	* @param __HANDLE__: TIM handle.
jhon309	0:c52df770855b	1282	* @param __AUTORELOAD__: specifies the Counter register new value.
jhon309	0:c52df770855b	1283	* @retval None
jhon309	0:c52df770855b	1284	*/
jhon309	0:c52df770855b	1285	#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
jhon309	0:c52df770855b	1286	do{ \
jhon309	0:c52df770855b	1287	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
jhon309	0:c52df770855b	1288	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
jhon309	0:c52df770855b	1289	} while(0)
jhon309	0:c52df770855b	1290
jhon309	0:c52df770855b	1291	/**
jhon309	0:c52df770855b	1292	* @brief Gets the TIM Autoreload Register value on runtime
jhon309	0:c52df770855b	1293	* @param __HANDLE__: TIM handle.
jhon309	0:c52df770855b	1294	* @retval None
jhon309	0:c52df770855b	1295	*/
jhon309	0:c52df770855b	1296	#define __HAL_TIM_GetAutoreload(__HANDLE__) \
jhon309	0:c52df770855b	1297	((__HANDLE__)->Instance->ARR)
jhon309	0:c52df770855b	1298
jhon309	0:c52df770855b	1299	/**
jhon309	0:c52df770855b	1300	* @brief Sets the TIM Clock Division value on runtime without calling
jhon309	0:c52df770855b	1301	* another time any Init function.
jhon309	0:c52df770855b	1302	* @param __HANDLE__: TIM handle.
jhon309	0:c52df770855b	1303	* @param __CKD__: specifies the clock division value.
jhon309	0:c52df770855b	1304	* This parameter can be one of the following value:
jhon309	0:c52df770855b	1305	* @arg TIM_CLOCKDIVISION_DIV1
jhon309	0:c52df770855b	1306	* @arg TIM_CLOCKDIVISION_DIV2
jhon309	0:c52df770855b	1307	* @arg TIM_CLOCKDIVISION_DIV4
jhon309	0:c52df770855b	1308	* @retval None
jhon309	0:c52df770855b	1309	*/
jhon309	0:c52df770855b	1310	#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
jhon309	0:c52df770855b	1311	do{ \
jhon309	0:c52df770855b	1312	(__HANDLE__)->Instance->CR1 &= ~TIM_CR1_CKD; \
jhon309	0:c52df770855b	1313	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
jhon309	0:c52df770855b	1314	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
jhon309	0:c52df770855b	1315	} while(0)
jhon309	0:c52df770855b	1316
jhon309	0:c52df770855b	1317	/**
jhon309	0:c52df770855b	1318	* @brief Gets the TIM Clock Division value on runtime
jhon309	0:c52df770855b	1319	* @param __HANDLE__: TIM handle.
jhon309	0:c52df770855b	1320	* @retval None
jhon309	0:c52df770855b	1321	*/
jhon309	0:c52df770855b	1322	#define __HAL_TIM_GetClockDivision(__HANDLE__) \
jhon309	0:c52df770855b	1323	((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
jhon309	0:c52df770855b	1324
jhon309	0:c52df770855b	1325	/**
jhon309	0:c52df770855b	1326	* @brief Sets the TIM Input Capture prescaler on runtime without calling
jhon309	0:c52df770855b	1327	* another time HAL_TIM_IC_ConfigChannel() function.
jhon309	0:c52df770855b	1328	* @param __HANDLE__: TIM handle.
jhon309	0:c52df770855b	1329	* @param __CHANNEL__ : TIM Channels to be configured.
jhon309	0:c52df770855b	1330	* This parameter can be one of the following values:
jhon309	0:c52df770855b	1331	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
jhon309	0:c52df770855b	1332	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
jhon309	0:c52df770855b	1333	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
jhon309	0:c52df770855b	1334	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
jhon309	0:c52df770855b	1335	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
jhon309	0:c52df770855b	1336	* This parameter can be one of the following values:
jhon309	0:c52df770855b	1337	* @arg TIM_ICPSC_DIV1: no prescaler
jhon309	0:c52df770855b	1338	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
jhon309	0:c52df770855b	1339	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
jhon309	0:c52df770855b	1340	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
jhon309	0:c52df770855b	1341	* @retval None
jhon309	0:c52df770855b	1342	*/
jhon309	0:c52df770855b	1343	#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
jhon309	0:c52df770855b	1344	do{ \
jhon309	0:c52df770855b	1345	__HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
jhon309	0:c52df770855b	1346	__HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
jhon309	0:c52df770855b	1347	} while(0)
jhon309	0:c52df770855b	1348
jhon309	0:c52df770855b	1349	/**
jhon309	0:c52df770855b	1350	* @brief Gets the TIM Input Capture prescaler on runtime
jhon309	0:c52df770855b	1351	* @param __HANDLE__: TIM handle.
jhon309	0:c52df770855b	1352	* @param __CHANNEL__: TIM Channels to be configured.
jhon309	0:c52df770855b	1353	* This parameter can be one of the following values:
jhon309	0:c52df770855b	1354	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
jhon309	0:c52df770855b	1355	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
jhon309	0:c52df770855b	1356	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
jhon309	0:c52df770855b	1357	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
jhon309	0:c52df770855b	1358	* @retval None
jhon309	0:c52df770855b	1359	*/
jhon309	0:c52df770855b	1360	#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
jhon309	0:c52df770855b	1361	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
jhon309	0:c52df770855b	1362	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
jhon309	0:c52df770855b	1363	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
jhon309	0:c52df770855b	1364	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
jhon309	0:c52df770855b	1365
jhon309	0:c52df770855b	1366	/**
jhon309	0:c52df770855b	1367	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
jhon309	0:c52df770855b	1368	* @param __HANDLE__: TIM handle.
jhon309	0:c52df770855b	1369	* @note When the USR bit of the TIMx_CR1 register is set, only counter
jhon309	0:c52df770855b	1370	* overflow/underflow generates an update interrupt or DMA request (if
jhon309	0:c52df770855b	1371	* enabled)
jhon309	0:c52df770855b	1372	* @retval None
jhon309	0:c52df770855b	1373	*/
jhon309	0:c52df770855b	1374	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
jhon309	0:c52df770855b	1375	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
jhon309	0:c52df770855b	1376
jhon309	0:c52df770855b	1377	/**
jhon309	0:c52df770855b	1378	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
jhon309	0:c52df770855b	1379	* @param __HANDLE__: TIM handle.
jhon309	0:c52df770855b	1380	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
jhon309	0:c52df770855b	1381	* following events generate an update interrupt or DMA request (if
jhon309	0:c52df770855b	1382	* enabled):
jhon309	0:c52df770855b	1383	* (+) Counter overflow/underflow
jhon309	0:c52df770855b	1384	* (+) Setting the UG bit
jhon309	0:c52df770855b	1385	* (+) Update generation through the slave mode controller
jhon309	0:c52df770855b	1386	* @retval None
jhon309	0:c52df770855b	1387	*/
jhon309	0:c52df770855b	1388	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
jhon309	0:c52df770855b	1389	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
jhon309	0:c52df770855b	1390
jhon309	0:c52df770855b	1391	/**
jhon309	0:c52df770855b	1392	* @}
jhon309	0:c52df770855b	1393	*/
jhon309	0:c52df770855b	1394
jhon309	0:c52df770855b	1395	/* Include TIM HAL Extension module */
jhon309	0:c52df770855b	1396	#include "stm32f0xx_hal_tim_ex.h"
jhon309	0:c52df770855b	1397
jhon309	0:c52df770855b	1398	/* Exported functions --------------------------------------------------------*/
jhon309	0:c52df770855b	1399	/** @addtogroup TIM_Exported_Functions TIM Exported Functions
jhon309	0:c52df770855b	1400	* @{
jhon309	0:c52df770855b	1401	*/
jhon309	0:c52df770855b	1402
jhon309	0:c52df770855b	1403	/** @addtogroup TIM_Exported_Functions_Group1 Time Base functions
jhon309	0:c52df770855b	1404	* @brief Time Base functions
jhon309	0:c52df770855b	1405	* @{
jhon309	0:c52df770855b	1406	*/
jhon309	0:c52df770855b	1407	/* Time Base functions ********************************************************/
jhon309	0:c52df770855b	1408	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1409	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1410	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1411	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1412	/* Blocking mode: Polling */
jhon309	0:c52df770855b	1413	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1414	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1415	/* Non-Blocking mode: Interrupt */
jhon309	0:c52df770855b	1416	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1417	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1418	/* Non-Blocking mode: DMA */
jhon309	0:c52df770855b	1419	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
jhon309	0:c52df770855b	1420	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1421	/**
jhon309	0:c52df770855b	1422	* @}
jhon309	0:c52df770855b	1423	*/
jhon309	0:c52df770855b	1424
jhon309	0:c52df770855b	1425	/** @addtogroup TIM_Exported_Functions_Group2 Time Output Compare functions
jhon309	0:c52df770855b	1426	* @brief Time Output Compare functions
jhon309	0:c52df770855b	1427	* @{
jhon309	0:c52df770855b	1428	*/
jhon309	0:c52df770855b	1429	/* Timer Output Compare functions **********************************************/
jhon309	0:c52df770855b	1430	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1431	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1432	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1433	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1434	/* Blocking mode: Polling */
jhon309	0:c52df770855b	1435	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
jhon309	0:c52df770855b	1436	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
jhon309	0:c52df770855b	1437	/* Non-Blocking mode: Interrupt */
jhon309	0:c52df770855b	1438	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
jhon309	0:c52df770855b	1439	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
jhon309	0:c52df770855b	1440	/* Non-Blocking mode: DMA */
jhon309	0:c52df770855b	1441	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
jhon309	0:c52df770855b	1442	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
jhon309	0:c52df770855b	1443	/**
jhon309	0:c52df770855b	1444	* @}
jhon309	0:c52df770855b	1445	*/
jhon309	0:c52df770855b	1446
jhon309	0:c52df770855b	1447	/** @addtogroup TIM_Exported_Functions_Group3 Time PWM functions
jhon309	0:c52df770855b	1448	* @brief Time PWM functions
jhon309	0:c52df770855b	1449	* @{
jhon309	0:c52df770855b	1450	*/
jhon309	0:c52df770855b	1451	/* Timer PWM functions *********************************************************/
jhon309	0:c52df770855b	1452	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1453	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1454	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1455	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1456	/* Blocking mode: Polling */
jhon309	0:c52df770855b	1457	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
jhon309	0:c52df770855b	1458	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
jhon309	0:c52df770855b	1459	/* Non-Blocking mode: Interrupt */
jhon309	0:c52df770855b	1460	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
jhon309	0:c52df770855b	1461	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
jhon309	0:c52df770855b	1462	/* Non-Blocking mode: DMA */
jhon309	0:c52df770855b	1463	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
jhon309	0:c52df770855b	1464	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
jhon309	0:c52df770855b	1465	/**
jhon309	0:c52df770855b	1466	* @}
jhon309	0:c52df770855b	1467	*/
jhon309	0:c52df770855b	1468
jhon309	0:c52df770855b	1469	/** @addtogroup TIM_Exported_Functions_Group4 Time Input Capture functions
jhon309	0:c52df770855b	1470	* @brief Time Input Capture functions
jhon309	0:c52df770855b	1471	* @{
jhon309	0:c52df770855b	1472	*/
jhon309	0:c52df770855b	1473	/* Timer Input Capture functions ***********************************************/
jhon309	0:c52df770855b	1474	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1475	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1476	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1477	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1478	/* Blocking mode: Polling */
jhon309	0:c52df770855b	1479	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
jhon309	0:c52df770855b	1480	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
jhon309	0:c52df770855b	1481	/* Non-Blocking mode: Interrupt */
jhon309	0:c52df770855b	1482	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
jhon309	0:c52df770855b	1483	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
jhon309	0:c52df770855b	1484	/* Non-Blocking mode: DMA */
jhon309	0:c52df770855b	1485	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
jhon309	0:c52df770855b	1486	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
jhon309	0:c52df770855b	1487	/**
jhon309	0:c52df770855b	1488	* @}
jhon309	0:c52df770855b	1489	*/
jhon309	0:c52df770855b	1490
jhon309	0:c52df770855b	1491	/** @addtogroup TIM_Exported_Functions_Group5 Time One Pulse functions
jhon309	0:c52df770855b	1492	* @brief Time One Pulse functions
jhon309	0:c52df770855b	1493	* @{
jhon309	0:c52df770855b	1494	*/
jhon309	0:c52df770855b	1495	/* Timer One Pulse functions ***************************************************/
jhon309	0:c52df770855b	1496	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
jhon309	0:c52df770855b	1497	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1498	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1499	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1500	/* Blocking mode: Polling */
jhon309	0:c52df770855b	1501	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
jhon309	0:c52df770855b	1502	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
jhon309	0:c52df770855b	1503	/* Non-Blocking mode: Interrupt */
jhon309	0:c52df770855b	1504	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
jhon309	0:c52df770855b	1505	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
jhon309	0:c52df770855b	1506	/**
jhon309	0:c52df770855b	1507	* @}
jhon309	0:c52df770855b	1508	*/
jhon309	0:c52df770855b	1509
jhon309	0:c52df770855b	1510	/** @addtogroup TIM_Exported_Functions_Group6 Time Encoder functions
jhon309	0:c52df770855b	1511	* @brief Time Encoder functions
jhon309	0:c52df770855b	1512	* @{
jhon309	0:c52df770855b	1513	*/
jhon309	0:c52df770855b	1514	/* Timer Encoder functions *****************************************************/
jhon309	0:c52df770855b	1515	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
jhon309	0:c52df770855b	1516	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1517	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1518	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1519	/* Blocking mode: Polling */
jhon309	0:c52df770855b	1520	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
jhon309	0:c52df770855b	1521	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
jhon309	0:c52df770855b	1522	/* Non-Blocking mode: Interrupt */
jhon309	0:c52df770855b	1523	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
jhon309	0:c52df770855b	1524	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
jhon309	0:c52df770855b	1525	/* Non-Blocking mode: DMA */
jhon309	0:c52df770855b	1526	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
jhon309	0:c52df770855b	1527	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
jhon309	0:c52df770855b	1528	/**
jhon309	0:c52df770855b	1529	* @}
jhon309	0:c52df770855b	1530	*/
jhon309	0:c52df770855b	1531
jhon309	0:c52df770855b	1532	/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
jhon309	0:c52df770855b	1533	* @brief IRQ handler management
jhon309	0:c52df770855b	1534	* @{
jhon309	0:c52df770855b	1535	*/
jhon309	0:c52df770855b	1536	/* Interrupt Handler functions **********************************************/
jhon309	0:c52df770855b	1537	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1538	/**
jhon309	0:c52df770855b	1539	* @}
jhon309	0:c52df770855b	1540	*/
jhon309	0:c52df770855b	1541
jhon309	0:c52df770855b	1542	/** @addtogroup TIM_Exported_Functions_Group8 Peripheral Control functions
jhon309	0:c52df770855b	1543	* @brief Peripheral Control functions
jhon309	0:c52df770855b	1544	* @{
jhon309	0:c52df770855b	1545	*/
jhon309	0:c52df770855b	1546	/* Control functions *********************************************************/
jhon309	0:c52df770855b	1547	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
jhon309	0:c52df770855b	1548	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
jhon309	0:c52df770855b	1549	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
jhon309	0:c52df770855b	1550	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
jhon309	0:c52df770855b	1551	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
jhon309	0:c52df770855b	1552	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
jhon309	0:c52df770855b	1553	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
jhon309	0:c52df770855b	1554	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
jhon309	0:c52df770855b	1555	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
jhon309	0:c52df770855b	1556	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
jhon309	0:c52df770855b	1557	uint32_t *BurstBuffer, uint32_t BurstLength);
jhon309	0:c52df770855b	1558	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
jhon309	0:c52df770855b	1559	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
jhon309	0:c52df770855b	1560	uint32_t *BurstBuffer, uint32_t BurstLength);
jhon309	0:c52df770855b	1561	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
jhon309	0:c52df770855b	1562	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
jhon309	0:c52df770855b	1563	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
jhon309	0:c52df770855b	1564	/**
jhon309	0:c52df770855b	1565	* @}
jhon309	0:c52df770855b	1566	*/
jhon309	0:c52df770855b	1567
jhon309	0:c52df770855b	1568	/** @addtogroup TIM_Exported_Functions_Group9
jhon309	0:c52df770855b	1569	* @brief TIM Callbacks functions
jhon309	0:c52df770855b	1570	* @{
jhon309	0:c52df770855b	1571	*/
jhon309	0:c52df770855b	1572	/* Callback in non blocking modes (Interrupt and DMA) *************************/
jhon309	0:c52df770855b	1573	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1574	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1575	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1576	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1577	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1578	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1579	/**
jhon309	0:c52df770855b	1580	* @}
jhon309	0:c52df770855b	1581	*/
jhon309	0:c52df770855b	1582
jhon309	0:c52df770855b	1583	/** @addtogroup TIM_Exported_Functions_Group10
jhon309	0:c52df770855b	1584	* @brief Peripheral State functions
jhon309	0:c52df770855b	1585	* @{
jhon309	0:c52df770855b	1586	*/
jhon309	0:c52df770855b	1587	/* Peripheral State functions **************************************************/
jhon309	0:c52df770855b	1588	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1589	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1590	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1591	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1592	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1593	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
jhon309	0:c52df770855b	1594	/**
jhon309	0:c52df770855b	1595	* @}
jhon309	0:c52df770855b	1596	*/
jhon309	0:c52df770855b	1597
jhon309	0:c52df770855b	1598	/**
jhon309	0:c52df770855b	1599	* @}
jhon309	0:c52df770855b	1600	*/
jhon309	0:c52df770855b	1601
jhon309	0:c52df770855b	1602	/* Private Macros -----------------------------------------------------------*/
jhon309	0:c52df770855b	1603	/** @defgroup TIM_Private_Macros TIM Private Macros
jhon309	0:c52df770855b	1604	* @{
jhon309	0:c52df770855b	1605	*/
jhon309	0:c52df770855b	1606	/* The counter of a timer instance is disabled only if all the CCx and CCxN
jhon309	0:c52df770855b	1607	channels have been disabled */
jhon309	0:c52df770855b	1608	#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
jhon309	0:c52df770855b	1609	#define CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
jhon309	0:c52df770855b	1610	/**
jhon309	0:c52df770855b	1611	* @}
jhon309	0:c52df770855b	1612	*/
jhon309	0:c52df770855b	1613
jhon309	0:c52df770855b	1614	/* Private Functions --------------------------------------------------------*/
jhon309	0:c52df770855b	1615	/** @addtogroup TIM_Private_Functions
jhon309	0:c52df770855b	1616	* @{
jhon309	0:c52df770855b	1617	*/
jhon309	0:c52df770855b	1618	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
jhon309	0:c52df770855b	1619	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
jhon309	0:c52df770855b	1620	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
jhon309	0:c52df770855b	1621	void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
jhon309	0:c52df770855b	1622	void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
jhon309	0:c52df770855b	1623	void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
jhon309	0:c52df770855b	1624	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
jhon309	0:c52df770855b	1625
jhon309	0:c52df770855b	1626	/**
jhon309	0:c52df770855b	1627	* @}
jhon309	0:c52df770855b	1628	*/
jhon309	0:c52df770855b	1629
jhon309	0:c52df770855b	1630	/**
jhon309	0:c52df770855b	1631	* @}
jhon309	0:c52df770855b	1632	*/
jhon309	0:c52df770855b	1633
jhon309	0:c52df770855b	1634	/**
jhon309	0:c52df770855b	1635	* @}
jhon309	0:c52df770855b	1636	*/
jhon309	0:c52df770855b	1637
jhon309	0:c52df770855b	1638	#ifdef __cplusplus
jhon309	0:c52df770855b	1639	}
jhon309	0:c52df770855b	1640	#endif
jhon309	0:c52df770855b	1641
jhon309	0:c52df770855b	1642	#endif /* __STM32F0xx_HAL_TIM_H */
jhon309	0:c52df770855b	1643
jhon309	0:c52df770855b	1644	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
jhon309	0:c52df770855b	1645

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Type:	Library
Created:	13 Aug 2015
Imports:	191
Forks:	0
Commits:	1
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TARGET_NUCLEO_F072RB/stm32f0xx_hal_tim.h@0:c52df770855b, 2015-08-13 (annotated)

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