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TARGET_NUCLEO_F072RB/stm32f0xx_hal_rcc_ex.h@0:c52df770855b, 2015-08-13 (annotated)

Committer:: jhon309
Date:: Thu Aug 13 00:21:57 2015 +0000
Revision:: 0:c52df770855b

DHT11

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jhon309	0:c52df770855b	1	/**
jhon309	0:c52df770855b	2	******************************************************************************
jhon309	0:c52df770855b	3	* @file stm32f0xx_hal_rcc_ex.h
jhon309	0:c52df770855b	4	* @author MCD Application Team
jhon309	0:c52df770855b	5	* @version V1.2.0
jhon309	0:c52df770855b	6	* @date 11-December-2014
jhon309	0:c52df770855b	7	* @brief Header file of RCC HAL Extension module.
jhon309	0:c52df770855b	8	******************************************************************************
jhon309	0:c52df770855b	9	* @attention
jhon309	0:c52df770855b	10	*
jhon309	0:c52df770855b	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
jhon309	0:c52df770855b	12	*
jhon309	0:c52df770855b	13	* Redistribution and use in source and binary forms, with or without modification,
jhon309	0:c52df770855b	14	* are permitted provided that the following conditions are met:
jhon309	0:c52df770855b	15	* 1. Redistributions of source code must retain the above copyright notice,
jhon309	0:c52df770855b	16	* this list of conditions and the following disclaimer.
jhon309	0:c52df770855b	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
jhon309	0:c52df770855b	18	* this list of conditions and the following disclaimer in the documentation
jhon309	0:c52df770855b	19	* and/or other materials provided with the distribution.
jhon309	0:c52df770855b	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
jhon309	0:c52df770855b	21	* may be used to endorse or promote products derived from this software
jhon309	0:c52df770855b	22	* without specific prior written permission.
jhon309	0:c52df770855b	23	*
jhon309	0:c52df770855b	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jhon309	0:c52df770855b	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jhon309	0:c52df770855b	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
jhon309	0:c52df770855b	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
jhon309	0:c52df770855b	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
jhon309	0:c52df770855b	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
jhon309	0:c52df770855b	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
jhon309	0:c52df770855b	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
jhon309	0:c52df770855b	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
jhon309	0:c52df770855b	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
jhon309	0:c52df770855b	34	*
jhon309	0:c52df770855b	35	******************************************************************************
jhon309	0:c52df770855b	36	*/
jhon309	0:c52df770855b	37
jhon309	0:c52df770855b	38	/* Define to prevent recursive inclusion -------------------------------------*/
jhon309	0:c52df770855b	39	#ifndef __STM32F0xx_HAL_RCC_EX_H
jhon309	0:c52df770855b	40	#define __STM32F0xx_HAL_RCC_EX_H
jhon309	0:c52df770855b	41
jhon309	0:c52df770855b	42	#ifdef __cplusplus
jhon309	0:c52df770855b	43	extern "C" {
jhon309	0:c52df770855b	44	#endif
jhon309	0:c52df770855b	45
jhon309	0:c52df770855b	46	/* Includes ------------------------------------------------------------------*/
jhon309	0:c52df770855b	47	#include "stm32f0xx_hal_def.h"
jhon309	0:c52df770855b	48
jhon309	0:c52df770855b	49	/** @addtogroup STM32F0xx_HAL_Driver
jhon309	0:c52df770855b	50	* @{
jhon309	0:c52df770855b	51	*/
jhon309	0:c52df770855b	52
jhon309	0:c52df770855b	53	/** @addtogroup RCCEx
jhon309	0:c52df770855b	54	* @{
jhon309	0:c52df770855b	55	*/
jhon309	0:c52df770855b	56
jhon309	0:c52df770855b	57	/* Exported types ------------------------------------------------------------*/
jhon309	0:c52df770855b	58
jhon309	0:c52df770855b	59	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
jhon309	0:c52df770855b	60	* @{
jhon309	0:c52df770855b	61	*/
jhon309	0:c52df770855b	62
jhon309	0:c52df770855b	63	/**
jhon309	0:c52df770855b	64	* @brief RCC extended clocks structure definition
jhon309	0:c52df770855b	65	*/
jhon309	0:c52df770855b	66	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
jhon309	0:c52df770855b	67	defined(STM32F030xC)
jhon309	0:c52df770855b	68	typedef struct
jhon309	0:c52df770855b	69	{
jhon309	0:c52df770855b	70	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
jhon309	0:c52df770855b	71	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
jhon309	0:c52df770855b	72
jhon309	0:c52df770855b	73	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
jhon309	0:c52df770855b	74	This parameter can be a value of @ref RCC_RTC_Clock_Source */
jhon309	0:c52df770855b	75
jhon309	0:c52df770855b	76	uint32_t Usart1ClockSelection; /*!< USART1 clock source
jhon309	0:c52df770855b	77	This parameter can be a value of @ref RCC_USART1_Clock_Source */
jhon309	0:c52df770855b	78
jhon309	0:c52df770855b	79	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
jhon309	0:c52df770855b	80	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
jhon309	0:c52df770855b	81
jhon309	0:c52df770855b	82	}RCC_PeriphCLKInitTypeDef;
jhon309	0:c52df770855b	83	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
jhon309	0:c52df770855b	84	STM32F030xC */
jhon309	0:c52df770855b	85
jhon309	0:c52df770855b	86	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
jhon309	0:c52df770855b	87	typedef struct
jhon309	0:c52df770855b	88	{
jhon309	0:c52df770855b	89	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
jhon309	0:c52df770855b	90	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
jhon309	0:c52df770855b	91
jhon309	0:c52df770855b	92	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
jhon309	0:c52df770855b	93	This parameter can be a value of @ref RCC_RTC_Clock_Source */
jhon309	0:c52df770855b	94
jhon309	0:c52df770855b	95	uint32_t Usart1ClockSelection; /*!< USART1 clock source
jhon309	0:c52df770855b	96	This parameter can be a value of @ref RCC_USART1_Clock_Source */
jhon309	0:c52df770855b	97
jhon309	0:c52df770855b	98	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
jhon309	0:c52df770855b	99	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
jhon309	0:c52df770855b	100
jhon309	0:c52df770855b	101	uint32_t UsbClockSelection; /*!< USB clock source
jhon309	0:c52df770855b	102	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
jhon309	0:c52df770855b	103
jhon309	0:c52df770855b	104	}RCC_PeriphCLKInitTypeDef;
jhon309	0:c52df770855b	105	#endif /* STM32F070x6 \|\| STM32F070xB */
jhon309	0:c52df770855b	106
jhon309	0:c52df770855b	107	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
jhon309	0:c52df770855b	108	typedef struct
jhon309	0:c52df770855b	109	{
jhon309	0:c52df770855b	110	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
jhon309	0:c52df770855b	111	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
jhon309	0:c52df770855b	112
jhon309	0:c52df770855b	113	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
jhon309	0:c52df770855b	114	This parameter can be a value of @ref RCC_RTC_Clock_Source */
jhon309	0:c52df770855b	115
jhon309	0:c52df770855b	116	uint32_t Usart1ClockSelection; /*!< USART1 clock source
jhon309	0:c52df770855b	117	This parameter can be a value of @ref RCC_USART1_Clock_Source */
jhon309	0:c52df770855b	118
jhon309	0:c52df770855b	119	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
jhon309	0:c52df770855b	120	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
jhon309	0:c52df770855b	121
jhon309	0:c52df770855b	122	uint32_t CecClockSelection; /*!< HDMI CEC clock source
jhon309	0:c52df770855b	123	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
jhon309	0:c52df770855b	124
jhon309	0:c52df770855b	125	uint32_t UsbClockSelection; /*!< USB clock source
jhon309	0:c52df770855b	126	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
jhon309	0:c52df770855b	127
jhon309	0:c52df770855b	128	}RCC_PeriphCLKInitTypeDef;
jhon309	0:c52df770855b	129	#endif /* STM32F042x6 \|\| STM32F048xx */
jhon309	0:c52df770855b	130
jhon309	0:c52df770855b	131	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
jhon309	0:c52df770855b	132	typedef struct
jhon309	0:c52df770855b	133	{
jhon309	0:c52df770855b	134	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
jhon309	0:c52df770855b	135	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
jhon309	0:c52df770855b	136
jhon309	0:c52df770855b	137	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
jhon309	0:c52df770855b	138	This parameter can be a value of @ref RCC_RTC_Clock_Source */
jhon309	0:c52df770855b	139
jhon309	0:c52df770855b	140	uint32_t Usart1ClockSelection; /*!< USART1 clock source
jhon309	0:c52df770855b	141	This parameter can be a value of @ref RCC_USART1_Clock_Source */
jhon309	0:c52df770855b	142
jhon309	0:c52df770855b	143	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
jhon309	0:c52df770855b	144	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
jhon309	0:c52df770855b	145
jhon309	0:c52df770855b	146	uint32_t CecClockSelection; /*!< HDMI CEC clock source
jhon309	0:c52df770855b	147	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
jhon309	0:c52df770855b	148
jhon309	0:c52df770855b	149	}RCC_PeriphCLKInitTypeDef;
jhon309	0:c52df770855b	150	#endif /* STM32F051x8 \|\| STM32F058xx */
jhon309	0:c52df770855b	151
jhon309	0:c52df770855b	152	#if defined(STM32F071xB)
jhon309	0:c52df770855b	153	typedef struct
jhon309	0:c52df770855b	154	{
jhon309	0:c52df770855b	155	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
jhon309	0:c52df770855b	156	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
jhon309	0:c52df770855b	157
jhon309	0:c52df770855b	158	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
jhon309	0:c52df770855b	159	This parameter can be a value of @ref RCC_RTC_Clock_Source */
jhon309	0:c52df770855b	160
jhon309	0:c52df770855b	161	uint32_t Usart1ClockSelection; /*!< USART1 clock source
jhon309	0:c52df770855b	162	This parameter can be a value of @ref RCC_USART1_Clock_Source */
jhon309	0:c52df770855b	163
jhon309	0:c52df770855b	164	uint32_t Usart2ClockSelection; /*!< USART2 clock source
jhon309	0:c52df770855b	165	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
jhon309	0:c52df770855b	166
jhon309	0:c52df770855b	167	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
jhon309	0:c52df770855b	168	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
jhon309	0:c52df770855b	169
jhon309	0:c52df770855b	170	uint32_t CecClockSelection; /*!< HDMI CEC clock source
jhon309	0:c52df770855b	171	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
jhon309	0:c52df770855b	172
jhon309	0:c52df770855b	173	}RCC_PeriphCLKInitTypeDef;
jhon309	0:c52df770855b	174	#endif /* STM32F071xB */
jhon309	0:c52df770855b	175
jhon309	0:c52df770855b	176	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
jhon309	0:c52df770855b	177	typedef struct
jhon309	0:c52df770855b	178	{
jhon309	0:c52df770855b	179	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
jhon309	0:c52df770855b	180	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
jhon309	0:c52df770855b	181
jhon309	0:c52df770855b	182	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
jhon309	0:c52df770855b	183	This parameter can be a value of @ref RCC_RTC_Clock_Source */
jhon309	0:c52df770855b	184
jhon309	0:c52df770855b	185	uint32_t Usart1ClockSelection; /*!< USART1 clock source
jhon309	0:c52df770855b	186	This parameter can be a value of @ref RCC_USART1_Clock_Source */
jhon309	0:c52df770855b	187
jhon309	0:c52df770855b	188	uint32_t Usart2ClockSelection; /*!< USART2 clock source
jhon309	0:c52df770855b	189	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
jhon309	0:c52df770855b	190
jhon309	0:c52df770855b	191	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
jhon309	0:c52df770855b	192	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
jhon309	0:c52df770855b	193
jhon309	0:c52df770855b	194	uint32_t CecClockSelection; /*!< HDMI CEC clock source
jhon309	0:c52df770855b	195	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
jhon309	0:c52df770855b	196
jhon309	0:c52df770855b	197	uint32_t UsbClockSelection; /*!< USB clock source
jhon309	0:c52df770855b	198	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
jhon309	0:c52df770855b	199
jhon309	0:c52df770855b	200	}RCC_PeriphCLKInitTypeDef;
jhon309	0:c52df770855b	201	#endif /* STM32F072xB \|\| STM32F078xx */
jhon309	0:c52df770855b	202
jhon309	0:c52df770855b	203
jhon309	0:c52df770855b	204	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	205	typedef struct
jhon309	0:c52df770855b	206	{
jhon309	0:c52df770855b	207	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
jhon309	0:c52df770855b	208	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
jhon309	0:c52df770855b	209
jhon309	0:c52df770855b	210	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
jhon309	0:c52df770855b	211	This parameter can be a value of @ref RCC_RTC_Clock_Source */
jhon309	0:c52df770855b	212
jhon309	0:c52df770855b	213	uint32_t Usart1ClockSelection; /*!< USART1 clock source
jhon309	0:c52df770855b	214	This parameter can be a value of @ref RCC_USART1_Clock_Source */
jhon309	0:c52df770855b	215
jhon309	0:c52df770855b	216	uint32_t Usart2ClockSelection; /*!< USART2 clock source
jhon309	0:c52df770855b	217	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
jhon309	0:c52df770855b	218
jhon309	0:c52df770855b	219	uint32_t Usart3ClockSelection; /*!< USART3 clock source
jhon309	0:c52df770855b	220	This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
jhon309	0:c52df770855b	221
jhon309	0:c52df770855b	222	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
jhon309	0:c52df770855b	223	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
jhon309	0:c52df770855b	224
jhon309	0:c52df770855b	225	uint32_t CecClockSelection; /*!< HDMI CEC clock source
jhon309	0:c52df770855b	226	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
jhon309	0:c52df770855b	227
jhon309	0:c52df770855b	228	}RCC_PeriphCLKInitTypeDef;
jhon309	0:c52df770855b	229	#endif /* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	230
jhon309	0:c52df770855b	231	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:c52df770855b	232	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	233	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	234
jhon309	0:c52df770855b	235	/**
jhon309	0:c52df770855b	236	* @brief RCC_CRS Init structure definition
jhon309	0:c52df770855b	237	*/
jhon309	0:c52df770855b	238	typedef struct
jhon309	0:c52df770855b	239	{
jhon309	0:c52df770855b	240	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
jhon309	0:c52df770855b	241	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
jhon309	0:c52df770855b	242
jhon309	0:c52df770855b	243	uint32_t Source; /*!< Specifies the SYNC signal source.
jhon309	0:c52df770855b	244	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
jhon309	0:c52df770855b	245
jhon309	0:c52df770855b	246	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
jhon309	0:c52df770855b	247	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
jhon309	0:c52df770855b	248
jhon309	0:c52df770855b	249	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
jhon309	0:c52df770855b	250	It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
jhon309	0:c52df770855b	251	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
jhon309	0:c52df770855b	252
jhon309	0:c52df770855b	253	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
jhon309	0:c52df770855b	254	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
jhon309	0:c52df770855b	255
jhon309	0:c52df770855b	256	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
jhon309	0:c52df770855b	257	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
jhon309	0:c52df770855b	258
jhon309	0:c52df770855b	259	}RCC_CRSInitTypeDef;
jhon309	0:c52df770855b	260
jhon309	0:c52df770855b	261	/**
jhon309	0:c52df770855b	262	* @brief RCC_CRS Synchronization structure definition
jhon309	0:c52df770855b	263	*/
jhon309	0:c52df770855b	264	typedef struct
jhon309	0:c52df770855b	265	{
jhon309	0:c52df770855b	266	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
jhon309	0:c52df770855b	267	This parameter must be a number between 0 and 0xFFFF*/
jhon309	0:c52df770855b	268
jhon309	0:c52df770855b	269	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
jhon309	0:c52df770855b	270	This parameter must be a number between 0 and 0x3F */
jhon309	0:c52df770855b	271
jhon309	0:c52df770855b	272	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
jhon309	0:c52df770855b	273	value latched in the time of the last SYNC event.
jhon309	0:c52df770855b	274	This parameter must be a number between 0 and 0xFFFF */
jhon309	0:c52df770855b	275
jhon309	0:c52df770855b	276	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
jhon309	0:c52df770855b	277	frequency error counter latched in the time of the last SYNC event.
jhon309	0:c52df770855b	278	It shows whether the actual frequency is below or above the target.
jhon309	0:c52df770855b	279	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
jhon309	0:c52df770855b	280
jhon309	0:c52df770855b	281	}RCC_CRSSynchroInfoTypeDef;
jhon309	0:c52df770855b	282
jhon309	0:c52df770855b	283	#endif /* STM32F042x6 \|\| STM32F048xx */
jhon309	0:c52df770855b	284	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:c52df770855b	285	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	286
jhon309	0:c52df770855b	287	/**
jhon309	0:c52df770855b	288	* @}
jhon309	0:c52df770855b	289	*/
jhon309	0:c52df770855b	290
jhon309	0:c52df770855b	291	/* Exported constants --------------------------------------------------------*/
jhon309	0:c52df770855b	292
jhon309	0:c52df770855b	293	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
jhon309	0:c52df770855b	294	* @{
jhon309	0:c52df770855b	295	*/
jhon309	0:c52df770855b	296
jhon309	0:c52df770855b	297	/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
jhon309	0:c52df770855b	298	* @{
jhon309	0:c52df770855b	299	*/
jhon309	0:c52df770855b	300	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:c52df770855b	301	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	302	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	303
jhon309	0:c52df770855b	304	#define RCC_CRS_NONE ((uint32_t)0x00000000)
jhon309	0:c52df770855b	305	#define RCC_CRS_TIMEOUT ((uint32_t)0x00000001)
jhon309	0:c52df770855b	306	#define RCC_CRS_SYNCOK ((uint32_t)0x00000002)
jhon309	0:c52df770855b	307	#define RCC_CRS_SYNCWARM ((uint32_t)0x00000004)
jhon309	0:c52df770855b	308	#define RCC_CRS_SYNCERR ((uint32_t)0x00000008)
jhon309	0:c52df770855b	309	#define RCC_CRS_SYNCMISS ((uint32_t)0x00000010)
jhon309	0:c52df770855b	310	#define RCC_CRS_TRIMOV ((uint32_t)0x00000020)
jhon309	0:c52df770855b	311
jhon309	0:c52df770855b	312	#endif /* STM32F042x6 \|\| STM32F048xx */
jhon309	0:c52df770855b	313	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:c52df770855b	314	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	315	/**
jhon309	0:c52df770855b	316	* @}
jhon309	0:c52df770855b	317	*/
jhon309	0:c52df770855b	318
jhon309	0:c52df770855b	319	/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
jhon309	0:c52df770855b	320	* @{
jhon309	0:c52df770855b	321	*/
jhon309	0:c52df770855b	322	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
jhon309	0:c52df770855b	323	defined(STM32F030xC)
jhon309	0:c52df770855b	324	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
jhon309	0:c52df770855b	325	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
jhon309	0:c52df770855b	326	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
jhon309	0:c52df770855b	327
jhon309	0:c52df770855b	328	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
jhon309	0:c52df770855b	329	RCC_PERIPHCLK_RTC))
jhon309	0:c52df770855b	330	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
jhon309	0:c52df770855b	331	STM32F030xC */
jhon309	0:c52df770855b	332
jhon309	0:c52df770855b	333	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
jhon309	0:c52df770855b	334	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
jhon309	0:c52df770855b	335	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
jhon309	0:c52df770855b	336	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
jhon309	0:c52df770855b	337	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
jhon309	0:c52df770855b	338
jhon309	0:c52df770855b	339	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
jhon309	0:c52df770855b	340	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
jhon309	0:c52df770855b	341	#endif /* STM32F070x6 \|\| STM32F070xB */
jhon309	0:c52df770855b	342
jhon309	0:c52df770855b	343	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
jhon309	0:c52df770855b	344	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
jhon309	0:c52df770855b	345	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
jhon309	0:c52df770855b	346	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
jhon309	0:c52df770855b	347	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
jhon309	0:c52df770855b	348	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
jhon309	0:c52df770855b	349
jhon309	0:c52df770855b	350	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
jhon309	0:c52df770855b	351	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC \| \
jhon309	0:c52df770855b	352	RCC_PERIPHCLK_USB))
jhon309	0:c52df770855b	353	#endif /* STM32F042x6 \|\| STM32F048xx */
jhon309	0:c52df770855b	354
jhon309	0:c52df770855b	355	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
jhon309	0:c52df770855b	356	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
jhon309	0:c52df770855b	357	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
jhon309	0:c52df770855b	358	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
jhon309	0:c52df770855b	359	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
jhon309	0:c52df770855b	360
jhon309	0:c52df770855b	361	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
jhon309	0:c52df770855b	362	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC))
jhon309	0:c52df770855b	363	#endif /* STM32F051x8 \|\| STM32F058xx */
jhon309	0:c52df770855b	364
jhon309	0:c52df770855b	365	#if defined(STM32F071xB)
jhon309	0:c52df770855b	366	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
jhon309	0:c52df770855b	367	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
jhon309	0:c52df770855b	368	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
jhon309	0:c52df770855b	369	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
jhon309	0:c52df770855b	370	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
jhon309	0:c52df770855b	371
jhon309	0:c52df770855b	372	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
jhon309	0:c52df770855b	373	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
jhon309	0:c52df770855b	374	RCC_PERIPHCLK_RTC))
jhon309	0:c52df770855b	375	#endif /* STM32F071xB */
jhon309	0:c52df770855b	376
jhon309	0:c52df770855b	377	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
jhon309	0:c52df770855b	378	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
jhon309	0:c52df770855b	379	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
jhon309	0:c52df770855b	380	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
jhon309	0:c52df770855b	381	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
jhon309	0:c52df770855b	382	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
jhon309	0:c52df770855b	383	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
jhon309	0:c52df770855b	384
jhon309	0:c52df770855b	385	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
jhon309	0:c52df770855b	386	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
jhon309	0:c52df770855b	387	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
jhon309	0:c52df770855b	388	#endif /* STM32F072xB \|\| STM32F078xx */
jhon309	0:c52df770855b	389
jhon309	0:c52df770855b	390	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	391	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
jhon309	0:c52df770855b	392	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
jhon309	0:c52df770855b	393	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
jhon309	0:c52df770855b	394	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
jhon309	0:c52df770855b	395	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
jhon309	0:c52df770855b	396	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00040000)
jhon309	0:c52df770855b	397
jhon309	0:c52df770855b	398	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
jhon309	0:c52df770855b	399	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
jhon309	0:c52df770855b	400	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USART3 ))
jhon309	0:c52df770855b	401	#endif /* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	402
jhon309	0:c52df770855b	403	/**
jhon309	0:c52df770855b	404	* @}
jhon309	0:c52df770855b	405	*/
jhon309	0:c52df770855b	406
jhon309	0:c52df770855b	407	/** @defgroup RCCEx_MCO_Clock_Source RCCEx MCO Clock Source
jhon309	0:c52df770855b	408	* @{
jhon309	0:c52df770855b	409	*/
jhon309	0:c52df770855b	410
jhon309	0:c52df770855b	411	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6) \|\| defined(STM32F070xB) \|\| defined(STM32F030xC)
jhon309	0:c52df770855b	412
jhon309	0:c52df770855b	413	#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
jhon309	0:c52df770855b	414
jhon309	0:c52df770855b	415	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
jhon309	0:c52df770855b	416	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
jhon309	0:c52df770855b	417	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
jhon309	0:c52df770855b	418	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
jhon309	0:c52df770855b	419	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
jhon309	0:c52df770855b	420	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
jhon309	0:c52df770855b	421	((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) \|\| \
jhon309	0:c52df770855b	422	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
jhon309	0:c52df770855b	423	((SOURCE) == RCC_MCOSOURCE_HSI14))
jhon309	0:c52df770855b	424
jhon309	0:c52df770855b	425	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F070x6 \|\| STM32F070xB \|\| STM32F030xC */
jhon309	0:c52df770855b	426
jhon309	0:c52df770855b	427	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
jhon309	0:c52df770855b	428
jhon309	0:c52df770855b	429	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
jhon309	0:c52df770855b	430	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
jhon309	0:c52df770855b	431	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
jhon309	0:c52df770855b	432	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
jhon309	0:c52df770855b	433	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
jhon309	0:c52df770855b	434	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
jhon309	0:c52df770855b	435	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
jhon309	0:c52df770855b	436	((SOURCE) == RCC_MCOSOURCE_HSI14))
jhon309	0:c52df770855b	437
jhon309	0:c52df770855b	438	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
jhon309	0:c52df770855b	439
jhon309	0:c52df770855b	440	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:c52df770855b	441	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	442	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	443
jhon309	0:c52df770855b	444	#define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48
jhon309	0:c52df770855b	445	#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
jhon309	0:c52df770855b	446
jhon309	0:c52df770855b	447	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
jhon309	0:c52df770855b	448	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
jhon309	0:c52df770855b	449	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
jhon309	0:c52df770855b	450	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
jhon309	0:c52df770855b	451	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
jhon309	0:c52df770855b	452	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
jhon309	0:c52df770855b	453	((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) \|\| \
jhon309	0:c52df770855b	454	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
jhon309	0:c52df770855b	455	((SOURCE) == RCC_MCOSOURCE_HSI14) \|\| \
jhon309	0:c52df770855b	456	((SOURCE) == RCC_MCOSOURCE_HSI48))
jhon309	0:c52df770855b	457
jhon309	0:c52df770855b	458	#define RCC_IT_HSI48 ((uint8_t)0x40)
jhon309	0:c52df770855b	459
jhon309	0:c52df770855b	460	/* Flags in the CR2 register */
jhon309	0:c52df770855b	461	#define RCC_CR2_HSI48RDY_BitNumber 16
jhon309	0:c52df770855b	462
jhon309	0:c52df770855b	463	#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) \| RCC_CR2_HSI48RDY_BitNumber))
jhon309	0:c52df770855b	464
jhon309	0:c52df770855b	465	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:c52df770855b	466	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:c52df770855b	467	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	468	/**
jhon309	0:c52df770855b	469	* @}
jhon309	0:c52df770855b	470	*/
jhon309	0:c52df770855b	471
jhon309	0:c52df770855b	472	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
jhon309	0:c52df770855b	473
jhon309	0:c52df770855b	474	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
jhon309	0:c52df770855b	475	* @{
jhon309	0:c52df770855b	476	*/
jhon309	0:c52df770855b	477	#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48
jhon309	0:c52df770855b	478	#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
jhon309	0:c52df770855b	479
jhon309	0:c52df770855b	480	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) \|\| \
jhon309	0:c52df770855b	481	((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
jhon309	0:c52df770855b	482	/**
jhon309	0:c52df770855b	483	* @}
jhon309	0:c52df770855b	484	*/
jhon309	0:c52df770855b	485
jhon309	0:c52df770855b	486	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| STM32F078xx */
jhon309	0:c52df770855b	487
jhon309	0:c52df770855b	488	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
jhon309	0:c52df770855b	489
jhon309	0:c52df770855b	490	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
jhon309	0:c52df770855b	491	* @{
jhon309	0:c52df770855b	492	*/
jhon309	0:c52df770855b	493	#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
jhon309	0:c52df770855b	494
jhon309	0:c52df770855b	495	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
jhon309	0:c52df770855b	496	/**
jhon309	0:c52df770855b	497	* @}
jhon309	0:c52df770855b	498	*/
jhon309	0:c52df770855b	499
jhon309	0:c52df770855b	500	#endif /* STM32F070x6 \|\| STM32F070xB */
jhon309	0:c52df770855b	501
jhon309	0:c52df770855b	502	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	503	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	504
jhon309	0:c52df770855b	505	/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
jhon309	0:c52df770855b	506	* @{
jhon309	0:c52df770855b	507	*/
jhon309	0:c52df770855b	508	#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
jhon309	0:c52df770855b	509	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
jhon309	0:c52df770855b	510	#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
jhon309	0:c52df770855b	511	#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
jhon309	0:c52df770855b	512
jhon309	0:c52df770855b	513	#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
jhon309	0:c52df770855b	514	((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
jhon309	0:c52df770855b	515	((SOURCE) == RCC_USART2CLKSOURCE_LSE) \|\| \
jhon309	0:c52df770855b	516	((SOURCE) == RCC_USART2CLKSOURCE_HSI))
jhon309	0:c52df770855b	517	/**
jhon309	0:c52df770855b	518	* @}
jhon309	0:c52df770855b	519	*/
jhon309	0:c52df770855b	520
jhon309	0:c52df770855b	521	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:c52df770855b	522	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	523
jhon309	0:c52df770855b	524	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	525
jhon309	0:c52df770855b	526	/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
jhon309	0:c52df770855b	527	* @{
jhon309	0:c52df770855b	528	*/
jhon309	0:c52df770855b	529	#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
jhon309	0:c52df770855b	530	#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
jhon309	0:c52df770855b	531	#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
jhon309	0:c52df770855b	532	#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
jhon309	0:c52df770855b	533
jhon309	0:c52df770855b	534	#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) \|\| \
jhon309	0:c52df770855b	535	((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) \|\| \
jhon309	0:c52df770855b	536	((SOURCE) == RCC_USART3CLKSOURCE_LSE) \|\| \
jhon309	0:c52df770855b	537	((SOURCE) == RCC_USART3CLKSOURCE_HSI))
jhon309	0:c52df770855b	538	/**
jhon309	0:c52df770855b	539	* @}
jhon309	0:c52df770855b	540	*/
jhon309	0:c52df770855b	541
jhon309	0:c52df770855b	542	#endif /* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	543
jhon309	0:c52df770855b	544
jhon309	0:c52df770855b	545	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:c52df770855b	546	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:c52df770855b	547	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	548	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	549
jhon309	0:c52df770855b	550	/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
jhon309	0:c52df770855b	551	* @{
jhon309	0:c52df770855b	552	*/
jhon309	0:c52df770855b	553	#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
jhon309	0:c52df770855b	554	#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
jhon309	0:c52df770855b	555
jhon309	0:c52df770855b	556	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
jhon309	0:c52df770855b	557	((SOURCE) == RCC_CECCLKSOURCE_LSE))
jhon309	0:c52df770855b	558	/**
jhon309	0:c52df770855b	559	* @}
jhon309	0:c52df770855b	560	*/
jhon309	0:c52df770855b	561
jhon309	0:c52df770855b	562	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:c52df770855b	563	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:c52df770855b	564	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:c52df770855b	565	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	566
jhon309	0:c52df770855b	567	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:c52df770855b	568	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	569	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	570
jhon309	0:c52df770855b	571	/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
jhon309	0:c52df770855b	572	* @{
jhon309	0:c52df770855b	573	*/
jhon309	0:c52df770855b	574	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
jhon309	0:c52df770855b	575	#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
jhon309	0:c52df770855b	576
jhon309	0:c52df770855b	577	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
jhon309	0:c52df770855b	578	((SOURCE) == RCC_PLLSOURCE_HSI48) \|\| \
jhon309	0:c52df770855b	579	((SOURCE) == RCC_PLLSOURCE_HSE))
jhon309	0:c52df770855b	580	/**
jhon309	0:c52df770855b	581	* @}
jhon309	0:c52df770855b	582	*/
jhon309	0:c52df770855b	583
jhon309	0:c52df770855b	584	/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
jhon309	0:c52df770855b	585	* @{
jhon309	0:c52df770855b	586	*/
jhon309	0:c52df770855b	587	#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
jhon309	0:c52df770855b	588
jhon309	0:c52df770855b	589	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
jhon309	0:c52df770855b	590	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
jhon309	0:c52df770855b	591	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) \|\| \
jhon309	0:c52df770855b	592	((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
jhon309	0:c52df770855b	593
jhon309	0:c52df770855b	594	#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
jhon309	0:c52df770855b	595
jhon309	0:c52df770855b	596	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
jhon309	0:c52df770855b	597	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
jhon309	0:c52df770855b	598	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) \|\| \
jhon309	0:c52df770855b	599	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
jhon309	0:c52df770855b	600	/**
jhon309	0:c52df770855b	601	* @}
jhon309	0:c52df770855b	602	*/
jhon309	0:c52df770855b	603
jhon309	0:c52df770855b	604	/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
jhon309	0:c52df770855b	605	* @{
jhon309	0:c52df770855b	606	*/
jhon309	0:c52df770855b	607	#define RCC_HSI48_OFF ((uint8_t)0x00)
jhon309	0:c52df770855b	608	#define RCC_HSI48_ON ((uint8_t)0x01)
jhon309	0:c52df770855b	609
jhon309	0:c52df770855b	610	#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) \|\| ((HSI48) == RCC_HSI48_ON))
jhon309	0:c52df770855b	611	/**
jhon309	0:c52df770855b	612	* @}
jhon309	0:c52df770855b	613	*/
jhon309	0:c52df770855b	614	#else
jhon309	0:c52df770855b	615	/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
jhon309	0:c52df770855b	616	* @{
jhon309	0:c52df770855b	617	*/
jhon309	0:c52df770855b	618
jhon309	0:c52df770855b	619	#if defined(STM32F070xB) \|\| defined(STM32F070x6) \|\| defined(STM32F030xC)
jhon309	0:c52df770855b	620	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
jhon309	0:c52df770855b	621	#else
jhon309	0:c52df770855b	622	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
jhon309	0:c52df770855b	623	#endif
jhon309	0:c52df770855b	624
jhon309	0:c52df770855b	625	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
jhon309	0:c52df770855b	626	((SOURCE) == RCC_PLLSOURCE_HSE))
jhon309	0:c52df770855b	627	/**
jhon309	0:c52df770855b	628	* @}
jhon309	0:c52df770855b	629	*/
jhon309	0:c52df770855b	630
jhon309	0:c52df770855b	631	/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
jhon309	0:c52df770855b	632	* @{
jhon309	0:c52df770855b	633	*/
jhon309	0:c52df770855b	634	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
jhon309	0:c52df770855b	635	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
jhon309	0:c52df770855b	636	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
jhon309	0:c52df770855b	637
jhon309	0:c52df770855b	638	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
jhon309	0:c52df770855b	639	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
jhon309	0:c52df770855b	640	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
jhon309	0:c52df770855b	641	/**
jhon309	0:c52df770855b	642	* @}
jhon309	0:c52df770855b	643	*/
jhon309	0:c52df770855b	644
jhon309	0:c52df770855b	645	/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
jhon309	0:c52df770855b	646	* @{
jhon309	0:c52df770855b	647	*/
jhon309	0:c52df770855b	648	#define RCC_HSI48_OFF ((uint8_t)0x00)
jhon309	0:c52df770855b	649
jhon309	0:c52df770855b	650	#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF))
jhon309	0:c52df770855b	651	/**
jhon309	0:c52df770855b	652	* @}
jhon309	0:c52df770855b	653	*/
jhon309	0:c52df770855b	654
jhon309	0:c52df770855b	655	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:c52df770855b	656	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:c52df770855b	657	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	658
jhon309	0:c52df770855b	659
jhon309	0:c52df770855b	660	/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
jhon309	0:c52df770855b	661	* @{
jhon309	0:c52df770855b	662	*/
jhon309	0:c52df770855b	663
jhon309	0:c52df770855b	664	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
jhon309	0:c52df770855b	665
jhon309	0:c52df770855b	666	#define RCC_MCO_NODIV ((uint32_t)0x00000000)
jhon309	0:c52df770855b	667
jhon309	0:c52df770855b	668	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV))
jhon309	0:c52df770855b	669
jhon309	0:c52df770855b	670	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
jhon309	0:c52df770855b	671
jhon309	0:c52df770855b	672	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6) \|\| \
jhon309	0:c52df770855b	673	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F071xB) \|\| defined(STM32F070xB) \|\| \
jhon309	0:c52df770855b	674	defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	675	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:c52df770855b	676
jhon309	0:c52df770855b	677	#define RCC_MCO_DIV1 ((uint32_t)0x00000000)
jhon309	0:c52df770855b	678	#define RCC_MCO_DIV2 ((uint32_t)0x10000000)
jhon309	0:c52df770855b	679	#define RCC_MCO_DIV4 ((uint32_t)0x20000000)
jhon309	0:c52df770855b	680	#define RCC_MCO_DIV8 ((uint32_t)0x30000000)
jhon309	0:c52df770855b	681	#define RCC_MCO_DIV16 ((uint32_t)0x40000000)
jhon309	0:c52df770855b	682	#define RCC_MCO_DIV32 ((uint32_t)0x50000000)
jhon309	0:c52df770855b	683	#define RCC_MCO_DIV64 ((uint32_t)0x60000000)
jhon309	0:c52df770855b	684	#define RCC_MCO_DIV128 ((uint32_t)0x70000000)
jhon309	0:c52df770855b	685
jhon309	0:c52df770855b	686	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) \|\| ((DIV) == RCC_MCO_DIV2) \|\| \
jhon309	0:c52df770855b	687	((DIV) == RCC_MCO_DIV4) \|\| ((DIV) == RCC_MCO_DIV8) \|\| \
jhon309	0:c52df770855b	688	((DIV) == RCC_MCO_DIV16) \|\| ((DIV) == RCC_MCO_DIV32) \|\| \
jhon309	0:c52df770855b	689	((DIV) == RCC_MCO_DIV64) \|\| ((DIV) == RCC_MCO_DIV128))
jhon309	0:c52df770855b	690
jhon309	0:c52df770855b	691	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:c52df770855b	692	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070x6 \|\| STM32F070xB */
jhon309	0:c52df770855b	693	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:c52df770855b	694
jhon309	0:c52df770855b	695	/**
jhon309	0:c52df770855b	696	* @}
jhon309	0:c52df770855b	697	*/
jhon309	0:c52df770855b	698
jhon309	0:c52df770855b	699	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:c52df770855b	700	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	701	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	702
jhon309	0:c52df770855b	703	/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
jhon309	0:c52df770855b	704	* @{
jhon309	0:c52df770855b	705	*/
jhon309	0:c52df770855b	706	#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /!< Synchro Signal soucre GPIO /
jhon309	0:c52df770855b	707	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
jhon309	0:c52df770855b	708	#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB SOF (default)/
jhon309	0:c52df770855b	709
jhon309	0:c52df770855b	710	#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) \|\| \
jhon309	0:c52df770855b	711	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) \|\| \
jhon309	0:c52df770855b	712	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
jhon309	0:c52df770855b	713	/**
jhon309	0:c52df770855b	714	* @}
jhon309	0:c52df770855b	715	*/
jhon309	0:c52df770855b	716
jhon309	0:c52df770855b	717	/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
jhon309	0:c52df770855b	718	* @{
jhon309	0:c52df770855b	719	*/
jhon309	0:c52df770855b	720	#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /!< Synchro Signal not divided (default) /
jhon309	0:c52df770855b	721	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
jhon309	0:c52df770855b	722	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
jhon309	0:c52df770855b	723	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
jhon309	0:c52df770855b	724	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
jhon309	0:c52df770855b	725	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
jhon309	0:c52df770855b	726	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
jhon309	0:c52df770855b	727	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
jhon309	0:c52df770855b	728
jhon309	0:c52df770855b	729	#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV2) \|\| \
jhon309	0:c52df770855b	730	((_DIV_) == RCC_CRS_SYNC_DIV4) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV8) \|\| \
jhon309	0:c52df770855b	731	((_DIV_) == RCC_CRS_SYNC_DIV16) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV32) \|\| \
jhon309	0:c52df770855b	732	((_DIV_) == RCC_CRS_SYNC_DIV64) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV128))
jhon309	0:c52df770855b	733	/**
jhon309	0:c52df770855b	734	* @}
jhon309	0:c52df770855b	735	*/
jhon309	0:c52df770855b	736
jhon309	0:c52df770855b	737	/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
jhon309	0:c52df770855b	738	* @{
jhon309	0:c52df770855b	739	*/
jhon309	0:c52df770855b	740	#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /!< Synchro Active on rising edge (default) /
jhon309	0:c52df770855b	741	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
jhon309	0:c52df770855b	742
jhon309	0:c52df770855b	743	#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
jhon309	0:c52df770855b	744	((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
jhon309	0:c52df770855b	745	/**
jhon309	0:c52df770855b	746	* @}
jhon309	0:c52df770855b	747	*/
jhon309	0:c52df770855b	748
jhon309	0:c52df770855b	749	/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
jhon309	0:c52df770855b	750	* @{
jhon309	0:c52df770855b	751	*/
jhon309	0:c52df770855b	752	#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
jhon309	0:c52df770855b	753	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
jhon309	0:c52df770855b	754
jhon309	0:c52df770855b	755	#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
jhon309	0:c52df770855b	756	/**
jhon309	0:c52df770855b	757	* @}
jhon309	0:c52df770855b	758	*/
jhon309	0:c52df770855b	759
jhon309	0:c52df770855b	760	/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
jhon309	0:c52df770855b	761	* @{
jhon309	0:c52df770855b	762	*/
jhon309	0:c52df770855b	763	#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /!< Default Frequency error limit /
jhon309	0:c52df770855b	764
jhon309	0:c52df770855b	765	#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
jhon309	0:c52df770855b	766	/**
jhon309	0:c52df770855b	767	* @}
jhon309	0:c52df770855b	768	*/
jhon309	0:c52df770855b	769
jhon309	0:c52df770855b	770	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
jhon309	0:c52df770855b	771	* @{
jhon309	0:c52df770855b	772	*/
jhon309	0:c52df770855b	773	#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
jhon309	0:c52df770855b	774	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
jhon309	0:c52df770855b	775	corresponds to a higher output frequency */
jhon309	0:c52df770855b	776
jhon309	0:c52df770855b	777	#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
jhon309	0:c52df770855b	778	/**
jhon309	0:c52df770855b	779	* @}
jhon309	0:c52df770855b	780	*/
jhon309	0:c52df770855b	781
jhon309	0:c52df770855b	782	/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
jhon309	0:c52df770855b	783	* @{
jhon309	0:c52df770855b	784	*/
jhon309	0:c52df770855b	785	#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /!< Upcounting direction, the actual frequency is above the target /
jhon309	0:c52df770855b	786	#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /!< Downcounting direction, the actual frequency is below the target /
jhon309	0:c52df770855b	787
jhon309	0:c52df770855b	788	#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) \|\| \
jhon309	0:c52df770855b	789	((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
jhon309	0:c52df770855b	790	/**
jhon309	0:c52df770855b	791	* @}
jhon309	0:c52df770855b	792	*/
jhon309	0:c52df770855b	793
jhon309	0:c52df770855b	794	/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
jhon309	0:c52df770855b	795	* @{
jhon309	0:c52df770855b	796	*/
jhon309	0:c52df770855b	797	#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK /
jhon309	0:c52df770855b	798	#define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning /
jhon309	0:c52df770855b	799	#define RCC_CRS_IT_ERR CRS_ISR_ERRF /!< error /
jhon309	0:c52df770855b	800	#define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC /
jhon309	0:c52df770855b	801	#define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
jhon309	0:c52df770855b	802	#define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
jhon309	0:c52df770855b	803	#define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
jhon309	0:c52df770855b	804
jhon309	0:c52df770855b	805	/**
jhon309	0:c52df770855b	806	* @}
jhon309	0:c52df770855b	807	*/
jhon309	0:c52df770855b	808
jhon309	0:c52df770855b	809	/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
jhon309	0:c52df770855b	810	* @{
jhon309	0:c52df770855b	811	*/
jhon309	0:c52df770855b	812	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
jhon309	0:c52df770855b	813	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
jhon309	0:c52df770855b	814	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
jhon309	0:c52df770855b	815	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
jhon309	0:c52df770855b	816	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
jhon309	0:c52df770855b	817	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
jhon309	0:c52df770855b	818	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
jhon309	0:c52df770855b	819
jhon309	0:c52df770855b	820	/**
jhon309	0:c52df770855b	821	* @}
jhon309	0:c52df770855b	822	*/
jhon309	0:c52df770855b	823
jhon309	0:c52df770855b	824	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:c52df770855b	825	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:c52df770855b	826	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	827
jhon309	0:c52df770855b	828	/**
jhon309	0:c52df770855b	829	* @}
jhon309	0:c52df770855b	830	*/
jhon309	0:c52df770855b	831
jhon309	0:c52df770855b	832	/* Exported macros ------------------------------------------------------------*/
jhon309	0:c52df770855b	833	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
jhon309	0:c52df770855b	834	* @{
jhon309	0:c52df770855b	835	*/
jhon309	0:c52df770855b	836
jhon309	0:c52df770855b	837	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
jhon309	0:c52df770855b	838	* @brief Enables or disables the AHB1 peripheral clock.
jhon309	0:c52df770855b	839	* @note After reset, the peripheral clock (used for registers read/write access)
jhon309	0:c52df770855b	840	* is disabled and the application software has to enable this clock before
jhon309	0:c52df770855b	841	* using it.
jhon309	0:c52df770855b	842	* @{
jhon309	0:c52df770855b	843	*/
jhon309	0:c52df770855b	844	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| \
jhon309	0:c52df770855b	845	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:c52df770855b	846	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	847	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:c52df770855b	848
jhon309	0:c52df770855b	849	#define __GPIOD_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIODEN))
jhon309	0:c52df770855b	850
jhon309	0:c52df770855b	851	#define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
jhon309	0:c52df770855b	852
jhon309	0:c52df770855b	853	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
jhon309	0:c52df770855b	854	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070xB \|\| */
jhon309	0:c52df770855b	855	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:c52df770855b	856	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:c52df770855b	857
jhon309	0:c52df770855b	858	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:c52df770855b	859	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:c52df770855b	860
jhon309	0:c52df770855b	861	#define __GPIOE_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOEEN))
jhon309	0:c52df770855b	862
jhon309	0:c52df770855b	863	#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
jhon309	0:c52df770855b	864
jhon309	0:c52df770855b	865	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:c52df770855b	866	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:c52df770855b	867
jhon309	0:c52df770855b	868	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:c52df770855b	869	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:c52df770855b	870	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	871	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	872
jhon309	0:c52df770855b	873	#define __TSC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_TSCEN))
jhon309	0:c52df770855b	874
jhon309	0:c52df770855b	875	#define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
jhon309	0:c52df770855b	876
jhon309	0:c52df770855b	877	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:c52df770855b	878	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:c52df770855b	879	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:c52df770855b	880	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	881
jhon309	0:c52df770855b	882	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	883
jhon309	0:c52df770855b	884	#define __DMA2_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA2EN))
jhon309	0:c52df770855b	885
jhon309	0:c52df770855b	886	#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
jhon309	0:c52df770855b	887
jhon309	0:c52df770855b	888	#endif /* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	889
jhon309	0:c52df770855b	890	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
jhon309	0:c52df770855b	891	* @note After reset, the peripheral clock (used for registers read/write access)
jhon309	0:c52df770855b	892	* is disabled and the application software has to enable this clock before
jhon309	0:c52df770855b	893	* using it.
jhon309	0:c52df770855b	894	*/
jhon309	0:c52df770855b	895	#if defined(STM32F030x8) \|\| \
jhon309	0:c52df770855b	896	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:c52df770855b	897	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:c52df770855b	898	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:c52df770855b	899	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:c52df770855b	900
jhon309	0:c52df770855b	901	#define __USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
jhon309	0:c52df770855b	902	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
jhon309	0:c52df770855b	903
jhon309	0:c52df770855b	904	#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
jhon309	0:c52df770855b	905	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
jhon309	0:c52df770855b	906
jhon309	0:c52df770855b	907	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:c52df770855b	908	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:c52df770855b	909	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:c52df770855b	910	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:c52df770855b	911
jhon309	0:c52df770855b	912	#if defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
jhon309	0:c52df770855b	913	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:c52df770855b	914	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:c52df770855b	915	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	916	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	917
jhon309	0:c52df770855b	918	#define __TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
jhon309	0:c52df770855b	919
jhon309	0:c52df770855b	920	#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
jhon309	0:c52df770855b	921
jhon309	0:c52df770855b	922	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
jhon309	0:c52df770855b	923	/* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:c52df770855b	924	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:c52df770855b	925	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:c52df770855b	926	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	927
jhon309	0:c52df770855b	928	#if defined(STM32F030x8) \|\| \
jhon309	0:c52df770855b	929	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:c52df770855b	930	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:c52df770855b	931	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:c52df770855b	932
jhon309	0:c52df770855b	933	#define __TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
jhon309	0:c52df770855b	934	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
jhon309	0:c52df770855b	935
jhon309	0:c52df770855b	936	#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
jhon309	0:c52df770855b	937	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
jhon309	0:c52df770855b	938
jhon309	0:c52df770855b	939	#endif /* STM32F030x8 \|\| */
jhon309	0:c52df770855b	940	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:c52df770855b	941	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:c52df770855b	942	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:c52df770855b	943
jhon309	0:c52df770855b	944	#if defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:c52df770855b	945	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	946	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	947
jhon309	0:c52df770855b	948	#define __DAC1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DACEN))
jhon309	0:c52df770855b	949
jhon309	0:c52df770855b	950	#define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
jhon309	0:c52df770855b	951
jhon309	0:c52df770855b	952	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:c52df770855b	953	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:c52df770855b	954	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	955
jhon309	0:c52df770855b	956	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:c52df770855b	957	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:c52df770855b	958	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	959	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	960
jhon309	0:c52df770855b	961	#define __CEC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CECEN))
jhon309	0:c52df770855b	962
jhon309	0:c52df770855b	963	#define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
jhon309	0:c52df770855b	964
jhon309	0:c52df770855b	965	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:c52df770855b	966	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:c52df770855b	967	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:c52df770855b	968	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	969
jhon309	0:c52df770855b	970	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:c52df770855b	971	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:c52df770855b	972
jhon309	0:c52df770855b	973	#define __TIM7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM7EN))
jhon309	0:c52df770855b	974	#define __USART3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART3EN))
jhon309	0:c52df770855b	975	#define __USART4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART4EN))
jhon309	0:c52df770855b	976
jhon309	0:c52df770855b	977	#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
jhon309	0:c52df770855b	978	#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
jhon309	0:c52df770855b	979	#define __USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
jhon309	0:c52df770855b	980
jhon309	0:c52df770855b	981	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:c52df770855b	982	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:c52df770855b	983
jhon309	0:c52df770855b	984	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
jhon309	0:c52df770855b	985	defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
jhon309	0:c52df770855b	986
jhon309	0:c52df770855b	987	#define __USB_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USBEN))
jhon309	0:c52df770855b	988
jhon309	0:c52df770855b	989	#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
jhon309	0:c52df770855b	990
jhon309	0:c52df770855b	991	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
jhon309	0:c52df770855b	992	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
jhon309	0:c52df770855b	993
jhon309	0:c52df770855b	994	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| \
jhon309	0:c52df770855b	995	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	996
jhon309	0:c52df770855b	997	#define __CAN_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CANEN))
jhon309	0:c52df770855b	998	#define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
jhon309	0:c52df770855b	999
jhon309	0:c52df770855b	1000	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
jhon309	0:c52df770855b	1001	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	1002
jhon309	0:c52df770855b	1003	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:c52df770855b	1004	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	1005	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	1006
jhon309	0:c52df770855b	1007	#define __CRS_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CRSEN))
jhon309	0:c52df770855b	1008
jhon309	0:c52df770855b	1009	#define __CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
jhon309	0:c52df770855b	1010
jhon309	0:c52df770855b	1011	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:c52df770855b	1012	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:c52df770855b	1013	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	1014
jhon309	0:c52df770855b	1015	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:c52df770855b	1016
jhon309	0:c52df770855b	1017	#define __USART5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART5EN))
jhon309	0:c52df770855b	1018
jhon309	0:c52df770855b	1019	#define __USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
jhon309	0:c52df770855b	1020
jhon309	0:c52df770855b	1021	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:c52df770855b	1022
jhon309	0:c52df770855b	1023	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
jhon309	0:c52df770855b	1024	* @note After reset, the peripheral clock (used for registers read/write access)
jhon309	0:c52df770855b	1025	* is disabled and the application software has to enable this clock before
jhon309	0:c52df770855b	1026	* using it.
jhon309	0:c52df770855b	1027	*/
jhon309	0:c52df770855b	1028	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
jhon309	0:c52df770855b	1029	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:c52df770855b	1030	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:c52df770855b	1031	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:c52df770855b	1032
jhon309	0:c52df770855b	1033	#define __TIM15_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM15EN))
jhon309	0:c52df770855b	1034
jhon309	0:c52df770855b	1035	#define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
jhon309	0:c52df770855b	1036
jhon309	0:c52df770855b	1037	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
jhon309	0:c52df770855b	1038	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:c52df770855b	1039	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:c52df770855b	1040	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:c52df770855b	1041
jhon309	0:c52df770855b	1042	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:c52df770855b	1043
jhon309	0:c52df770855b	1044	#define __USART6_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART6EN))
jhon309	0:c52df770855b	1045
jhon309	0:c52df770855b	1046	#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
jhon309	0:c52df770855b	1047
jhon309	0:c52df770855b	1048	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:c52df770855b	1049
jhon309	0:c52df770855b	1050	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	1051
jhon309	0:c52df770855b	1052	#define __USART7_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART7EN))
jhon309	0:c52df770855b	1053	#define __USART8_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART8EN))
jhon309	0:c52df770855b	1054
jhon309	0:c52df770855b	1055	#define __USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
jhon309	0:c52df770855b	1056	#define __USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
jhon309	0:c52df770855b	1057
jhon309	0:c52df770855b	1058	#endif /* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	1059
jhon309	0:c52df770855b	1060	/**
jhon309	0:c52df770855b	1061	* @}
jhon309	0:c52df770855b	1062	*/
jhon309	0:c52df770855b	1063
jhon309	0:c52df770855b	1064
jhon309	0:c52df770855b	1065	/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
jhon309	0:c52df770855b	1066	* @brief Forces or releases peripheral reset.
jhon309	0:c52df770855b	1067	* @{
jhon309	0:c52df770855b	1068	*/
jhon309	0:c52df770855b	1069
jhon309	0:c52df770855b	1070	/** @brief Force or release AHB peripheral reset.
jhon309	0:c52df770855b	1071	*/
jhon309	0:c52df770855b	1072	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| \
jhon309	0:c52df770855b	1073	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:c52df770855b	1074	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:c52df770855b	1075	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:c52df770855b	1076
jhon309	0:c52df770855b	1077	#define __GPIOD_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIODRST))
jhon309	0:c52df770855b	1078
jhon309	0:c52df770855b	1079	#define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
jhon309	0:c52df770855b	1080
jhon309	0:c52df770855b	1081	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
jhon309	0:c52df770855b	1082	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:c52df770855b	1083	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:c52df770855b	1084	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:c52df770855b	1085
jhon309	0:c52df770855b	1086	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:c52df770855b	1087	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:c52df770855b	1088
jhon309	0:c52df770855b	1089	#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
jhon309	0:c52df770855b	1090
jhon309	0:c52df770855b	1091	#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
jhon309	0:c52df770855b	1092
jhon309	0:c52df770855b	1093	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:c52df770855b	1094	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:c52df770855b	1095
jhon309	0:c52df770855b	1096	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:c52df770855b	1097	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:c52df770855b	1098	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	1099	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	1100
jhon309	0:c52df770855b	1101	#define __TSC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_TSCRST))
jhon309	0:c52df770855b	1102
jhon309	0:c52df770855b	1103	#define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
jhon309	0:c52df770855b	1104
jhon309	0:c52df770855b	1105	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:c52df770855b	1106	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:c52df770855b	1107	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:c52df770855b	1108	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	1109
jhon309	0:c52df770855b	1110	/** @brief Force or release APB1 peripheral reset.
jhon309	0:c52df770855b	1111	*/
jhon309	0:c52df770855b	1112	#if defined(STM32F030x8) \|\| \
jhon309	0:c52df770855b	1113	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
jhon309	0:c52df770855b	1114	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:c52df770855b	1115	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:c52df770855b	1116	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:c52df770855b	1117
jhon309	0:c52df770855b	1118	#define __USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
jhon309	0:c52df770855b	1119	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
jhon309	0:c52df770855b	1120
jhon309	0:c52df770855b	1121	#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
jhon309	0:c52df770855b	1122	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
jhon309	0:c52df770855b	1123
jhon309	0:c52df770855b	1124	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
jhon309	0:c52df770855b	1125	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:c52df770855b	1126	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:c52df770855b	1127	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:c52df770855b	1128
jhon309	0:c52df770855b	1129	#if defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
jhon309	0:c52df770855b	1130	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:c52df770855b	1131	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:c52df770855b	1132	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	1133	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	1134
jhon309	0:c52df770855b	1135	#define __TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
jhon309	0:c52df770855b	1136
jhon309	0:c52df770855b	1137	#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
jhon309	0:c52df770855b	1138
jhon309	0:c52df770855b	1139	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
jhon309	0:c52df770855b	1140	/* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:c52df770855b	1141	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:c52df770855b	1142	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:c52df770855b	1143	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	1144
jhon309	0:c52df770855b	1145	#if defined(STM32F030x8) \|\| \
jhon309	0:c52df770855b	1146	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:c52df770855b	1147	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\|\
jhon309	0:c52df770855b	1148	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:c52df770855b	1149
jhon309	0:c52df770855b	1150	#define __TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
jhon309	0:c52df770855b	1151	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
jhon309	0:c52df770855b	1152
jhon309	0:c52df770855b	1153	#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
jhon309	0:c52df770855b	1154	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
jhon309	0:c52df770855b	1155
jhon309	0:c52df770855b	1156	#endif /* STM32F030x8 \|\| */
jhon309	0:c52df770855b	1157	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:c52df770855b	1158	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:c52df770855b	1159	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:c52df770855b	1160
jhon309	0:c52df770855b	1161	#if defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:c52df770855b	1162	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	1163	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	1164
jhon309	0:c52df770855b	1165	#define __DAC1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
jhon309	0:c52df770855b	1166
jhon309	0:c52df770855b	1167	#define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
jhon309	0:c52df770855b	1168
jhon309	0:c52df770855b	1169	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:c52df770855b	1170	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:c52df770855b	1171	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	1172
jhon309	0:c52df770855b	1173	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:c52df770855b	1174	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:c52df770855b	1175	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	1176	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	1177
jhon309	0:c52df770855b	1178	#define __CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
jhon309	0:c52df770855b	1179
jhon309	0:c52df770855b	1180	#define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
jhon309	0:c52df770855b	1181
jhon309	0:c52df770855b	1182	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:c52df770855b	1183	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:c52df770855b	1184	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:c52df770855b	1185	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	1186
jhon309	0:c52df770855b	1187	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:c52df770855b	1188	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:c52df770855b	1189
jhon309	0:c52df770855b	1190	#define __TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
jhon309	0:c52df770855b	1191	#define __USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
jhon309	0:c52df770855b	1192	#define __USART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART4RST))
jhon309	0:c52df770855b	1193
jhon309	0:c52df770855b	1194	#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
jhon309	0:c52df770855b	1195	#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
jhon309	0:c52df770855b	1196	#define __USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
jhon309	0:c52df770855b	1197
jhon309	0:c52df770855b	1198	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:c52df770855b	1199	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:c52df770855b	1200
jhon309	0:c52df770855b	1201	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
jhon309	0:c52df770855b	1202	defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
jhon309	0:c52df770855b	1203
jhon309	0:c52df770855b	1204	#define __USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
jhon309	0:c52df770855b	1205
jhon309	0:c52df770855b	1206	#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
jhon309	0:c52df770855b	1207
jhon309	0:c52df770855b	1208	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
jhon309	0:c52df770855b	1209	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
jhon309	0:c52df770855b	1210
jhon309	0:c52df770855b	1211	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| \
jhon309	0:c52df770855b	1212	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	1213
jhon309	0:c52df770855b	1214	#define __CAN_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CANRST))
jhon309	0:c52df770855b	1215
jhon309	0:c52df770855b	1216	#define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
jhon309	0:c52df770855b	1217
jhon309	0:c52df770855b	1218	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
jhon309	0:c52df770855b	1219	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	1220
jhon309	0:c52df770855b	1221	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:c52df770855b	1222	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	1223	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	1224
jhon309	0:c52df770855b	1225	#define __CRS_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CRSRST))
jhon309	0:c52df770855b	1226
jhon309	0:c52df770855b	1227	#define __CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
jhon309	0:c52df770855b	1228
jhon309	0:c52df770855b	1229	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:c52df770855b	1230	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:c52df770855b	1231	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	1232
jhon309	0:c52df770855b	1233	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:c52df770855b	1234
jhon309	0:c52df770855b	1235	#define __USART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART5RST))
jhon309	0:c52df770855b	1236
jhon309	0:c52df770855b	1237	#define __USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
jhon309	0:c52df770855b	1238
jhon309	0:c52df770855b	1239	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:c52df770855b	1240
jhon309	0:c52df770855b	1241
jhon309	0:c52df770855b	1242	/** @brief Force or release APB2 peripheral reset.
jhon309	0:c52df770855b	1243	*/
jhon309	0:c52df770855b	1244	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
jhon309	0:c52df770855b	1245	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:c52df770855b	1246	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:c52df770855b	1247	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:c52df770855b	1248
jhon309	0:c52df770855b	1249	#define __TIM15_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM15RST))
jhon309	0:c52df770855b	1250
jhon309	0:c52df770855b	1251	#define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
jhon309	0:c52df770855b	1252
jhon309	0:c52df770855b	1253	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
jhon309	0:c52df770855b	1254	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:c52df770855b	1255	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:c52df770855b	1256	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:c52df770855b	1257
jhon309	0:c52df770855b	1258	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:c52df770855b	1259
jhon309	0:c52df770855b	1260	#define __USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
jhon309	0:c52df770855b	1261
jhon309	0:c52df770855b	1262	#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
jhon309	0:c52df770855b	1263
jhon309	0:c52df770855b	1264	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:c52df770855b	1265
jhon309	0:c52df770855b	1266	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	1267
jhon309	0:c52df770855b	1268	#define __USART7_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART7RST))
jhon309	0:c52df770855b	1269	#define __USART8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART8RST))
jhon309	0:c52df770855b	1270
jhon309	0:c52df770855b	1271	#define __USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
jhon309	0:c52df770855b	1272	#define __USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
jhon309	0:c52df770855b	1273
jhon309	0:c52df770855b	1274	#endif /* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	1275
jhon309	0:c52df770855b	1276	/**
jhon309	0:c52df770855b	1277	* @}
jhon309	0:c52df770855b	1278	*/
jhon309	0:c52df770855b	1279
jhon309	0:c52df770855b	1280	/** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable
jhon309	0:c52df770855b	1281	* @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
jhon309	0:c52df770855b	1282	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
jhon309	0:c52df770855b	1283	* @note HSI48 can not be stopped if it is used as system clock source. In this case,
jhon309	0:c52df770855b	1284	* you have to select another source of the system clock then stop the HSI14.
jhon309	0:c52df770855b	1285	* @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software
jhon309	0:c52df770855b	1286	* should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be
jhon309	0:c52df770855b	1287	* used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
jhon309	0:c52df770855b	1288	* @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator
jhon309	0:c52df770855b	1289	* clock cycles.
jhon309	0:c52df770855b	1290	* @{
jhon309	0:c52df770855b	1291	*/
jhon309	0:c52df770855b	1292	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:c52df770855b	1293	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	1294	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	1295
jhon309	0:c52df770855b	1296	#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
jhon309	0:c52df770855b	1297	#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
jhon309	0:c52df770855b	1298
jhon309	0:c52df770855b	1299	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
jhon309	0:c52df770855b	1300	* @retval The clock source can be one of the following values:
jhon309	0:c52df770855b	1301	* @arg RCC_HSI48_ON: HSI48 enabled
jhon309	0:c52df770855b	1302	* @arg RCC_HSI48_OFF: HSI48 disabled
jhon309	0:c52df770855b	1303	*/
jhon309	0:c52df770855b	1304	#define __HAL_RCC_GET_HSI48_STATE() \
jhon309	0:c52df770855b	1305	(((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
jhon309	0:c52df770855b	1306
jhon309	0:c52df770855b	1307	#else
jhon309	0:c52df770855b	1308
jhon309	0:c52df770855b	1309	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
jhon309	0:c52df770855b	1310	* @retval The clock source can be one of the following values:
jhon309	0:c52df770855b	1311	* @arg RCC_HSI_OFF: HSI48 disabled
jhon309	0:c52df770855b	1312	*/
jhon309	0:c52df770855b	1313	#define __HAL_RCC_GET_HSI48_STATE() RCC_HSI_OFF
jhon309	0:c52df770855b	1314
jhon309	0:c52df770855b	1315	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:c52df770855b	1316	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:c52df770855b	1317	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	1318
jhon309	0:c52df770855b	1319	/**
jhon309	0:c52df770855b	1320	* @}
jhon309	0:c52df770855b	1321	*/
jhon309	0:c52df770855b	1322
jhon309	0:c52df770855b	1323	/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
jhon309	0:c52df770855b	1324	* @{
jhon309	0:c52df770855b	1325	*/
jhon309	0:c52df770855b	1326	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:c52df770855b	1327	defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	1328	defined(STM32F070x6) \|\| defined(STM32F070xB)
jhon309	0:c52df770855b	1329
jhon309	0:c52df770855b	1330	/** @brief Macro to configure the USB clock (USBCLK).
jhon309	0:c52df770855b	1331	* @param __USBCLKSource__: specifies the USB clock source.
jhon309	0:c52df770855b	1332	* This parameter can be one of the following values:
jhon309	0:c52df770855b	1333	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
jhon309	0:c52df770855b	1334	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
jhon309	0:c52df770855b	1335	*/
jhon309	0:c52df770855b	1336	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
jhon309	0:c52df770855b	1337	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSource__))
jhon309	0:c52df770855b	1338
jhon309	0:c52df770855b	1339	/** @brief Macro to get the USB clock source.
jhon309	0:c52df770855b	1340	* @retval The clock source can be one of the following values:
jhon309	0:c52df770855b	1341	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
jhon309	0:c52df770855b	1342	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
jhon309	0:c52df770855b	1343	*/
jhon309	0:c52df770855b	1344	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
jhon309	0:c52df770855b	1345
jhon309	0:c52df770855b	1346	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:c52df770855b	1347	/* STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:c52df770855b	1348	/* STM32F070x6 \|\| STM32F070xB */
jhon309	0:c52df770855b	1349
jhon309	0:c52df770855b	1350	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:c52df770855b	1351	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
jhon309	0:c52df770855b	1352	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	1353	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	1354
jhon309	0:c52df770855b	1355	/** @brief Macro to configure the CEC clock.
jhon309	0:c52df770855b	1356	* @param __CECCLKSource__: specifies the CEC clock source.
jhon309	0:c52df770855b	1357	* This parameter can be one of the following values:
jhon309	0:c52df770855b	1358	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
jhon309	0:c52df770855b	1359	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
jhon309	0:c52df770855b	1360	*/
jhon309	0:c52df770855b	1361	#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
jhon309	0:c52df770855b	1362	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
jhon309	0:c52df770855b	1363
jhon309	0:c52df770855b	1364	/** @brief Macro to get the HDMI CEC clock source.
jhon309	0:c52df770855b	1365	* @retval The clock source can be one of the following values:
jhon309	0:c52df770855b	1366	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
jhon309	0:c52df770855b	1367	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
jhon309	0:c52df770855b	1368	*/
jhon309	0:c52df770855b	1369	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
jhon309	0:c52df770855b	1370
jhon309	0:c52df770855b	1371	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:c52df770855b	1372	/* STM32F051x8 \|\| STM32F058xx \|\| */
jhon309	0:c52df770855b	1373	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:c52df770855b	1374	/* STM32F091xC \|\| defined(STM32F098xx) */
jhon309	0:c52df770855b	1375
jhon309	0:c52df770855b	1376	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
jhon309	0:c52df770855b	1377	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
jhon309	0:c52df770855b	1378	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
jhon309	0:c52df770855b	1379	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:c52df770855b	1380
jhon309	0:c52df770855b	1381	/** @brief Macro to configure the MCO clock.
jhon309	0:c52df770855b	1382	* @param __MCOCLKSource__: specifies the MCO clock source.
jhon309	0:c52df770855b	1383	* This parameter can be one of the following values:
jhon309	0:c52df770855b	1384	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
jhon309	0:c52df770855b	1385	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
jhon309	0:c52df770855b	1386	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
jhon309	0:c52df770855b	1387	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
jhon309	0:c52df770855b	1388	* @arg RCC_MCOSOURCE_PLLCLK_NODIV: PLLCLK selected as MCO clock
jhon309	0:c52df770855b	1389	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
jhon309	0:c52df770855b	1390	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
jhon309	0:c52df770855b	1391	* @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
jhon309	0:c52df770855b	1392	* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
jhon309	0:c52df770855b	1393	* @param __MCODiv__: specifies the MCO clock prescaler.
jhon309	0:c52df770855b	1394	* This parameter can be one of the following values:
jhon309	0:c52df770855b	1395	* @arg RCC_MCO_DIV1: MCO clock source is divided by 1
jhon309	0:c52df770855b	1396	* @arg RCC_MCO_DIV2: MCO clock source is divided by 2
jhon309	0:c52df770855b	1397	* @arg RCC_MCO_DIV4: MCO clock source is divided by 4
jhon309	0:c52df770855b	1398	* @arg RCC_MCO_DIV8: MCO clock source is divided by 8
jhon309	0:c52df770855b	1399	* @arg RCC_MCO_DIV16: MCO clock source is divided by 16
jhon309	0:c52df770855b	1400	* @arg RCC_MCO_DIV32: MCO clock source is divided by 32
jhon309	0:c52df770855b	1401	* @arg RCC_MCO_DIV64: MCO clock source is divided by 64
jhon309	0:c52df770855b	1402	* @arg RCC_MCO_DIV128: MCO clock source is divided by 128
jhon309	0:c52df770855b	1403	*/
jhon309	0:c52df770855b	1404	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
jhon309	0:c52df770855b	1405	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO \| RCC_CFGR_MCOPRE), ((__MCOCLKSource__) \| (__MCODiv__)))
jhon309	0:c52df770855b	1406	#else
jhon309	0:c52df770855b	1407
jhon309	0:c52df770855b	1408	/** @brief Macro to configure the MCO clock.
jhon309	0:c52df770855b	1409	* @param __MCOCLKSource__: specifies the MCO clock source.
jhon309	0:c52df770855b	1410	* This parameter can be one of the following values:
jhon309	0:c52df770855b	1411	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
jhon309	0:c52df770855b	1412	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
jhon309	0:c52df770855b	1413	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
jhon309	0:c52df770855b	1414	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
jhon309	0:c52df770855b	1415	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
jhon309	0:c52df770855b	1416	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
jhon309	0:c52df770855b	1417	* @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
jhon309	0:c52df770855b	1418	* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
jhon309	0:c52df770855b	1419	* @param __MCODiv__: specifies the MCO clock prescaler.
jhon309	0:c52df770855b	1420	* This parameter can be one of the following values:
jhon309	0:c52df770855b	1421	* @arg RCC_MCO_NODIV: No division applied on MCO clock source
jhon309	0:c52df770855b	1422	*/
jhon309	0:c52df770855b	1423	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
jhon309	0:c52df770855b	1424	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, __MCOCLKSource__)
jhon309	0:c52df770855b	1425
jhon309	0:c52df770855b	1426	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F070x6 \|\| */
jhon309	0:c52df770855b	1427	/* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:c52df770855b	1428	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
jhon309	0:c52df770855b	1429	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:c52df770855b	1430
jhon309	0:c52df770855b	1431	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	1432	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	1433	/** @brief Macro to configure the USART2 clock (USART2CLK).
jhon309	0:c52df770855b	1434	* @param __USART2CLKSource__: specifies the USART2 clock source.
jhon309	0:c52df770855b	1435	* This parameter can be one of the following values:
jhon309	0:c52df770855b	1436	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
jhon309	0:c52df770855b	1437	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
jhon309	0:c52df770855b	1438	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
jhon309	0:c52df770855b	1439	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
jhon309	0:c52df770855b	1440	*/
jhon309	0:c52df770855b	1441	#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
jhon309	0:c52df770855b	1442	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__))
jhon309	0:c52df770855b	1443
jhon309	0:c52df770855b	1444	/** @brief Macro to get the USART2 clock source.
jhon309	0:c52df770855b	1445	* @retval The clock source can be one of the following values:
jhon309	0:c52df770855b	1446	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
jhon309	0:c52df770855b	1447	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
jhon309	0:c52df770855b	1448	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
jhon309	0:c52df770855b	1449	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
jhon309	0:c52df770855b	1450	*/
jhon309	0:c52df770855b	1451	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
jhon309	0:c52df770855b	1452	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F091xC \|\| STM32F098xx*/
jhon309	0:c52df770855b	1453
jhon309	0:c52df770855b	1454	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	1455	/** @brief Macro to configure the USART3 clock (USART3CLK).
jhon309	0:c52df770855b	1456	* @param __USART3CLKSource__: specifies the USART3 clock source.
jhon309	0:c52df770855b	1457	* This parameter can be one of the following values:
jhon309	0:c52df770855b	1458	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
jhon309	0:c52df770855b	1459	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
jhon309	0:c52df770855b	1460	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
jhon309	0:c52df770855b	1461	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
jhon309	0:c52df770855b	1462	*/
jhon309	0:c52df770855b	1463	#define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
jhon309	0:c52df770855b	1464	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__))
jhon309	0:c52df770855b	1465
jhon309	0:c52df770855b	1466	/** @brief Macro to get the USART3 clock source.
jhon309	0:c52df770855b	1467	* @retval The clock source can be one of the following values:
jhon309	0:c52df770855b	1468	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
jhon309	0:c52df770855b	1469	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
jhon309	0:c52df770855b	1470	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
jhon309	0:c52df770855b	1471	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
jhon309	0:c52df770855b	1472	*/
jhon309	0:c52df770855b	1473	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
jhon309	0:c52df770855b	1474
jhon309	0:c52df770855b	1475	#endif /* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	1476	/**
jhon309	0:c52df770855b	1477	* @}
jhon309	0:c52df770855b	1478	*/
jhon309	0:c52df770855b	1479
jhon309	0:c52df770855b	1480	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:c52df770855b	1481	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	1482	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	1483
jhon309	0:c52df770855b	1484	/** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag
jhon309	0:c52df770855b	1485	* @{
jhon309	0:c52df770855b	1486	*/
jhon309	0:c52df770855b	1487	/* Interrupt & Flag management */
jhon309	0:c52df770855b	1488
jhon309	0:c52df770855b	1489	/**
jhon309	0:c52df770855b	1490	* @brief Enables the specified CRS interrupts.
jhon309	0:c52df770855b	1491	* @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
jhon309	0:c52df770855b	1492	* This parameter can be any combination of the following values:
jhon309	0:c52df770855b	1493	* @arg RCC_CRS_IT_SYNCOK
jhon309	0:c52df770855b	1494	* @arg RCC_CRS_IT_SYNCWARN
jhon309	0:c52df770855b	1495	* @arg RCC_CRS_IT_ERR
jhon309	0:c52df770855b	1496	* @arg RCC_CRS_IT_ESYNC
jhon309	0:c52df770855b	1497	* @retval None
jhon309	0:c52df770855b	1498	*/
jhon309	0:c52df770855b	1499	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR \|= (__INTERRUPT__))
jhon309	0:c52df770855b	1500
jhon309	0:c52df770855b	1501	/**
jhon309	0:c52df770855b	1502	* @brief Disables the specified CRS interrupts.
jhon309	0:c52df770855b	1503	* @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
jhon309	0:c52df770855b	1504	* This parameter can be any combination of the following values:
jhon309	0:c52df770855b	1505	* @arg RCC_CRS_IT_SYNCOK
jhon309	0:c52df770855b	1506	* @arg RCC_CRS_IT_SYNCWARN
jhon309	0:c52df770855b	1507	* @arg RCC_CRS_IT_ERR
jhon309	0:c52df770855b	1508	* @arg RCC_CRS_IT_ESYNC
jhon309	0:c52df770855b	1509	* @retval None
jhon309	0:c52df770855b	1510	*/
jhon309	0:c52df770855b	1511	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
jhon309	0:c52df770855b	1512
jhon309	0:c52df770855b	1513	/** @brief Check the CRS's interrupt has occurred or not.
jhon309	0:c52df770855b	1514	* @param __INTERRUPT__: specifies the CRS interrupt source to check.
jhon309	0:c52df770855b	1515	* This parameter can be one of the following values:
jhon309	0:c52df770855b	1516	* @arg RCC_CRS_IT_SYNCOK
jhon309	0:c52df770855b	1517	* @arg RCC_CRS_IT_SYNCWARN
jhon309	0:c52df770855b	1518	* @arg RCC_CRS_IT_ERR
jhon309	0:c52df770855b	1519	* @arg RCC_CRS_IT_ESYNC
jhon309	0:c52df770855b	1520	* @retval The new state of __INTERRUPT__ (SET or RESET).
jhon309	0:c52df770855b	1521	*/
jhon309	0:c52df770855b	1522	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
jhon309	0:c52df770855b	1523
jhon309	0:c52df770855b	1524	/** @brief Clear the CRS's interrupt pending bits
jhon309	0:c52df770855b	1525	* bits to clear the selected interrupt pending bits.
jhon309	0:c52df770855b	1526	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
jhon309	0:c52df770855b	1527	* This parameter can be any combination of the following values:
jhon309	0:c52df770855b	1528	* @arg RCC_CRS_IT_SYNCOK
jhon309	0:c52df770855b	1529	* @arg RCC_CRS_IT_SYNCWARN
jhon309	0:c52df770855b	1530	* @arg RCC_CRS_IT_ERR
jhon309	0:c52df770855b	1531	* @arg RCC_CRS_IT_ESYNC
jhon309	0:c52df770855b	1532	* @arg RCC_CRS_IT_TRIMOVF
jhon309	0:c52df770855b	1533	* @arg RCC_CRS_IT_SYNCERR
jhon309	0:c52df770855b	1534	* @arg RCC_CRS_IT_SYNCMISS
jhon309	0:c52df770855b	1535	*/
jhon309	0:c52df770855b	1536	/* CRS IT Error Mask */
jhon309	0:c52df770855b	1537	#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
jhon309	0:c52df770855b	1538
jhon309	0:c52df770855b	1539	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
jhon309	0:c52df770855b	1540	(CRS->ICR \|= (__INTERRUPT__)))
jhon309	0:c52df770855b	1541
jhon309	0:c52df770855b	1542	/**
jhon309	0:c52df770855b	1543	* @brief Checks whether the specified CRS flag is set or not.
jhon309	0:c52df770855b	1544	* @param _FLAG_: specifies the flag to check.
jhon309	0:c52df770855b	1545	* This parameter can be one of the following values:
jhon309	0:c52df770855b	1546	* @arg RCC_CRS_FLAG_SYNCOK
jhon309	0:c52df770855b	1547	* @arg RCC_CRS_FLAG_SYNCWARN
jhon309	0:c52df770855b	1548	* @arg RCC_CRS_FLAG_ERR
jhon309	0:c52df770855b	1549	* @arg RCC_CRS_FLAG_ESYNC
jhon309	0:c52df770855b	1550	* @arg RCC_CRS_FLAG_TRIMOVF
jhon309	0:c52df770855b	1551	* @arg RCC_CRS_FLAG_SYNCERR
jhon309	0:c52df770855b	1552	* @arg RCC_CRS_FLAG_SYNCMISS
jhon309	0:c52df770855b	1553	* @retval The new state of _FLAG_ (TRUE or FALSE).
jhon309	0:c52df770855b	1554	*/
jhon309	0:c52df770855b	1555	#define __HAL_RCC_CRS_GET_FLAG(_FLAG_) ((CRS->ISR & (_FLAG_)) == (_FLAG_))
jhon309	0:c52df770855b	1556
jhon309	0:c52df770855b	1557	/**
jhon309	0:c52df770855b	1558	* @brief Clears the CRS specified FLAG.
jhon309	0:c52df770855b	1559	* @param _FLAG_: specifies the flag to clear.
jhon309	0:c52df770855b	1560	* This parameter can be one of the following values:
jhon309	0:c52df770855b	1561	* @arg RCC_CRS_FLAG_SYNCOK
jhon309	0:c52df770855b	1562	* @arg RCC_CRS_FLAG_SYNCWARN
jhon309	0:c52df770855b	1563	* @arg RCC_CRS_FLAG_ERR
jhon309	0:c52df770855b	1564	* @arg RCC_CRS_FLAG_ESYNC
jhon309	0:c52df770855b	1565	* @arg RCC_CRS_FLAG_TRIMOVF
jhon309	0:c52df770855b	1566	* @arg RCC_CRS_FLAG_SYNCERR
jhon309	0:c52df770855b	1567	* @arg RCC_CRS_FLAG_SYNCMISS
jhon309	0:c52df770855b	1568	* @retval None
jhon309	0:c52df770855b	1569	*/
jhon309	0:c52df770855b	1570
jhon309	0:c52df770855b	1571	/* CRS Flag Error Mask */
jhon309	0:c52df770855b	1572	#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
jhon309	0:c52df770855b	1573
jhon309	0:c52df770855b	1574	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
jhon309	0:c52df770855b	1575	(CRS->ICR \|= (__FLAG__)))
jhon309	0:c52df770855b	1576
jhon309	0:c52df770855b	1577	/**
jhon309	0:c52df770855b	1578	* @}
jhon309	0:c52df770855b	1579	*/
jhon309	0:c52df770855b	1580
jhon309	0:c52df770855b	1581	/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
jhon309	0:c52df770855b	1582	* @{
jhon309	0:c52df770855b	1583	*/
jhon309	0:c52df770855b	1584	/**
jhon309	0:c52df770855b	1585	* @brief Enables the oscillator clock for frequency error counter.
jhon309	0:c52df770855b	1586	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
jhon309	0:c52df770855b	1587	* @retval None
jhon309	0:c52df770855b	1588	*/
jhon309	0:c52df770855b	1589	#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR \|= CRS_CR_CEN)
jhon309	0:c52df770855b	1590
jhon309	0:c52df770855b	1591	/**
jhon309	0:c52df770855b	1592	* @brief Disables the oscillator clock for frequency error counter.
jhon309	0:c52df770855b	1593	* @retval None
jhon309	0:c52df770855b	1594	*/
jhon309	0:c52df770855b	1595	#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
jhon309	0:c52df770855b	1596
jhon309	0:c52df770855b	1597	/**
jhon309	0:c52df770855b	1598	* @brief Enables the automatic hardware adjustement of TRIM bits.
jhon309	0:c52df770855b	1599	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
jhon309	0:c52df770855b	1600	* @retval None
jhon309	0:c52df770855b	1601	*/
jhon309	0:c52df770855b	1602	#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR \|= CRS_CR_AUTOTRIMEN)
jhon309	0:c52df770855b	1603
jhon309	0:c52df770855b	1604	/**
jhon309	0:c52df770855b	1605	* @brief Enables or disables the automatic hardware adjustement of TRIM bits.
jhon309	0:c52df770855b	1606	* @retval None
jhon309	0:c52df770855b	1607	*/
jhon309	0:c52df770855b	1608	#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
jhon309	0:c52df770855b	1609
jhon309	0:c52df770855b	1610	/**
jhon309	0:c52df770855b	1611	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
jhon309	0:c52df770855b	1612	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
jhon309	0:c52df770855b	1613	* of the synchronization source after prescaling. It is then decreased by one in order to
jhon309	0:c52df770855b	1614	* reach the expected synchronization on the zero value. The formula is the following:
jhon309	0:c52df770855b	1615	* RELOAD = (fTARGET / fSYNC) -1
jhon309	0:c52df770855b	1616	* @param _FTARGET_ Target frequency (value in Hz)
jhon309	0:c52df770855b	1617	* @param _FSYNC_ Synchronization signal frequency (value in Hz)
jhon309	0:c52df770855b	1618	* @retval None
jhon309	0:c52df770855b	1619	*/
jhon309	0:c52df770855b	1620	#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1)
jhon309	0:c52df770855b	1621
jhon309	0:c52df770855b	1622	/**
jhon309	0:c52df770855b	1623	* @}
jhon309	0:c52df770855b	1624	*/
jhon309	0:c52df770855b	1625
jhon309	0:c52df770855b	1626	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:c52df770855b	1627	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:c52df770855b	1628	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	1629
jhon309	0:c52df770855b	1630	/**
jhon309	0:c52df770855b	1631	* @}
jhon309	0:c52df770855b	1632	*/
jhon309	0:c52df770855b	1633
jhon309	0:c52df770855b	1634	/* Exported functions --------------------------------------------------------*/
jhon309	0:c52df770855b	1635	/** @addtogroup RCCEx_Exported_Functions
jhon309	0:c52df770855b	1636	* @{
jhon309	0:c52df770855b	1637	*/
jhon309	0:c52df770855b	1638
jhon309	0:c52df770855b	1639	/** @addtogroup RCCEx_Exported_Functions_Group1
jhon309	0:c52df770855b	1640	* @{
jhon309	0:c52df770855b	1641	*/
jhon309	0:c52df770855b	1642
jhon309	0:c52df770855b	1643	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
jhon309	0:c52df770855b	1644	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
jhon309	0:c52df770855b	1645
jhon309	0:c52df770855b	1646	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
jhon309	0:c52df770855b	1647	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
jhon309	0:c52df770855b	1648	defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	1649	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
jhon309	0:c52df770855b	1650	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
jhon309	0:c52df770855b	1651	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
jhon309	0:c52df770855b	1652	uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
jhon309	0:c52df770855b	1653	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
jhon309	0:c52df770855b	1654	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
jhon309	0:c52df770855b	1655	/* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	1656
jhon309	0:c52df770855b	1657
jhon309	0:c52df770855b	1658	/**
jhon309	0:c52df770855b	1659	* @}
jhon309	0:c52df770855b	1660	*/
jhon309	0:c52df770855b	1661
jhon309	0:c52df770855b	1662	/**
jhon309	0:c52df770855b	1663	* @}
jhon309	0:c52df770855b	1664	*/
jhon309	0:c52df770855b	1665
jhon309	0:c52df770855b	1666	/**
jhon309	0:c52df770855b	1667	* @}
jhon309	0:c52df770855b	1668	*/
jhon309	0:c52df770855b	1669
jhon309	0:c52df770855b	1670	/**
jhon309	0:c52df770855b	1671	* @}
jhon309	0:c52df770855b	1672	*/
jhon309	0:c52df770855b	1673
jhon309	0:c52df770855b	1674	#ifdef __cplusplus
jhon309	0:c52df770855b	1675	}
jhon309	0:c52df770855b	1676	#endif
jhon309	0:c52df770855b	1677
jhon309	0:c52df770855b	1678	#endif /* __STM32F0xx_HAL_RCC_EX_H */
jhon309	0:c52df770855b	1679
jhon309	0:c52df770855b	1680	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	13 Aug 2015
Imports:	191
Forks:	0
Commits:	1
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TARGET_NUCLEO_F072RB/stm32f0xx_hal_rcc_ex.h@0:c52df770855b, 2015-08-13 (annotated)

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