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TARGET_NUCLEO_F072RB/stm32f0xx_hal_dma_ex.h@0:c52df770855b, 2015-08-13 (annotated)

Committer:: jhon309
Date:: Thu Aug 13 00:21:57 2015 +0000
Revision:: 0:c52df770855b

DHT11

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User	Revision	Line number	New contents of line
jhon309	0:c52df770855b	1	/**
jhon309	0:c52df770855b	2	******************************************************************************
jhon309	0:c52df770855b	3	* @file stm32f0xx_hal_dma_ex.h
jhon309	0:c52df770855b	4	* @author MCD Application Team
jhon309	0:c52df770855b	5	* @version V1.2.0
jhon309	0:c52df770855b	6	* @date 11-December-2014
jhon309	0:c52df770855b	7	* @brief Header file of DMA HAL Extension module.
jhon309	0:c52df770855b	8	******************************************************************************
jhon309	0:c52df770855b	9	* @attention
jhon309	0:c52df770855b	10	*
jhon309	0:c52df770855b	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
jhon309	0:c52df770855b	12	*
jhon309	0:c52df770855b	13	* Redistribution and use in source and binary forms, with or without modification,
jhon309	0:c52df770855b	14	* are permitted provided that the following conditions are met:
jhon309	0:c52df770855b	15	* 1. Redistributions of source code must retain the above copyright notice,
jhon309	0:c52df770855b	16	* this list of conditions and the following disclaimer.
jhon309	0:c52df770855b	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
jhon309	0:c52df770855b	18	* this list of conditions and the following disclaimer in the documentation
jhon309	0:c52df770855b	19	* and/or other materials provided with the distribution.
jhon309	0:c52df770855b	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
jhon309	0:c52df770855b	21	* may be used to endorse or promote products derived from this software
jhon309	0:c52df770855b	22	* without specific prior written permission.
jhon309	0:c52df770855b	23	*
jhon309	0:c52df770855b	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jhon309	0:c52df770855b	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jhon309	0:c52df770855b	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
jhon309	0:c52df770855b	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
jhon309	0:c52df770855b	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
jhon309	0:c52df770855b	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
jhon309	0:c52df770855b	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
jhon309	0:c52df770855b	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
jhon309	0:c52df770855b	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
jhon309	0:c52df770855b	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
jhon309	0:c52df770855b	34	*
jhon309	0:c52df770855b	35	******************************************************************************
jhon309	0:c52df770855b	36	*/
jhon309	0:c52df770855b	37
jhon309	0:c52df770855b	38	/* Define to prevent recursive inclusion -------------------------------------*/
jhon309	0:c52df770855b	39	#ifndef __STM32F0xx_HAL_DMA_EX_H
jhon309	0:c52df770855b	40	#define __STM32F0xx_HAL_DMA_EX_H
jhon309	0:c52df770855b	41
jhon309	0:c52df770855b	42	#ifdef __cplusplus
jhon309	0:c52df770855b	43	extern "C" {
jhon309	0:c52df770855b	44	#endif
jhon309	0:c52df770855b	45
jhon309	0:c52df770855b	46	/* Includes ------------------------------------------------------------------*/
jhon309	0:c52df770855b	47	#include "stm32f0xx_hal_def.h"
jhon309	0:c52df770855b	48
jhon309	0:c52df770855b	49	/** @addtogroup STM32F0xx_HAL_Driver
jhon309	0:c52df770855b	50	* @{
jhon309	0:c52df770855b	51	*/
jhon309	0:c52df770855b	52
jhon309	0:c52df770855b	53	/** @addtogroup DMAEx
jhon309	0:c52df770855b	54	* @{
jhon309	0:c52df770855b	55	*/
jhon309	0:c52df770855b	56
jhon309	0:c52df770855b	57	/* Exported types ------------------------------------------------------------*/
jhon309	0:c52df770855b	58	/* Exported constants --------------------------------------------------------*/
jhon309	0:c52df770855b	59	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:c52df770855b	60	/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
jhon309	0:c52df770855b	61	* @{
jhon309	0:c52df770855b	62	*/
jhon309	0:c52df770855b	63	#define DMA1_CHANNEL1_RMP 0x00000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:c52df770855b	64	#define DMA1_CHANNEL2_RMP 0x10000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:c52df770855b	65	#define DMA1_CHANNEL3_RMP 0x20000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:c52df770855b	66	#define DMA1_CHANNEL4_RMP 0x30000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:c52df770855b	67	#define DMA1_CHANNEL5_RMP 0x40000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:c52df770855b	68	#if !defined(STM32F030xC)
jhon309	0:c52df770855b	69	#define DMA1_CHANNEL6_RMP 0x50000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:c52df770855b	70	#define DMA1_CHANNEL7_RMP 0x60000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:c52df770855b	71	#define DMA2_CHANNEL1_RMP 0x00000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:c52df770855b	72	#define DMA2_CHANNEL2_RMP 0x10000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:c52df770855b	73	#define DMA2_CHANNEL3_RMP 0x20000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:c52df770855b	74	#define DMA2_CHANNEL4_RMP 0x30000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:c52df770855b	75	#define DMA2_CHANNEL5_RMP 0x40000000 /!< Internal define for remaping on STM32F09x/30xC /
jhon309	0:c52df770855b	76	#endif /* !defined(STM32F030xC) */
jhon309	0:c52df770855b	77
jhon309	0:c52df770855b	78	/**************** DMA1 remap bit field definition******************/
jhon309	0:c52df770855b	79	/* DMA1 - Channel 1 */
jhon309	0:c52df770855b	80	#define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_DEFAULT) /!< Default remap position for DMA1 /
jhon309	0:c52df770855b	81	#define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_ADC) /!< Remap ADC on DMA1 Channel 1/
jhon309	0:c52df770855b	82	#define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_TIM17_CH1) /!< Remap TIM17 channel 1 on DMA1 channel 1 /
jhon309	0:c52df770855b	83	#define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_TIM17_UP) /!< Remap TIM17 up on DMA1 channel 1 /
jhon309	0:c52df770855b	84	#define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART1_RX) /!< Remap USART1 Rx on DMA1 channel 1 /
jhon309	0:c52df770855b	85	#define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART2_RX) /!< Remap USART2 Rx on DMA1 channel 1 /
jhon309	0:c52df770855b	86	#define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART3_RX) /!< Remap USART3 Rx on DMA1 channel 1 /
jhon309	0:c52df770855b	87	#define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART4_RX) /!< Remap USART4 Rx on DMA1 channel 1 /
jhon309	0:c52df770855b	88	#define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART5_RX) /!< Remap USART5 Rx on DMA1 channel 1 /
jhon309	0:c52df770855b	89	#define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART6_RX) /!< Remap USART6 Rx on DMA1 channel 1 /
jhon309	0:c52df770855b	90	#if !defined(STM32F030xC)
jhon309	0:c52df770855b	91	#define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART7_RX) /!< Remap USART7 Rx on DMA1 channel 1 /
jhon309	0:c52df770855b	92	#define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART8_RX) /!< Remap USART8 Rx on DMA1 channel 1 /
jhon309	0:c52df770855b	93	#endif /* !defined(STM32F030xC) */
jhon309	0:c52df770855b	94
jhon309	0:c52df770855b	95	/* DMA1 - Channel 2 */
jhon309	0:c52df770855b	96	#define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_DEFAULT) /!< Default remap position for DMA1 /
jhon309	0:c52df770855b	97	#define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_ADC) /!< Remap ADC on DMA1 channel 2 /
jhon309	0:c52df770855b	98	#define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_I2C1_TX) /!< Remap I2C1 Tx on DMA1 channel 2 /
jhon309	0:c52df770855b	99	#define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_SPI1_RX) /!< Remap SPI1 Rx on DMA1 channel 2 /
jhon309	0:c52df770855b	100	#define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_TIM1_CH1) /!< Remap TIM1 channel 1 on DMA1 channel 2 /
jhon309	0:c52df770855b	101	#define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_TIM17_CH1) /!< Remap TIM17 channel 1 on DMA1 channel 2 /
jhon309	0:c52df770855b	102	#define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_TIM17_UP) /!< Remap TIM17 up on DMA1 channel 2 /
jhon309	0:c52df770855b	103	#define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART1_TX) /!< Remap USART1 Tx on DMA1 channel 2 /
jhon309	0:c52df770855b	104	#define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART2_TX) /!< Remap USART2 Tx on DMA1 channel 2 /
jhon309	0:c52df770855b	105	#define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART3_TX) /!< Remap USART3 Tx on DMA1 channel 2 /
jhon309	0:c52df770855b	106	#define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART4_TX) /!< Remap USART4 Tx on DMA1 channel 2 /
jhon309	0:c52df770855b	107	#define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART5_TX) /!< Remap USART5 Tx on DMA1 channel 2 /
jhon309	0:c52df770855b	108	#define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART6_TX) /!< Remap USART6 Tx on DMA1 channel 2 /
jhon309	0:c52df770855b	109	#if !defined(STM32F030xC)
jhon309	0:c52df770855b	110	#define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART7_TX) /!< Remap USART7 Tx on DMA1 channel 2 /
jhon309	0:c52df770855b	111	#define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART8_TX) /!< Remap USART8 Tx on DMA1 channel 2 /
jhon309	0:c52df770855b	112	#endif /* !defined(STM32F030xC) */
jhon309	0:c52df770855b	113
jhon309	0:c52df770855b	114	/* DMA1 - Channel 3 */
jhon309	0:c52df770855b	115	#define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_DEFAULT) /!< Default remap position for DMA1 /
jhon309	0:c52df770855b	116	#define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_TIM6_UP) /!< Remap TIM6 up on DMA1 channel 3 /
jhon309	0:c52df770855b	117	#if !defined(STM32F030xC)
jhon309	0:c52df770855b	118	#define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_DAC_CH1) /!< Remap DAC Channel 1on DMA1 channel 3 /
jhon309	0:c52df770855b	119	#endif /* !defined(STM32F030xC) */
jhon309	0:c52df770855b	120	#define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_I2C1_RX) /!< Remap I2C1 Rx on DMA1 channel 3 /
jhon309	0:c52df770855b	121	#define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_SPI1_TX) /!< Remap SPI1 Tx on DMA1 channel 3 /
jhon309	0:c52df770855b	122	#define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_TIM1_CH2) /!< Remap TIM1 channel 2 on DMA1 channel 3 /
jhon309	0:c52df770855b	123	#if !defined(STM32F030xC)
jhon309	0:c52df770855b	124	#define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_TIM2_CH2) /!< Remap TIM2 channel 2 on DMA1 channel 3 /
jhon309	0:c52df770855b	125	#endif /* !defined(STM32F030xC) */
jhon309	0:c52df770855b	126	#define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_TIM16_CH1) /!< Remap TIM16 channel 1 on DMA1 channel 3 /
jhon309	0:c52df770855b	127	#define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_TIM16_UP) /!< Remap TIM16 up on DMA1 channel 3 /
jhon309	0:c52df770855b	128	#define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART1_RX) /!< Remap USART1 Rx on DMA1 channel 3 /
jhon309	0:c52df770855b	129	#define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART2_RX) /!< Remap USART2 Rx on DMA1 channel 3 /
jhon309	0:c52df770855b	130	#define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART3_RX) /!< Remap USART3 Rx on DMA1 channel 3 /
jhon309	0:c52df770855b	131	#define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART4_RX) /!< Remap USART4 Rx on DMA1 channel 3 /
jhon309	0:c52df770855b	132	#define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART5_RX) /!< Remap USART5 Rx on DMA1 channel 3 /
jhon309	0:c52df770855b	133	#define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART6_RX) /!< Remap USART6 Rx on DMA1 channel 3 /
jhon309	0:c52df770855b	134	#if !defined(STM32F030xC)
jhon309	0:c52df770855b	135	#define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART7_RX) /!< Remap USART7 Rx on DMA1 channel 3 /
jhon309	0:c52df770855b	136	#define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART8_RX) /!< Remap USART8 Rx on DMA1 channel 3 /
jhon309	0:c52df770855b	137	#endif /* !defined(STM32F030xC) */
jhon309	0:c52df770855b	138
jhon309	0:c52df770855b	139	/* DMA1 - Channel 4 */
jhon309	0:c52df770855b	140	#define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_DEFAULT) /!< Default remap position for DMA1 /
jhon309	0:c52df770855b	141	#define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_TIM7_UP) /!< Remap TIM7 up on DMA1 channel 4 /
jhon309	0:c52df770855b	142	#if !defined(STM32F030xC)
jhon309	0:c52df770855b	143	#define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_DAC_CH2) /!< Remap DAC Channel 2 on DMA1 channel 4 /
jhon309	0:c52df770855b	144	#endif /* !defined(STM32F030xC) */
jhon309	0:c52df770855b	145	#define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_I2C2_TX) /!< Remap I2C2 Tx on DMA1 channel 4 /
jhon309	0:c52df770855b	146	#define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_SPI2_RX) /!< Remap SPI2 Rx on DMA1 channel 4 /
jhon309	0:c52df770855b	147	#if !defined(STM32F030xC)
jhon309	0:c52df770855b	148	#define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_TIM2_CH4) /!< Remap TIM2 channel 4 on DMA1 channel 4 /
jhon309	0:c52df770855b	149	#endif /* !defined(STM32F030xC) */
jhon309	0:c52df770855b	150	#define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_TIM3_CH1) /!< Remap TIM3 channel 1 on DMA1 channel 4 /
jhon309	0:c52df770855b	151	#define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_TIM3_TRIG) /!< Remap TIM3 Trig on DMA1 channel 4 /
jhon309	0:c52df770855b	152	#define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_TIM16_CH1) /!< Remap TIM16 channel 1 on DMA1 channel 4 /
jhon309	0:c52df770855b	153	#define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_TIM16_UP) /!< Remap TIM16 up on DMA1 channel 4 /
jhon309	0:c52df770855b	154	#define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART1_TX) /!< Remap USART1 Tx on DMA1 channel 4 /
jhon309	0:c52df770855b	155	#define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART2_TX) /!< Remap USART2 Tx on DMA1 channel 4 /
jhon309	0:c52df770855b	156	#define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART3_TX) /!< Remap USART3 Tx on DMA1 channel 4 /
jhon309	0:c52df770855b	157	#define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART4_TX) /!< Remap USART4 Tx on DMA1 channel 4 /
jhon309	0:c52df770855b	158	#define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART5_TX) /!< Remap USART5 Tx on DMA1 channel 4 /
jhon309	0:c52df770855b	159	#define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART6_TX) /!< Remap USART6 Tx on DMA1 channel 4 /
jhon309	0:c52df770855b	160	#if !defined(STM32F030xC)
jhon309	0:c52df770855b	161	#define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART7_TX) /!< Remap USART7 Tx on DMA1 channel 4 /
jhon309	0:c52df770855b	162	#define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART8_TX) /!< Remap USART8 Tx on DMA1 channel 4 /
jhon309	0:c52df770855b	163	#endif /* !defined(STM32F030xC) */
jhon309	0:c52df770855b	164
jhon309	0:c52df770855b	165	/* DMA1 - Channel 5 */
jhon309	0:c52df770855b	166	#define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_DEFAULT) /!< Default remap position for DMA1 /
jhon309	0:c52df770855b	167	#define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_I2C2_RX) /!< Remap I2C2 Rx on DMA1 channel 5 /
jhon309	0:c52df770855b	168	#define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_SPI2_TX) /!< Remap SPI1 Tx on DMA1 channel 5 /
jhon309	0:c52df770855b	169	#define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_TIM1_CH3) /!< Remap TIM1 channel 3 on DMA1 channel 5 /
jhon309	0:c52df770855b	170	#define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART1_RX) /!< Remap USART1 Rx on DMA1 channel 5 /
jhon309	0:c52df770855b	171	#define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART2_RX) /!< Remap USART2 Rx on DMA1 channel 5 /
jhon309	0:c52df770855b	172	#define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART3_RX) /!< Remap USART3 Rx on DMA1 channel 5 /
jhon309	0:c52df770855b	173	#define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART4_RX) /!< Remap USART4 Rx on DMA1 channel 5 /
jhon309	0:c52df770855b	174	#define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART5_RX) /!< Remap USART5 Rx on DMA1 channel 5 /
jhon309	0:c52df770855b	175	#define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART6_RX) /!< Remap USART6 Rx on DMA1 channel 5 /
jhon309	0:c52df770855b	176	#if !defined(STM32F030xC)
jhon309	0:c52df770855b	177	#define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART7_RX) /!< Remap USART7 Rx on DMA1 channel 5 /
jhon309	0:c52df770855b	178	#define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART8_RX) /!< Remap USART8 Rx on DMA1 channel 5 /
jhon309	0:c52df770855b	179	#endif /* !defined(STM32F030xC) */
jhon309	0:c52df770855b	180
jhon309	0:c52df770855b	181	#if !defined(STM32F030xC)
jhon309	0:c52df770855b	182	/* DMA1 - Channel 6 */
jhon309	0:c52df770855b	183	#define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_DEFAULT) /!< Default remap position for DMA1 /
jhon309	0:c52df770855b	184	#define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_I2C1_TX) /!< Remap I2C1 Tx on DMA1 channel 6 /
jhon309	0:c52df770855b	185	#define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_SPI2_RX) /!< Remap SPI2 Rx on DMA1 channel 6 /
jhon309	0:c52df770855b	186	#define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_TIM1_CH1) /!< Remap TIM1 channel 1 on DMA1 channel 6 /
jhon309	0:c52df770855b	187	#define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_TIM1_CH2) /!< Remap TIM1 channel 2 on DMA1 channel 6 /
jhon309	0:c52df770855b	188	#define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_TIM1_CH3) /!< Remap TIM1 channel 3 on DMA1 channel 6 /
jhon309	0:c52df770855b	189	#define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_TIM3_CH1) /!< Remap TIM3 channel 1 on DMA1 channel 6 /
jhon309	0:c52df770855b	190	#define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_TIM3_TRIG) /!< Remap TIM3 Trig on DMA1 channel 6 /
jhon309	0:c52df770855b	191	#define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_TIM16_CH1) /!< Remap TIM16 channel 1 on DMA1 channel 6 /
jhon309	0:c52df770855b	192	#define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_TIM16_UP) /!< Remap TIM16 up on DMA1 channel 6 /
jhon309	0:c52df770855b	193	#define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART1_RX) /!< Remap USART1 Rx on DMA1 channel 6 /
jhon309	0:c52df770855b	194	#define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART2_RX) /!< Remap USART2 Rx on DMA1 channel 6 /
jhon309	0:c52df770855b	195	#define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART3_RX) /!< Remap USART3 Rx on DMA1 channel 6 /
jhon309	0:c52df770855b	196	#define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART4_RX) /!< Remap USART4 Rx on DMA1 channel 6 /
jhon309	0:c52df770855b	197	#define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART5_RX) /!< Remap USART5 Rx on DMA1 channel 6 /
jhon309	0:c52df770855b	198	#define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART6_RX) /!< Remap USART6 Rx on DMA1 channel 6 /
jhon309	0:c52df770855b	199	#define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART7_RX) /!< Remap USART7 Rx on DMA1 channel 6 /
jhon309	0:c52df770855b	200	#define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART8_RX) /!< Remap USART8 Rx on DMA1 channel 6 /
jhon309	0:c52df770855b	201	/* DMA1 - Channel 7 */
jhon309	0:c52df770855b	202	#define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_DEFAULT) /!< Default remap position for DMA1 /
jhon309	0:c52df770855b	203	#define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_I2C1_RX) /!< Remap I2C1 Rx on DMA1 channel 7 /
jhon309	0:c52df770855b	204	#define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_SPI2_TX) /!< Remap SPI2 Tx on DMA1 channel 7 /
jhon309	0:c52df770855b	205	#define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_TIM2_CH2) /!< Remap TIM2 channel 2 on DMA1 channel 7 /
jhon309	0:c52df770855b	206	#define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_TIM2_CH4) /!< Remap TIM2 channel 4 on DMA1 channel 7 /
jhon309	0:c52df770855b	207	#define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_TIM17_CH1) /!< Remap TIM17 channel 1 on DMA1 channel 7 /
jhon309	0:c52df770855b	208	#define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_TIM17_UP) /!< Remap TIM17 up on DMA1 channel 7 /
jhon309	0:c52df770855b	209	#define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART1_TX) /!< Remap USART1 Tx on DMA1 channel 7 /
jhon309	0:c52df770855b	210	#define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART2_TX) /!< Remap USART2 Tx on DMA1 channel 7 /
jhon309	0:c52df770855b	211	#define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART3_TX) /!< Remap USART3 Tx on DMA1 channel 7 /
jhon309	0:c52df770855b	212	#define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART4_TX) /!< Remap USART4 Tx on DMA1 channel 7 /
jhon309	0:c52df770855b	213	#define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART5_TX) /!< Remap USART5 Tx on DMA1 channel 7 /
jhon309	0:c52df770855b	214	#define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART6_TX) /!< Remap USART6 Tx on DMA1 channel 7 /
jhon309	0:c52df770855b	215	#define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART7_TX) /!< Remap USART7 Tx on DMA1 channel 7 /
jhon309	0:c52df770855b	216	#define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART8_TX) /!< Remap USART8 Tx on DMA1 channel 7 /
jhon309	0:c52df770855b	217
jhon309	0:c52df770855b	218	/**************** DMA2 remap bit field definition******************/
jhon309	0:c52df770855b	219	/* DMA2 - Channel 1 */
jhon309	0:c52df770855b	220	#define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_DEFAULT) /!< Default remap position for DMA2 /
jhon309	0:c52df770855b	221	#define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_I2C2_TX) /!< Remap I2C2 TX on DMA2 channel 1 /
jhon309	0:c52df770855b	222	#define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART1_TX) /!< Remap USART1 Tx on DMA2 channel 1 /
jhon309	0:c52df770855b	223	#define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART2_TX) /!< Remap USART2 Tx on DMA2 channel 1 /
jhon309	0:c52df770855b	224	#define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART3_TX) /!< Remap USART3 Tx on DMA2 channel 1 /
jhon309	0:c52df770855b	225	#define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART4_TX) /!< Remap USART4 Tx on DMA2 channel 1 /
jhon309	0:c52df770855b	226	#define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART5_TX) /!< Remap USART5 Tx on DMA2 channel 1 /
jhon309	0:c52df770855b	227	#define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART6_TX) /!< Remap USART6 Tx on DMA2 channel 1 /
jhon309	0:c52df770855b	228	#define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART7_TX) /!< Remap USART7 Tx on DMA2 channel 1 /
jhon309	0:c52df770855b	229	#define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART8_TX) /!< Remap USART8 Tx on DMA2 channel 1 /
jhon309	0:c52df770855b	230	/* DMA2 - Channel 2 */
jhon309	0:c52df770855b	231	#define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_DEFAULT) /!< Default remap position for DMA2 /
jhon309	0:c52df770855b	232	#define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_I2C2_RX) /!< Remap I2C2 Rx on DMA2 channel 2 /
jhon309	0:c52df770855b	233	#define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART1_RX) /!< Remap USART1 Rx on DMA2 channel 2 /
jhon309	0:c52df770855b	234	#define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART2_RX) /!< Remap USART2 Rx on DMA2 channel 2 /
jhon309	0:c52df770855b	235	#define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART3_RX) /!< Remap USART3 Rx on DMA2 channel 2 /
jhon309	0:c52df770855b	236	#define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART4_RX) /!< Remap USART4 Rx on DMA2 channel 2 /
jhon309	0:c52df770855b	237	#define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART5_RX) /!< Remap USART5 Rx on DMA2 channel 2 /
jhon309	0:c52df770855b	238	#define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART6_RX) /!< Remap USART6 Rx on DMA2 channel 2 /
jhon309	0:c52df770855b	239	#define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART7_RX) /!< Remap USART7 Rx on DMA2 channel 2 /
jhon309	0:c52df770855b	240	#define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART8_RX) /!< Remap USART8 Rx on DMA2 channel 2 /
jhon309	0:c52df770855b	241	/* DMA2 - Channel 3 */
jhon309	0:c52df770855b	242	#define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_DEFAULT) /!< Default remap position for DMA2 /
jhon309	0:c52df770855b	243	#define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_TIM6_UP) /!< Remap TIM6 up on DMA2 channel 3 /
jhon309	0:c52df770855b	244	#define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_DAC_CH1) /!< Remap DAC channel 1 on DMA2 channel 3 /
jhon309	0:c52df770855b	245	#define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_SPI1_RX) /!< Remap SPI1 Rx on DMA2 channel 3 /
jhon309	0:c52df770855b	246	#define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART1_RX) /!< Remap USART1 Rx on DMA2 channel 3 /
jhon309	0:c52df770855b	247	#define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART2_RX) /!< Remap USART2 Rx on DMA2 channel 3 /
jhon309	0:c52df770855b	248	#define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART3_RX) /!< Remap USART3 Rx on DMA2 channel 3 /
jhon309	0:c52df770855b	249	#define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART4_RX) /!< Remap USART4 Rx on DMA2 channel 3 /
jhon309	0:c52df770855b	250	#define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART5_RX) /!< Remap USART5 Rx on DMA2 channel 3 /
jhon309	0:c52df770855b	251	#define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART6_RX) /!< Remap USART6 Rx on DMA2 channel 3 /
jhon309	0:c52df770855b	252	#define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART7_RX) /!< Remap USART7 Rx on DMA2 channel 3 /
jhon309	0:c52df770855b	253	#define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART8_RX) /!< Remap USART8 Rx on DMA2 channel 3 /
jhon309	0:c52df770855b	254	/* DMA2 - Channel 4 */
jhon309	0:c52df770855b	255	#define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_DEFAULT) /!< Default remap position for DMA2 /
jhon309	0:c52df770855b	256	#define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_TIM7_UP) /!< Remap TIM7 up on DMA2 channel 4 /
jhon309	0:c52df770855b	257	#define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_DAC_CH2) /!< Remap DAC channel 2 on DMA2 channel 4 /
jhon309	0:c52df770855b	258	#define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_SPI1_TX) /!< Remap SPI1 Tx on DMA2 channel 4 /
jhon309	0:c52df770855b	259	#define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART1_TX) /!< Remap USART1 Tx on DMA2 channel 4 /
jhon309	0:c52df770855b	260	#define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART2_TX) /!< Remap USART2 Tx on DMA2 channel 4 /
jhon309	0:c52df770855b	261	#define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART3_TX) /!< Remap USART3 Tx on DMA2 channel 4 /
jhon309	0:c52df770855b	262	#define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART4_TX) /!< Remap USART4 Tx on DMA2 channel 4 /
jhon309	0:c52df770855b	263	#define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART5_TX) /!< Remap USART5 Tx on DMA2 channel 4 /
jhon309	0:c52df770855b	264	#define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART6_TX) /!< Remap USART6 Tx on DMA2 channel 4 /
jhon309	0:c52df770855b	265	#define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART7_TX) /!< Remap USART7 Tx on DMA2 channel 4 /
jhon309	0:c52df770855b	266	#define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART8_TX) /!< Remap USART8 Tx on DMA2 channel 4 /
jhon309	0:c52df770855b	267	/* DMA2 - Channel 5 */
jhon309	0:c52df770855b	268	#define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_DEFAULT) /!< Default remap position for DMA2 /
jhon309	0:c52df770855b	269	#define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_ADC) /!< Remap ADC on DMA2 channel 5 /
jhon309	0:c52df770855b	270	#define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART1_TX) /!< Remap USART1 Tx on DMA2 channel 5 /
jhon309	0:c52df770855b	271	#define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART2_TX) /!< Remap USART2 Tx on DMA2 channel 5 /
jhon309	0:c52df770855b	272	#define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART3_TX) /!< Remap USART3 Tx on DMA2 channel 5 /
jhon309	0:c52df770855b	273	#define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART4_TX) /!< Remap USART4 Tx on DMA2 channel 5 /
jhon309	0:c52df770855b	274	#define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART5_TX) /!< Remap USART5 Tx on DMA2 channel 5 /
jhon309	0:c52df770855b	275	#define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART6_TX) /!< Remap USART6 Tx on DMA2 channel 5 /
jhon309	0:c52df770855b	276	#define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART7_TX) /!< Remap USART7 Tx on DMA2 channel 5 /
jhon309	0:c52df770855b	277	#define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART8_TX) /!< Remap USART8 Tx on DMA2 channel 5 /
jhon309	0:c52df770855b	278	#endif /* !defined(STM32F030xC) */
jhon309	0:c52df770855b	279
jhon309	0:c52df770855b	280	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	281	#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) \|\|\
jhon309	0:c52df770855b	282	((REQUEST) == HAL_DMA1_CH1_ADC) \|\|\
jhon309	0:c52df770855b	283	((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) \|\|\
jhon309	0:c52df770855b	284	((REQUEST) == HAL_DMA1_CH1_TIM17_UP) \|\|\
jhon309	0:c52df770855b	285	((REQUEST) == HAL_DMA1_CH1_USART1_RX) \|\|\
jhon309	0:c52df770855b	286	((REQUEST) == HAL_DMA1_CH1_USART2_RX) \|\|\
jhon309	0:c52df770855b	287	((REQUEST) == HAL_DMA1_CH1_USART3_RX) \|\|\
jhon309	0:c52df770855b	288	((REQUEST) == HAL_DMA1_CH1_USART4_RX) \|\|\
jhon309	0:c52df770855b	289	((REQUEST) == HAL_DMA1_CH1_USART5_RX) \|\|\
jhon309	0:c52df770855b	290	((REQUEST) == HAL_DMA1_CH1_USART6_RX) \|\|\
jhon309	0:c52df770855b	291	((REQUEST) == HAL_DMA1_CH1_USART7_RX) \|\|\
jhon309	0:c52df770855b	292	((REQUEST) == HAL_DMA1_CH1_USART8_RX) \|\|\
jhon309	0:c52df770855b	293	((REQUEST) == HAL_DMA1_CH2_DEFAULT) \|\|\
jhon309	0:c52df770855b	294	((REQUEST) == HAL_DMA1_CH2_ADC) \|\|\
jhon309	0:c52df770855b	295	((REQUEST) == HAL_DMA1_CH2_I2C1_TX) \|\|\
jhon309	0:c52df770855b	296	((REQUEST) == HAL_DMA1_CH2_SPI1_RX) \|\|\
jhon309	0:c52df770855b	297	((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) \|\|\
jhon309	0:c52df770855b	298	((REQUEST) == HAL_DMA1_CH2_I2C1_TX) \|\|\
jhon309	0:c52df770855b	299	((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) \|\|\
jhon309	0:c52df770855b	300	((REQUEST) == HAL_DMA1_CH2_TIM17_UP) \|\|\
jhon309	0:c52df770855b	301	((REQUEST) == HAL_DMA1_CH2_USART1_TX) \|\|\
jhon309	0:c52df770855b	302	((REQUEST) == HAL_DMA1_CH2_USART2_TX) \|\|\
jhon309	0:c52df770855b	303	((REQUEST) == HAL_DMA1_CH2_USART3_TX) \|\|\
jhon309	0:c52df770855b	304	((REQUEST) == HAL_DMA1_CH2_USART4_TX) \|\|\
jhon309	0:c52df770855b	305	((REQUEST) == HAL_DMA1_CH2_USART5_TX) \|\|\
jhon309	0:c52df770855b	306	((REQUEST) == HAL_DMA1_CH2_USART6_TX) \|\|\
jhon309	0:c52df770855b	307	((REQUEST) == HAL_DMA1_CH2_USART7_TX) \|\|\
jhon309	0:c52df770855b	308	((REQUEST) == HAL_DMA1_CH2_USART8_TX) \|\|\
jhon309	0:c52df770855b	309	((REQUEST) == HAL_DMA1_CH3_DEFAULT) \|\|\
jhon309	0:c52df770855b	310	((REQUEST) == HAL_DMA1_CH3_TIM6_UP) \|\|\
jhon309	0:c52df770855b	311	((REQUEST) == HAL_DMA1_CH3_DAC_CH1) \|\|\
jhon309	0:c52df770855b	312	((REQUEST) == HAL_DMA1_CH3_I2C1_RX) \|\|\
jhon309	0:c52df770855b	313	((REQUEST) == HAL_DMA1_CH3_SPI1_TX) \|\|\
jhon309	0:c52df770855b	314	((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) \|\|\
jhon309	0:c52df770855b	315	((REQUEST) == HAL_DMA1_CH3_TIM2_CH2) \|\|\
jhon309	0:c52df770855b	316	((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) \|\|\
jhon309	0:c52df770855b	317	((REQUEST) == HAL_DMA1_CH3_TIM16_UP) \|\|\
jhon309	0:c52df770855b	318	((REQUEST) == HAL_DMA1_CH3_USART1_RX) \|\|\
jhon309	0:c52df770855b	319	((REQUEST) == HAL_DMA1_CH3_USART2_RX) \|\|\
jhon309	0:c52df770855b	320	((REQUEST) == HAL_DMA1_CH3_USART3_RX) \|\|\
jhon309	0:c52df770855b	321	((REQUEST) == HAL_DMA1_CH3_USART4_RX) \|\|\
jhon309	0:c52df770855b	322	((REQUEST) == HAL_DMA1_CH3_USART5_RX) \|\|\
jhon309	0:c52df770855b	323	((REQUEST) == HAL_DMA1_CH3_USART6_RX) \|\|\
jhon309	0:c52df770855b	324	((REQUEST) == HAL_DMA1_CH3_USART7_RX) \|\|\
jhon309	0:c52df770855b	325	((REQUEST) == HAL_DMA1_CH3_USART8_RX) \|\|\
jhon309	0:c52df770855b	326	((REQUEST) == HAL_DMA1_CH4_DEFAULT) \|\|\
jhon309	0:c52df770855b	327	((REQUEST) == HAL_DMA1_CH4_TIM7_UP) \|\|\
jhon309	0:c52df770855b	328	((REQUEST) == HAL_DMA1_CH4_DAC_CH2) \|\|\
jhon309	0:c52df770855b	329	((REQUEST) == HAL_DMA1_CH4_I2C2_TX) \|\|\
jhon309	0:c52df770855b	330	((REQUEST) == HAL_DMA1_CH4_SPI2_RX) \|\|\
jhon309	0:c52df770855b	331	((REQUEST) == HAL_DMA1_CH4_TIM2_CH4) \|\|\
jhon309	0:c52df770855b	332	((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) \|\|\
jhon309	0:c52df770855b	333	((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) \|\|\
jhon309	0:c52df770855b	334	((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) \|\|\
jhon309	0:c52df770855b	335	((REQUEST) == HAL_DMA1_CH4_TIM16_UP) \|\|\
jhon309	0:c52df770855b	336	((REQUEST) == HAL_DMA1_CH4_USART1_TX) \|\|\
jhon309	0:c52df770855b	337	((REQUEST) == HAL_DMA1_CH4_USART2_TX) \|\|\
jhon309	0:c52df770855b	338	((REQUEST) == HAL_DMA1_CH4_USART3_TX) \|\|\
jhon309	0:c52df770855b	339	((REQUEST) == HAL_DMA1_CH4_USART4_TX) \|\|\
jhon309	0:c52df770855b	340	((REQUEST) == HAL_DMA1_CH4_USART5_TX) \|\|\
jhon309	0:c52df770855b	341	((REQUEST) == HAL_DMA1_CH4_USART6_TX) \|\|\
jhon309	0:c52df770855b	342	((REQUEST) == HAL_DMA1_CH4_USART7_TX) \|\|\
jhon309	0:c52df770855b	343	((REQUEST) == HAL_DMA1_CH4_USART8_TX) \|\|\
jhon309	0:c52df770855b	344	((REQUEST) == HAL_DMA1_CH5_DEFAULT) \|\|\
jhon309	0:c52df770855b	345	((REQUEST) == HAL_DMA1_CH5_I2C2_RX) \|\|\
jhon309	0:c52df770855b	346	((REQUEST) == HAL_DMA1_CH5_SPI2_TX) \|\|\
jhon309	0:c52df770855b	347	((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) \|\|\
jhon309	0:c52df770855b	348	((REQUEST) == HAL_DMA1_CH5_USART1_RX) \|\|\
jhon309	0:c52df770855b	349	((REQUEST) == HAL_DMA1_CH5_USART2_RX) \|\|\
jhon309	0:c52df770855b	350	((REQUEST) == HAL_DMA1_CH5_USART3_RX) \|\|\
jhon309	0:c52df770855b	351	((REQUEST) == HAL_DMA1_CH5_USART4_RX) \|\|\
jhon309	0:c52df770855b	352	((REQUEST) == HAL_DMA1_CH5_USART5_RX) \|\|\
jhon309	0:c52df770855b	353	((REQUEST) == HAL_DMA1_CH5_USART6_RX) \|\|\
jhon309	0:c52df770855b	354	((REQUEST) == HAL_DMA1_CH5_USART7_RX) \|\|\
jhon309	0:c52df770855b	355	((REQUEST) == HAL_DMA1_CH5_USART8_RX) \|\|\
jhon309	0:c52df770855b	356	((REQUEST) == HAL_DMA1_CH6_DEFAULT) \|\|\
jhon309	0:c52df770855b	357	((REQUEST) == HAL_DMA1_CH6_I2C1_TX) \|\|\
jhon309	0:c52df770855b	358	((REQUEST) == HAL_DMA1_CH6_SPI2_RX) \|\|\
jhon309	0:c52df770855b	359	((REQUEST) == HAL_DMA1_CH6_TIM1_CH1) \|\|\
jhon309	0:c52df770855b	360	((REQUEST) == HAL_DMA1_CH6_TIM1_CH2) \|\|\
jhon309	0:c52df770855b	361	((REQUEST) == HAL_DMA1_CH6_TIM1_CH3) \|\|\
jhon309	0:c52df770855b	362	((REQUEST) == HAL_DMA1_CH6_TIM3_CH1) \|\|\
jhon309	0:c52df770855b	363	((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) \|\|\
jhon309	0:c52df770855b	364	((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) \|\|\
jhon309	0:c52df770855b	365	((REQUEST) == HAL_DMA1_CH6_TIM16_UP) \|\|\
jhon309	0:c52df770855b	366	((REQUEST) == HAL_DMA1_CH6_USART1_RX) \|\|\
jhon309	0:c52df770855b	367	((REQUEST) == HAL_DMA1_CH6_USART2_RX) \|\|\
jhon309	0:c52df770855b	368	((REQUEST) == HAL_DMA1_CH6_USART3_RX) \|\|\
jhon309	0:c52df770855b	369	((REQUEST) == HAL_DMA1_CH6_USART4_RX) \|\|\
jhon309	0:c52df770855b	370	((REQUEST) == HAL_DMA1_CH6_USART5_RX) \|\|\
jhon309	0:c52df770855b	371	((REQUEST) == HAL_DMA1_CH6_USART6_RX) \|\|\
jhon309	0:c52df770855b	372	((REQUEST) == HAL_DMA1_CH6_USART7_RX) \|\|\
jhon309	0:c52df770855b	373	((REQUEST) == HAL_DMA1_CH6_USART8_RX) \|\|\
jhon309	0:c52df770855b	374	((REQUEST) == HAL_DMA1_CH7_DEFAULT) \|\|\
jhon309	0:c52df770855b	375	((REQUEST) == HAL_DMA1_CH7_I2C1_RX) \|\|\
jhon309	0:c52df770855b	376	((REQUEST) == HAL_DMA1_CH7_SPI2_TX) \|\|\
jhon309	0:c52df770855b	377	((REQUEST) == HAL_DMA1_CH7_TIM2_CH2) \|\|\
jhon309	0:c52df770855b	378	((REQUEST) == HAL_DMA1_CH7_TIM2_CH4) \|\|\
jhon309	0:c52df770855b	379	((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) \|\|\
jhon309	0:c52df770855b	380	((REQUEST) == HAL_DMA1_CH7_TIM17_UP) \|\|\
jhon309	0:c52df770855b	381	((REQUEST) == HAL_DMA1_CH7_USART1_TX) \|\|\
jhon309	0:c52df770855b	382	((REQUEST) == HAL_DMA1_CH7_USART2_TX) \|\|\
jhon309	0:c52df770855b	383	((REQUEST) == HAL_DMA1_CH7_USART3_TX) \|\|\
jhon309	0:c52df770855b	384	((REQUEST) == HAL_DMA1_CH7_USART4_TX) \|\|\
jhon309	0:c52df770855b	385	((REQUEST) == HAL_DMA1_CH7_USART5_TX) \|\|\
jhon309	0:c52df770855b	386	((REQUEST) == HAL_DMA1_CH7_USART6_TX) \|\|\
jhon309	0:c52df770855b	387	((REQUEST) == HAL_DMA1_CH7_USART7_TX) \|\|\
jhon309	0:c52df770855b	388	((REQUEST) == HAL_DMA1_CH7_USART8_TX))
jhon309	0:c52df770855b	389
jhon309	0:c52df770855b	390	#define IS_HAL_DMA2_REMAP(REQUEST) (((REQUEST) == HAL_DMA2_CH1_DEFAULT) \|\|\
jhon309	0:c52df770855b	391	((REQUEST) == HAL_DMA2_CH1_I2C2_TX) \|\|\
jhon309	0:c52df770855b	392	((REQUEST) == HAL_DMA2_CH1_USART1_TX) \|\|\
jhon309	0:c52df770855b	393	((REQUEST) == HAL_DMA2_CH1_USART2_TX) \|\|\
jhon309	0:c52df770855b	394	((REQUEST) == HAL_DMA2_CH1_USART3_TX) \|\|\
jhon309	0:c52df770855b	395	((REQUEST) == HAL_DMA2_CH1_USART4_TX) \|\|\
jhon309	0:c52df770855b	396	((REQUEST) == HAL_DMA2_CH1_USART5_TX) \|\|\
jhon309	0:c52df770855b	397	((REQUEST) == HAL_DMA2_CH1_USART6_TX) \|\|\
jhon309	0:c52df770855b	398	((REQUEST) == HAL_DMA2_CH1_USART7_TX) \|\|\
jhon309	0:c52df770855b	399	((REQUEST) == HAL_DMA2_CH1_USART8_TX) \|\|\
jhon309	0:c52df770855b	400	((REQUEST) == HAL_DMA2_CH2_DEFAULT) \|\|\
jhon309	0:c52df770855b	401	((REQUEST) == HAL_DMA2_CH2_I2C2_RX) \|\|\
jhon309	0:c52df770855b	402	((REQUEST) == HAL_DMA2_CH2_USART1_RX) \|\|\
jhon309	0:c52df770855b	403	((REQUEST) == HAL_DMA2_CH2_USART2_RX) \|\|\
jhon309	0:c52df770855b	404	((REQUEST) == HAL_DMA2_CH2_USART3_RX) \|\|\
jhon309	0:c52df770855b	405	((REQUEST) == HAL_DMA2_CH2_USART4_RX) \|\|\
jhon309	0:c52df770855b	406	((REQUEST) == HAL_DMA2_CH2_USART5_RX) \|\|\
jhon309	0:c52df770855b	407	((REQUEST) == HAL_DMA2_CH2_USART6_RX) \|\|\
jhon309	0:c52df770855b	408	((REQUEST) == HAL_DMA2_CH2_USART7_RX) \|\|\
jhon309	0:c52df770855b	409	((REQUEST) == HAL_DMA2_CH2_USART8_RX) \|\|\
jhon309	0:c52df770855b	410	((REQUEST) == HAL_DMA2_CH3_DEFAULT) \|\|\
jhon309	0:c52df770855b	411	((REQUEST) == HAL_DMA2_CH3_TIM6_UP) \|\|\
jhon309	0:c52df770855b	412	((REQUEST) == HAL_DMA2_CH3_DAC_CH1) \|\|\
jhon309	0:c52df770855b	413	((REQUEST) == HAL_DMA2_CH3_SPI1_RX) \|\|\
jhon309	0:c52df770855b	414	((REQUEST) == HAL_DMA2_CH3_USART1_RX) \|\|\
jhon309	0:c52df770855b	415	((REQUEST) == HAL_DMA2_CH3_USART2_RX) \|\|\
jhon309	0:c52df770855b	416	((REQUEST) == HAL_DMA2_CH3_USART3_RX) \|\|\
jhon309	0:c52df770855b	417	((REQUEST) == HAL_DMA2_CH3_USART4_RX) \|\|\
jhon309	0:c52df770855b	418	((REQUEST) == HAL_DMA2_CH3_USART5_RX) \|\|\
jhon309	0:c52df770855b	419	((REQUEST) == HAL_DMA2_CH3_USART6_RX) \|\|\
jhon309	0:c52df770855b	420	((REQUEST) == HAL_DMA2_CH3_USART7_RX) \|\|\
jhon309	0:c52df770855b	421	((REQUEST) == HAL_DMA2_CH3_USART8_RX) \|\|\
jhon309	0:c52df770855b	422	((REQUEST) == HAL_DMA2_CH4_DEFAULT) \|\|\
jhon309	0:c52df770855b	423	((REQUEST) == HAL_DMA2_CH4_TIM7_UP) \|\|\
jhon309	0:c52df770855b	424	((REQUEST) == HAL_DMA2_CH4_DAC_CH2) \|\|\
jhon309	0:c52df770855b	425	((REQUEST) == HAL_DMA2_CH4_SPI1_TX) \|\|\
jhon309	0:c52df770855b	426	((REQUEST) == HAL_DMA2_CH4_USART1_TX) \|\|\
jhon309	0:c52df770855b	427	((REQUEST) == HAL_DMA2_CH4_USART2_TX) \|\|\
jhon309	0:c52df770855b	428	((REQUEST) == HAL_DMA2_CH4_USART3_TX) \|\|\
jhon309	0:c52df770855b	429	((REQUEST) == HAL_DMA2_CH4_USART4_TX) \|\|\
jhon309	0:c52df770855b	430	((REQUEST) == HAL_DMA2_CH4_USART5_TX) \|\|\
jhon309	0:c52df770855b	431	((REQUEST) == HAL_DMA2_CH4_USART6_TX) \|\|\
jhon309	0:c52df770855b	432	((REQUEST) == HAL_DMA2_CH4_USART7_TX) \|\|\
jhon309	0:c52df770855b	433	((REQUEST) == HAL_DMA2_CH4_USART8_TX) \|\|\
jhon309	0:c52df770855b	434	((REQUEST) == HAL_DMA2_CH5_DEFAULT) \|\|\
jhon309	0:c52df770855b	435	((REQUEST) == HAL_DMA2_CH5_ADC) \|\|\
jhon309	0:c52df770855b	436	((REQUEST) == HAL_DMA2_CH5_USART1_TX) \|\|\
jhon309	0:c52df770855b	437	((REQUEST) == HAL_DMA2_CH5_USART2_TX) \|\|\
jhon309	0:c52df770855b	438	((REQUEST) == HAL_DMA2_CH5_USART3_TX) \|\|\
jhon309	0:c52df770855b	439	((REQUEST) == HAL_DMA2_CH5_USART4_TX) \|\|\
jhon309	0:c52df770855b	440	((REQUEST) == HAL_DMA2_CH5_USART5_TX) \|\|\
jhon309	0:c52df770855b	441	((REQUEST) == HAL_DMA2_CH5_USART6_TX) \|\|\
jhon309	0:c52df770855b	442	((REQUEST) == HAL_DMA2_CH5_USART7_TX) \|\|\
jhon309	0:c52df770855b	443	((REQUEST) == HAL_DMA2_CH5_USART8_TX ))
jhon309	0:c52df770855b	444	#endif /* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	445
jhon309	0:c52df770855b	446	#if defined(STM32F030xC)
jhon309	0:c52df770855b	447	#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) \|\|\
jhon309	0:c52df770855b	448	((REQUEST) == HAL_DMA1_CH1_ADC) \|\|\
jhon309	0:c52df770855b	449	((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) \|\|\
jhon309	0:c52df770855b	450	((REQUEST) == HAL_DMA1_CH1_TIM17_UP) \|\|\
jhon309	0:c52df770855b	451	((REQUEST) == HAL_DMA1_CH1_USART1_RX) \|\|\
jhon309	0:c52df770855b	452	((REQUEST) == HAL_DMA1_CH1_USART2_RX) \|\|\
jhon309	0:c52df770855b	453	((REQUEST) == HAL_DMA1_CH1_USART3_RX) \|\|\
jhon309	0:c52df770855b	454	((REQUEST) == HAL_DMA1_CH1_USART4_RX) \|\|\
jhon309	0:c52df770855b	455	((REQUEST) == HAL_DMA1_CH1_USART5_RX) \|\|\
jhon309	0:c52df770855b	456	((REQUEST) == HAL_DMA1_CH1_USART6_RX) \|\|\
jhon309	0:c52df770855b	457	((REQUEST) == HAL_DMA1_CH2_DEFAULT) \|\|\
jhon309	0:c52df770855b	458	((REQUEST) == HAL_DMA1_CH2_ADC) \|\|\
jhon309	0:c52df770855b	459	((REQUEST) == HAL_DMA1_CH2_I2C1_TX) \|\|\
jhon309	0:c52df770855b	460	((REQUEST) == HAL_DMA1_CH2_SPI1_RX) \|\|\
jhon309	0:c52df770855b	461	((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) \|\|\
jhon309	0:c52df770855b	462	((REQUEST) == HAL_DMA1_CH2_I2C1_TX) \|\|\
jhon309	0:c52df770855b	463	((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) \|\|\
jhon309	0:c52df770855b	464	((REQUEST) == HAL_DMA1_CH2_TIM17_UP) \|\|\
jhon309	0:c52df770855b	465	((REQUEST) == HAL_DMA1_CH2_USART1_TX) \|\|\
jhon309	0:c52df770855b	466	((REQUEST) == HAL_DMA1_CH2_USART2_TX) \|\|\
jhon309	0:c52df770855b	467	((REQUEST) == HAL_DMA1_CH2_USART3_TX) \|\|\
jhon309	0:c52df770855b	468	((REQUEST) == HAL_DMA1_CH2_USART4_TX) \|\|\
jhon309	0:c52df770855b	469	((REQUEST) == HAL_DMA1_CH2_USART5_TX) \|\|\
jhon309	0:c52df770855b	470	((REQUEST) == HAL_DMA1_CH2_USART6_TX) \|\|\
jhon309	0:c52df770855b	471	((REQUEST) == HAL_DMA1_CH3_DEFAULT) \|\|\
jhon309	0:c52df770855b	472	((REQUEST) == HAL_DMA1_CH3_TIM6_UP) \|\|\
jhon309	0:c52df770855b	473	((REQUEST) == HAL_DMA1_CH3_I2C1_RX) \|\|\
jhon309	0:c52df770855b	474	((REQUEST) == HAL_DMA1_CH3_SPI1_TX) \|\|\
jhon309	0:c52df770855b	475	((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) \|\|\
jhon309	0:c52df770855b	476	((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) \|\|\
jhon309	0:c52df770855b	477	((REQUEST) == HAL_DMA1_CH3_TIM16_UP) \|\|\
jhon309	0:c52df770855b	478	((REQUEST) == HAL_DMA1_CH3_USART1_RX) \|\|\
jhon309	0:c52df770855b	479	((REQUEST) == HAL_DMA1_CH3_USART2_RX) \|\|\
jhon309	0:c52df770855b	480	((REQUEST) == HAL_DMA1_CH3_USART3_RX) \|\|\
jhon309	0:c52df770855b	481	((REQUEST) == HAL_DMA1_CH3_USART4_RX) \|\|\
jhon309	0:c52df770855b	482	((REQUEST) == HAL_DMA1_CH3_USART5_RX) \|\|\
jhon309	0:c52df770855b	483	((REQUEST) == HAL_DMA1_CH3_USART6_RX) \|\|\
jhon309	0:c52df770855b	484	((REQUEST) == HAL_DMA1_CH4_DEFAULT) \|\|\
jhon309	0:c52df770855b	485	((REQUEST) == HAL_DMA1_CH4_TIM7_UP) \|\|\
jhon309	0:c52df770855b	486	((REQUEST) == HAL_DMA1_CH4_I2C2_TX) \|\|\
jhon309	0:c52df770855b	487	((REQUEST) == HAL_DMA1_CH4_SPI2_RX) \|\|\
jhon309	0:c52df770855b	488	((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) \|\|\
jhon309	0:c52df770855b	489	((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) \|\|\
jhon309	0:c52df770855b	490	((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) \|\|\
jhon309	0:c52df770855b	491	((REQUEST) == HAL_DMA1_CH4_TIM16_UP) \|\|\
jhon309	0:c52df770855b	492	((REQUEST) == HAL_DMA1_CH4_USART1_TX) \|\|\
jhon309	0:c52df770855b	493	((REQUEST) == HAL_DMA1_CH4_USART2_TX) \|\|\
jhon309	0:c52df770855b	494	((REQUEST) == HAL_DMA1_CH4_USART3_TX) \|\|\
jhon309	0:c52df770855b	495	((REQUEST) == HAL_DMA1_CH4_USART4_TX) \|\|\
jhon309	0:c52df770855b	496	((REQUEST) == HAL_DMA1_CH4_USART5_TX) \|\|\
jhon309	0:c52df770855b	497	((REQUEST) == HAL_DMA1_CH4_USART6_TX) \|\|\
jhon309	0:c52df770855b	498	((REQUEST) == HAL_DMA1_CH5_DEFAULT) \|\|\
jhon309	0:c52df770855b	499	((REQUEST) == HAL_DMA1_CH5_I2C2_RX) \|\|\
jhon309	0:c52df770855b	500	((REQUEST) == HAL_DMA1_CH5_SPI2_TX) \|\|\
jhon309	0:c52df770855b	501	((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) \|\|\
jhon309	0:c52df770855b	502	((REQUEST) == HAL_DMA1_CH5_USART1_RX) \|\|\
jhon309	0:c52df770855b	503	((REQUEST) == HAL_DMA1_CH5_USART2_RX) \|\|\
jhon309	0:c52df770855b	504	((REQUEST) == HAL_DMA1_CH5_USART3_RX) \|\|\
jhon309	0:c52df770855b	505	((REQUEST) == HAL_DMA1_CH5_USART4_RX) \|\|\
jhon309	0:c52df770855b	506	((REQUEST) == HAL_DMA1_CH5_USART5_RX) \|\|\
jhon309	0:c52df770855b	507	((REQUEST) == HAL_DMA1_CH5_USART6_RX))
jhon309	0:c52df770855b	508	#endif /* STM32F030xC */
jhon309	0:c52df770855b	509
jhon309	0:c52df770855b	510	/**
jhon309	0:c52df770855b	511	* @}
jhon309	0:c52df770855b	512	*/
jhon309	0:c52df770855b	513	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:c52df770855b	514
jhon309	0:c52df770855b	515	/* Exported macros -----------------------------------------------------------*/
jhon309	0:c52df770855b	516
jhon309	0:c52df770855b	517	/** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros
jhon309	0:c52df770855b	518	* @{
jhon309	0:c52df770855b	519	*/
jhon309	0:c52df770855b	520	/* Interrupt & Flag management */
jhon309	0:c52df770855b	521
jhon309	0:c52df770855b	522	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
jhon309	0:c52df770855b	523	/**
jhon309	0:c52df770855b	524	* @brief Returns the current DMA Channel transfer complete flag.
jhon309	0:c52df770855b	525	* @param __HANDLE__: DMA handle
jhon309	0:c52df770855b	526	* @retval The specified transfer complete flag index.
jhon309	0:c52df770855b	527	*/
jhon309	0:c52df770855b	528	#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
jhon309	0:c52df770855b	529	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
jhon309	0:c52df770855b	530	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
jhon309	0:c52df770855b	531	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
jhon309	0:c52df770855b	532	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
jhon309	0:c52df770855b	533	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
jhon309	0:c52df770855b	534	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
jhon309	0:c52df770855b	535	DMA_FLAG_TC7)
jhon309	0:c52df770855b	536
jhon309	0:c52df770855b	537	/**
jhon309	0:c52df770855b	538	* @brief Returns the current DMA Channel half transfer complete flag.
jhon309	0:c52df770855b	539	* @param __HANDLE__: DMA handle
jhon309	0:c52df770855b	540	* @retval The specified half transfer complete flag index.
jhon309	0:c52df770855b	541	*/
jhon309	0:c52df770855b	542	#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
jhon309	0:c52df770855b	543	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
jhon309	0:c52df770855b	544	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
jhon309	0:c52df770855b	545	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
jhon309	0:c52df770855b	546	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
jhon309	0:c52df770855b	547	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
jhon309	0:c52df770855b	548	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
jhon309	0:c52df770855b	549	DMA_FLAG_HT7)
jhon309	0:c52df770855b	550
jhon309	0:c52df770855b	551	/**
jhon309	0:c52df770855b	552	* @brief Returns the current DMA Channel transfer error flag.
jhon309	0:c52df770855b	553	* @param __HANDLE__: DMA handle
jhon309	0:c52df770855b	554	* @retval The specified transfer error flag index.
jhon309	0:c52df770855b	555	*/
jhon309	0:c52df770855b	556	#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
jhon309	0:c52df770855b	557	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
jhon309	0:c52df770855b	558	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
jhon309	0:c52df770855b	559	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
jhon309	0:c52df770855b	560	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
jhon309	0:c52df770855b	561	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
jhon309	0:c52df770855b	562	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
jhon309	0:c52df770855b	563	DMA_FLAG_TE7)
jhon309	0:c52df770855b	564
jhon309	0:c52df770855b	565	/**
jhon309	0:c52df770855b	566	* @brief Get the DMA Channel pending flags.
jhon309	0:c52df770855b	567	* @param __HANDLE__: DMA handle
jhon309	0:c52df770855b	568	* @param __FLAG__: Get the specified flag.
jhon309	0:c52df770855b	569	* This parameter can be any combination of the following values:
jhon309	0:c52df770855b	570	* @arg DMA_FLAG_TCx: Transfer complete flag
jhon309	0:c52df770855b	571	* @arg DMA_FLAG_HTx: Half transfer complete flag
jhon309	0:c52df770855b	572	* @arg DMA_FLAG_TEx: Transfer error flag
jhon309	0:c52df770855b	573	* Where x can be 1_7 to select the DMA Channel flag.
jhon309	0:c52df770855b	574	* @retval The state of FLAG (SET or RESET).
jhon309	0:c52df770855b	575	*/
jhon309	0:c52df770855b	576
jhon309	0:c52df770855b	577	#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
jhon309	0:c52df770855b	578
jhon309	0:c52df770855b	579	/**
jhon309	0:c52df770855b	580	* @brief Clears the DMA Channel pending flags.
jhon309	0:c52df770855b	581	* @param __HANDLE__: DMA handle
jhon309	0:c52df770855b	582	* @param __FLAG__: specifies the flag to clear.
jhon309	0:c52df770855b	583	* This parameter can be any combination of the following values:
jhon309	0:c52df770855b	584	* @arg DMA_FLAG_TCx: Transfer complete flag
jhon309	0:c52df770855b	585	* @arg DMA_FLAG_HTx: Half transfer complete flag
jhon309	0:c52df770855b	586	* @arg DMA_FLAG_TEx: Transfer error flag
jhon309	0:c52df770855b	587	* Where x can be 1_7 to select the DMA Channel flag.
jhon309	0:c52df770855b	588	* @retval None
jhon309	0:c52df770855b	589	*/
jhon309	0:c52df770855b	590	#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
jhon309	0:c52df770855b	591
jhon309	0:c52df770855b	592	#elif defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	593	/**
jhon309	0:c52df770855b	594	* @brief Returns the current DMA Channel transfer complete flag.
jhon309	0:c52df770855b	595	* @param __HANDLE__: DMA handle
jhon309	0:c52df770855b	596	* @retval The specified transfer complete flag index.
jhon309	0:c52df770855b	597	*/
jhon309	0:c52df770855b	598	#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
jhon309	0:c52df770855b	599	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
jhon309	0:c52df770855b	600	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
jhon309	0:c52df770855b	601	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
jhon309	0:c52df770855b	602	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
jhon309	0:c52df770855b	603	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
jhon309	0:c52df770855b	604	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
jhon309	0:c52df770855b	605	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
jhon309	0:c52df770855b	606	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
jhon309	0:c52df770855b	607	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
jhon309	0:c52df770855b	608	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
jhon309	0:c52df770855b	609	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
jhon309	0:c52df770855b	610	DMA_FLAG_TC5)
jhon309	0:c52df770855b	611
jhon309	0:c52df770855b	612	/**
jhon309	0:c52df770855b	613	* @brief Returns the current DMA Channel half transfer complete flag.
jhon309	0:c52df770855b	614	* @param __HANDLE__: DMA handle
jhon309	0:c52df770855b	615	* @retval The specified half transfer complete flag index.
jhon309	0:c52df770855b	616	*/
jhon309	0:c52df770855b	617	#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
jhon309	0:c52df770855b	618	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
jhon309	0:c52df770855b	619	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
jhon309	0:c52df770855b	620	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
jhon309	0:c52df770855b	621	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
jhon309	0:c52df770855b	622	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
jhon309	0:c52df770855b	623	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
jhon309	0:c52df770855b	624	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
jhon309	0:c52df770855b	625	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
jhon309	0:c52df770855b	626	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
jhon309	0:c52df770855b	627	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
jhon309	0:c52df770855b	628	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
jhon309	0:c52df770855b	629	DMA_FLAG_HT5)
jhon309	0:c52df770855b	630
jhon309	0:c52df770855b	631	/**
jhon309	0:c52df770855b	632	* @brief Returns the current DMA Channel transfer error flag.
jhon309	0:c52df770855b	633	* @param __HANDLE__: DMA handle
jhon309	0:c52df770855b	634	* @retval The specified transfer error flag index.
jhon309	0:c52df770855b	635	*/
jhon309	0:c52df770855b	636	#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
jhon309	0:c52df770855b	637	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
jhon309	0:c52df770855b	638	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
jhon309	0:c52df770855b	639	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
jhon309	0:c52df770855b	640	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
jhon309	0:c52df770855b	641	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
jhon309	0:c52df770855b	642	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
jhon309	0:c52df770855b	643	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
jhon309	0:c52df770855b	644	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
jhon309	0:c52df770855b	645	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
jhon309	0:c52df770855b	646	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
jhon309	0:c52df770855b	647	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
jhon309	0:c52df770855b	648	DMA_FLAG_TE5)
jhon309	0:c52df770855b	649
jhon309	0:c52df770855b	650	/**
jhon309	0:c52df770855b	651	* @brief Get the DMA Channel pending flags.
jhon309	0:c52df770855b	652	* @param __HANDLE__: DMA handle
jhon309	0:c52df770855b	653	* @param __FLAG__: Get the specified flag.
jhon309	0:c52df770855b	654	* This parameter can be any combination of the following values:
jhon309	0:c52df770855b	655	* @arg DMA_FLAG_TCx: Transfer complete flag
jhon309	0:c52df770855b	656	* @arg DMA_FLAG_HTx: Half transfer complete flag
jhon309	0:c52df770855b	657	* @arg DMA_FLAG_TEx: Transfer error flag
jhon309	0:c52df770855b	658	* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
jhon309	0:c52df770855b	659	* @retval The state of FLAG (SET or RESET).
jhon309	0:c52df770855b	660	*/
jhon309	0:c52df770855b	661
jhon309	0:c52df770855b	662	#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
jhon309	0:c52df770855b	663	(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
jhon309	0:c52df770855b	664	(DMA1->ISR & (__FLAG__)))
jhon309	0:c52df770855b	665
jhon309	0:c52df770855b	666	/**
jhon309	0:c52df770855b	667	* @brief Clears the DMA Channel pending flags.
jhon309	0:c52df770855b	668	* @param __HANDLE__: DMA handle
jhon309	0:c52df770855b	669	* @param __FLAG__: specifies the flag to clear.
jhon309	0:c52df770855b	670	* This parameter can be any combination of the following values:
jhon309	0:c52df770855b	671	* @arg DMA_FLAG_TCx: Transfer complete flag
jhon309	0:c52df770855b	672	* @arg DMA_FLAG_HTx: Half transfer complete flag
jhon309	0:c52df770855b	673	* @arg DMA_FLAG_TEx: Transfer error flag
jhon309	0:c52df770855b	674	* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
jhon309	0:c52df770855b	675	* @retval None
jhon309	0:c52df770855b	676	*/
jhon309	0:c52df770855b	677	#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
jhon309	0:c52df770855b	678	(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
jhon309	0:c52df770855b	679	(DMA1->IFCR = (__FLAG__)))
jhon309	0:c52df770855b	680
jhon309	0:c52df770855b	681	#else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */
jhon309	0:c52df770855b	682	/**
jhon309	0:c52df770855b	683	* @brief Returns the current DMA Channel transfer complete flag.
jhon309	0:c52df770855b	684	* @param __HANDLE__: DMA handle
jhon309	0:c52df770855b	685	* @retval The specified transfer complete flag index.
jhon309	0:c52df770855b	686	*/
jhon309	0:c52df770855b	687	#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
jhon309	0:c52df770855b	688	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
jhon309	0:c52df770855b	689	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
jhon309	0:c52df770855b	690	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
jhon309	0:c52df770855b	691	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
jhon309	0:c52df770855b	692	DMA_FLAG_TC5)
jhon309	0:c52df770855b	693
jhon309	0:c52df770855b	694	/**
jhon309	0:c52df770855b	695	* @brief Returns the current DMA Channel half transfer complete flag.
jhon309	0:c52df770855b	696	* @param __HANDLE__: DMA handle
jhon309	0:c52df770855b	697	* @retval The specified half transfer complete flag index.
jhon309	0:c52df770855b	698	*/
jhon309	0:c52df770855b	699	#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
jhon309	0:c52df770855b	700	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
jhon309	0:c52df770855b	701	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
jhon309	0:c52df770855b	702	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
jhon309	0:c52df770855b	703	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
jhon309	0:c52df770855b	704	DMA_FLAG_HT5)
jhon309	0:c52df770855b	705
jhon309	0:c52df770855b	706	/**
jhon309	0:c52df770855b	707	* @brief Returns the current DMA Channel transfer error flag.
jhon309	0:c52df770855b	708	* @param __HANDLE__: DMA handle
jhon309	0:c52df770855b	709	* @retval The specified transfer error flag index.
jhon309	0:c52df770855b	710	*/
jhon309	0:c52df770855b	711	#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
jhon309	0:c52df770855b	712	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
jhon309	0:c52df770855b	713	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
jhon309	0:c52df770855b	714	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
jhon309	0:c52df770855b	715	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
jhon309	0:c52df770855b	716	DMA_FLAG_TE5)
jhon309	0:c52df770855b	717
jhon309	0:c52df770855b	718	/**
jhon309	0:c52df770855b	719	* @brief Get the DMA Channel pending flags.
jhon309	0:c52df770855b	720	* @param __HANDLE__: DMA handle
jhon309	0:c52df770855b	721	* @param __FLAG__: Get the specified flag.
jhon309	0:c52df770855b	722	* This parameter can be any combination of the following values:
jhon309	0:c52df770855b	723	* @arg DMA_FLAG_TCx: Transfer complete flag
jhon309	0:c52df770855b	724	* @arg DMA_FLAG_HTx: Half transfer complete flag
jhon309	0:c52df770855b	725	* @arg DMA_FLAG_TEx: Transfer error flag
jhon309	0:c52df770855b	726	* Where x can be 1_5 to select the DMA Channel flag.
jhon309	0:c52df770855b	727	* @retval The state of FLAG (SET or RESET).
jhon309	0:c52df770855b	728	*/
jhon309	0:c52df770855b	729
jhon309	0:c52df770855b	730	#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
jhon309	0:c52df770855b	731
jhon309	0:c52df770855b	732	/**
jhon309	0:c52df770855b	733	* @brief Clears the DMA Channel pending flags.
jhon309	0:c52df770855b	734	* @param __HANDLE__: DMA handle
jhon309	0:c52df770855b	735	* @param __FLAG__: specifies the flag to clear.
jhon309	0:c52df770855b	736	* This parameter can be any combination of the following values:
jhon309	0:c52df770855b	737	* @arg DMA_FLAG_TCx: Transfer complete flag
jhon309	0:c52df770855b	738	* @arg DMA_FLAG_HTx: Half transfer complete flag
jhon309	0:c52df770855b	739	* @arg DMA_FLAG_TEx: Transfer error flag
jhon309	0:c52df770855b	740	* Where x can be 1_5 to select the DMA Channel flag.
jhon309	0:c52df770855b	741	* @retval None
jhon309	0:c52df770855b	742	*/
jhon309	0:c52df770855b	743	#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
jhon309	0:c52df770855b	744
jhon309	0:c52df770855b	745	#endif
jhon309	0:c52df770855b	746
jhon309	0:c52df770855b	747
jhon309	0:c52df770855b	748	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
jhon309	0:c52df770855b	749	#define __HAL_DMA1_REMAP(__REQUEST__) \
jhon309	0:c52df770855b	750	do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__)); \
jhon309	0:c52df770855b	751	DMA1->CSELR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \
jhon309	0:c52df770855b	752	DMA1->CSELR \|= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \
jhon309	0:c52df770855b	753	}while(0)
jhon309	0:c52df770855b	754
jhon309	0:c52df770855b	755	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
jhon309	0:c52df770855b	756	#define __HAL_DMA2_REMAP(__REQUEST__) \
jhon309	0:c52df770855b	757	do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__)); \
jhon309	0:c52df770855b	758	DMA2->CSELR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \
jhon309	0:c52df770855b	759	DMA2->CSELR \|= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \
jhon309	0:c52df770855b	760	}while(0)
jhon309	0:c52df770855b	761	#endif /* STM32F091xC \|\| STM32F098xx */
jhon309	0:c52df770855b	762
jhon309	0:c52df770855b	763	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
jhon309	0:c52df770855b	764
jhon309	0:c52df770855b	765	/**
jhon309	0:c52df770855b	766	* @}
jhon309	0:c52df770855b	767	*/
jhon309	0:c52df770855b	768
jhon309	0:c52df770855b	769	/**
jhon309	0:c52df770855b	770	* @}
jhon309	0:c52df770855b	771	*/
jhon309	0:c52df770855b	772
jhon309	0:c52df770855b	773	/**
jhon309	0:c52df770855b	774	* @}
jhon309	0:c52df770855b	775	*/
jhon309	0:c52df770855b	776
jhon309	0:c52df770855b	777	#ifdef __cplusplus
jhon309	0:c52df770855b	778	}
jhon309	0:c52df770855b	779	#endif
jhon309	0:c52df770855b	780
jhon309	0:c52df770855b	781	#endif /* __STM32F0xx_HAL_DMA_EX_H */
jhon309	0:c52df770855b	782
jhon309	0:c52df770855b	783	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	13 Aug 2015
Imports:	191
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	5

TARGET_NUCLEO_F072RB/stm32f0xx_hal_dma_ex.h@0:c52df770855b, 2015-08-13 (annotated)

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