Jhon Plantikow / DHT11

DHT11

TARGET_NUCLEO_F072RB/stm32f0xx_hal_dma.h@0:c52df770855b, 2015-08-13 (annotated)

Committer:
jhon309
Date:
Thu Aug 13 00:21:57 2015 +0000
Revision:
0:c52df770855b
DHT11

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jhon309 0:c52df770855b 1 /**
jhon309 0:c52df770855b 2 ******************************************************************************
jhon309 0:c52df770855b 3 * @file stm32f0xx_hal_dma.h
jhon309 0:c52df770855b 4 * @author MCD Application Team
jhon309 0:c52df770855b 5 * @version V1.2.0
jhon309 0:c52df770855b 6 * @date 11-December-2014
jhon309 0:c52df770855b 7 * @brief Header file of DMA HAL module.
jhon309 0:c52df770855b 8 ******************************************************************************
jhon309 0:c52df770855b 9 * @attention
jhon309 0:c52df770855b 10 *
jhon309 0:c52df770855b 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
jhon309 0:c52df770855b 12 *
jhon309 0:c52df770855b 13 * Redistribution and use in source and binary forms, with or without modification,
jhon309 0:c52df770855b 14 * are permitted provided that the following conditions are met:
jhon309 0:c52df770855b 15 * 1. Redistributions of source code must retain the above copyright notice,
jhon309 0:c52df770855b 16 * this list of conditions and the following disclaimer.
jhon309 0:c52df770855b 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
jhon309 0:c52df770855b 18 * this list of conditions and the following disclaimer in the documentation
jhon309 0:c52df770855b 19 * and/or other materials provided with the distribution.
jhon309 0:c52df770855b 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
jhon309 0:c52df770855b 21 * may be used to endorse or promote products derived from this software
jhon309 0:c52df770855b 22 * without specific prior written permission.
jhon309 0:c52df770855b 23 *
jhon309 0:c52df770855b 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jhon309 0:c52df770855b 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jhon309 0:c52df770855b 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
jhon309 0:c52df770855b 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
jhon309 0:c52df770855b 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
jhon309 0:c52df770855b 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
jhon309 0:c52df770855b 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
jhon309 0:c52df770855b 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
jhon309 0:c52df770855b 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
jhon309 0:c52df770855b 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
jhon309 0:c52df770855b 34 *
jhon309 0:c52df770855b 35 ******************************************************************************
jhon309 0:c52df770855b 36 */
jhon309 0:c52df770855b 37
jhon309 0:c52df770855b 38 /* Define to prevent recursive inclusion -------------------------------------*/
jhon309 0:c52df770855b 39 #ifndef __STM32F0xx_HAL_DMA_H
jhon309 0:c52df770855b 40 #define __STM32F0xx_HAL_DMA_H
jhon309 0:c52df770855b 41
jhon309 0:c52df770855b 42 #ifdef __cplusplus
jhon309 0:c52df770855b 43 extern "C" {
jhon309 0:c52df770855b 44 #endif
jhon309 0:c52df770855b 45
jhon309 0:c52df770855b 46 /* Includes ------------------------------------------------------------------*/
jhon309 0:c52df770855b 47 #include "stm32f0xx_hal_def.h"
jhon309 0:c52df770855b 48
jhon309 0:c52df770855b 49 /** @addtogroup STM32F0xx_HAL_Driver
jhon309 0:c52df770855b 50 * @{
jhon309 0:c52df770855b 51 */
jhon309 0:c52df770855b 52
jhon309 0:c52df770855b 53 /** @addtogroup DMA
jhon309 0:c52df770855b 54 * @{
jhon309 0:c52df770855b 55 */
jhon309 0:c52df770855b 56
jhon309 0:c52df770855b 57 /* Exported types ------------------------------------------------------------*/
jhon309 0:c52df770855b 58 /** @defgroup DMA_Exported_Types DMA Exported Types
jhon309 0:c52df770855b 59 * @{
jhon309 0:c52df770855b 60 */
jhon309 0:c52df770855b 61
jhon309 0:c52df770855b 62 /**
jhon309 0:c52df770855b 63 * @brief DMA Configuration Structure definition
jhon309 0:c52df770855b 64 */
jhon309 0:c52df770855b 65 typedef struct
jhon309 0:c52df770855b 66 {
jhon309 0:c52df770855b 67 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
jhon309 0:c52df770855b 68 from memory to memory or from peripheral to memory.
jhon309 0:c52df770855b 69 This parameter can be a value of @ref DMA_Data_transfer_direction */
jhon309 0:c52df770855b 70
jhon309 0:c52df770855b 71 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
jhon309 0:c52df770855b 72 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
jhon309 0:c52df770855b 73
jhon309 0:c52df770855b 74 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
jhon309 0:c52df770855b 75 This parameter can be a value of @ref DMA_Memory_incremented_mode */
jhon309 0:c52df770855b 76
jhon309 0:c52df770855b 77 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
jhon309 0:c52df770855b 78 This parameter can be a value of @ref DMA_Peripheral_data_size */
jhon309 0:c52df770855b 79
jhon309 0:c52df770855b 80 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
jhon309 0:c52df770855b 81 This parameter can be a value of @ref DMA_Memory_data_size */
jhon309 0:c52df770855b 82
jhon309 0:c52df770855b 83 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
jhon309 0:c52df770855b 84 This parameter can be a value of @ref DMA_mode
jhon309 0:c52df770855b 85 @note The circular buffer mode cannot be used if the memory-to-memory
jhon309 0:c52df770855b 86 data transfer is configured on the selected Channel */
jhon309 0:c52df770855b 87
jhon309 0:c52df770855b 88 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
jhon309 0:c52df770855b 89 This parameter can be a value of @ref DMA_Priority_level */
jhon309 0:c52df770855b 90
jhon309 0:c52df770855b 91 } DMA_InitTypeDef;
jhon309 0:c52df770855b 92
jhon309 0:c52df770855b 93 /**
jhon309 0:c52df770855b 94 * @brief DMA Configuration enumeration values definition
jhon309 0:c52df770855b 95 */
jhon309 0:c52df770855b 96 typedef enum
jhon309 0:c52df770855b 97 {
jhon309 0:c52df770855b 98 DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
jhon309 0:c52df770855b 99 DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
jhon309 0:c52df770855b 100
jhon309 0:c52df770855b 101 } DMA_ControlTypeDef;
jhon309 0:c52df770855b 102
jhon309 0:c52df770855b 103 /**
jhon309 0:c52df770855b 104 * @brief HAL DMA State structures definition
jhon309 0:c52df770855b 105 */
jhon309 0:c52df770855b 106 typedef enum
jhon309 0:c52df770855b 107 {
jhon309 0:c52df770855b 108 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
jhon309 0:c52df770855b 109 HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
jhon309 0:c52df770855b 110 HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
jhon309 0:c52df770855b 111 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
jhon309 0:c52df770855b 112 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
jhon309 0:c52df770855b 113 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
jhon309 0:c52df770855b 114
jhon309 0:c52df770855b 115 }HAL_DMA_StateTypeDef;
jhon309 0:c52df770855b 116
jhon309 0:c52df770855b 117 /**
jhon309 0:c52df770855b 118 * @brief HAL DMA Error Code structure definition
jhon309 0:c52df770855b 119 */
jhon309 0:c52df770855b 120 typedef enum
jhon309 0:c52df770855b 121 {
jhon309 0:c52df770855b 122 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
jhon309 0:c52df770855b 123 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
jhon309 0:c52df770855b 124
jhon309 0:c52df770855b 125 }HAL_DMA_LevelCompleteTypeDef;
jhon309 0:c52df770855b 126
jhon309 0:c52df770855b 127
jhon309 0:c52df770855b 128 /**
jhon309 0:c52df770855b 129 * @brief DMA handle Structure definition
jhon309 0:c52df770855b 130 */
jhon309 0:c52df770855b 131 typedef struct __DMA_HandleTypeDef
jhon309 0:c52df770855b 132 {
jhon309 0:c52df770855b 133 DMA_Channel_TypeDef *Instance; /*!< Register base address */
jhon309 0:c52df770855b 134
jhon309 0:c52df770855b 135 DMA_InitTypeDef Init; /*!< DMA communication parameters */
jhon309 0:c52df770855b 136
jhon309 0:c52df770855b 137 HAL_LockTypeDef Lock; /*!< DMA locking object */
jhon309 0:c52df770855b 138
jhon309 0:c52df770855b 139 HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
jhon309 0:c52df770855b 140
jhon309 0:c52df770855b 141 void *Parent; /*!< Parent object state */
jhon309 0:c52df770855b 142
jhon309 0:c52df770855b 143 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
jhon309 0:c52df770855b 144
jhon309 0:c52df770855b 145 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
jhon309 0:c52df770855b 146
jhon309 0:c52df770855b 147 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
jhon309 0:c52df770855b 148
jhon309 0:c52df770855b 149 __IO uint32_t ErrorCode; /*!< DMA Error code */
jhon309 0:c52df770855b 150
jhon309 0:c52df770855b 151 } DMA_HandleTypeDef;
jhon309 0:c52df770855b 152 /**
jhon309 0:c52df770855b 153 * @}
jhon309 0:c52df770855b 154 */
jhon309 0:c52df770855b 155
jhon309 0:c52df770855b 156 /* Exported constants --------------------------------------------------------*/
jhon309 0:c52df770855b 157 /** @defgroup DMA_Exported_Constants DMA Exported Constants
jhon309 0:c52df770855b 158 * @{
jhon309 0:c52df770855b 159 */
jhon309 0:c52df770855b 160
jhon309 0:c52df770855b 161 /** @defgroup DMA_Error_Code DMA Error Code
jhon309 0:c52df770855b 162 * @{
jhon309 0:c52df770855b 163 */
jhon309 0:c52df770855b 164 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
jhon309 0:c52df770855b 165 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
jhon309 0:c52df770855b 166 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
jhon309 0:c52df770855b 167 /**
jhon309 0:c52df770855b 168 * @}
jhon309 0:c52df770855b 169 */
jhon309 0:c52df770855b 170
jhon309 0:c52df770855b 171 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
jhon309 0:c52df770855b 172 * @{
jhon309 0:c52df770855b 173 */
jhon309 0:c52df770855b 174 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
jhon309 0:c52df770855b 175 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
jhon309 0:c52df770855b 176 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
jhon309 0:c52df770855b 177
jhon309 0:c52df770855b 178 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
jhon309 0:c52df770855b 179 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
jhon309 0:c52df770855b 180 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
jhon309 0:c52df770855b 181 /**
jhon309 0:c52df770855b 182 * @}
jhon309 0:c52df770855b 183 */
jhon309 0:c52df770855b 184
jhon309 0:c52df770855b 185 /** @defgroup DMA_Data_buffer_size DMA Data buffer size
jhon309 0:c52df770855b 186 * @{
jhon309 0:c52df770855b 187 */
jhon309 0:c52df770855b 188 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
jhon309 0:c52df770855b 189 /**
jhon309 0:c52df770855b 190 * @}
jhon309 0:c52df770855b 191 */
jhon309 0:c52df770855b 192
jhon309 0:c52df770855b 193 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
jhon309 0:c52df770855b 194 * @{
jhon309 0:c52df770855b 195 */
jhon309 0:c52df770855b 196 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
jhon309 0:c52df770855b 197 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
jhon309 0:c52df770855b 198
jhon309 0:c52df770855b 199 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
jhon309 0:c52df770855b 200 ((STATE) == DMA_PINC_DISABLE))
jhon309 0:c52df770855b 201 /**
jhon309 0:c52df770855b 202 * @}
jhon309 0:c52df770855b 203 */
jhon309 0:c52df770855b 204
jhon309 0:c52df770855b 205 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
jhon309 0:c52df770855b 206 * @{
jhon309 0:c52df770855b 207 */
jhon309 0:c52df770855b 208 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
jhon309 0:c52df770855b 209 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
jhon309 0:c52df770855b 210
jhon309 0:c52df770855b 211 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
jhon309 0:c52df770855b 212 ((STATE) == DMA_MINC_DISABLE))
jhon309 0:c52df770855b 213 /**
jhon309 0:c52df770855b 214 * @}
jhon309 0:c52df770855b 215 */
jhon309 0:c52df770855b 216
jhon309 0:c52df770855b 217 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
jhon309 0:c52df770855b 218 * @{
jhon309 0:c52df770855b 219 */
jhon309 0:c52df770855b 220 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
jhon309 0:c52df770855b 221 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
jhon309 0:c52df770855b 222 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
jhon309 0:c52df770855b 223
jhon309 0:c52df770855b 224 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
jhon309 0:c52df770855b 225 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
jhon309 0:c52df770855b 226 ((SIZE) == DMA_PDATAALIGN_WORD))
jhon309 0:c52df770855b 227 /**
jhon309 0:c52df770855b 228 * @}
jhon309 0:c52df770855b 229 */
jhon309 0:c52df770855b 230
jhon309 0:c52df770855b 231
jhon309 0:c52df770855b 232 /** @defgroup DMA_Memory_data_size DMA Memory data size
jhon309 0:c52df770855b 233 * @{
jhon309 0:c52df770855b 234 */
jhon309 0:c52df770855b 235 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
jhon309 0:c52df770855b 236 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
jhon309 0:c52df770855b 237 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
jhon309 0:c52df770855b 238
jhon309 0:c52df770855b 239 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
jhon309 0:c52df770855b 240 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
jhon309 0:c52df770855b 241 ((SIZE) == DMA_MDATAALIGN_WORD ))
jhon309 0:c52df770855b 242 /**
jhon309 0:c52df770855b 243 * @}
jhon309 0:c52df770855b 244 */
jhon309 0:c52df770855b 245
jhon309 0:c52df770855b 246 /** @defgroup DMA_mode DMA mode
jhon309 0:c52df770855b 247 * @{
jhon309 0:c52df770855b 248 */
jhon309 0:c52df770855b 249 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
jhon309 0:c52df770855b 250 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
jhon309 0:c52df770855b 251
jhon309 0:c52df770855b 252 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
jhon309 0:c52df770855b 253 ((MODE) == DMA_CIRCULAR))
jhon309 0:c52df770855b 254 /**
jhon309 0:c52df770855b 255 * @}
jhon309 0:c52df770855b 256 */
jhon309 0:c52df770855b 257
jhon309 0:c52df770855b 258 /** @defgroup DMA_Priority_level DMA Priority level
jhon309 0:c52df770855b 259 * @{
jhon309 0:c52df770855b 260 */
jhon309 0:c52df770855b 261 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
jhon309 0:c52df770855b 262 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
jhon309 0:c52df770855b 263 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
jhon309 0:c52df770855b 264 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
jhon309 0:c52df770855b 265
jhon309 0:c52df770855b 266 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
jhon309 0:c52df770855b 267 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
jhon309 0:c52df770855b 268 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
jhon309 0:c52df770855b 269 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
jhon309 0:c52df770855b 270 /**
jhon309 0:c52df770855b 271 * @}
jhon309 0:c52df770855b 272 */
jhon309 0:c52df770855b 273
jhon309 0:c52df770855b 274
jhon309 0:c52df770855b 275 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
jhon309 0:c52df770855b 276 * @{
jhon309 0:c52df770855b 277 */
jhon309 0:c52df770855b 278
jhon309 0:c52df770855b 279 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
jhon309 0:c52df770855b 280 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
jhon309 0:c52df770855b 281 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
jhon309 0:c52df770855b 282
jhon309 0:c52df770855b 283 /**
jhon309 0:c52df770855b 284 * @}
jhon309 0:c52df770855b 285 */
jhon309 0:c52df770855b 286
jhon309 0:c52df770855b 287 /** @defgroup DMA_flag_definitions DMA flag definitions
jhon309 0:c52df770855b 288 * @{
jhon309 0:c52df770855b 289 */
jhon309 0:c52df770855b 290
jhon309 0:c52df770855b 291 #define DMA_FLAG_GL1 ((uint32_t)0x00000001) /*!< Channel 1 global interrupt flag */
jhon309 0:c52df770855b 292 #define DMA_FLAG_TC1 ((uint32_t)0x00000002) /*!< Channel 1 transfer complete flag */
jhon309 0:c52df770855b 293 #define DMA_FLAG_HT1 ((uint32_t)0x00000004) /*!< Channel 1 half transfer flag */
jhon309 0:c52df770855b 294 #define DMA_FLAG_TE1 ((uint32_t)0x00000008) /*!< Channel 1 transfer error flag */
jhon309 0:c52df770855b 295 #define DMA_FLAG_GL2 ((uint32_t)0x00000010) /*!< Channel 2 global interrupt flag */
jhon309 0:c52df770855b 296 #define DMA_FLAG_TC2 ((uint32_t)0x00000020) /*!< Channel 2 transfer complete flag */
jhon309 0:c52df770855b 297 #define DMA_FLAG_HT2 ((uint32_t)0x00000040) /*!< Channel 2 half transfer flag */
jhon309 0:c52df770855b 298 #define DMA_FLAG_TE2 ((uint32_t)0x00000080) /*!< Channel 2 transfer error flag */
jhon309 0:c52df770855b 299 #define DMA_FLAG_GL3 ((uint32_t)0x00000100) /*!< Channel 3 global interrupt flag */
jhon309 0:c52df770855b 300 #define DMA_FLAG_TC3 ((uint32_t)0x00000200) /*!< Channel 3 transfer complete flag */
jhon309 0:c52df770855b 301 #define DMA_FLAG_HT3 ((uint32_t)0x00000400) /*!< Channel 3 half transfer flag */
jhon309 0:c52df770855b 302 #define DMA_FLAG_TE3 ((uint32_t)0x00000800) /*!< Channel 3 transfer error flag */
jhon309 0:c52df770855b 303 #define DMA_FLAG_GL4 ((uint32_t)0x00001000) /*!< Channel 4 global interrupt flag */
jhon309 0:c52df770855b 304 #define DMA_FLAG_TC4 ((uint32_t)0x00002000) /*!< Channel 4 transfer complete flag */
jhon309 0:c52df770855b 305 #define DMA_FLAG_HT4 ((uint32_t)0x00004000) /*!< Channel 4 half transfer flag */
jhon309 0:c52df770855b 306 #define DMA_FLAG_TE4 ((uint32_t)0x00008000) /*!< Channel 4 transfer error flag */
jhon309 0:c52df770855b 307 #define DMA_FLAG_GL5 ((uint32_t)0x00010000) /*!< Channel 5 global interrupt flag */
jhon309 0:c52df770855b 308 #define DMA_FLAG_TC5 ((uint32_t)0x00020000) /*!< Channel 5 transfer complete flag */
jhon309 0:c52df770855b 309 #define DMA_FLAG_HT5 ((uint32_t)0x00040000) /*!< Channel 5 half transfer flag */
jhon309 0:c52df770855b 310 #define DMA_FLAG_TE5 ((uint32_t)0x00080000) /*!< Channel 5 transfer error flag */
jhon309 0:c52df770855b 311 #define DMA_FLAG_GL6 ((uint32_t)0x00100000) /*!< Channel 6 global interrupt flag */
jhon309 0:c52df770855b 312 #define DMA_FLAG_TC6 ((uint32_t)0x00200000) /*!< Channel 6 transfer complete flag */
jhon309 0:c52df770855b 313 #define DMA_FLAG_HT6 ((uint32_t)0x00400000) /*!< Channel 6 half transfer flag */
jhon309 0:c52df770855b 314 #define DMA_FLAG_TE6 ((uint32_t)0x00800000) /*!< Channel 6 transfer error flag */
jhon309 0:c52df770855b 315 #define DMA_FLAG_GL7 ((uint32_t)0x01000000) /*!< Channel 7 global interrupt flag */
jhon309 0:c52df770855b 316 #define DMA_FLAG_TC7 ((uint32_t)0x02000000) /*!< Channel 7 transfer complete flag */
jhon309 0:c52df770855b 317 #define DMA_FLAG_HT7 ((uint32_t)0x04000000) /*!< Channel 7 half transfer flag */
jhon309 0:c52df770855b 318 #define DMA_FLAG_TE7 ((uint32_t)0x08000000) /*!< Channel 7 transfer error flag */
jhon309 0:c52df770855b 319
jhon309 0:c52df770855b 320
jhon309 0:c52df770855b 321 /**
jhon309 0:c52df770855b 322 * @}
jhon309 0:c52df770855b 323 */
jhon309 0:c52df770855b 324
jhon309 0:c52df770855b 325 /**
jhon309 0:c52df770855b 326 * @}
jhon309 0:c52df770855b 327 */
jhon309 0:c52df770855b 328
jhon309 0:c52df770855b 329 /* Exported macros -----------------------------------------------------------*/
jhon309 0:c52df770855b 330 /** @defgroup DMA_Exported_Macros DMA Exported Macros
jhon309 0:c52df770855b 331 * @{
jhon309 0:c52df770855b 332 */
jhon309 0:c52df770855b 333
jhon309 0:c52df770855b 334 /** @brief Reset DMA handle state
jhon309 0:c52df770855b 335 * @param __HANDLE__: DMA handle.
jhon309 0:c52df770855b 336 * @retval None
jhon309 0:c52df770855b 337 */
jhon309 0:c52df770855b 338 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
jhon309 0:c52df770855b 339
jhon309 0:c52df770855b 340 /**
jhon309 0:c52df770855b 341 * @brief Enable the specified DMA Channel.
jhon309 0:c52df770855b 342 * @param __HANDLE__: DMA handle
jhon309 0:c52df770855b 343 * @retval None.
jhon309 0:c52df770855b 344 */
jhon309 0:c52df770855b 345 #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
jhon309 0:c52df770855b 346
jhon309 0:c52df770855b 347 /**
jhon309 0:c52df770855b 348 * @brief Disable the specified DMA Channel.
jhon309 0:c52df770855b 349 * @param __HANDLE__: DMA handle
jhon309 0:c52df770855b 350 * @retval None.
jhon309 0:c52df770855b 351 */
jhon309 0:c52df770855b 352 #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
jhon309 0:c52df770855b 353
jhon309 0:c52df770855b 354
jhon309 0:c52df770855b 355 /* Interrupt & Flag management */
jhon309 0:c52df770855b 356
jhon309 0:c52df770855b 357 /**
jhon309 0:c52df770855b 358 * @brief Enables the specified DMA Channel interrupts.
jhon309 0:c52df770855b 359 * @param __HANDLE__: DMA handle
jhon309 0:c52df770855b 360 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
jhon309 0:c52df770855b 361 * This parameter can be any combination of the following values:
jhon309 0:c52df770855b 362 * @arg DMA_IT_TC: Transfer complete interrupt mask
jhon309 0:c52df770855b 363 * @arg DMA_IT_HT: Half transfer complete interrupt mask
jhon309 0:c52df770855b 364 * @arg DMA_IT_TE: Transfer error interrupt mask
jhon309 0:c52df770855b 365 * @retval None
jhon309 0:c52df770855b 366 */
jhon309 0:c52df770855b 367 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
jhon309 0:c52df770855b 368
jhon309 0:c52df770855b 369 /**
jhon309 0:c52df770855b 370 * @brief Disables the specified DMA Channel interrupts.
jhon309 0:c52df770855b 371 * @param __HANDLE__: DMA handle
jhon309 0:c52df770855b 372 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
jhon309 0:c52df770855b 373 * This parameter can be any combination of the following values:
jhon309 0:c52df770855b 374 * @arg DMA_IT_TC: Transfer complete interrupt mask
jhon309 0:c52df770855b 375 * @arg DMA_IT_HT: Half transfer complete interrupt mask
jhon309 0:c52df770855b 376 * @arg DMA_IT_TE: Transfer error interrupt mask
jhon309 0:c52df770855b 377 * @retval None
jhon309 0:c52df770855b 378 */
jhon309 0:c52df770855b 379 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
jhon309 0:c52df770855b 380
jhon309 0:c52df770855b 381 /**
jhon309 0:c52df770855b 382 * @brief Checks whether the specified DMA Channel interrupt has occurred or not.
jhon309 0:c52df770855b 383 * @param __HANDLE__: DMA handle
jhon309 0:c52df770855b 384 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
jhon309 0:c52df770855b 385 * This parameter can be one of the following values:
jhon309 0:c52df770855b 386 * @arg DMA_IT_TC: Transfer complete interrupt mask
jhon309 0:c52df770855b 387 * @arg DMA_IT_HT: Half transfer complete interrupt mask
jhon309 0:c52df770855b 388 * @arg DMA_IT_TE: Transfer error interrupt mask
jhon309 0:c52df770855b 389 * @retval The state of DMA_IT (SET or RESET).
jhon309 0:c52df770855b 390 */
jhon309 0:c52df770855b 391 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
jhon309 0:c52df770855b 392
jhon309 0:c52df770855b 393 /**
jhon309 0:c52df770855b 394 * @}
jhon309 0:c52df770855b 395 */
jhon309 0:c52df770855b 396
jhon309 0:c52df770855b 397 /* Include DMA HAL Extension module */
jhon309 0:c52df770855b 398 #include "stm32f0xx_hal_dma_ex.h"
jhon309 0:c52df770855b 399
jhon309 0:c52df770855b 400 /* Exported functions --------------------------------------------------------*/
jhon309 0:c52df770855b 401 /** @addtogroup DMA_Exported_Functions DMA Exported Functions
jhon309 0:c52df770855b 402 * @{
jhon309 0:c52df770855b 403 */
jhon309 0:c52df770855b 404 /** @addtogroup DMA_Exported_Functions_Group1
jhon309 0:c52df770855b 405 * @brief Initialization and de-initialization functions
jhon309 0:c52df770855b 406 * @{
jhon309 0:c52df770855b 407 */
jhon309 0:c52df770855b 408 /* Initialization and de-initialization functions *****************************/
jhon309 0:c52df770855b 409 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
jhon309 0:c52df770855b 410 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
jhon309 0:c52df770855b 411 /**
jhon309 0:c52df770855b 412 * @}
jhon309 0:c52df770855b 413 */
jhon309 0:c52df770855b 414
jhon309 0:c52df770855b 415 /** @addtogroup DMA_Exported_Functions_Group2
jhon309 0:c52df770855b 416 * @brief I/O operation functions
jhon309 0:c52df770855b 417 * @{
jhon309 0:c52df770855b 418 */
jhon309 0:c52df770855b 419 /* IO operation functions *****************************************************/
jhon309 0:c52df770855b 420 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
jhon309 0:c52df770855b 421 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
jhon309 0:c52df770855b 422 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
jhon309 0:c52df770855b 423 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
jhon309 0:c52df770855b 424 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
jhon309 0:c52df770855b 425 /**
jhon309 0:c52df770855b 426 * @}
jhon309 0:c52df770855b 427 */
jhon309 0:c52df770855b 428
jhon309 0:c52df770855b 429 /* Peripheral State and Error functions ***************************************/
jhon309 0:c52df770855b 430 /** @addtogroup DMA_Exported_Functions_Group3
jhon309 0:c52df770855b 431 * @brief Peripheral State functions
jhon309 0:c52df770855b 432 * @{
jhon309 0:c52df770855b 433 */
jhon309 0:c52df770855b 434 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
jhon309 0:c52df770855b 435 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
jhon309 0:c52df770855b 436 /**
jhon309 0:c52df770855b 437 * @}
jhon309 0:c52df770855b 438 */
jhon309 0:c52df770855b 439
jhon309 0:c52df770855b 440 /**
jhon309 0:c52df770855b 441 * @}
jhon309 0:c52df770855b 442 */
jhon309 0:c52df770855b 443
jhon309 0:c52df770855b 444 /**
jhon309 0:c52df770855b 445 * @}
jhon309 0:c52df770855b 446 */
jhon309 0:c52df770855b 447
jhon309 0:c52df770855b 448 /**
jhon309 0:c52df770855b 449 * @}
jhon309 0:c52df770855b 450 */
jhon309 0:c52df770855b 451
jhon309 0:c52df770855b 452 #ifdef __cplusplus
jhon309 0:c52df770855b 453 }
jhon309 0:c52df770855b 454 #endif
jhon309 0:c52df770855b 455
jhon309 0:c52df770855b 456 #endif /* __STM32F0xx_HAL_DMA_H */
jhon309 0:c52df770855b 457
jhon309 0:c52df770855b 458 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
jhon309 0:c52df770855b 459