Jhon Plantikow / DHT11

DHT11

TARGET_NUCLEO_F072RB/stm32f072xb.h@0:c52df770855b, 2015-08-13 (annotated)

Committer:
jhon309
Date:
Thu Aug 13 00:21:57 2015 +0000
Revision:
0:c52df770855b
DHT11

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jhon309 0:c52df770855b 1 /**
jhon309 0:c52df770855b 2 ******************************************************************************
jhon309 0:c52df770855b 3 * @file stm32f072xb.h
jhon309 0:c52df770855b 4 * @author MCD Application Team
jhon309 0:c52df770855b 5 * @version V2.2.0
jhon309 0:c52df770855b 6 * @date 05-December-2014
jhon309 0:c52df770855b 7 * @brief CMSIS STM32F072x8/STM32F072xB devices Peripheral Access Layer Header File.
jhon309 0:c52df770855b 8 *
jhon309 0:c52df770855b 9 * This file contains:
jhon309 0:c52df770855b 10 * - Data structures and the address mapping for all peripherals
jhon309 0:c52df770855b 11 * - Peripheral's registers declarations and bits definition
jhon309 0:c52df770855b 12 * - Macros to access peripheral’s registers hardware
jhon309 0:c52df770855b 13 *
jhon309 0:c52df770855b 14 ******************************************************************************
jhon309 0:c52df770855b 15 * @attention
jhon309 0:c52df770855b 16 *
jhon309 0:c52df770855b 17 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
jhon309 0:c52df770855b 18 *
jhon309 0:c52df770855b 19 * Redistribution and use in source and binary forms, with or without modification,
jhon309 0:c52df770855b 20 * are permitted provided that the following conditions are met:
jhon309 0:c52df770855b 21 * 1. Redistributions of source code must retain the above copyright notice,
jhon309 0:c52df770855b 22 * this list of conditions and the following disclaimer.
jhon309 0:c52df770855b 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
jhon309 0:c52df770855b 24 * this list of conditions and the following disclaimer in the documentation
jhon309 0:c52df770855b 25 * and/or other materials provided with the distribution.
jhon309 0:c52df770855b 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
jhon309 0:c52df770855b 27 * may be used to endorse or promote products derived from this software
jhon309 0:c52df770855b 28 * without specific prior written permission.
jhon309 0:c52df770855b 29 *
jhon309 0:c52df770855b 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jhon309 0:c52df770855b 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jhon309 0:c52df770855b 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
jhon309 0:c52df770855b 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
jhon309 0:c52df770855b 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
jhon309 0:c52df770855b 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
jhon309 0:c52df770855b 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
jhon309 0:c52df770855b 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
jhon309 0:c52df770855b 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
jhon309 0:c52df770855b 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
jhon309 0:c52df770855b 40 *
jhon309 0:c52df770855b 41 ******************************************************************************
jhon309 0:c52df770855b 42 */
jhon309 0:c52df770855b 43
jhon309 0:c52df770855b 44 /** @addtogroup CMSIS_Device
jhon309 0:c52df770855b 45 * @{
jhon309 0:c52df770855b 46 */
jhon309 0:c52df770855b 47
jhon309 0:c52df770855b 48 /** @addtogroup stm32f072xb
jhon309 0:c52df770855b 49 * @{
jhon309 0:c52df770855b 50 */
jhon309 0:c52df770855b 51
jhon309 0:c52df770855b 52 #ifndef __STM32F072xB_H
jhon309 0:c52df770855b 53 #define __STM32F072xB_H
jhon309 0:c52df770855b 54
jhon309 0:c52df770855b 55 #ifdef __cplusplus
jhon309 0:c52df770855b 56 extern "C" {
jhon309 0:c52df770855b 57 #endif /* __cplusplus */
jhon309 0:c52df770855b 58
jhon309 0:c52df770855b 59 /** @addtogroup Configuration_section_for_CMSIS
jhon309 0:c52df770855b 60 * @{
jhon309 0:c52df770855b 61 */
jhon309 0:c52df770855b 62
jhon309 0:c52df770855b 63 /**
jhon309 0:c52df770855b 64 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
jhon309 0:c52df770855b 65 */
jhon309 0:c52df770855b 66 #define __CM0_REV 0 /*!< Core Revision r0p0 */
jhon309 0:c52df770855b 67 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
jhon309 0:c52df770855b 68 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
jhon309 0:c52df770855b 69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
jhon309 0:c52df770855b 70
jhon309 0:c52df770855b 71 /**
jhon309 0:c52df770855b 72 * @}
jhon309 0:c52df770855b 73 */
jhon309 0:c52df770855b 74
jhon309 0:c52df770855b 75 /** @addtogroup Peripheral_interrupt_number_definition
jhon309 0:c52df770855b 76 * @{
jhon309 0:c52df770855b 77 */
jhon309 0:c52df770855b 78
jhon309 0:c52df770855b 79 /**
jhon309 0:c52df770855b 80 * @brief STM32F072x8/STM32F072xB device Interrupt Number Definition
jhon309 0:c52df770855b 81 */
jhon309 0:c52df770855b 82 typedef enum
jhon309 0:c52df770855b 83 {
jhon309 0:c52df770855b 84 /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
jhon309 0:c52df770855b 85 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
jhon309 0:c52df770855b 86 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
jhon309 0:c52df770855b 87 SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
jhon309 0:c52df770855b 88 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
jhon309 0:c52df770855b 89 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
jhon309 0:c52df770855b 90
jhon309 0:c52df770855b 91 /****** STM32F072x8/STM32F072xB specific Interrupt Numbers **************************************************/
jhon309 0:c52df770855b 92 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
jhon309 0:c52df770855b 93 PVD_VDDIO2_IRQn = 1, /*!< PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31 */
jhon309 0:c52df770855b 94 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
jhon309 0:c52df770855b 95 FLASH_IRQn = 3, /*!< FLASH global Interrupt */
jhon309 0:c52df770855b 96 RCC_CRS_IRQn = 4, /*!< RCC & CRS global Interrupts */
jhon309 0:c52df770855b 97 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
jhon309 0:c52df770855b 98 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
jhon309 0:c52df770855b 99 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
jhon309 0:c52df770855b 100 TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */
jhon309 0:c52df770855b 101 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
jhon309 0:c52df770855b 102 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
jhon309 0:c52df770855b 103 DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 Interrupts */
jhon309 0:c52df770855b 104 ADC1_COMP_IRQn = 12, /*!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */
jhon309 0:c52df770855b 105 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
jhon309 0:c52df770855b 106 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
jhon309 0:c52df770855b 107 TIM2_IRQn = 15, /*!< TIM2 global Interrupt */
jhon309 0:c52df770855b 108 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
jhon309 0:c52df770855b 109 TIM6_DAC_IRQn = 17, /*!< TIM6 global and DAC channel underrun error Interrupts */
jhon309 0:c52df770855b 110 TIM7_IRQn = 18, /*!< TIM7 global Interrupt */
jhon309 0:c52df770855b 111 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
jhon309 0:c52df770855b 112 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
jhon309 0:c52df770855b 113 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
jhon309 0:c52df770855b 114 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
jhon309 0:c52df770855b 115 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
jhon309 0:c52df770855b 116 I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */
jhon309 0:c52df770855b 117 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
jhon309 0:c52df770855b 118 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
jhon309 0:c52df770855b 119 USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
jhon309 0:c52df770855b 120 USART2_IRQn = 28, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
jhon309 0:c52df770855b 121 USART3_4_IRQn = 29, /*!< USART3 and USART4 global Interrupts */
jhon309 0:c52df770855b 122 CEC_CAN_IRQn = 30, /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */
jhon309 0:c52df770855b 123 USB_IRQn = 31 /*!< USB global Interrupts & EXTI Line18 Interrupt */
jhon309 0:c52df770855b 124 } IRQn_Type;
jhon309 0:c52df770855b 125
jhon309 0:c52df770855b 126 /**
jhon309 0:c52df770855b 127 * @}
jhon309 0:c52df770855b 128 */
jhon309 0:c52df770855b 129
jhon309 0:c52df770855b 130 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
jhon309 0:c52df770855b 131 #include "system_stm32f0xx.h" /* STM32F0xx System Header */
jhon309 0:c52df770855b 132 #include <stdint.h>
jhon309 0:c52df770855b 133
jhon309 0:c52df770855b 134 /** @addtogroup Peripheral_registers_structures
jhon309 0:c52df770855b 135 * @{
jhon309 0:c52df770855b 136 */
jhon309 0:c52df770855b 137
jhon309 0:c52df770855b 138 /**
jhon309 0:c52df770855b 139 * @brief Analog to Digital Converter
jhon309 0:c52df770855b 140 */
jhon309 0:c52df770855b 141
jhon309 0:c52df770855b 142 typedef struct
jhon309 0:c52df770855b 143 {
jhon309 0:c52df770855b 144 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
jhon309 0:c52df770855b 145 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
jhon309 0:c52df770855b 146 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
jhon309 0:c52df770855b 147 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
jhon309 0:c52df770855b 148 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
jhon309 0:c52df770855b 149 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
jhon309 0:c52df770855b 150 uint32_t RESERVED1; /*!< Reserved, 0x18 */
jhon309 0:c52df770855b 151 uint32_t RESERVED2; /*!< Reserved, 0x1C */
jhon309 0:c52df770855b 152 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
jhon309 0:c52df770855b 153 uint32_t RESERVED3; /*!< Reserved, 0x24 */
jhon309 0:c52df770855b 154 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
jhon309 0:c52df770855b 155 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
jhon309 0:c52df770855b 156 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
jhon309 0:c52df770855b 157 }ADC_TypeDef;
jhon309 0:c52df770855b 158
jhon309 0:c52df770855b 159 typedef struct
jhon309 0:c52df770855b 160 {
jhon309 0:c52df770855b 161 __IO uint32_t CCR;
jhon309 0:c52df770855b 162 }ADC_Common_TypeDef;
jhon309 0:c52df770855b 163
jhon309 0:c52df770855b 164 /**
jhon309 0:c52df770855b 165 * @brief Controller Area Network TxMailBox
jhon309 0:c52df770855b 166 */
jhon309 0:c52df770855b 167 typedef struct
jhon309 0:c52df770855b 168 {
jhon309 0:c52df770855b 169 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
jhon309 0:c52df770855b 170 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
jhon309 0:c52df770855b 171 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
jhon309 0:c52df770855b 172 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
jhon309 0:c52df770855b 173 }CAN_TxMailBox_TypeDef;
jhon309 0:c52df770855b 174
jhon309 0:c52df770855b 175 /**
jhon309 0:c52df770855b 176 * @brief Controller Area Network FIFOMailBox
jhon309 0:c52df770855b 177 */
jhon309 0:c52df770855b 178 typedef struct
jhon309 0:c52df770855b 179 {
jhon309 0:c52df770855b 180 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
jhon309 0:c52df770855b 181 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
jhon309 0:c52df770855b 182 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
jhon309 0:c52df770855b 183 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
jhon309 0:c52df770855b 184 }CAN_FIFOMailBox_TypeDef;
jhon309 0:c52df770855b 185
jhon309 0:c52df770855b 186 /**
jhon309 0:c52df770855b 187 * @brief Controller Area Network FilterRegister
jhon309 0:c52df770855b 188 */
jhon309 0:c52df770855b 189 typedef struct
jhon309 0:c52df770855b 190 {
jhon309 0:c52df770855b 191 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
jhon309 0:c52df770855b 192 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
jhon309 0:c52df770855b 193 }CAN_FilterRegister_TypeDef;
jhon309 0:c52df770855b 194
jhon309 0:c52df770855b 195 /**
jhon309 0:c52df770855b 196 * @brief Controller Area Network
jhon309 0:c52df770855b 197 */
jhon309 0:c52df770855b 198 typedef struct
jhon309 0:c52df770855b 199 {
jhon309 0:c52df770855b 200 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
jhon309 0:c52df770855b 201 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
jhon309 0:c52df770855b 202 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
jhon309 0:c52df770855b 203 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
jhon309 0:c52df770855b 204 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
jhon309 0:c52df770855b 205 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
jhon309 0:c52df770855b 206 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
jhon309 0:c52df770855b 207 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
jhon309 0:c52df770855b 208 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
jhon309 0:c52df770855b 209 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
jhon309 0:c52df770855b 210 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
jhon309 0:c52df770855b 211 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
jhon309 0:c52df770855b 212 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
jhon309 0:c52df770855b 213 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
jhon309 0:c52df770855b 214 uint32_t RESERVED2; /*!< Reserved, 0x208 */
jhon309 0:c52df770855b 215 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
jhon309 0:c52df770855b 216 uint32_t RESERVED3; /*!< Reserved, 0x210 */
jhon309 0:c52df770855b 217 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
jhon309 0:c52df770855b 218 uint32_t RESERVED4; /*!< Reserved, 0x218 */
jhon309 0:c52df770855b 219 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
jhon309 0:c52df770855b 220 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
jhon309 0:c52df770855b 221 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
jhon309 0:c52df770855b 222 }CAN_TypeDef;
jhon309 0:c52df770855b 223
jhon309 0:c52df770855b 224 /**
jhon309 0:c52df770855b 225 * @brief HDMI-CEC
jhon309 0:c52df770855b 226 */
jhon309 0:c52df770855b 227
jhon309 0:c52df770855b 228 typedef struct
jhon309 0:c52df770855b 229 {
jhon309 0:c52df770855b 230 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
jhon309 0:c52df770855b 231 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
jhon309 0:c52df770855b 232 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
jhon309 0:c52df770855b 233 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
jhon309 0:c52df770855b 234 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
jhon309 0:c52df770855b 235 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
jhon309 0:c52df770855b 236 }CEC_TypeDef;
jhon309 0:c52df770855b 237
jhon309 0:c52df770855b 238 /**
jhon309 0:c52df770855b 239 * @brief Comparator
jhon309 0:c52df770855b 240 */
jhon309 0:c52df770855b 241
jhon309 0:c52df770855b 242 typedef struct
jhon309 0:c52df770855b 243 {
jhon309 0:c52df770855b 244 __IO uint32_t CSR; /*!< Comparator 1 & 2 control Status register, Address offset: 0x00 */
jhon309 0:c52df770855b 245 }COMP1_2_TypeDef;
jhon309 0:c52df770855b 246
jhon309 0:c52df770855b 247 typedef struct
jhon309 0:c52df770855b 248 {
jhon309 0:c52df770855b 249 __IO uint16_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
jhon309 0:c52df770855b 250 }COMP_TypeDef;
jhon309 0:c52df770855b 251
jhon309 0:c52df770855b 252 /**
jhon309 0:c52df770855b 253 * @brief CRC calculation unit
jhon309 0:c52df770855b 254 */
jhon309 0:c52df770855b 255
jhon309 0:c52df770855b 256 typedef struct
jhon309 0:c52df770855b 257 {
jhon309 0:c52df770855b 258 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
jhon309 0:c52df770855b 259 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
jhon309 0:c52df770855b 260 uint8_t RESERVED0; /*!< Reserved, 0x05 */
jhon309 0:c52df770855b 261 uint16_t RESERVED1; /*!< Reserved, 0x06 */
jhon309 0:c52df770855b 262 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
jhon309 0:c52df770855b 263 uint32_t RESERVED2; /*!< Reserved, 0x0C */
jhon309 0:c52df770855b 264 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
jhon309 0:c52df770855b 265 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
jhon309 0:c52df770855b 266 }CRC_TypeDef;
jhon309 0:c52df770855b 267
jhon309 0:c52df770855b 268 /**
jhon309 0:c52df770855b 269 * @brief Clock Recovery System
jhon309 0:c52df770855b 270 */
jhon309 0:c52df770855b 271 typedef struct
jhon309 0:c52df770855b 272 {
jhon309 0:c52df770855b 273 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
jhon309 0:c52df770855b 274 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
jhon309 0:c52df770855b 275 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
jhon309 0:c52df770855b 276 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
jhon309 0:c52df770855b 277 }CRS_TypeDef;
jhon309 0:c52df770855b 278
jhon309 0:c52df770855b 279 /**
jhon309 0:c52df770855b 280 * @brief Digital to Analog Converter
jhon309 0:c52df770855b 281 */
jhon309 0:c52df770855b 282
jhon309 0:c52df770855b 283 typedef struct
jhon309 0:c52df770855b 284 {
jhon309 0:c52df770855b 285 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
jhon309 0:c52df770855b 286 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
jhon309 0:c52df770855b 287 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
jhon309 0:c52df770855b 288 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
jhon309 0:c52df770855b 289 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
jhon309 0:c52df770855b 290 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
jhon309 0:c52df770855b 291 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
jhon309 0:c52df770855b 292 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
jhon309 0:c52df770855b 293 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
jhon309 0:c52df770855b 294 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
jhon309 0:c52df770855b 295 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
jhon309 0:c52df770855b 296 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
jhon309 0:c52df770855b 297 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
jhon309 0:c52df770855b 298 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
jhon309 0:c52df770855b 299 }DAC_TypeDef;
jhon309 0:c52df770855b 300
jhon309 0:c52df770855b 301 /**
jhon309 0:c52df770855b 302 * @brief Debug MCU
jhon309 0:c52df770855b 303 */
jhon309 0:c52df770855b 304
jhon309 0:c52df770855b 305 typedef struct
jhon309 0:c52df770855b 306 {
jhon309 0:c52df770855b 307 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
jhon309 0:c52df770855b 308 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
jhon309 0:c52df770855b 309 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
jhon309 0:c52df770855b 310 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
jhon309 0:c52df770855b 311 }DBGMCU_TypeDef;
jhon309 0:c52df770855b 312
jhon309 0:c52df770855b 313 /**
jhon309 0:c52df770855b 314 * @brief DMA Controller
jhon309 0:c52df770855b 315 */
jhon309 0:c52df770855b 316
jhon309 0:c52df770855b 317 typedef struct
jhon309 0:c52df770855b 318 {
jhon309 0:c52df770855b 319 __IO uint32_t CCR; /*!< DMA channel x configuration register */
jhon309 0:c52df770855b 320 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
jhon309 0:c52df770855b 321 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
jhon309 0:c52df770855b 322 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
jhon309 0:c52df770855b 323 }DMA_Channel_TypeDef;
jhon309 0:c52df770855b 324
jhon309 0:c52df770855b 325 typedef struct
jhon309 0:c52df770855b 326 {
jhon309 0:c52df770855b 327 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
jhon309 0:c52df770855b 328 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
jhon309 0:c52df770855b 329 }DMA_TypeDef;
jhon309 0:c52df770855b 330
jhon309 0:c52df770855b 331 /**
jhon309 0:c52df770855b 332 * @brief External Interrupt/Event Controller
jhon309 0:c52df770855b 333 */
jhon309 0:c52df770855b 334
jhon309 0:c52df770855b 335 typedef struct
jhon309 0:c52df770855b 336 {
jhon309 0:c52df770855b 337 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
jhon309 0:c52df770855b 338 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
jhon309 0:c52df770855b 339 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
jhon309 0:c52df770855b 340 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
jhon309 0:c52df770855b 341 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
jhon309 0:c52df770855b 342 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
jhon309 0:c52df770855b 343 }EXTI_TypeDef;
jhon309 0:c52df770855b 344
jhon309 0:c52df770855b 345 /**
jhon309 0:c52df770855b 346 * @brief FLASH Registers
jhon309 0:c52df770855b 347 */
jhon309 0:c52df770855b 348 typedef struct
jhon309 0:c52df770855b 349 {
jhon309 0:c52df770855b 350 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
jhon309 0:c52df770855b 351 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
jhon309 0:c52df770855b 352 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
jhon309 0:c52df770855b 353 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
jhon309 0:c52df770855b 354 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
jhon309 0:c52df770855b 355 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
jhon309 0:c52df770855b 356 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
jhon309 0:c52df770855b 357 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
jhon309 0:c52df770855b 358 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
jhon309 0:c52df770855b 359 }FLASH_TypeDef;
jhon309 0:c52df770855b 360
jhon309 0:c52df770855b 361
jhon309 0:c52df770855b 362 /**
jhon309 0:c52df770855b 363 * @brief Option Bytes Registers
jhon309 0:c52df770855b 364 */
jhon309 0:c52df770855b 365 typedef struct
jhon309 0:c52df770855b 366 {
jhon309 0:c52df770855b 367 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
jhon309 0:c52df770855b 368 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
jhon309 0:c52df770855b 369 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
jhon309 0:c52df770855b 370 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
jhon309 0:c52df770855b 371 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
jhon309 0:c52df770855b 372 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
jhon309 0:c52df770855b 373 __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
jhon309 0:c52df770855b 374 __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
jhon309 0:c52df770855b 375 }OB_TypeDef;
jhon309 0:c52df770855b 376
jhon309 0:c52df770855b 377 /**
jhon309 0:c52df770855b 378 * @brief General Purpose I/O
jhon309 0:c52df770855b 379 */
jhon309 0:c52df770855b 380
jhon309 0:c52df770855b 381 typedef struct
jhon309 0:c52df770855b 382 {
jhon309 0:c52df770855b 383 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
jhon309 0:c52df770855b 384 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
jhon309 0:c52df770855b 385 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
jhon309 0:c52df770855b 386 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
jhon309 0:c52df770855b 387 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
jhon309 0:c52df770855b 388 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
jhon309 0:c52df770855b 389 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
jhon309 0:c52df770855b 390 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
jhon309 0:c52df770855b 391 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
jhon309 0:c52df770855b 392 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
jhon309 0:c52df770855b 393 }GPIO_TypeDef;
jhon309 0:c52df770855b 394
jhon309 0:c52df770855b 395 /**
jhon309 0:c52df770855b 396 * @brief SysTem Configuration
jhon309 0:c52df770855b 397 */
jhon309 0:c52df770855b 398
jhon309 0:c52df770855b 399 typedef struct
jhon309 0:c52df770855b 400 {
jhon309 0:c52df770855b 401 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
jhon309 0:c52df770855b 402 uint32_t RESERVED; /*!< Reserved, 0x04 */
jhon309 0:c52df770855b 403 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
jhon309 0:c52df770855b 404 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
jhon309 0:c52df770855b 405 }SYSCFG_TypeDef;
jhon309 0:c52df770855b 406
jhon309 0:c52df770855b 407 /**
jhon309 0:c52df770855b 408 * @brief Inter-integrated Circuit Interface
jhon309 0:c52df770855b 409 */
jhon309 0:c52df770855b 410
jhon309 0:c52df770855b 411 typedef struct
jhon309 0:c52df770855b 412 {
jhon309 0:c52df770855b 413 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
jhon309 0:c52df770855b 414 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
jhon309 0:c52df770855b 415 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
jhon309 0:c52df770855b 416 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
jhon309 0:c52df770855b 417 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
jhon309 0:c52df770855b 418 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
jhon309 0:c52df770855b 419 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
jhon309 0:c52df770855b 420 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
jhon309 0:c52df770855b 421 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
jhon309 0:c52df770855b 422 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
jhon309 0:c52df770855b 423 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
jhon309 0:c52df770855b 424 }I2C_TypeDef;
jhon309 0:c52df770855b 425
jhon309 0:c52df770855b 426 /**
jhon309 0:c52df770855b 427 * @brief Independent WATCHDOG
jhon309 0:c52df770855b 428 */
jhon309 0:c52df770855b 429
jhon309 0:c52df770855b 430 typedef struct
jhon309 0:c52df770855b 431 {
jhon309 0:c52df770855b 432 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
jhon309 0:c52df770855b 433 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
jhon309 0:c52df770855b 434 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
jhon309 0:c52df770855b 435 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
jhon309 0:c52df770855b 436 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
jhon309 0:c52df770855b 437 }IWDG_TypeDef;
jhon309 0:c52df770855b 438
jhon309 0:c52df770855b 439 /**
jhon309 0:c52df770855b 440 * @brief Power Control
jhon309 0:c52df770855b 441 */
jhon309 0:c52df770855b 442
jhon309 0:c52df770855b 443 typedef struct
jhon309 0:c52df770855b 444 {
jhon309 0:c52df770855b 445 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
jhon309 0:c52df770855b 446 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
jhon309 0:c52df770855b 447 }PWR_TypeDef;
jhon309 0:c52df770855b 448
jhon309 0:c52df770855b 449 /**
jhon309 0:c52df770855b 450 * @brief Reset and Clock Control
jhon309 0:c52df770855b 451 */
jhon309 0:c52df770855b 452 typedef struct
jhon309 0:c52df770855b 453 {
jhon309 0:c52df770855b 454 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
jhon309 0:c52df770855b 455 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
jhon309 0:c52df770855b 456 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
jhon309 0:c52df770855b 457 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
jhon309 0:c52df770855b 458 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
jhon309 0:c52df770855b 459 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
jhon309 0:c52df770855b 460 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
jhon309 0:c52df770855b 461 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
jhon309 0:c52df770855b 462 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
jhon309 0:c52df770855b 463 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
jhon309 0:c52df770855b 464 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
jhon309 0:c52df770855b 465 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
jhon309 0:c52df770855b 466 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
jhon309 0:c52df770855b 467 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
jhon309 0:c52df770855b 468 }RCC_TypeDef;
jhon309 0:c52df770855b 469
jhon309 0:c52df770855b 470 /**
jhon309 0:c52df770855b 471 * @brief Real-Time Clock
jhon309 0:c52df770855b 472 */
jhon309 0:c52df770855b 473
jhon309 0:c52df770855b 474 typedef struct
jhon309 0:c52df770855b 475 {
jhon309 0:c52df770855b 476 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
jhon309 0:c52df770855b 477 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
jhon309 0:c52df770855b 478 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
jhon309 0:c52df770855b 479 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
jhon309 0:c52df770855b 480 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
jhon309 0:c52df770855b 481 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
jhon309 0:c52df770855b 482 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
jhon309 0:c52df770855b 483 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
jhon309 0:c52df770855b 484 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
jhon309 0:c52df770855b 485 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
jhon309 0:c52df770855b 486 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
jhon309 0:c52df770855b 487 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
jhon309 0:c52df770855b 488 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
jhon309 0:c52df770855b 489 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
jhon309 0:c52df770855b 490 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
jhon309 0:c52df770855b 491 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
jhon309 0:c52df770855b 492 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
jhon309 0:c52df770855b 493 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
jhon309 0:c52df770855b 494 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
jhon309 0:c52df770855b 495 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x4C */
jhon309 0:c52df770855b 496 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
jhon309 0:c52df770855b 497 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
jhon309 0:c52df770855b 498 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
jhon309 0:c52df770855b 499 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
jhon309 0:c52df770855b 500 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
jhon309 0:c52df770855b 501 }RTC_TypeDef;
jhon309 0:c52df770855b 502
jhon309 0:c52df770855b 503 /**
jhon309 0:c52df770855b 504 * @brief Serial Peripheral Interface
jhon309 0:c52df770855b 505 */
jhon309 0:c52df770855b 506
jhon309 0:c52df770855b 507 typedef struct
jhon309 0:c52df770855b 508 {
jhon309 0:c52df770855b 509 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
jhon309 0:c52df770855b 510 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
jhon309 0:c52df770855b 511 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
jhon309 0:c52df770855b 512 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
jhon309 0:c52df770855b 513 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
jhon309 0:c52df770855b 514 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
jhon309 0:c52df770855b 515 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
jhon309 0:c52df770855b 516 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
jhon309 0:c52df770855b 517 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
jhon309 0:c52df770855b 518 }SPI_TypeDef;
jhon309 0:c52df770855b 519
jhon309 0:c52df770855b 520 /**
jhon309 0:c52df770855b 521 * @brief TIM
jhon309 0:c52df770855b 522 */
jhon309 0:c52df770855b 523 typedef struct
jhon309 0:c52df770855b 524 {
jhon309 0:c52df770855b 525 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
jhon309 0:c52df770855b 526 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
jhon309 0:c52df770855b 527 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
jhon309 0:c52df770855b 528 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
jhon309 0:c52df770855b 529 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
jhon309 0:c52df770855b 530 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
jhon309 0:c52df770855b 531 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
jhon309 0:c52df770855b 532 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
jhon309 0:c52df770855b 533 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
jhon309 0:c52df770855b 534 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
jhon309 0:c52df770855b 535 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
jhon309 0:c52df770855b 536 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
jhon309 0:c52df770855b 537 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
jhon309 0:c52df770855b 538 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
jhon309 0:c52df770855b 539 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
jhon309 0:c52df770855b 540 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
jhon309 0:c52df770855b 541 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
jhon309 0:c52df770855b 542 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
jhon309 0:c52df770855b 543 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
jhon309 0:c52df770855b 544 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
jhon309 0:c52df770855b 545 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
jhon309 0:c52df770855b 546 }TIM_TypeDef;
jhon309 0:c52df770855b 547
jhon309 0:c52df770855b 548 /**
jhon309 0:c52df770855b 549 * @brief Touch Sensing Controller (TSC)
jhon309 0:c52df770855b 550 */
jhon309 0:c52df770855b 551 typedef struct
jhon309 0:c52df770855b 552 {
jhon309 0:c52df770855b 553 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
jhon309 0:c52df770855b 554 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
jhon309 0:c52df770855b 555 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
jhon309 0:c52df770855b 556 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
jhon309 0:c52df770855b 557 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
jhon309 0:c52df770855b 558 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
jhon309 0:c52df770855b 559 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
jhon309 0:c52df770855b 560 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
jhon309 0:c52df770855b 561 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
jhon309 0:c52df770855b 562 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
jhon309 0:c52df770855b 563 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
jhon309 0:c52df770855b 564 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
jhon309 0:c52df770855b 565 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
jhon309 0:c52df770855b 566 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
jhon309 0:c52df770855b 567 }TSC_TypeDef;
jhon309 0:c52df770855b 568
jhon309 0:c52df770855b 569 /**
jhon309 0:c52df770855b 570 * @brief Universal Synchronous Asynchronous Receiver Transmitter
jhon309 0:c52df770855b 571 */
jhon309 0:c52df770855b 572
jhon309 0:c52df770855b 573 typedef struct
jhon309 0:c52df770855b 574 {
jhon309 0:c52df770855b 575 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
jhon309 0:c52df770855b 576 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
jhon309 0:c52df770855b 577 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
jhon309 0:c52df770855b 578 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
jhon309 0:c52df770855b 579 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
jhon309 0:c52df770855b 580 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
jhon309 0:c52df770855b 581 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
jhon309 0:c52df770855b 582 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
jhon309 0:c52df770855b 583 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
jhon309 0:c52df770855b 584 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
jhon309 0:c52df770855b 585 uint16_t RESERVED1; /*!< Reserved, 0x26 */
jhon309 0:c52df770855b 586 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
jhon309 0:c52df770855b 587 uint16_t RESERVED2; /*!< Reserved, 0x2A */
jhon309 0:c52df770855b 588 }USART_TypeDef;
jhon309 0:c52df770855b 589
jhon309 0:c52df770855b 590 /**
jhon309 0:c52df770855b 591 * @brief Universal Serial Bus Full Speed Device
jhon309 0:c52df770855b 592 */
jhon309 0:c52df770855b 593
jhon309 0:c52df770855b 594 typedef struct
jhon309 0:c52df770855b 595 {
jhon309 0:c52df770855b 596 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
jhon309 0:c52df770855b 597 __IO uint16_t RESERVED0; /*!< Reserved */
jhon309 0:c52df770855b 598 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
jhon309 0:c52df770855b 599 __IO uint16_t RESERVED1; /*!< Reserved */
jhon309 0:c52df770855b 600 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
jhon309 0:c52df770855b 601 __IO uint16_t RESERVED2; /*!< Reserved */
jhon309 0:c52df770855b 602 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
jhon309 0:c52df770855b 603 __IO uint16_t RESERVED3; /*!< Reserved */
jhon309 0:c52df770855b 604 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
jhon309 0:c52df770855b 605 __IO uint16_t RESERVED4; /*!< Reserved */
jhon309 0:c52df770855b 606 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
jhon309 0:c52df770855b 607 __IO uint16_t RESERVED5; /*!< Reserved */
jhon309 0:c52df770855b 608 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
jhon309 0:c52df770855b 609 __IO uint16_t RESERVED6; /*!< Reserved */
jhon309 0:c52df770855b 610 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
jhon309 0:c52df770855b 611 __IO uint16_t RESERVED7[17]; /*!< Reserved */
jhon309 0:c52df770855b 612 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
jhon309 0:c52df770855b 613 __IO uint16_t RESERVED8; /*!< Reserved */
jhon309 0:c52df770855b 614 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
jhon309 0:c52df770855b 615 __IO uint16_t RESERVED9; /*!< Reserved */
jhon309 0:c52df770855b 616 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
jhon309 0:c52df770855b 617 __IO uint16_t RESERVEDA; /*!< Reserved */
jhon309 0:c52df770855b 618 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
jhon309 0:c52df770855b 619 __IO uint16_t RESERVEDB; /*!< Reserved */
jhon309 0:c52df770855b 620 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
jhon309 0:c52df770855b 621 __IO uint16_t RESERVEDC; /*!< Reserved */
jhon309 0:c52df770855b 622 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
jhon309 0:c52df770855b 623 __IO uint16_t RESERVEDD; /*!< Reserved */
jhon309 0:c52df770855b 624 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
jhon309 0:c52df770855b 625 __IO uint16_t RESERVEDE; /*!< Reserved */
jhon309 0:c52df770855b 626 }USB_TypeDef;
jhon309 0:c52df770855b 627
jhon309 0:c52df770855b 628 /**
jhon309 0:c52df770855b 629 * @brief Window WATCHDOG
jhon309 0:c52df770855b 630 */
jhon309 0:c52df770855b 631 typedef struct
jhon309 0:c52df770855b 632 {
jhon309 0:c52df770855b 633 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
jhon309 0:c52df770855b 634 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
jhon309 0:c52df770855b 635 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
jhon309 0:c52df770855b 636 }WWDG_TypeDef;
jhon309 0:c52df770855b 637
jhon309 0:c52df770855b 638 /**
jhon309 0:c52df770855b 639 * @}
jhon309 0:c52df770855b 640 */
jhon309 0:c52df770855b 641
jhon309 0:c52df770855b 642 /** @addtogroup Peripheral_memory_map
jhon309 0:c52df770855b 643 * @{
jhon309 0:c52df770855b 644 */
jhon309 0:c52df770855b 645
jhon309 0:c52df770855b 646 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
jhon309 0:c52df770855b 647 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
jhon309 0:c52df770855b 648 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
jhon309 0:c52df770855b 649
jhon309 0:c52df770855b 650 /*!< Peripheral memory map */
jhon309 0:c52df770855b 651 #define APBPERIPH_BASE PERIPH_BASE
jhon309 0:c52df770855b 652 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
jhon309 0:c52df770855b 653 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
jhon309 0:c52df770855b 654
jhon309 0:c52df770855b 655 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
jhon309 0:c52df770855b 656 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
jhon309 0:c52df770855b 657 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
jhon309 0:c52df770855b 658 #define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
jhon309 0:c52df770855b 659 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
jhon309 0:c52df770855b 660 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
jhon309 0:c52df770855b 661 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
jhon309 0:c52df770855b 662 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
jhon309 0:c52df770855b 663 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
jhon309 0:c52df770855b 664 #define USART2_BASE (APBPERIPH_BASE + 0x00004400)
jhon309 0:c52df770855b 665 #define USART3_BASE (APBPERIPH_BASE + 0x00004800)
jhon309 0:c52df770855b 666 #define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
jhon309 0:c52df770855b 667 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
jhon309 0:c52df770855b 668 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
jhon309 0:c52df770855b 669 #define USB_BASE (APBPERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
jhon309 0:c52df770855b 670 #define USB_PMAADDR (APBPERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
jhon309 0:c52df770855b 671 #define CAN_BASE (APBPERIPH_BASE + 0x00006400)
jhon309 0:c52df770855b 672 #define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
jhon309 0:c52df770855b 673 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
jhon309 0:c52df770855b 674 #define DAC_BASE (APBPERIPH_BASE + 0x00007400)
jhon309 0:c52df770855b 675 #define CEC_BASE (APBPERIPH_BASE + 0x00007800)
jhon309 0:c52df770855b 676
jhon309 0:c52df770855b 677 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
jhon309 0:c52df770855b 678 #define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
jhon309 0:c52df770855b 679 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
jhon309 0:c52df770855b 680 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
jhon309 0:c52df770855b 681 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
jhon309 0:c52df770855b 682 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
jhon309 0:c52df770855b 683 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
jhon309 0:c52df770855b 684 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
jhon309 0:c52df770855b 685 #define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
jhon309 0:c52df770855b 686 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
jhon309 0:c52df770855b 687 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
jhon309 0:c52df770855b 688 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
jhon309 0:c52df770855b 689
jhon309 0:c52df770855b 690 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
jhon309 0:c52df770855b 691 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
jhon309 0:c52df770855b 692 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
jhon309 0:c52df770855b 693 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
jhon309 0:c52df770855b 694 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
jhon309 0:c52df770855b 695 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
jhon309 0:c52df770855b 696 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
jhon309 0:c52df770855b 697 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
jhon309 0:c52df770855b 698
jhon309 0:c52df770855b 699 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
jhon309 0:c52df770855b 700 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
jhon309 0:c52df770855b 701 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
jhon309 0:c52df770855b 702 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
jhon309 0:c52df770855b 703 #define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
jhon309 0:c52df770855b 704
jhon309 0:c52df770855b 705 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
jhon309 0:c52df770855b 706 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
jhon309 0:c52df770855b 707 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
jhon309 0:c52df770855b 708 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
jhon309 0:c52df770855b 709 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
jhon309 0:c52df770855b 710 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
jhon309 0:c52df770855b 711
jhon309 0:c52df770855b 712 /**
jhon309 0:c52df770855b 713 * @}
jhon309 0:c52df770855b 714 */
jhon309 0:c52df770855b 715
jhon309 0:c52df770855b 716 /** @addtogroup Peripheral_declaration
jhon309 0:c52df770855b 717 * @{
jhon309 0:c52df770855b 718 */
jhon309 0:c52df770855b 719
jhon309 0:c52df770855b 720 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
jhon309 0:c52df770855b 721 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
jhon309 0:c52df770855b 722 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
jhon309 0:c52df770855b 723 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
jhon309 0:c52df770855b 724 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
jhon309 0:c52df770855b 725 #define RTC ((RTC_TypeDef *) RTC_BASE)
jhon309 0:c52df770855b 726 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
jhon309 0:c52df770855b 727 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
jhon309 0:c52df770855b 728 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
jhon309 0:c52df770855b 729 #define USART2 ((USART_TypeDef *) USART2_BASE)
jhon309 0:c52df770855b 730 #define USART3 ((USART_TypeDef *) USART3_BASE)
jhon309 0:c52df770855b 731 #define USART4 ((USART_TypeDef *) USART4_BASE)
jhon309 0:c52df770855b 732 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
jhon309 0:c52df770855b 733 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
jhon309 0:c52df770855b 734 #define CAN ((CAN_TypeDef *) CAN_BASE)
jhon309 0:c52df770855b 735 #define CRS ((CRS_TypeDef *) CRS_BASE)
jhon309 0:c52df770855b 736 #define PWR ((PWR_TypeDef *) PWR_BASE)
jhon309 0:c52df770855b 737 #define DAC ((DAC_TypeDef *) DAC_BASE)
jhon309 0:c52df770855b 738 #define CEC ((CEC_TypeDef *) CEC_BASE)
jhon309 0:c52df770855b 739 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
jhon309 0:c52df770855b 740 #define COMP ((COMP1_2_TypeDef *) COMP_BASE)
jhon309 0:c52df770855b 741 #define COMP1 ((COMP_TypeDef *) COMP_BASE)
jhon309 0:c52df770855b 742 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000002))
jhon309 0:c52df770855b 743 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
jhon309 0:c52df770855b 744 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
jhon309 0:c52df770855b 745 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
jhon309 0:c52df770855b 746 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
jhon309 0:c52df770855b 747 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
jhon309 0:c52df770855b 748 #define USART1 ((USART_TypeDef *) USART1_BASE)
jhon309 0:c52df770855b 749 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
jhon309 0:c52df770855b 750 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
jhon309 0:c52df770855b 751 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
jhon309 0:c52df770855b 752 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
jhon309 0:c52df770855b 753 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
jhon309 0:c52df770855b 754 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
jhon309 0:c52df770855b 755 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
jhon309 0:c52df770855b 756 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
jhon309 0:c52df770855b 757 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
jhon309 0:c52df770855b 758 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
jhon309 0:c52df770855b 759 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
jhon309 0:c52df770855b 760 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
jhon309 0:c52df770855b 761 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
jhon309 0:c52df770855b 762 #define OB ((OB_TypeDef *) OB_BASE)
jhon309 0:c52df770855b 763 #define RCC ((RCC_TypeDef *) RCC_BASE)
jhon309 0:c52df770855b 764 #define CRC ((CRC_TypeDef *) CRC_BASE)
jhon309 0:c52df770855b 765 #define TSC ((TSC_TypeDef *) TSC_BASE)
jhon309 0:c52df770855b 766 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
jhon309 0:c52df770855b 767 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
jhon309 0:c52df770855b 768 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
jhon309 0:c52df770855b 769 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
jhon309 0:c52df770855b 770 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
jhon309 0:c52df770855b 771 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
jhon309 0:c52df770855b 772 #define USB ((USB_TypeDef *) USB_BASE)
jhon309 0:c52df770855b 773 /**
jhon309 0:c52df770855b 774 * @}
jhon309 0:c52df770855b 775 */
jhon309 0:c52df770855b 776
jhon309 0:c52df770855b 777 /** @addtogroup Exported_constants
jhon309 0:c52df770855b 778 * @{
jhon309 0:c52df770855b 779 */
jhon309 0:c52df770855b 780
jhon309 0:c52df770855b 781 /** @addtogroup Peripheral_Registers_Bits_Definition
jhon309 0:c52df770855b 782 * @{
jhon309 0:c52df770855b 783 */
jhon309 0:c52df770855b 784
jhon309 0:c52df770855b 785 /******************************************************************************/
jhon309 0:c52df770855b 786 /* Peripheral Registers Bits Definition */
jhon309 0:c52df770855b 787 /******************************************************************************/
jhon309 0:c52df770855b 788 /******************************************************************************/
jhon309 0:c52df770855b 789 /* */
jhon309 0:c52df770855b 790 /* Analog to Digital Converter (ADC) */
jhon309 0:c52df770855b 791 /* */
jhon309 0:c52df770855b 792 /******************************************************************************/
jhon309 0:c52df770855b 793 /******************** Bits definition for ADC_ISR register ******************/
jhon309 0:c52df770855b 794 #define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
jhon309 0:c52df770855b 795 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
jhon309 0:c52df770855b 796 #define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
jhon309 0:c52df770855b 797 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
jhon309 0:c52df770855b 798 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
jhon309 0:c52df770855b 799 #define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
jhon309 0:c52df770855b 800
jhon309 0:c52df770855b 801 /* Old EOSEQ bit definition, maintained for legacy purpose */
jhon309 0:c52df770855b 802 #define ADC_ISR_EOS ADC_ISR_EOSEQ
jhon309 0:c52df770855b 803
jhon309 0:c52df770855b 804 /******************** Bits definition for ADC_IER register ******************/
jhon309 0:c52df770855b 805 #define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
jhon309 0:c52df770855b 806 #define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
jhon309 0:c52df770855b 807 #define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
jhon309 0:c52df770855b 808 #define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
jhon309 0:c52df770855b 809 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
jhon309 0:c52df770855b 810 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
jhon309 0:c52df770855b 811
jhon309 0:c52df770855b 812 /* Old EOSEQIE bit definition, maintained for legacy purpose */
jhon309 0:c52df770855b 813 #define ADC_IER_EOSIE ADC_IER_EOSEQIE
jhon309 0:c52df770855b 814
jhon309 0:c52df770855b 815 /******************** Bits definition for ADC_CR register *******************/
jhon309 0:c52df770855b 816 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
jhon309 0:c52df770855b 817 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
jhon309 0:c52df770855b 818 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
jhon309 0:c52df770855b 819 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
jhon309 0:c52df770855b 820 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
jhon309 0:c52df770855b 821
jhon309 0:c52df770855b 822 /******************* Bits definition for ADC_CFGR1 register *****************/
jhon309 0:c52df770855b 823 #define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
jhon309 0:c52df770855b 824 #define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
jhon309 0:c52df770855b 825 #define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
jhon309 0:c52df770855b 826 #define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
jhon309 0:c52df770855b 827 #define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
jhon309 0:c52df770855b 828 #define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
jhon309 0:c52df770855b 829 #define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
jhon309 0:c52df770855b 830 #define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
jhon309 0:c52df770855b 831 #define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
jhon309 0:c52df770855b 832 #define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
jhon309 0:c52df770855b 833 #define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
jhon309 0:c52df770855b 834 #define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
jhon309 0:c52df770855b 835 #define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
jhon309 0:c52df770855b 836 #define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
jhon309 0:c52df770855b 837 #define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
jhon309 0:c52df770855b 838 #define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
jhon309 0:c52df770855b 839 #define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
jhon309 0:c52df770855b 840 #define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
jhon309 0:c52df770855b 841 #define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
jhon309 0:c52df770855b 842 #define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
jhon309 0:c52df770855b 843 #define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
jhon309 0:c52df770855b 844 #define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
jhon309 0:c52df770855b 845 #define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
jhon309 0:c52df770855b 846 #define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
jhon309 0:c52df770855b 847 #define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
jhon309 0:c52df770855b 848 #define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
jhon309 0:c52df770855b 849 #define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
jhon309 0:c52df770855b 850
jhon309 0:c52df770855b 851 /* Old WAIT bit definition, maintained for legacy purpose */
jhon309 0:c52df770855b 852 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
jhon309 0:c52df770855b 853
jhon309 0:c52df770855b 854 /******************* Bits definition for ADC_CFGR2 register *****************/
jhon309 0:c52df770855b 855 #define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
jhon309 0:c52df770855b 856 #define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
jhon309 0:c52df770855b 857 #define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
jhon309 0:c52df770855b 858
jhon309 0:c52df770855b 859 /* Old bit definition, maintained for legacy purpose */
jhon309 0:c52df770855b 860 #define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
jhon309 0:c52df770855b 861 #define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
jhon309 0:c52df770855b 862
jhon309 0:c52df770855b 863 /****************** Bit definition for ADC_SMPR register ********************/
jhon309 0:c52df770855b 864 #define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
jhon309 0:c52df770855b 865 #define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
jhon309 0:c52df770855b 866 #define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
jhon309 0:c52df770855b 867 #define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
jhon309 0:c52df770855b 868
jhon309 0:c52df770855b 869 /* Old bit definition, maintained for legacy purpose */
jhon309 0:c52df770855b 870 #define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
jhon309 0:c52df770855b 871 #define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
jhon309 0:c52df770855b 872 #define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
jhon309 0:c52df770855b 873 #define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
jhon309 0:c52df770855b 874
jhon309 0:c52df770855b 875 /******************* Bit definition for ADC_TR register ********************/
jhon309 0:c52df770855b 876 #define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
jhon309 0:c52df770855b 877 #define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
jhon309 0:c52df770855b 878
jhon309 0:c52df770855b 879 /* Old bit definition, maintained for legacy purpose */
jhon309 0:c52df770855b 880 #define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
jhon309 0:c52df770855b 881 #define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
jhon309 0:c52df770855b 882
jhon309 0:c52df770855b 883 /****************** Bit definition for ADC_CHSELR register ******************/
jhon309 0:c52df770855b 884 #define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
jhon309 0:c52df770855b 885 #define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
jhon309 0:c52df770855b 886 #define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
jhon309 0:c52df770855b 887 #define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
jhon309 0:c52df770855b 888 #define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
jhon309 0:c52df770855b 889 #define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
jhon309 0:c52df770855b 890 #define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
jhon309 0:c52df770855b 891 #define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
jhon309 0:c52df770855b 892 #define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
jhon309 0:c52df770855b 893 #define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
jhon309 0:c52df770855b 894 #define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
jhon309 0:c52df770855b 895 #define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
jhon309 0:c52df770855b 896 #define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
jhon309 0:c52df770855b 897 #define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
jhon309 0:c52df770855b 898 #define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
jhon309 0:c52df770855b 899 #define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
jhon309 0:c52df770855b 900 #define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
jhon309 0:c52df770855b 901 #define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
jhon309 0:c52df770855b 902 #define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
jhon309 0:c52df770855b 903
jhon309 0:c52df770855b 904 /******************** Bit definition for ADC_DR register ********************/
jhon309 0:c52df770855b 905 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
jhon309 0:c52df770855b 906
jhon309 0:c52df770855b 907 /******************* Bit definition for ADC_CCR register ********************/
jhon309 0:c52df770855b 908 #define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
jhon309 0:c52df770855b 909 #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
jhon309 0:c52df770855b 910 #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
jhon309 0:c52df770855b 911
jhon309 0:c52df770855b 912 /******************************************************************************/
jhon309 0:c52df770855b 913 /* */
jhon309 0:c52df770855b 914 /* Controller Area Network (CAN ) */
jhon309 0:c52df770855b 915 /* */
jhon309 0:c52df770855b 916 /******************************************************************************/
jhon309 0:c52df770855b 917 /*!<CAN control and status registers */
jhon309 0:c52df770855b 918 /******************* Bit definition for CAN_MCR register ********************/
jhon309 0:c52df770855b 919 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
jhon309 0:c52df770855b 920 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
jhon309 0:c52df770855b 921 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
jhon309 0:c52df770855b 922 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
jhon309 0:c52df770855b 923 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
jhon309 0:c52df770855b 924 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
jhon309 0:c52df770855b 925 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
jhon309 0:c52df770855b 926 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
jhon309 0:c52df770855b 927 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
jhon309 0:c52df770855b 928
jhon309 0:c52df770855b 929 /******************* Bit definition for CAN_MSR register ********************/
jhon309 0:c52df770855b 930 #define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
jhon309 0:c52df770855b 931 #define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
jhon309 0:c52df770855b 932 #define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
jhon309 0:c52df770855b 933 #define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
jhon309 0:c52df770855b 934 #define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
jhon309 0:c52df770855b 935 #define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
jhon309 0:c52df770855b 936 #define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
jhon309 0:c52df770855b 937 #define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
jhon309 0:c52df770855b 938 #define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
jhon309 0:c52df770855b 939
jhon309 0:c52df770855b 940 /******************* Bit definition for CAN_TSR register ********************/
jhon309 0:c52df770855b 941 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
jhon309 0:c52df770855b 942 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
jhon309 0:c52df770855b 943 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
jhon309 0:c52df770855b 944 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
jhon309 0:c52df770855b 945 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
jhon309 0:c52df770855b 946 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
jhon309 0:c52df770855b 947 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
jhon309 0:c52df770855b 948 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
jhon309 0:c52df770855b 949 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
jhon309 0:c52df770855b 950 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
jhon309 0:c52df770855b 951 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
jhon309 0:c52df770855b 952 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
jhon309 0:c52df770855b 953 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
jhon309 0:c52df770855b 954 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
jhon309 0:c52df770855b 955 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
jhon309 0:c52df770855b 956 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
jhon309 0:c52df770855b 957
jhon309 0:c52df770855b 958 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
jhon309 0:c52df770855b 959 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
jhon309 0:c52df770855b 960 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
jhon309 0:c52df770855b 961 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
jhon309 0:c52df770855b 962
jhon309 0:c52df770855b 963 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
jhon309 0:c52df770855b 964 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
jhon309 0:c52df770855b 965 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
jhon309 0:c52df770855b 966 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
jhon309 0:c52df770855b 967
jhon309 0:c52df770855b 968 /******************* Bit definition for CAN_RF0R register *******************/
jhon309 0:c52df770855b 969 #define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
jhon309 0:c52df770855b 970 #define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
jhon309 0:c52df770855b 971 #define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
jhon309 0:c52df770855b 972 #define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
jhon309 0:c52df770855b 973
jhon309 0:c52df770855b 974 /******************* Bit definition for CAN_RF1R register *******************/
jhon309 0:c52df770855b 975 #define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
jhon309 0:c52df770855b 976 #define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
jhon309 0:c52df770855b 977 #define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
jhon309 0:c52df770855b 978 #define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
jhon309 0:c52df770855b 979
jhon309 0:c52df770855b 980 /******************** Bit definition for CAN_IER register *******************/
jhon309 0:c52df770855b 981 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
jhon309 0:c52df770855b 982 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
jhon309 0:c52df770855b 983 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
jhon309 0:c52df770855b 984 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
jhon309 0:c52df770855b 985 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
jhon309 0:c52df770855b 986 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
jhon309 0:c52df770855b 987 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
jhon309 0:c52df770855b 988 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
jhon309 0:c52df770855b 989 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
jhon309 0:c52df770855b 990 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
jhon309 0:c52df770855b 991 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
jhon309 0:c52df770855b 992 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
jhon309 0:c52df770855b 993 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
jhon309 0:c52df770855b 994 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
jhon309 0:c52df770855b 995
jhon309 0:c52df770855b 996 /******************** Bit definition for CAN_ESR register *******************/
jhon309 0:c52df770855b 997 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
jhon309 0:c52df770855b 998 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
jhon309 0:c52df770855b 999 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
jhon309 0:c52df770855b 1000
jhon309 0:c52df770855b 1001 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
jhon309 0:c52df770855b 1002 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
jhon309 0:c52df770855b 1003 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
jhon309 0:c52df770855b 1004 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
jhon309 0:c52df770855b 1005
jhon309 0:c52df770855b 1006 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
jhon309 0:c52df770855b 1007 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
jhon309 0:c52df770855b 1008
jhon309 0:c52df770855b 1009 /******************* Bit definition for CAN_BTR register ********************/
jhon309 0:c52df770855b 1010 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
jhon309 0:c52df770855b 1011 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
jhon309 0:c52df770855b 1012 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
jhon309 0:c52df770855b 1013 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
jhon309 0:c52df770855b 1014 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
jhon309 0:c52df770855b 1015 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
jhon309 0:c52df770855b 1016 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
jhon309 0:c52df770855b 1017 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
jhon309 0:c52df770855b 1018 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
jhon309 0:c52df770855b 1019 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
jhon309 0:c52df770855b 1020 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
jhon309 0:c52df770855b 1021 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
jhon309 0:c52df770855b 1022 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
jhon309 0:c52df770855b 1023 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
jhon309 0:c52df770855b 1024 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
jhon309 0:c52df770855b 1025
jhon309 0:c52df770855b 1026 /*!<Mailbox registers */
jhon309 0:c52df770855b 1027 /****************** Bit definition for CAN_TI0R register ********************/
jhon309 0:c52df770855b 1028 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
jhon309 0:c52df770855b 1029 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
jhon309 0:c52df770855b 1030 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
jhon309 0:c52df770855b 1031 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
jhon309 0:c52df770855b 1032 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
jhon309 0:c52df770855b 1033
jhon309 0:c52df770855b 1034 /****************** Bit definition for CAN_TDT0R register *******************/
jhon309 0:c52df770855b 1035 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
jhon309 0:c52df770855b 1036 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
jhon309 0:c52df770855b 1037 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
jhon309 0:c52df770855b 1038
jhon309 0:c52df770855b 1039 /****************** Bit definition for CAN_TDL0R register *******************/
jhon309 0:c52df770855b 1040 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
jhon309 0:c52df770855b 1041 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
jhon309 0:c52df770855b 1042 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
jhon309 0:c52df770855b 1043 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
jhon309 0:c52df770855b 1044
jhon309 0:c52df770855b 1045 /****************** Bit definition for CAN_TDH0R register *******************/
jhon309 0:c52df770855b 1046 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
jhon309 0:c52df770855b 1047 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
jhon309 0:c52df770855b 1048 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
jhon309 0:c52df770855b 1049 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
jhon309 0:c52df770855b 1050
jhon309 0:c52df770855b 1051 /******************* Bit definition for CAN_TI1R register *******************/
jhon309 0:c52df770855b 1052 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
jhon309 0:c52df770855b 1053 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
jhon309 0:c52df770855b 1054 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
jhon309 0:c52df770855b 1055 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
jhon309 0:c52df770855b 1056 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
jhon309 0:c52df770855b 1057
jhon309 0:c52df770855b 1058 /******************* Bit definition for CAN_TDT1R register ******************/
jhon309 0:c52df770855b 1059 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
jhon309 0:c52df770855b 1060 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
jhon309 0:c52df770855b 1061 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
jhon309 0:c52df770855b 1062
jhon309 0:c52df770855b 1063 /******************* Bit definition for CAN_TDL1R register ******************/
jhon309 0:c52df770855b 1064 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
jhon309 0:c52df770855b 1065 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
jhon309 0:c52df770855b 1066 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
jhon309 0:c52df770855b 1067 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
jhon309 0:c52df770855b 1068
jhon309 0:c52df770855b 1069 /******************* Bit definition for CAN_TDH1R register ******************/
jhon309 0:c52df770855b 1070 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
jhon309 0:c52df770855b 1071 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
jhon309 0:c52df770855b 1072 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
jhon309 0:c52df770855b 1073 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
jhon309 0:c52df770855b 1074
jhon309 0:c52df770855b 1075 /******************* Bit definition for CAN_TI2R register *******************/
jhon309 0:c52df770855b 1076 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
jhon309 0:c52df770855b 1077 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
jhon309 0:c52df770855b 1078 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
jhon309 0:c52df770855b 1079 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
jhon309 0:c52df770855b 1080 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
jhon309 0:c52df770855b 1081
jhon309 0:c52df770855b 1082 /******************* Bit definition for CAN_TDT2R register ******************/
jhon309 0:c52df770855b 1083 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
jhon309 0:c52df770855b 1084 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
jhon309 0:c52df770855b 1085 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
jhon309 0:c52df770855b 1086
jhon309 0:c52df770855b 1087 /******************* Bit definition for CAN_TDL2R register ******************/
jhon309 0:c52df770855b 1088 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
jhon309 0:c52df770855b 1089 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
jhon309 0:c52df770855b 1090 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
jhon309 0:c52df770855b 1091 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
jhon309 0:c52df770855b 1092
jhon309 0:c52df770855b 1093 /******************* Bit definition for CAN_TDH2R register ******************/
jhon309 0:c52df770855b 1094 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
jhon309 0:c52df770855b 1095 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
jhon309 0:c52df770855b 1096 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
jhon309 0:c52df770855b 1097 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
jhon309 0:c52df770855b 1098
jhon309 0:c52df770855b 1099 /******************* Bit definition for CAN_RI0R register *******************/
jhon309 0:c52df770855b 1100 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
jhon309 0:c52df770855b 1101 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
jhon309 0:c52df770855b 1102 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
jhon309 0:c52df770855b 1103 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
jhon309 0:c52df770855b 1104
jhon309 0:c52df770855b 1105 /******************* Bit definition for CAN_RDT0R register ******************/
jhon309 0:c52df770855b 1106 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
jhon309 0:c52df770855b 1107 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
jhon309 0:c52df770855b 1108 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
jhon309 0:c52df770855b 1109
jhon309 0:c52df770855b 1110 /******************* Bit definition for CAN_RDL0R register ******************/
jhon309 0:c52df770855b 1111 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
jhon309 0:c52df770855b 1112 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
jhon309 0:c52df770855b 1113 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
jhon309 0:c52df770855b 1114 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
jhon309 0:c52df770855b 1115
jhon309 0:c52df770855b 1116 /******************* Bit definition for CAN_RDH0R register ******************/
jhon309 0:c52df770855b 1117 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
jhon309 0:c52df770855b 1118 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
jhon309 0:c52df770855b 1119 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
jhon309 0:c52df770855b 1120 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
jhon309 0:c52df770855b 1121
jhon309 0:c52df770855b 1122 /******************* Bit definition for CAN_RI1R register *******************/
jhon309 0:c52df770855b 1123 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
jhon309 0:c52df770855b 1124 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
jhon309 0:c52df770855b 1125 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
jhon309 0:c52df770855b 1126 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
jhon309 0:c52df770855b 1127
jhon309 0:c52df770855b 1128 /******************* Bit definition for CAN_RDT1R register ******************/
jhon309 0:c52df770855b 1129 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
jhon309 0:c52df770855b 1130 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
jhon309 0:c52df770855b 1131 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
jhon309 0:c52df770855b 1132
jhon309 0:c52df770855b 1133 /******************* Bit definition for CAN_RDL1R register ******************/
jhon309 0:c52df770855b 1134 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
jhon309 0:c52df770855b 1135 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
jhon309 0:c52df770855b 1136 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
jhon309 0:c52df770855b 1137 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
jhon309 0:c52df770855b 1138
jhon309 0:c52df770855b 1139 /******************* Bit definition for CAN_RDH1R register ******************/
jhon309 0:c52df770855b 1140 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
jhon309 0:c52df770855b 1141 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
jhon309 0:c52df770855b 1142 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
jhon309 0:c52df770855b 1143 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
jhon309 0:c52df770855b 1144
jhon309 0:c52df770855b 1145 /*!<CAN filter registers */
jhon309 0:c52df770855b 1146 /******************* Bit definition for CAN_FMR register ********************/
jhon309 0:c52df770855b 1147 #define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
jhon309 0:c52df770855b 1148
jhon309 0:c52df770855b 1149 /******************* Bit definition for CAN_FM1R register *******************/
jhon309 0:c52df770855b 1150 #define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
jhon309 0:c52df770855b 1151 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
jhon309 0:c52df770855b 1152 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
jhon309 0:c52df770855b 1153 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
jhon309 0:c52df770855b 1154 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
jhon309 0:c52df770855b 1155 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
jhon309 0:c52df770855b 1156 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
jhon309 0:c52df770855b 1157 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
jhon309 0:c52df770855b 1158 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
jhon309 0:c52df770855b 1159 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
jhon309 0:c52df770855b 1160 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
jhon309 0:c52df770855b 1161 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
jhon309 0:c52df770855b 1162 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
jhon309 0:c52df770855b 1163 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
jhon309 0:c52df770855b 1164 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
jhon309 0:c52df770855b 1165
jhon309 0:c52df770855b 1166 /******************* Bit definition for CAN_FS1R register *******************/
jhon309 0:c52df770855b 1167 #define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
jhon309 0:c52df770855b 1168 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
jhon309 0:c52df770855b 1169 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
jhon309 0:c52df770855b 1170 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
jhon309 0:c52df770855b 1171 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
jhon309 0:c52df770855b 1172 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
jhon309 0:c52df770855b 1173 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
jhon309 0:c52df770855b 1174 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
jhon309 0:c52df770855b 1175 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
jhon309 0:c52df770855b 1176 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
jhon309 0:c52df770855b 1177 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
jhon309 0:c52df770855b 1178 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
jhon309 0:c52df770855b 1179 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
jhon309 0:c52df770855b 1180 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
jhon309 0:c52df770855b 1181 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
jhon309 0:c52df770855b 1182
jhon309 0:c52df770855b 1183 /****************** Bit definition for CAN_FFA1R register *******************/
jhon309 0:c52df770855b 1184 #define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
jhon309 0:c52df770855b 1185 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
jhon309 0:c52df770855b 1186 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
jhon309 0:c52df770855b 1187 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
jhon309 0:c52df770855b 1188 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
jhon309 0:c52df770855b 1189 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
jhon309 0:c52df770855b 1190 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
jhon309 0:c52df770855b 1191 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
jhon309 0:c52df770855b 1192 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
jhon309 0:c52df770855b 1193 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
jhon309 0:c52df770855b 1194 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
jhon309 0:c52df770855b 1195 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
jhon309 0:c52df770855b 1196 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
jhon309 0:c52df770855b 1197 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
jhon309 0:c52df770855b 1198 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
jhon309 0:c52df770855b 1199
jhon309 0:c52df770855b 1200 /******************* Bit definition for CAN_FA1R register *******************/
jhon309 0:c52df770855b 1201 #define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
jhon309 0:c52df770855b 1202 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
jhon309 0:c52df770855b 1203 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
jhon309 0:c52df770855b 1204 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
jhon309 0:c52df770855b 1205 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
jhon309 0:c52df770855b 1206 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
jhon309 0:c52df770855b 1207 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
jhon309 0:c52df770855b 1208 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
jhon309 0:c52df770855b 1209 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
jhon309 0:c52df770855b 1210 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
jhon309 0:c52df770855b 1211 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
jhon309 0:c52df770855b 1212 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
jhon309 0:c52df770855b 1213 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
jhon309 0:c52df770855b 1214 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
jhon309 0:c52df770855b 1215 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
jhon309 0:c52df770855b 1216
jhon309 0:c52df770855b 1217 /******************* Bit definition for CAN_F0R1 register *******************/
jhon309 0:c52df770855b 1218 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 1219 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 1220 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 1221 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 1222 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 1223 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 1224 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 1225 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 1226 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 1227 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 1228 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 1229 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 1230 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 1231 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 1232 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 1233 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 1234 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 1235 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 1236 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 1237 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 1238 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 1239 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 1240 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 1241 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 1242 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 1243 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 1244 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 1245 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 1246 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 1247 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 1248 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 1249 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 1250
jhon309 0:c52df770855b 1251 /******************* Bit definition for CAN_F1R1 register *******************/
jhon309 0:c52df770855b 1252 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 1253 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 1254 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 1255 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 1256 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 1257 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 1258 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 1259 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 1260 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 1261 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 1262 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 1263 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 1264 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 1265 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 1266 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 1267 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 1268 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 1269 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 1270 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 1271 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 1272 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 1273 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 1274 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 1275 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 1276 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 1277 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 1278 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 1279 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 1280 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 1281 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 1282 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 1283 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 1284
jhon309 0:c52df770855b 1285 /******************* Bit definition for CAN_F2R1 register *******************/
jhon309 0:c52df770855b 1286 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 1287 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 1288 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 1289 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 1290 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 1291 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 1292 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 1293 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 1294 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 1295 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 1296 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 1297 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 1298 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 1299 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 1300 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 1301 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 1302 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 1303 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 1304 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 1305 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 1306 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 1307 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 1308 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 1309 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 1310 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 1311 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 1312 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 1313 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 1314 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 1315 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 1316 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 1317 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 1318
jhon309 0:c52df770855b 1319 /******************* Bit definition for CAN_F3R1 register *******************/
jhon309 0:c52df770855b 1320 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 1321 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 1322 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 1323 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 1324 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 1325 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 1326 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 1327 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 1328 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 1329 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 1330 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 1331 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 1332 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 1333 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 1334 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 1335 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 1336 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 1337 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 1338 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 1339 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 1340 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 1341 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 1342 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 1343 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 1344 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 1345 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 1346 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 1347 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 1348 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 1349 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 1350 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 1351 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 1352
jhon309 0:c52df770855b 1353 /******************* Bit definition for CAN_F4R1 register *******************/
jhon309 0:c52df770855b 1354 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 1355 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 1356 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 1357 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 1358 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 1359 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 1360 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 1361 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 1362 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 1363 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 1364 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 1365 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 1366 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 1367 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 1368 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 1369 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 1370 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 1371 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 1372 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 1373 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 1374 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 1375 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 1376 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 1377 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 1378 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 1379 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 1380 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 1381 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 1382 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 1383 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 1384 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 1385 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 1386
jhon309 0:c52df770855b 1387 /******************* Bit definition for CAN_F5R1 register *******************/
jhon309 0:c52df770855b 1388 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 1389 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 1390 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 1391 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 1392 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 1393 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 1394 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 1395 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 1396 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 1397 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 1398 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 1399 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 1400 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 1401 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 1402 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 1403 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 1404 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 1405 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 1406 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 1407 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 1408 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 1409 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 1410 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 1411 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 1412 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 1413 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 1414 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 1415 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 1416 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 1417 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 1418 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 1419 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 1420
jhon309 0:c52df770855b 1421 /******************* Bit definition for CAN_F6R1 register *******************/
jhon309 0:c52df770855b 1422 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 1423 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 1424 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 1425 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 1426 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 1427 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 1428 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 1429 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 1430 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 1431 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 1432 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 1433 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 1434 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 1435 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 1436 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 1437 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 1438 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 1439 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 1440 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 1441 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 1442 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 1443 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 1444 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 1445 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 1446 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 1447 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 1448 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 1449 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 1450 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 1451 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 1452 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 1453 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 1454
jhon309 0:c52df770855b 1455 /******************* Bit definition for CAN_F7R1 register *******************/
jhon309 0:c52df770855b 1456 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 1457 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 1458 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 1459 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 1460 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 1461 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 1462 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 1463 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 1464 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 1465 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 1466 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 1467 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 1468 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 1469 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 1470 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 1471 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 1472 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 1473 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 1474 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 1475 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 1476 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 1477 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 1478 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 1479 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 1480 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 1481 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 1482 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 1483 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 1484 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 1485 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 1486 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 1487 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 1488
jhon309 0:c52df770855b 1489 /******************* Bit definition for CAN_F8R1 register *******************/
jhon309 0:c52df770855b 1490 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 1491 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 1492 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 1493 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 1494 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 1495 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 1496 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 1497 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 1498 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 1499 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 1500 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 1501 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 1502 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 1503 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 1504 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 1505 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 1506 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 1507 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 1508 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 1509 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 1510 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 1511 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 1512 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 1513 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 1514 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 1515 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 1516 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 1517 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 1518 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 1519 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 1520 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 1521 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 1522
jhon309 0:c52df770855b 1523 /******************* Bit definition for CAN_F9R1 register *******************/
jhon309 0:c52df770855b 1524 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 1525 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 1526 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 1527 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 1528 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 1529 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 1530 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 1531 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 1532 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 1533 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 1534 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 1535 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 1536 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 1537 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 1538 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 1539 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 1540 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 1541 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 1542 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 1543 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 1544 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 1545 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 1546 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 1547 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 1548 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 1549 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 1550 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 1551 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 1552 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 1553 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 1554 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 1555 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 1556
jhon309 0:c52df770855b 1557 /******************* Bit definition for CAN_F10R1 register ******************/
jhon309 0:c52df770855b 1558 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 1559 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 1560 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 1561 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 1562 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 1563 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 1564 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 1565 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 1566 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 1567 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 1568 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 1569 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 1570 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 1571 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 1572 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 1573 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 1574 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 1575 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 1576 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 1577 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 1578 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 1579 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 1580 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 1581 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 1582 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 1583 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 1584 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 1585 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 1586 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 1587 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 1588 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 1589 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 1590
jhon309 0:c52df770855b 1591 /******************* Bit definition for CAN_F11R1 register ******************/
jhon309 0:c52df770855b 1592 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 1593 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 1594 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 1595 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 1596 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 1597 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 1598 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 1599 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 1600 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 1601 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 1602 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 1603 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 1604 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 1605 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 1606 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 1607 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 1608 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 1609 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 1610 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 1611 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 1612 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 1613 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 1614 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 1615 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 1616 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 1617 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 1618 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 1619 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 1620 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 1621 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 1622 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 1623 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 1624
jhon309 0:c52df770855b 1625 /******************* Bit definition for CAN_F12R1 register ******************/
jhon309 0:c52df770855b 1626 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 1627 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 1628 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 1629 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 1630 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 1631 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 1632 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 1633 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 1634 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 1635 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 1636 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 1637 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 1638 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 1639 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 1640 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 1641 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 1642 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 1643 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 1644 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 1645 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 1646 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 1647 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 1648 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 1649 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 1650 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 1651 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 1652 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 1653 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 1654 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 1655 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 1656 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 1657 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 1658
jhon309 0:c52df770855b 1659 /******************* Bit definition for CAN_F13R1 register ******************/
jhon309 0:c52df770855b 1660 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 1661 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 1662 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 1663 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 1664 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 1665 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 1666 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 1667 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 1668 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 1669 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 1670 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 1671 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 1672 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 1673 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 1674 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 1675 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 1676 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 1677 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 1678 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 1679 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 1680 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 1681 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 1682 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 1683 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 1684 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 1685 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 1686 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 1687 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 1688 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 1689 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 1690 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 1691 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 1692
jhon309 0:c52df770855b 1693 /******************* Bit definition for CAN_F0R2 register *******************/
jhon309 0:c52df770855b 1694 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 1695 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 1696 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 1697 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 1698 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 1699 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 1700 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 1701 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 1702 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 1703 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 1704 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 1705 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 1706 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 1707 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 1708 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 1709 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 1710 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 1711 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 1712 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 1713 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 1714 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 1715 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 1716 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 1717 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 1718 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 1719 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 1720 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 1721 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 1722 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 1723 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 1724 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 1725 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 1726
jhon309 0:c52df770855b 1727 /******************* Bit definition for CAN_F1R2 register *******************/
jhon309 0:c52df770855b 1728 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 1729 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 1730 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 1731 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 1732 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 1733 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 1734 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 1735 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 1736 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 1737 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 1738 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 1739 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 1740 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 1741 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 1742 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 1743 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 1744 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 1745 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 1746 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 1747 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 1748 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 1749 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 1750 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 1751 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 1752 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 1753 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 1754 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 1755 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 1756 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 1757 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 1758 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 1759 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 1760
jhon309 0:c52df770855b 1761 /******************* Bit definition for CAN_F2R2 register *******************/
jhon309 0:c52df770855b 1762 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 1763 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 1764 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 1765 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 1766 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 1767 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 1768 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 1769 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 1770 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 1771 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 1772 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 1773 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 1774 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 1775 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 1776 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 1777 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 1778 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 1779 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 1780 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 1781 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 1782 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 1783 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 1784 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 1785 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 1786 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 1787 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 1788 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 1789 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 1790 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 1791 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 1792 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 1793 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 1794
jhon309 0:c52df770855b 1795 /******************* Bit definition for CAN_F3R2 register *******************/
jhon309 0:c52df770855b 1796 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 1797 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 1798 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 1799 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 1800 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 1801 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 1802 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 1803 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 1804 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 1805 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 1806 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 1807 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 1808 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 1809 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 1810 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 1811 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 1812 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 1813 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 1814 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 1815 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 1816 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 1817 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 1818 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 1819 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 1820 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 1821 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 1822 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 1823 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 1824 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 1825 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 1826 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 1827 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 1828
jhon309 0:c52df770855b 1829 /******************* Bit definition for CAN_F4R2 register *******************/
jhon309 0:c52df770855b 1830 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 1831 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 1832 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 1833 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 1834 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 1835 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 1836 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 1837 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 1838 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 1839 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 1840 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 1841 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 1842 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 1843 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 1844 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 1845 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 1846 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 1847 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 1848 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 1849 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 1850 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 1851 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 1852 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 1853 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 1854 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 1855 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 1856 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 1857 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 1858 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 1859 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 1860 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 1861 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 1862
jhon309 0:c52df770855b 1863 /******************* Bit definition for CAN_F5R2 register *******************/
jhon309 0:c52df770855b 1864 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 1865 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 1866 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 1867 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 1868 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 1869 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 1870 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 1871 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 1872 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 1873 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 1874 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 1875 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 1876 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 1877 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 1878 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 1879 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 1880 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 1881 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 1882 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 1883 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 1884 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 1885 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 1886 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 1887 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 1888 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 1889 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 1890 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 1891 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 1892 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 1893 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 1894 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 1895 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 1896
jhon309 0:c52df770855b 1897 /******************* Bit definition for CAN_F6R2 register *******************/
jhon309 0:c52df770855b 1898 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 1899 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 1900 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 1901 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 1902 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 1903 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 1904 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 1905 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 1906 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 1907 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 1908 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 1909 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 1910 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 1911 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 1912 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 1913 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 1914 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 1915 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 1916 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 1917 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 1918 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 1919 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 1920 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 1921 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 1922 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 1923 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 1924 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 1925 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 1926 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 1927 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 1928 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 1929 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 1930
jhon309 0:c52df770855b 1931 /******************* Bit definition for CAN_F7R2 register *******************/
jhon309 0:c52df770855b 1932 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 1933 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 1934 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 1935 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 1936 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 1937 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 1938 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 1939 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 1940 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 1941 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 1942 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 1943 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 1944 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 1945 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 1946 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 1947 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 1948 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 1949 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 1950 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 1951 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 1952 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 1953 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 1954 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 1955 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 1956 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 1957 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 1958 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 1959 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 1960 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 1961 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 1962 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 1963 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 1964
jhon309 0:c52df770855b 1965 /******************* Bit definition for CAN_F8R2 register *******************/
jhon309 0:c52df770855b 1966 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 1967 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 1968 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 1969 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 1970 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 1971 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 1972 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 1973 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 1974 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 1975 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 1976 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 1977 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 1978 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 1979 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 1980 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 1981 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 1982 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 1983 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 1984 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 1985 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 1986 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 1987 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 1988 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 1989 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 1990 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 1991 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 1992 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 1993 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 1994 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 1995 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 1996 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 1997 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 1998
jhon309 0:c52df770855b 1999 /******************* Bit definition for CAN_F9R2 register *******************/
jhon309 0:c52df770855b 2000 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 2001 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 2002 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 2003 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 2004 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 2005 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 2006 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 2007 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 2008 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 2009 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 2010 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 2011 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 2012 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 2013 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 2014 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 2015 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 2016 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 2017 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 2018 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 2019 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 2020 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 2021 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 2022 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 2023 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 2024 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 2025 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 2026 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 2027 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 2028 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 2029 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 2030 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 2031 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 2032
jhon309 0:c52df770855b 2033 /******************* Bit definition for CAN_F10R2 register ******************/
jhon309 0:c52df770855b 2034 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 2035 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 2036 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 2037 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 2038 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 2039 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 2040 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 2041 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 2042 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 2043 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 2044 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 2045 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 2046 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 2047 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 2048 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 2049 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 2050 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 2051 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 2052 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 2053 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 2054 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 2055 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 2056 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 2057 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 2058 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 2059 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 2060 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 2061 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 2062 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 2063 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 2064 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 2065 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 2066
jhon309 0:c52df770855b 2067 /******************* Bit definition for CAN_F11R2 register ******************/
jhon309 0:c52df770855b 2068 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 2069 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 2070 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 2071 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 2072 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 2073 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 2074 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 2075 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 2076 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 2077 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 2078 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 2079 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 2080 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 2081 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 2082 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 2083 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 2084 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 2085 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 2086 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 2087 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 2088 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 2089 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 2090 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 2091 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 2092 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 2093 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 2094 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 2095 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 2096 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 2097 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 2098 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 2099 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 2100
jhon309 0:c52df770855b 2101 /******************* Bit definition for CAN_F12R2 register ******************/
jhon309 0:c52df770855b 2102 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 2103 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 2104 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 2105 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 2106 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 2107 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 2108 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 2109 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 2110 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 2111 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 2112 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 2113 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 2114 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 2115 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 2116 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 2117 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 2118 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 2119 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 2120 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 2121 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 2122 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 2123 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 2124 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 2125 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 2126 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 2127 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 2128 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 2129 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 2130 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 2131 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 2132 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 2133 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 2134
jhon309 0:c52df770855b 2135 /******************* Bit definition for CAN_F13R2 register ******************/
jhon309 0:c52df770855b 2136 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
jhon309 0:c52df770855b 2137 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
jhon309 0:c52df770855b 2138 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
jhon309 0:c52df770855b 2139 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
jhon309 0:c52df770855b 2140 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
jhon309 0:c52df770855b 2141 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
jhon309 0:c52df770855b 2142 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
jhon309 0:c52df770855b 2143 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
jhon309 0:c52df770855b 2144 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
jhon309 0:c52df770855b 2145 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
jhon309 0:c52df770855b 2146 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
jhon309 0:c52df770855b 2147 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
jhon309 0:c52df770855b 2148 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
jhon309 0:c52df770855b 2149 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
jhon309 0:c52df770855b 2150 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
jhon309 0:c52df770855b 2151 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
jhon309 0:c52df770855b 2152 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
jhon309 0:c52df770855b 2153 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
jhon309 0:c52df770855b 2154 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
jhon309 0:c52df770855b 2155 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
jhon309 0:c52df770855b 2156 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
jhon309 0:c52df770855b 2157 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
jhon309 0:c52df770855b 2158 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
jhon309 0:c52df770855b 2159 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
jhon309 0:c52df770855b 2160 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
jhon309 0:c52df770855b 2161 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
jhon309 0:c52df770855b 2162 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
jhon309 0:c52df770855b 2163 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
jhon309 0:c52df770855b 2164 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
jhon309 0:c52df770855b 2165 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
jhon309 0:c52df770855b 2166 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
jhon309 0:c52df770855b 2167 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
jhon309 0:c52df770855b 2168
jhon309 0:c52df770855b 2169 /******************************************************************************/
jhon309 0:c52df770855b 2170 /* */
jhon309 0:c52df770855b 2171 /* HDMI-CEC (CEC) */
jhon309 0:c52df770855b 2172 /* */
jhon309 0:c52df770855b 2173 /******************************************************************************/
jhon309 0:c52df770855b 2174
jhon309 0:c52df770855b 2175 /******************* Bit definition for CEC_CR register *********************/
jhon309 0:c52df770855b 2176 #define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
jhon309 0:c52df770855b 2177 #define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
jhon309 0:c52df770855b 2178 #define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
jhon309 0:c52df770855b 2179
jhon309 0:c52df770855b 2180 /******************* Bit definition for CEC_CFGR register *******************/
jhon309 0:c52df770855b 2181 #define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
jhon309 0:c52df770855b 2182 #define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
jhon309 0:c52df770855b 2183 #define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
jhon309 0:c52df770855b 2184 #define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
jhon309 0:c52df770855b 2185 #define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Bit Period Error gener. */
jhon309 0:c52df770855b 2186 #define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast No Error generation */
jhon309 0:c52df770855b 2187 #define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
jhon309 0:c52df770855b 2188 #define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
jhon309 0:c52df770855b 2189 #define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
jhon309 0:c52df770855b 2190
jhon309 0:c52df770855b 2191 /******************* Bit definition for CEC_TXDR register *******************/
jhon309 0:c52df770855b 2192 #define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
jhon309 0:c52df770855b 2193
jhon309 0:c52df770855b 2194 /******************* Bit definition for CEC_RXDR register *******************/
jhon309 0:c52df770855b 2195 #define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
jhon309 0:c52df770855b 2196
jhon309 0:c52df770855b 2197 /******************* Bit definition for CEC_ISR register ********************/
jhon309 0:c52df770855b 2198 #define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
jhon309 0:c52df770855b 2199 #define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
jhon309 0:c52df770855b 2200 #define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
jhon309 0:c52df770855b 2201 #define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
jhon309 0:c52df770855b 2202 #define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
jhon309 0:c52df770855b 2203 #define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
jhon309 0:c52df770855b 2204 #define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
jhon309 0:c52df770855b 2205 #define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
jhon309 0:c52df770855b 2206 #define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
jhon309 0:c52df770855b 2207 #define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
jhon309 0:c52df770855b 2208 #define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
jhon309 0:c52df770855b 2209 #define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
jhon309 0:c52df770855b 2210 #define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
jhon309 0:c52df770855b 2211
jhon309 0:c52df770855b 2212 /******************* Bit definition for CEC_IER register ********************/
jhon309 0:c52df770855b 2213 #define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
jhon309 0:c52df770855b 2214 #define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
jhon309 0:c52df770855b 2215 #define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
jhon309 0:c52df770855b 2216 #define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
jhon309 0:c52df770855b 2217 #define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/
jhon309 0:c52df770855b 2218 #define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
jhon309 0:c52df770855b 2219 #define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
jhon309 0:c52df770855b 2220 #define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
jhon309 0:c52df770855b 2221 #define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
jhon309 0:c52df770855b 2222 #define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
jhon309 0:c52df770855b 2223 #define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
jhon309 0:c52df770855b 2224 #define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
jhon309 0:c52df770855b 2225 #define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
jhon309 0:c52df770855b 2226
jhon309 0:c52df770855b 2227
jhon309 0:c52df770855b 2228 /******************************************************************************/
jhon309 0:c52df770855b 2229 /* */
jhon309 0:c52df770855b 2230 /* Analog Comparators (COMP) */
jhon309 0:c52df770855b 2231 /* */
jhon309 0:c52df770855b 2232 /******************************************************************************/
jhon309 0:c52df770855b 2233 /*********************** Bit definition for COMP_CSR register ***************/
jhon309 0:c52df770855b 2234 /* COMP1 bits definition */
jhon309 0:c52df770855b 2235 #define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
jhon309 0:c52df770855b 2236 #define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< SW1 switch control */
jhon309 0:c52df770855b 2237 #define COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */
jhon309 0:c52df770855b 2238 #define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
jhon309 0:c52df770855b 2239 #define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
jhon309 0:c52df770855b 2240 #define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
jhon309 0:c52df770855b 2241 #define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
jhon309 0:c52df770855b 2242 #define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
jhon309 0:c52df770855b 2243 #define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
jhon309 0:c52df770855b 2244 #define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) /*!< COMP1 output select */
jhon309 0:c52df770855b 2245 #define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
jhon309 0:c52df770855b 2246 #define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
jhon309 0:c52df770855b 2247 #define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
jhon309 0:c52df770855b 2248 #define COMP_CSR_COMP1POL ((uint32_t)0x00000800) /*!< COMP1 output polarity */
jhon309 0:c52df770855b 2249 #define COMP_CSR_COMP1HYST ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
jhon309 0:c52df770855b 2250 #define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
jhon309 0:c52df770855b 2251 #define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
jhon309 0:c52df770855b 2252 #define COMP_CSR_COMP1OUT ((uint32_t)0x00004000) /*!< COMP1 output level */
jhon309 0:c52df770855b 2253 #define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) /*!< COMP1 lock */
jhon309 0:c52df770855b 2254 /* COMP2 bits definition */
jhon309 0:c52df770855b 2255 #define COMP_CSR_COMP2EN ((uint32_t)0x00010000) /*!< COMP2 enable */
jhon309 0:c52df770855b 2256 #define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) /*!< COMP2 power mode */
jhon309 0:c52df770855b 2257 #define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
jhon309 0:c52df770855b 2258 #define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
jhon309 0:c52df770855b 2259 #define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
jhon309 0:c52df770855b 2260 #define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
jhon309 0:c52df770855b 2261 #define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
jhon309 0:c52df770855b 2262 #define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
jhon309 0:c52df770855b 2263 #define COMP_CSR_WNDWEN ((uint32_t)0x00800000) /*!< Comparators window mode enable */
jhon309 0:c52df770855b 2264 #define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) /*!< COMP2 output select */
jhon309 0:c52df770855b 2265 #define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
jhon309 0:c52df770855b 2266 #define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
jhon309 0:c52df770855b 2267 #define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
jhon309 0:c52df770855b 2268 #define COMP_CSR_COMP2POL ((uint32_t)0x08000000) /*!< COMP2 output polarity */
jhon309 0:c52df770855b 2269 #define COMP_CSR_COMP2HYST ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
jhon309 0:c52df770855b 2270 #define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
jhon309 0:c52df770855b 2271 #define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
jhon309 0:c52df770855b 2272 #define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
jhon309 0:c52df770855b 2273 #define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
jhon309 0:c52df770855b 2274 /* COMPx bits definition */
jhon309 0:c52df770855b 2275 #define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */
jhon309 0:c52df770855b 2276 #define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */
jhon309 0:c52df770855b 2277 #define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */
jhon309 0:c52df770855b 2278 #define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */
jhon309 0:c52df770855b 2279 #define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */
jhon309 0:c52df770855b 2280 #define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */
jhon309 0:c52df770855b 2281 #define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */
jhon309 0:c52df770855b 2282 #define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */
jhon309 0:c52df770855b 2283 #define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */
jhon309 0:c52df770855b 2284 #define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */
jhon309 0:c52df770855b 2285 #define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */
jhon309 0:c52df770855b 2286 #define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */
jhon309 0:c52df770855b 2287 #define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */
jhon309 0:c52df770855b 2288 #define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */
jhon309 0:c52df770855b 2289 #define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */
jhon309 0:c52df770855b 2290 #define COMP_CSR_COMPxHYST_1 ((uint16_t)0x2000) /*!< COMPx hysteresis bit 1 */
jhon309 0:c52df770855b 2291 #define COMP_CSR_COMPxOUT ((uint16_t)0x4000) /*!< COMPx output level */
jhon309 0:c52df770855b 2292 #define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */
jhon309 0:c52df770855b 2293
jhon309 0:c52df770855b 2294 /******************************************************************************/
jhon309 0:c52df770855b 2295 /* */
jhon309 0:c52df770855b 2296 /* CRC calculation unit (CRC) */
jhon309 0:c52df770855b 2297 /* */
jhon309 0:c52df770855b 2298 /******************************************************************************/
jhon309 0:c52df770855b 2299 /******************* Bit definition for CRC_DR register *********************/
jhon309 0:c52df770855b 2300 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
jhon309 0:c52df770855b 2301
jhon309 0:c52df770855b 2302 /******************* Bit definition for CRC_IDR register ********************/
jhon309 0:c52df770855b 2303 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
jhon309 0:c52df770855b 2304
jhon309 0:c52df770855b 2305 /******************** Bit definition for CRC_CR register ********************/
jhon309 0:c52df770855b 2306 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
jhon309 0:c52df770855b 2307 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
jhon309 0:c52df770855b 2308 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
jhon309 0:c52df770855b 2309 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
jhon309 0:c52df770855b 2310 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
jhon309 0:c52df770855b 2311 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
jhon309 0:c52df770855b 2312 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
jhon309 0:c52df770855b 2313 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
jhon309 0:c52df770855b 2314
jhon309 0:c52df770855b 2315 /******************* Bit definition for CRC_INIT register *******************/
jhon309 0:c52df770855b 2316 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
jhon309 0:c52df770855b 2317
jhon309 0:c52df770855b 2318 /******************* Bit definition for CRC_POL register ********************/
jhon309 0:c52df770855b 2319 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
jhon309 0:c52df770855b 2320
jhon309 0:c52df770855b 2321 /******************************************************************************/
jhon309 0:c52df770855b 2322 /* */
jhon309 0:c52df770855b 2323 /* CRS Clock Recovery System */
jhon309 0:c52df770855b 2324 /******************************************************************************/
jhon309 0:c52df770855b 2325
jhon309 0:c52df770855b 2326 /******************* Bit definition for CRS_CR register *********************/
jhon309 0:c52df770855b 2327 #define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
jhon309 0:c52df770855b 2328 #define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
jhon309 0:c52df770855b 2329 #define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
jhon309 0:c52df770855b 2330 #define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
jhon309 0:c52df770855b 2331 #define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
jhon309 0:c52df770855b 2332 #define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
jhon309 0:c52df770855b 2333 #define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
jhon309 0:c52df770855b 2334 #define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
jhon309 0:c52df770855b 2335
jhon309 0:c52df770855b 2336 /******************* Bit definition for CRS_CFGR register *********************/
jhon309 0:c52df770855b 2337 #define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
jhon309 0:c52df770855b 2338 #define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
jhon309 0:c52df770855b 2339
jhon309 0:c52df770855b 2340 #define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
jhon309 0:c52df770855b 2341 #define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
jhon309 0:c52df770855b 2342 #define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
jhon309 0:c52df770855b 2343 #define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
jhon309 0:c52df770855b 2344
jhon309 0:c52df770855b 2345 #define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
jhon309 0:c52df770855b 2346 #define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
jhon309 0:c52df770855b 2347 #define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
jhon309 0:c52df770855b 2348
jhon309 0:c52df770855b 2349 #define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
jhon309 0:c52df770855b 2350
jhon309 0:c52df770855b 2351 /******************* Bit definition for CRS_ISR register *********************/
jhon309 0:c52df770855b 2352 #define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
jhon309 0:c52df770855b 2353 #define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
jhon309 0:c52df770855b 2354 #define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
jhon309 0:c52df770855b 2355 #define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
jhon309 0:c52df770855b 2356 #define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
jhon309 0:c52df770855b 2357 #define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
jhon309 0:c52df770855b 2358 #define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
jhon309 0:c52df770855b 2359 #define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
jhon309 0:c52df770855b 2360 #define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
jhon309 0:c52df770855b 2361
jhon309 0:c52df770855b 2362 /******************* Bit definition for CRS_ICR register *********************/
jhon309 0:c52df770855b 2363 #define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
jhon309 0:c52df770855b 2364 #define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
jhon309 0:c52df770855b 2365 #define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
jhon309 0:c52df770855b 2366 #define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
jhon309 0:c52df770855b 2367
jhon309 0:c52df770855b 2368 /******************************************************************************/
jhon309 0:c52df770855b 2369 /* */
jhon309 0:c52df770855b 2370 /* Digital to Analog Converter (DAC) */
jhon309 0:c52df770855b 2371 /* */
jhon309 0:c52df770855b 2372 /******************************************************************************/
jhon309 0:c52df770855b 2373 /******************** Bit definition for DAC_CR register ********************/
jhon309 0:c52df770855b 2374 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
jhon309 0:c52df770855b 2375 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
jhon309 0:c52df770855b 2376 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
jhon309 0:c52df770855b 2377
jhon309 0:c52df770855b 2378 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
jhon309 0:c52df770855b 2379 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
jhon309 0:c52df770855b 2380 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
jhon309 0:c52df770855b 2381 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
jhon309 0:c52df770855b 2382
jhon309 0:c52df770855b 2383 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
jhon309 0:c52df770855b 2384 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
jhon309 0:c52df770855b 2385 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
jhon309 0:c52df770855b 2386
jhon309 0:c52df770855b 2387 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
jhon309 0:c52df770855b 2388 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
jhon309 0:c52df770855b 2389 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
jhon309 0:c52df770855b 2390 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
jhon309 0:c52df770855b 2391 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
jhon309 0:c52df770855b 2392
jhon309 0:c52df770855b 2393 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
jhon309 0:c52df770855b 2394 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA Underrun Interrupt enable */
jhon309 0:c52df770855b 2395
jhon309 0:c52df770855b 2396 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
jhon309 0:c52df770855b 2397 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
jhon309 0:c52df770855b 2398 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
jhon309 0:c52df770855b 2399
jhon309 0:c52df770855b 2400 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
jhon309 0:c52df770855b 2401 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
jhon309 0:c52df770855b 2402 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
jhon309 0:c52df770855b 2403 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
jhon309 0:c52df770855b 2404
jhon309 0:c52df770855b 2405 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
jhon309 0:c52df770855b 2406 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
jhon309 0:c52df770855b 2407 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
jhon309 0:c52df770855b 2408
jhon309 0:c52df770855b 2409 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
jhon309 0:c52df770855b 2410 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
jhon309 0:c52df770855b 2411 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
jhon309 0:c52df770855b 2412 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
jhon309 0:c52df770855b 2413 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
jhon309 0:c52df770855b 2414
jhon309 0:c52df770855b 2415 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
jhon309 0:c52df770855b 2416 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA Underrun Interrupt enable */
jhon309 0:c52df770855b 2417
jhon309 0:c52df770855b 2418 /***************** Bit definition for DAC_SWTRIGR register ******************/
jhon309 0:c52df770855b 2419 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
jhon309 0:c52df770855b 2420 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
jhon309 0:c52df770855b 2421
jhon309 0:c52df770855b 2422 /***************** Bit definition for DAC_DHR12R1 register ******************/
jhon309 0:c52df770855b 2423 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
jhon309 0:c52df770855b 2424
jhon309 0:c52df770855b 2425 /***************** Bit definition for DAC_DHR12L1 register ******************/
jhon309 0:c52df770855b 2426 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
jhon309 0:c52df770855b 2427
jhon309 0:c52df770855b 2428 /****************** Bit definition for DAC_DHR8R1 register ******************/
jhon309 0:c52df770855b 2429 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
jhon309 0:c52df770855b 2430
jhon309 0:c52df770855b 2431 /***************** Bit definition for DAC_DHR12R2 register ******************/
jhon309 0:c52df770855b 2432 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
jhon309 0:c52df770855b 2433
jhon309 0:c52df770855b 2434 /***************** Bit definition for DAC_DHR12L2 register ******************/
jhon309 0:c52df770855b 2435 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
jhon309 0:c52df770855b 2436
jhon309 0:c52df770855b 2437 /****************** Bit definition for DAC_DHR8R2 register ******************/
jhon309 0:c52df770855b 2438 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
jhon309 0:c52df770855b 2439
jhon309 0:c52df770855b 2440 /***************** Bit definition for DAC_DHR12RD register ******************/
jhon309 0:c52df770855b 2441 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
jhon309 0:c52df770855b 2442 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
jhon309 0:c52df770855b 2443
jhon309 0:c52df770855b 2444 /***************** Bit definition for DAC_DHR12LD register ******************/
jhon309 0:c52df770855b 2445 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
jhon309 0:c52df770855b 2446 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
jhon309 0:c52df770855b 2447
jhon309 0:c52df770855b 2448 /****************** Bit definition for DAC_DHR8RD register ******************/
jhon309 0:c52df770855b 2449 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
jhon309 0:c52df770855b 2450 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
jhon309 0:c52df770855b 2451
jhon309 0:c52df770855b 2452 /******************* Bit definition for DAC_DOR1 register *******************/
jhon309 0:c52df770855b 2453 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
jhon309 0:c52df770855b 2454
jhon309 0:c52df770855b 2455 /******************* Bit definition for DAC_DOR2 register *******************/
jhon309 0:c52df770855b 2456 #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
jhon309 0:c52df770855b 2457
jhon309 0:c52df770855b 2458 /******************** Bit definition for DAC_SR register ********************/
jhon309 0:c52df770855b 2459 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
jhon309 0:c52df770855b 2460 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
jhon309 0:c52df770855b 2461
jhon309 0:c52df770855b 2462 /******************************************************************************/
jhon309 0:c52df770855b 2463 /* */
jhon309 0:c52df770855b 2464 /* Debug MCU (DBGMCU) */
jhon309 0:c52df770855b 2465 /* */
jhon309 0:c52df770855b 2466 /******************************************************************************/
jhon309 0:c52df770855b 2467
jhon309 0:c52df770855b 2468 /**************** Bit definition for DBGMCU_IDCODE register *****************/
jhon309 0:c52df770855b 2469 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
jhon309 0:c52df770855b 2470
jhon309 0:c52df770855b 2471 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
jhon309 0:c52df770855b 2472 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
jhon309 0:c52df770855b 2473 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
jhon309 0:c52df770855b 2474 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
jhon309 0:c52df770855b 2475 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
jhon309 0:c52df770855b 2476 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
jhon309 0:c52df770855b 2477 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
jhon309 0:c52df770855b 2478 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
jhon309 0:c52df770855b 2479 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
jhon309 0:c52df770855b 2480 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
jhon309 0:c52df770855b 2481 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
jhon309 0:c52df770855b 2482 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
jhon309 0:c52df770855b 2483 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
jhon309 0:c52df770855b 2484 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
jhon309 0:c52df770855b 2485 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
jhon309 0:c52df770855b 2486 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
jhon309 0:c52df770855b 2487 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
jhon309 0:c52df770855b 2488
jhon309 0:c52df770855b 2489 /****************** Bit definition for DBGMCU_CR register *******************/
jhon309 0:c52df770855b 2490 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
jhon309 0:c52df770855b 2491 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
jhon309 0:c52df770855b 2492
jhon309 0:c52df770855b 2493 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
jhon309 0:c52df770855b 2494 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
jhon309 0:c52df770855b 2495 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
jhon309 0:c52df770855b 2496 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
jhon309 0:c52df770855b 2497 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */
jhon309 0:c52df770855b 2498 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
jhon309 0:c52df770855b 2499 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
jhon309 0:c52df770855b 2500 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
jhon309 0:c52df770855b 2501 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
jhon309 0:c52df770855b 2502 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
jhon309 0:c52df770855b 2503 #define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000) /*!< CAN debug stopped when Core is halted */
jhon309 0:c52df770855b 2504
jhon309 0:c52df770855b 2505 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
jhon309 0:c52df770855b 2506 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
jhon309 0:c52df770855b 2507 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted */
jhon309 0:c52df770855b 2508 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
jhon309 0:c52df770855b 2509 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
jhon309 0:c52df770855b 2510
jhon309 0:c52df770855b 2511 /******************************************************************************/
jhon309 0:c52df770855b 2512 /* */
jhon309 0:c52df770855b 2513 /* DMA Controller (DMA) */
jhon309 0:c52df770855b 2514 /* */
jhon309 0:c52df770855b 2515 /******************************************************************************/
jhon309 0:c52df770855b 2516 /******************* Bit definition for DMA_ISR register ********************/
jhon309 0:c52df770855b 2517 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
jhon309 0:c52df770855b 2518 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
jhon309 0:c52df770855b 2519 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
jhon309 0:c52df770855b 2520 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
jhon309 0:c52df770855b 2521 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
jhon309 0:c52df770855b 2522 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
jhon309 0:c52df770855b 2523 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
jhon309 0:c52df770855b 2524 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
jhon309 0:c52df770855b 2525 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
jhon309 0:c52df770855b 2526 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
jhon309 0:c52df770855b 2527 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
jhon309 0:c52df770855b 2528 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
jhon309 0:c52df770855b 2529 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
jhon309 0:c52df770855b 2530 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
jhon309 0:c52df770855b 2531 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
jhon309 0:c52df770855b 2532 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
jhon309 0:c52df770855b 2533 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
jhon309 0:c52df770855b 2534 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
jhon309 0:c52df770855b 2535 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
jhon309 0:c52df770855b 2536 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
jhon309 0:c52df770855b 2537 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
jhon309 0:c52df770855b 2538 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
jhon309 0:c52df770855b 2539 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
jhon309 0:c52df770855b 2540 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
jhon309 0:c52df770855b 2541 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
jhon309 0:c52df770855b 2542 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
jhon309 0:c52df770855b 2543 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
jhon309 0:c52df770855b 2544 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
jhon309 0:c52df770855b 2545
jhon309 0:c52df770855b 2546 /******************* Bit definition for DMA_IFCR register *******************/
jhon309 0:c52df770855b 2547 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
jhon309 0:c52df770855b 2548 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
jhon309 0:c52df770855b 2549 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
jhon309 0:c52df770855b 2550 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
jhon309 0:c52df770855b 2551 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
jhon309 0:c52df770855b 2552 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
jhon309 0:c52df770855b 2553 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
jhon309 0:c52df770855b 2554 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
jhon309 0:c52df770855b 2555 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
jhon309 0:c52df770855b 2556 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
jhon309 0:c52df770855b 2557 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
jhon309 0:c52df770855b 2558 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
jhon309 0:c52df770855b 2559 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
jhon309 0:c52df770855b 2560 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
jhon309 0:c52df770855b 2561 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
jhon309 0:c52df770855b 2562 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
jhon309 0:c52df770855b 2563 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
jhon309 0:c52df770855b 2564 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
jhon309 0:c52df770855b 2565 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
jhon309 0:c52df770855b 2566 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
jhon309 0:c52df770855b 2567 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
jhon309 0:c52df770855b 2568 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
jhon309 0:c52df770855b 2569 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
jhon309 0:c52df770855b 2570 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
jhon309 0:c52df770855b 2571 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
jhon309 0:c52df770855b 2572 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
jhon309 0:c52df770855b 2573 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
jhon309 0:c52df770855b 2574 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
jhon309 0:c52df770855b 2575
jhon309 0:c52df770855b 2576 /******************* Bit definition for DMA_CCR register ********************/
jhon309 0:c52df770855b 2577 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
jhon309 0:c52df770855b 2578 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
jhon309 0:c52df770855b 2579 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
jhon309 0:c52df770855b 2580 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
jhon309 0:c52df770855b 2581 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
jhon309 0:c52df770855b 2582 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
jhon309 0:c52df770855b 2583 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
jhon309 0:c52df770855b 2584 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
jhon309 0:c52df770855b 2585
jhon309 0:c52df770855b 2586 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
jhon309 0:c52df770855b 2587 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
jhon309 0:c52df770855b 2588 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
jhon309 0:c52df770855b 2589
jhon309 0:c52df770855b 2590 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
jhon309 0:c52df770855b 2591 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
jhon309 0:c52df770855b 2592 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
jhon309 0:c52df770855b 2593
jhon309 0:c52df770855b 2594 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
jhon309 0:c52df770855b 2595 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
jhon309 0:c52df770855b 2596 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
jhon309 0:c52df770855b 2597
jhon309 0:c52df770855b 2598 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
jhon309 0:c52df770855b 2599
jhon309 0:c52df770855b 2600 /****************** Bit definition for DMA_CNDTR register *******************/
jhon309 0:c52df770855b 2601 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
jhon309 0:c52df770855b 2602
jhon309 0:c52df770855b 2603 /****************** Bit definition for DMA_CPAR register ********************/
jhon309 0:c52df770855b 2604 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
jhon309 0:c52df770855b 2605
jhon309 0:c52df770855b 2606 /****************** Bit definition for DMA_CMAR register ********************/
jhon309 0:c52df770855b 2607 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
jhon309 0:c52df770855b 2608
jhon309 0:c52df770855b 2609 /******************************************************************************/
jhon309 0:c52df770855b 2610 /* */
jhon309 0:c52df770855b 2611 /* External Interrupt/Event Controller (EXTI) */
jhon309 0:c52df770855b 2612 /* */
jhon309 0:c52df770855b 2613 /******************************************************************************/
jhon309 0:c52df770855b 2614 /******************* Bit definition for EXTI_IMR register *******************/
jhon309 0:c52df770855b 2615 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
jhon309 0:c52df770855b 2616 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
jhon309 0:c52df770855b 2617 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
jhon309 0:c52df770855b 2618 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
jhon309 0:c52df770855b 2619 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
jhon309 0:c52df770855b 2620 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
jhon309 0:c52df770855b 2621 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
jhon309 0:c52df770855b 2622 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
jhon309 0:c52df770855b 2623 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
jhon309 0:c52df770855b 2624 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
jhon309 0:c52df770855b 2625 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
jhon309 0:c52df770855b 2626 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
jhon309 0:c52df770855b 2627 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
jhon309 0:c52df770855b 2628 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
jhon309 0:c52df770855b 2629 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
jhon309 0:c52df770855b 2630 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
jhon309 0:c52df770855b 2631 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
jhon309 0:c52df770855b 2632 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
jhon309 0:c52df770855b 2633 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
jhon309 0:c52df770855b 2634 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
jhon309 0:c52df770855b 2635 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
jhon309 0:c52df770855b 2636 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
jhon309 0:c52df770855b 2637 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
jhon309 0:c52df770855b 2638 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
jhon309 0:c52df770855b 2639
jhon309 0:c52df770855b 2640 /****************** Bit definition for EXTI_EMR register ********************/
jhon309 0:c52df770855b 2641 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
jhon309 0:c52df770855b 2642 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
jhon309 0:c52df770855b 2643 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
jhon309 0:c52df770855b 2644 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
jhon309 0:c52df770855b 2645 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
jhon309 0:c52df770855b 2646 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
jhon309 0:c52df770855b 2647 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
jhon309 0:c52df770855b 2648 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
jhon309 0:c52df770855b 2649 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
jhon309 0:c52df770855b 2650 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
jhon309 0:c52df770855b 2651 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
jhon309 0:c52df770855b 2652 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
jhon309 0:c52df770855b 2653 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
jhon309 0:c52df770855b 2654 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
jhon309 0:c52df770855b 2655 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
jhon309 0:c52df770855b 2656 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
jhon309 0:c52df770855b 2657 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
jhon309 0:c52df770855b 2658 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
jhon309 0:c52df770855b 2659 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
jhon309 0:c52df770855b 2660 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
jhon309 0:c52df770855b 2661 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
jhon309 0:c52df770855b 2662 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
jhon309 0:c52df770855b 2663 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
jhon309 0:c52df770855b 2664 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
jhon309 0:c52df770855b 2665
jhon309 0:c52df770855b 2666 /******************* Bit definition for EXTI_RTSR register ******************/
jhon309 0:c52df770855b 2667 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
jhon309 0:c52df770855b 2668 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
jhon309 0:c52df770855b 2669 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
jhon309 0:c52df770855b 2670 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
jhon309 0:c52df770855b 2671 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
jhon309 0:c52df770855b 2672 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
jhon309 0:c52df770855b 2673 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
jhon309 0:c52df770855b 2674 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
jhon309 0:c52df770855b 2675 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
jhon309 0:c52df770855b 2676 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
jhon309 0:c52df770855b 2677 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
jhon309 0:c52df770855b 2678 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
jhon309 0:c52df770855b 2679 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
jhon309 0:c52df770855b 2680 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
jhon309 0:c52df770855b 2681 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
jhon309 0:c52df770855b 2682 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
jhon309 0:c52df770855b 2683 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
jhon309 0:c52df770855b 2684 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
jhon309 0:c52df770855b 2685 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
jhon309 0:c52df770855b 2686
jhon309 0:c52df770855b 2687 /******************* Bit definition for EXTI_FTSR register *******************/
jhon309 0:c52df770855b 2688 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
jhon309 0:c52df770855b 2689 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
jhon309 0:c52df770855b 2690 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
jhon309 0:c52df770855b 2691 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
jhon309 0:c52df770855b 2692 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
jhon309 0:c52df770855b 2693 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
jhon309 0:c52df770855b 2694 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
jhon309 0:c52df770855b 2695 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
jhon309 0:c52df770855b 2696 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
jhon309 0:c52df770855b 2697 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
jhon309 0:c52df770855b 2698 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
jhon309 0:c52df770855b 2699 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
jhon309 0:c52df770855b 2700 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
jhon309 0:c52df770855b 2701 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
jhon309 0:c52df770855b 2702 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
jhon309 0:c52df770855b 2703 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
jhon309 0:c52df770855b 2704 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
jhon309 0:c52df770855b 2705 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
jhon309 0:c52df770855b 2706 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
jhon309 0:c52df770855b 2707
jhon309 0:c52df770855b 2708 /******************* Bit definition for EXTI_SWIER register *******************/
jhon309 0:c52df770855b 2709 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
jhon309 0:c52df770855b 2710 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
jhon309 0:c52df770855b 2711 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
jhon309 0:c52df770855b 2712 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
jhon309 0:c52df770855b 2713 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
jhon309 0:c52df770855b 2714 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
jhon309 0:c52df770855b 2715 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
jhon309 0:c52df770855b 2716 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
jhon309 0:c52df770855b 2717 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
jhon309 0:c52df770855b 2718 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
jhon309 0:c52df770855b 2719 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
jhon309 0:c52df770855b 2720 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
jhon309 0:c52df770855b 2721 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
jhon309 0:c52df770855b 2722 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
jhon309 0:c52df770855b 2723 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
jhon309 0:c52df770855b 2724 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
jhon309 0:c52df770855b 2725 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
jhon309 0:c52df770855b 2726 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
jhon309 0:c52df770855b 2727 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
jhon309 0:c52df770855b 2728
jhon309 0:c52df770855b 2729 /****************** Bit definition for EXTI_PR register *********************/
jhon309 0:c52df770855b 2730 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
jhon309 0:c52df770855b 2731 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
jhon309 0:c52df770855b 2732 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
jhon309 0:c52df770855b 2733 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
jhon309 0:c52df770855b 2734 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
jhon309 0:c52df770855b 2735 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
jhon309 0:c52df770855b 2736 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
jhon309 0:c52df770855b 2737 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
jhon309 0:c52df770855b 2738 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
jhon309 0:c52df770855b 2739 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
jhon309 0:c52df770855b 2740 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
jhon309 0:c52df770855b 2741 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
jhon309 0:c52df770855b 2742 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
jhon309 0:c52df770855b 2743 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
jhon309 0:c52df770855b 2744 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
jhon309 0:c52df770855b 2745 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
jhon309 0:c52df770855b 2746 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
jhon309 0:c52df770855b 2747 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
jhon309 0:c52df770855b 2748 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
jhon309 0:c52df770855b 2749
jhon309 0:c52df770855b 2750 /******************************************************************************/
jhon309 0:c52df770855b 2751 /* */
jhon309 0:c52df770855b 2752 /* FLASH and Option Bytes Registers */
jhon309 0:c52df770855b 2753 /* */
jhon309 0:c52df770855b 2754 /******************************************************************************/
jhon309 0:c52df770855b 2755
jhon309 0:c52df770855b 2756 /******************* Bit definition for FLASH_ACR register ******************/
jhon309 0:c52df770855b 2757 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
jhon309 0:c52df770855b 2758
jhon309 0:c52df770855b 2759 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
jhon309 0:c52df770855b 2760 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
jhon309 0:c52df770855b 2761
jhon309 0:c52df770855b 2762 /****************** Bit definition for FLASH_KEYR register ******************/
jhon309 0:c52df770855b 2763 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
jhon309 0:c52df770855b 2764
jhon309 0:c52df770855b 2765 /***************** Bit definition for FLASH_OPTKEYR register ****************/
jhon309 0:c52df770855b 2766 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
jhon309 0:c52df770855b 2767
jhon309 0:c52df770855b 2768 /****************** FLASH Keys **********************************************/
jhon309 0:c52df770855b 2769 #define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
jhon309 0:c52df770855b 2770 #define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
jhon309 0:c52df770855b 2771 to unlock the write access to the FPEC. */
jhon309 0:c52df770855b 2772
jhon309 0:c52df770855b 2773 #define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
jhon309 0:c52df770855b 2774 #define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
jhon309 0:c52df770855b 2775 unlock the write access to the option byte block */
jhon309 0:c52df770855b 2776
jhon309 0:c52df770855b 2777 /****************** Bit definition for FLASH_SR register *******************/
jhon309 0:c52df770855b 2778 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
jhon309 0:c52df770855b 2779 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
jhon309 0:c52df770855b 2780 #define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
jhon309 0:c52df770855b 2781 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
jhon309 0:c52df770855b 2782 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
jhon309 0:c52df770855b 2783
jhon309 0:c52df770855b 2784 /******************* Bit definition for FLASH_CR register *******************/
jhon309 0:c52df770855b 2785 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
jhon309 0:c52df770855b 2786 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
jhon309 0:c52df770855b 2787 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
jhon309 0:c52df770855b 2788 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
jhon309 0:c52df770855b 2789 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
jhon309 0:c52df770855b 2790 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
jhon309 0:c52df770855b 2791 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
jhon309 0:c52df770855b 2792 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
jhon309 0:c52df770855b 2793 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
jhon309 0:c52df770855b 2794 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
jhon309 0:c52df770855b 2795 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
jhon309 0:c52df770855b 2796
jhon309 0:c52df770855b 2797 /******************* Bit definition for FLASH_AR register *******************/
jhon309 0:c52df770855b 2798 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
jhon309 0:c52df770855b 2799
jhon309 0:c52df770855b 2800 /****************** Bit definition for FLASH_OBR register *******************/
jhon309 0:c52df770855b 2801 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
jhon309 0:c52df770855b 2802 #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
jhon309 0:c52df770855b 2803 #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
jhon309 0:c52df770855b 2804
jhon309 0:c52df770855b 2805 #define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
jhon309 0:c52df770855b 2806 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
jhon309 0:c52df770855b 2807 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
jhon309 0:c52df770855b 2808 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
jhon309 0:c52df770855b 2809 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
jhon309 0:c52df770855b 2810 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
jhon309 0:c52df770855b 2811
jhon309 0:c52df770855b 2812 /* Old BOOT1 bit definition, maintained for legacy purpose */
jhon309 0:c52df770855b 2813 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
jhon309 0:c52df770855b 2814
jhon309 0:c52df770855b 2815 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
jhon309 0:c52df770855b 2816 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
jhon309 0:c52df770855b 2817
jhon309 0:c52df770855b 2818 /****************** Bit definition for FLASH_WRPR register ******************/
jhon309 0:c52df770855b 2819 #define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */
jhon309 0:c52df770855b 2820
jhon309 0:c52df770855b 2821 /*----------------------------------------------------------------------------*/
jhon309 0:c52df770855b 2822
jhon309 0:c52df770855b 2823 /****************** Bit definition for OB_RDP register **********************/
jhon309 0:c52df770855b 2824 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
jhon309 0:c52df770855b 2825 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
jhon309 0:c52df770855b 2826
jhon309 0:c52df770855b 2827 /****************** Bit definition for OB_USER register *********************/
jhon309 0:c52df770855b 2828 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
jhon309 0:c52df770855b 2829 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
jhon309 0:c52df770855b 2830
jhon309 0:c52df770855b 2831 /****************** Bit definition for OB_WRP0 register *********************/
jhon309 0:c52df770855b 2832 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
jhon309 0:c52df770855b 2833 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
jhon309 0:c52df770855b 2834
jhon309 0:c52df770855b 2835 /****************** Bit definition for OB_WRP1 register *********************/
jhon309 0:c52df770855b 2836 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
jhon309 0:c52df770855b 2837 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
jhon309 0:c52df770855b 2838
jhon309 0:c52df770855b 2839 /****************** Bit definition for OB_WRP2 register *********************/
jhon309 0:c52df770855b 2840 #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
jhon309 0:c52df770855b 2841 #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
jhon309 0:c52df770855b 2842
jhon309 0:c52df770855b 2843 /****************** Bit definition for OB_WRP3 register *********************/
jhon309 0:c52df770855b 2844 #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
jhon309 0:c52df770855b 2845 #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
jhon309 0:c52df770855b 2846
jhon309 0:c52df770855b 2847 /******************************************************************************/
jhon309 0:c52df770855b 2848 /* */
jhon309 0:c52df770855b 2849 /* General Purpose IOs (GPIO) */
jhon309 0:c52df770855b 2850 /* */
jhon309 0:c52df770855b 2851 /******************************************************************************/
jhon309 0:c52df770855b 2852 /******************* Bit definition for GPIO_MODER register *****************/
jhon309 0:c52df770855b 2853 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
jhon309 0:c52df770855b 2854 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
jhon309 0:c52df770855b 2855 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
jhon309 0:c52df770855b 2856 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
jhon309 0:c52df770855b 2857 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
jhon309 0:c52df770855b 2858 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
jhon309 0:c52df770855b 2859 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
jhon309 0:c52df770855b 2860 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
jhon309 0:c52df770855b 2861 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
jhon309 0:c52df770855b 2862 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
jhon309 0:c52df770855b 2863 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
jhon309 0:c52df770855b 2864 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
jhon309 0:c52df770855b 2865 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
jhon309 0:c52df770855b 2866 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
jhon309 0:c52df770855b 2867 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
jhon309 0:c52df770855b 2868 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
jhon309 0:c52df770855b 2869 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
jhon309 0:c52df770855b 2870 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
jhon309 0:c52df770855b 2871 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
jhon309 0:c52df770855b 2872 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
jhon309 0:c52df770855b 2873 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
jhon309 0:c52df770855b 2874 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
jhon309 0:c52df770855b 2875 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
jhon309 0:c52df770855b 2876 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
jhon309 0:c52df770855b 2877 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
jhon309 0:c52df770855b 2878 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
jhon309 0:c52df770855b 2879 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
jhon309 0:c52df770855b 2880 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
jhon309 0:c52df770855b 2881 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
jhon309 0:c52df770855b 2882 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
jhon309 0:c52df770855b 2883 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
jhon309 0:c52df770855b 2884 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
jhon309 0:c52df770855b 2885 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
jhon309 0:c52df770855b 2886 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
jhon309 0:c52df770855b 2887 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
jhon309 0:c52df770855b 2888 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
jhon309 0:c52df770855b 2889 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
jhon309 0:c52df770855b 2890 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
jhon309 0:c52df770855b 2891 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
jhon309 0:c52df770855b 2892 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
jhon309 0:c52df770855b 2893 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
jhon309 0:c52df770855b 2894 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
jhon309 0:c52df770855b 2895 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
jhon309 0:c52df770855b 2896 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
jhon309 0:c52df770855b 2897 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
jhon309 0:c52df770855b 2898 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
jhon309 0:c52df770855b 2899 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
jhon309 0:c52df770855b 2900 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
jhon309 0:c52df770855b 2901
jhon309 0:c52df770855b 2902 /****************** Bit definition for GPIO_OTYPER register *****************/
jhon309 0:c52df770855b 2903 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
jhon309 0:c52df770855b 2904 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
jhon309 0:c52df770855b 2905 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
jhon309 0:c52df770855b 2906 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
jhon309 0:c52df770855b 2907 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
jhon309 0:c52df770855b 2908 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
jhon309 0:c52df770855b 2909 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
jhon309 0:c52df770855b 2910 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
jhon309 0:c52df770855b 2911 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
jhon309 0:c52df770855b 2912 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
jhon309 0:c52df770855b 2913 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
jhon309 0:c52df770855b 2914 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
jhon309 0:c52df770855b 2915 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
jhon309 0:c52df770855b 2916 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
jhon309 0:c52df770855b 2917 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
jhon309 0:c52df770855b 2918 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
jhon309 0:c52df770855b 2919
jhon309 0:c52df770855b 2920 /**************** Bit definition for GPIO_OSPEEDR register ******************/
jhon309 0:c52df770855b 2921 #define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
jhon309 0:c52df770855b 2922 #define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
jhon309 0:c52df770855b 2923 #define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
jhon309 0:c52df770855b 2924 #define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
jhon309 0:c52df770855b 2925 #define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
jhon309 0:c52df770855b 2926 #define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
jhon309 0:c52df770855b 2927 #define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
jhon309 0:c52df770855b 2928 #define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
jhon309 0:c52df770855b 2929 #define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
jhon309 0:c52df770855b 2930 #define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
jhon309 0:c52df770855b 2931 #define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
jhon309 0:c52df770855b 2932 #define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
jhon309 0:c52df770855b 2933 #define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
jhon309 0:c52df770855b 2934 #define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
jhon309 0:c52df770855b 2935 #define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
jhon309 0:c52df770855b 2936 #define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
jhon309 0:c52df770855b 2937 #define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
jhon309 0:c52df770855b 2938 #define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
jhon309 0:c52df770855b 2939 #define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
jhon309 0:c52df770855b 2940 #define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
jhon309 0:c52df770855b 2941 #define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
jhon309 0:c52df770855b 2942 #define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
jhon309 0:c52df770855b 2943 #define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
jhon309 0:c52df770855b 2944 #define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
jhon309 0:c52df770855b 2945 #define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
jhon309 0:c52df770855b 2946 #define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
jhon309 0:c52df770855b 2947 #define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
jhon309 0:c52df770855b 2948 #define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
jhon309 0:c52df770855b 2949 #define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
jhon309 0:c52df770855b 2950 #define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
jhon309 0:c52df770855b 2951 #define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
jhon309 0:c52df770855b 2952 #define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
jhon309 0:c52df770855b 2953 #define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
jhon309 0:c52df770855b 2954 #define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
jhon309 0:c52df770855b 2955 #define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
jhon309 0:c52df770855b 2956 #define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
jhon309 0:c52df770855b 2957 #define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
jhon309 0:c52df770855b 2958 #define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
jhon309 0:c52df770855b 2959 #define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
jhon309 0:c52df770855b 2960 #define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
jhon309 0:c52df770855b 2961 #define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
jhon309 0:c52df770855b 2962 #define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
jhon309 0:c52df770855b 2963 #define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
jhon309 0:c52df770855b 2964 #define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
jhon309 0:c52df770855b 2965 #define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
jhon309 0:c52df770855b 2966 #define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
jhon309 0:c52df770855b 2967 #define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
jhon309 0:c52df770855b 2968 #define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
jhon309 0:c52df770855b 2969
jhon309 0:c52df770855b 2970 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
jhon309 0:c52df770855b 2971 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
jhon309 0:c52df770855b 2972 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
jhon309 0:c52df770855b 2973 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
jhon309 0:c52df770855b 2974 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
jhon309 0:c52df770855b 2975 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
jhon309 0:c52df770855b 2976 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
jhon309 0:c52df770855b 2977 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
jhon309 0:c52df770855b 2978 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
jhon309 0:c52df770855b 2979 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
jhon309 0:c52df770855b 2980 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
jhon309 0:c52df770855b 2981 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
jhon309 0:c52df770855b 2982 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
jhon309 0:c52df770855b 2983 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
jhon309 0:c52df770855b 2984 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
jhon309 0:c52df770855b 2985 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
jhon309 0:c52df770855b 2986 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
jhon309 0:c52df770855b 2987 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
jhon309 0:c52df770855b 2988 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
jhon309 0:c52df770855b 2989 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
jhon309 0:c52df770855b 2990 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
jhon309 0:c52df770855b 2991 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
jhon309 0:c52df770855b 2992 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
jhon309 0:c52df770855b 2993 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
jhon309 0:c52df770855b 2994 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
jhon309 0:c52df770855b 2995 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
jhon309 0:c52df770855b 2996 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
jhon309 0:c52df770855b 2997 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
jhon309 0:c52df770855b 2998 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
jhon309 0:c52df770855b 2999 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
jhon309 0:c52df770855b 3000 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
jhon309 0:c52df770855b 3001 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
jhon309 0:c52df770855b 3002 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
jhon309 0:c52df770855b 3003 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
jhon309 0:c52df770855b 3004 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
jhon309 0:c52df770855b 3005 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
jhon309 0:c52df770855b 3006 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
jhon309 0:c52df770855b 3007 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
jhon309 0:c52df770855b 3008 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
jhon309 0:c52df770855b 3009 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
jhon309 0:c52df770855b 3010 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
jhon309 0:c52df770855b 3011 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
jhon309 0:c52df770855b 3012 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
jhon309 0:c52df770855b 3013 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
jhon309 0:c52df770855b 3014 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
jhon309 0:c52df770855b 3015 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
jhon309 0:c52df770855b 3016 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
jhon309 0:c52df770855b 3017 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
jhon309 0:c52df770855b 3018 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
jhon309 0:c52df770855b 3019
jhon309 0:c52df770855b 3020 /******************* Bit definition for GPIO_PUPDR register ******************/
jhon309 0:c52df770855b 3021 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
jhon309 0:c52df770855b 3022 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
jhon309 0:c52df770855b 3023 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
jhon309 0:c52df770855b 3024 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
jhon309 0:c52df770855b 3025 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
jhon309 0:c52df770855b 3026 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
jhon309 0:c52df770855b 3027 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
jhon309 0:c52df770855b 3028 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
jhon309 0:c52df770855b 3029 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
jhon309 0:c52df770855b 3030 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
jhon309 0:c52df770855b 3031 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
jhon309 0:c52df770855b 3032 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
jhon309 0:c52df770855b 3033 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
jhon309 0:c52df770855b 3034 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
jhon309 0:c52df770855b 3035 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
jhon309 0:c52df770855b 3036 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
jhon309 0:c52df770855b 3037 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
jhon309 0:c52df770855b 3038 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
jhon309 0:c52df770855b 3039 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
jhon309 0:c52df770855b 3040 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
jhon309 0:c52df770855b 3041 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
jhon309 0:c52df770855b 3042 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
jhon309 0:c52df770855b 3043 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
jhon309 0:c52df770855b 3044 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
jhon309 0:c52df770855b 3045 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
jhon309 0:c52df770855b 3046 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
jhon309 0:c52df770855b 3047 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
jhon309 0:c52df770855b 3048 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
jhon309 0:c52df770855b 3049 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
jhon309 0:c52df770855b 3050 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
jhon309 0:c52df770855b 3051 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
jhon309 0:c52df770855b 3052 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
jhon309 0:c52df770855b 3053 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
jhon309 0:c52df770855b 3054 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
jhon309 0:c52df770855b 3055 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
jhon309 0:c52df770855b 3056 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
jhon309 0:c52df770855b 3057 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
jhon309 0:c52df770855b 3058 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
jhon309 0:c52df770855b 3059 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
jhon309 0:c52df770855b 3060 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
jhon309 0:c52df770855b 3061 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
jhon309 0:c52df770855b 3062 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
jhon309 0:c52df770855b 3063 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
jhon309 0:c52df770855b 3064 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
jhon309 0:c52df770855b 3065 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
jhon309 0:c52df770855b 3066 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
jhon309 0:c52df770855b 3067 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
jhon309 0:c52df770855b 3068 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
jhon309 0:c52df770855b 3069
jhon309 0:c52df770855b 3070 /******************* Bit definition for GPIO_IDR register *******************/
jhon309 0:c52df770855b 3071 #define GPIO_IDR_0 ((uint32_t)0x00000001)
jhon309 0:c52df770855b 3072 #define GPIO_IDR_1 ((uint32_t)0x00000002)
jhon309 0:c52df770855b 3073 #define GPIO_IDR_2 ((uint32_t)0x00000004)
jhon309 0:c52df770855b 3074 #define GPIO_IDR_3 ((uint32_t)0x00000008)
jhon309 0:c52df770855b 3075 #define GPIO_IDR_4 ((uint32_t)0x00000010)
jhon309 0:c52df770855b 3076 #define GPIO_IDR_5 ((uint32_t)0x00000020)
jhon309 0:c52df770855b 3077 #define GPIO_IDR_6 ((uint32_t)0x00000040)
jhon309 0:c52df770855b 3078 #define GPIO_IDR_7 ((uint32_t)0x00000080)
jhon309 0:c52df770855b 3079 #define GPIO_IDR_8 ((uint32_t)0x00000100)
jhon309 0:c52df770855b 3080 #define GPIO_IDR_9 ((uint32_t)0x00000200)
jhon309 0:c52df770855b 3081 #define GPIO_IDR_10 ((uint32_t)0x00000400)
jhon309 0:c52df770855b 3082 #define GPIO_IDR_11 ((uint32_t)0x00000800)
jhon309 0:c52df770855b 3083 #define GPIO_IDR_12 ((uint32_t)0x00001000)
jhon309 0:c52df770855b 3084 #define GPIO_IDR_13 ((uint32_t)0x00002000)
jhon309 0:c52df770855b 3085 #define GPIO_IDR_14 ((uint32_t)0x00004000)
jhon309 0:c52df770855b 3086 #define GPIO_IDR_15 ((uint32_t)0x00008000)
jhon309 0:c52df770855b 3087
jhon309 0:c52df770855b 3088 /****************** Bit definition for GPIO_ODR register ********************/
jhon309 0:c52df770855b 3089 #define GPIO_ODR_0 ((uint32_t)0x00000001)
jhon309 0:c52df770855b 3090 #define GPIO_ODR_1 ((uint32_t)0x00000002)
jhon309 0:c52df770855b 3091 #define GPIO_ODR_2 ((uint32_t)0x00000004)
jhon309 0:c52df770855b 3092 #define GPIO_ODR_3 ((uint32_t)0x00000008)
jhon309 0:c52df770855b 3093 #define GPIO_ODR_4 ((uint32_t)0x00000010)
jhon309 0:c52df770855b 3094 #define GPIO_ODR_5 ((uint32_t)0x00000020)
jhon309 0:c52df770855b 3095 #define GPIO_ODR_6 ((uint32_t)0x00000040)
jhon309 0:c52df770855b 3096 #define GPIO_ODR_7 ((uint32_t)0x00000080)
jhon309 0:c52df770855b 3097 #define GPIO_ODR_8 ((uint32_t)0x00000100)
jhon309 0:c52df770855b 3098 #define GPIO_ODR_9 ((uint32_t)0x00000200)
jhon309 0:c52df770855b 3099 #define GPIO_ODR_10 ((uint32_t)0x00000400)
jhon309 0:c52df770855b 3100 #define GPIO_ODR_11 ((uint32_t)0x00000800)
jhon309 0:c52df770855b 3101 #define GPIO_ODR_12 ((uint32_t)0x00001000)
jhon309 0:c52df770855b 3102 #define GPIO_ODR_13 ((uint32_t)0x00002000)
jhon309 0:c52df770855b 3103 #define GPIO_ODR_14 ((uint32_t)0x00004000)
jhon309 0:c52df770855b 3104 #define GPIO_ODR_15 ((uint32_t)0x00008000)
jhon309 0:c52df770855b 3105
jhon309 0:c52df770855b 3106 /****************** Bit definition for GPIO_BSRR register ********************/
jhon309 0:c52df770855b 3107 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
jhon309 0:c52df770855b 3108 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
jhon309 0:c52df770855b 3109 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
jhon309 0:c52df770855b 3110 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
jhon309 0:c52df770855b 3111 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
jhon309 0:c52df770855b 3112 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
jhon309 0:c52df770855b 3113 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
jhon309 0:c52df770855b 3114 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
jhon309 0:c52df770855b 3115 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
jhon309 0:c52df770855b 3116 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
jhon309 0:c52df770855b 3117 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
jhon309 0:c52df770855b 3118 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
jhon309 0:c52df770855b 3119 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
jhon309 0:c52df770855b 3120 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
jhon309 0:c52df770855b 3121 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
jhon309 0:c52df770855b 3122 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
jhon309 0:c52df770855b 3123 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
jhon309 0:c52df770855b 3124 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
jhon309 0:c52df770855b 3125 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
jhon309 0:c52df770855b 3126 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
jhon309 0:c52df770855b 3127 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
jhon309 0:c52df770855b 3128 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
jhon309 0:c52df770855b 3129 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
jhon309 0:c52df770855b 3130 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
jhon309 0:c52df770855b 3131 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
jhon309 0:c52df770855b 3132 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
jhon309 0:c52df770855b 3133 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
jhon309 0:c52df770855b 3134 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
jhon309 0:c52df770855b 3135 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
jhon309 0:c52df770855b 3136 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
jhon309 0:c52df770855b 3137 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
jhon309 0:c52df770855b 3138 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
jhon309 0:c52df770855b 3139
jhon309 0:c52df770855b 3140 /****************** Bit definition for GPIO_LCKR register ********************/
jhon309 0:c52df770855b 3141 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
jhon309 0:c52df770855b 3142 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
jhon309 0:c52df770855b 3143 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
jhon309 0:c52df770855b 3144 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
jhon309 0:c52df770855b 3145 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
jhon309 0:c52df770855b 3146 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
jhon309 0:c52df770855b 3147 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
jhon309 0:c52df770855b 3148 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
jhon309 0:c52df770855b 3149 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
jhon309 0:c52df770855b 3150 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
jhon309 0:c52df770855b 3151 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
jhon309 0:c52df770855b 3152 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
jhon309 0:c52df770855b 3153 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
jhon309 0:c52df770855b 3154 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
jhon309 0:c52df770855b 3155 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
jhon309 0:c52df770855b 3156 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
jhon309 0:c52df770855b 3157 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
jhon309 0:c52df770855b 3158
jhon309 0:c52df770855b 3159 /****************** Bit definition for GPIO_AFRL register ********************/
jhon309 0:c52df770855b 3160 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
jhon309 0:c52df770855b 3161 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
jhon309 0:c52df770855b 3162 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
jhon309 0:c52df770855b 3163 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
jhon309 0:c52df770855b 3164 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
jhon309 0:c52df770855b 3165 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
jhon309 0:c52df770855b 3166 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
jhon309 0:c52df770855b 3167 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
jhon309 0:c52df770855b 3168
jhon309 0:c52df770855b 3169 /****************** Bit definition for GPIO_AFRH register ********************/
jhon309 0:c52df770855b 3170 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
jhon309 0:c52df770855b 3171 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
jhon309 0:c52df770855b 3172 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
jhon309 0:c52df770855b 3173 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
jhon309 0:c52df770855b 3174 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
jhon309 0:c52df770855b 3175 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
jhon309 0:c52df770855b 3176 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
jhon309 0:c52df770855b 3177 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
jhon309 0:c52df770855b 3178
jhon309 0:c52df770855b 3179 /****************** Bit definition for GPIO_BRR register *********************/
jhon309 0:c52df770855b 3180 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
jhon309 0:c52df770855b 3181 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
jhon309 0:c52df770855b 3182 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
jhon309 0:c52df770855b 3183 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
jhon309 0:c52df770855b 3184 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
jhon309 0:c52df770855b 3185 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
jhon309 0:c52df770855b 3186 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
jhon309 0:c52df770855b 3187 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
jhon309 0:c52df770855b 3188 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
jhon309 0:c52df770855b 3189 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
jhon309 0:c52df770855b 3190 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
jhon309 0:c52df770855b 3191 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
jhon309 0:c52df770855b 3192 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
jhon309 0:c52df770855b 3193 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
jhon309 0:c52df770855b 3194 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
jhon309 0:c52df770855b 3195 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
jhon309 0:c52df770855b 3196
jhon309 0:c52df770855b 3197 /******************************************************************************/
jhon309 0:c52df770855b 3198 /* */
jhon309 0:c52df770855b 3199 /* Inter-integrated Circuit Interface (I2C) */
jhon309 0:c52df770855b 3200 /* */
jhon309 0:c52df770855b 3201 /******************************************************************************/
jhon309 0:c52df770855b 3202
jhon309 0:c52df770855b 3203 /******************* Bit definition for I2C_CR1 register *******************/
jhon309 0:c52df770855b 3204 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
jhon309 0:c52df770855b 3205 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
jhon309 0:c52df770855b 3206 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
jhon309 0:c52df770855b 3207 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
jhon309 0:c52df770855b 3208 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
jhon309 0:c52df770855b 3209 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
jhon309 0:c52df770855b 3210 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
jhon309 0:c52df770855b 3211 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
jhon309 0:c52df770855b 3212 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
jhon309 0:c52df770855b 3213 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
jhon309 0:c52df770855b 3214 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
jhon309 0:c52df770855b 3215 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
jhon309 0:c52df770855b 3216 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
jhon309 0:c52df770855b 3217 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
jhon309 0:c52df770855b 3218 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
jhon309 0:c52df770855b 3219 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
jhon309 0:c52df770855b 3220 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
jhon309 0:c52df770855b 3221 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
jhon309 0:c52df770855b 3222 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
jhon309 0:c52df770855b 3223 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
jhon309 0:c52df770855b 3224 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
jhon309 0:c52df770855b 3225
jhon309 0:c52df770855b 3226 /****************** Bit definition for I2C_CR2 register ********************/
jhon309 0:c52df770855b 3227 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
jhon309 0:c52df770855b 3228 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
jhon309 0:c52df770855b 3229 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
jhon309 0:c52df770855b 3230 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
jhon309 0:c52df770855b 3231 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
jhon309 0:c52df770855b 3232 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
jhon309 0:c52df770855b 3233 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
jhon309 0:c52df770855b 3234 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
jhon309 0:c52df770855b 3235 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
jhon309 0:c52df770855b 3236 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
jhon309 0:c52df770855b 3237 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
jhon309 0:c52df770855b 3238
jhon309 0:c52df770855b 3239 /******************* Bit definition for I2C_OAR1 register ******************/
jhon309 0:c52df770855b 3240 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
jhon309 0:c52df770855b 3241 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
jhon309 0:c52df770855b 3242 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
jhon309 0:c52df770855b 3243
jhon309 0:c52df770855b 3244 /******************* Bit definition for I2C_OAR2 register ******************/
jhon309 0:c52df770855b 3245 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
jhon309 0:c52df770855b 3246 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
jhon309 0:c52df770855b 3247 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
jhon309 0:c52df770855b 3248
jhon309 0:c52df770855b 3249 /******************* Bit definition for I2C_TIMINGR register ****************/
jhon309 0:c52df770855b 3250 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
jhon309 0:c52df770855b 3251 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
jhon309 0:c52df770855b 3252 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
jhon309 0:c52df770855b 3253 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
jhon309 0:c52df770855b 3254 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
jhon309 0:c52df770855b 3255
jhon309 0:c52df770855b 3256 /******************* Bit definition for I2C_TIMEOUTR register ****************/
jhon309 0:c52df770855b 3257 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
jhon309 0:c52df770855b 3258 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
jhon309 0:c52df770855b 3259 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
jhon309 0:c52df770855b 3260 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
jhon309 0:c52df770855b 3261 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
jhon309 0:c52df770855b 3262
jhon309 0:c52df770855b 3263 /****************** Bit definition for I2C_ISR register ********************/
jhon309 0:c52df770855b 3264 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
jhon309 0:c52df770855b 3265 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
jhon309 0:c52df770855b 3266 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
jhon309 0:c52df770855b 3267 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
jhon309 0:c52df770855b 3268 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
jhon309 0:c52df770855b 3269 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
jhon309 0:c52df770855b 3270 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
jhon309 0:c52df770855b 3271 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
jhon309 0:c52df770855b 3272 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
jhon309 0:c52df770855b 3273 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
jhon309 0:c52df770855b 3274 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
jhon309 0:c52df770855b 3275 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
jhon309 0:c52df770855b 3276 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
jhon309 0:c52df770855b 3277 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
jhon309 0:c52df770855b 3278 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
jhon309 0:c52df770855b 3279 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
jhon309 0:c52df770855b 3280 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
jhon309 0:c52df770855b 3281
jhon309 0:c52df770855b 3282 /****************** Bit definition for I2C_ICR register ********************/
jhon309 0:c52df770855b 3283 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
jhon309 0:c52df770855b 3284 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
jhon309 0:c52df770855b 3285 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
jhon309 0:c52df770855b 3286 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
jhon309 0:c52df770855b 3287 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
jhon309 0:c52df770855b 3288 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
jhon309 0:c52df770855b 3289 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
jhon309 0:c52df770855b 3290 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
jhon309 0:c52df770855b 3291 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
jhon309 0:c52df770855b 3292
jhon309 0:c52df770855b 3293 /****************** Bit definition for I2C_PECR register *******************/
jhon309 0:c52df770855b 3294 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
jhon309 0:c52df770855b 3295
jhon309 0:c52df770855b 3296 /****************** Bit definition for I2C_RXDR register *********************/
jhon309 0:c52df770855b 3297 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
jhon309 0:c52df770855b 3298
jhon309 0:c52df770855b 3299 /****************** Bit definition for I2C_TXDR register *******************/
jhon309 0:c52df770855b 3300 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
jhon309 0:c52df770855b 3301
jhon309 0:c52df770855b 3302 /*****************************************************************************/
jhon309 0:c52df770855b 3303 /* */
jhon309 0:c52df770855b 3304 /* Independent WATCHDOG (IWDG) */
jhon309 0:c52df770855b 3305 /* */
jhon309 0:c52df770855b 3306 /*****************************************************************************/
jhon309 0:c52df770855b 3307 /******************* Bit definition for IWDG_KR register *******************/
jhon309 0:c52df770855b 3308 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */
jhon309 0:c52df770855b 3309
jhon309 0:c52df770855b 3310 /******************* Bit definition for IWDG_PR register *******************/
jhon309 0:c52df770855b 3311 #define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */
jhon309 0:c52df770855b 3312 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */
jhon309 0:c52df770855b 3313 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */
jhon309 0:c52df770855b 3314 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */
jhon309 0:c52df770855b 3315
jhon309 0:c52df770855b 3316 /******************* Bit definition for IWDG_RLR register ******************/
jhon309 0:c52df770855b 3317 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */
jhon309 0:c52df770855b 3318
jhon309 0:c52df770855b 3319 /******************* Bit definition for IWDG_SR register *******************/
jhon309 0:c52df770855b 3320 #define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
jhon309 0:c52df770855b 3321 #define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
jhon309 0:c52df770855b 3322 #define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
jhon309 0:c52df770855b 3323
jhon309 0:c52df770855b 3324 /******************* Bit definition for IWDG_KR register *******************/
jhon309 0:c52df770855b 3325 #define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
jhon309 0:c52df770855b 3326
jhon309 0:c52df770855b 3327 /*****************************************************************************/
jhon309 0:c52df770855b 3328 /* */
jhon309 0:c52df770855b 3329 /* Power Control (PWR) */
jhon309 0:c52df770855b 3330 /* */
jhon309 0:c52df770855b 3331 /*****************************************************************************/
jhon309 0:c52df770855b 3332
jhon309 0:c52df770855b 3333 /******************** Bit definition for PWR_CR register *******************/
jhon309 0:c52df770855b 3334 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
jhon309 0:c52df770855b 3335 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
jhon309 0:c52df770855b 3336 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
jhon309 0:c52df770855b 3337 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
jhon309 0:c52df770855b 3338 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
jhon309 0:c52df770855b 3339
jhon309 0:c52df770855b 3340 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
jhon309 0:c52df770855b 3341 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
jhon309 0:c52df770855b 3342 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
jhon309 0:c52df770855b 3343 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
jhon309 0:c52df770855b 3344
jhon309 0:c52df770855b 3345 /*!< PVD level configuration */
jhon309 0:c52df770855b 3346 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
jhon309 0:c52df770855b 3347 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
jhon309 0:c52df770855b 3348 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
jhon309 0:c52df770855b 3349 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
jhon309 0:c52df770855b 3350 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
jhon309 0:c52df770855b 3351 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
jhon309 0:c52df770855b 3352 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
jhon309 0:c52df770855b 3353 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
jhon309 0:c52df770855b 3354
jhon309 0:c52df770855b 3355 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
jhon309 0:c52df770855b 3356
jhon309 0:c52df770855b 3357 /******************* Bit definition for PWR_CSR register *******************/
jhon309 0:c52df770855b 3358 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
jhon309 0:c52df770855b 3359 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
jhon309 0:c52df770855b 3360 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
jhon309 0:c52df770855b 3361 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
jhon309 0:c52df770855b 3362
jhon309 0:c52df770855b 3363 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
jhon309 0:c52df770855b 3364 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
jhon309 0:c52df770855b 3365 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
jhon309 0:c52df770855b 3366 #define PWR_CSR_EWUP4 ((uint32_t)0x00000800) /*!< Enable WKUP pin 4 */
jhon309 0:c52df770855b 3367 #define PWR_CSR_EWUP5 ((uint32_t)0x00001000) /*!< Enable WKUP pin 5 */
jhon309 0:c52df770855b 3368 #define PWR_CSR_EWUP6 ((uint32_t)0x00002000) /*!< Enable WKUP pin 6 */
jhon309 0:c52df770855b 3369 #define PWR_CSR_EWUP7 ((uint32_t)0x00004000) /*!< Enable WKUP pin 7 */
jhon309 0:c52df770855b 3370 #define PWR_CSR_EWUP8 ((uint32_t)0x00008000) /*!< Enable WKUP pin 8 */
jhon309 0:c52df770855b 3371
jhon309 0:c52df770855b 3372 /*****************************************************************************/
jhon309 0:c52df770855b 3373 /* */
jhon309 0:c52df770855b 3374 /* Reset and Clock Control */
jhon309 0:c52df770855b 3375 /* */
jhon309 0:c52df770855b 3376 /*****************************************************************************/
jhon309 0:c52df770855b 3377
jhon309 0:c52df770855b 3378 /******************** Bit definition for RCC_CR register *******************/
jhon309 0:c52df770855b 3379 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
jhon309 0:c52df770855b 3380 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
jhon309 0:c52df770855b 3381
jhon309 0:c52df770855b 3382 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
jhon309 0:c52df770855b 3383 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
jhon309 0:c52df770855b 3384 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
jhon309 0:c52df770855b 3385 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
jhon309 0:c52df770855b 3386 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
jhon309 0:c52df770855b 3387 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
jhon309 0:c52df770855b 3388
jhon309 0:c52df770855b 3389 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
jhon309 0:c52df770855b 3390 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
jhon309 0:c52df770855b 3391 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
jhon309 0:c52df770855b 3392 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
jhon309 0:c52df770855b 3393 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
jhon309 0:c52df770855b 3394 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
jhon309 0:c52df770855b 3395 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
jhon309 0:c52df770855b 3396 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
jhon309 0:c52df770855b 3397 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
jhon309 0:c52df770855b 3398
jhon309 0:c52df770855b 3399 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
jhon309 0:c52df770855b 3400 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
jhon309 0:c52df770855b 3401 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
jhon309 0:c52df770855b 3402 #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
jhon309 0:c52df770855b 3403 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
jhon309 0:c52df770855b 3404 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
jhon309 0:c52df770855b 3405
jhon309 0:c52df770855b 3406 /******************** Bit definition for RCC_CFGR register *****************/
jhon309 0:c52df770855b 3407 /*!< SW configuration */
jhon309 0:c52df770855b 3408 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
jhon309 0:c52df770855b 3409 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
jhon309 0:c52df770855b 3410 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
jhon309 0:c52df770855b 3411
jhon309 0:c52df770855b 3412 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
jhon309 0:c52df770855b 3413 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
jhon309 0:c52df770855b 3414 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
jhon309 0:c52df770855b 3415 #define RCC_CFGR_SW_HSI48 ((uint32_t)0x00000003) /*!< HSI48 selected as system clock */
jhon309 0:c52df770855b 3416
jhon309 0:c52df770855b 3417 /*!< SWS configuration */
jhon309 0:c52df770855b 3418 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
jhon309 0:c52df770855b 3419 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
jhon309 0:c52df770855b 3420 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
jhon309 0:c52df770855b 3421
jhon309 0:c52df770855b 3422 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
jhon309 0:c52df770855b 3423 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
jhon309 0:c52df770855b 3424 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
jhon309 0:c52df770855b 3425 #define RCC_CFGR_SWS_HSI48 ((uint32_t)0x0000000C) /*!< HSI48 oscillator used as system clock */
jhon309 0:c52df770855b 3426
jhon309 0:c52df770855b 3427 /*!< HPRE configuration */
jhon309 0:c52df770855b 3428 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
jhon309 0:c52df770855b 3429 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
jhon309 0:c52df770855b 3430 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
jhon309 0:c52df770855b 3431 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
jhon309 0:c52df770855b 3432 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
jhon309 0:c52df770855b 3433
jhon309 0:c52df770855b 3434 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
jhon309 0:c52df770855b 3435 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
jhon309 0:c52df770855b 3436 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
jhon309 0:c52df770855b 3437 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
jhon309 0:c52df770855b 3438 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
jhon309 0:c52df770855b 3439 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
jhon309 0:c52df770855b 3440 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
jhon309 0:c52df770855b 3441 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
jhon309 0:c52df770855b 3442 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
jhon309 0:c52df770855b 3443
jhon309 0:c52df770855b 3444 /*!< PPRE configuration */
jhon309 0:c52df770855b 3445 #define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
jhon309 0:c52df770855b 3446 #define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
jhon309 0:c52df770855b 3447 #define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
jhon309 0:c52df770855b 3448 #define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
jhon309 0:c52df770855b 3449
jhon309 0:c52df770855b 3450 #define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
jhon309 0:c52df770855b 3451 #define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
jhon309 0:c52df770855b 3452 #define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
jhon309 0:c52df770855b 3453 #define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
jhon309 0:c52df770855b 3454 #define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
jhon309 0:c52df770855b 3455
jhon309 0:c52df770855b 3456 /*!< ADCPPRE configuration */
jhon309 0:c52df770855b 3457 #define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADCPRE bit (ADC prescaler) */
jhon309 0:c52df770855b 3458
jhon309 0:c52df770855b 3459 #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK divided by 2 */
jhon309 0:c52df770855b 3460 #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK divided by 4 */
jhon309 0:c52df770855b 3461
jhon309 0:c52df770855b 3462 #define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
jhon309 0:c52df770855b 3463 #define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
jhon309 0:c52df770855b 3464 #define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI/PREDIV clock selected as PLL entry clock source */
jhon309 0:c52df770855b 3465 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
jhon309 0:c52df770855b 3466 #define RCC_CFGR_PLLSRC_HSI48_PREDIV ((uint32_t)0x00018000) /*!< HSI48/PREDIV clock selected as PLL entry clock source */
jhon309 0:c52df770855b 3467
jhon309 0:c52df770855b 3468 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
jhon309 0:c52df770855b 3469 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
jhon309 0:c52df770855b 3470 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
jhon309 0:c52df770855b 3471
jhon309 0:c52df770855b 3472 /*!< PLLMUL configuration */
jhon309 0:c52df770855b 3473 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
jhon309 0:c52df770855b 3474 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
jhon309 0:c52df770855b 3475 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
jhon309 0:c52df770855b 3476 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
jhon309 0:c52df770855b 3477 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
jhon309 0:c52df770855b 3478
jhon309 0:c52df770855b 3479 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
jhon309 0:c52df770855b 3480 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
jhon309 0:c52df770855b 3481 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
jhon309 0:c52df770855b 3482 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
jhon309 0:c52df770855b 3483 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
jhon309 0:c52df770855b 3484 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
jhon309 0:c52df770855b 3485 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
jhon309 0:c52df770855b 3486 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
jhon309 0:c52df770855b 3487 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
jhon309 0:c52df770855b 3488 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
jhon309 0:c52df770855b 3489 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
jhon309 0:c52df770855b 3490 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
jhon309 0:c52df770855b 3491 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
jhon309 0:c52df770855b 3492 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
jhon309 0:c52df770855b 3493 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
jhon309 0:c52df770855b 3494
jhon309 0:c52df770855b 3495 /*!< USB configuration */
jhon309 0:c52df770855b 3496 #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
jhon309 0:c52df770855b 3497
jhon309 0:c52df770855b 3498 /*!< MCO configuration */
jhon309 0:c52df770855b 3499 #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
jhon309 0:c52df770855b 3500 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
jhon309 0:c52df770855b 3501 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
jhon309 0:c52df770855b 3502 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
jhon309 0:c52df770855b 3503 #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
jhon309 0:c52df770855b 3504
jhon309 0:c52df770855b 3505 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
jhon309 0:c52df770855b 3506 #define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
jhon309 0:c52df770855b 3507 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
jhon309 0:c52df770855b 3508 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
jhon309 0:c52df770855b 3509 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
jhon309 0:c52df770855b 3510 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
jhon309 0:c52df770855b 3511 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
jhon309 0:c52df770855b 3512 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
jhon309 0:c52df770855b 3513 #define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /*!< HSI48 clock selected as MCO source */
jhon309 0:c52df770855b 3514
jhon309 0:c52df770855b 3515 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCO prescaler */
jhon309 0:c52df770855b 3516 #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
jhon309 0:c52df770855b 3517 #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
jhon309 0:c52df770855b 3518 #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
jhon309 0:c52df770855b 3519 #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
jhon309 0:c52df770855b 3520 #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
jhon309 0:c52df770855b 3521 #define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
jhon309 0:c52df770855b 3522 #define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
jhon309 0:c52df770855b 3523 #define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
jhon309 0:c52df770855b 3524
jhon309 0:c52df770855b 3525 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
jhon309 0:c52df770855b 3526
jhon309 0:c52df770855b 3527 /*!<****************** Bit definition for RCC_CIR register *****************/
jhon309 0:c52df770855b 3528 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
jhon309 0:c52df770855b 3529 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
jhon309 0:c52df770855b 3530 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
jhon309 0:c52df770855b 3531 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
jhon309 0:c52df770855b 3532 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
jhon309 0:c52df770855b 3533 #define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
jhon309 0:c52df770855b 3534 #define RCC_CIR_HSI48RDYF ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt flag */
jhon309 0:c52df770855b 3535 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
jhon309 0:c52df770855b 3536 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
jhon309 0:c52df770855b 3537 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
jhon309 0:c52df770855b 3538 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
jhon309 0:c52df770855b 3539 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
jhon309 0:c52df770855b 3540 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
jhon309 0:c52df770855b 3541 #define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
jhon309 0:c52df770855b 3542 #define RCC_CIR_HSI48RDYIE ((uint32_t)0x00004000) /*!< HSI48 Ready Interrupt Enable */
jhon309 0:c52df770855b 3543 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
jhon309 0:c52df770855b 3544 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
jhon309 0:c52df770855b 3545 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
jhon309 0:c52df770855b 3546 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
jhon309 0:c52df770855b 3547 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
jhon309 0:c52df770855b 3548 #define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
jhon309 0:c52df770855b 3549 #define RCC_CIR_HSI48RDYC ((uint32_t)0x00400000) /*!< HSI48 Ready Interrupt Clear */
jhon309 0:c52df770855b 3550 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
jhon309 0:c52df770855b 3551
jhon309 0:c52df770855b 3552 /***************** Bit definition for RCC_APB2RSTR register ****************/
jhon309 0:c52df770855b 3553 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
jhon309 0:c52df770855b 3554 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
jhon309 0:c52df770855b 3555 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
jhon309 0:c52df770855b 3556 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
jhon309 0:c52df770855b 3557 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
jhon309 0:c52df770855b 3558 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 clock reset */
jhon309 0:c52df770855b 3559 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
jhon309 0:c52df770855b 3560 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
jhon309 0:c52df770855b 3561 #define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
jhon309 0:c52df770855b 3562
jhon309 0:c52df770855b 3563 /*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
jhon309 0:c52df770855b 3564 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
jhon309 0:c52df770855b 3565
jhon309 0:c52df770855b 3566 /***************** Bit definition for RCC_APB1RSTR register ****************/
jhon309 0:c52df770855b 3567 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
jhon309 0:c52df770855b 3568 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
jhon309 0:c52df770855b 3569 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
jhon309 0:c52df770855b 3570 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 clock reset */
jhon309 0:c52df770855b 3571 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
jhon309 0:c52df770855b 3572 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
jhon309 0:c52df770855b 3573 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
jhon309 0:c52df770855b 3574 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
jhon309 0:c52df770855b 3575 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 clock reset */
jhon309 0:c52df770855b 3576 #define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /*!< USART 4 clock reset */
jhon309 0:c52df770855b 3577 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
jhon309 0:c52df770855b 3578 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
jhon309 0:c52df770855b 3579 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB clock reset */
jhon309 0:c52df770855b 3580 #define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN clock reset */
jhon309 0:c52df770855b 3581 #define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /*!< CRS clock reset */
jhon309 0:c52df770855b 3582 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
jhon309 0:c52df770855b 3583 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
jhon309 0:c52df770855b 3584 #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC clock reset */
jhon309 0:c52df770855b 3585
jhon309 0:c52df770855b 3586 /****************** Bit definition for RCC_AHBENR register *****************/
jhon309 0:c52df770855b 3587 #define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
jhon309 0:c52df770855b 3588 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
jhon309 0:c52df770855b 3589 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
jhon309 0:c52df770855b 3590 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
jhon309 0:c52df770855b 3591 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
jhon309 0:c52df770855b 3592 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
jhon309 0:c52df770855b 3593 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
jhon309 0:c52df770855b 3594 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
jhon309 0:c52df770855b 3595 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
jhon309 0:c52df770855b 3596 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
jhon309 0:c52df770855b 3597 #define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS controller clock enable */
jhon309 0:c52df770855b 3598
jhon309 0:c52df770855b 3599 /* Old Bit definition maintained for legacy purpose */
jhon309 0:c52df770855b 3600 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
jhon309 0:c52df770855b 3601 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
jhon309 0:c52df770855b 3602
jhon309 0:c52df770855b 3603 /***************** Bit definition for RCC_APB2ENR register *****************/
jhon309 0:c52df770855b 3604 #define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
jhon309 0:c52df770855b 3605 #define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
jhon309 0:c52df770855b 3606 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
jhon309 0:c52df770855b 3607 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
jhon309 0:c52df770855b 3608 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
jhon309 0:c52df770855b 3609 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
jhon309 0:c52df770855b 3610 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
jhon309 0:c52df770855b 3611 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
jhon309 0:c52df770855b 3612 #define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
jhon309 0:c52df770855b 3613
jhon309 0:c52df770855b 3614 /* Old Bit definition maintained for legacy purpose */
jhon309 0:c52df770855b 3615 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
jhon309 0:c52df770855b 3616 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
jhon309 0:c52df770855b 3617
jhon309 0:c52df770855b 3618 /***************** Bit definition for RCC_APB1ENR register *****************/
jhon309 0:c52df770855b 3619 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
jhon309 0:c52df770855b 3620 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
jhon309 0:c52df770855b 3621 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
jhon309 0:c52df770855b 3622 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
jhon309 0:c52df770855b 3623 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
jhon309 0:c52df770855b 3624 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
jhon309 0:c52df770855b 3625 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
jhon309 0:c52df770855b 3626 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
jhon309 0:c52df770855b 3627 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART3 clock enable */
jhon309 0:c52df770855b 3628 #define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /*!< USART4 clock enable */
jhon309 0:c52df770855b 3629 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
jhon309 0:c52df770855b 3630 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
jhon309 0:c52df770855b 3631 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
jhon309 0:c52df770855b 3632 #define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
jhon309 0:c52df770855b 3633 #define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /*!< CRS clock enable */
jhon309 0:c52df770855b 3634 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
jhon309 0:c52df770855b 3635 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
jhon309 0:c52df770855b 3636 #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC clock enable */
jhon309 0:c52df770855b 3637
jhon309 0:c52df770855b 3638 /******************* Bit definition for RCC_BDCR register ******************/
jhon309 0:c52df770855b 3639 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
jhon309 0:c52df770855b 3640 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
jhon309 0:c52df770855b 3641 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
jhon309 0:c52df770855b 3642
jhon309 0:c52df770855b 3643 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
jhon309 0:c52df770855b 3644 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
jhon309 0:c52df770855b 3645 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
jhon309 0:c52df770855b 3646
jhon309 0:c52df770855b 3647 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
jhon309 0:c52df770855b 3648 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
jhon309 0:c52df770855b 3649 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
jhon309 0:c52df770855b 3650
jhon309 0:c52df770855b 3651 /*!< RTC configuration */
jhon309 0:c52df770855b 3652 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
jhon309 0:c52df770855b 3653 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
jhon309 0:c52df770855b 3654 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
jhon309 0:c52df770855b 3655 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
jhon309 0:c52df770855b 3656
jhon309 0:c52df770855b 3657 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
jhon309 0:c52df770855b 3658 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
jhon309 0:c52df770855b 3659
jhon309 0:c52df770855b 3660 /******************* Bit definition for RCC_CSR register *******************/
jhon309 0:c52df770855b 3661 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
jhon309 0:c52df770855b 3662 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
jhon309 0:c52df770855b 3663 #define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
jhon309 0:c52df770855b 3664 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
jhon309 0:c52df770855b 3665 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
jhon309 0:c52df770855b 3666 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
jhon309 0:c52df770855b 3667 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
jhon309 0:c52df770855b 3668 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
jhon309 0:c52df770855b 3669 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
jhon309 0:c52df770855b 3670 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
jhon309 0:c52df770855b 3671 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
jhon309 0:c52df770855b 3672
jhon309 0:c52df770855b 3673 /* Old Bit definition maintained for legacy purpose */
jhon309 0:c52df770855b 3674 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
jhon309 0:c52df770855b 3675
jhon309 0:c52df770855b 3676 /******************* Bit definition for RCC_AHBRSTR register ***************/
jhon309 0:c52df770855b 3677 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
jhon309 0:c52df770855b 3678 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
jhon309 0:c52df770855b 3679 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
jhon309 0:c52df770855b 3680 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD clock reset */
jhon309 0:c52df770855b 3681 #define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00200000) /*!< GPIOE clock reset */
jhon309 0:c52df770855b 3682 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF clock reset */
jhon309 0:c52df770855b 3683 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TS clock reset */
jhon309 0:c52df770855b 3684
jhon309 0:c52df770855b 3685 /* Old Bit definition maintained for legacy purpose */
jhon309 0:c52df770855b 3686 #define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */
jhon309 0:c52df770855b 3687
jhon309 0:c52df770855b 3688 /******************* Bit definition for RCC_CFGR2 register *****************/
jhon309 0:c52df770855b 3689 /*!< PREDIV configuration */
jhon309 0:c52df770855b 3690 #define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
jhon309 0:c52df770855b 3691 #define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
jhon309 0:c52df770855b 3692 #define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
jhon309 0:c52df770855b 3693 #define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
jhon309 0:c52df770855b 3694 #define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
jhon309 0:c52df770855b 3695
jhon309 0:c52df770855b 3696 #define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
jhon309 0:c52df770855b 3697 #define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
jhon309 0:c52df770855b 3698 #define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
jhon309 0:c52df770855b 3699 #define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
jhon309 0:c52df770855b 3700 #define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
jhon309 0:c52df770855b 3701 #define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
jhon309 0:c52df770855b 3702 #define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
jhon309 0:c52df770855b 3703 #define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
jhon309 0:c52df770855b 3704 #define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
jhon309 0:c52df770855b 3705 #define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
jhon309 0:c52df770855b 3706 #define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
jhon309 0:c52df770855b 3707 #define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
jhon309 0:c52df770855b 3708 #define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
jhon309 0:c52df770855b 3709 #define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
jhon309 0:c52df770855b 3710 #define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
jhon309 0:c52df770855b 3711 #define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
jhon309 0:c52df770855b 3712
jhon309 0:c52df770855b 3713 /******************* Bit definition for RCC_CFGR3 register *****************/
jhon309 0:c52df770855b 3714 /*!< USART1 Clock source selection */
jhon309 0:c52df770855b 3715 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
jhon309 0:c52df770855b 3716 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
jhon309 0:c52df770855b 3717 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
jhon309 0:c52df770855b 3718
jhon309 0:c52df770855b 3719 #define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART1 clock source */
jhon309 0:c52df770855b 3720 #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
jhon309 0:c52df770855b 3721 #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
jhon309 0:c52df770855b 3722 #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
jhon309 0:c52df770855b 3723
jhon309 0:c52df770855b 3724 /*!< I2C1 Clock source selection */
jhon309 0:c52df770855b 3725 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
jhon309 0:c52df770855b 3726
jhon309 0:c52df770855b 3727 #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
jhon309 0:c52df770855b 3728 #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
jhon309 0:c52df770855b 3729
jhon309 0:c52df770855b 3730 /*!< CEC Clock source selection */
jhon309 0:c52df770855b 3731 #define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /*!< CECSW bits */
jhon309 0:c52df770855b 3732
jhon309 0:c52df770855b 3733 #define RCC_CFGR3_CECSW_HSI_DIV244 ((uint32_t)0x00000000) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
jhon309 0:c52df770855b 3734 #define RCC_CFGR3_CECSW_LSE ((uint32_t)0x00000040) /*!< LSE clock selected as HDMI CEC entry clock source */
jhon309 0:c52df770855b 3735
jhon309 0:c52df770855b 3736 /*!< USB Clock source selection */
jhon309 0:c52df770855b 3737 #define RCC_CFGR3_USBSW ((uint32_t)0x00000080) /*!< USBSW bits */
jhon309 0:c52df770855b 3738
jhon309 0:c52df770855b 3739 #define RCC_CFGR3_USBSW_HSI48 ((uint32_t)0x00000000) /*!< HSI48 oscillator clock used as USB clock source */
jhon309 0:c52df770855b 3740 #define RCC_CFGR3_USBSW_PLLCLK ((uint32_t)0x00000080) /*!< PLLCLK selected as USB clock source */
jhon309 0:c52df770855b 3741
jhon309 0:c52df770855b 3742 /*!< USART2 Clock source selection */
jhon309 0:c52df770855b 3743 #define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
jhon309 0:c52df770855b 3744 #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
jhon309 0:c52df770855b 3745 #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
jhon309 0:c52df770855b 3746
jhon309 0:c52df770855b 3747 #define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART2 clock source */
jhon309 0:c52df770855b 3748 #define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
jhon309 0:c52df770855b 3749 #define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
jhon309 0:c52df770855b 3750 #define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
jhon309 0:c52df770855b 3751
jhon309 0:c52df770855b 3752 /******************* Bit definition for RCC_CR2 register *******************/
jhon309 0:c52df770855b 3753 #define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
jhon309 0:c52df770855b 3754 #define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
jhon309 0:c52df770855b 3755 #define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
jhon309 0:c52df770855b 3756 #define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
jhon309 0:c52df770855b 3757 #define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
jhon309 0:c52df770855b 3758 #define RCC_CR2_HSI48ON ((uint32_t)0x00010000) /*!< Internal High Speed 48MHz clock enable */
jhon309 0:c52df770855b 3759 #define RCC_CR2_HSI48RDY ((uint32_t)0x00020000) /*!< Internal High Speed 48MHz clock ready flag */
jhon309 0:c52df770855b 3760 #define RCC_CR2_HSI48CAL ((uint32_t)0xFF000000) /*!< Internal High Speed 48MHz clock Calibration */
jhon309 0:c52df770855b 3761
jhon309 0:c52df770855b 3762 /*****************************************************************************/
jhon309 0:c52df770855b 3763 /* */
jhon309 0:c52df770855b 3764 /* Real-Time Clock (RTC) */
jhon309 0:c52df770855b 3765 /* */
jhon309 0:c52df770855b 3766 /*****************************************************************************/
jhon309 0:c52df770855b 3767 /******************** Bits definition for RTC_TR register ******************/
jhon309 0:c52df770855b 3768 #define RTC_TR_PM ((uint32_t)0x00400000)
jhon309 0:c52df770855b 3769 #define RTC_TR_HT ((uint32_t)0x00300000)
jhon309 0:c52df770855b 3770 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
jhon309 0:c52df770855b 3771 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
jhon309 0:c52df770855b 3772 #define RTC_TR_HU ((uint32_t)0x000F0000)
jhon309 0:c52df770855b 3773 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
jhon309 0:c52df770855b 3774 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
jhon309 0:c52df770855b 3775 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
jhon309 0:c52df770855b 3776 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
jhon309 0:c52df770855b 3777 #define RTC_TR_MNT ((uint32_t)0x00007000)
jhon309 0:c52df770855b 3778 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
jhon309 0:c52df770855b 3779 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
jhon309 0:c52df770855b 3780 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
jhon309 0:c52df770855b 3781 #define RTC_TR_MNU ((uint32_t)0x00000F00)
jhon309 0:c52df770855b 3782 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
jhon309 0:c52df770855b 3783 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
jhon309 0:c52df770855b 3784 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
jhon309 0:c52df770855b 3785 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
jhon309 0:c52df770855b 3786 #define RTC_TR_ST ((uint32_t)0x00000070)
jhon309 0:c52df770855b 3787 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
jhon309 0:c52df770855b 3788 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
jhon309 0:c52df770855b 3789 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
jhon309 0:c52df770855b 3790 #define RTC_TR_SU ((uint32_t)0x0000000F)
jhon309 0:c52df770855b 3791 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
jhon309 0:c52df770855b 3792 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
jhon309 0:c52df770855b 3793 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
jhon309 0:c52df770855b 3794 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
jhon309 0:c52df770855b 3795
jhon309 0:c52df770855b 3796 /******************** Bits definition for RTC_DR register ******************/
jhon309 0:c52df770855b 3797 #define RTC_DR_YT ((uint32_t)0x00F00000)
jhon309 0:c52df770855b 3798 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
jhon309 0:c52df770855b 3799 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
jhon309 0:c52df770855b 3800 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
jhon309 0:c52df770855b 3801 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
jhon309 0:c52df770855b 3802 #define RTC_DR_YU ((uint32_t)0x000F0000)
jhon309 0:c52df770855b 3803 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
jhon309 0:c52df770855b 3804 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
jhon309 0:c52df770855b 3805 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
jhon309 0:c52df770855b 3806 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
jhon309 0:c52df770855b 3807 #define RTC_DR_WDU ((uint32_t)0x0000E000)
jhon309 0:c52df770855b 3808 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
jhon309 0:c52df770855b 3809 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
jhon309 0:c52df770855b 3810 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
jhon309 0:c52df770855b 3811 #define RTC_DR_MT ((uint32_t)0x00001000)
jhon309 0:c52df770855b 3812 #define RTC_DR_MU ((uint32_t)0x00000F00)
jhon309 0:c52df770855b 3813 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
jhon309 0:c52df770855b 3814 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
jhon309 0:c52df770855b 3815 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
jhon309 0:c52df770855b 3816 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
jhon309 0:c52df770855b 3817 #define RTC_DR_DT ((uint32_t)0x00000030)
jhon309 0:c52df770855b 3818 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
jhon309 0:c52df770855b 3819 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
jhon309 0:c52df770855b 3820 #define RTC_DR_DU ((uint32_t)0x0000000F)
jhon309 0:c52df770855b 3821 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
jhon309 0:c52df770855b 3822 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
jhon309 0:c52df770855b 3823 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
jhon309 0:c52df770855b 3824 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
jhon309 0:c52df770855b 3825
jhon309 0:c52df770855b 3826 /******************** Bits definition for RTC_CR register ******************/
jhon309 0:c52df770855b 3827 #define RTC_CR_COE ((uint32_t)0x00800000)
jhon309 0:c52df770855b 3828 #define RTC_CR_OSEL ((uint32_t)0x00600000)
jhon309 0:c52df770855b 3829 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
jhon309 0:c52df770855b 3830 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
jhon309 0:c52df770855b 3831 #define RTC_CR_POL ((uint32_t)0x00100000)
jhon309 0:c52df770855b 3832 #define RTC_CR_COSEL ((uint32_t)0x00080000)
jhon309 0:c52df770855b 3833 #define RTC_CR_BCK ((uint32_t)0x00040000)
jhon309 0:c52df770855b 3834 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
jhon309 0:c52df770855b 3835 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
jhon309 0:c52df770855b 3836 #define RTC_CR_TSIE ((uint32_t)0x00008000)
jhon309 0:c52df770855b 3837 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
jhon309 0:c52df770855b 3838 #define RTC_CR_TSE ((uint32_t)0x00000800)
jhon309 0:c52df770855b 3839 #define RTC_CR_WUTE ((uint32_t)0x00000400)
jhon309 0:c52df770855b 3840 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
jhon309 0:c52df770855b 3841 #define RTC_CR_FMT ((uint32_t)0x00000040)
jhon309 0:c52df770855b 3842 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
jhon309 0:c52df770855b 3843 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
jhon309 0:c52df770855b 3844 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
jhon309 0:c52df770855b 3845 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
jhon309 0:c52df770855b 3846 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
jhon309 0:c52df770855b 3847 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
jhon309 0:c52df770855b 3848 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
jhon309 0:c52df770855b 3849
jhon309 0:c52df770855b 3850 /******************** Bits definition for RTC_ISR register *****************/
jhon309 0:c52df770855b 3851 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
jhon309 0:c52df770855b 3852 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
jhon309 0:c52df770855b 3853 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
jhon309 0:c52df770855b 3854 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
jhon309 0:c52df770855b 3855 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
jhon309 0:c52df770855b 3856 #define RTC_ISR_TSF ((uint32_t)0x00000800)
jhon309 0:c52df770855b 3857 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
jhon309 0:c52df770855b 3858 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
jhon309 0:c52df770855b 3859 #define RTC_ISR_INIT ((uint32_t)0x00000080)
jhon309 0:c52df770855b 3860 #define RTC_ISR_INITF ((uint32_t)0x00000040)
jhon309 0:c52df770855b 3861 #define RTC_ISR_RSF ((uint32_t)0x00000020)
jhon309 0:c52df770855b 3862 #define RTC_ISR_INITS ((uint32_t)0x00000010)
jhon309 0:c52df770855b 3863 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
jhon309 0:c52df770855b 3864 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
jhon309 0:c52df770855b 3865 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
jhon309 0:c52df770855b 3866
jhon309 0:c52df770855b 3867 /******************** Bits definition for RTC_PRER register ****************/
jhon309 0:c52df770855b 3868 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
jhon309 0:c52df770855b 3869 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
jhon309 0:c52df770855b 3870
jhon309 0:c52df770855b 3871 /******************** Bits definition for RTC_WUTR register ****************/
jhon309 0:c52df770855b 3872 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
jhon309 0:c52df770855b 3873
jhon309 0:c52df770855b 3874 /******************** Bits definition for RTC_ALRMAR register **************/
jhon309 0:c52df770855b 3875 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
jhon309 0:c52df770855b 3876 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
jhon309 0:c52df770855b 3877 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
jhon309 0:c52df770855b 3878 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
jhon309 0:c52df770855b 3879 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
jhon309 0:c52df770855b 3880 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
jhon309 0:c52df770855b 3881 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
jhon309 0:c52df770855b 3882 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
jhon309 0:c52df770855b 3883 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
jhon309 0:c52df770855b 3884 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
jhon309 0:c52df770855b 3885 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
jhon309 0:c52df770855b 3886 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
jhon309 0:c52df770855b 3887 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
jhon309 0:c52df770855b 3888 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
jhon309 0:c52df770855b 3889 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
jhon309 0:c52df770855b 3890 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
jhon309 0:c52df770855b 3891 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
jhon309 0:c52df770855b 3892 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
jhon309 0:c52df770855b 3893 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
jhon309 0:c52df770855b 3894 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
jhon309 0:c52df770855b 3895 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
jhon309 0:c52df770855b 3896 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
jhon309 0:c52df770855b 3897 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
jhon309 0:c52df770855b 3898 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
jhon309 0:c52df770855b 3899 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
jhon309 0:c52df770855b 3900 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
jhon309 0:c52df770855b 3901 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
jhon309 0:c52df770855b 3902 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
jhon309 0:c52df770855b 3903 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
jhon309 0:c52df770855b 3904 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
jhon309 0:c52df770855b 3905 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
jhon309 0:c52df770855b 3906 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
jhon309 0:c52df770855b 3907 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
jhon309 0:c52df770855b 3908 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
jhon309 0:c52df770855b 3909 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
jhon309 0:c52df770855b 3910 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
jhon309 0:c52df770855b 3911 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
jhon309 0:c52df770855b 3912 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
jhon309 0:c52df770855b 3913 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
jhon309 0:c52df770855b 3914 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
jhon309 0:c52df770855b 3915
jhon309 0:c52df770855b 3916 /******************** Bits definition for RTC_WPR register *****************/
jhon309 0:c52df770855b 3917 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
jhon309 0:c52df770855b 3918
jhon309 0:c52df770855b 3919 /******************** Bits definition for RTC_SSR register *****************/
jhon309 0:c52df770855b 3920 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
jhon309 0:c52df770855b 3921
jhon309 0:c52df770855b 3922 /******************** Bits definition for RTC_SHIFTR register **************/
jhon309 0:c52df770855b 3923 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
jhon309 0:c52df770855b 3924 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
jhon309 0:c52df770855b 3925
jhon309 0:c52df770855b 3926 /******************** Bits definition for RTC_TSTR register ****************/
jhon309 0:c52df770855b 3927 #define RTC_TSTR_PM ((uint32_t)0x00400000)
jhon309 0:c52df770855b 3928 #define RTC_TSTR_HT ((uint32_t)0x00300000)
jhon309 0:c52df770855b 3929 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
jhon309 0:c52df770855b 3930 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
jhon309 0:c52df770855b 3931 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
jhon309 0:c52df770855b 3932 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
jhon309 0:c52df770855b 3933 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
jhon309 0:c52df770855b 3934 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
jhon309 0:c52df770855b 3935 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
jhon309 0:c52df770855b 3936 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
jhon309 0:c52df770855b 3937 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
jhon309 0:c52df770855b 3938 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
jhon309 0:c52df770855b 3939 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
jhon309 0:c52df770855b 3940 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
jhon309 0:c52df770855b 3941 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
jhon309 0:c52df770855b 3942 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
jhon309 0:c52df770855b 3943 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
jhon309 0:c52df770855b 3944 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
jhon309 0:c52df770855b 3945 #define RTC_TSTR_ST ((uint32_t)0x00000070)
jhon309 0:c52df770855b 3946 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
jhon309 0:c52df770855b 3947 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
jhon309 0:c52df770855b 3948 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
jhon309 0:c52df770855b 3949 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
jhon309 0:c52df770855b 3950 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
jhon309 0:c52df770855b 3951 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
jhon309 0:c52df770855b 3952 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
jhon309 0:c52df770855b 3953 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
jhon309 0:c52df770855b 3954
jhon309 0:c52df770855b 3955 /******************** Bits definition for RTC_TSDR register ****************/
jhon309 0:c52df770855b 3956 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
jhon309 0:c52df770855b 3957 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
jhon309 0:c52df770855b 3958 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
jhon309 0:c52df770855b 3959 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
jhon309 0:c52df770855b 3960 #define RTC_TSDR_MT ((uint32_t)0x00001000)
jhon309 0:c52df770855b 3961 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
jhon309 0:c52df770855b 3962 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
jhon309 0:c52df770855b 3963 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
jhon309 0:c52df770855b 3964 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
jhon309 0:c52df770855b 3965 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
jhon309 0:c52df770855b 3966 #define RTC_TSDR_DT ((uint32_t)0x00000030)
jhon309 0:c52df770855b 3967 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
jhon309 0:c52df770855b 3968 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
jhon309 0:c52df770855b 3969 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
jhon309 0:c52df770855b 3970 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
jhon309 0:c52df770855b 3971 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
jhon309 0:c52df770855b 3972 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
jhon309 0:c52df770855b 3973 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
jhon309 0:c52df770855b 3974
jhon309 0:c52df770855b 3975 /******************** Bits definition for RTC_TSSSR register ***************/
jhon309 0:c52df770855b 3976 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
jhon309 0:c52df770855b 3977
jhon309 0:c52df770855b 3978 /******************** Bits definition for RTC_CALR register ****************/
jhon309 0:c52df770855b 3979 #define RTC_CALR_CALP ((uint32_t)0x00008000)
jhon309 0:c52df770855b 3980 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
jhon309 0:c52df770855b 3981 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
jhon309 0:c52df770855b 3982 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
jhon309 0:c52df770855b 3983 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
jhon309 0:c52df770855b 3984 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
jhon309 0:c52df770855b 3985 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
jhon309 0:c52df770855b 3986 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
jhon309 0:c52df770855b 3987 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
jhon309 0:c52df770855b 3988 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
jhon309 0:c52df770855b 3989 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
jhon309 0:c52df770855b 3990 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
jhon309 0:c52df770855b 3991 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
jhon309 0:c52df770855b 3992
jhon309 0:c52df770855b 3993 /******************** Bits definition for RTC_TAFCR register ***************/
jhon309 0:c52df770855b 3994 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
jhon309 0:c52df770855b 3995 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
jhon309 0:c52df770855b 3996 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
jhon309 0:c52df770855b 3997 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
jhon309 0:c52df770855b 3998 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
jhon309 0:c52df770855b 3999 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
jhon309 0:c52df770855b 4000 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
jhon309 0:c52df770855b 4001 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
jhon309 0:c52df770855b 4002 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
jhon309 0:c52df770855b 4003 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
jhon309 0:c52df770855b 4004 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
jhon309 0:c52df770855b 4005 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
jhon309 0:c52df770855b 4006 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
jhon309 0:c52df770855b 4007 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
jhon309 0:c52df770855b 4008 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
jhon309 0:c52df770855b 4009 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
jhon309 0:c52df770855b 4010 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
jhon309 0:c52df770855b 4011 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
jhon309 0:c52df770855b 4012 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
jhon309 0:c52df770855b 4013 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
jhon309 0:c52df770855b 4014
jhon309 0:c52df770855b 4015 /******************** Bits definition for RTC_ALRMASSR register ************/
jhon309 0:c52df770855b 4016 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
jhon309 0:c52df770855b 4017 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
jhon309 0:c52df770855b 4018 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
jhon309 0:c52df770855b 4019 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
jhon309 0:c52df770855b 4020 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
jhon309 0:c52df770855b 4021 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
jhon309 0:c52df770855b 4022
jhon309 0:c52df770855b 4023 /******************** Bits definition for RTC_BKP0R register ***************/
jhon309 0:c52df770855b 4024 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
jhon309 0:c52df770855b 4025
jhon309 0:c52df770855b 4026 /******************** Bits definition for RTC_BKP1R register ***************/
jhon309 0:c52df770855b 4027 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
jhon309 0:c52df770855b 4028
jhon309 0:c52df770855b 4029 /******************** Bits definition for RTC_BKP2R register ***************/
jhon309 0:c52df770855b 4030 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
jhon309 0:c52df770855b 4031
jhon309 0:c52df770855b 4032 /******************** Bits definition for RTC_BKP3R register ***************/
jhon309 0:c52df770855b 4033 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
jhon309 0:c52df770855b 4034
jhon309 0:c52df770855b 4035 /******************** Bits definition for RTC_BKP4R register ***************/
jhon309 0:c52df770855b 4036 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
jhon309 0:c52df770855b 4037
jhon309 0:c52df770855b 4038 /******************** Number of backup registers ******************************/
jhon309 0:c52df770855b 4039 #define RTC_BKP_NUMBER ((uint32_t)0x00000005)
jhon309 0:c52df770855b 4040
jhon309 0:c52df770855b 4041 /*****************************************************************************/
jhon309 0:c52df770855b 4042 /* */
jhon309 0:c52df770855b 4043 /* Serial Peripheral Interface (SPI) */
jhon309 0:c52df770855b 4044 /* */
jhon309 0:c52df770855b 4045 /*****************************************************************************/
jhon309 0:c52df770855b 4046 /******************* Bit definition for SPI_CR1 register *******************/
jhon309 0:c52df770855b 4047 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
jhon309 0:c52df770855b 4048 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
jhon309 0:c52df770855b 4049 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
jhon309 0:c52df770855b 4050 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
jhon309 0:c52df770855b 4051 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
jhon309 0:c52df770855b 4052 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
jhon309 0:c52df770855b 4053 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
jhon309 0:c52df770855b 4054 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
jhon309 0:c52df770855b 4055 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
jhon309 0:c52df770855b 4056 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
jhon309 0:c52df770855b 4057 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
jhon309 0:c52df770855b 4058 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
jhon309 0:c52df770855b 4059 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
jhon309 0:c52df770855b 4060 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
jhon309 0:c52df770855b 4061 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
jhon309 0:c52df770855b 4062 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
jhon309 0:c52df770855b 4063 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
jhon309 0:c52df770855b 4064
jhon309 0:c52df770855b 4065 /******************* Bit definition for SPI_CR2 register *******************/
jhon309 0:c52df770855b 4066 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
jhon309 0:c52df770855b 4067 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
jhon309 0:c52df770855b 4068 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
jhon309 0:c52df770855b 4069 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
jhon309 0:c52df770855b 4070 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
jhon309 0:c52df770855b 4071 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
jhon309 0:c52df770855b 4072 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
jhon309 0:c52df770855b 4073 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
jhon309 0:c52df770855b 4074 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
jhon309 0:c52df770855b 4075 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
jhon309 0:c52df770855b 4076 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
jhon309 0:c52df770855b 4077 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
jhon309 0:c52df770855b 4078 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
jhon309 0:c52df770855b 4079 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
jhon309 0:c52df770855b 4080 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
jhon309 0:c52df770855b 4081 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
jhon309 0:c52df770855b 4082
jhon309 0:c52df770855b 4083 /******************** Bit definition for SPI_SR register *******************/
jhon309 0:c52df770855b 4084 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
jhon309 0:c52df770855b 4085 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
jhon309 0:c52df770855b 4086 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
jhon309 0:c52df770855b 4087 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
jhon309 0:c52df770855b 4088 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
jhon309 0:c52df770855b 4089 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
jhon309 0:c52df770855b 4090 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
jhon309 0:c52df770855b 4091 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
jhon309 0:c52df770855b 4092 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
jhon309 0:c52df770855b 4093 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
jhon309 0:c52df770855b 4094 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
jhon309 0:c52df770855b 4095 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
jhon309 0:c52df770855b 4096 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
jhon309 0:c52df770855b 4097 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
jhon309 0:c52df770855b 4098 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
jhon309 0:c52df770855b 4099
jhon309 0:c52df770855b 4100 /******************** Bit definition for SPI_DR register *******************/
jhon309 0:c52df770855b 4101 #define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data Register */
jhon309 0:c52df770855b 4102
jhon309 0:c52df770855b 4103 /******************* Bit definition for SPI_CRCPR register *****************/
jhon309 0:c52df770855b 4104 #define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /*!< CRC polynomial register */
jhon309 0:c52df770855b 4105
jhon309 0:c52df770855b 4106 /****************** Bit definition for SPI_RXCRCR register *****************/
jhon309 0:c52df770855b 4107 #define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /*!< Rx CRC Register */
jhon309 0:c52df770855b 4108
jhon309 0:c52df770855b 4109 /****************** Bit definition for SPI_TXCRCR register *****************/
jhon309 0:c52df770855b 4110 #define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /*!< Tx CRC Register */
jhon309 0:c52df770855b 4111
jhon309 0:c52df770855b 4112 /****************** Bit definition for SPI_I2SCFGR register ****************/
jhon309 0:c52df770855b 4113 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
jhon309 0:c52df770855b 4114 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
jhon309 0:c52df770855b 4115 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
jhon309 0:c52df770855b 4116 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
jhon309 0:c52df770855b 4117 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
jhon309 0:c52df770855b 4118 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
jhon309 0:c52df770855b 4119 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
jhon309 0:c52df770855b 4120 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
jhon309 0:c52df770855b 4121 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
jhon309 0:c52df770855b 4122 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
jhon309 0:c52df770855b 4123 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
jhon309 0:c52df770855b 4124 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
jhon309 0:c52df770855b 4125 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
jhon309 0:c52df770855b 4126 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
jhon309 0:c52df770855b 4127
jhon309 0:c52df770855b 4128 /****************** Bit definition for SPI_I2SPR register ******************/
jhon309 0:c52df770855b 4129 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
jhon309 0:c52df770855b 4130 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
jhon309 0:c52df770855b 4131 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
jhon309 0:c52df770855b 4132
jhon309 0:c52df770855b 4133 /*****************************************************************************/
jhon309 0:c52df770855b 4134 /* */
jhon309 0:c52df770855b 4135 /* System Configuration (SYSCFG) */
jhon309 0:c52df770855b 4136 /* */
jhon309 0:c52df770855b 4137 /*****************************************************************************/
jhon309 0:c52df770855b 4138 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
jhon309 0:c52df770855b 4139 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
jhon309 0:c52df770855b 4140 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
jhon309 0:c52df770855b 4141 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
jhon309 0:c52df770855b 4142
jhon309 0:c52df770855b 4143 #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x7F007F00) /*!< DMA remap mask */
jhon309 0:c52df770855b 4144 #define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
jhon309 0:c52df770855b 4145 #define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
jhon309 0:c52df770855b 4146 #define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
jhon309 0:c52df770855b 4147 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
jhon309 0:c52df770855b 4148 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
jhon309 0:c52df770855b 4149 #define SYSCFG_CFGR1_TIM16_DMA_RMP2 ((uint32_t)0x00002000) /*!< Timer 16 DMA remap 2 */
jhon309 0:c52df770855b 4150 #define SYSCFG_CFGR1_TIM17_DMA_RMP2 ((uint32_t)0x00004000) /*!< Timer 17 DMA remap 2 */
jhon309 0:c52df770855b 4151 #define SYSCFG_CFGR1_SPI2_DMA_RMP ((uint32_t)0x01000000) /*!< SPI2 DMA remap */
jhon309 0:c52df770855b 4152 #define SYSCFG_CFGR1_USART2_DMA_RMP ((uint32_t)0x02000000) /*!< USART2 DMA remap */
jhon309 0:c52df770855b 4153 #define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /*!< USART3 DMA remap */
jhon309 0:c52df770855b 4154 #define SYSCFG_CFGR1_I2C1_DMA_RMP ((uint32_t)0x08000000) /*!< I2C1 DMA remap */
jhon309 0:c52df770855b 4155 #define SYSCFG_CFGR1_TIM1_DMA_RMP ((uint32_t)0x10000000) /*!< TIM1 DMA remap */
jhon309 0:c52df770855b 4156 #define SYSCFG_CFGR1_TIM2_DMA_RMP ((uint32_t)0x20000000) /*!< TIM2 DMA remap */
jhon309 0:c52df770855b 4157 #define SYSCFG_CFGR1_TIM3_DMA_RMP ((uint32_t)0x40000000) /*!< TIM3 DMA remap */
jhon309 0:c52df770855b 4158
jhon309 0:c52df770855b 4159 #define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
jhon309 0:c52df770855b 4160 #define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
jhon309 0:c52df770855b 4161 #define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
jhon309 0:c52df770855b 4162 #define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
jhon309 0:c52df770855b 4163 #define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
jhon309 0:c52df770855b 4164 #define SYSCFG_CFGR1_I2C_FMP_I2C2 ((uint32_t)0x00200000) /*!< Enable I2C2 Fast mode plus */
jhon309 0:c52df770855b 4165
jhon309 0:c52df770855b 4166 /***************** Bit definition for SYSCFG_EXTICR1 register **************/
jhon309 0:c52df770855b 4167 #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
jhon309 0:c52df770855b 4168 #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
jhon309 0:c52df770855b 4169 #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
jhon309 0:c52df770855b 4170 #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
jhon309 0:c52df770855b 4171
jhon309 0:c52df770855b 4172 /**
jhon309 0:c52df770855b 4173 * @brief EXTI0 configuration
jhon309 0:c52df770855b 4174 */
jhon309 0:c52df770855b 4175 #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
jhon309 0:c52df770855b 4176 #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
jhon309 0:c52df770855b 4177 #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
jhon309 0:c52df770855b 4178 #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
jhon309 0:c52df770855b 4179 #define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
jhon309 0:c52df770855b 4180 #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
jhon309 0:c52df770855b 4181
jhon309 0:c52df770855b 4182 /**
jhon309 0:c52df770855b 4183 * @brief EXTI1 configuration
jhon309 0:c52df770855b 4184 */
jhon309 0:c52df770855b 4185 #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
jhon309 0:c52df770855b 4186 #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
jhon309 0:c52df770855b 4187 #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
jhon309 0:c52df770855b 4188 #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
jhon309 0:c52df770855b 4189 #define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
jhon309 0:c52df770855b 4190 #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
jhon309 0:c52df770855b 4191
jhon309 0:c52df770855b 4192 /**
jhon309 0:c52df770855b 4193 * @brief EXTI2 configuration
jhon309 0:c52df770855b 4194 */
jhon309 0:c52df770855b 4195 #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
jhon309 0:c52df770855b 4196 #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
jhon309 0:c52df770855b 4197 #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
jhon309 0:c52df770855b 4198 #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
jhon309 0:c52df770855b 4199 #define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
jhon309 0:c52df770855b 4200 #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
jhon309 0:c52df770855b 4201
jhon309 0:c52df770855b 4202 /**
jhon309 0:c52df770855b 4203 * @brief EXTI3 configuration
jhon309 0:c52df770855b 4204 */
jhon309 0:c52df770855b 4205 #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
jhon309 0:c52df770855b 4206 #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
jhon309 0:c52df770855b 4207 #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
jhon309 0:c52df770855b 4208 #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
jhon309 0:c52df770855b 4209 #define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
jhon309 0:c52df770855b 4210 #define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
jhon309 0:c52df770855b 4211
jhon309 0:c52df770855b 4212 /***************** Bit definition for SYSCFG_EXTICR2 register **************/
jhon309 0:c52df770855b 4213 #define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
jhon309 0:c52df770855b 4214 #define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
jhon309 0:c52df770855b 4215 #define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
jhon309 0:c52df770855b 4216 #define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
jhon309 0:c52df770855b 4217
jhon309 0:c52df770855b 4218 /**
jhon309 0:c52df770855b 4219 * @brief EXTI4 configuration
jhon309 0:c52df770855b 4220 */
jhon309 0:c52df770855b 4221 #define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
jhon309 0:c52df770855b 4222 #define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
jhon309 0:c52df770855b 4223 #define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
jhon309 0:c52df770855b 4224 #define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
jhon309 0:c52df770855b 4225 #define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
jhon309 0:c52df770855b 4226 #define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
jhon309 0:c52df770855b 4227
jhon309 0:c52df770855b 4228 /**
jhon309 0:c52df770855b 4229 * @brief EXTI5 configuration
jhon309 0:c52df770855b 4230 */
jhon309 0:c52df770855b 4231 #define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
jhon309 0:c52df770855b 4232 #define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
jhon309 0:c52df770855b 4233 #define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
jhon309 0:c52df770855b 4234 #define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
jhon309 0:c52df770855b 4235 #define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
jhon309 0:c52df770855b 4236 #define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
jhon309 0:c52df770855b 4237
jhon309 0:c52df770855b 4238 /**
jhon309 0:c52df770855b 4239 * @brief EXTI6 configuration
jhon309 0:c52df770855b 4240 */
jhon309 0:c52df770855b 4241 #define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
jhon309 0:c52df770855b 4242 #define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
jhon309 0:c52df770855b 4243 #define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
jhon309 0:c52df770855b 4244 #define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
jhon309 0:c52df770855b 4245 #define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
jhon309 0:c52df770855b 4246 #define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
jhon309 0:c52df770855b 4247
jhon309 0:c52df770855b 4248 /**
jhon309 0:c52df770855b 4249 * @brief EXTI7 configuration
jhon309 0:c52df770855b 4250 */
jhon309 0:c52df770855b 4251 #define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
jhon309 0:c52df770855b 4252 #define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
jhon309 0:c52df770855b 4253 #define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
jhon309 0:c52df770855b 4254 #define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
jhon309 0:c52df770855b 4255 #define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
jhon309 0:c52df770855b 4256 #define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
jhon309 0:c52df770855b 4257
jhon309 0:c52df770855b 4258 /***************** Bit definition for SYSCFG_EXTICR3 register **************/
jhon309 0:c52df770855b 4259 #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
jhon309 0:c52df770855b 4260 #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
jhon309 0:c52df770855b 4261 #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
jhon309 0:c52df770855b 4262 #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
jhon309 0:c52df770855b 4263
jhon309 0:c52df770855b 4264 /**
jhon309 0:c52df770855b 4265 * @brief EXTI8 configuration
jhon309 0:c52df770855b 4266 */
jhon309 0:c52df770855b 4267 #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
jhon309 0:c52df770855b 4268 #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
jhon309 0:c52df770855b 4269 #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
jhon309 0:c52df770855b 4270 #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
jhon309 0:c52df770855b 4271 #define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
jhon309 0:c52df770855b 4272
jhon309 0:c52df770855b 4273 /**
jhon309 0:c52df770855b 4274 * @brief EXTI9 configuration
jhon309 0:c52df770855b 4275 */
jhon309 0:c52df770855b 4276 #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
jhon309 0:c52df770855b 4277 #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
jhon309 0:c52df770855b 4278 #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
jhon309 0:c52df770855b 4279 #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
jhon309 0:c52df770855b 4280 #define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
jhon309 0:c52df770855b 4281 #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
jhon309 0:c52df770855b 4282
jhon309 0:c52df770855b 4283 /**
jhon309 0:c52df770855b 4284 * @brief EXTI10 configuration
jhon309 0:c52df770855b 4285 */
jhon309 0:c52df770855b 4286 #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
jhon309 0:c52df770855b 4287 #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
jhon309 0:c52df770855b 4288 #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
jhon309 0:c52df770855b 4289 #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PE[10] pin */
jhon309 0:c52df770855b 4290 #define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PD[10] pin */
jhon309 0:c52df770855b 4291 #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
jhon309 0:c52df770855b 4292
jhon309 0:c52df770855b 4293 /**
jhon309 0:c52df770855b 4294 * @brief EXTI11 configuration
jhon309 0:c52df770855b 4295 */
jhon309 0:c52df770855b 4296 #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
jhon309 0:c52df770855b 4297 #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
jhon309 0:c52df770855b 4298 #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
jhon309 0:c52df770855b 4299 #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
jhon309 0:c52df770855b 4300 #define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
jhon309 0:c52df770855b 4301
jhon309 0:c52df770855b 4302 /***************** Bit definition for SYSCFG_EXTICR4 register **************/
jhon309 0:c52df770855b 4303 #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
jhon309 0:c52df770855b 4304 #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
jhon309 0:c52df770855b 4305 #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
jhon309 0:c52df770855b 4306 #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
jhon309 0:c52df770855b 4307
jhon309 0:c52df770855b 4308 /**
jhon309 0:c52df770855b 4309 * @brief EXTI12 configuration
jhon309 0:c52df770855b 4310 */
jhon309 0:c52df770855b 4311 #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
jhon309 0:c52df770855b 4312 #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
jhon309 0:c52df770855b 4313 #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
jhon309 0:c52df770855b 4314 #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
jhon309 0:c52df770855b 4315 #define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
jhon309 0:c52df770855b 4316
jhon309 0:c52df770855b 4317 /**
jhon309 0:c52df770855b 4318 * @brief EXTI13 configuration
jhon309 0:c52df770855b 4319 */
jhon309 0:c52df770855b 4320 #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
jhon309 0:c52df770855b 4321 #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
jhon309 0:c52df770855b 4322 #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
jhon309 0:c52df770855b 4323 #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
jhon309 0:c52df770855b 4324 #define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
jhon309 0:c52df770855b 4325
jhon309 0:c52df770855b 4326 /**
jhon309 0:c52df770855b 4327 * @brief EXTI14 configuration
jhon309 0:c52df770855b 4328 */
jhon309 0:c52df770855b 4329 #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
jhon309 0:c52df770855b 4330 #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
jhon309 0:c52df770855b 4331 #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
jhon309 0:c52df770855b 4332 #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
jhon309 0:c52df770855b 4333 #define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
jhon309 0:c52df770855b 4334
jhon309 0:c52df770855b 4335 /**
jhon309 0:c52df770855b 4336 * @brief EXTI15 configuration
jhon309 0:c52df770855b 4337 */
jhon309 0:c52df770855b 4338 #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
jhon309 0:c52df770855b 4339 #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
jhon309 0:c52df770855b 4340 #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
jhon309 0:c52df770855b 4341 #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
jhon309 0:c52df770855b 4342 #define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
jhon309 0:c52df770855b 4343
jhon309 0:c52df770855b 4344 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
jhon309 0:c52df770855b 4345 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
jhon309 0:c52df770855b 4346 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
jhon309 0:c52df770855b 4347 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
jhon309 0:c52df770855b 4348 #define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
jhon309 0:c52df770855b 4349 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
jhon309 0:c52df770855b 4350
jhon309 0:c52df770855b 4351 /*****************************************************************************/
jhon309 0:c52df770855b 4352 /* */
jhon309 0:c52df770855b 4353 /* Timers (TIM) */
jhon309 0:c52df770855b 4354 /* */
jhon309 0:c52df770855b 4355 /*****************************************************************************/
jhon309 0:c52df770855b 4356 /******************* Bit definition for TIM_CR1 register *******************/
jhon309 0:c52df770855b 4357 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
jhon309 0:c52df770855b 4358 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
jhon309 0:c52df770855b 4359 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
jhon309 0:c52df770855b 4360 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
jhon309 0:c52df770855b 4361 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
jhon309 0:c52df770855b 4362
jhon309 0:c52df770855b 4363 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
jhon309 0:c52df770855b 4364 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
jhon309 0:c52df770855b 4365 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
jhon309 0:c52df770855b 4366
jhon309 0:c52df770855b 4367 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
jhon309 0:c52df770855b 4368
jhon309 0:c52df770855b 4369 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
jhon309 0:c52df770855b 4370 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
jhon309 0:c52df770855b 4371 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
jhon309 0:c52df770855b 4372
jhon309 0:c52df770855b 4373 /******************* Bit definition for TIM_CR2 register *******************/
jhon309 0:c52df770855b 4374 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
jhon309 0:c52df770855b 4375 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
jhon309 0:c52df770855b 4376 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
jhon309 0:c52df770855b 4377
jhon309 0:c52df770855b 4378 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
jhon309 0:c52df770855b 4379 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
jhon309 0:c52df770855b 4380 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
jhon309 0:c52df770855b 4381 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
jhon309 0:c52df770855b 4382
jhon309 0:c52df770855b 4383 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
jhon309 0:c52df770855b 4384 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
jhon309 0:c52df770855b 4385 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
jhon309 0:c52df770855b 4386 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
jhon309 0:c52df770855b 4387 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
jhon309 0:c52df770855b 4388 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
jhon309 0:c52df770855b 4389 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
jhon309 0:c52df770855b 4390 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
jhon309 0:c52df770855b 4391
jhon309 0:c52df770855b 4392 /******************* Bit definition for TIM_SMCR register ******************/
jhon309 0:c52df770855b 4393 #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
jhon309 0:c52df770855b 4394 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
jhon309 0:c52df770855b 4395 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
jhon309 0:c52df770855b 4396 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
jhon309 0:c52df770855b 4397
jhon309 0:c52df770855b 4398 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
jhon309 0:c52df770855b 4399
jhon309 0:c52df770855b 4400 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
jhon309 0:c52df770855b 4401 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
jhon309 0:c52df770855b 4402 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
jhon309 0:c52df770855b 4403 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
jhon309 0:c52df770855b 4404
jhon309 0:c52df770855b 4405 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
jhon309 0:c52df770855b 4406
jhon309 0:c52df770855b 4407 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
jhon309 0:c52df770855b 4408 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
jhon309 0:c52df770855b 4409 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
jhon309 0:c52df770855b 4410 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
jhon309 0:c52df770855b 4411 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
jhon309 0:c52df770855b 4412
jhon309 0:c52df770855b 4413 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
jhon309 0:c52df770855b 4414 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
jhon309 0:c52df770855b 4415 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
jhon309 0:c52df770855b 4416
jhon309 0:c52df770855b 4417 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
jhon309 0:c52df770855b 4418 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
jhon309 0:c52df770855b 4419
jhon309 0:c52df770855b 4420 /******************* Bit definition for TIM_DIER register ******************/
jhon309 0:c52df770855b 4421 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
jhon309 0:c52df770855b 4422 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
jhon309 0:c52df770855b 4423 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
jhon309 0:c52df770855b 4424 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
jhon309 0:c52df770855b 4425 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
jhon309 0:c52df770855b 4426 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
jhon309 0:c52df770855b 4427 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
jhon309 0:c52df770855b 4428 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
jhon309 0:c52df770855b 4429 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
jhon309 0:c52df770855b 4430 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
jhon309 0:c52df770855b 4431 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
jhon309 0:c52df770855b 4432 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
jhon309 0:c52df770855b 4433 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
jhon309 0:c52df770855b 4434 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
jhon309 0:c52df770855b 4435 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
jhon309 0:c52df770855b 4436
jhon309 0:c52df770855b 4437 /******************** Bit definition for TIM_SR register *******************/
jhon309 0:c52df770855b 4438 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
jhon309 0:c52df770855b 4439 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
jhon309 0:c52df770855b 4440 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
jhon309 0:c52df770855b 4441 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
jhon309 0:c52df770855b 4442 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
jhon309 0:c52df770855b 4443 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
jhon309 0:c52df770855b 4444 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
jhon309 0:c52df770855b 4445 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
jhon309 0:c52df770855b 4446 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
jhon309 0:c52df770855b 4447 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
jhon309 0:c52df770855b 4448 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
jhon309 0:c52df770855b 4449 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
jhon309 0:c52df770855b 4450
jhon309 0:c52df770855b 4451 /******************* Bit definition for TIM_EGR register *******************/
jhon309 0:c52df770855b 4452 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
jhon309 0:c52df770855b 4453 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
jhon309 0:c52df770855b 4454 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
jhon309 0:c52df770855b 4455 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
jhon309 0:c52df770855b 4456 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
jhon309 0:c52df770855b 4457 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
jhon309 0:c52df770855b 4458 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
jhon309 0:c52df770855b 4459 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
jhon309 0:c52df770855b 4460
jhon309 0:c52df770855b 4461 /****************** Bit definition for TIM_CCMR1 register ******************/
jhon309 0:c52df770855b 4462 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
jhon309 0:c52df770855b 4463 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
jhon309 0:c52df770855b 4464 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
jhon309 0:c52df770855b 4465
jhon309 0:c52df770855b 4466 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
jhon309 0:c52df770855b 4467 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
jhon309 0:c52df770855b 4468
jhon309 0:c52df770855b 4469 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
jhon309 0:c52df770855b 4470 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
jhon309 0:c52df770855b 4471 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
jhon309 0:c52df770855b 4472 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
jhon309 0:c52df770855b 4473
jhon309 0:c52df770855b 4474 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
jhon309 0:c52df770855b 4475
jhon309 0:c52df770855b 4476 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
jhon309 0:c52df770855b 4477 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
jhon309 0:c52df770855b 4478 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
jhon309 0:c52df770855b 4479
jhon309 0:c52df770855b 4480 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
jhon309 0:c52df770855b 4481 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
jhon309 0:c52df770855b 4482
jhon309 0:c52df770855b 4483 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
jhon309 0:c52df770855b 4484 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
jhon309 0:c52df770855b 4485 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
jhon309 0:c52df770855b 4486 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
jhon309 0:c52df770855b 4487
jhon309 0:c52df770855b 4488 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
jhon309 0:c52df770855b 4489
jhon309 0:c52df770855b 4490 /*---------------------------------------------------------------------------*/
jhon309 0:c52df770855b 4491
jhon309 0:c52df770855b 4492 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
jhon309 0:c52df770855b 4493 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
jhon309 0:c52df770855b 4494 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
jhon309 0:c52df770855b 4495
jhon309 0:c52df770855b 4496 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
jhon309 0:c52df770855b 4497 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
jhon309 0:c52df770855b 4498 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
jhon309 0:c52df770855b 4499 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
jhon309 0:c52df770855b 4500 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
jhon309 0:c52df770855b 4501
jhon309 0:c52df770855b 4502 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
jhon309 0:c52df770855b 4503 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
jhon309 0:c52df770855b 4504 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
jhon309 0:c52df770855b 4505
jhon309 0:c52df770855b 4506 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
jhon309 0:c52df770855b 4507 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
jhon309 0:c52df770855b 4508 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
jhon309 0:c52df770855b 4509 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
jhon309 0:c52df770855b 4510 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
jhon309 0:c52df770855b 4511
jhon309 0:c52df770855b 4512 /****************** Bit definition for TIM_CCMR2 register ******************/
jhon309 0:c52df770855b 4513 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
jhon309 0:c52df770855b 4514 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
jhon309 0:c52df770855b 4515 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
jhon309 0:c52df770855b 4516
jhon309 0:c52df770855b 4517 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
jhon309 0:c52df770855b 4518 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
jhon309 0:c52df770855b 4519
jhon309 0:c52df770855b 4520 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
jhon309 0:c52df770855b 4521 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
jhon309 0:c52df770855b 4522 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
jhon309 0:c52df770855b 4523 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
jhon309 0:c52df770855b 4524
jhon309 0:c52df770855b 4525 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
jhon309 0:c52df770855b 4526
jhon309 0:c52df770855b 4527 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
jhon309 0:c52df770855b 4528 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
jhon309 0:c52df770855b 4529 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
jhon309 0:c52df770855b 4530
jhon309 0:c52df770855b 4531 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
jhon309 0:c52df770855b 4532 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
jhon309 0:c52df770855b 4533
jhon309 0:c52df770855b 4534 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
jhon309 0:c52df770855b 4535 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
jhon309 0:c52df770855b 4536 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
jhon309 0:c52df770855b 4537 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
jhon309 0:c52df770855b 4538
jhon309 0:c52df770855b 4539 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
jhon309 0:c52df770855b 4540
jhon309 0:c52df770855b 4541 /*---------------------------------------------------------------------------*/
jhon309 0:c52df770855b 4542
jhon309 0:c52df770855b 4543 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
jhon309 0:c52df770855b 4544 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
jhon309 0:c52df770855b 4545 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
jhon309 0:c52df770855b 4546
jhon309 0:c52df770855b 4547 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
jhon309 0:c52df770855b 4548 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
jhon309 0:c52df770855b 4549 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
jhon309 0:c52df770855b 4550 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
jhon309 0:c52df770855b 4551 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
jhon309 0:c52df770855b 4552
jhon309 0:c52df770855b 4553 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
jhon309 0:c52df770855b 4554 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
jhon309 0:c52df770855b 4555 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
jhon309 0:c52df770855b 4556
jhon309 0:c52df770855b 4557 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
jhon309 0:c52df770855b 4558 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
jhon309 0:c52df770855b 4559 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
jhon309 0:c52df770855b 4560 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
jhon309 0:c52df770855b 4561 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
jhon309 0:c52df770855b 4562
jhon309 0:c52df770855b 4563 /******************* Bit definition for TIM_CCER register ******************/
jhon309 0:c52df770855b 4564 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
jhon309 0:c52df770855b 4565 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
jhon309 0:c52df770855b 4566 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
jhon309 0:c52df770855b 4567 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
jhon309 0:c52df770855b 4568 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
jhon309 0:c52df770855b 4569 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
jhon309 0:c52df770855b 4570 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
jhon309 0:c52df770855b 4571 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
jhon309 0:c52df770855b 4572 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
jhon309 0:c52df770855b 4573 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
jhon309 0:c52df770855b 4574 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
jhon309 0:c52df770855b 4575 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
jhon309 0:c52df770855b 4576 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
jhon309 0:c52df770855b 4577 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
jhon309 0:c52df770855b 4578 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
jhon309 0:c52df770855b 4579
jhon309 0:c52df770855b 4580 /******************* Bit definition for TIM_CNT register *******************/
jhon309 0:c52df770855b 4581 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
jhon309 0:c52df770855b 4582
jhon309 0:c52df770855b 4583 /******************* Bit definition for TIM_PSC register *******************/
jhon309 0:c52df770855b 4584 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
jhon309 0:c52df770855b 4585
jhon309 0:c52df770855b 4586 /******************* Bit definition for TIM_ARR register *******************/
jhon309 0:c52df770855b 4587 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
jhon309 0:c52df770855b 4588
jhon309 0:c52df770855b 4589 /******************* Bit definition for TIM_RCR register *******************/
jhon309 0:c52df770855b 4590 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
jhon309 0:c52df770855b 4591
jhon309 0:c52df770855b 4592 /******************* Bit definition for TIM_CCR1 register ******************/
jhon309 0:c52df770855b 4593 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
jhon309 0:c52df770855b 4594
jhon309 0:c52df770855b 4595 /******************* Bit definition for TIM_CCR2 register ******************/
jhon309 0:c52df770855b 4596 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
jhon309 0:c52df770855b 4597
jhon309 0:c52df770855b 4598 /******************* Bit definition for TIM_CCR3 register ******************/
jhon309 0:c52df770855b 4599 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
jhon309 0:c52df770855b 4600
jhon309 0:c52df770855b 4601 /******************* Bit definition for TIM_CCR4 register ******************/
jhon309 0:c52df770855b 4602 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
jhon309 0:c52df770855b 4603
jhon309 0:c52df770855b 4604 /******************* Bit definition for TIM_BDTR register ******************/
jhon309 0:c52df770855b 4605 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
jhon309 0:c52df770855b 4606 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
jhon309 0:c52df770855b 4607 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
jhon309 0:c52df770855b 4608 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
jhon309 0:c52df770855b 4609 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
jhon309 0:c52df770855b 4610 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
jhon309 0:c52df770855b 4611 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
jhon309 0:c52df770855b 4612 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
jhon309 0:c52df770855b 4613 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
jhon309 0:c52df770855b 4614
jhon309 0:c52df770855b 4615 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
jhon309 0:c52df770855b 4616 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
jhon309 0:c52df770855b 4617 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
jhon309 0:c52df770855b 4618
jhon309 0:c52df770855b 4619 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
jhon309 0:c52df770855b 4620 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
jhon309 0:c52df770855b 4621 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
jhon309 0:c52df770855b 4622 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
jhon309 0:c52df770855b 4623 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
jhon309 0:c52df770855b 4624 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
jhon309 0:c52df770855b 4625
jhon309 0:c52df770855b 4626 /******************* Bit definition for TIM_DCR register *******************/
jhon309 0:c52df770855b 4627 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
jhon309 0:c52df770855b 4628 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
jhon309 0:c52df770855b 4629 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
jhon309 0:c52df770855b 4630 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
jhon309 0:c52df770855b 4631 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
jhon309 0:c52df770855b 4632 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
jhon309 0:c52df770855b 4633
jhon309 0:c52df770855b 4634 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
jhon309 0:c52df770855b 4635 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
jhon309 0:c52df770855b 4636 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
jhon309 0:c52df770855b 4637 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
jhon309 0:c52df770855b 4638 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
jhon309 0:c52df770855b 4639 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
jhon309 0:c52df770855b 4640
jhon309 0:c52df770855b 4641 /******************* Bit definition for TIM_DMAR register ******************/
jhon309 0:c52df770855b 4642 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
jhon309 0:c52df770855b 4643
jhon309 0:c52df770855b 4644 /******************* Bit definition for TIM14_OR register ********************/
jhon309 0:c52df770855b 4645 #define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
jhon309 0:c52df770855b 4646 #define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
jhon309 0:c52df770855b 4647 #define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
jhon309 0:c52df770855b 4648
jhon309 0:c52df770855b 4649 /******************************************************************************/
jhon309 0:c52df770855b 4650 /* */
jhon309 0:c52df770855b 4651 /* Touch Sensing Controller (TSC) */
jhon309 0:c52df770855b 4652 /* */
jhon309 0:c52df770855b 4653 /******************************************************************************/
jhon309 0:c52df770855b 4654 /******************* Bit definition for TSC_CR register *********************/
jhon309 0:c52df770855b 4655 #define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
jhon309 0:c52df770855b 4656 #define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
jhon309 0:c52df770855b 4657 #define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
jhon309 0:c52df770855b 4658 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
jhon309 0:c52df770855b 4659 #define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
jhon309 0:c52df770855b 4660
jhon309 0:c52df770855b 4661 #define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
jhon309 0:c52df770855b 4662 #define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
jhon309 0:c52df770855b 4663 #define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
jhon309 0:c52df770855b 4664 #define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
jhon309 0:c52df770855b 4665
jhon309 0:c52df770855b 4666 #define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
jhon309 0:c52df770855b 4667 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
jhon309 0:c52df770855b 4668 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
jhon309 0:c52df770855b 4669 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
jhon309 0:c52df770855b 4670
jhon309 0:c52df770855b 4671 #define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
jhon309 0:c52df770855b 4672 #define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
jhon309 0:c52df770855b 4673
jhon309 0:c52df770855b 4674 #define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
jhon309 0:c52df770855b 4675 #define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
jhon309 0:c52df770855b 4676 #define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
jhon309 0:c52df770855b 4677 #define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
jhon309 0:c52df770855b 4678 #define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
jhon309 0:c52df770855b 4679 #define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
jhon309 0:c52df770855b 4680 #define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
jhon309 0:c52df770855b 4681 #define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
jhon309 0:c52df770855b 4682
jhon309 0:c52df770855b 4683 #define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
jhon309 0:c52df770855b 4684 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
jhon309 0:c52df770855b 4685 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
jhon309 0:c52df770855b 4686 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
jhon309 0:c52df770855b 4687 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
jhon309 0:c52df770855b 4688
jhon309 0:c52df770855b 4689 #define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
jhon309 0:c52df770855b 4690 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
jhon309 0:c52df770855b 4691 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
jhon309 0:c52df770855b 4692 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
jhon309 0:c52df770855b 4693 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
jhon309 0:c52df770855b 4694
jhon309 0:c52df770855b 4695 /******************* Bit definition for TSC_IER register ********************/
jhon309 0:c52df770855b 4696 #define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
jhon309 0:c52df770855b 4697 #define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
jhon309 0:c52df770855b 4698
jhon309 0:c52df770855b 4699 /******************* Bit definition for TSC_ICR register ********************/
jhon309 0:c52df770855b 4700 #define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
jhon309 0:c52df770855b 4701 #define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
jhon309 0:c52df770855b 4702
jhon309 0:c52df770855b 4703 /******************* Bit definition for TSC_ISR register ********************/
jhon309 0:c52df770855b 4704 #define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
jhon309 0:c52df770855b 4705 #define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
jhon309 0:c52df770855b 4706
jhon309 0:c52df770855b 4707 /******************* Bit definition for TSC_IOHCR register ******************/
jhon309 0:c52df770855b 4708 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4709 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4710 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4711 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4712 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4713 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4714 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4715 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4716 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4717 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4718 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4719 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4720 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4721 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4722 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4723 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4724 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4725 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4726 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4727 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4728 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4729 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4730 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4731 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4732 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4733 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4734 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4735 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4736 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4737 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4738 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4739 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
jhon309 0:c52df770855b 4740
jhon309 0:c52df770855b 4741 /******************* Bit definition for TSC_IOASCR register *****************/
jhon309 0:c52df770855b 4742 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
jhon309 0:c52df770855b 4743 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
jhon309 0:c52df770855b 4744 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
jhon309 0:c52df770855b 4745 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
jhon309 0:c52df770855b 4746 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
jhon309 0:c52df770855b 4747 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
jhon309 0:c52df770855b 4748 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
jhon309 0:c52df770855b 4749 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
jhon309 0:c52df770855b 4750 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
jhon309 0:c52df770855b 4751 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
jhon309 0:c52df770855b 4752 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
jhon309 0:c52df770855b 4753 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
jhon309 0:c52df770855b 4754 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
jhon309 0:c52df770855b 4755 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
jhon309 0:c52df770855b 4756 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
jhon309 0:c52df770855b 4757 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
jhon309 0:c52df770855b 4758 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
jhon309 0:c52df770855b 4759 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
jhon309 0:c52df770855b 4760 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
jhon309 0:c52df770855b 4761 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
jhon309 0:c52df770855b 4762 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
jhon309 0:c52df770855b 4763 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
jhon309 0:c52df770855b 4764 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
jhon309 0:c52df770855b 4765 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
jhon309 0:c52df770855b 4766 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
jhon309 0:c52df770855b 4767 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
jhon309 0:c52df770855b 4768 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
jhon309 0:c52df770855b 4769 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
jhon309 0:c52df770855b 4770 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
jhon309 0:c52df770855b 4771 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
jhon309 0:c52df770855b 4772 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
jhon309 0:c52df770855b 4773 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
jhon309 0:c52df770855b 4774
jhon309 0:c52df770855b 4775 /******************* Bit definition for TSC_IOSCR register ******************/
jhon309 0:c52df770855b 4776 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
jhon309 0:c52df770855b 4777 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
jhon309 0:c52df770855b 4778 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
jhon309 0:c52df770855b 4779 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
jhon309 0:c52df770855b 4780 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
jhon309 0:c52df770855b 4781 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
jhon309 0:c52df770855b 4782 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
jhon309 0:c52df770855b 4783 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
jhon309 0:c52df770855b 4784 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
jhon309 0:c52df770855b 4785 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
jhon309 0:c52df770855b 4786 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
jhon309 0:c52df770855b 4787 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
jhon309 0:c52df770855b 4788 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
jhon309 0:c52df770855b 4789 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
jhon309 0:c52df770855b 4790 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
jhon309 0:c52df770855b 4791 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
jhon309 0:c52df770855b 4792 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
jhon309 0:c52df770855b 4793 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
jhon309 0:c52df770855b 4794 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
jhon309 0:c52df770855b 4795 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
jhon309 0:c52df770855b 4796 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
jhon309 0:c52df770855b 4797 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
jhon309 0:c52df770855b 4798 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
jhon309 0:c52df770855b 4799 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
jhon309 0:c52df770855b 4800 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
jhon309 0:c52df770855b 4801 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
jhon309 0:c52df770855b 4802 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
jhon309 0:c52df770855b 4803 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
jhon309 0:c52df770855b 4804 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
jhon309 0:c52df770855b 4805 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
jhon309 0:c52df770855b 4806 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
jhon309 0:c52df770855b 4807 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
jhon309 0:c52df770855b 4808
jhon309 0:c52df770855b 4809 /******************* Bit definition for TSC_IOCCR register ******************/
jhon309 0:c52df770855b 4810 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
jhon309 0:c52df770855b 4811 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
jhon309 0:c52df770855b 4812 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
jhon309 0:c52df770855b 4813 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
jhon309 0:c52df770855b 4814 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
jhon309 0:c52df770855b 4815 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
jhon309 0:c52df770855b 4816 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
jhon309 0:c52df770855b 4817 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
jhon309 0:c52df770855b 4818 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
jhon309 0:c52df770855b 4819 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
jhon309 0:c52df770855b 4820 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
jhon309 0:c52df770855b 4821 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
jhon309 0:c52df770855b 4822 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
jhon309 0:c52df770855b 4823 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
jhon309 0:c52df770855b 4824 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
jhon309 0:c52df770855b 4825 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
jhon309 0:c52df770855b 4826 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
jhon309 0:c52df770855b 4827 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
jhon309 0:c52df770855b 4828 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
jhon309 0:c52df770855b 4829 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
jhon309 0:c52df770855b 4830 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
jhon309 0:c52df770855b 4831 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
jhon309 0:c52df770855b 4832 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
jhon309 0:c52df770855b 4833 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
jhon309 0:c52df770855b 4834 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
jhon309 0:c52df770855b 4835 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
jhon309 0:c52df770855b 4836 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
jhon309 0:c52df770855b 4837 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
jhon309 0:c52df770855b 4838 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
jhon309 0:c52df770855b 4839 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
jhon309 0:c52df770855b 4840 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
jhon309 0:c52df770855b 4841 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
jhon309 0:c52df770855b 4842
jhon309 0:c52df770855b 4843 /******************* Bit definition for TSC_IOGCSR register *****************/
jhon309 0:c52df770855b 4844 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
jhon309 0:c52df770855b 4845 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
jhon309 0:c52df770855b 4846 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
jhon309 0:c52df770855b 4847 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
jhon309 0:c52df770855b 4848 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
jhon309 0:c52df770855b 4849 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
jhon309 0:c52df770855b 4850 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
jhon309 0:c52df770855b 4851 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
jhon309 0:c52df770855b 4852 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
jhon309 0:c52df770855b 4853 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
jhon309 0:c52df770855b 4854 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
jhon309 0:c52df770855b 4855 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
jhon309 0:c52df770855b 4856 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
jhon309 0:c52df770855b 4857 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
jhon309 0:c52df770855b 4858 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
jhon309 0:c52df770855b 4859 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
jhon309 0:c52df770855b 4860
jhon309 0:c52df770855b 4861 /******************* Bit definition for TSC_IOGXCR register *****************/
jhon309 0:c52df770855b 4862 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
jhon309 0:c52df770855b 4863
jhon309 0:c52df770855b 4864 /******************************************************************************/
jhon309 0:c52df770855b 4865 /* */
jhon309 0:c52df770855b 4866 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
jhon309 0:c52df770855b 4867 /* */
jhon309 0:c52df770855b 4868 /******************************************************************************/
jhon309 0:c52df770855b 4869 /****************** Bit definition for USART_CR1 register *******************/
jhon309 0:c52df770855b 4870 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
jhon309 0:c52df770855b 4871 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
jhon309 0:c52df770855b 4872 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
jhon309 0:c52df770855b 4873 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
jhon309 0:c52df770855b 4874 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
jhon309 0:c52df770855b 4875 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
jhon309 0:c52df770855b 4876 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
jhon309 0:c52df770855b 4877 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
jhon309 0:c52df770855b 4878 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
jhon309 0:c52df770855b 4879 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
jhon309 0:c52df770855b 4880 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
jhon309 0:c52df770855b 4881 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
jhon309 0:c52df770855b 4882 #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
jhon309 0:c52df770855b 4883 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
jhon309 0:c52df770855b 4884 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
jhon309 0:c52df770855b 4885 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
jhon309 0:c52df770855b 4886 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
jhon309 0:c52df770855b 4887 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
jhon309 0:c52df770855b 4888 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
jhon309 0:c52df770855b 4889 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
jhon309 0:c52df770855b 4890 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
jhon309 0:c52df770855b 4891 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
jhon309 0:c52df770855b 4892 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
jhon309 0:c52df770855b 4893 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
jhon309 0:c52df770855b 4894 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
jhon309 0:c52df770855b 4895 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
jhon309 0:c52df770855b 4896 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
jhon309 0:c52df770855b 4897 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
jhon309 0:c52df770855b 4898 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
jhon309 0:c52df770855b 4899 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
jhon309 0:c52df770855b 4900 #define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
jhon309 0:c52df770855b 4901 #define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
jhon309 0:c52df770855b 4902
jhon309 0:c52df770855b 4903 /****************** Bit definition for USART_CR2 register *******************/
jhon309 0:c52df770855b 4904 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
jhon309 0:c52df770855b 4905 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
jhon309 0:c52df770855b 4906 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
jhon309 0:c52df770855b 4907 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
jhon309 0:c52df770855b 4908 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
jhon309 0:c52df770855b 4909 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
jhon309 0:c52df770855b 4910 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
jhon309 0:c52df770855b 4911 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
jhon309 0:c52df770855b 4912 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
jhon309 0:c52df770855b 4913 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
jhon309 0:c52df770855b 4914 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
jhon309 0:c52df770855b 4915 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
jhon309 0:c52df770855b 4916 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
jhon309 0:c52df770855b 4917 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
jhon309 0:c52df770855b 4918 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
jhon309 0:c52df770855b 4919 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
jhon309 0:c52df770855b 4920 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
jhon309 0:c52df770855b 4921 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
jhon309 0:c52df770855b 4922 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
jhon309 0:c52df770855b 4923 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
jhon309 0:c52df770855b 4924 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
jhon309 0:c52df770855b 4925 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
jhon309 0:c52df770855b 4926
jhon309 0:c52df770855b 4927 /****************** Bit definition for USART_CR3 register *******************/
jhon309 0:c52df770855b 4928 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
jhon309 0:c52df770855b 4929 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
jhon309 0:c52df770855b 4930 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
jhon309 0:c52df770855b 4931 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
jhon309 0:c52df770855b 4932 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
jhon309 0:c52df770855b 4933 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
jhon309 0:c52df770855b 4934 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
jhon309 0:c52df770855b 4935 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
jhon309 0:c52df770855b 4936 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
jhon309 0:c52df770855b 4937 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
jhon309 0:c52df770855b 4938 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
jhon309 0:c52df770855b 4939 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
jhon309 0:c52df770855b 4940 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
jhon309 0:c52df770855b 4941 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
jhon309 0:c52df770855b 4942 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
jhon309 0:c52df770855b 4943 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
jhon309 0:c52df770855b 4944 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
jhon309 0:c52df770855b 4945 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
jhon309 0:c52df770855b 4946 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
jhon309 0:c52df770855b 4947 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
jhon309 0:c52df770855b 4948 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
jhon309 0:c52df770855b 4949 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
jhon309 0:c52df770855b 4950 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
jhon309 0:c52df770855b 4951 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
jhon309 0:c52df770855b 4952
jhon309 0:c52df770855b 4953 /****************** Bit definition for USART_BRR register *******************/
jhon309 0:c52df770855b 4954 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
jhon309 0:c52df770855b 4955 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
jhon309 0:c52df770855b 4956
jhon309 0:c52df770855b 4957 /****************** Bit definition for USART_GTPR register ******************/
jhon309 0:c52df770855b 4958 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
jhon309 0:c52df770855b 4959 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
jhon309 0:c52df770855b 4960
jhon309 0:c52df770855b 4961
jhon309 0:c52df770855b 4962 /******************* Bit definition for USART_RTOR register *****************/
jhon309 0:c52df770855b 4963 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
jhon309 0:c52df770855b 4964 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
jhon309 0:c52df770855b 4965
jhon309 0:c52df770855b 4966 /******************* Bit definition for USART_RQR register ******************/
jhon309 0:c52df770855b 4967 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
jhon309 0:c52df770855b 4968 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
jhon309 0:c52df770855b 4969 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
jhon309 0:c52df770855b 4970 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
jhon309 0:c52df770855b 4971 #define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
jhon309 0:c52df770855b 4972
jhon309 0:c52df770855b 4973 /******************* Bit definition for USART_ISR register ******************/
jhon309 0:c52df770855b 4974 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
jhon309 0:c52df770855b 4975 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
jhon309 0:c52df770855b 4976 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
jhon309 0:c52df770855b 4977 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
jhon309 0:c52df770855b 4978 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
jhon309 0:c52df770855b 4979 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
jhon309 0:c52df770855b 4980 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
jhon309 0:c52df770855b 4981 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
jhon309 0:c52df770855b 4982 #define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
jhon309 0:c52df770855b 4983 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
jhon309 0:c52df770855b 4984 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
jhon309 0:c52df770855b 4985 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
jhon309 0:c52df770855b 4986 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
jhon309 0:c52df770855b 4987 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
jhon309 0:c52df770855b 4988 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
jhon309 0:c52df770855b 4989 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
jhon309 0:c52df770855b 4990 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
jhon309 0:c52df770855b 4991 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
jhon309 0:c52df770855b 4992 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
jhon309 0:c52df770855b 4993 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
jhon309 0:c52df770855b 4994 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
jhon309 0:c52df770855b 4995 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
jhon309 0:c52df770855b 4996
jhon309 0:c52df770855b 4997 /******************* Bit definition for USART_ICR register ******************/
jhon309 0:c52df770855b 4998 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
jhon309 0:c52df770855b 4999 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
jhon309 0:c52df770855b 5000 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
jhon309 0:c52df770855b 5001 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
jhon309 0:c52df770855b 5002 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
jhon309 0:c52df770855b 5003 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
jhon309 0:c52df770855b 5004 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
jhon309 0:c52df770855b 5005 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
jhon309 0:c52df770855b 5006 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
jhon309 0:c52df770855b 5007 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
jhon309 0:c52df770855b 5008 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
jhon309 0:c52df770855b 5009 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
jhon309 0:c52df770855b 5010
jhon309 0:c52df770855b 5011 /******************* Bit definition for USART_RDR register ******************/
jhon309 0:c52df770855b 5012 #define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
jhon309 0:c52df770855b 5013
jhon309 0:c52df770855b 5014 /******************* Bit definition for USART_TDR register ******************/
jhon309 0:c52df770855b 5015 #define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
jhon309 0:c52df770855b 5016
jhon309 0:c52df770855b 5017 /******************************************************************************/
jhon309 0:c52df770855b 5018 /* */
jhon309 0:c52df770855b 5019 /* USB Device General registers */
jhon309 0:c52df770855b 5020 /* */
jhon309 0:c52df770855b 5021 /******************************************************************************/
jhon309 0:c52df770855b 5022 #define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
jhon309 0:c52df770855b 5023 #define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
jhon309 0:c52df770855b 5024 #define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
jhon309 0:c52df770855b 5025 #define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
jhon309 0:c52df770855b 5026 #define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
jhon309 0:c52df770855b 5027 #define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
jhon309 0:c52df770855b 5028 #define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
jhon309 0:c52df770855b 5029
jhon309 0:c52df770855b 5030 /**************************** ISTR interrupt events *************************/
jhon309 0:c52df770855b 5031 #define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
jhon309 0:c52df770855b 5032 #define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
jhon309 0:c52df770855b 5033 #define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
jhon309 0:c52df770855b 5034 #define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
jhon309 0:c52df770855b 5035 #define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
jhon309 0:c52df770855b 5036 #define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
jhon309 0:c52df770855b 5037 #define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
jhon309 0:c52df770855b 5038 #define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
jhon309 0:c52df770855b 5039 #define USB_ISTR_L1REQ ((uint16_t)0x0080) /*!< LPM L1 state request */
jhon309 0:c52df770855b 5040 #define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
jhon309 0:c52df770855b 5041 #define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
jhon309 0:c52df770855b 5042
jhon309 0:c52df770855b 5043 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
jhon309 0:c52df770855b 5044 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
jhon309 0:c52df770855b 5045 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
jhon309 0:c52df770855b 5046 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
jhon309 0:c52df770855b 5047 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
jhon309 0:c52df770855b 5048 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
jhon309 0:c52df770855b 5049 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
jhon309 0:c52df770855b 5050 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
jhon309 0:c52df770855b 5051 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
jhon309 0:c52df770855b 5052
jhon309 0:c52df770855b 5053 /************************* CNTR control register bits definitions ***********/
jhon309 0:c52df770855b 5054 #define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
jhon309 0:c52df770855b 5055 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
jhon309 0:c52df770855b 5056 #define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
jhon309 0:c52df770855b 5057 #define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
jhon309 0:c52df770855b 5058 #define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
jhon309 0:c52df770855b 5059 #define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
jhon309 0:c52df770855b 5060 #define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
jhon309 0:c52df770855b 5061 #define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
jhon309 0:c52df770855b 5062 #define USB_CNTR_L1REQM ((uint16_t)0x0080) /*!< LPM L1 state request interrupt mask */
jhon309 0:c52df770855b 5063 #define USB_CNTR_L1RESUME ((uint16_t)0x0020) /*!< LPM L1 Resume request */
jhon309 0:c52df770855b 5064 #define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
jhon309 0:c52df770855b 5065 #define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
jhon309 0:c52df770855b 5066 #define USB_CNTR_LPMODE ((uint16_t)0x0004) /*!< Low-power MODE */
jhon309 0:c52df770855b 5067 #define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
jhon309 0:c52df770855b 5068 #define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
jhon309 0:c52df770855b 5069
jhon309 0:c52df770855b 5070 /************************* BCDR control register bits definitions ***********/
jhon309 0:c52df770855b 5071 #define USB_BCDR_DPPU ((uint16_t)0x8000) /*!< DP Pull-up Enable */
jhon309 0:c52df770855b 5072 #define USB_BCDR_PS2DET ((uint16_t)0x0080) /*!< PS2 port or proprietary charger detected */
jhon309 0:c52df770855b 5073 #define USB_BCDR_SDET ((uint16_t)0x0040) /*!< Secondary detection (SD) status */
jhon309 0:c52df770855b 5074 #define USB_BCDR_PDET ((uint16_t)0x0020) /*!< Primary detection (PD) status */
jhon309 0:c52df770855b 5075 #define USB_BCDR_DCDET ((uint16_t)0x0010) /*!< Data contact detection (DCD) status */
jhon309 0:c52df770855b 5076 #define USB_BCDR_SDEN ((uint16_t)0x0008) /*!< Secondary detection (SD) mode enable */
jhon309 0:c52df770855b 5077 #define USB_BCDR_PDEN ((uint16_t)0x0004) /*!< Primary detection (PD) mode enable */
jhon309 0:c52df770855b 5078 #define USB_BCDR_DCDEN ((uint16_t)0x0002) /*!< Data contact detection (DCD) mode enable */
jhon309 0:c52df770855b 5079 #define USB_BCDR_BCDEN ((uint16_t)0x0001) /*!< Battery charging detector (BCD) enable */
jhon309 0:c52df770855b 5080
jhon309 0:c52df770855b 5081 /*************************** LPM register bits definitions ******************/
jhon309 0:c52df770855b 5082 #define USB_LPMCSR_BESL ((uint16_t)0x00F0) /*!< BESL value received with last ACKed LPM Token */
jhon309 0:c52df770855b 5083 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /*!< bRemoteWake value received with last ACKed LPM Token */
jhon309 0:c52df770855b 5084 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /*!< LPM Token acknowledge enable*/
jhon309 0:c52df770855b 5085 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /*!< LPM support enable */
jhon309 0:c52df770855b 5086
jhon309 0:c52df770855b 5087 /******************** FNR Frame Number Register bit definitions ************/
jhon309 0:c52df770855b 5088 #define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
jhon309 0:c52df770855b 5089 #define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
jhon309 0:c52df770855b 5090 #define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
jhon309 0:c52df770855b 5091 #define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
jhon309 0:c52df770855b 5092 #define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
jhon309 0:c52df770855b 5093
jhon309 0:c52df770855b 5094 /******************** DADDR Device ADDRess bit definitions ****************/
jhon309 0:c52df770855b 5095 #define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
jhon309 0:c52df770855b 5096 #define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
jhon309 0:c52df770855b 5097
jhon309 0:c52df770855b 5098 /****************************** Endpoint register *************************/
jhon309 0:c52df770855b 5099 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
jhon309 0:c52df770855b 5100 #define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
jhon309 0:c52df770855b 5101 #define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
jhon309 0:c52df770855b 5102 #define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
jhon309 0:c52df770855b 5103 #define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
jhon309 0:c52df770855b 5104 #define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
jhon309 0:c52df770855b 5105 #define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
jhon309 0:c52df770855b 5106 #define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
jhon309 0:c52df770855b 5107 /* bit positions */
jhon309 0:c52df770855b 5108 #define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
jhon309 0:c52df770855b 5109 #define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
jhon309 0:c52df770855b 5110 #define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
jhon309 0:c52df770855b 5111 #define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
jhon309 0:c52df770855b 5112 #define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
jhon309 0:c52df770855b 5113 #define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
jhon309 0:c52df770855b 5114 #define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
jhon309 0:c52df770855b 5115 #define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
jhon309 0:c52df770855b 5116 #define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
jhon309 0:c52df770855b 5117 #define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
jhon309 0:c52df770855b 5118
jhon309 0:c52df770855b 5119 /* EndPoint REGister MASK (no toggle fields) */
jhon309 0:c52df770855b 5120 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
jhon309 0:c52df770855b 5121 /*!< EP_TYPE[1:0] EndPoint TYPE */
jhon309 0:c52df770855b 5122 #define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
jhon309 0:c52df770855b 5123 #define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
jhon309 0:c52df770855b 5124 #define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
jhon309 0:c52df770855b 5125 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
jhon309 0:c52df770855b 5126 #define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
jhon309 0:c52df770855b 5127 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
jhon309 0:c52df770855b 5128
jhon309 0:c52df770855b 5129 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
jhon309 0:c52df770855b 5130 /*!< STAT_TX[1:0] STATus for TX transfer */
jhon309 0:c52df770855b 5131 #define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
jhon309 0:c52df770855b 5132 #define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
jhon309 0:c52df770855b 5133 #define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
jhon309 0:c52df770855b 5134 #define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
jhon309 0:c52df770855b 5135 #define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
jhon309 0:c52df770855b 5136 #define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
jhon309 0:c52df770855b 5137 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
jhon309 0:c52df770855b 5138 /*!< STAT_RX[1:0] STATus for RX transfer */
jhon309 0:c52df770855b 5139 #define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
jhon309 0:c52df770855b 5140 #define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
jhon309 0:c52df770855b 5141 #define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
jhon309 0:c52df770855b 5142 #define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
jhon309 0:c52df770855b 5143 #define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
jhon309 0:c52df770855b 5144 #define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
jhon309 0:c52df770855b 5145 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
jhon309 0:c52df770855b 5146
jhon309 0:c52df770855b 5147 /******************************************************************************/
jhon309 0:c52df770855b 5148 /* */
jhon309 0:c52df770855b 5149 /* Window WATCHDOG (WWDG) */
jhon309 0:c52df770855b 5150 /* */
jhon309 0:c52df770855b 5151 /******************************************************************************/
jhon309 0:c52df770855b 5152 /******************* Bit definition for WWDG_CR register ********************/
jhon309 0:c52df770855b 5153 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
jhon309 0:c52df770855b 5154 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
jhon309 0:c52df770855b 5155 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
jhon309 0:c52df770855b 5156 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
jhon309 0:c52df770855b 5157 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
jhon309 0:c52df770855b 5158 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
jhon309 0:c52df770855b 5159 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
jhon309 0:c52df770855b 5160 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
jhon309 0:c52df770855b 5161
jhon309 0:c52df770855b 5162 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
jhon309 0:c52df770855b 5163
jhon309 0:c52df770855b 5164 /******************* Bit definition for WWDG_CFR register *******************/
jhon309 0:c52df770855b 5165 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
jhon309 0:c52df770855b 5166 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
jhon309 0:c52df770855b 5167 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
jhon309 0:c52df770855b 5168 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
jhon309 0:c52df770855b 5169 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
jhon309 0:c52df770855b 5170 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
jhon309 0:c52df770855b 5171 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
jhon309 0:c52df770855b 5172 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
jhon309 0:c52df770855b 5173
jhon309 0:c52df770855b 5174 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
jhon309 0:c52df770855b 5175 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
jhon309 0:c52df770855b 5176 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
jhon309 0:c52df770855b 5177
jhon309 0:c52df770855b 5178 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
jhon309 0:c52df770855b 5179
jhon309 0:c52df770855b 5180 /******************* Bit definition for WWDG_SR register ********************/
jhon309 0:c52df770855b 5181 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
jhon309 0:c52df770855b 5182
jhon309 0:c52df770855b 5183 /**
jhon309 0:c52df770855b 5184 * @}
jhon309 0:c52df770855b 5185 */
jhon309 0:c52df770855b 5186
jhon309 0:c52df770855b 5187 /**
jhon309 0:c52df770855b 5188 * @}
jhon309 0:c52df770855b 5189 */
jhon309 0:c52df770855b 5190
jhon309 0:c52df770855b 5191
jhon309 0:c52df770855b 5192 /** @addtogroup Exported_macro
jhon309 0:c52df770855b 5193 * @{
jhon309 0:c52df770855b 5194 */
jhon309 0:c52df770855b 5195
jhon309 0:c52df770855b 5196 /****************************** ADC Instances *********************************/
jhon309 0:c52df770855b 5197 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
jhon309 0:c52df770855b 5198
jhon309 0:c52df770855b 5199 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
jhon309 0:c52df770855b 5200
jhon309 0:c52df770855b 5201 /******************************* CAN Instances ********************************/
jhon309 0:c52df770855b 5202 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
jhon309 0:c52df770855b 5203
jhon309 0:c52df770855b 5204 /****************************** COMP Instances *********************************/
jhon309 0:c52df770855b 5205 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
jhon309 0:c52df770855b 5206 ((INSTANCE) == COMP2))
jhon309 0:c52df770855b 5207
jhon309 0:c52df770855b 5208 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
jhon309 0:c52df770855b 5209
jhon309 0:c52df770855b 5210 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
jhon309 0:c52df770855b 5211
jhon309 0:c52df770855b 5212 /****************************** CEC Instances *********************************/
jhon309 0:c52df770855b 5213 #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
jhon309 0:c52df770855b 5214
jhon309 0:c52df770855b 5215 /****************************** CRC Instances *********************************/
jhon309 0:c52df770855b 5216 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
jhon309 0:c52df770855b 5217
jhon309 0:c52df770855b 5218 /******************************* DAC Instances ********************************/
jhon309 0:c52df770855b 5219 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
jhon309 0:c52df770855b 5220
jhon309 0:c52df770855b 5221 /******************************* DMA Instances ******************************/
jhon309 0:c52df770855b 5222 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
jhon309 0:c52df770855b 5223 ((INSTANCE) == DMA1_Channel2) || \
jhon309 0:c52df770855b 5224 ((INSTANCE) == DMA1_Channel3) || \
jhon309 0:c52df770855b 5225 ((INSTANCE) == DMA1_Channel4) || \
jhon309 0:c52df770855b 5226 ((INSTANCE) == DMA1_Channel5) || \
jhon309 0:c52df770855b 5227 ((INSTANCE) == DMA1_Channel6) || \
jhon309 0:c52df770855b 5228 ((INSTANCE) == DMA1_Channel7))
jhon309 0:c52df770855b 5229
jhon309 0:c52df770855b 5230 /****************************** GPIO Instances ********************************/
jhon309 0:c52df770855b 5231 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
jhon309 0:c52df770855b 5232 ((INSTANCE) == GPIOB) || \
jhon309 0:c52df770855b 5233 ((INSTANCE) == GPIOC) || \
jhon309 0:c52df770855b 5234 ((INSTANCE) == GPIOD) || \
jhon309 0:c52df770855b 5235 ((INSTANCE) == GPIOE) || \
jhon309 0:c52df770855b 5236 ((INSTANCE) == GPIOF))
jhon309 0:c52df770855b 5237
jhon309 0:c52df770855b 5238 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
jhon309 0:c52df770855b 5239 ((INSTANCE) == GPIOB) || \
jhon309 0:c52df770855b 5240 ((INSTANCE) == GPIOC) || \
jhon309 0:c52df770855b 5241 ((INSTANCE) == GPIOD) || \
jhon309 0:c52df770855b 5242 ((INSTANCE) == GPIOE))
jhon309 0:c52df770855b 5243
jhon309 0:c52df770855b 5244 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
jhon309 0:c52df770855b 5245 ((INSTANCE) == GPIOB))
jhon309 0:c52df770855b 5246
jhon309 0:c52df770855b 5247 /****************************** I2C Instances *********************************/
jhon309 0:c52df770855b 5248 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
jhon309 0:c52df770855b 5249 ((INSTANCE) == I2C2))
jhon309 0:c52df770855b 5250
jhon309 0:c52df770855b 5251 /****************************** I2S Instances *********************************/
jhon309 0:c52df770855b 5252 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
jhon309 0:c52df770855b 5253 ((INSTANCE) == SPI2))
jhon309 0:c52df770855b 5254
jhon309 0:c52df770855b 5255 /****************************** IWDG Instances ********************************/
jhon309 0:c52df770855b 5256 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
jhon309 0:c52df770855b 5257
jhon309 0:c52df770855b 5258 /****************************** RTC Instances *********************************/
jhon309 0:c52df770855b 5259 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
jhon309 0:c52df770855b 5260
jhon309 0:c52df770855b 5261 /****************************** SMBUS Instances *********************************/
jhon309 0:c52df770855b 5262 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
jhon309 0:c52df770855b 5263
jhon309 0:c52df770855b 5264 /****************************** SPI Instances *********************************/
jhon309 0:c52df770855b 5265 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
jhon309 0:c52df770855b 5266 ((INSTANCE) == SPI2))
jhon309 0:c52df770855b 5267
jhon309 0:c52df770855b 5268 /****************************** TIM Instances *********************************/
jhon309 0:c52df770855b 5269 #define IS_TIM_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5270 (((INSTANCE) == TIM1) || \
jhon309 0:c52df770855b 5271 ((INSTANCE) == TIM2) || \
jhon309 0:c52df770855b 5272 ((INSTANCE) == TIM3) || \
jhon309 0:c52df770855b 5273 ((INSTANCE) == TIM6) || \
jhon309 0:c52df770855b 5274 ((INSTANCE) == TIM7) || \
jhon309 0:c52df770855b 5275 ((INSTANCE) == TIM14) || \
jhon309 0:c52df770855b 5276 ((INSTANCE) == TIM15) || \
jhon309 0:c52df770855b 5277 ((INSTANCE) == TIM16) || \
jhon309 0:c52df770855b 5278 ((INSTANCE) == TIM17))
jhon309 0:c52df770855b 5279
jhon309 0:c52df770855b 5280 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5281 (((INSTANCE) == TIM1) || \
jhon309 0:c52df770855b 5282 ((INSTANCE) == TIM2) || \
jhon309 0:c52df770855b 5283 ((INSTANCE) == TIM3) || \
jhon309 0:c52df770855b 5284 ((INSTANCE) == TIM14) || \
jhon309 0:c52df770855b 5285 ((INSTANCE) == TIM15) || \
jhon309 0:c52df770855b 5286 ((INSTANCE) == TIM16) || \
jhon309 0:c52df770855b 5287 ((INSTANCE) == TIM17))
jhon309 0:c52df770855b 5288
jhon309 0:c52df770855b 5289 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5290 (((INSTANCE) == TIM1) || \
jhon309 0:c52df770855b 5291 ((INSTANCE) == TIM2) || \
jhon309 0:c52df770855b 5292 ((INSTANCE) == TIM3) || \
jhon309 0:c52df770855b 5293 ((INSTANCE) == TIM15))
jhon309 0:c52df770855b 5294
jhon309 0:c52df770855b 5295 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5296 (((INSTANCE) == TIM1) || \
jhon309 0:c52df770855b 5297 ((INSTANCE) == TIM2) || \
jhon309 0:c52df770855b 5298 ((INSTANCE) == TIM3))
jhon309 0:c52df770855b 5299
jhon309 0:c52df770855b 5300 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5301 (((INSTANCE) == TIM1) || \
jhon309 0:c52df770855b 5302 ((INSTANCE) == TIM2) || \
jhon309 0:c52df770855b 5303 ((INSTANCE) == TIM3))
jhon309 0:c52df770855b 5304
jhon309 0:c52df770855b 5305 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5306 (((INSTANCE) == TIM1) || \
jhon309 0:c52df770855b 5307 ((INSTANCE) == TIM2) || \
jhon309 0:c52df770855b 5308 ((INSTANCE) == TIM3))
jhon309 0:c52df770855b 5309
jhon309 0:c52df770855b 5310 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5311 (((INSTANCE) == TIM1) || \
jhon309 0:c52df770855b 5312 ((INSTANCE) == TIM2) || \
jhon309 0:c52df770855b 5313 ((INSTANCE) == TIM3))
jhon309 0:c52df770855b 5314
jhon309 0:c52df770855b 5315 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5316 (((INSTANCE) == TIM1) || \
jhon309 0:c52df770855b 5317 ((INSTANCE) == TIM2) || \
jhon309 0:c52df770855b 5318 ((INSTANCE) == TIM3) || \
jhon309 0:c52df770855b 5319 ((INSTANCE) == TIM15))
jhon309 0:c52df770855b 5320
jhon309 0:c52df770855b 5321 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5322 (((INSTANCE) == TIM1) || \
jhon309 0:c52df770855b 5323 ((INSTANCE) == TIM2) || \
jhon309 0:c52df770855b 5324 ((INSTANCE) == TIM3) || \
jhon309 0:c52df770855b 5325 ((INSTANCE) == TIM15))
jhon309 0:c52df770855b 5326
jhon309 0:c52df770855b 5327 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5328 (((INSTANCE) == TIM1) || \
jhon309 0:c52df770855b 5329 ((INSTANCE) == TIM2) || \
jhon309 0:c52df770855b 5330 ((INSTANCE) == TIM3))
jhon309 0:c52df770855b 5331
jhon309 0:c52df770855b 5332 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5333 (((INSTANCE) == TIM1) || \
jhon309 0:c52df770855b 5334 ((INSTANCE) == TIM2) || \
jhon309 0:c52df770855b 5335 ((INSTANCE) == TIM3))
jhon309 0:c52df770855b 5336
jhon309 0:c52df770855b 5337 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5338 (((INSTANCE) == TIM1))
jhon309 0:c52df770855b 5339
jhon309 0:c52df770855b 5340 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5341 (((INSTANCE) == TIM1) || \
jhon309 0:c52df770855b 5342 ((INSTANCE) == TIM2) || \
jhon309 0:c52df770855b 5343 ((INSTANCE) == TIM3))
jhon309 0:c52df770855b 5344
jhon309 0:c52df770855b 5345 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5346 (((INSTANCE) == TIM1) || \
jhon309 0:c52df770855b 5347 ((INSTANCE) == TIM2) || \
jhon309 0:c52df770855b 5348 ((INSTANCE) == TIM3) || \
jhon309 0:c52df770855b 5349 ((INSTANCE) == TIM6) || \
jhon309 0:c52df770855b 5350 ((INSTANCE) == TIM7) || \
jhon309 0:c52df770855b 5351 ((INSTANCE) == TIM15))
jhon309 0:c52df770855b 5352
jhon309 0:c52df770855b 5353 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5354 (((INSTANCE) == TIM1) || \
jhon309 0:c52df770855b 5355 ((INSTANCE) == TIM2) || \
jhon309 0:c52df770855b 5356 ((INSTANCE) == TIM3) || \
jhon309 0:c52df770855b 5357 ((INSTANCE) == TIM15))
jhon309 0:c52df770855b 5358
jhon309 0:c52df770855b 5359 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5360 ((INSTANCE) == TIM2)
jhon309 0:c52df770855b 5361
jhon309 0:c52df770855b 5362 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5363 (((INSTANCE) == TIM1) || \
jhon309 0:c52df770855b 5364 ((INSTANCE) == TIM2) || \
jhon309 0:c52df770855b 5365 ((INSTANCE) == TIM3) || \
jhon309 0:c52df770855b 5366 ((INSTANCE) == TIM15) || \
jhon309 0:c52df770855b 5367 ((INSTANCE) == TIM16) || \
jhon309 0:c52df770855b 5368 ((INSTANCE) == TIM17))
jhon309 0:c52df770855b 5369
jhon309 0:c52df770855b 5370 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5371 (((INSTANCE) == TIM1) || \
jhon309 0:c52df770855b 5372 ((INSTANCE) == TIM15) || \
jhon309 0:c52df770855b 5373 ((INSTANCE) == TIM16) || \
jhon309 0:c52df770855b 5374 ((INSTANCE) == TIM17))
jhon309 0:c52df770855b 5375
jhon309 0:c52df770855b 5376 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
jhon309 0:c52df770855b 5377 ((((INSTANCE) == TIM1) && \
jhon309 0:c52df770855b 5378 (((CHANNEL) == TIM_CHANNEL_1) || \
jhon309 0:c52df770855b 5379 ((CHANNEL) == TIM_CHANNEL_2) || \
jhon309 0:c52df770855b 5380 ((CHANNEL) == TIM_CHANNEL_3) || \
jhon309 0:c52df770855b 5381 ((CHANNEL) == TIM_CHANNEL_4))) \
jhon309 0:c52df770855b 5382 || \
jhon309 0:c52df770855b 5383 (((INSTANCE) == TIM2) && \
jhon309 0:c52df770855b 5384 (((CHANNEL) == TIM_CHANNEL_1) || \
jhon309 0:c52df770855b 5385 ((CHANNEL) == TIM_CHANNEL_2) || \
jhon309 0:c52df770855b 5386 ((CHANNEL) == TIM_CHANNEL_3) || \
jhon309 0:c52df770855b 5387 ((CHANNEL) == TIM_CHANNEL_4))) \
jhon309 0:c52df770855b 5388 || \
jhon309 0:c52df770855b 5389 (((INSTANCE) == TIM3) && \
jhon309 0:c52df770855b 5390 (((CHANNEL) == TIM_CHANNEL_1) || \
jhon309 0:c52df770855b 5391 ((CHANNEL) == TIM_CHANNEL_2) || \
jhon309 0:c52df770855b 5392 ((CHANNEL) == TIM_CHANNEL_3) || \
jhon309 0:c52df770855b 5393 ((CHANNEL) == TIM_CHANNEL_4))) \
jhon309 0:c52df770855b 5394 || \
jhon309 0:c52df770855b 5395 (((INSTANCE) == TIM14) && \
jhon309 0:c52df770855b 5396 (((CHANNEL) == TIM_CHANNEL_1))) \
jhon309 0:c52df770855b 5397 || \
jhon309 0:c52df770855b 5398 (((INSTANCE) == TIM15) && \
jhon309 0:c52df770855b 5399 (((CHANNEL) == TIM_CHANNEL_1) || \
jhon309 0:c52df770855b 5400 ((CHANNEL) == TIM_CHANNEL_2))) \
jhon309 0:c52df770855b 5401 || \
jhon309 0:c52df770855b 5402 (((INSTANCE) == TIM16) && \
jhon309 0:c52df770855b 5403 (((CHANNEL) == TIM_CHANNEL_1))) \
jhon309 0:c52df770855b 5404 || \
jhon309 0:c52df770855b 5405 (((INSTANCE) == TIM17) && \
jhon309 0:c52df770855b 5406 (((CHANNEL) == TIM_CHANNEL_1))))
jhon309 0:c52df770855b 5407
jhon309 0:c52df770855b 5408 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
jhon309 0:c52df770855b 5409 ((((INSTANCE) == TIM1) && \
jhon309 0:c52df770855b 5410 (((CHANNEL) == TIM_CHANNEL_1) || \
jhon309 0:c52df770855b 5411 ((CHANNEL) == TIM_CHANNEL_2) || \
jhon309 0:c52df770855b 5412 ((CHANNEL) == TIM_CHANNEL_3))) \
jhon309 0:c52df770855b 5413 || \
jhon309 0:c52df770855b 5414 (((INSTANCE) == TIM15) && \
jhon309 0:c52df770855b 5415 ((CHANNEL) == TIM_CHANNEL_1)) \
jhon309 0:c52df770855b 5416 || \
jhon309 0:c52df770855b 5417 (((INSTANCE) == TIM16) && \
jhon309 0:c52df770855b 5418 ((CHANNEL) == TIM_CHANNEL_1)) \
jhon309 0:c52df770855b 5419 || \
jhon309 0:c52df770855b 5420 (((INSTANCE) == TIM17) && \
jhon309 0:c52df770855b 5421 ((CHANNEL) == TIM_CHANNEL_1)))
jhon309 0:c52df770855b 5422
jhon309 0:c52df770855b 5423 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5424 (((INSTANCE) == TIM1) || \
jhon309 0:c52df770855b 5425 ((INSTANCE) == TIM2) || \
jhon309 0:c52df770855b 5426 ((INSTANCE) == TIM3))
jhon309 0:c52df770855b 5427
jhon309 0:c52df770855b 5428 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5429 (((INSTANCE) == TIM1) || \
jhon309 0:c52df770855b 5430 ((INSTANCE) == TIM15) || \
jhon309 0:c52df770855b 5431 ((INSTANCE) == TIM16) || \
jhon309 0:c52df770855b 5432 ((INSTANCE) == TIM17))
jhon309 0:c52df770855b 5433
jhon309 0:c52df770855b 5434 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5435 (((INSTANCE) == TIM1) || \
jhon309 0:c52df770855b 5436 ((INSTANCE) == TIM2) || \
jhon309 0:c52df770855b 5437 ((INSTANCE) == TIM3) || \
jhon309 0:c52df770855b 5438 ((INSTANCE) == TIM14) || \
jhon309 0:c52df770855b 5439 ((INSTANCE) == TIM15) || \
jhon309 0:c52df770855b 5440 ((INSTANCE) == TIM16) || \
jhon309 0:c52df770855b 5441 ((INSTANCE) == TIM17))
jhon309 0:c52df770855b 5442
jhon309 0:c52df770855b 5443 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5444 (((INSTANCE) == TIM1) || \
jhon309 0:c52df770855b 5445 ((INSTANCE) == TIM2) || \
jhon309 0:c52df770855b 5446 ((INSTANCE) == TIM3) || \
jhon309 0:c52df770855b 5447 ((INSTANCE) == TIM6) || \
jhon309 0:c52df770855b 5448 ((INSTANCE) == TIM7) || \
jhon309 0:c52df770855b 5449 ((INSTANCE) == TIM15) || \
jhon309 0:c52df770855b 5450 ((INSTANCE) == TIM16) || \
jhon309 0:c52df770855b 5451 ((INSTANCE) == TIM17))
jhon309 0:c52df770855b 5452
jhon309 0:c52df770855b 5453 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5454 (((INSTANCE) == TIM1) || \
jhon309 0:c52df770855b 5455 ((INSTANCE) == TIM2) || \
jhon309 0:c52df770855b 5456 ((INSTANCE) == TIM3) || \
jhon309 0:c52df770855b 5457 ((INSTANCE) == TIM15) || \
jhon309 0:c52df770855b 5458 ((INSTANCE) == TIM16) || \
jhon309 0:c52df770855b 5459 ((INSTANCE) == TIM17))
jhon309 0:c52df770855b 5460
jhon309 0:c52df770855b 5461 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5462 (((INSTANCE) == TIM1) || \
jhon309 0:c52df770855b 5463 ((INSTANCE) == TIM15) || \
jhon309 0:c52df770855b 5464 ((INSTANCE) == TIM16) || \
jhon309 0:c52df770855b 5465 ((INSTANCE) == TIM17))
jhon309 0:c52df770855b 5466
jhon309 0:c52df770855b 5467 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
jhon309 0:c52df770855b 5468 ((INSTANCE) == TIM14)
jhon309 0:c52df770855b 5469
jhon309 0:c52df770855b 5470 /****************************** TSC Instances *********************************/
jhon309 0:c52df770855b 5471 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
jhon309 0:c52df770855b 5472
jhon309 0:c52df770855b 5473 /*********************** UART Instances : IRDA mode ***************************/
jhon309 0:c52df770855b 5474 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
jhon309 0:c52df770855b 5475 ((INSTANCE) == USART2))
jhon309 0:c52df770855b 5476
jhon309 0:c52df770855b 5477 /********************* UART Instances : Smard card mode ***********************/
jhon309 0:c52df770855b 5478 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
jhon309 0:c52df770855b 5479 ((INSTANCE) == USART2))
jhon309 0:c52df770855b 5480
jhon309 0:c52df770855b 5481 /******************** USART Instances : Synchronous mode **********************/
jhon309 0:c52df770855b 5482 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
jhon309 0:c52df770855b 5483 ((INSTANCE) == USART2) || \
jhon309 0:c52df770855b 5484 ((INSTANCE) == USART3) || \
jhon309 0:c52df770855b 5485 ((INSTANCE) == USART4))
jhon309 0:c52df770855b 5486
jhon309 0:c52df770855b 5487 /******************** USART Instances : auto Baud rate detection **************/
jhon309 0:c52df770855b 5488 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
jhon309 0:c52df770855b 5489 ((INSTANCE) == USART2))
jhon309 0:c52df770855b 5490
jhon309 0:c52df770855b 5491 /******************** UART Instances : Asynchronous mode **********************/
jhon309 0:c52df770855b 5492 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
jhon309 0:c52df770855b 5493 ((INSTANCE) == USART2) || \
jhon309 0:c52df770855b 5494 ((INSTANCE) == USART3) || \
jhon309 0:c52df770855b 5495 ((INSTANCE) == USART4))
jhon309 0:c52df770855b 5496
jhon309 0:c52df770855b 5497 /******************** UART Instances : Half-Duplex mode **********************/
jhon309 0:c52df770855b 5498 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
jhon309 0:c52df770855b 5499 ((INSTANCE) == USART2) || \
jhon309 0:c52df770855b 5500 ((INSTANCE) == USART3) || \
jhon309 0:c52df770855b 5501 ((INSTANCE) == USART4))
jhon309 0:c52df770855b 5502
jhon309 0:c52df770855b 5503 /****************** UART Instances : Hardware Flow control ********************/
jhon309 0:c52df770855b 5504 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
jhon309 0:c52df770855b 5505 ((INSTANCE) == USART2) || \
jhon309 0:c52df770855b 5506 ((INSTANCE) == USART3) || \
jhon309 0:c52df770855b 5507 ((INSTANCE) == USART4))
jhon309 0:c52df770855b 5508
jhon309 0:c52df770855b 5509 /****************** UART Instances : LIN mode ********************/
jhon309 0:c52df770855b 5510 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
jhon309 0:c52df770855b 5511 ((INSTANCE) == USART2))
jhon309 0:c52df770855b 5512
jhon309 0:c52df770855b 5513 /****************** UART Instances : wakeup from stop mode ********************/
jhon309 0:c52df770855b 5514 #define IS_UART_WAKEUP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
jhon309 0:c52df770855b 5515 ((INSTANCE) == USART2))
jhon309 0:c52df770855b 5516
jhon309 0:c52df770855b 5517 /****************** UART Instances : Auto Baud Rate detection ********************/
jhon309 0:c52df770855b 5518 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
jhon309 0:c52df770855b 5519 ((INSTANCE) == USART2))
jhon309 0:c52df770855b 5520
jhon309 0:c52df770855b 5521 /****************** UART Instances : Driver enable detection ********************/
jhon309 0:c52df770855b 5522 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
jhon309 0:c52df770855b 5523 ((INSTANCE) == USART2) || \
jhon309 0:c52df770855b 5524 ((INSTANCE) == USART3) || \
jhon309 0:c52df770855b 5525 ((INSTANCE) == USART4))
jhon309 0:c52df770855b 5526
jhon309 0:c52df770855b 5527 /****************************** USB Instances ********************************/
jhon309 0:c52df770855b 5528 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
jhon309 0:c52df770855b 5529
jhon309 0:c52df770855b 5530 /****************************** WWDG Instances ********************************/
jhon309 0:c52df770855b 5531 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
jhon309 0:c52df770855b 5532
jhon309 0:c52df770855b 5533 /**
jhon309 0:c52df770855b 5534 * @}
jhon309 0:c52df770855b 5535 */
jhon309 0:c52df770855b 5536
jhon309 0:c52df770855b 5537
jhon309 0:c52df770855b 5538 /******************************************************************************/
jhon309 0:c52df770855b 5539 /* For a painless codes migration between the STM32F0xx device product */
jhon309 0:c52df770855b 5540 /* lines, the aliases defined below are put in place to overcome the */
jhon309 0:c52df770855b 5541 /* differences in the interrupt handlers and IRQn definitions. */
jhon309 0:c52df770855b 5542 /* No need to update developed interrupt code when moving across */
jhon309 0:c52df770855b 5543 /* product lines within the same STM32F0 Family */
jhon309 0:c52df770855b 5544 /******************************************************************************/
jhon309 0:c52df770855b 5545
jhon309 0:c52df770855b 5546 /* Aliases for __IRQn */
jhon309 0:c52df770855b 5547 #define PVD_IRQn PVD_VDDIO2_IRQn
jhon309 0:c52df770855b 5548 #define VDDIO2_IRQn PVD_VDDIO2_IRQn
jhon309 0:c52df770855b 5549 #define RCC_IRQn RCC_CRS_IRQn
jhon309 0:c52df770855b 5550 #define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
jhon309 0:c52df770855b 5551 #define ADC1_IRQn ADC1_COMP_IRQn
jhon309 0:c52df770855b 5552 #define TIM6_IRQn TIM6_DAC_IRQn
jhon309 0:c52df770855b 5553
jhon309 0:c52df770855b 5554 /* Aliases for __IRQHandler */
jhon309 0:c52df770855b 5555 #define PVD_IRQHandler PVD_VDDIO2_IRQHandler
jhon309 0:c52df770855b 5556 #define VDDIO2_IRQHandler PVD_VDDIO2_IRQHandler
jhon309 0:c52df770855b 5557 #define RCC_IRQHandler RCC_CRS_IRQHandler
jhon309 0:c52df770855b 5558 #define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
jhon309 0:c52df770855b 5559 #define ADC1_IRQHandler ADC1_COMP_IRQHandler
jhon309 0:c52df770855b 5560 #define TIM6_IRQHandler TIM6_DAC_IRQHandler
jhon309 0:c52df770855b 5561
jhon309 0:c52df770855b 5562 #ifdef __cplusplus
jhon309 0:c52df770855b 5563 }
jhon309 0:c52df770855b 5564 #endif /* __cplusplus */
jhon309 0:c52df770855b 5565
jhon309 0:c52df770855b 5566 #endif /* __STM32F072xB_H */
jhon309 0:c52df770855b 5567
jhon309 0:c52df770855b 5568 /**
jhon309 0:c52df770855b 5569 * @}
jhon309 0:c52df770855b 5570 */
jhon309 0:c52df770855b 5571
jhon309 0:c52df770855b 5572 /**
jhon309 0:c52df770855b 5573 * @}
jhon309 0:c52df770855b 5574 */
jhon309 0:c52df770855b 5575
jhon309 0:c52df770855b 5576 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/