Jhon Plantikow / DHT11

DHT11

TARGET_NUCLEO_F072RB/core_cmFunc.h@0:c52df770855b, 2015-08-13 (annotated)

Committer:
jhon309
Date:
Thu Aug 13 00:21:57 2015 +0000
Revision:
0:c52df770855b
DHT11

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jhon309 0:c52df770855b 1 /**************************************************************************//**
jhon309 0:c52df770855b 2 * @file core_cmFunc.h
jhon309 0:c52df770855b 3 * @brief CMSIS Cortex-M Core Function Access Header File
jhon309 0:c52df770855b 4 * @version V3.20
jhon309 0:c52df770855b 5 * @date 25. February 2013
jhon309 0:c52df770855b 6 *
jhon309 0:c52df770855b 7 * @note
jhon309 0:c52df770855b 8 *
jhon309 0:c52df770855b 9 ******************************************************************************/
jhon309 0:c52df770855b 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
jhon309 0:c52df770855b 11
jhon309 0:c52df770855b 12 All rights reserved.
jhon309 0:c52df770855b 13 Redistribution and use in source and binary forms, with or without
jhon309 0:c52df770855b 14 modification, are permitted provided that the following conditions are met:
jhon309 0:c52df770855b 15 - Redistributions of source code must retain the above copyright
jhon309 0:c52df770855b 16 notice, this list of conditions and the following disclaimer.
jhon309 0:c52df770855b 17 - Redistributions in binary form must reproduce the above copyright
jhon309 0:c52df770855b 18 notice, this list of conditions and the following disclaimer in the
jhon309 0:c52df770855b 19 documentation and/or other materials provided with the distribution.
jhon309 0:c52df770855b 20 - Neither the name of ARM nor the names of its contributors may be used
jhon309 0:c52df770855b 21 to endorse or promote products derived from this software without
jhon309 0:c52df770855b 22 specific prior written permission.
jhon309 0:c52df770855b 23 *
jhon309 0:c52df770855b 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jhon309 0:c52df770855b 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jhon309 0:c52df770855b 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
jhon309 0:c52df770855b 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
jhon309 0:c52df770855b 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
jhon309 0:c52df770855b 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
jhon309 0:c52df770855b 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
jhon309 0:c52df770855b 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
jhon309 0:c52df770855b 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
jhon309 0:c52df770855b 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
jhon309 0:c52df770855b 34 POSSIBILITY OF SUCH DAMAGE.
jhon309 0:c52df770855b 35 ---------------------------------------------------------------------------*/
jhon309 0:c52df770855b 36
jhon309 0:c52df770855b 37
jhon309 0:c52df770855b 38 #ifndef __CORE_CMFUNC_H
jhon309 0:c52df770855b 39 #define __CORE_CMFUNC_H
jhon309 0:c52df770855b 40
jhon309 0:c52df770855b 41
jhon309 0:c52df770855b 42 /* ########################### Core Function Access ########################### */
jhon309 0:c52df770855b 43 /** \ingroup CMSIS_Core_FunctionInterface
jhon309 0:c52df770855b 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
jhon309 0:c52df770855b 45 @{
jhon309 0:c52df770855b 46 */
jhon309 0:c52df770855b 47
jhon309 0:c52df770855b 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
jhon309 0:c52df770855b 49 /* ARM armcc specific functions */
jhon309 0:c52df770855b 50
jhon309 0:c52df770855b 51 #if (__ARMCC_VERSION < 400677)
jhon309 0:c52df770855b 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
jhon309 0:c52df770855b 53 #endif
jhon309 0:c52df770855b 54
jhon309 0:c52df770855b 55 /* intrinsic void __enable_irq(); */
jhon309 0:c52df770855b 56 /* intrinsic void __disable_irq(); */
jhon309 0:c52df770855b 57
jhon309 0:c52df770855b 58 /** \brief Get Control Register
jhon309 0:c52df770855b 59
jhon309 0:c52df770855b 60 This function returns the content of the Control Register.
jhon309 0:c52df770855b 61
jhon309 0:c52df770855b 62 \return Control Register value
jhon309 0:c52df770855b 63 */
jhon309 0:c52df770855b 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
jhon309 0:c52df770855b 65 {
jhon309 0:c52df770855b 66 register uint32_t __regControl __ASM("control");
jhon309 0:c52df770855b 67 return(__regControl);
jhon309 0:c52df770855b 68 }
jhon309 0:c52df770855b 69
jhon309 0:c52df770855b 70
jhon309 0:c52df770855b 71 /** \brief Set Control Register
jhon309 0:c52df770855b 72
jhon309 0:c52df770855b 73 This function writes the given value to the Control Register.
jhon309 0:c52df770855b 74
jhon309 0:c52df770855b 75 \param [in] control Control Register value to set
jhon309 0:c52df770855b 76 */
jhon309 0:c52df770855b 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
jhon309 0:c52df770855b 78 {
jhon309 0:c52df770855b 79 register uint32_t __regControl __ASM("control");
jhon309 0:c52df770855b 80 __regControl = control;
jhon309 0:c52df770855b 81 }
jhon309 0:c52df770855b 82
jhon309 0:c52df770855b 83
jhon309 0:c52df770855b 84 /** \brief Get IPSR Register
jhon309 0:c52df770855b 85
jhon309 0:c52df770855b 86 This function returns the content of the IPSR Register.
jhon309 0:c52df770855b 87
jhon309 0:c52df770855b 88 \return IPSR Register value
jhon309 0:c52df770855b 89 */
jhon309 0:c52df770855b 90 __STATIC_INLINE uint32_t __get_IPSR(void)
jhon309 0:c52df770855b 91 {
jhon309 0:c52df770855b 92 register uint32_t __regIPSR __ASM("ipsr");
jhon309 0:c52df770855b 93 return(__regIPSR);
jhon309 0:c52df770855b 94 }
jhon309 0:c52df770855b 95
jhon309 0:c52df770855b 96
jhon309 0:c52df770855b 97 /** \brief Get APSR Register
jhon309 0:c52df770855b 98
jhon309 0:c52df770855b 99 This function returns the content of the APSR Register.
jhon309 0:c52df770855b 100
jhon309 0:c52df770855b 101 \return APSR Register value
jhon309 0:c52df770855b 102 */
jhon309 0:c52df770855b 103 __STATIC_INLINE uint32_t __get_APSR(void)
jhon309 0:c52df770855b 104 {
jhon309 0:c52df770855b 105 register uint32_t __regAPSR __ASM("apsr");
jhon309 0:c52df770855b 106 return(__regAPSR);
jhon309 0:c52df770855b 107 }
jhon309 0:c52df770855b 108
jhon309 0:c52df770855b 109
jhon309 0:c52df770855b 110 /** \brief Get xPSR Register
jhon309 0:c52df770855b 111
jhon309 0:c52df770855b 112 This function returns the content of the xPSR Register.
jhon309 0:c52df770855b 113
jhon309 0:c52df770855b 114 \return xPSR Register value
jhon309 0:c52df770855b 115 */
jhon309 0:c52df770855b 116 __STATIC_INLINE uint32_t __get_xPSR(void)
jhon309 0:c52df770855b 117 {
jhon309 0:c52df770855b 118 register uint32_t __regXPSR __ASM("xpsr");
jhon309 0:c52df770855b 119 return(__regXPSR);
jhon309 0:c52df770855b 120 }
jhon309 0:c52df770855b 121
jhon309 0:c52df770855b 122
jhon309 0:c52df770855b 123 /** \brief Get Process Stack Pointer
jhon309 0:c52df770855b 124
jhon309 0:c52df770855b 125 This function returns the current value of the Process Stack Pointer (PSP).
jhon309 0:c52df770855b 126
jhon309 0:c52df770855b 127 \return PSP Register value
jhon309 0:c52df770855b 128 */
jhon309 0:c52df770855b 129 __STATIC_INLINE uint32_t __get_PSP(void)
jhon309 0:c52df770855b 130 {
jhon309 0:c52df770855b 131 register uint32_t __regProcessStackPointer __ASM("psp");
jhon309 0:c52df770855b 132 return(__regProcessStackPointer);
jhon309 0:c52df770855b 133 }
jhon309 0:c52df770855b 134
jhon309 0:c52df770855b 135
jhon309 0:c52df770855b 136 /** \brief Set Process Stack Pointer
jhon309 0:c52df770855b 137
jhon309 0:c52df770855b 138 This function assigns the given value to the Process Stack Pointer (PSP).
jhon309 0:c52df770855b 139
jhon309 0:c52df770855b 140 \param [in] topOfProcStack Process Stack Pointer value to set
jhon309 0:c52df770855b 141 */
jhon309 0:c52df770855b 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
jhon309 0:c52df770855b 143 {
jhon309 0:c52df770855b 144 register uint32_t __regProcessStackPointer __ASM("psp");
jhon309 0:c52df770855b 145 __regProcessStackPointer = topOfProcStack;
jhon309 0:c52df770855b 146 }
jhon309 0:c52df770855b 147
jhon309 0:c52df770855b 148
jhon309 0:c52df770855b 149 /** \brief Get Main Stack Pointer
jhon309 0:c52df770855b 150
jhon309 0:c52df770855b 151 This function returns the current value of the Main Stack Pointer (MSP).
jhon309 0:c52df770855b 152
jhon309 0:c52df770855b 153 \return MSP Register value
jhon309 0:c52df770855b 154 */
jhon309 0:c52df770855b 155 __STATIC_INLINE uint32_t __get_MSP(void)
jhon309 0:c52df770855b 156 {
jhon309 0:c52df770855b 157 register uint32_t __regMainStackPointer __ASM("msp");
jhon309 0:c52df770855b 158 return(__regMainStackPointer);
jhon309 0:c52df770855b 159 }
jhon309 0:c52df770855b 160
jhon309 0:c52df770855b 161
jhon309 0:c52df770855b 162 /** \brief Set Main Stack Pointer
jhon309 0:c52df770855b 163
jhon309 0:c52df770855b 164 This function assigns the given value to the Main Stack Pointer (MSP).
jhon309 0:c52df770855b 165
jhon309 0:c52df770855b 166 \param [in] topOfMainStack Main Stack Pointer value to set
jhon309 0:c52df770855b 167 */
jhon309 0:c52df770855b 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
jhon309 0:c52df770855b 169 {
jhon309 0:c52df770855b 170 register uint32_t __regMainStackPointer __ASM("msp");
jhon309 0:c52df770855b 171 __regMainStackPointer = topOfMainStack;
jhon309 0:c52df770855b 172 }
jhon309 0:c52df770855b 173
jhon309 0:c52df770855b 174
jhon309 0:c52df770855b 175 /** \brief Get Priority Mask
jhon309 0:c52df770855b 176
jhon309 0:c52df770855b 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
jhon309 0:c52df770855b 178
jhon309 0:c52df770855b 179 \return Priority Mask value
jhon309 0:c52df770855b 180 */
jhon309 0:c52df770855b 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
jhon309 0:c52df770855b 182 {
jhon309 0:c52df770855b 183 register uint32_t __regPriMask __ASM("primask");
jhon309 0:c52df770855b 184 return(__regPriMask);
jhon309 0:c52df770855b 185 }
jhon309 0:c52df770855b 186
jhon309 0:c52df770855b 187
jhon309 0:c52df770855b 188 /** \brief Set Priority Mask
jhon309 0:c52df770855b 189
jhon309 0:c52df770855b 190 This function assigns the given value to the Priority Mask Register.
jhon309 0:c52df770855b 191
jhon309 0:c52df770855b 192 \param [in] priMask Priority Mask
jhon309 0:c52df770855b 193 */
jhon309 0:c52df770855b 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
jhon309 0:c52df770855b 195 {
jhon309 0:c52df770855b 196 register uint32_t __regPriMask __ASM("primask");
jhon309 0:c52df770855b 197 __regPriMask = (priMask);
jhon309 0:c52df770855b 198 }
jhon309 0:c52df770855b 199
jhon309 0:c52df770855b 200
jhon309 0:c52df770855b 201 #if (__CORTEX_M >= 0x03)
jhon309 0:c52df770855b 202
jhon309 0:c52df770855b 203 /** \brief Enable FIQ
jhon309 0:c52df770855b 204
jhon309 0:c52df770855b 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
jhon309 0:c52df770855b 206 Can only be executed in Privileged modes.
jhon309 0:c52df770855b 207 */
jhon309 0:c52df770855b 208 #define __enable_fault_irq __enable_fiq
jhon309 0:c52df770855b 209
jhon309 0:c52df770855b 210
jhon309 0:c52df770855b 211 /** \brief Disable FIQ
jhon309 0:c52df770855b 212
jhon309 0:c52df770855b 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
jhon309 0:c52df770855b 214 Can only be executed in Privileged modes.
jhon309 0:c52df770855b 215 */
jhon309 0:c52df770855b 216 #define __disable_fault_irq __disable_fiq
jhon309 0:c52df770855b 217
jhon309 0:c52df770855b 218
jhon309 0:c52df770855b 219 /** \brief Get Base Priority
jhon309 0:c52df770855b 220
jhon309 0:c52df770855b 221 This function returns the current value of the Base Priority register.
jhon309 0:c52df770855b 222
jhon309 0:c52df770855b 223 \return Base Priority register value
jhon309 0:c52df770855b 224 */
jhon309 0:c52df770855b 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
jhon309 0:c52df770855b 226 {
jhon309 0:c52df770855b 227 register uint32_t __regBasePri __ASM("basepri");
jhon309 0:c52df770855b 228 return(__regBasePri);
jhon309 0:c52df770855b 229 }
jhon309 0:c52df770855b 230
jhon309 0:c52df770855b 231
jhon309 0:c52df770855b 232 /** \brief Set Base Priority
jhon309 0:c52df770855b 233
jhon309 0:c52df770855b 234 This function assigns the given value to the Base Priority register.
jhon309 0:c52df770855b 235
jhon309 0:c52df770855b 236 \param [in] basePri Base Priority value to set
jhon309 0:c52df770855b 237 */
jhon309 0:c52df770855b 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
jhon309 0:c52df770855b 239 {
jhon309 0:c52df770855b 240 register uint32_t __regBasePri __ASM("basepri");
jhon309 0:c52df770855b 241 __regBasePri = (basePri & 0xff);
jhon309 0:c52df770855b 242 }
jhon309 0:c52df770855b 243
jhon309 0:c52df770855b 244
jhon309 0:c52df770855b 245 /** \brief Get Fault Mask
jhon309 0:c52df770855b 246
jhon309 0:c52df770855b 247 This function returns the current value of the Fault Mask register.
jhon309 0:c52df770855b 248
jhon309 0:c52df770855b 249 \return Fault Mask register value
jhon309 0:c52df770855b 250 */
jhon309 0:c52df770855b 251 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
jhon309 0:c52df770855b 252 {
jhon309 0:c52df770855b 253 register uint32_t __regFaultMask __ASM("faultmask");
jhon309 0:c52df770855b 254 return(__regFaultMask);
jhon309 0:c52df770855b 255 }
jhon309 0:c52df770855b 256
jhon309 0:c52df770855b 257
jhon309 0:c52df770855b 258 /** \brief Set Fault Mask
jhon309 0:c52df770855b 259
jhon309 0:c52df770855b 260 This function assigns the given value to the Fault Mask register.
jhon309 0:c52df770855b 261
jhon309 0:c52df770855b 262 \param [in] faultMask Fault Mask value to set
jhon309 0:c52df770855b 263 */
jhon309 0:c52df770855b 264 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
jhon309 0:c52df770855b 265 {
jhon309 0:c52df770855b 266 register uint32_t __regFaultMask __ASM("faultmask");
jhon309 0:c52df770855b 267 __regFaultMask = (faultMask & (uint32_t)1);
jhon309 0:c52df770855b 268 }
jhon309 0:c52df770855b 269
jhon309 0:c52df770855b 270 #endif /* (__CORTEX_M >= 0x03) */
jhon309 0:c52df770855b 271
jhon309 0:c52df770855b 272
jhon309 0:c52df770855b 273 #if (__CORTEX_M == 0x04)
jhon309 0:c52df770855b 274
jhon309 0:c52df770855b 275 /** \brief Get FPSCR
jhon309 0:c52df770855b 276
jhon309 0:c52df770855b 277 This function returns the current value of the Floating Point Status/Control register.
jhon309 0:c52df770855b 278
jhon309 0:c52df770855b 279 \return Floating Point Status/Control register value
jhon309 0:c52df770855b 280 */
jhon309 0:c52df770855b 281 __STATIC_INLINE uint32_t __get_FPSCR(void)
jhon309 0:c52df770855b 282 {
jhon309 0:c52df770855b 283 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jhon309 0:c52df770855b 284 register uint32_t __regfpscr __ASM("fpscr");
jhon309 0:c52df770855b 285 return(__regfpscr);
jhon309 0:c52df770855b 286 #else
jhon309 0:c52df770855b 287 return(0);
jhon309 0:c52df770855b 288 #endif
jhon309 0:c52df770855b 289 }
jhon309 0:c52df770855b 290
jhon309 0:c52df770855b 291
jhon309 0:c52df770855b 292 /** \brief Set FPSCR
jhon309 0:c52df770855b 293
jhon309 0:c52df770855b 294 This function assigns the given value to the Floating Point Status/Control register.
jhon309 0:c52df770855b 295
jhon309 0:c52df770855b 296 \param [in] fpscr Floating Point Status/Control value to set
jhon309 0:c52df770855b 297 */
jhon309 0:c52df770855b 298 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
jhon309 0:c52df770855b 299 {
jhon309 0:c52df770855b 300 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jhon309 0:c52df770855b 301 register uint32_t __regfpscr __ASM("fpscr");
jhon309 0:c52df770855b 302 __regfpscr = (fpscr);
jhon309 0:c52df770855b 303 #endif
jhon309 0:c52df770855b 304 }
jhon309 0:c52df770855b 305
jhon309 0:c52df770855b 306 #endif /* (__CORTEX_M == 0x04) */
jhon309 0:c52df770855b 307
jhon309 0:c52df770855b 308
jhon309 0:c52df770855b 309 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
jhon309 0:c52df770855b 310 /* IAR iccarm specific functions */
jhon309 0:c52df770855b 311
jhon309 0:c52df770855b 312 #include <cmsis_iar.h>
jhon309 0:c52df770855b 313
jhon309 0:c52df770855b 314
jhon309 0:c52df770855b 315 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
jhon309 0:c52df770855b 316 /* TI CCS specific functions */
jhon309 0:c52df770855b 317
jhon309 0:c52df770855b 318 #include <cmsis_ccs.h>
jhon309 0:c52df770855b 319
jhon309 0:c52df770855b 320
jhon309 0:c52df770855b 321 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
jhon309 0:c52df770855b 322 /* GNU gcc specific functions */
jhon309 0:c52df770855b 323
jhon309 0:c52df770855b 324 /** \brief Enable IRQ Interrupts
jhon309 0:c52df770855b 325
jhon309 0:c52df770855b 326 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
jhon309 0:c52df770855b 327 Can only be executed in Privileged modes.
jhon309 0:c52df770855b 328 */
jhon309 0:c52df770855b 329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
jhon309 0:c52df770855b 330 {
jhon309 0:c52df770855b 331 __ASM volatile ("cpsie i" : : : "memory");
jhon309 0:c52df770855b 332 }
jhon309 0:c52df770855b 333
jhon309 0:c52df770855b 334
jhon309 0:c52df770855b 335 /** \brief Disable IRQ Interrupts
jhon309 0:c52df770855b 336
jhon309 0:c52df770855b 337 This function disables IRQ interrupts by setting the I-bit in the CPSR.
jhon309 0:c52df770855b 338 Can only be executed in Privileged modes.
jhon309 0:c52df770855b 339 */
jhon309 0:c52df770855b 340 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
jhon309 0:c52df770855b 341 {
jhon309 0:c52df770855b 342 __ASM volatile ("cpsid i" : : : "memory");
jhon309 0:c52df770855b 343 }
jhon309 0:c52df770855b 344
jhon309 0:c52df770855b 345
jhon309 0:c52df770855b 346 /** \brief Get Control Register
jhon309 0:c52df770855b 347
jhon309 0:c52df770855b 348 This function returns the content of the Control Register.
jhon309 0:c52df770855b 349
jhon309 0:c52df770855b 350 \return Control Register value
jhon309 0:c52df770855b 351 */
jhon309 0:c52df770855b 352 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
jhon309 0:c52df770855b 353 {
jhon309 0:c52df770855b 354 uint32_t result;
jhon309 0:c52df770855b 355
jhon309 0:c52df770855b 356 __ASM volatile ("MRS %0, control" : "=r" (result) );
jhon309 0:c52df770855b 357 return(result);
jhon309 0:c52df770855b 358 }
jhon309 0:c52df770855b 359
jhon309 0:c52df770855b 360
jhon309 0:c52df770855b 361 /** \brief Set Control Register
jhon309 0:c52df770855b 362
jhon309 0:c52df770855b 363 This function writes the given value to the Control Register.
jhon309 0:c52df770855b 364
jhon309 0:c52df770855b 365 \param [in] control Control Register value to set
jhon309 0:c52df770855b 366 */
jhon309 0:c52df770855b 367 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
jhon309 0:c52df770855b 368 {
jhon309 0:c52df770855b 369 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
jhon309 0:c52df770855b 370 }
jhon309 0:c52df770855b 371
jhon309 0:c52df770855b 372
jhon309 0:c52df770855b 373 /** \brief Get IPSR Register
jhon309 0:c52df770855b 374
jhon309 0:c52df770855b 375 This function returns the content of the IPSR Register.
jhon309 0:c52df770855b 376
jhon309 0:c52df770855b 377 \return IPSR Register value
jhon309 0:c52df770855b 378 */
jhon309 0:c52df770855b 379 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
jhon309 0:c52df770855b 380 {
jhon309 0:c52df770855b 381 uint32_t result;
jhon309 0:c52df770855b 382
jhon309 0:c52df770855b 383 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
jhon309 0:c52df770855b 384 return(result);
jhon309 0:c52df770855b 385 }
jhon309 0:c52df770855b 386
jhon309 0:c52df770855b 387
jhon309 0:c52df770855b 388 /** \brief Get APSR Register
jhon309 0:c52df770855b 389
jhon309 0:c52df770855b 390 This function returns the content of the APSR Register.
jhon309 0:c52df770855b 391
jhon309 0:c52df770855b 392 \return APSR Register value
jhon309 0:c52df770855b 393 */
jhon309 0:c52df770855b 394 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
jhon309 0:c52df770855b 395 {
jhon309 0:c52df770855b 396 uint32_t result;
jhon309 0:c52df770855b 397
jhon309 0:c52df770855b 398 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
jhon309 0:c52df770855b 399 return(result);
jhon309 0:c52df770855b 400 }
jhon309 0:c52df770855b 401
jhon309 0:c52df770855b 402
jhon309 0:c52df770855b 403 /** \brief Get xPSR Register
jhon309 0:c52df770855b 404
jhon309 0:c52df770855b 405 This function returns the content of the xPSR Register.
jhon309 0:c52df770855b 406
jhon309 0:c52df770855b 407 \return xPSR Register value
jhon309 0:c52df770855b 408 */
jhon309 0:c52df770855b 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
jhon309 0:c52df770855b 410 {
jhon309 0:c52df770855b 411 uint32_t result;
jhon309 0:c52df770855b 412
jhon309 0:c52df770855b 413 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
jhon309 0:c52df770855b 414 return(result);
jhon309 0:c52df770855b 415 }
jhon309 0:c52df770855b 416
jhon309 0:c52df770855b 417
jhon309 0:c52df770855b 418 /** \brief Get Process Stack Pointer
jhon309 0:c52df770855b 419
jhon309 0:c52df770855b 420 This function returns the current value of the Process Stack Pointer (PSP).
jhon309 0:c52df770855b 421
jhon309 0:c52df770855b 422 \return PSP Register value
jhon309 0:c52df770855b 423 */
jhon309 0:c52df770855b 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
jhon309 0:c52df770855b 425 {
jhon309 0:c52df770855b 426 register uint32_t result;
jhon309 0:c52df770855b 427
jhon309 0:c52df770855b 428 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
jhon309 0:c52df770855b 429 return(result);
jhon309 0:c52df770855b 430 }
jhon309 0:c52df770855b 431
jhon309 0:c52df770855b 432
jhon309 0:c52df770855b 433 /** \brief Set Process Stack Pointer
jhon309 0:c52df770855b 434
jhon309 0:c52df770855b 435 This function assigns the given value to the Process Stack Pointer (PSP).
jhon309 0:c52df770855b 436
jhon309 0:c52df770855b 437 \param [in] topOfProcStack Process Stack Pointer value to set
jhon309 0:c52df770855b 438 */
jhon309 0:c52df770855b 439 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
jhon309 0:c52df770855b 440 {
jhon309 0:c52df770855b 441 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
jhon309 0:c52df770855b 442 }
jhon309 0:c52df770855b 443
jhon309 0:c52df770855b 444
jhon309 0:c52df770855b 445 /** \brief Get Main Stack Pointer
jhon309 0:c52df770855b 446
jhon309 0:c52df770855b 447 This function returns the current value of the Main Stack Pointer (MSP).
jhon309 0:c52df770855b 448
jhon309 0:c52df770855b 449 \return MSP Register value
jhon309 0:c52df770855b 450 */
jhon309 0:c52df770855b 451 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
jhon309 0:c52df770855b 452 {
jhon309 0:c52df770855b 453 register uint32_t result;
jhon309 0:c52df770855b 454
jhon309 0:c52df770855b 455 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
jhon309 0:c52df770855b 456 return(result);
jhon309 0:c52df770855b 457 }
jhon309 0:c52df770855b 458
jhon309 0:c52df770855b 459
jhon309 0:c52df770855b 460 /** \brief Set Main Stack Pointer
jhon309 0:c52df770855b 461
jhon309 0:c52df770855b 462 This function assigns the given value to the Main Stack Pointer (MSP).
jhon309 0:c52df770855b 463
jhon309 0:c52df770855b 464 \param [in] topOfMainStack Main Stack Pointer value to set
jhon309 0:c52df770855b 465 */
jhon309 0:c52df770855b 466 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
jhon309 0:c52df770855b 467 {
jhon309 0:c52df770855b 468 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
jhon309 0:c52df770855b 469 }
jhon309 0:c52df770855b 470
jhon309 0:c52df770855b 471
jhon309 0:c52df770855b 472 /** \brief Get Priority Mask
jhon309 0:c52df770855b 473
jhon309 0:c52df770855b 474 This function returns the current state of the priority mask bit from the Priority Mask Register.
jhon309 0:c52df770855b 475
jhon309 0:c52df770855b 476 \return Priority Mask value
jhon309 0:c52df770855b 477 */
jhon309 0:c52df770855b 478 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
jhon309 0:c52df770855b 479 {
jhon309 0:c52df770855b 480 uint32_t result;
jhon309 0:c52df770855b 481
jhon309 0:c52df770855b 482 __ASM volatile ("MRS %0, primask" : "=r" (result) );
jhon309 0:c52df770855b 483 return(result);
jhon309 0:c52df770855b 484 }
jhon309 0:c52df770855b 485
jhon309 0:c52df770855b 486
jhon309 0:c52df770855b 487 /** \brief Set Priority Mask
jhon309 0:c52df770855b 488
jhon309 0:c52df770855b 489 This function assigns the given value to the Priority Mask Register.
jhon309 0:c52df770855b 490
jhon309 0:c52df770855b 491 \param [in] priMask Priority Mask
jhon309 0:c52df770855b 492 */
jhon309 0:c52df770855b 493 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
jhon309 0:c52df770855b 494 {
jhon309 0:c52df770855b 495 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
jhon309 0:c52df770855b 496 }
jhon309 0:c52df770855b 497
jhon309 0:c52df770855b 498
jhon309 0:c52df770855b 499 #if (__CORTEX_M >= 0x03)
jhon309 0:c52df770855b 500
jhon309 0:c52df770855b 501 /** \brief Enable FIQ
jhon309 0:c52df770855b 502
jhon309 0:c52df770855b 503 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
jhon309 0:c52df770855b 504 Can only be executed in Privileged modes.
jhon309 0:c52df770855b 505 */
jhon309 0:c52df770855b 506 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
jhon309 0:c52df770855b 507 {
jhon309 0:c52df770855b 508 __ASM volatile ("cpsie f" : : : "memory");
jhon309 0:c52df770855b 509 }
jhon309 0:c52df770855b 510
jhon309 0:c52df770855b 511
jhon309 0:c52df770855b 512 /** \brief Disable FIQ
jhon309 0:c52df770855b 513
jhon309 0:c52df770855b 514 This function disables FIQ interrupts by setting the F-bit in the CPSR.
jhon309 0:c52df770855b 515 Can only be executed in Privileged modes.
jhon309 0:c52df770855b 516 */
jhon309 0:c52df770855b 517 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
jhon309 0:c52df770855b 518 {
jhon309 0:c52df770855b 519 __ASM volatile ("cpsid f" : : : "memory");
jhon309 0:c52df770855b 520 }
jhon309 0:c52df770855b 521
jhon309 0:c52df770855b 522
jhon309 0:c52df770855b 523 /** \brief Get Base Priority
jhon309 0:c52df770855b 524
jhon309 0:c52df770855b 525 This function returns the current value of the Base Priority register.
jhon309 0:c52df770855b 526
jhon309 0:c52df770855b 527 \return Base Priority register value
jhon309 0:c52df770855b 528 */
jhon309 0:c52df770855b 529 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
jhon309 0:c52df770855b 530 {
jhon309 0:c52df770855b 531 uint32_t result;
jhon309 0:c52df770855b 532
jhon309 0:c52df770855b 533 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
jhon309 0:c52df770855b 534 return(result);
jhon309 0:c52df770855b 535 }
jhon309 0:c52df770855b 536
jhon309 0:c52df770855b 537
jhon309 0:c52df770855b 538 /** \brief Set Base Priority
jhon309 0:c52df770855b 539
jhon309 0:c52df770855b 540 This function assigns the given value to the Base Priority register.
jhon309 0:c52df770855b 541
jhon309 0:c52df770855b 542 \param [in] basePri Base Priority value to set
jhon309 0:c52df770855b 543 */
jhon309 0:c52df770855b 544 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
jhon309 0:c52df770855b 545 {
jhon309 0:c52df770855b 546 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
jhon309 0:c52df770855b 547 }
jhon309 0:c52df770855b 548
jhon309 0:c52df770855b 549
jhon309 0:c52df770855b 550 /** \brief Get Fault Mask
jhon309 0:c52df770855b 551
jhon309 0:c52df770855b 552 This function returns the current value of the Fault Mask register.
jhon309 0:c52df770855b 553
jhon309 0:c52df770855b 554 \return Fault Mask register value
jhon309 0:c52df770855b 555 */
jhon309 0:c52df770855b 556 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
jhon309 0:c52df770855b 557 {
jhon309 0:c52df770855b 558 uint32_t result;
jhon309 0:c52df770855b 559
jhon309 0:c52df770855b 560 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
jhon309 0:c52df770855b 561 return(result);
jhon309 0:c52df770855b 562 }
jhon309 0:c52df770855b 563
jhon309 0:c52df770855b 564
jhon309 0:c52df770855b 565 /** \brief Set Fault Mask
jhon309 0:c52df770855b 566
jhon309 0:c52df770855b 567 This function assigns the given value to the Fault Mask register.
jhon309 0:c52df770855b 568
jhon309 0:c52df770855b 569 \param [in] faultMask Fault Mask value to set
jhon309 0:c52df770855b 570 */
jhon309 0:c52df770855b 571 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
jhon309 0:c52df770855b 572 {
jhon309 0:c52df770855b 573 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
jhon309 0:c52df770855b 574 }
jhon309 0:c52df770855b 575
jhon309 0:c52df770855b 576 #endif /* (__CORTEX_M >= 0x03) */
jhon309 0:c52df770855b 577
jhon309 0:c52df770855b 578
jhon309 0:c52df770855b 579 #if (__CORTEX_M == 0x04)
jhon309 0:c52df770855b 580
jhon309 0:c52df770855b 581 /** \brief Get FPSCR
jhon309 0:c52df770855b 582
jhon309 0:c52df770855b 583 This function returns the current value of the Floating Point Status/Control register.
jhon309 0:c52df770855b 584
jhon309 0:c52df770855b 585 \return Floating Point Status/Control register value
jhon309 0:c52df770855b 586 */
jhon309 0:c52df770855b 587 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
jhon309 0:c52df770855b 588 {
jhon309 0:c52df770855b 589 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jhon309 0:c52df770855b 590 uint32_t result;
jhon309 0:c52df770855b 591
jhon309 0:c52df770855b 592 /* Empty asm statement works as a scheduling barrier */
jhon309 0:c52df770855b 593 __ASM volatile ("");
jhon309 0:c52df770855b 594 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
jhon309 0:c52df770855b 595 __ASM volatile ("");
jhon309 0:c52df770855b 596 return(result);
jhon309 0:c52df770855b 597 #else
jhon309 0:c52df770855b 598 return(0);
jhon309 0:c52df770855b 599 #endif
jhon309 0:c52df770855b 600 }
jhon309 0:c52df770855b 601
jhon309 0:c52df770855b 602
jhon309 0:c52df770855b 603 /** \brief Set FPSCR
jhon309 0:c52df770855b 604
jhon309 0:c52df770855b 605 This function assigns the given value to the Floating Point Status/Control register.
jhon309 0:c52df770855b 606
jhon309 0:c52df770855b 607 \param [in] fpscr Floating Point Status/Control value to set
jhon309 0:c52df770855b 608 */
jhon309 0:c52df770855b 609 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
jhon309 0:c52df770855b 610 {
jhon309 0:c52df770855b 611 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jhon309 0:c52df770855b 612 /* Empty asm statement works as a scheduling barrier */
jhon309 0:c52df770855b 613 __ASM volatile ("");
jhon309 0:c52df770855b 614 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
jhon309 0:c52df770855b 615 __ASM volatile ("");
jhon309 0:c52df770855b 616 #endif
jhon309 0:c52df770855b 617 }
jhon309 0:c52df770855b 618
jhon309 0:c52df770855b 619 #endif /* (__CORTEX_M == 0x04) */
jhon309 0:c52df770855b 620
jhon309 0:c52df770855b 621
jhon309 0:c52df770855b 622 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
jhon309 0:c52df770855b 623 /* TASKING carm specific functions */
jhon309 0:c52df770855b 624
jhon309 0:c52df770855b 625 /*
jhon309 0:c52df770855b 626 * The CMSIS functions have been implemented as intrinsics in the compiler.
jhon309 0:c52df770855b 627 * Please use "carm -?i" to get an up to date list of all instrinsics,
jhon309 0:c52df770855b 628 * Including the CMSIS ones.
jhon309 0:c52df770855b 629 */
jhon309 0:c52df770855b 630
jhon309 0:c52df770855b 631 #endif
jhon309 0:c52df770855b 632
jhon309 0:c52df770855b 633 /*@} end of CMSIS_Core_RegAccFunctions */
jhon309 0:c52df770855b 634
jhon309 0:c52df770855b 635
jhon309 0:c52df770855b 636 #endif /* __CORE_CMFUNC_H */