Jhon Plantikow / DHT11

DHT11

TARGET_NUCLEO_F072RB/core_cm4.h@0:c52df770855b, 2015-08-13 (annotated)

Committer:
jhon309
Date:
Thu Aug 13 00:21:57 2015 +0000
Revision:
0:c52df770855b
DHT11

Who changed what in which revision?

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jhon309 0:c52df770855b 1 /**************************************************************************//**
jhon309 0:c52df770855b 2 * @file core_cm4.h
jhon309 0:c52df770855b 3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
jhon309 0:c52df770855b 4 * @version V3.20
jhon309 0:c52df770855b 5 * @date 25. February 2013
jhon309 0:c52df770855b 6 *
jhon309 0:c52df770855b 7 * @note
jhon309 0:c52df770855b 8 *
jhon309 0:c52df770855b 9 ******************************************************************************/
jhon309 0:c52df770855b 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
jhon309 0:c52df770855b 11
jhon309 0:c52df770855b 12 All rights reserved.
jhon309 0:c52df770855b 13 Redistribution and use in source and binary forms, with or without
jhon309 0:c52df770855b 14 modification, are permitted provided that the following conditions are met:
jhon309 0:c52df770855b 15 - Redistributions of source code must retain the above copyright
jhon309 0:c52df770855b 16 notice, this list of conditions and the following disclaimer.
jhon309 0:c52df770855b 17 - Redistributions in binary form must reproduce the above copyright
jhon309 0:c52df770855b 18 notice, this list of conditions and the following disclaimer in the
jhon309 0:c52df770855b 19 documentation and/or other materials provided with the distribution.
jhon309 0:c52df770855b 20 - Neither the name of ARM nor the names of its contributors may be used
jhon309 0:c52df770855b 21 to endorse or promote products derived from this software without
jhon309 0:c52df770855b 22 specific prior written permission.
jhon309 0:c52df770855b 23 *
jhon309 0:c52df770855b 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jhon309 0:c52df770855b 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jhon309 0:c52df770855b 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
jhon309 0:c52df770855b 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
jhon309 0:c52df770855b 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
jhon309 0:c52df770855b 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
jhon309 0:c52df770855b 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
jhon309 0:c52df770855b 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
jhon309 0:c52df770855b 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
jhon309 0:c52df770855b 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
jhon309 0:c52df770855b 34 POSSIBILITY OF SUCH DAMAGE.
jhon309 0:c52df770855b 35 ---------------------------------------------------------------------------*/
jhon309 0:c52df770855b 36
jhon309 0:c52df770855b 37
jhon309 0:c52df770855b 38 #if defined ( __ICCARM__ )
jhon309 0:c52df770855b 39 #pragma system_include /* treat file as system include file for MISRA check */
jhon309 0:c52df770855b 40 #endif
jhon309 0:c52df770855b 41
jhon309 0:c52df770855b 42 #ifdef __cplusplus
jhon309 0:c52df770855b 43 extern "C" {
jhon309 0:c52df770855b 44 #endif
jhon309 0:c52df770855b 45
jhon309 0:c52df770855b 46 #ifndef __CORE_CM4_H_GENERIC
jhon309 0:c52df770855b 47 #define __CORE_CM4_H_GENERIC
jhon309 0:c52df770855b 48
jhon309 0:c52df770855b 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
jhon309 0:c52df770855b 50 CMSIS violates the following MISRA-C:2004 rules:
jhon309 0:c52df770855b 51
jhon309 0:c52df770855b 52 \li Required Rule 8.5, object/function definition in header file.<br>
jhon309 0:c52df770855b 53 Function definitions in header files are used to allow 'inlining'.
jhon309 0:c52df770855b 54
jhon309 0:c52df770855b 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
jhon309 0:c52df770855b 56 Unions are used for effective representation of core registers.
jhon309 0:c52df770855b 57
jhon309 0:c52df770855b 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
jhon309 0:c52df770855b 59 Function-like macros are used to allow more efficient code.
jhon309 0:c52df770855b 60 */
jhon309 0:c52df770855b 61
jhon309 0:c52df770855b 62
jhon309 0:c52df770855b 63 /*******************************************************************************
jhon309 0:c52df770855b 64 * CMSIS definitions
jhon309 0:c52df770855b 65 ******************************************************************************/
jhon309 0:c52df770855b 66 /** \ingroup Cortex_M4
jhon309 0:c52df770855b 67 @{
jhon309 0:c52df770855b 68 */
jhon309 0:c52df770855b 69
jhon309 0:c52df770855b 70 /* CMSIS CM4 definitions */
jhon309 0:c52df770855b 71 #define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
jhon309 0:c52df770855b 72 #define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
jhon309 0:c52df770855b 73 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
jhon309 0:c52df770855b 74 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
jhon309 0:c52df770855b 75
jhon309 0:c52df770855b 76 #define __CORTEX_M (0x04) /*!< Cortex-M Core */
jhon309 0:c52df770855b 77
jhon309 0:c52df770855b 78
jhon309 0:c52df770855b 79 #if defined ( __CC_ARM )
jhon309 0:c52df770855b 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
jhon309 0:c52df770855b 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
jhon309 0:c52df770855b 82 #define __STATIC_INLINE static __inline
jhon309 0:c52df770855b 83
jhon309 0:c52df770855b 84 #elif defined ( __ICCARM__ )
jhon309 0:c52df770855b 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
jhon309 0:c52df770855b 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
jhon309 0:c52df770855b 87 #define __STATIC_INLINE static inline
jhon309 0:c52df770855b 88
jhon309 0:c52df770855b 89 #elif defined ( __TMS470__ )
jhon309 0:c52df770855b 90 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
jhon309 0:c52df770855b 91 #define __STATIC_INLINE static inline
jhon309 0:c52df770855b 92
jhon309 0:c52df770855b 93 #elif defined ( __GNUC__ )
jhon309 0:c52df770855b 94 #define __ASM __asm /*!< asm keyword for GNU Compiler */
jhon309 0:c52df770855b 95 #define __INLINE inline /*!< inline keyword for GNU Compiler */
jhon309 0:c52df770855b 96 #define __STATIC_INLINE static inline
jhon309 0:c52df770855b 97
jhon309 0:c52df770855b 98 #elif defined ( __TASKING__ )
jhon309 0:c52df770855b 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
jhon309 0:c52df770855b 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
jhon309 0:c52df770855b 101 #define __STATIC_INLINE static inline
jhon309 0:c52df770855b 102
jhon309 0:c52df770855b 103 #endif
jhon309 0:c52df770855b 104
jhon309 0:c52df770855b 105 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
jhon309 0:c52df770855b 106 */
jhon309 0:c52df770855b 107 #if defined ( __CC_ARM )
jhon309 0:c52df770855b 108 #if defined __TARGET_FPU_VFP
jhon309 0:c52df770855b 109 #if (__FPU_PRESENT == 1)
jhon309 0:c52df770855b 110 #define __FPU_USED 1
jhon309 0:c52df770855b 111 #else
jhon309 0:c52df770855b 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:c52df770855b 113 #define __FPU_USED 0
jhon309 0:c52df770855b 114 #endif
jhon309 0:c52df770855b 115 #else
jhon309 0:c52df770855b 116 #define __FPU_USED 0
jhon309 0:c52df770855b 117 #endif
jhon309 0:c52df770855b 118
jhon309 0:c52df770855b 119 #elif defined ( __ICCARM__ )
jhon309 0:c52df770855b 120 #if defined __ARMVFP__
jhon309 0:c52df770855b 121 #if (__FPU_PRESENT == 1)
jhon309 0:c52df770855b 122 #define __FPU_USED 1
jhon309 0:c52df770855b 123 #else
jhon309 0:c52df770855b 124 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:c52df770855b 125 #define __FPU_USED 0
jhon309 0:c52df770855b 126 #endif
jhon309 0:c52df770855b 127 #else
jhon309 0:c52df770855b 128 #define __FPU_USED 0
jhon309 0:c52df770855b 129 #endif
jhon309 0:c52df770855b 130
jhon309 0:c52df770855b 131 #elif defined ( __TMS470__ )
jhon309 0:c52df770855b 132 #if defined __TI_VFP_SUPPORT__
jhon309 0:c52df770855b 133 #if (__FPU_PRESENT == 1)
jhon309 0:c52df770855b 134 #define __FPU_USED 1
jhon309 0:c52df770855b 135 #else
jhon309 0:c52df770855b 136 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:c52df770855b 137 #define __FPU_USED 0
jhon309 0:c52df770855b 138 #endif
jhon309 0:c52df770855b 139 #else
jhon309 0:c52df770855b 140 #define __FPU_USED 0
jhon309 0:c52df770855b 141 #endif
jhon309 0:c52df770855b 142
jhon309 0:c52df770855b 143 #elif defined ( __GNUC__ )
jhon309 0:c52df770855b 144 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
jhon309 0:c52df770855b 145 #if (__FPU_PRESENT == 1)
jhon309 0:c52df770855b 146 #define __FPU_USED 1
jhon309 0:c52df770855b 147 #else
jhon309 0:c52df770855b 148 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:c52df770855b 149 #define __FPU_USED 0
jhon309 0:c52df770855b 150 #endif
jhon309 0:c52df770855b 151 #else
jhon309 0:c52df770855b 152 #define __FPU_USED 0
jhon309 0:c52df770855b 153 #endif
jhon309 0:c52df770855b 154
jhon309 0:c52df770855b 155 #elif defined ( __TASKING__ )
jhon309 0:c52df770855b 156 #if defined __FPU_VFP__
jhon309 0:c52df770855b 157 #if (__FPU_PRESENT == 1)
jhon309 0:c52df770855b 158 #define __FPU_USED 1
jhon309 0:c52df770855b 159 #else
jhon309 0:c52df770855b 160 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:c52df770855b 161 #define __FPU_USED 0
jhon309 0:c52df770855b 162 #endif
jhon309 0:c52df770855b 163 #else
jhon309 0:c52df770855b 164 #define __FPU_USED 0
jhon309 0:c52df770855b 165 #endif
jhon309 0:c52df770855b 166 #endif
jhon309 0:c52df770855b 167
jhon309 0:c52df770855b 168 #include <stdint.h> /* standard types definitions */
jhon309 0:c52df770855b 169 #include <core_cmInstr.h> /* Core Instruction Access */
jhon309 0:c52df770855b 170 #include <core_cmFunc.h> /* Core Function Access */
jhon309 0:c52df770855b 171 #include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
jhon309 0:c52df770855b 172
jhon309 0:c52df770855b 173 #endif /* __CORE_CM4_H_GENERIC */
jhon309 0:c52df770855b 174
jhon309 0:c52df770855b 175 #ifndef __CMSIS_GENERIC
jhon309 0:c52df770855b 176
jhon309 0:c52df770855b 177 #ifndef __CORE_CM4_H_DEPENDANT
jhon309 0:c52df770855b 178 #define __CORE_CM4_H_DEPENDANT
jhon309 0:c52df770855b 179
jhon309 0:c52df770855b 180 /* check device defines and use defaults */
jhon309 0:c52df770855b 181 #if defined __CHECK_DEVICE_DEFINES
jhon309 0:c52df770855b 182 #ifndef __CM4_REV
jhon309 0:c52df770855b 183 #define __CM4_REV 0x0000
jhon309 0:c52df770855b 184 #warning "__CM4_REV not defined in device header file; using default!"
jhon309 0:c52df770855b 185 #endif
jhon309 0:c52df770855b 186
jhon309 0:c52df770855b 187 #ifndef __FPU_PRESENT
jhon309 0:c52df770855b 188 #define __FPU_PRESENT 0
jhon309 0:c52df770855b 189 #warning "__FPU_PRESENT not defined in device header file; using default!"
jhon309 0:c52df770855b 190 #endif
jhon309 0:c52df770855b 191
jhon309 0:c52df770855b 192 #ifndef __MPU_PRESENT
jhon309 0:c52df770855b 193 #define __MPU_PRESENT 0
jhon309 0:c52df770855b 194 #warning "__MPU_PRESENT not defined in device header file; using default!"
jhon309 0:c52df770855b 195 #endif
jhon309 0:c52df770855b 196
jhon309 0:c52df770855b 197 #ifndef __NVIC_PRIO_BITS
jhon309 0:c52df770855b 198 #define __NVIC_PRIO_BITS 4
jhon309 0:c52df770855b 199 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
jhon309 0:c52df770855b 200 #endif
jhon309 0:c52df770855b 201
jhon309 0:c52df770855b 202 #ifndef __Vendor_SysTickConfig
jhon309 0:c52df770855b 203 #define __Vendor_SysTickConfig 0
jhon309 0:c52df770855b 204 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
jhon309 0:c52df770855b 205 #endif
jhon309 0:c52df770855b 206 #endif
jhon309 0:c52df770855b 207
jhon309 0:c52df770855b 208 /* IO definitions (access restrictions to peripheral registers) */
jhon309 0:c52df770855b 209 /**
jhon309 0:c52df770855b 210 \defgroup CMSIS_glob_defs CMSIS Global Defines
jhon309 0:c52df770855b 211
jhon309 0:c52df770855b 212 <strong>IO Type Qualifiers</strong> are used
jhon309 0:c52df770855b 213 \li to specify the access to peripheral variables.
jhon309 0:c52df770855b 214 \li for automatic generation of peripheral register debug information.
jhon309 0:c52df770855b 215 */
jhon309 0:c52df770855b 216 #ifdef __cplusplus
jhon309 0:c52df770855b 217 #define __I volatile /*!< Defines 'read only' permissions */
jhon309 0:c52df770855b 218 #else
jhon309 0:c52df770855b 219 #define __I volatile const /*!< Defines 'read only' permissions */
jhon309 0:c52df770855b 220 #endif
jhon309 0:c52df770855b 221 #define __O volatile /*!< Defines 'write only' permissions */
jhon309 0:c52df770855b 222 #define __IO volatile /*!< Defines 'read / write' permissions */
jhon309 0:c52df770855b 223
jhon309 0:c52df770855b 224 /*@} end of group Cortex_M4 */
jhon309 0:c52df770855b 225
jhon309 0:c52df770855b 226
jhon309 0:c52df770855b 227
jhon309 0:c52df770855b 228 /*******************************************************************************
jhon309 0:c52df770855b 229 * Register Abstraction
jhon309 0:c52df770855b 230 Core Register contain:
jhon309 0:c52df770855b 231 - Core Register
jhon309 0:c52df770855b 232 - Core NVIC Register
jhon309 0:c52df770855b 233 - Core SCB Register
jhon309 0:c52df770855b 234 - Core SysTick Register
jhon309 0:c52df770855b 235 - Core Debug Register
jhon309 0:c52df770855b 236 - Core MPU Register
jhon309 0:c52df770855b 237 - Core FPU Register
jhon309 0:c52df770855b 238 ******************************************************************************/
jhon309 0:c52df770855b 239 /** \defgroup CMSIS_core_register Defines and Type Definitions
jhon309 0:c52df770855b 240 \brief Type definitions and defines for Cortex-M processor based devices.
jhon309 0:c52df770855b 241 */
jhon309 0:c52df770855b 242
jhon309 0:c52df770855b 243 /** \ingroup CMSIS_core_register
jhon309 0:c52df770855b 244 \defgroup CMSIS_CORE Status and Control Registers
jhon309 0:c52df770855b 245 \brief Core Register type definitions.
jhon309 0:c52df770855b 246 @{
jhon309 0:c52df770855b 247 */
jhon309 0:c52df770855b 248
jhon309 0:c52df770855b 249 /** \brief Union type to access the Application Program Status Register (APSR).
jhon309 0:c52df770855b 250 */
jhon309 0:c52df770855b 251 typedef union
jhon309 0:c52df770855b 252 {
jhon309 0:c52df770855b 253 struct
jhon309 0:c52df770855b 254 {
jhon309 0:c52df770855b 255 #if (__CORTEX_M != 0x04)
jhon309 0:c52df770855b 256 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
jhon309 0:c52df770855b 257 #else
jhon309 0:c52df770855b 258 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
jhon309 0:c52df770855b 259 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
jhon309 0:c52df770855b 260 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
jhon309 0:c52df770855b 261 #endif
jhon309 0:c52df770855b 262 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
jhon309 0:c52df770855b 263 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
jhon309 0:c52df770855b 264 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
jhon309 0:c52df770855b 265 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
jhon309 0:c52df770855b 266 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
jhon309 0:c52df770855b 267 } b; /*!< Structure used for bit access */
jhon309 0:c52df770855b 268 uint32_t w; /*!< Type used for word access */
jhon309 0:c52df770855b 269 } APSR_Type;
jhon309 0:c52df770855b 270
jhon309 0:c52df770855b 271
jhon309 0:c52df770855b 272 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
jhon309 0:c52df770855b 273 */
jhon309 0:c52df770855b 274 typedef union
jhon309 0:c52df770855b 275 {
jhon309 0:c52df770855b 276 struct
jhon309 0:c52df770855b 277 {
jhon309 0:c52df770855b 278 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
jhon309 0:c52df770855b 279 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
jhon309 0:c52df770855b 280 } b; /*!< Structure used for bit access */
jhon309 0:c52df770855b 281 uint32_t w; /*!< Type used for word access */
jhon309 0:c52df770855b 282 } IPSR_Type;
jhon309 0:c52df770855b 283
jhon309 0:c52df770855b 284
jhon309 0:c52df770855b 285 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
jhon309 0:c52df770855b 286 */
jhon309 0:c52df770855b 287 typedef union
jhon309 0:c52df770855b 288 {
jhon309 0:c52df770855b 289 struct
jhon309 0:c52df770855b 290 {
jhon309 0:c52df770855b 291 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
jhon309 0:c52df770855b 292 #if (__CORTEX_M != 0x04)
jhon309 0:c52df770855b 293 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
jhon309 0:c52df770855b 294 #else
jhon309 0:c52df770855b 295 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
jhon309 0:c52df770855b 296 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
jhon309 0:c52df770855b 297 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
jhon309 0:c52df770855b 298 #endif
jhon309 0:c52df770855b 299 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
jhon309 0:c52df770855b 300 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
jhon309 0:c52df770855b 301 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
jhon309 0:c52df770855b 302 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
jhon309 0:c52df770855b 303 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
jhon309 0:c52df770855b 304 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
jhon309 0:c52df770855b 305 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
jhon309 0:c52df770855b 306 } b; /*!< Structure used for bit access */
jhon309 0:c52df770855b 307 uint32_t w; /*!< Type used for word access */
jhon309 0:c52df770855b 308 } xPSR_Type;
jhon309 0:c52df770855b 309
jhon309 0:c52df770855b 310
jhon309 0:c52df770855b 311 /** \brief Union type to access the Control Registers (CONTROL).
jhon309 0:c52df770855b 312 */
jhon309 0:c52df770855b 313 typedef union
jhon309 0:c52df770855b 314 {
jhon309 0:c52df770855b 315 struct
jhon309 0:c52df770855b 316 {
jhon309 0:c52df770855b 317 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
jhon309 0:c52df770855b 318 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
jhon309 0:c52df770855b 319 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
jhon309 0:c52df770855b 320 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
jhon309 0:c52df770855b 321 } b; /*!< Structure used for bit access */
jhon309 0:c52df770855b 322 uint32_t w; /*!< Type used for word access */
jhon309 0:c52df770855b 323 } CONTROL_Type;
jhon309 0:c52df770855b 324
jhon309 0:c52df770855b 325 /*@} end of group CMSIS_CORE */
jhon309 0:c52df770855b 326
jhon309 0:c52df770855b 327
jhon309 0:c52df770855b 328 /** \ingroup CMSIS_core_register
jhon309 0:c52df770855b 329 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
jhon309 0:c52df770855b 330 \brief Type definitions for the NVIC Registers
jhon309 0:c52df770855b 331 @{
jhon309 0:c52df770855b 332 */
jhon309 0:c52df770855b 333
jhon309 0:c52df770855b 334 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
jhon309 0:c52df770855b 335 */
jhon309 0:c52df770855b 336 typedef struct
jhon309 0:c52df770855b 337 {
jhon309 0:c52df770855b 338 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
jhon309 0:c52df770855b 339 uint32_t RESERVED0[24];
jhon309 0:c52df770855b 340 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
jhon309 0:c52df770855b 341 uint32_t RSERVED1[24];
jhon309 0:c52df770855b 342 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
jhon309 0:c52df770855b 343 uint32_t RESERVED2[24];
jhon309 0:c52df770855b 344 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
jhon309 0:c52df770855b 345 uint32_t RESERVED3[24];
jhon309 0:c52df770855b 346 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
jhon309 0:c52df770855b 347 uint32_t RESERVED4[56];
jhon309 0:c52df770855b 348 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
jhon309 0:c52df770855b 349 uint32_t RESERVED5[644];
jhon309 0:c52df770855b 350 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
jhon309 0:c52df770855b 351 } NVIC_Type;
jhon309 0:c52df770855b 352
jhon309 0:c52df770855b 353 /* Software Triggered Interrupt Register Definitions */
jhon309 0:c52df770855b 354 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
jhon309 0:c52df770855b 355 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
jhon309 0:c52df770855b 356
jhon309 0:c52df770855b 357 /*@} end of group CMSIS_NVIC */
jhon309 0:c52df770855b 358
jhon309 0:c52df770855b 359
jhon309 0:c52df770855b 360 /** \ingroup CMSIS_core_register
jhon309 0:c52df770855b 361 \defgroup CMSIS_SCB System Control Block (SCB)
jhon309 0:c52df770855b 362 \brief Type definitions for the System Control Block Registers
jhon309 0:c52df770855b 363 @{
jhon309 0:c52df770855b 364 */
jhon309 0:c52df770855b 365
jhon309 0:c52df770855b 366 /** \brief Structure type to access the System Control Block (SCB).
jhon309 0:c52df770855b 367 */
jhon309 0:c52df770855b 368 typedef struct
jhon309 0:c52df770855b 369 {
jhon309 0:c52df770855b 370 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
jhon309 0:c52df770855b 371 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
jhon309 0:c52df770855b 372 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
jhon309 0:c52df770855b 373 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
jhon309 0:c52df770855b 374 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
jhon309 0:c52df770855b 375 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
jhon309 0:c52df770855b 376 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
jhon309 0:c52df770855b 377 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
jhon309 0:c52df770855b 378 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
jhon309 0:c52df770855b 379 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
jhon309 0:c52df770855b 380 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
jhon309 0:c52df770855b 381 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
jhon309 0:c52df770855b 382 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
jhon309 0:c52df770855b 383 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
jhon309 0:c52df770855b 384 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
jhon309 0:c52df770855b 385 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
jhon309 0:c52df770855b 386 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
jhon309 0:c52df770855b 387 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
jhon309 0:c52df770855b 388 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
jhon309 0:c52df770855b 389 uint32_t RESERVED0[5];
jhon309 0:c52df770855b 390 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
jhon309 0:c52df770855b 391 } SCB_Type;
jhon309 0:c52df770855b 392
jhon309 0:c52df770855b 393 /* SCB CPUID Register Definitions */
jhon309 0:c52df770855b 394 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
jhon309 0:c52df770855b 395 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
jhon309 0:c52df770855b 396
jhon309 0:c52df770855b 397 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
jhon309 0:c52df770855b 398 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
jhon309 0:c52df770855b 399
jhon309 0:c52df770855b 400 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
jhon309 0:c52df770855b 401 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
jhon309 0:c52df770855b 402
jhon309 0:c52df770855b 403 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
jhon309 0:c52df770855b 404 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
jhon309 0:c52df770855b 405
jhon309 0:c52df770855b 406 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
jhon309 0:c52df770855b 407 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
jhon309 0:c52df770855b 408
jhon309 0:c52df770855b 409 /* SCB Interrupt Control State Register Definitions */
jhon309 0:c52df770855b 410 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
jhon309 0:c52df770855b 411 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
jhon309 0:c52df770855b 412
jhon309 0:c52df770855b 413 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
jhon309 0:c52df770855b 414 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
jhon309 0:c52df770855b 415
jhon309 0:c52df770855b 416 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
jhon309 0:c52df770855b 417 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
jhon309 0:c52df770855b 418
jhon309 0:c52df770855b 419 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
jhon309 0:c52df770855b 420 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
jhon309 0:c52df770855b 421
jhon309 0:c52df770855b 422 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
jhon309 0:c52df770855b 423 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
jhon309 0:c52df770855b 424
jhon309 0:c52df770855b 425 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
jhon309 0:c52df770855b 426 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
jhon309 0:c52df770855b 427
jhon309 0:c52df770855b 428 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
jhon309 0:c52df770855b 429 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
jhon309 0:c52df770855b 430
jhon309 0:c52df770855b 431 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
jhon309 0:c52df770855b 432 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
jhon309 0:c52df770855b 433
jhon309 0:c52df770855b 434 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
jhon309 0:c52df770855b 435 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
jhon309 0:c52df770855b 436
jhon309 0:c52df770855b 437 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
jhon309 0:c52df770855b 438 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
jhon309 0:c52df770855b 439
jhon309 0:c52df770855b 440 /* SCB Vector Table Offset Register Definitions */
jhon309 0:c52df770855b 441 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
jhon309 0:c52df770855b 442 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
jhon309 0:c52df770855b 443
jhon309 0:c52df770855b 444 /* SCB Application Interrupt and Reset Control Register Definitions */
jhon309 0:c52df770855b 445 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
jhon309 0:c52df770855b 446 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
jhon309 0:c52df770855b 447
jhon309 0:c52df770855b 448 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
jhon309 0:c52df770855b 449 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
jhon309 0:c52df770855b 450
jhon309 0:c52df770855b 451 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
jhon309 0:c52df770855b 452 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
jhon309 0:c52df770855b 453
jhon309 0:c52df770855b 454 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
jhon309 0:c52df770855b 455 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
jhon309 0:c52df770855b 456
jhon309 0:c52df770855b 457 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
jhon309 0:c52df770855b 458 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
jhon309 0:c52df770855b 459
jhon309 0:c52df770855b 460 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
jhon309 0:c52df770855b 461 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
jhon309 0:c52df770855b 462
jhon309 0:c52df770855b 463 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
jhon309 0:c52df770855b 464 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
jhon309 0:c52df770855b 465
jhon309 0:c52df770855b 466 /* SCB System Control Register Definitions */
jhon309 0:c52df770855b 467 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
jhon309 0:c52df770855b 468 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
jhon309 0:c52df770855b 469
jhon309 0:c52df770855b 470 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
jhon309 0:c52df770855b 471 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
jhon309 0:c52df770855b 472
jhon309 0:c52df770855b 473 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
jhon309 0:c52df770855b 474 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
jhon309 0:c52df770855b 475
jhon309 0:c52df770855b 476 /* SCB Configuration Control Register Definitions */
jhon309 0:c52df770855b 477 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
jhon309 0:c52df770855b 478 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
jhon309 0:c52df770855b 479
jhon309 0:c52df770855b 480 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
jhon309 0:c52df770855b 481 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
jhon309 0:c52df770855b 482
jhon309 0:c52df770855b 483 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
jhon309 0:c52df770855b 484 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
jhon309 0:c52df770855b 485
jhon309 0:c52df770855b 486 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
jhon309 0:c52df770855b 487 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
jhon309 0:c52df770855b 488
jhon309 0:c52df770855b 489 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
jhon309 0:c52df770855b 490 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
jhon309 0:c52df770855b 491
jhon309 0:c52df770855b 492 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
jhon309 0:c52df770855b 493 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
jhon309 0:c52df770855b 494
jhon309 0:c52df770855b 495 /* SCB System Handler Control and State Register Definitions */
jhon309 0:c52df770855b 496 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
jhon309 0:c52df770855b 497 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
jhon309 0:c52df770855b 498
jhon309 0:c52df770855b 499 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
jhon309 0:c52df770855b 500 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
jhon309 0:c52df770855b 501
jhon309 0:c52df770855b 502 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
jhon309 0:c52df770855b 503 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
jhon309 0:c52df770855b 504
jhon309 0:c52df770855b 505 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
jhon309 0:c52df770855b 506 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
jhon309 0:c52df770855b 507
jhon309 0:c52df770855b 508 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
jhon309 0:c52df770855b 509 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
jhon309 0:c52df770855b 510
jhon309 0:c52df770855b 511 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
jhon309 0:c52df770855b 512 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
jhon309 0:c52df770855b 513
jhon309 0:c52df770855b 514 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
jhon309 0:c52df770855b 515 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
jhon309 0:c52df770855b 516
jhon309 0:c52df770855b 517 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
jhon309 0:c52df770855b 518 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
jhon309 0:c52df770855b 519
jhon309 0:c52df770855b 520 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
jhon309 0:c52df770855b 521 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
jhon309 0:c52df770855b 522
jhon309 0:c52df770855b 523 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
jhon309 0:c52df770855b 524 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
jhon309 0:c52df770855b 525
jhon309 0:c52df770855b 526 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
jhon309 0:c52df770855b 527 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
jhon309 0:c52df770855b 528
jhon309 0:c52df770855b 529 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
jhon309 0:c52df770855b 530 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
jhon309 0:c52df770855b 531
jhon309 0:c52df770855b 532 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
jhon309 0:c52df770855b 533 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
jhon309 0:c52df770855b 534
jhon309 0:c52df770855b 535 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
jhon309 0:c52df770855b 536 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
jhon309 0:c52df770855b 537
jhon309 0:c52df770855b 538 /* SCB Configurable Fault Status Registers Definitions */
jhon309 0:c52df770855b 539 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
jhon309 0:c52df770855b 540 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
jhon309 0:c52df770855b 541
jhon309 0:c52df770855b 542 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
jhon309 0:c52df770855b 543 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
jhon309 0:c52df770855b 544
jhon309 0:c52df770855b 545 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
jhon309 0:c52df770855b 546 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
jhon309 0:c52df770855b 547
jhon309 0:c52df770855b 548 /* SCB Hard Fault Status Registers Definitions */
jhon309 0:c52df770855b 549 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
jhon309 0:c52df770855b 550 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
jhon309 0:c52df770855b 551
jhon309 0:c52df770855b 552 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
jhon309 0:c52df770855b 553 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
jhon309 0:c52df770855b 554
jhon309 0:c52df770855b 555 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
jhon309 0:c52df770855b 556 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
jhon309 0:c52df770855b 557
jhon309 0:c52df770855b 558 /* SCB Debug Fault Status Register Definitions */
jhon309 0:c52df770855b 559 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
jhon309 0:c52df770855b 560 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
jhon309 0:c52df770855b 561
jhon309 0:c52df770855b 562 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
jhon309 0:c52df770855b 563 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
jhon309 0:c52df770855b 564
jhon309 0:c52df770855b 565 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
jhon309 0:c52df770855b 566 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
jhon309 0:c52df770855b 567
jhon309 0:c52df770855b 568 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
jhon309 0:c52df770855b 569 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
jhon309 0:c52df770855b 570
jhon309 0:c52df770855b 571 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
jhon309 0:c52df770855b 572 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
jhon309 0:c52df770855b 573
jhon309 0:c52df770855b 574 /*@} end of group CMSIS_SCB */
jhon309 0:c52df770855b 575
jhon309 0:c52df770855b 576
jhon309 0:c52df770855b 577 /** \ingroup CMSIS_core_register
jhon309 0:c52df770855b 578 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
jhon309 0:c52df770855b 579 \brief Type definitions for the System Control and ID Register not in the SCB
jhon309 0:c52df770855b 580 @{
jhon309 0:c52df770855b 581 */
jhon309 0:c52df770855b 582
jhon309 0:c52df770855b 583 /** \brief Structure type to access the System Control and ID Register not in the SCB.
jhon309 0:c52df770855b 584 */
jhon309 0:c52df770855b 585 typedef struct
jhon309 0:c52df770855b 586 {
jhon309 0:c52df770855b 587 uint32_t RESERVED0[1];
jhon309 0:c52df770855b 588 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
jhon309 0:c52df770855b 589 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
jhon309 0:c52df770855b 590 } SCnSCB_Type;
jhon309 0:c52df770855b 591
jhon309 0:c52df770855b 592 /* Interrupt Controller Type Register Definitions */
jhon309 0:c52df770855b 593 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
jhon309 0:c52df770855b 594 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
jhon309 0:c52df770855b 595
jhon309 0:c52df770855b 596 /* Auxiliary Control Register Definitions */
jhon309 0:c52df770855b 597 #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
jhon309 0:c52df770855b 598 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
jhon309 0:c52df770855b 599
jhon309 0:c52df770855b 600 #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
jhon309 0:c52df770855b 601 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
jhon309 0:c52df770855b 602
jhon309 0:c52df770855b 603 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
jhon309 0:c52df770855b 604 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
jhon309 0:c52df770855b 605
jhon309 0:c52df770855b 606 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
jhon309 0:c52df770855b 607 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
jhon309 0:c52df770855b 608
jhon309 0:c52df770855b 609 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
jhon309 0:c52df770855b 610 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
jhon309 0:c52df770855b 611
jhon309 0:c52df770855b 612 /*@} end of group CMSIS_SCnotSCB */
jhon309 0:c52df770855b 613
jhon309 0:c52df770855b 614
jhon309 0:c52df770855b 615 /** \ingroup CMSIS_core_register
jhon309 0:c52df770855b 616 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
jhon309 0:c52df770855b 617 \brief Type definitions for the System Timer Registers.
jhon309 0:c52df770855b 618 @{
jhon309 0:c52df770855b 619 */
jhon309 0:c52df770855b 620
jhon309 0:c52df770855b 621 /** \brief Structure type to access the System Timer (SysTick).
jhon309 0:c52df770855b 622 */
jhon309 0:c52df770855b 623 typedef struct
jhon309 0:c52df770855b 624 {
jhon309 0:c52df770855b 625 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
jhon309 0:c52df770855b 626 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
jhon309 0:c52df770855b 627 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
jhon309 0:c52df770855b 628 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
jhon309 0:c52df770855b 629 } SysTick_Type;
jhon309 0:c52df770855b 630
jhon309 0:c52df770855b 631 /* SysTick Control / Status Register Definitions */
jhon309 0:c52df770855b 632 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
jhon309 0:c52df770855b 633 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
jhon309 0:c52df770855b 634
jhon309 0:c52df770855b 635 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
jhon309 0:c52df770855b 636 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
jhon309 0:c52df770855b 637
jhon309 0:c52df770855b 638 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
jhon309 0:c52df770855b 639 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
jhon309 0:c52df770855b 640
jhon309 0:c52df770855b 641 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
jhon309 0:c52df770855b 642 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
jhon309 0:c52df770855b 643
jhon309 0:c52df770855b 644 /* SysTick Reload Register Definitions */
jhon309 0:c52df770855b 645 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
jhon309 0:c52df770855b 646 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
jhon309 0:c52df770855b 647
jhon309 0:c52df770855b 648 /* SysTick Current Register Definitions */
jhon309 0:c52df770855b 649 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
jhon309 0:c52df770855b 650 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
jhon309 0:c52df770855b 651
jhon309 0:c52df770855b 652 /* SysTick Calibration Register Definitions */
jhon309 0:c52df770855b 653 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
jhon309 0:c52df770855b 654 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
jhon309 0:c52df770855b 655
jhon309 0:c52df770855b 656 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
jhon309 0:c52df770855b 657 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
jhon309 0:c52df770855b 658
jhon309 0:c52df770855b 659 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
jhon309 0:c52df770855b 660 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
jhon309 0:c52df770855b 661
jhon309 0:c52df770855b 662 /*@} end of group CMSIS_SysTick */
jhon309 0:c52df770855b 663
jhon309 0:c52df770855b 664
jhon309 0:c52df770855b 665 /** \ingroup CMSIS_core_register
jhon309 0:c52df770855b 666 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
jhon309 0:c52df770855b 667 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
jhon309 0:c52df770855b 668 @{
jhon309 0:c52df770855b 669 */
jhon309 0:c52df770855b 670
jhon309 0:c52df770855b 671 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
jhon309 0:c52df770855b 672 */
jhon309 0:c52df770855b 673 typedef struct
jhon309 0:c52df770855b 674 {
jhon309 0:c52df770855b 675 __O union
jhon309 0:c52df770855b 676 {
jhon309 0:c52df770855b 677 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
jhon309 0:c52df770855b 678 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
jhon309 0:c52df770855b 679 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
jhon309 0:c52df770855b 680 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
jhon309 0:c52df770855b 681 uint32_t RESERVED0[864];
jhon309 0:c52df770855b 682 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
jhon309 0:c52df770855b 683 uint32_t RESERVED1[15];
jhon309 0:c52df770855b 684 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
jhon309 0:c52df770855b 685 uint32_t RESERVED2[15];
jhon309 0:c52df770855b 686 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
jhon309 0:c52df770855b 687 uint32_t RESERVED3[29];
jhon309 0:c52df770855b 688 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
jhon309 0:c52df770855b 689 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
jhon309 0:c52df770855b 690 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
jhon309 0:c52df770855b 691 uint32_t RESERVED4[43];
jhon309 0:c52df770855b 692 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
jhon309 0:c52df770855b 693 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
jhon309 0:c52df770855b 694 uint32_t RESERVED5[6];
jhon309 0:c52df770855b 695 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
jhon309 0:c52df770855b 696 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
jhon309 0:c52df770855b 697 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
jhon309 0:c52df770855b 698 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
jhon309 0:c52df770855b 699 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
jhon309 0:c52df770855b 700 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
jhon309 0:c52df770855b 701 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
jhon309 0:c52df770855b 702 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
jhon309 0:c52df770855b 703 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
jhon309 0:c52df770855b 704 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
jhon309 0:c52df770855b 705 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
jhon309 0:c52df770855b 706 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
jhon309 0:c52df770855b 707 } ITM_Type;
jhon309 0:c52df770855b 708
jhon309 0:c52df770855b 709 /* ITM Trace Privilege Register Definitions */
jhon309 0:c52df770855b 710 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
jhon309 0:c52df770855b 711 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
jhon309 0:c52df770855b 712
jhon309 0:c52df770855b 713 /* ITM Trace Control Register Definitions */
jhon309 0:c52df770855b 714 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
jhon309 0:c52df770855b 715 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
jhon309 0:c52df770855b 716
jhon309 0:c52df770855b 717 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
jhon309 0:c52df770855b 718 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
jhon309 0:c52df770855b 719
jhon309 0:c52df770855b 720 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
jhon309 0:c52df770855b 721 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
jhon309 0:c52df770855b 722
jhon309 0:c52df770855b 723 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
jhon309 0:c52df770855b 724 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
jhon309 0:c52df770855b 725
jhon309 0:c52df770855b 726 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
jhon309 0:c52df770855b 727 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
jhon309 0:c52df770855b 728
jhon309 0:c52df770855b 729 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
jhon309 0:c52df770855b 730 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
jhon309 0:c52df770855b 731
jhon309 0:c52df770855b 732 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
jhon309 0:c52df770855b 733 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
jhon309 0:c52df770855b 734
jhon309 0:c52df770855b 735 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
jhon309 0:c52df770855b 736 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
jhon309 0:c52df770855b 737
jhon309 0:c52df770855b 738 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
jhon309 0:c52df770855b 739 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
jhon309 0:c52df770855b 740
jhon309 0:c52df770855b 741 /* ITM Integration Write Register Definitions */
jhon309 0:c52df770855b 742 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
jhon309 0:c52df770855b 743 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
jhon309 0:c52df770855b 744
jhon309 0:c52df770855b 745 /* ITM Integration Read Register Definitions */
jhon309 0:c52df770855b 746 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
jhon309 0:c52df770855b 747 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
jhon309 0:c52df770855b 748
jhon309 0:c52df770855b 749 /* ITM Integration Mode Control Register Definitions */
jhon309 0:c52df770855b 750 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
jhon309 0:c52df770855b 751 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
jhon309 0:c52df770855b 752
jhon309 0:c52df770855b 753 /* ITM Lock Status Register Definitions */
jhon309 0:c52df770855b 754 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
jhon309 0:c52df770855b 755 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
jhon309 0:c52df770855b 756
jhon309 0:c52df770855b 757 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
jhon309 0:c52df770855b 758 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
jhon309 0:c52df770855b 759
jhon309 0:c52df770855b 760 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
jhon309 0:c52df770855b 761 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
jhon309 0:c52df770855b 762
jhon309 0:c52df770855b 763 /*@}*/ /* end of group CMSIS_ITM */
jhon309 0:c52df770855b 764
jhon309 0:c52df770855b 765
jhon309 0:c52df770855b 766 /** \ingroup CMSIS_core_register
jhon309 0:c52df770855b 767 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
jhon309 0:c52df770855b 768 \brief Type definitions for the Data Watchpoint and Trace (DWT)
jhon309 0:c52df770855b 769 @{
jhon309 0:c52df770855b 770 */
jhon309 0:c52df770855b 771
jhon309 0:c52df770855b 772 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
jhon309 0:c52df770855b 773 */
jhon309 0:c52df770855b 774 typedef struct
jhon309 0:c52df770855b 775 {
jhon309 0:c52df770855b 776 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
jhon309 0:c52df770855b 777 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
jhon309 0:c52df770855b 778 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
jhon309 0:c52df770855b 779 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
jhon309 0:c52df770855b 780 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
jhon309 0:c52df770855b 781 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
jhon309 0:c52df770855b 782 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
jhon309 0:c52df770855b 783 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
jhon309 0:c52df770855b 784 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
jhon309 0:c52df770855b 785 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
jhon309 0:c52df770855b 786 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
jhon309 0:c52df770855b 787 uint32_t RESERVED0[1];
jhon309 0:c52df770855b 788 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
jhon309 0:c52df770855b 789 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
jhon309 0:c52df770855b 790 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
jhon309 0:c52df770855b 791 uint32_t RESERVED1[1];
jhon309 0:c52df770855b 792 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
jhon309 0:c52df770855b 793 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
jhon309 0:c52df770855b 794 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
jhon309 0:c52df770855b 795 uint32_t RESERVED2[1];
jhon309 0:c52df770855b 796 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
jhon309 0:c52df770855b 797 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
jhon309 0:c52df770855b 798 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
jhon309 0:c52df770855b 799 } DWT_Type;
jhon309 0:c52df770855b 800
jhon309 0:c52df770855b 801 /* DWT Control Register Definitions */
jhon309 0:c52df770855b 802 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
jhon309 0:c52df770855b 803 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
jhon309 0:c52df770855b 804
jhon309 0:c52df770855b 805 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
jhon309 0:c52df770855b 806 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
jhon309 0:c52df770855b 807
jhon309 0:c52df770855b 808 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
jhon309 0:c52df770855b 809 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
jhon309 0:c52df770855b 810
jhon309 0:c52df770855b 811 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
jhon309 0:c52df770855b 812 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
jhon309 0:c52df770855b 813
jhon309 0:c52df770855b 814 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
jhon309 0:c52df770855b 815 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
jhon309 0:c52df770855b 816
jhon309 0:c52df770855b 817 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
jhon309 0:c52df770855b 818 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
jhon309 0:c52df770855b 819
jhon309 0:c52df770855b 820 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
jhon309 0:c52df770855b 821 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
jhon309 0:c52df770855b 822
jhon309 0:c52df770855b 823 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
jhon309 0:c52df770855b 824 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
jhon309 0:c52df770855b 825
jhon309 0:c52df770855b 826 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
jhon309 0:c52df770855b 827 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
jhon309 0:c52df770855b 828
jhon309 0:c52df770855b 829 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
jhon309 0:c52df770855b 830 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
jhon309 0:c52df770855b 831
jhon309 0:c52df770855b 832 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
jhon309 0:c52df770855b 833 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
jhon309 0:c52df770855b 834
jhon309 0:c52df770855b 835 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
jhon309 0:c52df770855b 836 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
jhon309 0:c52df770855b 837
jhon309 0:c52df770855b 838 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
jhon309 0:c52df770855b 839 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
jhon309 0:c52df770855b 840
jhon309 0:c52df770855b 841 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
jhon309 0:c52df770855b 842 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
jhon309 0:c52df770855b 843
jhon309 0:c52df770855b 844 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
jhon309 0:c52df770855b 845 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
jhon309 0:c52df770855b 846
jhon309 0:c52df770855b 847 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
jhon309 0:c52df770855b 848 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
jhon309 0:c52df770855b 849
jhon309 0:c52df770855b 850 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
jhon309 0:c52df770855b 851 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
jhon309 0:c52df770855b 852
jhon309 0:c52df770855b 853 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
jhon309 0:c52df770855b 854 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
jhon309 0:c52df770855b 855
jhon309 0:c52df770855b 856 /* DWT CPI Count Register Definitions */
jhon309 0:c52df770855b 857 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
jhon309 0:c52df770855b 858 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
jhon309 0:c52df770855b 859
jhon309 0:c52df770855b 860 /* DWT Exception Overhead Count Register Definitions */
jhon309 0:c52df770855b 861 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
jhon309 0:c52df770855b 862 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
jhon309 0:c52df770855b 863
jhon309 0:c52df770855b 864 /* DWT Sleep Count Register Definitions */
jhon309 0:c52df770855b 865 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
jhon309 0:c52df770855b 866 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
jhon309 0:c52df770855b 867
jhon309 0:c52df770855b 868 /* DWT LSU Count Register Definitions */
jhon309 0:c52df770855b 869 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
jhon309 0:c52df770855b 870 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
jhon309 0:c52df770855b 871
jhon309 0:c52df770855b 872 /* DWT Folded-instruction Count Register Definitions */
jhon309 0:c52df770855b 873 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
jhon309 0:c52df770855b 874 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
jhon309 0:c52df770855b 875
jhon309 0:c52df770855b 876 /* DWT Comparator Mask Register Definitions */
jhon309 0:c52df770855b 877 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
jhon309 0:c52df770855b 878 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
jhon309 0:c52df770855b 879
jhon309 0:c52df770855b 880 /* DWT Comparator Function Register Definitions */
jhon309 0:c52df770855b 881 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
jhon309 0:c52df770855b 882 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
jhon309 0:c52df770855b 883
jhon309 0:c52df770855b 884 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
jhon309 0:c52df770855b 885 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
jhon309 0:c52df770855b 886
jhon309 0:c52df770855b 887 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
jhon309 0:c52df770855b 888 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
jhon309 0:c52df770855b 889
jhon309 0:c52df770855b 890 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
jhon309 0:c52df770855b 891 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
jhon309 0:c52df770855b 892
jhon309 0:c52df770855b 893 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
jhon309 0:c52df770855b 894 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
jhon309 0:c52df770855b 895
jhon309 0:c52df770855b 896 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
jhon309 0:c52df770855b 897 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
jhon309 0:c52df770855b 898
jhon309 0:c52df770855b 899 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
jhon309 0:c52df770855b 900 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
jhon309 0:c52df770855b 901
jhon309 0:c52df770855b 902 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
jhon309 0:c52df770855b 903 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
jhon309 0:c52df770855b 904
jhon309 0:c52df770855b 905 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
jhon309 0:c52df770855b 906 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
jhon309 0:c52df770855b 907
jhon309 0:c52df770855b 908 /*@}*/ /* end of group CMSIS_DWT */
jhon309 0:c52df770855b 909
jhon309 0:c52df770855b 910
jhon309 0:c52df770855b 911 /** \ingroup CMSIS_core_register
jhon309 0:c52df770855b 912 \defgroup CMSIS_TPI Trace Port Interface (TPI)
jhon309 0:c52df770855b 913 \brief Type definitions for the Trace Port Interface (TPI)
jhon309 0:c52df770855b 914 @{
jhon309 0:c52df770855b 915 */
jhon309 0:c52df770855b 916
jhon309 0:c52df770855b 917 /** \brief Structure type to access the Trace Port Interface Register (TPI).
jhon309 0:c52df770855b 918 */
jhon309 0:c52df770855b 919 typedef struct
jhon309 0:c52df770855b 920 {
jhon309 0:c52df770855b 921 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
jhon309 0:c52df770855b 922 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
jhon309 0:c52df770855b 923 uint32_t RESERVED0[2];
jhon309 0:c52df770855b 924 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
jhon309 0:c52df770855b 925 uint32_t RESERVED1[55];
jhon309 0:c52df770855b 926 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
jhon309 0:c52df770855b 927 uint32_t RESERVED2[131];
jhon309 0:c52df770855b 928 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
jhon309 0:c52df770855b 929 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
jhon309 0:c52df770855b 930 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
jhon309 0:c52df770855b 931 uint32_t RESERVED3[759];
jhon309 0:c52df770855b 932 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
jhon309 0:c52df770855b 933 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
jhon309 0:c52df770855b 934 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
jhon309 0:c52df770855b 935 uint32_t RESERVED4[1];
jhon309 0:c52df770855b 936 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
jhon309 0:c52df770855b 937 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
jhon309 0:c52df770855b 938 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
jhon309 0:c52df770855b 939 uint32_t RESERVED5[39];
jhon309 0:c52df770855b 940 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
jhon309 0:c52df770855b 941 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
jhon309 0:c52df770855b 942 uint32_t RESERVED7[8];
jhon309 0:c52df770855b 943 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
jhon309 0:c52df770855b 944 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
jhon309 0:c52df770855b 945 } TPI_Type;
jhon309 0:c52df770855b 946
jhon309 0:c52df770855b 947 /* TPI Asynchronous Clock Prescaler Register Definitions */
jhon309 0:c52df770855b 948 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
jhon309 0:c52df770855b 949 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
jhon309 0:c52df770855b 950
jhon309 0:c52df770855b 951 /* TPI Selected Pin Protocol Register Definitions */
jhon309 0:c52df770855b 952 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
jhon309 0:c52df770855b 953 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
jhon309 0:c52df770855b 954
jhon309 0:c52df770855b 955 /* TPI Formatter and Flush Status Register Definitions */
jhon309 0:c52df770855b 956 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
jhon309 0:c52df770855b 957 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
jhon309 0:c52df770855b 958
jhon309 0:c52df770855b 959 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
jhon309 0:c52df770855b 960 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
jhon309 0:c52df770855b 961
jhon309 0:c52df770855b 962 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
jhon309 0:c52df770855b 963 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
jhon309 0:c52df770855b 964
jhon309 0:c52df770855b 965 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
jhon309 0:c52df770855b 966 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
jhon309 0:c52df770855b 967
jhon309 0:c52df770855b 968 /* TPI Formatter and Flush Control Register Definitions */
jhon309 0:c52df770855b 969 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
jhon309 0:c52df770855b 970 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
jhon309 0:c52df770855b 971
jhon309 0:c52df770855b 972 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
jhon309 0:c52df770855b 973 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
jhon309 0:c52df770855b 974
jhon309 0:c52df770855b 975 /* TPI TRIGGER Register Definitions */
jhon309 0:c52df770855b 976 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
jhon309 0:c52df770855b 977 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
jhon309 0:c52df770855b 978
jhon309 0:c52df770855b 979 /* TPI Integration ETM Data Register Definitions (FIFO0) */
jhon309 0:c52df770855b 980 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
jhon309 0:c52df770855b 981 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
jhon309 0:c52df770855b 982
jhon309 0:c52df770855b 983 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
jhon309 0:c52df770855b 984 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
jhon309 0:c52df770855b 985
jhon309 0:c52df770855b 986 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
jhon309 0:c52df770855b 987 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
jhon309 0:c52df770855b 988
jhon309 0:c52df770855b 989 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
jhon309 0:c52df770855b 990 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
jhon309 0:c52df770855b 991
jhon309 0:c52df770855b 992 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
jhon309 0:c52df770855b 993 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
jhon309 0:c52df770855b 994
jhon309 0:c52df770855b 995 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
jhon309 0:c52df770855b 996 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
jhon309 0:c52df770855b 997
jhon309 0:c52df770855b 998 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
jhon309 0:c52df770855b 999 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
jhon309 0:c52df770855b 1000
jhon309 0:c52df770855b 1001 /* TPI ITATBCTR2 Register Definitions */
jhon309 0:c52df770855b 1002 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
jhon309 0:c52df770855b 1003 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
jhon309 0:c52df770855b 1004
jhon309 0:c52df770855b 1005 /* TPI Integration ITM Data Register Definitions (FIFO1) */
jhon309 0:c52df770855b 1006 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
jhon309 0:c52df770855b 1007 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
jhon309 0:c52df770855b 1008
jhon309 0:c52df770855b 1009 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
jhon309 0:c52df770855b 1010 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
jhon309 0:c52df770855b 1011
jhon309 0:c52df770855b 1012 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
jhon309 0:c52df770855b 1013 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
jhon309 0:c52df770855b 1014
jhon309 0:c52df770855b 1015 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
jhon309 0:c52df770855b 1016 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
jhon309 0:c52df770855b 1017
jhon309 0:c52df770855b 1018 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
jhon309 0:c52df770855b 1019 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
jhon309 0:c52df770855b 1020
jhon309 0:c52df770855b 1021 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
jhon309 0:c52df770855b 1022 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
jhon309 0:c52df770855b 1023
jhon309 0:c52df770855b 1024 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
jhon309 0:c52df770855b 1025 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
jhon309 0:c52df770855b 1026
jhon309 0:c52df770855b 1027 /* TPI ITATBCTR0 Register Definitions */
jhon309 0:c52df770855b 1028 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
jhon309 0:c52df770855b 1029 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
jhon309 0:c52df770855b 1030
jhon309 0:c52df770855b 1031 /* TPI Integration Mode Control Register Definitions */
jhon309 0:c52df770855b 1032 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
jhon309 0:c52df770855b 1033 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
jhon309 0:c52df770855b 1034
jhon309 0:c52df770855b 1035 /* TPI DEVID Register Definitions */
jhon309 0:c52df770855b 1036 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
jhon309 0:c52df770855b 1037 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
jhon309 0:c52df770855b 1038
jhon309 0:c52df770855b 1039 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
jhon309 0:c52df770855b 1040 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
jhon309 0:c52df770855b 1041
jhon309 0:c52df770855b 1042 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
jhon309 0:c52df770855b 1043 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
jhon309 0:c52df770855b 1044
jhon309 0:c52df770855b 1045 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
jhon309 0:c52df770855b 1046 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
jhon309 0:c52df770855b 1047
jhon309 0:c52df770855b 1048 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
jhon309 0:c52df770855b 1049 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
jhon309 0:c52df770855b 1050
jhon309 0:c52df770855b 1051 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
jhon309 0:c52df770855b 1052 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
jhon309 0:c52df770855b 1053
jhon309 0:c52df770855b 1054 /* TPI DEVTYPE Register Definitions */
jhon309 0:c52df770855b 1055 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
jhon309 0:c52df770855b 1056 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
jhon309 0:c52df770855b 1057
jhon309 0:c52df770855b 1058 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
jhon309 0:c52df770855b 1059 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
jhon309 0:c52df770855b 1060
jhon309 0:c52df770855b 1061 /*@}*/ /* end of group CMSIS_TPI */
jhon309 0:c52df770855b 1062
jhon309 0:c52df770855b 1063
jhon309 0:c52df770855b 1064 #if (__MPU_PRESENT == 1)
jhon309 0:c52df770855b 1065 /** \ingroup CMSIS_core_register
jhon309 0:c52df770855b 1066 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
jhon309 0:c52df770855b 1067 \brief Type definitions for the Memory Protection Unit (MPU)
jhon309 0:c52df770855b 1068 @{
jhon309 0:c52df770855b 1069 */
jhon309 0:c52df770855b 1070
jhon309 0:c52df770855b 1071 /** \brief Structure type to access the Memory Protection Unit (MPU).
jhon309 0:c52df770855b 1072 */
jhon309 0:c52df770855b 1073 typedef struct
jhon309 0:c52df770855b 1074 {
jhon309 0:c52df770855b 1075 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
jhon309 0:c52df770855b 1076 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
jhon309 0:c52df770855b 1077 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
jhon309 0:c52df770855b 1078 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
jhon309 0:c52df770855b 1079 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
jhon309 0:c52df770855b 1080 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
jhon309 0:c52df770855b 1081 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
jhon309 0:c52df770855b 1082 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
jhon309 0:c52df770855b 1083 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
jhon309 0:c52df770855b 1084 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
jhon309 0:c52df770855b 1085 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
jhon309 0:c52df770855b 1086 } MPU_Type;
jhon309 0:c52df770855b 1087
jhon309 0:c52df770855b 1088 /* MPU Type Register */
jhon309 0:c52df770855b 1089 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
jhon309 0:c52df770855b 1090 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
jhon309 0:c52df770855b 1091
jhon309 0:c52df770855b 1092 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
jhon309 0:c52df770855b 1093 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
jhon309 0:c52df770855b 1094
jhon309 0:c52df770855b 1095 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
jhon309 0:c52df770855b 1096 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
jhon309 0:c52df770855b 1097
jhon309 0:c52df770855b 1098 /* MPU Control Register */
jhon309 0:c52df770855b 1099 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
jhon309 0:c52df770855b 1100 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
jhon309 0:c52df770855b 1101
jhon309 0:c52df770855b 1102 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
jhon309 0:c52df770855b 1103 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
jhon309 0:c52df770855b 1104
jhon309 0:c52df770855b 1105 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
jhon309 0:c52df770855b 1106 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
jhon309 0:c52df770855b 1107
jhon309 0:c52df770855b 1108 /* MPU Region Number Register */
jhon309 0:c52df770855b 1109 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
jhon309 0:c52df770855b 1110 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
jhon309 0:c52df770855b 1111
jhon309 0:c52df770855b 1112 /* MPU Region Base Address Register */
jhon309 0:c52df770855b 1113 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
jhon309 0:c52df770855b 1114 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
jhon309 0:c52df770855b 1115
jhon309 0:c52df770855b 1116 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
jhon309 0:c52df770855b 1117 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
jhon309 0:c52df770855b 1118
jhon309 0:c52df770855b 1119 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
jhon309 0:c52df770855b 1120 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
jhon309 0:c52df770855b 1121
jhon309 0:c52df770855b 1122 /* MPU Region Attribute and Size Register */
jhon309 0:c52df770855b 1123 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
jhon309 0:c52df770855b 1124 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
jhon309 0:c52df770855b 1125
jhon309 0:c52df770855b 1126 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
jhon309 0:c52df770855b 1127 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
jhon309 0:c52df770855b 1128
jhon309 0:c52df770855b 1129 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
jhon309 0:c52df770855b 1130 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
jhon309 0:c52df770855b 1131
jhon309 0:c52df770855b 1132 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
jhon309 0:c52df770855b 1133 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
jhon309 0:c52df770855b 1134
jhon309 0:c52df770855b 1135 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
jhon309 0:c52df770855b 1136 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
jhon309 0:c52df770855b 1137
jhon309 0:c52df770855b 1138 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
jhon309 0:c52df770855b 1139 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
jhon309 0:c52df770855b 1140
jhon309 0:c52df770855b 1141 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
jhon309 0:c52df770855b 1142 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
jhon309 0:c52df770855b 1143
jhon309 0:c52df770855b 1144 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
jhon309 0:c52df770855b 1145 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
jhon309 0:c52df770855b 1146
jhon309 0:c52df770855b 1147 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
jhon309 0:c52df770855b 1148 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
jhon309 0:c52df770855b 1149
jhon309 0:c52df770855b 1150 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
jhon309 0:c52df770855b 1151 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
jhon309 0:c52df770855b 1152
jhon309 0:c52df770855b 1153 /*@} end of group CMSIS_MPU */
jhon309 0:c52df770855b 1154 #endif
jhon309 0:c52df770855b 1155
jhon309 0:c52df770855b 1156
jhon309 0:c52df770855b 1157 #if (__FPU_PRESENT == 1)
jhon309 0:c52df770855b 1158 /** \ingroup CMSIS_core_register
jhon309 0:c52df770855b 1159 \defgroup CMSIS_FPU Floating Point Unit (FPU)
jhon309 0:c52df770855b 1160 \brief Type definitions for the Floating Point Unit (FPU)
jhon309 0:c52df770855b 1161 @{
jhon309 0:c52df770855b 1162 */
jhon309 0:c52df770855b 1163
jhon309 0:c52df770855b 1164 /** \brief Structure type to access the Floating Point Unit (FPU).
jhon309 0:c52df770855b 1165 */
jhon309 0:c52df770855b 1166 typedef struct
jhon309 0:c52df770855b 1167 {
jhon309 0:c52df770855b 1168 uint32_t RESERVED0[1];
jhon309 0:c52df770855b 1169 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
jhon309 0:c52df770855b 1170 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
jhon309 0:c52df770855b 1171 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
jhon309 0:c52df770855b 1172 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
jhon309 0:c52df770855b 1173 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
jhon309 0:c52df770855b 1174 } FPU_Type;
jhon309 0:c52df770855b 1175
jhon309 0:c52df770855b 1176 /* Floating-Point Context Control Register */
jhon309 0:c52df770855b 1177 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
jhon309 0:c52df770855b 1178 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
jhon309 0:c52df770855b 1179
jhon309 0:c52df770855b 1180 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
jhon309 0:c52df770855b 1181 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
jhon309 0:c52df770855b 1182
jhon309 0:c52df770855b 1183 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
jhon309 0:c52df770855b 1184 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
jhon309 0:c52df770855b 1185
jhon309 0:c52df770855b 1186 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
jhon309 0:c52df770855b 1187 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
jhon309 0:c52df770855b 1188
jhon309 0:c52df770855b 1189 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
jhon309 0:c52df770855b 1190 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
jhon309 0:c52df770855b 1191
jhon309 0:c52df770855b 1192 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
jhon309 0:c52df770855b 1193 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
jhon309 0:c52df770855b 1194
jhon309 0:c52df770855b 1195 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
jhon309 0:c52df770855b 1196 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
jhon309 0:c52df770855b 1197
jhon309 0:c52df770855b 1198 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
jhon309 0:c52df770855b 1199 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
jhon309 0:c52df770855b 1200
jhon309 0:c52df770855b 1201 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
jhon309 0:c52df770855b 1202 #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
jhon309 0:c52df770855b 1203
jhon309 0:c52df770855b 1204 /* Floating-Point Context Address Register */
jhon309 0:c52df770855b 1205 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
jhon309 0:c52df770855b 1206 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
jhon309 0:c52df770855b 1207
jhon309 0:c52df770855b 1208 /* Floating-Point Default Status Control Register */
jhon309 0:c52df770855b 1209 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
jhon309 0:c52df770855b 1210 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
jhon309 0:c52df770855b 1211
jhon309 0:c52df770855b 1212 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
jhon309 0:c52df770855b 1213 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
jhon309 0:c52df770855b 1214
jhon309 0:c52df770855b 1215 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
jhon309 0:c52df770855b 1216 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
jhon309 0:c52df770855b 1217
jhon309 0:c52df770855b 1218 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
jhon309 0:c52df770855b 1219 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
jhon309 0:c52df770855b 1220
jhon309 0:c52df770855b 1221 /* Media and FP Feature Register 0 */
jhon309 0:c52df770855b 1222 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
jhon309 0:c52df770855b 1223 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
jhon309 0:c52df770855b 1224
jhon309 0:c52df770855b 1225 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
jhon309 0:c52df770855b 1226 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
jhon309 0:c52df770855b 1227
jhon309 0:c52df770855b 1228 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
jhon309 0:c52df770855b 1229 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
jhon309 0:c52df770855b 1230
jhon309 0:c52df770855b 1231 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
jhon309 0:c52df770855b 1232 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
jhon309 0:c52df770855b 1233
jhon309 0:c52df770855b 1234 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
jhon309 0:c52df770855b 1235 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
jhon309 0:c52df770855b 1236
jhon309 0:c52df770855b 1237 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
jhon309 0:c52df770855b 1238 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
jhon309 0:c52df770855b 1239
jhon309 0:c52df770855b 1240 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
jhon309 0:c52df770855b 1241 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
jhon309 0:c52df770855b 1242
jhon309 0:c52df770855b 1243 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
jhon309 0:c52df770855b 1244 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
jhon309 0:c52df770855b 1245
jhon309 0:c52df770855b 1246 /* Media and FP Feature Register 1 */
jhon309 0:c52df770855b 1247 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
jhon309 0:c52df770855b 1248 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
jhon309 0:c52df770855b 1249
jhon309 0:c52df770855b 1250 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
jhon309 0:c52df770855b 1251 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
jhon309 0:c52df770855b 1252
jhon309 0:c52df770855b 1253 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
jhon309 0:c52df770855b 1254 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
jhon309 0:c52df770855b 1255
jhon309 0:c52df770855b 1256 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
jhon309 0:c52df770855b 1257 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
jhon309 0:c52df770855b 1258
jhon309 0:c52df770855b 1259 /*@} end of group CMSIS_FPU */
jhon309 0:c52df770855b 1260 #endif
jhon309 0:c52df770855b 1261
jhon309 0:c52df770855b 1262
jhon309 0:c52df770855b 1263 /** \ingroup CMSIS_core_register
jhon309 0:c52df770855b 1264 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
jhon309 0:c52df770855b 1265 \brief Type definitions for the Core Debug Registers
jhon309 0:c52df770855b 1266 @{
jhon309 0:c52df770855b 1267 */
jhon309 0:c52df770855b 1268
jhon309 0:c52df770855b 1269 /** \brief Structure type to access the Core Debug Register (CoreDebug).
jhon309 0:c52df770855b 1270 */
jhon309 0:c52df770855b 1271 typedef struct
jhon309 0:c52df770855b 1272 {
jhon309 0:c52df770855b 1273 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
jhon309 0:c52df770855b 1274 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
jhon309 0:c52df770855b 1275 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
jhon309 0:c52df770855b 1276 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
jhon309 0:c52df770855b 1277 } CoreDebug_Type;
jhon309 0:c52df770855b 1278
jhon309 0:c52df770855b 1279 /* Debug Halting Control and Status Register */
jhon309 0:c52df770855b 1280 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
jhon309 0:c52df770855b 1281 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
jhon309 0:c52df770855b 1282
jhon309 0:c52df770855b 1283 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
jhon309 0:c52df770855b 1284 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
jhon309 0:c52df770855b 1285
jhon309 0:c52df770855b 1286 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
jhon309 0:c52df770855b 1287 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
jhon309 0:c52df770855b 1288
jhon309 0:c52df770855b 1289 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
jhon309 0:c52df770855b 1290 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
jhon309 0:c52df770855b 1291
jhon309 0:c52df770855b 1292 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
jhon309 0:c52df770855b 1293 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
jhon309 0:c52df770855b 1294
jhon309 0:c52df770855b 1295 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
jhon309 0:c52df770855b 1296 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
jhon309 0:c52df770855b 1297
jhon309 0:c52df770855b 1298 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
jhon309 0:c52df770855b 1299 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
jhon309 0:c52df770855b 1300
jhon309 0:c52df770855b 1301 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
jhon309 0:c52df770855b 1302 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
jhon309 0:c52df770855b 1303
jhon309 0:c52df770855b 1304 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
jhon309 0:c52df770855b 1305 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
jhon309 0:c52df770855b 1306
jhon309 0:c52df770855b 1307 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
jhon309 0:c52df770855b 1308 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
jhon309 0:c52df770855b 1309
jhon309 0:c52df770855b 1310 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
jhon309 0:c52df770855b 1311 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
jhon309 0:c52df770855b 1312
jhon309 0:c52df770855b 1313 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
jhon309 0:c52df770855b 1314 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
jhon309 0:c52df770855b 1315
jhon309 0:c52df770855b 1316 /* Debug Core Register Selector Register */
jhon309 0:c52df770855b 1317 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
jhon309 0:c52df770855b 1318 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
jhon309 0:c52df770855b 1319
jhon309 0:c52df770855b 1320 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
jhon309 0:c52df770855b 1321 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
jhon309 0:c52df770855b 1322
jhon309 0:c52df770855b 1323 /* Debug Exception and Monitor Control Register */
jhon309 0:c52df770855b 1324 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
jhon309 0:c52df770855b 1325 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
jhon309 0:c52df770855b 1326
jhon309 0:c52df770855b 1327 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
jhon309 0:c52df770855b 1328 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
jhon309 0:c52df770855b 1329
jhon309 0:c52df770855b 1330 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
jhon309 0:c52df770855b 1331 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
jhon309 0:c52df770855b 1332
jhon309 0:c52df770855b 1333 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
jhon309 0:c52df770855b 1334 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
jhon309 0:c52df770855b 1335
jhon309 0:c52df770855b 1336 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
jhon309 0:c52df770855b 1337 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
jhon309 0:c52df770855b 1338
jhon309 0:c52df770855b 1339 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
jhon309 0:c52df770855b 1340 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
jhon309 0:c52df770855b 1341
jhon309 0:c52df770855b 1342 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
jhon309 0:c52df770855b 1343 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
jhon309 0:c52df770855b 1344
jhon309 0:c52df770855b 1345 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
jhon309 0:c52df770855b 1346 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
jhon309 0:c52df770855b 1347
jhon309 0:c52df770855b 1348 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
jhon309 0:c52df770855b 1349 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
jhon309 0:c52df770855b 1350
jhon309 0:c52df770855b 1351 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
jhon309 0:c52df770855b 1352 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
jhon309 0:c52df770855b 1353
jhon309 0:c52df770855b 1354 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
jhon309 0:c52df770855b 1355 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
jhon309 0:c52df770855b 1356
jhon309 0:c52df770855b 1357 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
jhon309 0:c52df770855b 1358 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
jhon309 0:c52df770855b 1359
jhon309 0:c52df770855b 1360 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
jhon309 0:c52df770855b 1361 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
jhon309 0:c52df770855b 1362
jhon309 0:c52df770855b 1363 /*@} end of group CMSIS_CoreDebug */
jhon309 0:c52df770855b 1364
jhon309 0:c52df770855b 1365
jhon309 0:c52df770855b 1366 /** \ingroup CMSIS_core_register
jhon309 0:c52df770855b 1367 \defgroup CMSIS_core_base Core Definitions
jhon309 0:c52df770855b 1368 \brief Definitions for base addresses, unions, and structures.
jhon309 0:c52df770855b 1369 @{
jhon309 0:c52df770855b 1370 */
jhon309 0:c52df770855b 1371
jhon309 0:c52df770855b 1372 /* Memory mapping of Cortex-M4 Hardware */
jhon309 0:c52df770855b 1373 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
jhon309 0:c52df770855b 1374 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
jhon309 0:c52df770855b 1375 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
jhon309 0:c52df770855b 1376 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
jhon309 0:c52df770855b 1377 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
jhon309 0:c52df770855b 1378 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
jhon309 0:c52df770855b 1379 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
jhon309 0:c52df770855b 1380 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
jhon309 0:c52df770855b 1381
jhon309 0:c52df770855b 1382 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
jhon309 0:c52df770855b 1383 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
jhon309 0:c52df770855b 1384 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
jhon309 0:c52df770855b 1385 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
jhon309 0:c52df770855b 1386 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
jhon309 0:c52df770855b 1387 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
jhon309 0:c52df770855b 1388 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
jhon309 0:c52df770855b 1389 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
jhon309 0:c52df770855b 1390
jhon309 0:c52df770855b 1391 #if (__MPU_PRESENT == 1)
jhon309 0:c52df770855b 1392 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
jhon309 0:c52df770855b 1393 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
jhon309 0:c52df770855b 1394 #endif
jhon309 0:c52df770855b 1395
jhon309 0:c52df770855b 1396 #if (__FPU_PRESENT == 1)
jhon309 0:c52df770855b 1397 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
jhon309 0:c52df770855b 1398 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
jhon309 0:c52df770855b 1399 #endif
jhon309 0:c52df770855b 1400
jhon309 0:c52df770855b 1401 /*@} */
jhon309 0:c52df770855b 1402
jhon309 0:c52df770855b 1403
jhon309 0:c52df770855b 1404
jhon309 0:c52df770855b 1405 /*******************************************************************************
jhon309 0:c52df770855b 1406 * Hardware Abstraction Layer
jhon309 0:c52df770855b 1407 Core Function Interface contains:
jhon309 0:c52df770855b 1408 - Core NVIC Functions
jhon309 0:c52df770855b 1409 - Core SysTick Functions
jhon309 0:c52df770855b 1410 - Core Debug Functions
jhon309 0:c52df770855b 1411 - Core Register Access Functions
jhon309 0:c52df770855b 1412 ******************************************************************************/
jhon309 0:c52df770855b 1413 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
jhon309 0:c52df770855b 1414 */
jhon309 0:c52df770855b 1415
jhon309 0:c52df770855b 1416
jhon309 0:c52df770855b 1417
jhon309 0:c52df770855b 1418 /* ########################## NVIC functions #################################### */
jhon309 0:c52df770855b 1419 /** \ingroup CMSIS_Core_FunctionInterface
jhon309 0:c52df770855b 1420 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
jhon309 0:c52df770855b 1421 \brief Functions that manage interrupts and exceptions via the NVIC.
jhon309 0:c52df770855b 1422 @{
jhon309 0:c52df770855b 1423 */
jhon309 0:c52df770855b 1424
jhon309 0:c52df770855b 1425 /** \brief Set Priority Grouping
jhon309 0:c52df770855b 1426
jhon309 0:c52df770855b 1427 The function sets the priority grouping field using the required unlock sequence.
jhon309 0:c52df770855b 1428 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
jhon309 0:c52df770855b 1429 Only values from 0..7 are used.
jhon309 0:c52df770855b 1430 In case of a conflict between priority grouping and available
jhon309 0:c52df770855b 1431 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
jhon309 0:c52df770855b 1432
jhon309 0:c52df770855b 1433 \param [in] PriorityGroup Priority grouping field.
jhon309 0:c52df770855b 1434 */
jhon309 0:c52df770855b 1435 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
jhon309 0:c52df770855b 1436 {
jhon309 0:c52df770855b 1437 uint32_t reg_value;
jhon309 0:c52df770855b 1438 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
jhon309 0:c52df770855b 1439
jhon309 0:c52df770855b 1440 reg_value = SCB->AIRCR; /* read old register configuration */
jhon309 0:c52df770855b 1441 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
jhon309 0:c52df770855b 1442 reg_value = (reg_value |
jhon309 0:c52df770855b 1443 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
jhon309 0:c52df770855b 1444 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
jhon309 0:c52df770855b 1445 SCB->AIRCR = reg_value;
jhon309 0:c52df770855b 1446 }
jhon309 0:c52df770855b 1447
jhon309 0:c52df770855b 1448
jhon309 0:c52df770855b 1449 /** \brief Get Priority Grouping
jhon309 0:c52df770855b 1450
jhon309 0:c52df770855b 1451 The function reads the priority grouping field from the NVIC Interrupt Controller.
jhon309 0:c52df770855b 1452
jhon309 0:c52df770855b 1453 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
jhon309 0:c52df770855b 1454 */
jhon309 0:c52df770855b 1455 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
jhon309 0:c52df770855b 1456 {
jhon309 0:c52df770855b 1457 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
jhon309 0:c52df770855b 1458 }
jhon309 0:c52df770855b 1459
jhon309 0:c52df770855b 1460
jhon309 0:c52df770855b 1461 /** \brief Enable External Interrupt
jhon309 0:c52df770855b 1462
jhon309 0:c52df770855b 1463 The function enables a device-specific interrupt in the NVIC interrupt controller.
jhon309 0:c52df770855b 1464
jhon309 0:c52df770855b 1465 \param [in] IRQn External interrupt number. Value cannot be negative.
jhon309 0:c52df770855b 1466 */
jhon309 0:c52df770855b 1467 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
jhon309 0:c52df770855b 1468 {
jhon309 0:c52df770855b 1469 /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
jhon309 0:c52df770855b 1470 NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
jhon309 0:c52df770855b 1471 }
jhon309 0:c52df770855b 1472
jhon309 0:c52df770855b 1473
jhon309 0:c52df770855b 1474 /** \brief Disable External Interrupt
jhon309 0:c52df770855b 1475
jhon309 0:c52df770855b 1476 The function disables a device-specific interrupt in the NVIC interrupt controller.
jhon309 0:c52df770855b 1477
jhon309 0:c52df770855b 1478 \param [in] IRQn External interrupt number. Value cannot be negative.
jhon309 0:c52df770855b 1479 */
jhon309 0:c52df770855b 1480 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
jhon309 0:c52df770855b 1481 {
jhon309 0:c52df770855b 1482 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
jhon309 0:c52df770855b 1483 }
jhon309 0:c52df770855b 1484
jhon309 0:c52df770855b 1485
jhon309 0:c52df770855b 1486 /** \brief Get Pending Interrupt
jhon309 0:c52df770855b 1487
jhon309 0:c52df770855b 1488 The function reads the pending register in the NVIC and returns the pending bit
jhon309 0:c52df770855b 1489 for the specified interrupt.
jhon309 0:c52df770855b 1490
jhon309 0:c52df770855b 1491 \param [in] IRQn Interrupt number.
jhon309 0:c52df770855b 1492
jhon309 0:c52df770855b 1493 \return 0 Interrupt status is not pending.
jhon309 0:c52df770855b 1494 \return 1 Interrupt status is pending.
jhon309 0:c52df770855b 1495 */
jhon309 0:c52df770855b 1496 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
jhon309 0:c52df770855b 1497 {
jhon309 0:c52df770855b 1498 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
jhon309 0:c52df770855b 1499 }
jhon309 0:c52df770855b 1500
jhon309 0:c52df770855b 1501
jhon309 0:c52df770855b 1502 /** \brief Set Pending Interrupt
jhon309 0:c52df770855b 1503
jhon309 0:c52df770855b 1504 The function sets the pending bit of an external interrupt.
jhon309 0:c52df770855b 1505
jhon309 0:c52df770855b 1506 \param [in] IRQn Interrupt number. Value cannot be negative.
jhon309 0:c52df770855b 1507 */
jhon309 0:c52df770855b 1508 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
jhon309 0:c52df770855b 1509 {
jhon309 0:c52df770855b 1510 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
jhon309 0:c52df770855b 1511 }
jhon309 0:c52df770855b 1512
jhon309 0:c52df770855b 1513
jhon309 0:c52df770855b 1514 /** \brief Clear Pending Interrupt
jhon309 0:c52df770855b 1515
jhon309 0:c52df770855b 1516 The function clears the pending bit of an external interrupt.
jhon309 0:c52df770855b 1517
jhon309 0:c52df770855b 1518 \param [in] IRQn External interrupt number. Value cannot be negative.
jhon309 0:c52df770855b 1519 */
jhon309 0:c52df770855b 1520 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
jhon309 0:c52df770855b 1521 {
jhon309 0:c52df770855b 1522 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
jhon309 0:c52df770855b 1523 }
jhon309 0:c52df770855b 1524
jhon309 0:c52df770855b 1525
jhon309 0:c52df770855b 1526 /** \brief Get Active Interrupt
jhon309 0:c52df770855b 1527
jhon309 0:c52df770855b 1528 The function reads the active register in NVIC and returns the active bit.
jhon309 0:c52df770855b 1529
jhon309 0:c52df770855b 1530 \param [in] IRQn Interrupt number.
jhon309 0:c52df770855b 1531
jhon309 0:c52df770855b 1532 \return 0 Interrupt status is not active.
jhon309 0:c52df770855b 1533 \return 1 Interrupt status is active.
jhon309 0:c52df770855b 1534 */
jhon309 0:c52df770855b 1535 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
jhon309 0:c52df770855b 1536 {
jhon309 0:c52df770855b 1537 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
jhon309 0:c52df770855b 1538 }
jhon309 0:c52df770855b 1539
jhon309 0:c52df770855b 1540
jhon309 0:c52df770855b 1541 /** \brief Set Interrupt Priority
jhon309 0:c52df770855b 1542
jhon309 0:c52df770855b 1543 The function sets the priority of an interrupt.
jhon309 0:c52df770855b 1544
jhon309 0:c52df770855b 1545 \note The priority cannot be set for every core interrupt.
jhon309 0:c52df770855b 1546
jhon309 0:c52df770855b 1547 \param [in] IRQn Interrupt number.
jhon309 0:c52df770855b 1548 \param [in] priority Priority to set.
jhon309 0:c52df770855b 1549 */
jhon309 0:c52df770855b 1550 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
jhon309 0:c52df770855b 1551 {
jhon309 0:c52df770855b 1552 if(IRQn < 0) {
jhon309 0:c52df770855b 1553 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
jhon309 0:c52df770855b 1554 else {
jhon309 0:c52df770855b 1555 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
jhon309 0:c52df770855b 1556 }
jhon309 0:c52df770855b 1557
jhon309 0:c52df770855b 1558
jhon309 0:c52df770855b 1559 /** \brief Get Interrupt Priority
jhon309 0:c52df770855b 1560
jhon309 0:c52df770855b 1561 The function reads the priority of an interrupt. The interrupt
jhon309 0:c52df770855b 1562 number can be positive to specify an external (device specific)
jhon309 0:c52df770855b 1563 interrupt, or negative to specify an internal (core) interrupt.
jhon309 0:c52df770855b 1564
jhon309 0:c52df770855b 1565
jhon309 0:c52df770855b 1566 \param [in] IRQn Interrupt number.
jhon309 0:c52df770855b 1567 \return Interrupt Priority. Value is aligned automatically to the implemented
jhon309 0:c52df770855b 1568 priority bits of the microcontroller.
jhon309 0:c52df770855b 1569 */
jhon309 0:c52df770855b 1570 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
jhon309 0:c52df770855b 1571 {
jhon309 0:c52df770855b 1572
jhon309 0:c52df770855b 1573 if(IRQn < 0) {
jhon309 0:c52df770855b 1574 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
jhon309 0:c52df770855b 1575 else {
jhon309 0:c52df770855b 1576 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
jhon309 0:c52df770855b 1577 }
jhon309 0:c52df770855b 1578
jhon309 0:c52df770855b 1579
jhon309 0:c52df770855b 1580 /** \brief Encode Priority
jhon309 0:c52df770855b 1581
jhon309 0:c52df770855b 1582 The function encodes the priority for an interrupt with the given priority group,
jhon309 0:c52df770855b 1583 preemptive priority value, and subpriority value.
jhon309 0:c52df770855b 1584 In case of a conflict between priority grouping and available
jhon309 0:c52df770855b 1585 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
jhon309 0:c52df770855b 1586
jhon309 0:c52df770855b 1587 \param [in] PriorityGroup Used priority group.
jhon309 0:c52df770855b 1588 \param [in] PreemptPriority Preemptive priority value (starting from 0).
jhon309 0:c52df770855b 1589 \param [in] SubPriority Subpriority value (starting from 0).
jhon309 0:c52df770855b 1590 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
jhon309 0:c52df770855b 1591 */
jhon309 0:c52df770855b 1592 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
jhon309 0:c52df770855b 1593 {
jhon309 0:c52df770855b 1594 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
jhon309 0:c52df770855b 1595 uint32_t PreemptPriorityBits;
jhon309 0:c52df770855b 1596 uint32_t SubPriorityBits;
jhon309 0:c52df770855b 1597
jhon309 0:c52df770855b 1598 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
jhon309 0:c52df770855b 1599 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
jhon309 0:c52df770855b 1600
jhon309 0:c52df770855b 1601 return (
jhon309 0:c52df770855b 1602 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
jhon309 0:c52df770855b 1603 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
jhon309 0:c52df770855b 1604 );
jhon309 0:c52df770855b 1605 }
jhon309 0:c52df770855b 1606
jhon309 0:c52df770855b 1607
jhon309 0:c52df770855b 1608 /** \brief Decode Priority
jhon309 0:c52df770855b 1609
jhon309 0:c52df770855b 1610 The function decodes an interrupt priority value with a given priority group to
jhon309 0:c52df770855b 1611 preemptive priority value and subpriority value.
jhon309 0:c52df770855b 1612 In case of a conflict between priority grouping and available
jhon309 0:c52df770855b 1613 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
jhon309 0:c52df770855b 1614
jhon309 0:c52df770855b 1615 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
jhon309 0:c52df770855b 1616 \param [in] PriorityGroup Used priority group.
jhon309 0:c52df770855b 1617 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
jhon309 0:c52df770855b 1618 \param [out] pSubPriority Subpriority value (starting from 0).
jhon309 0:c52df770855b 1619 */
jhon309 0:c52df770855b 1620 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
jhon309 0:c52df770855b 1621 {
jhon309 0:c52df770855b 1622 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
jhon309 0:c52df770855b 1623 uint32_t PreemptPriorityBits;
jhon309 0:c52df770855b 1624 uint32_t SubPriorityBits;
jhon309 0:c52df770855b 1625
jhon309 0:c52df770855b 1626 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
jhon309 0:c52df770855b 1627 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
jhon309 0:c52df770855b 1628
jhon309 0:c52df770855b 1629 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
jhon309 0:c52df770855b 1630 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
jhon309 0:c52df770855b 1631 }
jhon309 0:c52df770855b 1632
jhon309 0:c52df770855b 1633
jhon309 0:c52df770855b 1634 /** \brief System Reset
jhon309 0:c52df770855b 1635
jhon309 0:c52df770855b 1636 The function initiates a system reset request to reset the MCU.
jhon309 0:c52df770855b 1637 */
jhon309 0:c52df770855b 1638 __STATIC_INLINE void NVIC_SystemReset(void)
jhon309 0:c52df770855b 1639 {
jhon309 0:c52df770855b 1640 __DSB(); /* Ensure all outstanding memory accesses included
jhon309 0:c52df770855b 1641 buffered write are completed before reset */
jhon309 0:c52df770855b 1642 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
jhon309 0:c52df770855b 1643 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
jhon309 0:c52df770855b 1644 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
jhon309 0:c52df770855b 1645 __DSB(); /* Ensure completion of memory access */
jhon309 0:c52df770855b 1646 while(1); /* wait until reset */
jhon309 0:c52df770855b 1647 }
jhon309 0:c52df770855b 1648
jhon309 0:c52df770855b 1649 /*@} end of CMSIS_Core_NVICFunctions */
jhon309 0:c52df770855b 1650
jhon309 0:c52df770855b 1651
jhon309 0:c52df770855b 1652
jhon309 0:c52df770855b 1653 /* ################################## SysTick function ############################################ */
jhon309 0:c52df770855b 1654 /** \ingroup CMSIS_Core_FunctionInterface
jhon309 0:c52df770855b 1655 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
jhon309 0:c52df770855b 1656 \brief Functions that configure the System.
jhon309 0:c52df770855b 1657 @{
jhon309 0:c52df770855b 1658 */
jhon309 0:c52df770855b 1659
jhon309 0:c52df770855b 1660 #if (__Vendor_SysTickConfig == 0)
jhon309 0:c52df770855b 1661
jhon309 0:c52df770855b 1662 /** \brief System Tick Configuration
jhon309 0:c52df770855b 1663
jhon309 0:c52df770855b 1664 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
jhon309 0:c52df770855b 1665 Counter is in free running mode to generate periodic interrupts.
jhon309 0:c52df770855b 1666
jhon309 0:c52df770855b 1667 \param [in] ticks Number of ticks between two interrupts.
jhon309 0:c52df770855b 1668
jhon309 0:c52df770855b 1669 \return 0 Function succeeded.
jhon309 0:c52df770855b 1670 \return 1 Function failed.
jhon309 0:c52df770855b 1671
jhon309 0:c52df770855b 1672 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
jhon309 0:c52df770855b 1673 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
jhon309 0:c52df770855b 1674 must contain a vendor-specific implementation of this function.
jhon309 0:c52df770855b 1675
jhon309 0:c52df770855b 1676 */
jhon309 0:c52df770855b 1677 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
jhon309 0:c52df770855b 1678 {
jhon309 0:c52df770855b 1679 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
jhon309 0:c52df770855b 1680
jhon309 0:c52df770855b 1681 SysTick->LOAD = ticks - 1; /* set reload register */
jhon309 0:c52df770855b 1682 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
jhon309 0:c52df770855b 1683 SysTick->VAL = 0; /* Load the SysTick Counter Value */
jhon309 0:c52df770855b 1684 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
jhon309 0:c52df770855b 1685 SysTick_CTRL_TICKINT_Msk |
jhon309 0:c52df770855b 1686 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
jhon309 0:c52df770855b 1687 return (0); /* Function successful */
jhon309 0:c52df770855b 1688 }
jhon309 0:c52df770855b 1689
jhon309 0:c52df770855b 1690 #endif
jhon309 0:c52df770855b 1691
jhon309 0:c52df770855b 1692 /*@} end of CMSIS_Core_SysTickFunctions */
jhon309 0:c52df770855b 1693
jhon309 0:c52df770855b 1694
jhon309 0:c52df770855b 1695
jhon309 0:c52df770855b 1696 /* ##################################### Debug In/Output function ########################################### */
jhon309 0:c52df770855b 1697 /** \ingroup CMSIS_Core_FunctionInterface
jhon309 0:c52df770855b 1698 \defgroup CMSIS_core_DebugFunctions ITM Functions
jhon309 0:c52df770855b 1699 \brief Functions that access the ITM debug interface.
jhon309 0:c52df770855b 1700 @{
jhon309 0:c52df770855b 1701 */
jhon309 0:c52df770855b 1702
jhon309 0:c52df770855b 1703 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
jhon309 0:c52df770855b 1704 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
jhon309 0:c52df770855b 1705
jhon309 0:c52df770855b 1706
jhon309 0:c52df770855b 1707 /** \brief ITM Send Character
jhon309 0:c52df770855b 1708
jhon309 0:c52df770855b 1709 The function transmits a character via the ITM channel 0, and
jhon309 0:c52df770855b 1710 \li Just returns when no debugger is connected that has booked the output.
jhon309 0:c52df770855b 1711 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
jhon309 0:c52df770855b 1712
jhon309 0:c52df770855b 1713 \param [in] ch Character to transmit.
jhon309 0:c52df770855b 1714
jhon309 0:c52df770855b 1715 \returns Character to transmit.
jhon309 0:c52df770855b 1716 */
jhon309 0:c52df770855b 1717 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
jhon309 0:c52df770855b 1718 {
jhon309 0:c52df770855b 1719 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
jhon309 0:c52df770855b 1720 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
jhon309 0:c52df770855b 1721 {
jhon309 0:c52df770855b 1722 while (ITM->PORT[0].u32 == 0);
jhon309 0:c52df770855b 1723 ITM->PORT[0].u8 = (uint8_t) ch;
jhon309 0:c52df770855b 1724 }
jhon309 0:c52df770855b 1725 return (ch);
jhon309 0:c52df770855b 1726 }
jhon309 0:c52df770855b 1727
jhon309 0:c52df770855b 1728
jhon309 0:c52df770855b 1729 /** \brief ITM Receive Character
jhon309 0:c52df770855b 1730
jhon309 0:c52df770855b 1731 The function inputs a character via the external variable \ref ITM_RxBuffer.
jhon309 0:c52df770855b 1732
jhon309 0:c52df770855b 1733 \return Received character.
jhon309 0:c52df770855b 1734 \return -1 No character pending.
jhon309 0:c52df770855b 1735 */
jhon309 0:c52df770855b 1736 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
jhon309 0:c52df770855b 1737 int32_t ch = -1; /* no character available */
jhon309 0:c52df770855b 1738
jhon309 0:c52df770855b 1739 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
jhon309 0:c52df770855b 1740 ch = ITM_RxBuffer;
jhon309 0:c52df770855b 1741 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
jhon309 0:c52df770855b 1742 }
jhon309 0:c52df770855b 1743
jhon309 0:c52df770855b 1744 return (ch);
jhon309 0:c52df770855b 1745 }
jhon309 0:c52df770855b 1746
jhon309 0:c52df770855b 1747
jhon309 0:c52df770855b 1748 /** \brief ITM Check Character
jhon309 0:c52df770855b 1749
jhon309 0:c52df770855b 1750 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
jhon309 0:c52df770855b 1751
jhon309 0:c52df770855b 1752 \return 0 No character available.
jhon309 0:c52df770855b 1753 \return 1 Character available.
jhon309 0:c52df770855b 1754 */
jhon309 0:c52df770855b 1755 __STATIC_INLINE int32_t ITM_CheckChar (void) {
jhon309 0:c52df770855b 1756
jhon309 0:c52df770855b 1757 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
jhon309 0:c52df770855b 1758 return (0); /* no character available */
jhon309 0:c52df770855b 1759 } else {
jhon309 0:c52df770855b 1760 return (1); /* character available */
jhon309 0:c52df770855b 1761 }
jhon309 0:c52df770855b 1762 }
jhon309 0:c52df770855b 1763
jhon309 0:c52df770855b 1764 /*@} end of CMSIS_core_DebugFunctions */
jhon309 0:c52df770855b 1765
jhon309 0:c52df770855b 1766 #endif /* __CORE_CM4_H_DEPENDANT */
jhon309 0:c52df770855b 1767
jhon309 0:c52df770855b 1768 #endif /* __CMSIS_GENERIC */
jhon309 0:c52df770855b 1769
jhon309 0:c52df770855b 1770 #ifdef __cplusplus
jhon309 0:c52df770855b 1771 }
jhon309 0:c52df770855b 1772 #endif