Jhon Plantikow / DHT11

DHT11

TARGET_NUCLEO_F072RB/core_cm0plus.h@0:c52df770855b, 2015-08-13 (annotated)

Committer:
jhon309
Date:
Thu Aug 13 00:21:57 2015 +0000
Revision:
0:c52df770855b
DHT11

Who changed what in which revision?

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jhon309 0:c52df770855b 1 /**************************************************************************//**
jhon309 0:c52df770855b 2 * @file core_cm0plus.h
jhon309 0:c52df770855b 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
jhon309 0:c52df770855b 4 * @version V3.20
jhon309 0:c52df770855b 5 * @date 25. February 2013
jhon309 0:c52df770855b 6 *
jhon309 0:c52df770855b 7 * @note
jhon309 0:c52df770855b 8 *
jhon309 0:c52df770855b 9 ******************************************************************************/
jhon309 0:c52df770855b 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
jhon309 0:c52df770855b 11
jhon309 0:c52df770855b 12 All rights reserved.
jhon309 0:c52df770855b 13 Redistribution and use in source and binary forms, with or without
jhon309 0:c52df770855b 14 modification, are permitted provided that the following conditions are met:
jhon309 0:c52df770855b 15 - Redistributions of source code must retain the above copyright
jhon309 0:c52df770855b 16 notice, this list of conditions and the following disclaimer.
jhon309 0:c52df770855b 17 - Redistributions in binary form must reproduce the above copyright
jhon309 0:c52df770855b 18 notice, this list of conditions and the following disclaimer in the
jhon309 0:c52df770855b 19 documentation and/or other materials provided with the distribution.
jhon309 0:c52df770855b 20 - Neither the name of ARM nor the names of its contributors may be used
jhon309 0:c52df770855b 21 to endorse or promote products derived from this software without
jhon309 0:c52df770855b 22 specific prior written permission.
jhon309 0:c52df770855b 23 *
jhon309 0:c52df770855b 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jhon309 0:c52df770855b 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jhon309 0:c52df770855b 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
jhon309 0:c52df770855b 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
jhon309 0:c52df770855b 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
jhon309 0:c52df770855b 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
jhon309 0:c52df770855b 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
jhon309 0:c52df770855b 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
jhon309 0:c52df770855b 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
jhon309 0:c52df770855b 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
jhon309 0:c52df770855b 34 POSSIBILITY OF SUCH DAMAGE.
jhon309 0:c52df770855b 35 ---------------------------------------------------------------------------*/
jhon309 0:c52df770855b 36
jhon309 0:c52df770855b 37
jhon309 0:c52df770855b 38 #if defined ( __ICCARM__ )
jhon309 0:c52df770855b 39 #pragma system_include /* treat file as system include file for MISRA check */
jhon309 0:c52df770855b 40 #endif
jhon309 0:c52df770855b 41
jhon309 0:c52df770855b 42 #ifdef __cplusplus
jhon309 0:c52df770855b 43 extern "C" {
jhon309 0:c52df770855b 44 #endif
jhon309 0:c52df770855b 45
jhon309 0:c52df770855b 46 #ifndef __CORE_CM0PLUS_H_GENERIC
jhon309 0:c52df770855b 47 #define __CORE_CM0PLUS_H_GENERIC
jhon309 0:c52df770855b 48
jhon309 0:c52df770855b 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
jhon309 0:c52df770855b 50 CMSIS violates the following MISRA-C:2004 rules:
jhon309 0:c52df770855b 51
jhon309 0:c52df770855b 52 \li Required Rule 8.5, object/function definition in header file.<br>
jhon309 0:c52df770855b 53 Function definitions in header files are used to allow 'inlining'.
jhon309 0:c52df770855b 54
jhon309 0:c52df770855b 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
jhon309 0:c52df770855b 56 Unions are used for effective representation of core registers.
jhon309 0:c52df770855b 57
jhon309 0:c52df770855b 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
jhon309 0:c52df770855b 59 Function-like macros are used to allow more efficient code.
jhon309 0:c52df770855b 60 */
jhon309 0:c52df770855b 61
jhon309 0:c52df770855b 62
jhon309 0:c52df770855b 63 /*******************************************************************************
jhon309 0:c52df770855b 64 * CMSIS definitions
jhon309 0:c52df770855b 65 ******************************************************************************/
jhon309 0:c52df770855b 66 /** \ingroup Cortex-M0+
jhon309 0:c52df770855b 67 @{
jhon309 0:c52df770855b 68 */
jhon309 0:c52df770855b 69
jhon309 0:c52df770855b 70 /* CMSIS CM0P definitions */
jhon309 0:c52df770855b 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
jhon309 0:c52df770855b 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
jhon309 0:c52df770855b 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
jhon309 0:c52df770855b 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
jhon309 0:c52df770855b 75
jhon309 0:c52df770855b 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
jhon309 0:c52df770855b 77
jhon309 0:c52df770855b 78
jhon309 0:c52df770855b 79 #if defined ( __CC_ARM )
jhon309 0:c52df770855b 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
jhon309 0:c52df770855b 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
jhon309 0:c52df770855b 82 #define __STATIC_INLINE static __inline
jhon309 0:c52df770855b 83
jhon309 0:c52df770855b 84 #elif defined ( __ICCARM__ )
jhon309 0:c52df770855b 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
jhon309 0:c52df770855b 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
jhon309 0:c52df770855b 87 #define __STATIC_INLINE static inline
jhon309 0:c52df770855b 88
jhon309 0:c52df770855b 89 #elif defined ( __GNUC__ )
jhon309 0:c52df770855b 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
jhon309 0:c52df770855b 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
jhon309 0:c52df770855b 92 #define __STATIC_INLINE static inline
jhon309 0:c52df770855b 93
jhon309 0:c52df770855b 94 #elif defined ( __TASKING__ )
jhon309 0:c52df770855b 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
jhon309 0:c52df770855b 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
jhon309 0:c52df770855b 97 #define __STATIC_INLINE static inline
jhon309 0:c52df770855b 98
jhon309 0:c52df770855b 99 #endif
jhon309 0:c52df770855b 100
jhon309 0:c52df770855b 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
jhon309 0:c52df770855b 102 */
jhon309 0:c52df770855b 103 #define __FPU_USED 0
jhon309 0:c52df770855b 104
jhon309 0:c52df770855b 105 #if defined ( __CC_ARM )
jhon309 0:c52df770855b 106 #if defined __TARGET_FPU_VFP
jhon309 0:c52df770855b 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:c52df770855b 108 #endif
jhon309 0:c52df770855b 109
jhon309 0:c52df770855b 110 #elif defined ( __ICCARM__ )
jhon309 0:c52df770855b 111 #if defined __ARMVFP__
jhon309 0:c52df770855b 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:c52df770855b 113 #endif
jhon309 0:c52df770855b 114
jhon309 0:c52df770855b 115 #elif defined ( __GNUC__ )
jhon309 0:c52df770855b 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
jhon309 0:c52df770855b 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:c52df770855b 118 #endif
jhon309 0:c52df770855b 119
jhon309 0:c52df770855b 120 #elif defined ( __TASKING__ )
jhon309 0:c52df770855b 121 #if defined __FPU_VFP__
jhon309 0:c52df770855b 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:c52df770855b 123 #endif
jhon309 0:c52df770855b 124 #endif
jhon309 0:c52df770855b 125
jhon309 0:c52df770855b 126 #include <stdint.h> /* standard types definitions */
jhon309 0:c52df770855b 127 #include <core_cmInstr.h> /* Core Instruction Access */
jhon309 0:c52df770855b 128 #include <core_cmFunc.h> /* Core Function Access */
jhon309 0:c52df770855b 129
jhon309 0:c52df770855b 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
jhon309 0:c52df770855b 131
jhon309 0:c52df770855b 132 #ifndef __CMSIS_GENERIC
jhon309 0:c52df770855b 133
jhon309 0:c52df770855b 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
jhon309 0:c52df770855b 135 #define __CORE_CM0PLUS_H_DEPENDANT
jhon309 0:c52df770855b 136
jhon309 0:c52df770855b 137 /* check device defines and use defaults */
jhon309 0:c52df770855b 138 #if defined __CHECK_DEVICE_DEFINES
jhon309 0:c52df770855b 139 #ifndef __CM0PLUS_REV
jhon309 0:c52df770855b 140 #define __CM0PLUS_REV 0x0000
jhon309 0:c52df770855b 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
jhon309 0:c52df770855b 142 #endif
jhon309 0:c52df770855b 143
jhon309 0:c52df770855b 144 #ifndef __MPU_PRESENT
jhon309 0:c52df770855b 145 #define __MPU_PRESENT 0
jhon309 0:c52df770855b 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
jhon309 0:c52df770855b 147 #endif
jhon309 0:c52df770855b 148
jhon309 0:c52df770855b 149 #ifndef __VTOR_PRESENT
jhon309 0:c52df770855b 150 #define __VTOR_PRESENT 0
jhon309 0:c52df770855b 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
jhon309 0:c52df770855b 152 #endif
jhon309 0:c52df770855b 153
jhon309 0:c52df770855b 154 #ifndef __NVIC_PRIO_BITS
jhon309 0:c52df770855b 155 #define __NVIC_PRIO_BITS 2
jhon309 0:c52df770855b 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
jhon309 0:c52df770855b 157 #endif
jhon309 0:c52df770855b 158
jhon309 0:c52df770855b 159 #ifndef __Vendor_SysTickConfig
jhon309 0:c52df770855b 160 #define __Vendor_SysTickConfig 0
jhon309 0:c52df770855b 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
jhon309 0:c52df770855b 162 #endif
jhon309 0:c52df770855b 163 #endif
jhon309 0:c52df770855b 164
jhon309 0:c52df770855b 165 /* IO definitions (access restrictions to peripheral registers) */
jhon309 0:c52df770855b 166 /**
jhon309 0:c52df770855b 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
jhon309 0:c52df770855b 168
jhon309 0:c52df770855b 169 <strong>IO Type Qualifiers</strong> are used
jhon309 0:c52df770855b 170 \li to specify the access to peripheral variables.
jhon309 0:c52df770855b 171 \li for automatic generation of peripheral register debug information.
jhon309 0:c52df770855b 172 */
jhon309 0:c52df770855b 173 #ifdef __cplusplus
jhon309 0:c52df770855b 174 #define __I volatile /*!< Defines 'read only' permissions */
jhon309 0:c52df770855b 175 #else
jhon309 0:c52df770855b 176 #define __I volatile const /*!< Defines 'read only' permissions */
jhon309 0:c52df770855b 177 #endif
jhon309 0:c52df770855b 178 #define __O volatile /*!< Defines 'write only' permissions */
jhon309 0:c52df770855b 179 #define __IO volatile /*!< Defines 'read / write' permissions */
jhon309 0:c52df770855b 180
jhon309 0:c52df770855b 181 /*@} end of group Cortex-M0+ */
jhon309 0:c52df770855b 182
jhon309 0:c52df770855b 183
jhon309 0:c52df770855b 184
jhon309 0:c52df770855b 185 /*******************************************************************************
jhon309 0:c52df770855b 186 * Register Abstraction
jhon309 0:c52df770855b 187 Core Register contain:
jhon309 0:c52df770855b 188 - Core Register
jhon309 0:c52df770855b 189 - Core NVIC Register
jhon309 0:c52df770855b 190 - Core SCB Register
jhon309 0:c52df770855b 191 - Core SysTick Register
jhon309 0:c52df770855b 192 - Core MPU Register
jhon309 0:c52df770855b 193 ******************************************************************************/
jhon309 0:c52df770855b 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
jhon309 0:c52df770855b 195 \brief Type definitions and defines for Cortex-M processor based devices.
jhon309 0:c52df770855b 196 */
jhon309 0:c52df770855b 197
jhon309 0:c52df770855b 198 /** \ingroup CMSIS_core_register
jhon309 0:c52df770855b 199 \defgroup CMSIS_CORE Status and Control Registers
jhon309 0:c52df770855b 200 \brief Core Register type definitions.
jhon309 0:c52df770855b 201 @{
jhon309 0:c52df770855b 202 */
jhon309 0:c52df770855b 203
jhon309 0:c52df770855b 204 /** \brief Union type to access the Application Program Status Register (APSR).
jhon309 0:c52df770855b 205 */
jhon309 0:c52df770855b 206 typedef union
jhon309 0:c52df770855b 207 {
jhon309 0:c52df770855b 208 struct
jhon309 0:c52df770855b 209 {
jhon309 0:c52df770855b 210 #if (__CORTEX_M != 0x04)
jhon309 0:c52df770855b 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
jhon309 0:c52df770855b 212 #else
jhon309 0:c52df770855b 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
jhon309 0:c52df770855b 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
jhon309 0:c52df770855b 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
jhon309 0:c52df770855b 216 #endif
jhon309 0:c52df770855b 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
jhon309 0:c52df770855b 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
jhon309 0:c52df770855b 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
jhon309 0:c52df770855b 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
jhon309 0:c52df770855b 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
jhon309 0:c52df770855b 222 } b; /*!< Structure used for bit access */
jhon309 0:c52df770855b 223 uint32_t w; /*!< Type used for word access */
jhon309 0:c52df770855b 224 } APSR_Type;
jhon309 0:c52df770855b 225
jhon309 0:c52df770855b 226
jhon309 0:c52df770855b 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
jhon309 0:c52df770855b 228 */
jhon309 0:c52df770855b 229 typedef union
jhon309 0:c52df770855b 230 {
jhon309 0:c52df770855b 231 struct
jhon309 0:c52df770855b 232 {
jhon309 0:c52df770855b 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
jhon309 0:c52df770855b 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
jhon309 0:c52df770855b 235 } b; /*!< Structure used for bit access */
jhon309 0:c52df770855b 236 uint32_t w; /*!< Type used for word access */
jhon309 0:c52df770855b 237 } IPSR_Type;
jhon309 0:c52df770855b 238
jhon309 0:c52df770855b 239
jhon309 0:c52df770855b 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
jhon309 0:c52df770855b 241 */
jhon309 0:c52df770855b 242 typedef union
jhon309 0:c52df770855b 243 {
jhon309 0:c52df770855b 244 struct
jhon309 0:c52df770855b 245 {
jhon309 0:c52df770855b 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
jhon309 0:c52df770855b 247 #if (__CORTEX_M != 0x04)
jhon309 0:c52df770855b 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
jhon309 0:c52df770855b 249 #else
jhon309 0:c52df770855b 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
jhon309 0:c52df770855b 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
jhon309 0:c52df770855b 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
jhon309 0:c52df770855b 253 #endif
jhon309 0:c52df770855b 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
jhon309 0:c52df770855b 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
jhon309 0:c52df770855b 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
jhon309 0:c52df770855b 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
jhon309 0:c52df770855b 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
jhon309 0:c52df770855b 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
jhon309 0:c52df770855b 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
jhon309 0:c52df770855b 261 } b; /*!< Structure used for bit access */
jhon309 0:c52df770855b 262 uint32_t w; /*!< Type used for word access */
jhon309 0:c52df770855b 263 } xPSR_Type;
jhon309 0:c52df770855b 264
jhon309 0:c52df770855b 265
jhon309 0:c52df770855b 266 /** \brief Union type to access the Control Registers (CONTROL).
jhon309 0:c52df770855b 267 */
jhon309 0:c52df770855b 268 typedef union
jhon309 0:c52df770855b 269 {
jhon309 0:c52df770855b 270 struct
jhon309 0:c52df770855b 271 {
jhon309 0:c52df770855b 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
jhon309 0:c52df770855b 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
jhon309 0:c52df770855b 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
jhon309 0:c52df770855b 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
jhon309 0:c52df770855b 276 } b; /*!< Structure used for bit access */
jhon309 0:c52df770855b 277 uint32_t w; /*!< Type used for word access */
jhon309 0:c52df770855b 278 } CONTROL_Type;
jhon309 0:c52df770855b 279
jhon309 0:c52df770855b 280 /*@} end of group CMSIS_CORE */
jhon309 0:c52df770855b 281
jhon309 0:c52df770855b 282
jhon309 0:c52df770855b 283 /** \ingroup CMSIS_core_register
jhon309 0:c52df770855b 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
jhon309 0:c52df770855b 285 \brief Type definitions for the NVIC Registers
jhon309 0:c52df770855b 286 @{
jhon309 0:c52df770855b 287 */
jhon309 0:c52df770855b 288
jhon309 0:c52df770855b 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
jhon309 0:c52df770855b 290 */
jhon309 0:c52df770855b 291 typedef struct
jhon309 0:c52df770855b 292 {
jhon309 0:c52df770855b 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
jhon309 0:c52df770855b 294 uint32_t RESERVED0[31];
jhon309 0:c52df770855b 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
jhon309 0:c52df770855b 296 uint32_t RSERVED1[31];
jhon309 0:c52df770855b 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
jhon309 0:c52df770855b 298 uint32_t RESERVED2[31];
jhon309 0:c52df770855b 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
jhon309 0:c52df770855b 300 uint32_t RESERVED3[31];
jhon309 0:c52df770855b 301 uint32_t RESERVED4[64];
jhon309 0:c52df770855b 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
jhon309 0:c52df770855b 303 } NVIC_Type;
jhon309 0:c52df770855b 304
jhon309 0:c52df770855b 305 /*@} end of group CMSIS_NVIC */
jhon309 0:c52df770855b 306
jhon309 0:c52df770855b 307
jhon309 0:c52df770855b 308 /** \ingroup CMSIS_core_register
jhon309 0:c52df770855b 309 \defgroup CMSIS_SCB System Control Block (SCB)
jhon309 0:c52df770855b 310 \brief Type definitions for the System Control Block Registers
jhon309 0:c52df770855b 311 @{
jhon309 0:c52df770855b 312 */
jhon309 0:c52df770855b 313
jhon309 0:c52df770855b 314 /** \brief Structure type to access the System Control Block (SCB).
jhon309 0:c52df770855b 315 */
jhon309 0:c52df770855b 316 typedef struct
jhon309 0:c52df770855b 317 {
jhon309 0:c52df770855b 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
jhon309 0:c52df770855b 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
jhon309 0:c52df770855b 320 #if (__VTOR_PRESENT == 1)
jhon309 0:c52df770855b 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
jhon309 0:c52df770855b 322 #else
jhon309 0:c52df770855b 323 uint32_t RESERVED0;
jhon309 0:c52df770855b 324 #endif
jhon309 0:c52df770855b 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
jhon309 0:c52df770855b 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
jhon309 0:c52df770855b 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
jhon309 0:c52df770855b 328 uint32_t RESERVED1;
jhon309 0:c52df770855b 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
jhon309 0:c52df770855b 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
jhon309 0:c52df770855b 331 } SCB_Type;
jhon309 0:c52df770855b 332
jhon309 0:c52df770855b 333 /* SCB CPUID Register Definitions */
jhon309 0:c52df770855b 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
jhon309 0:c52df770855b 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
jhon309 0:c52df770855b 336
jhon309 0:c52df770855b 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
jhon309 0:c52df770855b 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
jhon309 0:c52df770855b 339
jhon309 0:c52df770855b 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
jhon309 0:c52df770855b 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
jhon309 0:c52df770855b 342
jhon309 0:c52df770855b 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
jhon309 0:c52df770855b 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
jhon309 0:c52df770855b 345
jhon309 0:c52df770855b 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
jhon309 0:c52df770855b 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
jhon309 0:c52df770855b 348
jhon309 0:c52df770855b 349 /* SCB Interrupt Control State Register Definitions */
jhon309 0:c52df770855b 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
jhon309 0:c52df770855b 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
jhon309 0:c52df770855b 352
jhon309 0:c52df770855b 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
jhon309 0:c52df770855b 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
jhon309 0:c52df770855b 355
jhon309 0:c52df770855b 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
jhon309 0:c52df770855b 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
jhon309 0:c52df770855b 358
jhon309 0:c52df770855b 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
jhon309 0:c52df770855b 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
jhon309 0:c52df770855b 361
jhon309 0:c52df770855b 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
jhon309 0:c52df770855b 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
jhon309 0:c52df770855b 364
jhon309 0:c52df770855b 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
jhon309 0:c52df770855b 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
jhon309 0:c52df770855b 367
jhon309 0:c52df770855b 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
jhon309 0:c52df770855b 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
jhon309 0:c52df770855b 370
jhon309 0:c52df770855b 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
jhon309 0:c52df770855b 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
jhon309 0:c52df770855b 373
jhon309 0:c52df770855b 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
jhon309 0:c52df770855b 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
jhon309 0:c52df770855b 376
jhon309 0:c52df770855b 377 #if (__VTOR_PRESENT == 1)
jhon309 0:c52df770855b 378 /* SCB Interrupt Control State Register Definitions */
jhon309 0:c52df770855b 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
jhon309 0:c52df770855b 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
jhon309 0:c52df770855b 381 #endif
jhon309 0:c52df770855b 382
jhon309 0:c52df770855b 383 /* SCB Application Interrupt and Reset Control Register Definitions */
jhon309 0:c52df770855b 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
jhon309 0:c52df770855b 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
jhon309 0:c52df770855b 386
jhon309 0:c52df770855b 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
jhon309 0:c52df770855b 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
jhon309 0:c52df770855b 389
jhon309 0:c52df770855b 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
jhon309 0:c52df770855b 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
jhon309 0:c52df770855b 392
jhon309 0:c52df770855b 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
jhon309 0:c52df770855b 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
jhon309 0:c52df770855b 395
jhon309 0:c52df770855b 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
jhon309 0:c52df770855b 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
jhon309 0:c52df770855b 398
jhon309 0:c52df770855b 399 /* SCB System Control Register Definitions */
jhon309 0:c52df770855b 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
jhon309 0:c52df770855b 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
jhon309 0:c52df770855b 402
jhon309 0:c52df770855b 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
jhon309 0:c52df770855b 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
jhon309 0:c52df770855b 405
jhon309 0:c52df770855b 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
jhon309 0:c52df770855b 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
jhon309 0:c52df770855b 408
jhon309 0:c52df770855b 409 /* SCB Configuration Control Register Definitions */
jhon309 0:c52df770855b 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
jhon309 0:c52df770855b 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
jhon309 0:c52df770855b 412
jhon309 0:c52df770855b 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
jhon309 0:c52df770855b 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
jhon309 0:c52df770855b 415
jhon309 0:c52df770855b 416 /* SCB System Handler Control and State Register Definitions */
jhon309 0:c52df770855b 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
jhon309 0:c52df770855b 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
jhon309 0:c52df770855b 419
jhon309 0:c52df770855b 420 /*@} end of group CMSIS_SCB */
jhon309 0:c52df770855b 421
jhon309 0:c52df770855b 422
jhon309 0:c52df770855b 423 /** \ingroup CMSIS_core_register
jhon309 0:c52df770855b 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
jhon309 0:c52df770855b 425 \brief Type definitions for the System Timer Registers.
jhon309 0:c52df770855b 426 @{
jhon309 0:c52df770855b 427 */
jhon309 0:c52df770855b 428
jhon309 0:c52df770855b 429 /** \brief Structure type to access the System Timer (SysTick).
jhon309 0:c52df770855b 430 */
jhon309 0:c52df770855b 431 typedef struct
jhon309 0:c52df770855b 432 {
jhon309 0:c52df770855b 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
jhon309 0:c52df770855b 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
jhon309 0:c52df770855b 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
jhon309 0:c52df770855b 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
jhon309 0:c52df770855b 437 } SysTick_Type;
jhon309 0:c52df770855b 438
jhon309 0:c52df770855b 439 /* SysTick Control / Status Register Definitions */
jhon309 0:c52df770855b 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
jhon309 0:c52df770855b 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
jhon309 0:c52df770855b 442
jhon309 0:c52df770855b 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
jhon309 0:c52df770855b 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
jhon309 0:c52df770855b 445
jhon309 0:c52df770855b 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
jhon309 0:c52df770855b 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
jhon309 0:c52df770855b 448
jhon309 0:c52df770855b 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
jhon309 0:c52df770855b 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
jhon309 0:c52df770855b 451
jhon309 0:c52df770855b 452 /* SysTick Reload Register Definitions */
jhon309 0:c52df770855b 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
jhon309 0:c52df770855b 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
jhon309 0:c52df770855b 455
jhon309 0:c52df770855b 456 /* SysTick Current Register Definitions */
jhon309 0:c52df770855b 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
jhon309 0:c52df770855b 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
jhon309 0:c52df770855b 459
jhon309 0:c52df770855b 460 /* SysTick Calibration Register Definitions */
jhon309 0:c52df770855b 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
jhon309 0:c52df770855b 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
jhon309 0:c52df770855b 463
jhon309 0:c52df770855b 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
jhon309 0:c52df770855b 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
jhon309 0:c52df770855b 466
jhon309 0:c52df770855b 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
jhon309 0:c52df770855b 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
jhon309 0:c52df770855b 469
jhon309 0:c52df770855b 470 /*@} end of group CMSIS_SysTick */
jhon309 0:c52df770855b 471
jhon309 0:c52df770855b 472 #if (__MPU_PRESENT == 1)
jhon309 0:c52df770855b 473 /** \ingroup CMSIS_core_register
jhon309 0:c52df770855b 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
jhon309 0:c52df770855b 475 \brief Type definitions for the Memory Protection Unit (MPU)
jhon309 0:c52df770855b 476 @{
jhon309 0:c52df770855b 477 */
jhon309 0:c52df770855b 478
jhon309 0:c52df770855b 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
jhon309 0:c52df770855b 480 */
jhon309 0:c52df770855b 481 typedef struct
jhon309 0:c52df770855b 482 {
jhon309 0:c52df770855b 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
jhon309 0:c52df770855b 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
jhon309 0:c52df770855b 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
jhon309 0:c52df770855b 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
jhon309 0:c52df770855b 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
jhon309 0:c52df770855b 488 } MPU_Type;
jhon309 0:c52df770855b 489
jhon309 0:c52df770855b 490 /* MPU Type Register */
jhon309 0:c52df770855b 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
jhon309 0:c52df770855b 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
jhon309 0:c52df770855b 493
jhon309 0:c52df770855b 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
jhon309 0:c52df770855b 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
jhon309 0:c52df770855b 496
jhon309 0:c52df770855b 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
jhon309 0:c52df770855b 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
jhon309 0:c52df770855b 499
jhon309 0:c52df770855b 500 /* MPU Control Register */
jhon309 0:c52df770855b 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
jhon309 0:c52df770855b 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
jhon309 0:c52df770855b 503
jhon309 0:c52df770855b 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
jhon309 0:c52df770855b 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
jhon309 0:c52df770855b 506
jhon309 0:c52df770855b 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
jhon309 0:c52df770855b 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
jhon309 0:c52df770855b 509
jhon309 0:c52df770855b 510 /* MPU Region Number Register */
jhon309 0:c52df770855b 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
jhon309 0:c52df770855b 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
jhon309 0:c52df770855b 513
jhon309 0:c52df770855b 514 /* MPU Region Base Address Register */
jhon309 0:c52df770855b 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
jhon309 0:c52df770855b 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
jhon309 0:c52df770855b 517
jhon309 0:c52df770855b 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
jhon309 0:c52df770855b 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
jhon309 0:c52df770855b 520
jhon309 0:c52df770855b 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
jhon309 0:c52df770855b 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
jhon309 0:c52df770855b 523
jhon309 0:c52df770855b 524 /* MPU Region Attribute and Size Register */
jhon309 0:c52df770855b 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
jhon309 0:c52df770855b 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
jhon309 0:c52df770855b 527
jhon309 0:c52df770855b 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
jhon309 0:c52df770855b 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
jhon309 0:c52df770855b 530
jhon309 0:c52df770855b 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
jhon309 0:c52df770855b 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
jhon309 0:c52df770855b 533
jhon309 0:c52df770855b 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
jhon309 0:c52df770855b 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
jhon309 0:c52df770855b 536
jhon309 0:c52df770855b 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
jhon309 0:c52df770855b 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
jhon309 0:c52df770855b 539
jhon309 0:c52df770855b 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
jhon309 0:c52df770855b 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
jhon309 0:c52df770855b 542
jhon309 0:c52df770855b 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
jhon309 0:c52df770855b 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
jhon309 0:c52df770855b 545
jhon309 0:c52df770855b 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
jhon309 0:c52df770855b 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
jhon309 0:c52df770855b 548
jhon309 0:c52df770855b 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
jhon309 0:c52df770855b 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
jhon309 0:c52df770855b 551
jhon309 0:c52df770855b 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
jhon309 0:c52df770855b 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
jhon309 0:c52df770855b 554
jhon309 0:c52df770855b 555 /*@} end of group CMSIS_MPU */
jhon309 0:c52df770855b 556 #endif
jhon309 0:c52df770855b 557
jhon309 0:c52df770855b 558
jhon309 0:c52df770855b 559 /** \ingroup CMSIS_core_register
jhon309 0:c52df770855b 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
jhon309 0:c52df770855b 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
jhon309 0:c52df770855b 562 are only accessible over DAP and not via processor. Therefore
jhon309 0:c52df770855b 563 they are not covered by the Cortex-M0 header file.
jhon309 0:c52df770855b 564 @{
jhon309 0:c52df770855b 565 */
jhon309 0:c52df770855b 566 /*@} end of group CMSIS_CoreDebug */
jhon309 0:c52df770855b 567
jhon309 0:c52df770855b 568
jhon309 0:c52df770855b 569 /** \ingroup CMSIS_core_register
jhon309 0:c52df770855b 570 \defgroup CMSIS_core_base Core Definitions
jhon309 0:c52df770855b 571 \brief Definitions for base addresses, unions, and structures.
jhon309 0:c52df770855b 572 @{
jhon309 0:c52df770855b 573 */
jhon309 0:c52df770855b 574
jhon309 0:c52df770855b 575 /* Memory mapping of Cortex-M0+ Hardware */
jhon309 0:c52df770855b 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
jhon309 0:c52df770855b 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
jhon309 0:c52df770855b 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
jhon309 0:c52df770855b 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
jhon309 0:c52df770855b 580
jhon309 0:c52df770855b 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
jhon309 0:c52df770855b 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
jhon309 0:c52df770855b 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
jhon309 0:c52df770855b 584
jhon309 0:c52df770855b 585 #if (__MPU_PRESENT == 1)
jhon309 0:c52df770855b 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
jhon309 0:c52df770855b 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
jhon309 0:c52df770855b 588 #endif
jhon309 0:c52df770855b 589
jhon309 0:c52df770855b 590 /*@} */
jhon309 0:c52df770855b 591
jhon309 0:c52df770855b 592
jhon309 0:c52df770855b 593
jhon309 0:c52df770855b 594 /*******************************************************************************
jhon309 0:c52df770855b 595 * Hardware Abstraction Layer
jhon309 0:c52df770855b 596 Core Function Interface contains:
jhon309 0:c52df770855b 597 - Core NVIC Functions
jhon309 0:c52df770855b 598 - Core SysTick Functions
jhon309 0:c52df770855b 599 - Core Register Access Functions
jhon309 0:c52df770855b 600 ******************************************************************************/
jhon309 0:c52df770855b 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
jhon309 0:c52df770855b 602 */
jhon309 0:c52df770855b 603
jhon309 0:c52df770855b 604
jhon309 0:c52df770855b 605
jhon309 0:c52df770855b 606 /* ########################## NVIC functions #################################### */
jhon309 0:c52df770855b 607 /** \ingroup CMSIS_Core_FunctionInterface
jhon309 0:c52df770855b 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
jhon309 0:c52df770855b 609 \brief Functions that manage interrupts and exceptions via the NVIC.
jhon309 0:c52df770855b 610 @{
jhon309 0:c52df770855b 611 */
jhon309 0:c52df770855b 612
jhon309 0:c52df770855b 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
jhon309 0:c52df770855b 614 /* The following MACROS handle generation of the register offset and byte masks */
jhon309 0:c52df770855b 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
jhon309 0:c52df770855b 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
jhon309 0:c52df770855b 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
jhon309 0:c52df770855b 618
jhon309 0:c52df770855b 619
jhon309 0:c52df770855b 620 /** \brief Enable External Interrupt
jhon309 0:c52df770855b 621
jhon309 0:c52df770855b 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
jhon309 0:c52df770855b 623
jhon309 0:c52df770855b 624 \param [in] IRQn External interrupt number. Value cannot be negative.
jhon309 0:c52df770855b 625 */
jhon309 0:c52df770855b 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
jhon309 0:c52df770855b 627 {
jhon309 0:c52df770855b 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
jhon309 0:c52df770855b 629 }
jhon309 0:c52df770855b 630
jhon309 0:c52df770855b 631
jhon309 0:c52df770855b 632 /** \brief Disable External Interrupt
jhon309 0:c52df770855b 633
jhon309 0:c52df770855b 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
jhon309 0:c52df770855b 635
jhon309 0:c52df770855b 636 \param [in] IRQn External interrupt number. Value cannot be negative.
jhon309 0:c52df770855b 637 */
jhon309 0:c52df770855b 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
jhon309 0:c52df770855b 639 {
jhon309 0:c52df770855b 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
jhon309 0:c52df770855b 641 }
jhon309 0:c52df770855b 642
jhon309 0:c52df770855b 643
jhon309 0:c52df770855b 644 /** \brief Get Pending Interrupt
jhon309 0:c52df770855b 645
jhon309 0:c52df770855b 646 The function reads the pending register in the NVIC and returns the pending bit
jhon309 0:c52df770855b 647 for the specified interrupt.
jhon309 0:c52df770855b 648
jhon309 0:c52df770855b 649 \param [in] IRQn Interrupt number.
jhon309 0:c52df770855b 650
jhon309 0:c52df770855b 651 \return 0 Interrupt status is not pending.
jhon309 0:c52df770855b 652 \return 1 Interrupt status is pending.
jhon309 0:c52df770855b 653 */
jhon309 0:c52df770855b 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
jhon309 0:c52df770855b 655 {
jhon309 0:c52df770855b 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
jhon309 0:c52df770855b 657 }
jhon309 0:c52df770855b 658
jhon309 0:c52df770855b 659
jhon309 0:c52df770855b 660 /** \brief Set Pending Interrupt
jhon309 0:c52df770855b 661
jhon309 0:c52df770855b 662 The function sets the pending bit of an external interrupt.
jhon309 0:c52df770855b 663
jhon309 0:c52df770855b 664 \param [in] IRQn Interrupt number. Value cannot be negative.
jhon309 0:c52df770855b 665 */
jhon309 0:c52df770855b 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
jhon309 0:c52df770855b 667 {
jhon309 0:c52df770855b 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
jhon309 0:c52df770855b 669 }
jhon309 0:c52df770855b 670
jhon309 0:c52df770855b 671
jhon309 0:c52df770855b 672 /** \brief Clear Pending Interrupt
jhon309 0:c52df770855b 673
jhon309 0:c52df770855b 674 The function clears the pending bit of an external interrupt.
jhon309 0:c52df770855b 675
jhon309 0:c52df770855b 676 \param [in] IRQn External interrupt number. Value cannot be negative.
jhon309 0:c52df770855b 677 */
jhon309 0:c52df770855b 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
jhon309 0:c52df770855b 679 {
jhon309 0:c52df770855b 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
jhon309 0:c52df770855b 681 }
jhon309 0:c52df770855b 682
jhon309 0:c52df770855b 683
jhon309 0:c52df770855b 684 /** \brief Set Interrupt Priority
jhon309 0:c52df770855b 685
jhon309 0:c52df770855b 686 The function sets the priority of an interrupt.
jhon309 0:c52df770855b 687
jhon309 0:c52df770855b 688 \note The priority cannot be set for every core interrupt.
jhon309 0:c52df770855b 689
jhon309 0:c52df770855b 690 \param [in] IRQn Interrupt number.
jhon309 0:c52df770855b 691 \param [in] priority Priority to set.
jhon309 0:c52df770855b 692 */
jhon309 0:c52df770855b 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
jhon309 0:c52df770855b 694 {
jhon309 0:c52df770855b 695 if(IRQn < 0) {
jhon309 0:c52df770855b 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
jhon309 0:c52df770855b 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
jhon309 0:c52df770855b 698 else {
jhon309 0:c52df770855b 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
jhon309 0:c52df770855b 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
jhon309 0:c52df770855b 701 }
jhon309 0:c52df770855b 702
jhon309 0:c52df770855b 703
jhon309 0:c52df770855b 704 /** \brief Get Interrupt Priority
jhon309 0:c52df770855b 705
jhon309 0:c52df770855b 706 The function reads the priority of an interrupt. The interrupt
jhon309 0:c52df770855b 707 number can be positive to specify an external (device specific)
jhon309 0:c52df770855b 708 interrupt, or negative to specify an internal (core) interrupt.
jhon309 0:c52df770855b 709
jhon309 0:c52df770855b 710
jhon309 0:c52df770855b 711 \param [in] IRQn Interrupt number.
jhon309 0:c52df770855b 712 \return Interrupt Priority. Value is aligned automatically to the implemented
jhon309 0:c52df770855b 713 priority bits of the microcontroller.
jhon309 0:c52df770855b 714 */
jhon309 0:c52df770855b 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
jhon309 0:c52df770855b 716 {
jhon309 0:c52df770855b 717
jhon309 0:c52df770855b 718 if(IRQn < 0) {
jhon309 0:c52df770855b 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
jhon309 0:c52df770855b 720 else {
jhon309 0:c52df770855b 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
jhon309 0:c52df770855b 722 }
jhon309 0:c52df770855b 723
jhon309 0:c52df770855b 724
jhon309 0:c52df770855b 725 /** \brief System Reset
jhon309 0:c52df770855b 726
jhon309 0:c52df770855b 727 The function initiates a system reset request to reset the MCU.
jhon309 0:c52df770855b 728 */
jhon309 0:c52df770855b 729 __STATIC_INLINE void NVIC_SystemReset(void)
jhon309 0:c52df770855b 730 {
jhon309 0:c52df770855b 731 __DSB(); /* Ensure all outstanding memory accesses included
jhon309 0:c52df770855b 732 buffered write are completed before reset */
jhon309 0:c52df770855b 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
jhon309 0:c52df770855b 734 SCB_AIRCR_SYSRESETREQ_Msk);
jhon309 0:c52df770855b 735 __DSB(); /* Ensure completion of memory access */
jhon309 0:c52df770855b 736 while(1); /* wait until reset */
jhon309 0:c52df770855b 737 }
jhon309 0:c52df770855b 738
jhon309 0:c52df770855b 739 /*@} end of CMSIS_Core_NVICFunctions */
jhon309 0:c52df770855b 740
jhon309 0:c52df770855b 741
jhon309 0:c52df770855b 742
jhon309 0:c52df770855b 743 /* ################################## SysTick function ############################################ */
jhon309 0:c52df770855b 744 /** \ingroup CMSIS_Core_FunctionInterface
jhon309 0:c52df770855b 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
jhon309 0:c52df770855b 746 \brief Functions that configure the System.
jhon309 0:c52df770855b 747 @{
jhon309 0:c52df770855b 748 */
jhon309 0:c52df770855b 749
jhon309 0:c52df770855b 750 #if (__Vendor_SysTickConfig == 0)
jhon309 0:c52df770855b 751
jhon309 0:c52df770855b 752 /** \brief System Tick Configuration
jhon309 0:c52df770855b 753
jhon309 0:c52df770855b 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
jhon309 0:c52df770855b 755 Counter is in free running mode to generate periodic interrupts.
jhon309 0:c52df770855b 756
jhon309 0:c52df770855b 757 \param [in] ticks Number of ticks between two interrupts.
jhon309 0:c52df770855b 758
jhon309 0:c52df770855b 759 \return 0 Function succeeded.
jhon309 0:c52df770855b 760 \return 1 Function failed.
jhon309 0:c52df770855b 761
jhon309 0:c52df770855b 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
jhon309 0:c52df770855b 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
jhon309 0:c52df770855b 764 must contain a vendor-specific implementation of this function.
jhon309 0:c52df770855b 765
jhon309 0:c52df770855b 766 */
jhon309 0:c52df770855b 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
jhon309 0:c52df770855b 768 {
jhon309 0:c52df770855b 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
jhon309 0:c52df770855b 770
jhon309 0:c52df770855b 771 SysTick->LOAD = ticks - 1; /* set reload register */
jhon309 0:c52df770855b 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
jhon309 0:c52df770855b 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
jhon309 0:c52df770855b 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
jhon309 0:c52df770855b 775 SysTick_CTRL_TICKINT_Msk |
jhon309 0:c52df770855b 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
jhon309 0:c52df770855b 777 return (0); /* Function successful */
jhon309 0:c52df770855b 778 }
jhon309 0:c52df770855b 779
jhon309 0:c52df770855b 780 #endif
jhon309 0:c52df770855b 781
jhon309 0:c52df770855b 782 /*@} end of CMSIS_Core_SysTickFunctions */
jhon309 0:c52df770855b 783
jhon309 0:c52df770855b 784
jhon309 0:c52df770855b 785
jhon309 0:c52df770855b 786
jhon309 0:c52df770855b 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
jhon309 0:c52df770855b 788
jhon309 0:c52df770855b 789 #endif /* __CMSIS_GENERIC */
jhon309 0:c52df770855b 790
jhon309 0:c52df770855b 791 #ifdef __cplusplus
jhon309 0:c52df770855b 792 }
jhon309 0:c52df770855b 793 #endif