Jhon Plantikow / DHT11

DHT11

TARGET_NUCLEO_F072RB/core_caFunc.h@0:c52df770855b, 2015-08-13 (annotated)

Committer:
jhon309
Date:
Thu Aug 13 00:21:57 2015 +0000
Revision:
0:c52df770855b
DHT11

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jhon309 0:c52df770855b 1 /**************************************************************************//**
jhon309 0:c52df770855b 2 * @file core_caFunc.h
jhon309 0:c52df770855b 3 * @brief CMSIS Cortex-A Core Function Access Header File
jhon309 0:c52df770855b 4 * @version V3.10
jhon309 0:c52df770855b 5 * @date 9 May 2013
jhon309 0:c52df770855b 6 *
jhon309 0:c52df770855b 7 * @note
jhon309 0:c52df770855b 8 *
jhon309 0:c52df770855b 9 ******************************************************************************/
jhon309 0:c52df770855b 10 /* Copyright (c) 2009 - 2012 ARM LIMITED
jhon309 0:c52df770855b 11
jhon309 0:c52df770855b 12 All rights reserved.
jhon309 0:c52df770855b 13 Redistribution and use in source and binary forms, with or without
jhon309 0:c52df770855b 14 modification, are permitted provided that the following conditions are met:
jhon309 0:c52df770855b 15 - Redistributions of source code must retain the above copyright
jhon309 0:c52df770855b 16 notice, this list of conditions and the following disclaimer.
jhon309 0:c52df770855b 17 - Redistributions in binary form must reproduce the above copyright
jhon309 0:c52df770855b 18 notice, this list of conditions and the following disclaimer in the
jhon309 0:c52df770855b 19 documentation and/or other materials provided with the distribution.
jhon309 0:c52df770855b 20 - Neither the name of ARM nor the names of its contributors may be used
jhon309 0:c52df770855b 21 to endorse or promote products derived from this software without
jhon309 0:c52df770855b 22 specific prior written permission.
jhon309 0:c52df770855b 23 *
jhon309 0:c52df770855b 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jhon309 0:c52df770855b 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jhon309 0:c52df770855b 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
jhon309 0:c52df770855b 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
jhon309 0:c52df770855b 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
jhon309 0:c52df770855b 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
jhon309 0:c52df770855b 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
jhon309 0:c52df770855b 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
jhon309 0:c52df770855b 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
jhon309 0:c52df770855b 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
jhon309 0:c52df770855b 34 POSSIBILITY OF SUCH DAMAGE.
jhon309 0:c52df770855b 35 ---------------------------------------------------------------------------*/
jhon309 0:c52df770855b 36
jhon309 0:c52df770855b 37
jhon309 0:c52df770855b 38 #ifndef __CORE_CAFUNC_H__
jhon309 0:c52df770855b 39 #define __CORE_CAFUNC_H__
jhon309 0:c52df770855b 40
jhon309 0:c52df770855b 41
jhon309 0:c52df770855b 42 /* ########################### Core Function Access ########################### */
jhon309 0:c52df770855b 43 /** \ingroup CMSIS_Core_FunctionInterface
jhon309 0:c52df770855b 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
jhon309 0:c52df770855b 45 @{
jhon309 0:c52df770855b 46 */
jhon309 0:c52df770855b 47
jhon309 0:c52df770855b 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
jhon309 0:c52df770855b 49 /* ARM armcc specific functions */
jhon309 0:c52df770855b 50
jhon309 0:c52df770855b 51 #if (__ARMCC_VERSION < 400677)
jhon309 0:c52df770855b 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
jhon309 0:c52df770855b 53 #endif
jhon309 0:c52df770855b 54
jhon309 0:c52df770855b 55 #define MODE_USR 0x10
jhon309 0:c52df770855b 56 #define MODE_FIQ 0x11
jhon309 0:c52df770855b 57 #define MODE_IRQ 0x12
jhon309 0:c52df770855b 58 #define MODE_SVC 0x13
jhon309 0:c52df770855b 59 #define MODE_MON 0x16
jhon309 0:c52df770855b 60 #define MODE_ABT 0x17
jhon309 0:c52df770855b 61 #define MODE_HYP 0x1A
jhon309 0:c52df770855b 62 #define MODE_UND 0x1B
jhon309 0:c52df770855b 63 #define MODE_SYS 0x1F
jhon309 0:c52df770855b 64
jhon309 0:c52df770855b 65 /** \brief Get APSR Register
jhon309 0:c52df770855b 66
jhon309 0:c52df770855b 67 This function returns the content of the APSR Register.
jhon309 0:c52df770855b 68
jhon309 0:c52df770855b 69 \return APSR Register value
jhon309 0:c52df770855b 70 */
jhon309 0:c52df770855b 71 __STATIC_INLINE uint32_t __get_APSR(void)
jhon309 0:c52df770855b 72 {
jhon309 0:c52df770855b 73 register uint32_t __regAPSR __ASM("apsr");
jhon309 0:c52df770855b 74 return(__regAPSR);
jhon309 0:c52df770855b 75 }
jhon309 0:c52df770855b 76
jhon309 0:c52df770855b 77
jhon309 0:c52df770855b 78 /** \brief Get CPSR Register
jhon309 0:c52df770855b 79
jhon309 0:c52df770855b 80 This function returns the content of the CPSR Register.
jhon309 0:c52df770855b 81
jhon309 0:c52df770855b 82 \return CPSR Register value
jhon309 0:c52df770855b 83 */
jhon309 0:c52df770855b 84 __STATIC_INLINE uint32_t __get_CPSR(void)
jhon309 0:c52df770855b 85 {
jhon309 0:c52df770855b 86 register uint32_t __regCPSR __ASM("cpsr");
jhon309 0:c52df770855b 87 return(__regCPSR);
jhon309 0:c52df770855b 88 }
jhon309 0:c52df770855b 89
jhon309 0:c52df770855b 90 /** \brief Set Stack Pointer
jhon309 0:c52df770855b 91
jhon309 0:c52df770855b 92 This function assigns the given value to the current stack pointer.
jhon309 0:c52df770855b 93
jhon309 0:c52df770855b 94 \param [in] topOfStack Stack Pointer value to set
jhon309 0:c52df770855b 95 */
jhon309 0:c52df770855b 96 register uint32_t __regSP __ASM("sp");
jhon309 0:c52df770855b 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
jhon309 0:c52df770855b 98 {
jhon309 0:c52df770855b 99 __regSP = topOfStack;
jhon309 0:c52df770855b 100 }
jhon309 0:c52df770855b 101
jhon309 0:c52df770855b 102
jhon309 0:c52df770855b 103 /** \brief Get link register
jhon309 0:c52df770855b 104
jhon309 0:c52df770855b 105 This function returns the value of the link register
jhon309 0:c52df770855b 106
jhon309 0:c52df770855b 107 \return Value of link register
jhon309 0:c52df770855b 108 */
jhon309 0:c52df770855b 109 register uint32_t __reglr __ASM("lr");
jhon309 0:c52df770855b 110 __STATIC_INLINE uint32_t __get_LR(void)
jhon309 0:c52df770855b 111 {
jhon309 0:c52df770855b 112 return(__reglr);
jhon309 0:c52df770855b 113 }
jhon309 0:c52df770855b 114
jhon309 0:c52df770855b 115 /** \brief Set link register
jhon309 0:c52df770855b 116
jhon309 0:c52df770855b 117 This function sets the value of the link register
jhon309 0:c52df770855b 118
jhon309 0:c52df770855b 119 \param [in] lr LR value to set
jhon309 0:c52df770855b 120 */
jhon309 0:c52df770855b 121 __STATIC_INLINE void __set_LR(uint32_t lr)
jhon309 0:c52df770855b 122 {
jhon309 0:c52df770855b 123 __reglr = lr;
jhon309 0:c52df770855b 124 }
jhon309 0:c52df770855b 125
jhon309 0:c52df770855b 126 /** \brief Set Process Stack Pointer
jhon309 0:c52df770855b 127
jhon309 0:c52df770855b 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
jhon309 0:c52df770855b 129
jhon309 0:c52df770855b 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
jhon309 0:c52df770855b 131 */
jhon309 0:c52df770855b 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
jhon309 0:c52df770855b 133 {
jhon309 0:c52df770855b 134 ARM
jhon309 0:c52df770855b 135 PRESERVE8
jhon309 0:c52df770855b 136
jhon309 0:c52df770855b 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
jhon309 0:c52df770855b 138 MRS R1, CPSR
jhon309 0:c52df770855b 139 CPS #MODE_SYS ;no effect in USR mode
jhon309 0:c52df770855b 140 MOV SP, R0
jhon309 0:c52df770855b 141 MSR CPSR_c, R1 ;no effect in USR mode
jhon309 0:c52df770855b 142 ISB
jhon309 0:c52df770855b 143 BX LR
jhon309 0:c52df770855b 144
jhon309 0:c52df770855b 145 }
jhon309 0:c52df770855b 146
jhon309 0:c52df770855b 147 /** \brief Set User Mode
jhon309 0:c52df770855b 148
jhon309 0:c52df770855b 149 This function changes the processor state to User Mode
jhon309 0:c52df770855b 150
jhon309 0:c52df770855b 151 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
jhon309 0:c52df770855b 152 */
jhon309 0:c52df770855b 153 __STATIC_ASM void __set_CPS_USR(void)
jhon309 0:c52df770855b 154 {
jhon309 0:c52df770855b 155 ARM
jhon309 0:c52df770855b 156
jhon309 0:c52df770855b 157 CPS #MODE_USR
jhon309 0:c52df770855b 158 BX LR
jhon309 0:c52df770855b 159 }
jhon309 0:c52df770855b 160
jhon309 0:c52df770855b 161
jhon309 0:c52df770855b 162 /** \brief Enable FIQ
jhon309 0:c52df770855b 163
jhon309 0:c52df770855b 164 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
jhon309 0:c52df770855b 165 Can only be executed in Privileged modes.
jhon309 0:c52df770855b 166 */
jhon309 0:c52df770855b 167 #define __enable_fault_irq __enable_fiq
jhon309 0:c52df770855b 168
jhon309 0:c52df770855b 169
jhon309 0:c52df770855b 170 /** \brief Disable FIQ
jhon309 0:c52df770855b 171
jhon309 0:c52df770855b 172 This function disables FIQ interrupts by setting the F-bit in the CPSR.
jhon309 0:c52df770855b 173 Can only be executed in Privileged modes.
jhon309 0:c52df770855b 174 */
jhon309 0:c52df770855b 175 #define __disable_fault_irq __disable_fiq
jhon309 0:c52df770855b 176
jhon309 0:c52df770855b 177
jhon309 0:c52df770855b 178 /** \brief Get FPSCR
jhon309 0:c52df770855b 179
jhon309 0:c52df770855b 180 This function returns the current value of the Floating Point Status/Control register.
jhon309 0:c52df770855b 181
jhon309 0:c52df770855b 182 \return Floating Point Status/Control register value
jhon309 0:c52df770855b 183 */
jhon309 0:c52df770855b 184 __STATIC_INLINE uint32_t __get_FPSCR(void)
jhon309 0:c52df770855b 185 {
jhon309 0:c52df770855b 186 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jhon309 0:c52df770855b 187 register uint32_t __regfpscr __ASM("fpscr");
jhon309 0:c52df770855b 188 return(__regfpscr);
jhon309 0:c52df770855b 189 #else
jhon309 0:c52df770855b 190 return(0);
jhon309 0:c52df770855b 191 #endif
jhon309 0:c52df770855b 192 }
jhon309 0:c52df770855b 193
jhon309 0:c52df770855b 194
jhon309 0:c52df770855b 195 /** \brief Set FPSCR
jhon309 0:c52df770855b 196
jhon309 0:c52df770855b 197 This function assigns the given value to the Floating Point Status/Control register.
jhon309 0:c52df770855b 198
jhon309 0:c52df770855b 199 \param [in] fpscr Floating Point Status/Control value to set
jhon309 0:c52df770855b 200 */
jhon309 0:c52df770855b 201 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
jhon309 0:c52df770855b 202 {
jhon309 0:c52df770855b 203 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jhon309 0:c52df770855b 204 register uint32_t __regfpscr __ASM("fpscr");
jhon309 0:c52df770855b 205 __regfpscr = (fpscr);
jhon309 0:c52df770855b 206 #endif
jhon309 0:c52df770855b 207 }
jhon309 0:c52df770855b 208
jhon309 0:c52df770855b 209 /** \brief Get FPEXC
jhon309 0:c52df770855b 210
jhon309 0:c52df770855b 211 This function returns the current value of the Floating Point Exception Control register.
jhon309 0:c52df770855b 212
jhon309 0:c52df770855b 213 \return Floating Point Exception Control register value
jhon309 0:c52df770855b 214 */
jhon309 0:c52df770855b 215 __STATIC_INLINE uint32_t __get_FPEXC(void)
jhon309 0:c52df770855b 216 {
jhon309 0:c52df770855b 217 #if (__FPU_PRESENT == 1)
jhon309 0:c52df770855b 218 register uint32_t __regfpexc __ASM("fpexc");
jhon309 0:c52df770855b 219 return(__regfpexc);
jhon309 0:c52df770855b 220 #else
jhon309 0:c52df770855b 221 return(0);
jhon309 0:c52df770855b 222 #endif
jhon309 0:c52df770855b 223 }
jhon309 0:c52df770855b 224
jhon309 0:c52df770855b 225
jhon309 0:c52df770855b 226 /** \brief Set FPEXC
jhon309 0:c52df770855b 227
jhon309 0:c52df770855b 228 This function assigns the given value to the Floating Point Exception Control register.
jhon309 0:c52df770855b 229
jhon309 0:c52df770855b 230 \param [in] fpscr Floating Point Exception Control value to set
jhon309 0:c52df770855b 231 */
jhon309 0:c52df770855b 232 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
jhon309 0:c52df770855b 233 {
jhon309 0:c52df770855b 234 #if (__FPU_PRESENT == 1)
jhon309 0:c52df770855b 235 register uint32_t __regfpexc __ASM("fpexc");
jhon309 0:c52df770855b 236 __regfpexc = (fpexc);
jhon309 0:c52df770855b 237 #endif
jhon309 0:c52df770855b 238 }
jhon309 0:c52df770855b 239
jhon309 0:c52df770855b 240 /** \brief Get CPACR
jhon309 0:c52df770855b 241
jhon309 0:c52df770855b 242 This function returns the current value of the Coprocessor Access Control register.
jhon309 0:c52df770855b 243
jhon309 0:c52df770855b 244 \return Coprocessor Access Control register value
jhon309 0:c52df770855b 245 */
jhon309 0:c52df770855b 246 __STATIC_INLINE uint32_t __get_CPACR(void)
jhon309 0:c52df770855b 247 {
jhon309 0:c52df770855b 248 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
jhon309 0:c52df770855b 249 return __regCPACR;
jhon309 0:c52df770855b 250 }
jhon309 0:c52df770855b 251
jhon309 0:c52df770855b 252 /** \brief Set CPACR
jhon309 0:c52df770855b 253
jhon309 0:c52df770855b 254 This function assigns the given value to the Coprocessor Access Control register.
jhon309 0:c52df770855b 255
jhon309 0:c52df770855b 256 \param [in] cpacr Coporcessor Acccess Control value to set
jhon309 0:c52df770855b 257 */
jhon309 0:c52df770855b 258 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
jhon309 0:c52df770855b 259 {
jhon309 0:c52df770855b 260 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
jhon309 0:c52df770855b 261 __regCPACR = cpacr;
jhon309 0:c52df770855b 262 __ISB();
jhon309 0:c52df770855b 263 }
jhon309 0:c52df770855b 264
jhon309 0:c52df770855b 265 /** \brief Get CBAR
jhon309 0:c52df770855b 266
jhon309 0:c52df770855b 267 This function returns the value of the Configuration Base Address register.
jhon309 0:c52df770855b 268
jhon309 0:c52df770855b 269 \return Configuration Base Address register value
jhon309 0:c52df770855b 270 */
jhon309 0:c52df770855b 271 __STATIC_INLINE uint32_t __get_CBAR() {
jhon309 0:c52df770855b 272 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
jhon309 0:c52df770855b 273 return(__regCBAR);
jhon309 0:c52df770855b 274 }
jhon309 0:c52df770855b 275
jhon309 0:c52df770855b 276 /** \brief Get TTBR0
jhon309 0:c52df770855b 277
jhon309 0:c52df770855b 278 This function returns the value of the Configuration Base Address register.
jhon309 0:c52df770855b 279
jhon309 0:c52df770855b 280 \return Translation Table Base Register 0 value
jhon309 0:c52df770855b 281 */
jhon309 0:c52df770855b 282 __STATIC_INLINE uint32_t __get_TTBR0() {
jhon309 0:c52df770855b 283 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
jhon309 0:c52df770855b 284 return(__regTTBR0);
jhon309 0:c52df770855b 285 }
jhon309 0:c52df770855b 286
jhon309 0:c52df770855b 287 /** \brief Set TTBR0
jhon309 0:c52df770855b 288
jhon309 0:c52df770855b 289 This function assigns the given value to the Coprocessor Access Control register.
jhon309 0:c52df770855b 290
jhon309 0:c52df770855b 291 \param [in] ttbr0 Translation Table Base Register 0 value to set
jhon309 0:c52df770855b 292 */
jhon309 0:c52df770855b 293 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
jhon309 0:c52df770855b 294 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
jhon309 0:c52df770855b 295 __regTTBR0 = ttbr0;
jhon309 0:c52df770855b 296 __ISB();
jhon309 0:c52df770855b 297 }
jhon309 0:c52df770855b 298
jhon309 0:c52df770855b 299 /** \brief Get DACR
jhon309 0:c52df770855b 300
jhon309 0:c52df770855b 301 This function returns the value of the Domain Access Control Register.
jhon309 0:c52df770855b 302
jhon309 0:c52df770855b 303 \return Domain Access Control Register value
jhon309 0:c52df770855b 304 */
jhon309 0:c52df770855b 305 __STATIC_INLINE uint32_t __get_DACR() {
jhon309 0:c52df770855b 306 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
jhon309 0:c52df770855b 307 return(__regDACR);
jhon309 0:c52df770855b 308 }
jhon309 0:c52df770855b 309
jhon309 0:c52df770855b 310 /** \brief Set DACR
jhon309 0:c52df770855b 311
jhon309 0:c52df770855b 312 This function assigns the given value to the Coprocessor Access Control register.
jhon309 0:c52df770855b 313
jhon309 0:c52df770855b 314 \param [in] dacr Domain Access Control Register value to set
jhon309 0:c52df770855b 315 */
jhon309 0:c52df770855b 316 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
jhon309 0:c52df770855b 317 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
jhon309 0:c52df770855b 318 __regDACR = dacr;
jhon309 0:c52df770855b 319 __ISB();
jhon309 0:c52df770855b 320 }
jhon309 0:c52df770855b 321
jhon309 0:c52df770855b 322 /******************************** Cache and BTAC enable ****************************************************/
jhon309 0:c52df770855b 323
jhon309 0:c52df770855b 324 /** \brief Set SCTLR
jhon309 0:c52df770855b 325
jhon309 0:c52df770855b 326 This function assigns the given value to the System Control Register.
jhon309 0:c52df770855b 327
jhon309 0:c52df770855b 328 \param [in] sctlr System Control Register, value to set
jhon309 0:c52df770855b 329 */
jhon309 0:c52df770855b 330 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
jhon309 0:c52df770855b 331 {
jhon309 0:c52df770855b 332 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
jhon309 0:c52df770855b 333 __regSCTLR = sctlr;
jhon309 0:c52df770855b 334 }
jhon309 0:c52df770855b 335
jhon309 0:c52df770855b 336 /** \brief Get SCTLR
jhon309 0:c52df770855b 337
jhon309 0:c52df770855b 338 This function returns the value of the System Control Register.
jhon309 0:c52df770855b 339
jhon309 0:c52df770855b 340 \return System Control Register value
jhon309 0:c52df770855b 341 */
jhon309 0:c52df770855b 342 __STATIC_INLINE uint32_t __get_SCTLR() {
jhon309 0:c52df770855b 343 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
jhon309 0:c52df770855b 344 return(__regSCTLR);
jhon309 0:c52df770855b 345 }
jhon309 0:c52df770855b 346
jhon309 0:c52df770855b 347 /** \brief Enable Caches
jhon309 0:c52df770855b 348
jhon309 0:c52df770855b 349 Enable Caches
jhon309 0:c52df770855b 350 */
jhon309 0:c52df770855b 351 __STATIC_INLINE void __enable_caches(void) {
jhon309 0:c52df770855b 352 // Set I bit 12 to enable I Cache
jhon309 0:c52df770855b 353 // Set C bit 2 to enable D Cache
jhon309 0:c52df770855b 354 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
jhon309 0:c52df770855b 355 }
jhon309 0:c52df770855b 356
jhon309 0:c52df770855b 357 /** \brief Disable Caches
jhon309 0:c52df770855b 358
jhon309 0:c52df770855b 359 Disable Caches
jhon309 0:c52df770855b 360 */
jhon309 0:c52df770855b 361 __STATIC_INLINE void __disable_caches(void) {
jhon309 0:c52df770855b 362 // Clear I bit 12 to disable I Cache
jhon309 0:c52df770855b 363 // Clear C bit 2 to disable D Cache
jhon309 0:c52df770855b 364 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
jhon309 0:c52df770855b 365 __ISB();
jhon309 0:c52df770855b 366 }
jhon309 0:c52df770855b 367
jhon309 0:c52df770855b 368 /** \brief Enable BTAC
jhon309 0:c52df770855b 369
jhon309 0:c52df770855b 370 Enable BTAC
jhon309 0:c52df770855b 371 */
jhon309 0:c52df770855b 372 __STATIC_INLINE void __enable_btac(void) {
jhon309 0:c52df770855b 373 // Set Z bit 11 to enable branch prediction
jhon309 0:c52df770855b 374 __set_SCTLR( __get_SCTLR() | (1 << 11));
jhon309 0:c52df770855b 375 __ISB();
jhon309 0:c52df770855b 376 }
jhon309 0:c52df770855b 377
jhon309 0:c52df770855b 378 /** \brief Disable BTAC
jhon309 0:c52df770855b 379
jhon309 0:c52df770855b 380 Disable BTAC
jhon309 0:c52df770855b 381 */
jhon309 0:c52df770855b 382 __STATIC_INLINE void __disable_btac(void) {
jhon309 0:c52df770855b 383 // Clear Z bit 11 to disable branch prediction
jhon309 0:c52df770855b 384 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
jhon309 0:c52df770855b 385 }
jhon309 0:c52df770855b 386
jhon309 0:c52df770855b 387
jhon309 0:c52df770855b 388 /** \brief Enable MMU
jhon309 0:c52df770855b 389
jhon309 0:c52df770855b 390 Enable MMU
jhon309 0:c52df770855b 391 */
jhon309 0:c52df770855b 392 __STATIC_INLINE void __enable_mmu(void) {
jhon309 0:c52df770855b 393 // Set M bit 0 to enable the MMU
jhon309 0:c52df770855b 394 // Set AFE bit to enable simplified access permissions model
jhon309 0:c52df770855b 395 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
jhon309 0:c52df770855b 396 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
jhon309 0:c52df770855b 397 __ISB();
jhon309 0:c52df770855b 398 }
jhon309 0:c52df770855b 399
jhon309 0:c52df770855b 400 /** \brief Enable MMU
jhon309 0:c52df770855b 401
jhon309 0:c52df770855b 402 Enable MMU
jhon309 0:c52df770855b 403 */
jhon309 0:c52df770855b 404 __STATIC_INLINE void __disable_mmu(void) {
jhon309 0:c52df770855b 405 // Clear M bit 0 to disable the MMU
jhon309 0:c52df770855b 406 __set_SCTLR( __get_SCTLR() & ~1);
jhon309 0:c52df770855b 407 __ISB();
jhon309 0:c52df770855b 408 }
jhon309 0:c52df770855b 409
jhon309 0:c52df770855b 410 /******************************** TLB maintenance operations ************************************************/
jhon309 0:c52df770855b 411 /** \brief Invalidate the whole tlb
jhon309 0:c52df770855b 412
jhon309 0:c52df770855b 413 TLBIALL. Invalidate the whole tlb
jhon309 0:c52df770855b 414 */
jhon309 0:c52df770855b 415
jhon309 0:c52df770855b 416 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
jhon309 0:c52df770855b 417 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
jhon309 0:c52df770855b 418 __TLBIALL = 0;
jhon309 0:c52df770855b 419 __DSB();
jhon309 0:c52df770855b 420 __ISB();
jhon309 0:c52df770855b 421 }
jhon309 0:c52df770855b 422
jhon309 0:c52df770855b 423 /******************************** BTB maintenance operations ************************************************/
jhon309 0:c52df770855b 424 /** \brief Invalidate entire branch predictor array
jhon309 0:c52df770855b 425
jhon309 0:c52df770855b 426 BPIALL. Branch Predictor Invalidate All.
jhon309 0:c52df770855b 427 */
jhon309 0:c52df770855b 428
jhon309 0:c52df770855b 429 __STATIC_INLINE void __v7_inv_btac(void) {
jhon309 0:c52df770855b 430 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
jhon309 0:c52df770855b 431 __BPIALL = 0;
jhon309 0:c52df770855b 432 __DSB(); //ensure completion of the invalidation
jhon309 0:c52df770855b 433 __ISB(); //ensure instruction fetch path sees new state
jhon309 0:c52df770855b 434 }
jhon309 0:c52df770855b 435
jhon309 0:c52df770855b 436
jhon309 0:c52df770855b 437 /******************************** L1 cache operations ******************************************************/
jhon309 0:c52df770855b 438
jhon309 0:c52df770855b 439 /** \brief Invalidate the whole I$
jhon309 0:c52df770855b 440
jhon309 0:c52df770855b 441 ICIALLU. Instruction Cache Invalidate All to PoU
jhon309 0:c52df770855b 442 */
jhon309 0:c52df770855b 443 __STATIC_INLINE void __v7_inv_icache_all(void) {
jhon309 0:c52df770855b 444 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
jhon309 0:c52df770855b 445 __ICIALLU = 0;
jhon309 0:c52df770855b 446 __DSB(); //ensure completion of the invalidation
jhon309 0:c52df770855b 447 __ISB(); //ensure instruction fetch path sees new I cache state
jhon309 0:c52df770855b 448 }
jhon309 0:c52df770855b 449
jhon309 0:c52df770855b 450 /** \brief Clean D$ by MVA
jhon309 0:c52df770855b 451
jhon309 0:c52df770855b 452 DCCMVAC. Data cache clean by MVA to PoC
jhon309 0:c52df770855b 453 */
jhon309 0:c52df770855b 454 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
jhon309 0:c52df770855b 455 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
jhon309 0:c52df770855b 456 __DCCMVAC = (uint32_t)va;
jhon309 0:c52df770855b 457 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jhon309 0:c52df770855b 458 }
jhon309 0:c52df770855b 459
jhon309 0:c52df770855b 460 /** \brief Invalidate D$ by MVA
jhon309 0:c52df770855b 461
jhon309 0:c52df770855b 462 DCIMVAC. Data cache invalidate by MVA to PoC
jhon309 0:c52df770855b 463 */
jhon309 0:c52df770855b 464 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
jhon309 0:c52df770855b 465 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
jhon309 0:c52df770855b 466 __DCIMVAC = (uint32_t)va;
jhon309 0:c52df770855b 467 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jhon309 0:c52df770855b 468 }
jhon309 0:c52df770855b 469
jhon309 0:c52df770855b 470 /** \brief Clean and Invalidate D$ by MVA
jhon309 0:c52df770855b 471
jhon309 0:c52df770855b 472 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
jhon309 0:c52df770855b 473 */
jhon309 0:c52df770855b 474 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
jhon309 0:c52df770855b 475 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
jhon309 0:c52df770855b 476 __DCCIMVAC = (uint32_t)va;
jhon309 0:c52df770855b 477 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jhon309 0:c52df770855b 478 }
jhon309 0:c52df770855b 479
jhon309 0:c52df770855b 480 /** \brief
jhon309 0:c52df770855b 481 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
jhon309 0:c52df770855b 482 */
jhon309 0:c52df770855b 483 #pragma push
jhon309 0:c52df770855b 484 #pragma arm
jhon309 0:c52df770855b 485 __STATIC_ASM void __v7_all_cache(uint32_t op) {
jhon309 0:c52df770855b 486 ARM
jhon309 0:c52df770855b 487
jhon309 0:c52df770855b 488 PUSH {R4-R11}
jhon309 0:c52df770855b 489
jhon309 0:c52df770855b 490 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
jhon309 0:c52df770855b 491 ANDS R3, R6, #0x07000000 // Extract coherency level
jhon309 0:c52df770855b 492 MOV R3, R3, LSR #23 // Total cache levels << 1
jhon309 0:c52df770855b 493 BEQ Finished // If 0, no need to clean
jhon309 0:c52df770855b 494
jhon309 0:c52df770855b 495 MOV R10, #0 // R10 holds current cache level << 1
jhon309 0:c52df770855b 496 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
jhon309 0:c52df770855b 497 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
jhon309 0:c52df770855b 498 AND R1, R1, #7 // Isolate those lower 3 bits
jhon309 0:c52df770855b 499 CMP R1, #2
jhon309 0:c52df770855b 500 BLT Skip // No cache or only instruction cache at this level
jhon309 0:c52df770855b 501
jhon309 0:c52df770855b 502 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
jhon309 0:c52df770855b 503 ISB // ISB to sync the change to the CacheSizeID reg
jhon309 0:c52df770855b 504 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
jhon309 0:c52df770855b 505 AND R2, R1, #7 // Extract the line length field
jhon309 0:c52df770855b 506 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
jhon309 0:c52df770855b 507 LDR R4, =0x3FF
jhon309 0:c52df770855b 508 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
jhon309 0:c52df770855b 509 CLZ R5, R4 // R5 is the bit position of the way size increment
jhon309 0:c52df770855b 510 LDR R7, =0x7FFF
jhon309 0:c52df770855b 511 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
jhon309 0:c52df770855b 512
jhon309 0:c52df770855b 513 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
jhon309 0:c52df770855b 514
jhon309 0:c52df770855b 515 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
jhon309 0:c52df770855b 516 ORR R11, R11, R7, LSL R2 // Factor in the Set number
jhon309 0:c52df770855b 517 CMP R0, #0
jhon309 0:c52df770855b 518 BNE Dccsw
jhon309 0:c52df770855b 519 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
jhon309 0:c52df770855b 520 B cont
jhon309 0:c52df770855b 521 Dccsw CMP R0, #1
jhon309 0:c52df770855b 522 BNE Dccisw
jhon309 0:c52df770855b 523 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
jhon309 0:c52df770855b 524 B cont
jhon309 0:c52df770855b 525 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW, Clean and Invalidate by Set/Way
jhon309 0:c52df770855b 526 cont SUBS R9, R9, #1 // Decrement the Way number
jhon309 0:c52df770855b 527 BGE Loop3
jhon309 0:c52df770855b 528 SUBS R7, R7, #1 // Decrement the Set number
jhon309 0:c52df770855b 529 BGE Loop2
jhon309 0:c52df770855b 530 Skip ADD R10, R10, #2 // increment the cache number
jhon309 0:c52df770855b 531 CMP R3, R10
jhon309 0:c52df770855b 532 BGT Loop1
jhon309 0:c52df770855b 533
jhon309 0:c52df770855b 534 Finished
jhon309 0:c52df770855b 535 DSB
jhon309 0:c52df770855b 536 POP {R4-R11}
jhon309 0:c52df770855b 537 BX lr
jhon309 0:c52df770855b 538
jhon309 0:c52df770855b 539 }
jhon309 0:c52df770855b 540 #pragma pop
jhon309 0:c52df770855b 541
jhon309 0:c52df770855b 542 /** \brief __v7_all_cache - helper function
jhon309 0:c52df770855b 543
jhon309 0:c52df770855b 544 */
jhon309 0:c52df770855b 545
jhon309 0:c52df770855b 546 /** \brief Invalidate the whole D$
jhon309 0:c52df770855b 547
jhon309 0:c52df770855b 548 DCISW. Invalidate by Set/Way
jhon309 0:c52df770855b 549 */
jhon309 0:c52df770855b 550
jhon309 0:c52df770855b 551 __STATIC_INLINE void __v7_inv_dcache_all(void) {
jhon309 0:c52df770855b 552 __v7_all_cache(0);
jhon309 0:c52df770855b 553 }
jhon309 0:c52df770855b 554
jhon309 0:c52df770855b 555 /** \brief Clean the whole D$
jhon309 0:c52df770855b 556
jhon309 0:c52df770855b 557 DCCSW. Clean by Set/Way
jhon309 0:c52df770855b 558 */
jhon309 0:c52df770855b 559
jhon309 0:c52df770855b 560 __STATIC_INLINE void __v7_clean_dcache_all(void) {
jhon309 0:c52df770855b 561 __v7_all_cache(1);
jhon309 0:c52df770855b 562 }
jhon309 0:c52df770855b 563
jhon309 0:c52df770855b 564 /** \brief Clean and invalidate the whole D$
jhon309 0:c52df770855b 565
jhon309 0:c52df770855b 566 DCCISW. Clean and Invalidate by Set/Way
jhon309 0:c52df770855b 567 */
jhon309 0:c52df770855b 568
jhon309 0:c52df770855b 569 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
jhon309 0:c52df770855b 570 __v7_all_cache(2);
jhon309 0:c52df770855b 571 }
jhon309 0:c52df770855b 572
jhon309 0:c52df770855b 573 #include "core_ca_mmu.h"
jhon309 0:c52df770855b 574
jhon309 0:c52df770855b 575 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
jhon309 0:c52df770855b 576
jhon309 0:c52df770855b 577 #error IAR Compiler support not implemented for Cortex-A
jhon309 0:c52df770855b 578
jhon309 0:c52df770855b 579 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
jhon309 0:c52df770855b 580
jhon309 0:c52df770855b 581 /* GNU gcc specific functions */
jhon309 0:c52df770855b 582
jhon309 0:c52df770855b 583 #define MODE_USR 0x10
jhon309 0:c52df770855b 584 #define MODE_FIQ 0x11
jhon309 0:c52df770855b 585 #define MODE_IRQ 0x12
jhon309 0:c52df770855b 586 #define MODE_SVC 0x13
jhon309 0:c52df770855b 587 #define MODE_MON 0x16
jhon309 0:c52df770855b 588 #define MODE_ABT 0x17
jhon309 0:c52df770855b 589 #define MODE_HYP 0x1A
jhon309 0:c52df770855b 590 #define MODE_UND 0x1B
jhon309 0:c52df770855b 591 #define MODE_SYS 0x1F
jhon309 0:c52df770855b 592
jhon309 0:c52df770855b 593
jhon309 0:c52df770855b 594 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
jhon309 0:c52df770855b 595 {
jhon309 0:c52df770855b 596 __ASM volatile ("cpsie i");
jhon309 0:c52df770855b 597 }
jhon309 0:c52df770855b 598
jhon309 0:c52df770855b 599 /** \brief Disable IRQ Interrupts
jhon309 0:c52df770855b 600
jhon309 0:c52df770855b 601 This function disables IRQ interrupts by setting the I-bit in the CPSR.
jhon309 0:c52df770855b 602 Can only be executed in Privileged modes.
jhon309 0:c52df770855b 603 */
jhon309 0:c52df770855b 604 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
jhon309 0:c52df770855b 605 {
jhon309 0:c52df770855b 606 uint32_t result;
jhon309 0:c52df770855b 607
jhon309 0:c52df770855b 608 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
jhon309 0:c52df770855b 609 __ASM volatile ("cpsid i");
jhon309 0:c52df770855b 610 return(result & 0x80);
jhon309 0:c52df770855b 611 }
jhon309 0:c52df770855b 612
jhon309 0:c52df770855b 613
jhon309 0:c52df770855b 614 /** \brief Get APSR Register
jhon309 0:c52df770855b 615
jhon309 0:c52df770855b 616 This function returns the content of the APSR Register.
jhon309 0:c52df770855b 617
jhon309 0:c52df770855b 618 \return APSR Register value
jhon309 0:c52df770855b 619 */
jhon309 0:c52df770855b 620 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
jhon309 0:c52df770855b 621 {
jhon309 0:c52df770855b 622 #if 1
jhon309 0:c52df770855b 623 uint32_t result;
jhon309 0:c52df770855b 624
jhon309 0:c52df770855b 625 __ASM volatile ("mrs %0, apsr" : "=r" (result) );
jhon309 0:c52df770855b 626 return (result);
jhon309 0:c52df770855b 627 #else
jhon309 0:c52df770855b 628 register uint32_t __regAPSR __ASM("apsr");
jhon309 0:c52df770855b 629 return(__regAPSR);
jhon309 0:c52df770855b 630 #endif
jhon309 0:c52df770855b 631 }
jhon309 0:c52df770855b 632
jhon309 0:c52df770855b 633
jhon309 0:c52df770855b 634 /** \brief Get CPSR Register
jhon309 0:c52df770855b 635
jhon309 0:c52df770855b 636 This function returns the content of the CPSR Register.
jhon309 0:c52df770855b 637
jhon309 0:c52df770855b 638 \return CPSR Register value
jhon309 0:c52df770855b 639 */
jhon309 0:c52df770855b 640 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
jhon309 0:c52df770855b 641 {
jhon309 0:c52df770855b 642 #if 1
jhon309 0:c52df770855b 643 register uint32_t __regCPSR;
jhon309 0:c52df770855b 644 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
jhon309 0:c52df770855b 645 #else
jhon309 0:c52df770855b 646 register uint32_t __regCPSR __ASM("cpsr");
jhon309 0:c52df770855b 647 #endif
jhon309 0:c52df770855b 648 return(__regCPSR);
jhon309 0:c52df770855b 649 }
jhon309 0:c52df770855b 650
jhon309 0:c52df770855b 651 #if 0
jhon309 0:c52df770855b 652 /** \brief Set Stack Pointer
jhon309 0:c52df770855b 653
jhon309 0:c52df770855b 654 This function assigns the given value to the current stack pointer.
jhon309 0:c52df770855b 655
jhon309 0:c52df770855b 656 \param [in] topOfStack Stack Pointer value to set
jhon309 0:c52df770855b 657 */
jhon309 0:c52df770855b 658 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
jhon309 0:c52df770855b 659 {
jhon309 0:c52df770855b 660 register uint32_t __regSP __ASM("sp");
jhon309 0:c52df770855b 661 __regSP = topOfStack;
jhon309 0:c52df770855b 662 }
jhon309 0:c52df770855b 663 #endif
jhon309 0:c52df770855b 664
jhon309 0:c52df770855b 665 /** \brief Get link register
jhon309 0:c52df770855b 666
jhon309 0:c52df770855b 667 This function returns the value of the link register
jhon309 0:c52df770855b 668
jhon309 0:c52df770855b 669 \return Value of link register
jhon309 0:c52df770855b 670 */
jhon309 0:c52df770855b 671 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
jhon309 0:c52df770855b 672 {
jhon309 0:c52df770855b 673 register uint32_t __reglr __ASM("lr");
jhon309 0:c52df770855b 674 return(__reglr);
jhon309 0:c52df770855b 675 }
jhon309 0:c52df770855b 676
jhon309 0:c52df770855b 677 #if 0
jhon309 0:c52df770855b 678 /** \brief Set link register
jhon309 0:c52df770855b 679
jhon309 0:c52df770855b 680 This function sets the value of the link register
jhon309 0:c52df770855b 681
jhon309 0:c52df770855b 682 \param [in] lr LR value to set
jhon309 0:c52df770855b 683 */
jhon309 0:c52df770855b 684 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
jhon309 0:c52df770855b 685 {
jhon309 0:c52df770855b 686 register uint32_t __reglr __ASM("lr");
jhon309 0:c52df770855b 687 __reglr = lr;
jhon309 0:c52df770855b 688 }
jhon309 0:c52df770855b 689 #endif
jhon309 0:c52df770855b 690
jhon309 0:c52df770855b 691 /** \brief Set Process Stack Pointer
jhon309 0:c52df770855b 692
jhon309 0:c52df770855b 693 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
jhon309 0:c52df770855b 694
jhon309 0:c52df770855b 695 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
jhon309 0:c52df770855b 696 */
jhon309 0:c52df770855b 697 extern void __set_PSP(uint32_t topOfProcStack);
jhon309 0:c52df770855b 698
jhon309 0:c52df770855b 699 /** \brief Set User Mode
jhon309 0:c52df770855b 700
jhon309 0:c52df770855b 701 This function changes the processor state to User Mode
jhon309 0:c52df770855b 702
jhon309 0:c52df770855b 703 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
jhon309 0:c52df770855b 704 */
jhon309 0:c52df770855b 705 extern void __set_CPS_USR(void);
jhon309 0:c52df770855b 706
jhon309 0:c52df770855b 707 /** \brief Enable FIQ
jhon309 0:c52df770855b 708
jhon309 0:c52df770855b 709 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
jhon309 0:c52df770855b 710 Can only be executed in Privileged modes.
jhon309 0:c52df770855b 711 */
jhon309 0:c52df770855b 712 #define __enable_fault_irq __enable_fiq
jhon309 0:c52df770855b 713
jhon309 0:c52df770855b 714
jhon309 0:c52df770855b 715 /** \brief Disable FIQ
jhon309 0:c52df770855b 716
jhon309 0:c52df770855b 717 This function disables FIQ interrupts by setting the F-bit in the CPSR.
jhon309 0:c52df770855b 718 Can only be executed in Privileged modes.
jhon309 0:c52df770855b 719 */
jhon309 0:c52df770855b 720 #define __disable_fault_irq __disable_fiq
jhon309 0:c52df770855b 721
jhon309 0:c52df770855b 722
jhon309 0:c52df770855b 723 /** \brief Get FPSCR
jhon309 0:c52df770855b 724
jhon309 0:c52df770855b 725 This function returns the current value of the Floating Point Status/Control register.
jhon309 0:c52df770855b 726
jhon309 0:c52df770855b 727 \return Floating Point Status/Control register value
jhon309 0:c52df770855b 728 */
jhon309 0:c52df770855b 729 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
jhon309 0:c52df770855b 730 {
jhon309 0:c52df770855b 731 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jhon309 0:c52df770855b 732 #if 1
jhon309 0:c52df770855b 733 uint32_t result;
jhon309 0:c52df770855b 734
jhon309 0:c52df770855b 735 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
jhon309 0:c52df770855b 736 return (result);
jhon309 0:c52df770855b 737 #else
jhon309 0:c52df770855b 738 register uint32_t __regfpscr __ASM("fpscr");
jhon309 0:c52df770855b 739 return(__regfpscr);
jhon309 0:c52df770855b 740 #endif
jhon309 0:c52df770855b 741 #else
jhon309 0:c52df770855b 742 return(0);
jhon309 0:c52df770855b 743 #endif
jhon309 0:c52df770855b 744 }
jhon309 0:c52df770855b 745
jhon309 0:c52df770855b 746
jhon309 0:c52df770855b 747 /** \brief Set FPSCR
jhon309 0:c52df770855b 748
jhon309 0:c52df770855b 749 This function assigns the given value to the Floating Point Status/Control register.
jhon309 0:c52df770855b 750
jhon309 0:c52df770855b 751 \param [in] fpscr Floating Point Status/Control value to set
jhon309 0:c52df770855b 752 */
jhon309 0:c52df770855b 753 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
jhon309 0:c52df770855b 754 {
jhon309 0:c52df770855b 755 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
jhon309 0:c52df770855b 756 #if 1
jhon309 0:c52df770855b 757 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
jhon309 0:c52df770855b 758 #else
jhon309 0:c52df770855b 759 register uint32_t __regfpscr __ASM("fpscr");
jhon309 0:c52df770855b 760 __regfpscr = (fpscr);
jhon309 0:c52df770855b 761 #endif
jhon309 0:c52df770855b 762 #endif
jhon309 0:c52df770855b 763 }
jhon309 0:c52df770855b 764
jhon309 0:c52df770855b 765 /** \brief Get FPEXC
jhon309 0:c52df770855b 766
jhon309 0:c52df770855b 767 This function returns the current value of the Floating Point Exception Control register.
jhon309 0:c52df770855b 768
jhon309 0:c52df770855b 769 \return Floating Point Exception Control register value
jhon309 0:c52df770855b 770 */
jhon309 0:c52df770855b 771 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
jhon309 0:c52df770855b 772 {
jhon309 0:c52df770855b 773 #if (__FPU_PRESENT == 1)
jhon309 0:c52df770855b 774 #if 1
jhon309 0:c52df770855b 775 uint32_t result;
jhon309 0:c52df770855b 776
jhon309 0:c52df770855b 777 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
jhon309 0:c52df770855b 778 return (result);
jhon309 0:c52df770855b 779 #else
jhon309 0:c52df770855b 780 register uint32_t __regfpexc __ASM("fpexc");
jhon309 0:c52df770855b 781 return(__regfpexc);
jhon309 0:c52df770855b 782 #endif
jhon309 0:c52df770855b 783 #else
jhon309 0:c52df770855b 784 return(0);
jhon309 0:c52df770855b 785 #endif
jhon309 0:c52df770855b 786 }
jhon309 0:c52df770855b 787
jhon309 0:c52df770855b 788
jhon309 0:c52df770855b 789 /** \brief Set FPEXC
jhon309 0:c52df770855b 790
jhon309 0:c52df770855b 791 This function assigns the given value to the Floating Point Exception Control register.
jhon309 0:c52df770855b 792
jhon309 0:c52df770855b 793 \param [in] fpscr Floating Point Exception Control value to set
jhon309 0:c52df770855b 794 */
jhon309 0:c52df770855b 795 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
jhon309 0:c52df770855b 796 {
jhon309 0:c52df770855b 797 #if (__FPU_PRESENT == 1)
jhon309 0:c52df770855b 798 #if 1
jhon309 0:c52df770855b 799 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
jhon309 0:c52df770855b 800 #else
jhon309 0:c52df770855b 801 register uint32_t __regfpexc __ASM("fpexc");
jhon309 0:c52df770855b 802 __regfpexc = (fpexc);
jhon309 0:c52df770855b 803 #endif
jhon309 0:c52df770855b 804 #endif
jhon309 0:c52df770855b 805 }
jhon309 0:c52df770855b 806
jhon309 0:c52df770855b 807 /** \brief Get CPACR
jhon309 0:c52df770855b 808
jhon309 0:c52df770855b 809 This function returns the current value of the Coprocessor Access Control register.
jhon309 0:c52df770855b 810
jhon309 0:c52df770855b 811 \return Coprocessor Access Control register value
jhon309 0:c52df770855b 812 */
jhon309 0:c52df770855b 813 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
jhon309 0:c52df770855b 814 {
jhon309 0:c52df770855b 815 #if 1
jhon309 0:c52df770855b 816 register uint32_t __regCPACR;
jhon309 0:c52df770855b 817 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
jhon309 0:c52df770855b 818 #else
jhon309 0:c52df770855b 819 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
jhon309 0:c52df770855b 820 #endif
jhon309 0:c52df770855b 821 return __regCPACR;
jhon309 0:c52df770855b 822 }
jhon309 0:c52df770855b 823
jhon309 0:c52df770855b 824 /** \brief Set CPACR
jhon309 0:c52df770855b 825
jhon309 0:c52df770855b 826 This function assigns the given value to the Coprocessor Access Control register.
jhon309 0:c52df770855b 827
jhon309 0:c52df770855b 828 \param [in] cpacr Coporcessor Acccess Control value to set
jhon309 0:c52df770855b 829 */
jhon309 0:c52df770855b 830 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
jhon309 0:c52df770855b 831 {
jhon309 0:c52df770855b 832 #if 1
jhon309 0:c52df770855b 833 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
jhon309 0:c52df770855b 834 #else
jhon309 0:c52df770855b 835 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
jhon309 0:c52df770855b 836 __regCPACR = cpacr;
jhon309 0:c52df770855b 837 #endif
jhon309 0:c52df770855b 838 __ISB();
jhon309 0:c52df770855b 839 }
jhon309 0:c52df770855b 840
jhon309 0:c52df770855b 841 /** \brief Get CBAR
jhon309 0:c52df770855b 842
jhon309 0:c52df770855b 843 This function returns the value of the Configuration Base Address register.
jhon309 0:c52df770855b 844
jhon309 0:c52df770855b 845 \return Configuration Base Address register value
jhon309 0:c52df770855b 846 */
jhon309 0:c52df770855b 847 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
jhon309 0:c52df770855b 848 #if 1
jhon309 0:c52df770855b 849 register uint32_t __regCBAR;
jhon309 0:c52df770855b 850 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
jhon309 0:c52df770855b 851 #else
jhon309 0:c52df770855b 852 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
jhon309 0:c52df770855b 853 #endif
jhon309 0:c52df770855b 854 return(__regCBAR);
jhon309 0:c52df770855b 855 }
jhon309 0:c52df770855b 856
jhon309 0:c52df770855b 857 /** \brief Get TTBR0
jhon309 0:c52df770855b 858
jhon309 0:c52df770855b 859 This function returns the value of the Configuration Base Address register.
jhon309 0:c52df770855b 860
jhon309 0:c52df770855b 861 \return Translation Table Base Register 0 value
jhon309 0:c52df770855b 862 */
jhon309 0:c52df770855b 863 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
jhon309 0:c52df770855b 864 #if 1
jhon309 0:c52df770855b 865 register uint32_t __regTTBR0;
jhon309 0:c52df770855b 866 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
jhon309 0:c52df770855b 867 #else
jhon309 0:c52df770855b 868 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
jhon309 0:c52df770855b 869 #endif
jhon309 0:c52df770855b 870 return(__regTTBR0);
jhon309 0:c52df770855b 871 }
jhon309 0:c52df770855b 872
jhon309 0:c52df770855b 873 /** \brief Set TTBR0
jhon309 0:c52df770855b 874
jhon309 0:c52df770855b 875 This function assigns the given value to the Coprocessor Access Control register.
jhon309 0:c52df770855b 876
jhon309 0:c52df770855b 877 \param [in] ttbr0 Translation Table Base Register 0 value to set
jhon309 0:c52df770855b 878 */
jhon309 0:c52df770855b 879 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
jhon309 0:c52df770855b 880 #if 1
jhon309 0:c52df770855b 881 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
jhon309 0:c52df770855b 882 #else
jhon309 0:c52df770855b 883 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
jhon309 0:c52df770855b 884 __regTTBR0 = ttbr0;
jhon309 0:c52df770855b 885 #endif
jhon309 0:c52df770855b 886 __ISB();
jhon309 0:c52df770855b 887 }
jhon309 0:c52df770855b 888
jhon309 0:c52df770855b 889 /** \brief Get DACR
jhon309 0:c52df770855b 890
jhon309 0:c52df770855b 891 This function returns the value of the Domain Access Control Register.
jhon309 0:c52df770855b 892
jhon309 0:c52df770855b 893 \return Domain Access Control Register value
jhon309 0:c52df770855b 894 */
jhon309 0:c52df770855b 895 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
jhon309 0:c52df770855b 896 #if 1
jhon309 0:c52df770855b 897 register uint32_t __regDACR;
jhon309 0:c52df770855b 898 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
jhon309 0:c52df770855b 899 #else
jhon309 0:c52df770855b 900 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
jhon309 0:c52df770855b 901 #endif
jhon309 0:c52df770855b 902 return(__regDACR);
jhon309 0:c52df770855b 903 }
jhon309 0:c52df770855b 904
jhon309 0:c52df770855b 905 /** \brief Set DACR
jhon309 0:c52df770855b 906
jhon309 0:c52df770855b 907 This function assigns the given value to the Coprocessor Access Control register.
jhon309 0:c52df770855b 908
jhon309 0:c52df770855b 909 \param [in] dacr Domain Access Control Register value to set
jhon309 0:c52df770855b 910 */
jhon309 0:c52df770855b 911 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
jhon309 0:c52df770855b 912 #if 1
jhon309 0:c52df770855b 913 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
jhon309 0:c52df770855b 914 #else
jhon309 0:c52df770855b 915 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
jhon309 0:c52df770855b 916 __regDACR = dacr;
jhon309 0:c52df770855b 917 #endif
jhon309 0:c52df770855b 918 __ISB();
jhon309 0:c52df770855b 919 }
jhon309 0:c52df770855b 920
jhon309 0:c52df770855b 921 /******************************** Cache and BTAC enable ****************************************************/
jhon309 0:c52df770855b 922
jhon309 0:c52df770855b 923 /** \brief Set SCTLR
jhon309 0:c52df770855b 924
jhon309 0:c52df770855b 925 This function assigns the given value to the System Control Register.
jhon309 0:c52df770855b 926
jhon309 0:c52df770855b 927 \param [in] sctlr System Control Register, value to set
jhon309 0:c52df770855b 928 */
jhon309 0:c52df770855b 929 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
jhon309 0:c52df770855b 930 {
jhon309 0:c52df770855b 931 #if 1
jhon309 0:c52df770855b 932 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
jhon309 0:c52df770855b 933 #else
jhon309 0:c52df770855b 934 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
jhon309 0:c52df770855b 935 __regSCTLR = sctlr;
jhon309 0:c52df770855b 936 #endif
jhon309 0:c52df770855b 937 }
jhon309 0:c52df770855b 938
jhon309 0:c52df770855b 939 /** \brief Get SCTLR
jhon309 0:c52df770855b 940
jhon309 0:c52df770855b 941 This function returns the value of the System Control Register.
jhon309 0:c52df770855b 942
jhon309 0:c52df770855b 943 \return System Control Register value
jhon309 0:c52df770855b 944 */
jhon309 0:c52df770855b 945 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
jhon309 0:c52df770855b 946 #if 1
jhon309 0:c52df770855b 947 register uint32_t __regSCTLR;
jhon309 0:c52df770855b 948 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
jhon309 0:c52df770855b 949 #else
jhon309 0:c52df770855b 950 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
jhon309 0:c52df770855b 951 #endif
jhon309 0:c52df770855b 952 return(__regSCTLR);
jhon309 0:c52df770855b 953 }
jhon309 0:c52df770855b 954
jhon309 0:c52df770855b 955 /** \brief Enable Caches
jhon309 0:c52df770855b 956
jhon309 0:c52df770855b 957 Enable Caches
jhon309 0:c52df770855b 958 */
jhon309 0:c52df770855b 959 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
jhon309 0:c52df770855b 960 // Set I bit 12 to enable I Cache
jhon309 0:c52df770855b 961 // Set C bit 2 to enable D Cache
jhon309 0:c52df770855b 962 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
jhon309 0:c52df770855b 963 }
jhon309 0:c52df770855b 964
jhon309 0:c52df770855b 965 /** \brief Disable Caches
jhon309 0:c52df770855b 966
jhon309 0:c52df770855b 967 Disable Caches
jhon309 0:c52df770855b 968 */
jhon309 0:c52df770855b 969 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
jhon309 0:c52df770855b 970 // Clear I bit 12 to disable I Cache
jhon309 0:c52df770855b 971 // Clear C bit 2 to disable D Cache
jhon309 0:c52df770855b 972 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
jhon309 0:c52df770855b 973 __ISB();
jhon309 0:c52df770855b 974 }
jhon309 0:c52df770855b 975
jhon309 0:c52df770855b 976 /** \brief Enable BTAC
jhon309 0:c52df770855b 977
jhon309 0:c52df770855b 978 Enable BTAC
jhon309 0:c52df770855b 979 */
jhon309 0:c52df770855b 980 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
jhon309 0:c52df770855b 981 // Set Z bit 11 to enable branch prediction
jhon309 0:c52df770855b 982 __set_SCTLR( __get_SCTLR() | (1 << 11));
jhon309 0:c52df770855b 983 __ISB();
jhon309 0:c52df770855b 984 }
jhon309 0:c52df770855b 985
jhon309 0:c52df770855b 986 /** \brief Disable BTAC
jhon309 0:c52df770855b 987
jhon309 0:c52df770855b 988 Disable BTAC
jhon309 0:c52df770855b 989 */
jhon309 0:c52df770855b 990 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
jhon309 0:c52df770855b 991 // Clear Z bit 11 to disable branch prediction
jhon309 0:c52df770855b 992 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
jhon309 0:c52df770855b 993 }
jhon309 0:c52df770855b 994
jhon309 0:c52df770855b 995
jhon309 0:c52df770855b 996 /** \brief Enable MMU
jhon309 0:c52df770855b 997
jhon309 0:c52df770855b 998 Enable MMU
jhon309 0:c52df770855b 999 */
jhon309 0:c52df770855b 1000 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
jhon309 0:c52df770855b 1001 // Set M bit 0 to enable the MMU
jhon309 0:c52df770855b 1002 // Set AFE bit to enable simplified access permissions model
jhon309 0:c52df770855b 1003 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
jhon309 0:c52df770855b 1004 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
jhon309 0:c52df770855b 1005 __ISB();
jhon309 0:c52df770855b 1006 }
jhon309 0:c52df770855b 1007
jhon309 0:c52df770855b 1008 /** \brief Enable MMU
jhon309 0:c52df770855b 1009
jhon309 0:c52df770855b 1010 Enable MMU
jhon309 0:c52df770855b 1011 */
jhon309 0:c52df770855b 1012 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
jhon309 0:c52df770855b 1013 // Clear M bit 0 to disable the MMU
jhon309 0:c52df770855b 1014 __set_SCTLR( __get_SCTLR() & ~1);
jhon309 0:c52df770855b 1015 __ISB();
jhon309 0:c52df770855b 1016 }
jhon309 0:c52df770855b 1017
jhon309 0:c52df770855b 1018 /******************************** TLB maintenance operations ************************************************/
jhon309 0:c52df770855b 1019 /** \brief Invalidate the whole tlb
jhon309 0:c52df770855b 1020
jhon309 0:c52df770855b 1021 TLBIALL. Invalidate the whole tlb
jhon309 0:c52df770855b 1022 */
jhon309 0:c52df770855b 1023
jhon309 0:c52df770855b 1024 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
jhon309 0:c52df770855b 1025 #if 1
jhon309 0:c52df770855b 1026 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
jhon309 0:c52df770855b 1027 #else
jhon309 0:c52df770855b 1028 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
jhon309 0:c52df770855b 1029 __TLBIALL = 0;
jhon309 0:c52df770855b 1030 #endif
jhon309 0:c52df770855b 1031 __DSB();
jhon309 0:c52df770855b 1032 __ISB();
jhon309 0:c52df770855b 1033 }
jhon309 0:c52df770855b 1034
jhon309 0:c52df770855b 1035 /******************************** BTB maintenance operations ************************************************/
jhon309 0:c52df770855b 1036 /** \brief Invalidate entire branch predictor array
jhon309 0:c52df770855b 1037
jhon309 0:c52df770855b 1038 BPIALL. Branch Predictor Invalidate All.
jhon309 0:c52df770855b 1039 */
jhon309 0:c52df770855b 1040
jhon309 0:c52df770855b 1041 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
jhon309 0:c52df770855b 1042 #if 1
jhon309 0:c52df770855b 1043 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
jhon309 0:c52df770855b 1044 #else
jhon309 0:c52df770855b 1045 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
jhon309 0:c52df770855b 1046 __BPIALL = 0;
jhon309 0:c52df770855b 1047 #endif
jhon309 0:c52df770855b 1048 __DSB(); //ensure completion of the invalidation
jhon309 0:c52df770855b 1049 __ISB(); //ensure instruction fetch path sees new state
jhon309 0:c52df770855b 1050 }
jhon309 0:c52df770855b 1051
jhon309 0:c52df770855b 1052
jhon309 0:c52df770855b 1053 /******************************** L1 cache operations ******************************************************/
jhon309 0:c52df770855b 1054
jhon309 0:c52df770855b 1055 /** \brief Invalidate the whole I$
jhon309 0:c52df770855b 1056
jhon309 0:c52df770855b 1057 ICIALLU. Instruction Cache Invalidate All to PoU
jhon309 0:c52df770855b 1058 */
jhon309 0:c52df770855b 1059 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
jhon309 0:c52df770855b 1060 #if 1
jhon309 0:c52df770855b 1061 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
jhon309 0:c52df770855b 1062 #else
jhon309 0:c52df770855b 1063 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
jhon309 0:c52df770855b 1064 __ICIALLU = 0;
jhon309 0:c52df770855b 1065 #endif
jhon309 0:c52df770855b 1066 __DSB(); //ensure completion of the invalidation
jhon309 0:c52df770855b 1067 __ISB(); //ensure instruction fetch path sees new I cache state
jhon309 0:c52df770855b 1068 }
jhon309 0:c52df770855b 1069
jhon309 0:c52df770855b 1070 /** \brief Clean D$ by MVA
jhon309 0:c52df770855b 1071
jhon309 0:c52df770855b 1072 DCCMVAC. Data cache clean by MVA to PoC
jhon309 0:c52df770855b 1073 */
jhon309 0:c52df770855b 1074 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
jhon309 0:c52df770855b 1075 #if 1
jhon309 0:c52df770855b 1076 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
jhon309 0:c52df770855b 1077 #else
jhon309 0:c52df770855b 1078 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
jhon309 0:c52df770855b 1079 __DCCMVAC = (uint32_t)va;
jhon309 0:c52df770855b 1080 #endif
jhon309 0:c52df770855b 1081 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jhon309 0:c52df770855b 1082 }
jhon309 0:c52df770855b 1083
jhon309 0:c52df770855b 1084 /** \brief Invalidate D$ by MVA
jhon309 0:c52df770855b 1085
jhon309 0:c52df770855b 1086 DCIMVAC. Data cache invalidate by MVA to PoC
jhon309 0:c52df770855b 1087 */
jhon309 0:c52df770855b 1088 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
jhon309 0:c52df770855b 1089 #if 1
jhon309 0:c52df770855b 1090 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
jhon309 0:c52df770855b 1091 #else
jhon309 0:c52df770855b 1092 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
jhon309 0:c52df770855b 1093 __DCIMVAC = (uint32_t)va;
jhon309 0:c52df770855b 1094 #endif
jhon309 0:c52df770855b 1095 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jhon309 0:c52df770855b 1096 }
jhon309 0:c52df770855b 1097
jhon309 0:c52df770855b 1098 /** \brief Clean and Invalidate D$ by MVA
jhon309 0:c52df770855b 1099
jhon309 0:c52df770855b 1100 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
jhon309 0:c52df770855b 1101 */
jhon309 0:c52df770855b 1102 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
jhon309 0:c52df770855b 1103 #if 1
jhon309 0:c52df770855b 1104 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
jhon309 0:c52df770855b 1105 #else
jhon309 0:c52df770855b 1106 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
jhon309 0:c52df770855b 1107 __DCCIMVAC = (uint32_t)va;
jhon309 0:c52df770855b 1108 #endif
jhon309 0:c52df770855b 1109 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
jhon309 0:c52df770855b 1110 }
jhon309 0:c52df770855b 1111
jhon309 0:c52df770855b 1112 /** \brief
jhon309 0:c52df770855b 1113 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
jhon309 0:c52df770855b 1114 */
jhon309 0:c52df770855b 1115
jhon309 0:c52df770855b 1116 /** \brief __v7_all_cache - helper function
jhon309 0:c52df770855b 1117
jhon309 0:c52df770855b 1118 */
jhon309 0:c52df770855b 1119
jhon309 0:c52df770855b 1120 extern void __v7_all_cache(uint32_t op);
jhon309 0:c52df770855b 1121
jhon309 0:c52df770855b 1122
jhon309 0:c52df770855b 1123 /** \brief Invalidate the whole D$
jhon309 0:c52df770855b 1124
jhon309 0:c52df770855b 1125 DCISW. Invalidate by Set/Way
jhon309 0:c52df770855b 1126 */
jhon309 0:c52df770855b 1127
jhon309 0:c52df770855b 1128 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
jhon309 0:c52df770855b 1129 __v7_all_cache(0);
jhon309 0:c52df770855b 1130 }
jhon309 0:c52df770855b 1131
jhon309 0:c52df770855b 1132 /** \brief Clean the whole D$
jhon309 0:c52df770855b 1133
jhon309 0:c52df770855b 1134 DCCSW. Clean by Set/Way
jhon309 0:c52df770855b 1135 */
jhon309 0:c52df770855b 1136
jhon309 0:c52df770855b 1137 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
jhon309 0:c52df770855b 1138 __v7_all_cache(1);
jhon309 0:c52df770855b 1139 }
jhon309 0:c52df770855b 1140
jhon309 0:c52df770855b 1141 /** \brief Clean and invalidate the whole D$
jhon309 0:c52df770855b 1142
jhon309 0:c52df770855b 1143 DCCISW. Clean and Invalidate by Set/Way
jhon309 0:c52df770855b 1144 */
jhon309 0:c52df770855b 1145
jhon309 0:c52df770855b 1146 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
jhon309 0:c52df770855b 1147 __v7_all_cache(2);
jhon309 0:c52df770855b 1148 }
jhon309 0:c52df770855b 1149
jhon309 0:c52df770855b 1150 #include "core_ca_mmu.h"
jhon309 0:c52df770855b 1151
jhon309 0:c52df770855b 1152 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
jhon309 0:c52df770855b 1153
jhon309 0:c52df770855b 1154 #error TASKING Compiler support not implemented for Cortex-A
jhon309 0:c52df770855b 1155
jhon309 0:c52df770855b 1156 #endif
jhon309 0:c52df770855b 1157
jhon309 0:c52df770855b 1158 /*@} end of CMSIS_Core_RegAccFunctions */
jhon309 0:c52df770855b 1159
jhon309 0:c52df770855b 1160
jhon309 0:c52df770855b 1161 #endif /* __CORE_CAFUNC_H__ */