Kits Hennick / Mbed 2 deprecated EM100_Energy_Manager_power_saver

Energy Manager App

Dependencies:   C12832_lcd LM75B mbed-rtos mbed

Fork of rtos_mutex by avnish aggarwal

PowerControl.h@6:3b2a6cb895a9, 2013-09-20 (annotated)

Committer:
jesstvaldez
Date:
Fri Sep 20 04:12:04 2013 +0000
Revision:
6:3b2a6cb895a9
EM100 V1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jesstvaldez 6:3b2a6cb895a9 1 /* mbed PowerControl Library
jesstvaldez 6:3b2a6cb895a9 2 * Copyright (c) 2010 Michael Wei
jesstvaldez 6:3b2a6cb895a9 3 */
jesstvaldez 6:3b2a6cb895a9 4
jesstvaldez 6:3b2a6cb895a9 5 #ifndef MBED_POWERCONTROL_H
jesstvaldez 6:3b2a6cb895a9 6 #define MBED_POWERCONTROL_H
jesstvaldez 6:3b2a6cb895a9 7
jesstvaldez 6:3b2a6cb895a9 8 //shouldn't have to include, but fixes weird problems with defines
jesstvaldez 6:3b2a6cb895a9 9 //#include "LPC1768/LPC17xx.h"
jesstvaldez 6:3b2a6cb895a9 10
jesstvaldez 6:3b2a6cb895a9 11 //System Control Register
jesstvaldez 6:3b2a6cb895a9 12 // bit 0: Reserved
jesstvaldez 6:3b2a6cb895a9 13 // bit 1: Sleep on Exit
jesstvaldez 6:3b2a6cb895a9 14 #define LPC1768_SCR_SLEEPONEXIT 0x2
jesstvaldez 6:3b2a6cb895a9 15 // bit 2: Deep Sleep
jesstvaldez 6:3b2a6cb895a9 16 #define LPC1768_SCR_SLEEPDEEP 0x4
jesstvaldez 6:3b2a6cb895a9 17 // bit 3: Resereved
jesstvaldez 6:3b2a6cb895a9 18 // bit 4: Send on Pending
jesstvaldez 6:3b2a6cb895a9 19 #define LPC1768_SCR_SEVONPEND 0x10
jesstvaldez 6:3b2a6cb895a9 20 // bit 5-31: Reserved
jesstvaldez 6:3b2a6cb895a9 21
jesstvaldez 6:3b2a6cb895a9 22 //Power Control Register
jesstvaldez 6:3b2a6cb895a9 23 // bit 0: Power mode control bit 0 (power-down mode)
jesstvaldez 6:3b2a6cb895a9 24 #define LPC1768_PCON_PM0 0x1
jesstvaldez 6:3b2a6cb895a9 25 // bit 1: Power mode control bit 1 (deep power-down mode)
jesstvaldez 6:3b2a6cb895a9 26 #define LPC1768_PCON_PM1 0x2
jesstvaldez 6:3b2a6cb895a9 27 // bit 2: Brown-out reduced power mode
jesstvaldez 6:3b2a6cb895a9 28 #define LPC1768_PCON_BODRPM 0x4
jesstvaldez 6:3b2a6cb895a9 29 // bit 3: Brown-out global disable
jesstvaldez 6:3b2a6cb895a9 30 #define LPC1768_PCON_BOGD 0x8
jesstvaldez 6:3b2a6cb895a9 31 // bit 4: Brown-out reset disable
jesstvaldez 6:3b2a6cb895a9 32 #define LPC1768_PCON_BORD 0x10
jesstvaldez 6:3b2a6cb895a9 33 // bit 5-7 : Reserved
jesstvaldez 6:3b2a6cb895a9 34 // bit 8: Sleep Mode Entry Flag
jesstvaldez 6:3b2a6cb895a9 35 #define LPC1768_PCON_SMFLAG 0x100
jesstvaldez 6:3b2a6cb895a9 36 // bit 9: Deep Sleep Entry Flag
jesstvaldez 6:3b2a6cb895a9 37 #define LPC1768_PCON_DSFLAG 0x200
jesstvaldez 6:3b2a6cb895a9 38 // bit 10: Power Down Entry Flag
jesstvaldez 6:3b2a6cb895a9 39 #define LPC1768_PCON_PDFLAG 0x400
jesstvaldez 6:3b2a6cb895a9 40 // bit 11: Deep Power Down Entry Flag
jesstvaldez 6:3b2a6cb895a9 41 #define LPC1768_PCON_DPDFLAG 0x800
jesstvaldez 6:3b2a6cb895a9 42 // bit 12-31: Reserved
jesstvaldez 6:3b2a6cb895a9 43
jesstvaldez 6:3b2a6cb895a9 44 //"Sleep Mode" (WFI).
jesstvaldez 6:3b2a6cb895a9 45 inline void Sleep(void)
jesstvaldez 6:3b2a6cb895a9 46 {
jesstvaldez 6:3b2a6cb895a9 47 __WFI();
jesstvaldez 6:3b2a6cb895a9 48 }
jesstvaldez 6:3b2a6cb895a9 49
jesstvaldez 6:3b2a6cb895a9 50 //"Deep Sleep" Mode
jesstvaldez 6:3b2a6cb895a9 51 inline void DeepSleep(void)
jesstvaldez 6:3b2a6cb895a9 52 {
jesstvaldez 6:3b2a6cb895a9 53 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
jesstvaldez 6:3b2a6cb895a9 54 __WFI();
jesstvaldez 6:3b2a6cb895a9 55 }
jesstvaldez 6:3b2a6cb895a9 56
jesstvaldez 6:3b2a6cb895a9 57 //"Power-Down" Mode
jesstvaldez 6:3b2a6cb895a9 58 inline void PowerDown(void)
jesstvaldez 6:3b2a6cb895a9 59 {
jesstvaldez 6:3b2a6cb895a9 60 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
jesstvaldez 6:3b2a6cb895a9 61 LPC_SC->PCON &= ~LPC1768_PCON_PM1;
jesstvaldez 6:3b2a6cb895a9 62 LPC_SC->PCON |= LPC1768_PCON_PM0;
jesstvaldez 6:3b2a6cb895a9 63 __WFI();
jesstvaldez 6:3b2a6cb895a9 64 //reset back to normal
jesstvaldez 6:3b2a6cb895a9 65 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
jesstvaldez 6:3b2a6cb895a9 66 }
jesstvaldez 6:3b2a6cb895a9 67
jesstvaldez 6:3b2a6cb895a9 68 //"Deep Power-Down" Mode
jesstvaldez 6:3b2a6cb895a9 69 inline void DeepPowerDown(void)
jesstvaldez 6:3b2a6cb895a9 70 {
jesstvaldez 6:3b2a6cb895a9 71 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
jesstvaldez 6:3b2a6cb895a9 72 LPC_SC->PCON |= LPC1768_PCON_PM1 | LPC1768_PCON_PM0;
jesstvaldez 6:3b2a6cb895a9 73 __WFI();
jesstvaldez 6:3b2a6cb895a9 74 //reset back to normal
jesstvaldez 6:3b2a6cb895a9 75 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
jesstvaldez 6:3b2a6cb895a9 76 }
jesstvaldez 6:3b2a6cb895a9 77
jesstvaldez 6:3b2a6cb895a9 78 //shut down BOD during power-down/deep sleep
jesstvaldez 6:3b2a6cb895a9 79 inline void BrownOut_ReducedPowerMode_Enable(void)
jesstvaldez 6:3b2a6cb895a9 80 {
jesstvaldez 6:3b2a6cb895a9 81 LPC_SC->PCON |= LPC1768_PCON_BODRPM;
jesstvaldez 6:3b2a6cb895a9 82 }
jesstvaldez 6:3b2a6cb895a9 83
jesstvaldez 6:3b2a6cb895a9 84 //turn on BOD during power-down/deep sleep
jesstvaldez 6:3b2a6cb895a9 85 inline void BrownOut_ReducedPowerMode_Disable(void)
jesstvaldez 6:3b2a6cb895a9 86 {
jesstvaldez 6:3b2a6cb895a9 87 LPC_SC->PCON &= ~LPC1768_PCON_BODRPM;
jesstvaldez 6:3b2a6cb895a9 88 }
jesstvaldez 6:3b2a6cb895a9 89
jesstvaldez 6:3b2a6cb895a9 90 //turn off brown out circutry
jesstvaldez 6:3b2a6cb895a9 91 inline void BrownOut_Global_Disable(void)
jesstvaldez 6:3b2a6cb895a9 92 {
jesstvaldez 6:3b2a6cb895a9 93 LPC_SC->PCON |= LPC1768_PCON_BOGD;
jesstvaldez 6:3b2a6cb895a9 94 }
jesstvaldez 6:3b2a6cb895a9 95
jesstvaldez 6:3b2a6cb895a9 96 //turn on brown out circutry
jesstvaldez 6:3b2a6cb895a9 97 inline void BrownOut_Global_Enable(void)
jesstvaldez 6:3b2a6cb895a9 98 {
jesstvaldez 6:3b2a6cb895a9 99 LPC_SC->PCON &= !LPC1768_PCON_BOGD;
jesstvaldez 6:3b2a6cb895a9 100 }
jesstvaldez 6:3b2a6cb895a9 101
jesstvaldez 6:3b2a6cb895a9 102 //turn off brown out reset circutry
jesstvaldez 6:3b2a6cb895a9 103 inline void BrownOut_Reset_Disable(void)
jesstvaldez 6:3b2a6cb895a9 104 {
jesstvaldez 6:3b2a6cb895a9 105 LPC_SC->PCON |= LPC1768_PCON_BORD;
jesstvaldez 6:3b2a6cb895a9 106 }
jesstvaldez 6:3b2a6cb895a9 107
jesstvaldez 6:3b2a6cb895a9 108 //turn on brown outreset circutry
jesstvaldez 6:3b2a6cb895a9 109 inline void BrownOut_Reset_Enable(void)
jesstvaldez 6:3b2a6cb895a9 110 {
jesstvaldez 6:3b2a6cb895a9 111 LPC_SC->PCON &= ~LPC1768_PCON_BORD;
jesstvaldez 6:3b2a6cb895a9 112 }
jesstvaldez 6:3b2a6cb895a9 113 //Peripheral Control Register
jesstvaldez 6:3b2a6cb895a9 114 // bit 0: Reserved
jesstvaldez 6:3b2a6cb895a9 115 // bit 1: PCTIM0: Timer/Counter 0 power/clock enable
jesstvaldez 6:3b2a6cb895a9 116 #define LPC1768_PCONP_PCTIM0 0x2
jesstvaldez 6:3b2a6cb895a9 117 // bit 2: PCTIM1: Timer/Counter 1 power/clock enable
jesstvaldez 6:3b2a6cb895a9 118 #define LPC1768_PCONP_PCTIM1 0x4
jesstvaldez 6:3b2a6cb895a9 119 // bit 3: PCUART0: UART 0 power/clock enable
jesstvaldez 6:3b2a6cb895a9 120 #define LPC1768_PCONP_PCUART0 0x8
jesstvaldez 6:3b2a6cb895a9 121 // bit 4: PCUART1: UART 1 power/clock enable
jesstvaldez 6:3b2a6cb895a9 122 #define LPC1768_PCONP_PCUART1 0x10
jesstvaldez 6:3b2a6cb895a9 123 // bit 5: Reserved
jesstvaldez 6:3b2a6cb895a9 124 // bit 6: PCPWM1: PWM 1 power/clock enable
jesstvaldez 6:3b2a6cb895a9 125 #define LPC1768_PCONP_PCPWM1 0x40
jesstvaldez 6:3b2a6cb895a9 126 // bit 7: PCI2C0: I2C interface 0 power/clock enable
jesstvaldez 6:3b2a6cb895a9 127 #define LPC1768_PCONP_PCI2C0 0x80
jesstvaldez 6:3b2a6cb895a9 128 // bit 8: PCSPI: SPI interface power/clock enable
jesstvaldez 6:3b2a6cb895a9 129 #define LPC1768_PCONP_PCSPI 0x100
jesstvaldez 6:3b2a6cb895a9 130 // bit 9: PCRTC: RTC power/clock enable
jesstvaldez 6:3b2a6cb895a9 131 #define LPC1768_PCONP_PCRTC 0x200
jesstvaldez 6:3b2a6cb895a9 132 // bit 10: PCSSP1: SSP interface 1 power/clock enable
jesstvaldez 6:3b2a6cb895a9 133 #define LPC1768_PCONP_PCSSP1 0x400
jesstvaldez 6:3b2a6cb895a9 134 // bit 11: Reserved
jesstvaldez 6:3b2a6cb895a9 135 // bit 12: PCADC: A/D converter power/clock enable
jesstvaldez 6:3b2a6cb895a9 136 #define LPC1768_PCONP_PCADC 0x1000
jesstvaldez 6:3b2a6cb895a9 137 // bit 13: PCCAN1: CAN controller 1 power/clock enable
jesstvaldez 6:3b2a6cb895a9 138 #define LPC1768_PCONP_PCCAN1 0x2000
jesstvaldez 6:3b2a6cb895a9 139 // bit 14: PCCAN2: CAN controller 2 power/clock enable
jesstvaldez 6:3b2a6cb895a9 140 #define LPC1768_PCONP_PCCAN2 0x4000
jesstvaldez 6:3b2a6cb895a9 141 // bit 15: PCGPIO: GPIOs power/clock enable
jesstvaldez 6:3b2a6cb895a9 142 #define LPC1768_PCONP_PCGPIO 0x8000
jesstvaldez 6:3b2a6cb895a9 143 // bit 16: PCRIT: Repetitive interrupt timer power/clock enable
jesstvaldez 6:3b2a6cb895a9 144 #define LPC1768_PCONP_PCRIT 0x10000
jesstvaldez 6:3b2a6cb895a9 145 // bit 17: PCMCPWM: Motor control PWM power/clock enable
jesstvaldez 6:3b2a6cb895a9 146 #define LPC1768_PCONP_PCMCPWM 0x20000
jesstvaldez 6:3b2a6cb895a9 147 // bit 18: PCQEI: Quadrature encoder interface power/clock enable
jesstvaldez 6:3b2a6cb895a9 148 #define LPC1768_PCONP_PCQEI 0x40000
jesstvaldez 6:3b2a6cb895a9 149 // bit 19: PCI2C1: I2C interface 1 power/clock enable
jesstvaldez 6:3b2a6cb895a9 150 #define LPC1768_PCONP_PCI2C1 0x80000
jesstvaldez 6:3b2a6cb895a9 151 // bit 20: Reserved
jesstvaldez 6:3b2a6cb895a9 152 // bit 21: PCSSP0: SSP interface 0 power/clock enable
jesstvaldez 6:3b2a6cb895a9 153 #define LPC1768_PCONP_PCSSP0 0x200000
jesstvaldez 6:3b2a6cb895a9 154 // bit 22: PCTIM2: Timer 2 power/clock enable
jesstvaldez 6:3b2a6cb895a9 155 #define LPC1768_PCONP_PCTIM2 0x400000
jesstvaldez 6:3b2a6cb895a9 156 // bit 23: PCTIM3: Timer 3 power/clock enable
jesstvaldez 6:3b2a6cb895a9 157 #define LPC1768_PCONP_PCQTIM3 0x800000
jesstvaldez 6:3b2a6cb895a9 158 // bit 24: PCUART2: UART 2 power/clock enable
jesstvaldez 6:3b2a6cb895a9 159 #define LPC1768_PCONP_PCUART2 0x1000000
jesstvaldez 6:3b2a6cb895a9 160 // bit 25: PCUART3: UART 3 power/clock enable
jesstvaldez 6:3b2a6cb895a9 161 #define LPC1768_PCONP_PCUART3 0x2000000
jesstvaldez 6:3b2a6cb895a9 162 // bit 26: PCI2C2: I2C interface 2 power/clock enable
jesstvaldez 6:3b2a6cb895a9 163 #define LPC1768_PCONP_PCI2C2 0x4000000
jesstvaldez 6:3b2a6cb895a9 164 // bit 27: PCI2S: I2S interface power/clock enable
jesstvaldez 6:3b2a6cb895a9 165 #define LPC1768_PCONP_PCI2S 0x8000000
jesstvaldez 6:3b2a6cb895a9 166 // bit 28: Reserved
jesstvaldez 6:3b2a6cb895a9 167 // bit 29: PCGPDMA: GP DMA function power/clock enable
jesstvaldez 6:3b2a6cb895a9 168 #define LPC1768_PCONP_PCGPDMA 0x20000000
jesstvaldez 6:3b2a6cb895a9 169 // bit 30: PCENET: Ethernet block power/clock enable
jesstvaldez 6:3b2a6cb895a9 170 #define LPC1768_PCONP_PCENET 0x40000000
jesstvaldez 6:3b2a6cb895a9 171 // bit 31: PCUSB: USB interface power/clock enable
jesstvaldez 6:3b2a6cb895a9 172 #define LPC1768_PCONP_PCUSB 0x80000000
jesstvaldez 6:3b2a6cb895a9 173
jesstvaldez 6:3b2a6cb895a9 174 //Powers Up specified Peripheral(s)
jesstvaldez 6:3b2a6cb895a9 175 inline unsigned int Peripheral_PowerUp(unsigned int bitMask)
jesstvaldez 6:3b2a6cb895a9 176 {
jesstvaldez 6:3b2a6cb895a9 177 return LPC_SC->PCONP |= bitMask;
jesstvaldez 6:3b2a6cb895a9 178 }
jesstvaldez 6:3b2a6cb895a9 179
jesstvaldez 6:3b2a6cb895a9 180 //Powers Down specified Peripheral(s)
jesstvaldez 6:3b2a6cb895a9 181 inline unsigned int Peripheral_PowerDown(unsigned int bitMask)
jesstvaldez 6:3b2a6cb895a9 182 {
jesstvaldez 6:3b2a6cb895a9 183 return LPC_SC->PCONP &= ~bitMask;
jesstvaldez 6:3b2a6cb895a9 184 }
jesstvaldez 6:3b2a6cb895a9 185
jesstvaldez 6:3b2a6cb895a9 186 //returns if the peripheral is on or off
jesstvaldez 6:3b2a6cb895a9 187 inline bool Peripheral_GetStatus(unsigned int peripheral)
jesstvaldez 6:3b2a6cb895a9 188 {
jesstvaldez 6:3b2a6cb895a9 189 return (LPC_SC->PCONP & peripheral) ? true : false;
jesstvaldez 6:3b2a6cb895a9 190 }
jesstvaldez 6:3b2a6cb895a9 191
jesstvaldez 6:3b2a6cb895a9 192 #endif