CT32B0_PWM.cpp

00001  /**
00002  * @file    CT32B0_PWM.cpp
00003  * @brief   Small driver to user CT32B0 for PWM
00004  *
00005  * @author  Jeroen Lodder
00006  * @date        Oktober 2013
00007  *
00008  * @note        Since only one timer is used to supply 4 PWM channels 
00009  *                  a problem occurs because CT32B0 only support 3 PWM channels.
00010  *                  
00011  *                  Since this software is designed for a H-Bridge implementation 
00012  *                  only 2 of 4 PWM channels are required to be active simultaneously.
00013  *                  
00014  *                  This is where the stage variable comes in:
00015  *                  Stage 0: PWM enabled on MAT 0, MAT 1 and MAT 2.
00016  *                  Stage 1: PWM enabled on MAT 0, MAT 1 and MAT 3.
00017  *                  Unused MAT outputs will be pullled down.
00018  * @{
00019  */
00020 #include "mbed.h"
00021 #include "CT32B0_PWM.h"
00022 
00023 // Prescaler 48 gives 1 us per tick
00024 #define CT32B0_PRESCALER 48     /**< @brief Timer prescaler from AHBCLK */  
00025 
00026 /* Static makes them private to this module */
00027 volatile static uint8_t  stage      = 0;    /**< @brief Stage identifier for mat2/3 swap */
00028 volatile static uint32_t period     = 0;    /**< @brief PWM Period register */
00029 volatile static uint32_t mat[4];            /**< @brief PWM Mat output registers */
00030 volatile static uint32_t default_period_us; /**< @brief Given period in us */
00031 volatile static uint32_t defaultstate;      /**< @brief Default PWM state on init */
00032 
00033 /**
00034  * @brief   Initializes PWM
00035  *
00036  * @param[in] period_us     Period in us, when prescaler is 48
00037  * @param[in] defaultstate  State after initializing
00038  * @note Run Start() to start pwm
00039  */
00040 void CT32B0_initpwm(uint32_t period_us, uint32_t defaultstate){
00041         // Calculte period
00042         period = period_us;
00043 
00044         // Store latest setting
00045         mat[0] = defaultstate;
00046         mat[1] = defaultstate;
00047         mat[2] = defaultstate;
00048         mat[3] = defaultstate;
00049     
00050         LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6)|(1<<9);
00051 
00052         LPC_CT32B0->IR      = 0x5F;                         // Clear int 
00053         LPC_CT32B0->TCR     = 2;                                // Reset
00054         LPC_CT32B0->PR      = CT32B0_PRESCALER; 
00055         LPC_CT32B0->CCR     = 0;    // No capture
00056         LPC_CT32B0->EMR     =   0;  // Not required, refer to PWMC
00057         LPC_CT32B0->CTCR    =   0;  // No special counters mode
00058         
00059         // Set outputs to stage
00060         if(!stage){
00061             // Stage 0, use MAT2 as period
00062             LPC_CT32B0->PWMC        =   (1<<0)|(1<<1)|(0<<2)|(1<<3);
00063             LPC_CT32B0->MCR         = (1<<7);               // Reset on MR2
00064             LPC_CT32B0->MR2         = period;
00065             LPC_CT32B0->MR3         = defaultstate;
00066             
00067             LPC_GPIO->DIR[1]        |= (1<<26);     // Disable P1_26
00068             LPC_GPIO->CLR[1]        = (1<<26);
00069             LPC_IOCON->PIO1_26  = 0x0;  // Change pin mode
00070             LPC_IOCON->PIO1_27  = 0x1;
00071         }else{
00072             // Stage 1, use MAT3 as period
00073             LPC_CT32B0->PWMC        =   (1<<0)|(1<<1)|(1<<2)|(0<<3);
00074             LPC_CT32B0->MCR         = (1<<10);          //Reset on MR3
00075             LPC_CT32B0->MR2         = defaultstate;
00076             LPC_CT32B0->MR3         = period;
00077             
00078             LPC_GPIO->DIR[1]        |= (1<<27);         // Disable P1_27            
00079             LPC_GPIO->CLR[1]        = (1<<27);  
00080             LPC_IOCON->PIO1_26  = 0x1;  
00081             LPC_IOCON->PIO1_27  = 0x0; // Change pin mode
00082         }
00083         
00084         // MAT 1 and MAT 2 are not affected by stage
00085         LPC_CT32B0->MR0 = defaultstate; 
00086         LPC_CT32B0->MR1 = defaultstate;
00087         LPC_IOCON->PIO1_24 = 0x1; // Change pin mode
00088     LPC_IOCON->PIO1_25 = 0x1; // Change pin mode
00089         
00090         LPC_CT32B0->TCR     = 0;
00091 }
00092 
00093 /**
00094  * @brief   Re-Initializes PWM
00095  */
00096 void CT32B0_reinitpwm(void){
00097     CT32B0_initpwm(default_period_us,defaultstate   );
00098 }
00099 
00100 /**
00101  * @brief   Start PWM
00102  */
00103 void CT32B0_start(void){
00104     LPC_CT32B0->TCR     = 1;        // Enable
00105 }
00106 
00107 /**
00108  * @brief   Stop PWM
00109  * @param[in] state     PWM output state when pwm disabled
00110  */
00111 void CT32B0_deinit(uint8_t state){
00112   LPC_CT32B0->TCR       = 2;        // Disable and reset counter
00113     // Set all to GPIO
00114     LPC_IOCON->PIO1_24 = 0;
00115   LPC_IOCON->PIO1_25 = 0;
00116     LPC_IOCON->PIO1_26 = 0;
00117     LPC_IOCON->PIO1_27 = 0;
00118     LPC_GPIO->DIR[1]     |= (1<<24)|(1<<25)|(1<<26)|(1<<27);
00119     if(state)
00120         LPC_GPIO->SET[1]    = (1<<24)|(1<<25)|(1<<26)|(1<<27);
00121     else
00122         LPC_GPIO->CLR[1]    = (1<<24)|(1<<25)|(1<<26)|(1<<27);
00123 }
00124 
00125 /**
00126  * @brief   Set stage
00127  * @param[in]   stagearg    1 or 0
00128  */
00129 void CT32B0_stage(uint8_t stagearg){
00130     stage = stagearg;
00131     // Set outputs to stage
00132     if(!stage){
00133         // Stage 0, use MAT2 as period
00134         LPC_CT32B0->PWMC        =   (1<<0)|(1<<1)|(0<<2)|(1<<3);
00135         LPC_CT32B0->MCR         = (1<<7);       // Reset on MR2
00136         LPC_CT32B0->MR2         = period;
00137         LPC_CT32B0->MR3         =   mat[3];
00138         LPC_GPIO->CLR[1]        = (1<<26);
00139         LPC_GPIO->SET[1]        = (1<<27);
00140         LPC_IOCON->PIO1_26  = 0x0;  // GPIO
00141         LPC_IOCON->PIO1_27  = 0x1;
00142     }else{
00143         // Stage 1, use MAT3 as period
00144         LPC_CT32B0->PWMC        =   (1<<0)|(1<<1)|(1<<2)|(0<<3);
00145         LPC_CT32B0->MCR         = (1<<10);  //Reset on MR3
00146         LPC_CT32B0->MR2         =   mat[2];
00147         LPC_CT32B0->MR3         = period;
00148         LPC_GPIO->CLR[1]        = (1<<27);
00149         LPC_GPIO->SET[1]        = (1<<26);
00150         LPC_IOCON->PIO1_26  = 0x1;
00151         LPC_IOCON->PIO1_27  = 0x0;  // GPIO
00152     }
00153 }
00154 
00155 /**
00156  * @brief  Reload all match compare registers
00157  */
00158 void CT32B0_reload_mat(void){
00159     LPC_CT32B0->MR0 = mat[0]; 
00160     LPC_CT32B0->MR1 = mat[1];
00161     if(!stage){
00162     LPC_CT32B0->MR3 = mat[3]; 
00163     }else{
00164       LPC_CT32B0->MR2 = mat[2];
00165     }
00166 }
00167 
00168 /**
00169  * @brief   Set channel PWM
00170  */
00171 void CT32B0_set(uint8_t matnr, uint32_t value){
00172     mat[matnr] = value;
00173     CT32B0_reload_mat();
00174 }
00175 
00176 /**
00177  * @brief   Wait for timer to reach 0
00178  */
00179 void CT32B0_wait_refresh(void){
00180     if( (LPC_CT32B0->TCR & 1) )
00181         while(LPC_CT32B0->TC != 0);
00182 }
00183 /**
00184  * @}
00185  */
00186