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targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg322f64.h@50:a417edff4437, 2016-01-15 (annotated)

Committer:
mbed_official
Date:
Fri Jan 15 07:45:16 2016 +0000
Revision:
50:a417edff4437
Parent:
0:9b334a45a8ff 
Synchronized with git revision 6010f32619bfcbb01cc73747d4ff9040863482d9



Full URL: https://github.com/mbedmicro/mbed/commit/6010f32619bfcbb01cc73747d4ff9040863482d9/



Remove doubling of buffer size in realiseEndpoint()

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 2 * @file efm32hg322f64.h
bogdanm 0:9b334a45a8ff 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
bogdanm 0:9b334a45a8ff 4 * for EFM32HG322F64
mbed_official 50:a417edff4437 5 * @version 4.2.0
bogdanm 0:9b334a45a8ff 6 ******************************************************************************
bogdanm 0:9b334a45a8ff 7 * @section License
mbed_official 50:a417edff4437 8 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
bogdanm 0:9b334a45a8ff 9 ******************************************************************************
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * Permission is granted to anyone to use this software for any purpose,
bogdanm 0:9b334a45a8ff 12 * including commercial applications, and to alter it and redistribute it
bogdanm 0:9b334a45a8ff 13 * freely, subject to the following restrictions:
bogdanm 0:9b334a45a8ff 14 *
bogdanm 0:9b334a45a8ff 15 * 1. The origin of this software must not be misrepresented; you must not
bogdanm 0:9b334a45a8ff 16 * claim that you wrote the original software.@n
bogdanm 0:9b334a45a8ff 17 * 2. Altered source versions must be plainly marked as such, and must not be
bogdanm 0:9b334a45a8ff 18 * misrepresented as being the original software.@n
bogdanm 0:9b334a45a8ff 19 * 3. This notice may not be removed or altered from any source distribution.
bogdanm 0:9b334a45a8ff 20 *
bogdanm 0:9b334a45a8ff 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
bogdanm 0:9b334a45a8ff 22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
bogdanm 0:9b334a45a8ff 23 * providing the Software "AS IS", with no express or implied warranties of any
bogdanm 0:9b334a45a8ff 24 * kind, including, but not limited to, any implied warranties of
bogdanm 0:9b334a45a8ff 25 * merchantability or fitness for any particular purpose or warranties against
bogdanm 0:9b334a45a8ff 26 * infringement of any proprietary rights of a third party.
bogdanm 0:9b334a45a8ff 27 *
bogdanm 0:9b334a45a8ff 28 * Silicon Laboratories, Inc. will not be liable for any consequential,
bogdanm 0:9b334a45a8ff 29 * incidental, or special damages, or any other relief, or for any claim by
bogdanm 0:9b334a45a8ff 30 * any third party, arising from your use of this Software.
bogdanm 0:9b334a45a8ff 31 *
bogdanm 0:9b334a45a8ff 32 *****************************************************************************/
bogdanm 0:9b334a45a8ff 33
mbed_official 50:a417edff4437 34 #ifndef EFM32HG322F64_H
mbed_official 50:a417edff4437 35 #define EFM32HG322F64_H
bogdanm 0:9b334a45a8ff 36
bogdanm 0:9b334a45a8ff 37 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 38 extern "C" {
bogdanm 0:9b334a45a8ff 39 #endif
bogdanm 0:9b334a45a8ff 40
bogdanm 0:9b334a45a8ff 41 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 42 * @addtogroup Parts
bogdanm 0:9b334a45a8ff 43 * @{
bogdanm 0:9b334a45a8ff 44 *****************************************************************************/
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 47 * @defgroup EFM32HG322F64 EFM32HG322F64
bogdanm 0:9b334a45a8ff 48 * @{
bogdanm 0:9b334a45a8ff 49 *****************************************************************************/
bogdanm 0:9b334a45a8ff 50
bogdanm 0:9b334a45a8ff 51 /** Interrupt Number Definition */
bogdanm 0:9b334a45a8ff 52 typedef enum IRQn
bogdanm 0:9b334a45a8ff 53 {
bogdanm 0:9b334a45a8ff 54 /****** Cortex-M0+ Processor Exceptions Numbers *****************************************/
bogdanm 0:9b334a45a8ff 55 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M0+ Non Maskable Interrupt */
bogdanm 0:9b334a45a8ff 56 HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
bogdanm 0:9b334a45a8ff 57 SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
bogdanm 0:9b334a45a8ff 58 PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
bogdanm 0:9b334a45a8ff 59 SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 /****** EFM32HG Peripheral Interrupt Numbers *********************************************/
bogdanm 0:9b334a45a8ff 62 DMA_IRQn = 0, /*!< 16+0 EFM32 DMA Interrupt */
bogdanm 0:9b334a45a8ff 63 GPIO_EVEN_IRQn = 1, /*!< 16+1 EFM32 GPIO_EVEN Interrupt */
bogdanm 0:9b334a45a8ff 64 TIMER0_IRQn = 2, /*!< 16+2 EFM32 TIMER0 Interrupt */
bogdanm 0:9b334a45a8ff 65 ACMP0_IRQn = 3, /*!< 16+3 EFM32 ACMP0 Interrupt */
bogdanm 0:9b334a45a8ff 66 ADC0_IRQn = 4, /*!< 16+4 EFM32 ADC0 Interrupt */
bogdanm 0:9b334a45a8ff 67 I2C0_IRQn = 5, /*!< 16+5 EFM32 I2C0 Interrupt */
bogdanm 0:9b334a45a8ff 68 GPIO_ODD_IRQn = 6, /*!< 16+6 EFM32 GPIO_ODD Interrupt */
bogdanm 0:9b334a45a8ff 69 TIMER1_IRQn = 7, /*!< 16+7 EFM32 TIMER1 Interrupt */
bogdanm 0:9b334a45a8ff 70 USART1_RX_IRQn = 8, /*!< 16+8 EFM32 USART1_RX Interrupt */
bogdanm 0:9b334a45a8ff 71 USART1_TX_IRQn = 9, /*!< 16+9 EFM32 USART1_TX Interrupt */
bogdanm 0:9b334a45a8ff 72 LEUART0_IRQn = 10, /*!< 16+10 EFM32 LEUART0 Interrupt */
bogdanm 0:9b334a45a8ff 73 PCNT0_IRQn = 11, /*!< 16+11 EFM32 PCNT0 Interrupt */
bogdanm 0:9b334a45a8ff 74 RTC_IRQn = 12, /*!< 16+12 EFM32 RTC Interrupt */
bogdanm 0:9b334a45a8ff 75 CMU_IRQn = 13, /*!< 16+13 EFM32 CMU Interrupt */
bogdanm 0:9b334a45a8ff 76 VCMP_IRQn = 14, /*!< 16+14 EFM32 VCMP Interrupt */
bogdanm 0:9b334a45a8ff 77 MSC_IRQn = 15, /*!< 16+15 EFM32 MSC Interrupt */
bogdanm 0:9b334a45a8ff 78 AES_IRQn = 16, /*!< 16+16 EFM32 AES Interrupt */
bogdanm 0:9b334a45a8ff 79 USART0_RX_IRQn = 17, /*!< 16+17 EFM32 USART0_RX Interrupt */
bogdanm 0:9b334a45a8ff 80 USART0_TX_IRQn = 18, /*!< 16+18 EFM32 USART0_TX Interrupt */
bogdanm 0:9b334a45a8ff 81 USB_IRQn = 19, /*!< 16+19 EFM32 USB Interrupt */
bogdanm 0:9b334a45a8ff 82 TIMER2_IRQn = 20, /*!< 16+20 EFM32 TIMER2 Interrupt */
bogdanm 0:9b334a45a8ff 83 } IRQn_Type;
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 86 * @defgroup EFM32HG322F64_Core EFM32HG322F64 Core
bogdanm 0:9b334a45a8ff 87 * @{
bogdanm 0:9b334a45a8ff 88 * @brief Processor and Core Peripheral Section
bogdanm 0:9b334a45a8ff 89 *****************************************************************************/
bogdanm 0:9b334a45a8ff 90 #define __MPU_PRESENT 0 /**< MPU not present */
bogdanm 0:9b334a45a8ff 91 #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
bogdanm 0:9b334a45a8ff 92 #define __NVIC_PRIO_BITS 2 /**< NVIC interrupt priority bits */
bogdanm 0:9b334a45a8ff 93 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
bogdanm 0:9b334a45a8ff 94
bogdanm 0:9b334a45a8ff 95 /** @} End of group EFM32HG322F64_Core */
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 98 * @defgroup EFM32HG322F64_Part EFM32HG322F64 Part
bogdanm 0:9b334a45a8ff 99 * @{
bogdanm 0:9b334a45a8ff 100 ******************************************************************************/
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102 /** Part family */
bogdanm 0:9b334a45a8ff 103 #define _EFM32_HAPPY_FAMILY 1 /**< Happy Gecko EFM32HG MCU Family */
bogdanm 0:9b334a45a8ff 104 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
bogdanm 0:9b334a45a8ff 105 #define _SILICON_LABS_32B_PLATFORM_1 /**< Silicon Labs platform name */
bogdanm 0:9b334a45a8ff 106 #define _SILICON_LABS_32B_PLATFORM 1 /**< Silicon Labs platform name */
bogdanm 0:9b334a45a8ff 107
bogdanm 0:9b334a45a8ff 108 /* If part number is not defined as compiler option, define it */
bogdanm 0:9b334a45a8ff 109 #if !defined(EFM32HG322F64)
bogdanm 0:9b334a45a8ff 110 #define EFM32HG322F64 1 /**< Happy Gecko Part */
bogdanm 0:9b334a45a8ff 111 #endif
bogdanm 0:9b334a45a8ff 112
bogdanm 0:9b334a45a8ff 113 /** Configure part number */
bogdanm 0:9b334a45a8ff 114 #define PART_NUMBER "EFM32HG322F64" /**< Part Number */
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 /** Memory Base addresses and limits */
bogdanm 0:9b334a45a8ff 117 #define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
bogdanm 0:9b334a45a8ff 118 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
bogdanm 0:9b334a45a8ff 119 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
bogdanm 0:9b334a45a8ff 120 #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
bogdanm 0:9b334a45a8ff 121 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
bogdanm 0:9b334a45a8ff 122 #define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
bogdanm 0:9b334a45a8ff 123 #define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
bogdanm 0:9b334a45a8ff 124 #define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
bogdanm 0:9b334a45a8ff 125 #define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
bogdanm 0:9b334a45a8ff 126 #define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
bogdanm 0:9b334a45a8ff 127 #define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
bogdanm 0:9b334a45a8ff 128 #define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
bogdanm 0:9b334a45a8ff 129 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
bogdanm 0:9b334a45a8ff 130 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
bogdanm 0:9b334a45a8ff 131 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
bogdanm 0:9b334a45a8ff 132 #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
bogdanm 0:9b334a45a8ff 133 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
bogdanm 0:9b334a45a8ff 134 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
bogdanm 0:9b334a45a8ff 135 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
bogdanm 0:9b334a45a8ff 136 #define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
bogdanm 0:9b334a45a8ff 137 #define DEVICE_MEM_BASE ((uint32_t) 0xF0040000UL) /**< DEVICE base address */
bogdanm 0:9b334a45a8ff 138 #define DEVICE_MEM_SIZE ((uint32_t) 0x1000UL) /**< DEVICE available address space */
bogdanm 0:9b334a45a8ff 139 #define DEVICE_MEM_END ((uint32_t) 0xF0040FFFUL) /**< DEVICE end address */
bogdanm 0:9b334a45a8ff 140 #define DEVICE_MEM_BITS ((uint32_t) 0x12UL) /**< DEVICE used bits */
bogdanm 0:9b334a45a8ff 141 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
bogdanm 0:9b334a45a8ff 142 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
bogdanm 0:9b334a45a8ff 143 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
bogdanm 0:9b334a45a8ff 144 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 /** Flash and SRAM limits for EFM32HG322F64 */
bogdanm 0:9b334a45a8ff 147 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
bogdanm 0:9b334a45a8ff 148 #define FLASH_SIZE (0x00010000UL) /**< Available Flash Memory */
bogdanm 0:9b334a45a8ff 149 #define FLASH_PAGE_SIZE 1024 /**< Flash Memory page size */
bogdanm 0:9b334a45a8ff 150 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
bogdanm 0:9b334a45a8ff 151 #define SRAM_SIZE (0x00002000UL) /**< Available SRAM Memory */
bogdanm 0:9b334a45a8ff 152 #define __CM0PLUS_REV 0x001 /**< Cortex-M0+ Core revision r0p1 */
bogdanm 0:9b334a45a8ff 153 #define PRS_CHAN_COUNT 6 /**< Number of PRS channels */
bogdanm 0:9b334a45a8ff 154 #define DMA_CHAN_COUNT 6 /**< Number of DMA channels */
bogdanm 0:9b334a45a8ff 155
bogdanm 0:9b334a45a8ff 156 /** AF channels connect the different on-chip peripherals with the af-mux */
bogdanm 0:9b334a45a8ff 157 #define AFCHAN_MAX 42
bogdanm 0:9b334a45a8ff 158 #define AFCHANLOC_MAX 7
bogdanm 0:9b334a45a8ff 159 /** Analog AF channels */
bogdanm 0:9b334a45a8ff 160 #define AFACHAN_MAX 27
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162 /* Part number capabilities */
bogdanm 0:9b334a45a8ff 163
bogdanm 0:9b334a45a8ff 164 #define TIMER_PRESENT /**< TIMER is available in this part */
bogdanm 0:9b334a45a8ff 165 #define TIMER_COUNT 3 /**< 3 TIMERs available */
bogdanm 0:9b334a45a8ff 166 #define ACMP_PRESENT /**< ACMP is available in this part */
bogdanm 0:9b334a45a8ff 167 #define ACMP_COUNT 1 /**< 1 ACMPs available */
bogdanm 0:9b334a45a8ff 168 #define USART_PRESENT /**< USART is available in this part */
bogdanm 0:9b334a45a8ff 169 #define USART_COUNT 2 /**< 2 USARTs available */
bogdanm 0:9b334a45a8ff 170 #define IDAC_PRESENT /**< IDAC is available in this part */
bogdanm 0:9b334a45a8ff 171 #define IDAC_COUNT 1 /**< 1 IDACs available */
bogdanm 0:9b334a45a8ff 172 #define ADC_PRESENT /**< ADC is available in this part */
bogdanm 0:9b334a45a8ff 173 #define ADC_COUNT 1 /**< 1 ADCs available */
bogdanm 0:9b334a45a8ff 174 #define LEUART_PRESENT /**< LEUART is available in this part */
bogdanm 0:9b334a45a8ff 175 #define LEUART_COUNT 1 /**< 1 LEUARTs available */
bogdanm 0:9b334a45a8ff 176 #define PCNT_PRESENT /**< PCNT is available in this part */
bogdanm 0:9b334a45a8ff 177 #define PCNT_COUNT 1 /**< 1 PCNTs available */
bogdanm 0:9b334a45a8ff 178 #define I2C_PRESENT /**< I2C is available in this part */
bogdanm 0:9b334a45a8ff 179 #define I2C_COUNT 1 /**< 1 I2Cs available */
bogdanm 0:9b334a45a8ff 180 #define AES_PRESENT
bogdanm 0:9b334a45a8ff 181 #define AES_COUNT 1
bogdanm 0:9b334a45a8ff 182 #define DMA_PRESENT
bogdanm 0:9b334a45a8ff 183 #define DMA_COUNT 1
bogdanm 0:9b334a45a8ff 184 #define LE_PRESENT
bogdanm 0:9b334a45a8ff 185 #define LE_COUNT 1
bogdanm 0:9b334a45a8ff 186 #define USBC_PRESENT
bogdanm 0:9b334a45a8ff 187 #define USBC_COUNT 1
bogdanm 0:9b334a45a8ff 188 #define USBLE_PRESENT
bogdanm 0:9b334a45a8ff 189 #define USBLE_COUNT 1
bogdanm 0:9b334a45a8ff 190 #define USB_PRESENT
bogdanm 0:9b334a45a8ff 191 #define USB_COUNT 1
bogdanm 0:9b334a45a8ff 192 #define MSC_PRESENT
bogdanm 0:9b334a45a8ff 193 #define MSC_COUNT 1
bogdanm 0:9b334a45a8ff 194 #define EMU_PRESENT
bogdanm 0:9b334a45a8ff 195 #define EMU_COUNT 1
bogdanm 0:9b334a45a8ff 196 #define RMU_PRESENT
bogdanm 0:9b334a45a8ff 197 #define RMU_COUNT 1
bogdanm 0:9b334a45a8ff 198 #define CMU_PRESENT
bogdanm 0:9b334a45a8ff 199 #define CMU_COUNT 1
bogdanm 0:9b334a45a8ff 200 #define PRS_PRESENT
bogdanm 0:9b334a45a8ff 201 #define PRS_COUNT 1
bogdanm 0:9b334a45a8ff 202 #define GPIO_PRESENT
bogdanm 0:9b334a45a8ff 203 #define GPIO_COUNT 1
bogdanm 0:9b334a45a8ff 204 #define VCMP_PRESENT
bogdanm 0:9b334a45a8ff 205 #define VCMP_COUNT 1
bogdanm 0:9b334a45a8ff 206 #define RTC_PRESENT
bogdanm 0:9b334a45a8ff 207 #define RTC_COUNT 1
bogdanm 0:9b334a45a8ff 208 #define HFXTAL_PRESENT
bogdanm 0:9b334a45a8ff 209 #define HFXTAL_COUNT 1
bogdanm 0:9b334a45a8ff 210 #define LFXTAL_PRESENT
bogdanm 0:9b334a45a8ff 211 #define LFXTAL_COUNT 1
bogdanm 0:9b334a45a8ff 212 #define USHFRCO_PRESENT
bogdanm 0:9b334a45a8ff 213 #define USHFRCO_COUNT 1
bogdanm 0:9b334a45a8ff 214 #define WDOG_PRESENT
bogdanm 0:9b334a45a8ff 215 #define WDOG_COUNT 1
bogdanm 0:9b334a45a8ff 216 #define DBG_PRESENT
bogdanm 0:9b334a45a8ff 217 #define DBG_COUNT 1
bogdanm 0:9b334a45a8ff 218 #define MTB_PRESENT
bogdanm 0:9b334a45a8ff 219 #define MTB_COUNT 1
bogdanm 0:9b334a45a8ff 220 #define BOOTLOADER_PRESENT
bogdanm 0:9b334a45a8ff 221 #define BOOTLOADER_COUNT 1
bogdanm 0:9b334a45a8ff 222 #define ANALOG_PRESENT
bogdanm 0:9b334a45a8ff 223 #define ANALOG_COUNT 1
bogdanm 0:9b334a45a8ff 224
bogdanm 0:9b334a45a8ff 225 /** @} End of group EFM32HG322F64_Part */
bogdanm 0:9b334a45a8ff 226
mbed_official 50:a417edff4437 227 #ifndef ARM_MATH_CM0PLUS
mbed_official 50:a417edff4437 228 #define ARM_MATH_CM0PLUS
mbed_official 50:a417edff4437 229 #endif
bogdanm 0:9b334a45a8ff 230 #include "arm_math.h" /* To get __CLZ definitions etc. */
bogdanm 0:9b334a45a8ff 231 #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
bogdanm 0:9b334a45a8ff 232 #include "system_efm32hg.h" /* System Header */
bogdanm 0:9b334a45a8ff 233
bogdanm 0:9b334a45a8ff 234 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 235 * @defgroup EFM32HG322F64_Peripheral_TypeDefs EFM32HG322F64 Peripheral TypeDefs
bogdanm 0:9b334a45a8ff 236 * @{
bogdanm 0:9b334a45a8ff 237 * @brief Device Specific Peripheral Register Structures
bogdanm 0:9b334a45a8ff 238 *****************************************************************************/
bogdanm 0:9b334a45a8ff 239
bogdanm 0:9b334a45a8ff 240 #include "efm32hg_aes.h"
bogdanm 0:9b334a45a8ff 241 #include "efm32hg_dma_ch.h"
bogdanm 0:9b334a45a8ff 242 #include "efm32hg_dma.h"
bogdanm 0:9b334a45a8ff 243 #include "efm32hg_usb_diep.h"
bogdanm 0:9b334a45a8ff 244 #include "efm32hg_usb_doep.h"
bogdanm 0:9b334a45a8ff 245 #include "efm32hg_usb.h"
bogdanm 0:9b334a45a8ff 246 #include "efm32hg_msc.h"
bogdanm 0:9b334a45a8ff 247 #include "efm32hg_emu.h"
bogdanm 0:9b334a45a8ff 248 #include "efm32hg_rmu.h"
bogdanm 0:9b334a45a8ff 249 #include "efm32hg_cmu.h"
bogdanm 0:9b334a45a8ff 250 #include "efm32hg_timer_cc.h"
bogdanm 0:9b334a45a8ff 251 #include "efm32hg_timer.h"
bogdanm 0:9b334a45a8ff 252 #include "efm32hg_acmp.h"
bogdanm 0:9b334a45a8ff 253 #include "efm32hg_usart.h"
bogdanm 0:9b334a45a8ff 254 #include "efm32hg_prs_ch.h"
bogdanm 0:9b334a45a8ff 255 #include "efm32hg_prs.h"
bogdanm 0:9b334a45a8ff 256 #include "efm32hg_idac.h"
bogdanm 0:9b334a45a8ff 257 #include "efm32hg_gpio_p.h"
bogdanm 0:9b334a45a8ff 258 #include "efm32hg_gpio.h"
bogdanm 0:9b334a45a8ff 259 #include "efm32hg_vcmp.h"
bogdanm 0:9b334a45a8ff 260 #include "efm32hg_adc.h"
bogdanm 0:9b334a45a8ff 261 #include "efm32hg_leuart.h"
bogdanm 0:9b334a45a8ff 262 #include "efm32hg_pcnt.h"
bogdanm 0:9b334a45a8ff 263 #include "efm32hg_i2c.h"
bogdanm 0:9b334a45a8ff 264 #include "efm32hg_rtc.h"
bogdanm 0:9b334a45a8ff 265 #include "efm32hg_wdog.h"
bogdanm 0:9b334a45a8ff 266 #include "efm32hg_mtb.h"
bogdanm 0:9b334a45a8ff 267 #include "efm32hg_dma_descriptor.h"
bogdanm 0:9b334a45a8ff 268 #include "efm32hg_devinfo.h"
bogdanm 0:9b334a45a8ff 269 #include "efm32hg_romtable.h"
bogdanm 0:9b334a45a8ff 270 #include "efm32hg_calibrate.h"
bogdanm 0:9b334a45a8ff 271
bogdanm 0:9b334a45a8ff 272 /** @} End of group EFM32HG322F64_Peripheral_TypeDefs */
bogdanm 0:9b334a45a8ff 273
bogdanm 0:9b334a45a8ff 274 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 275 * @defgroup EFM32HG322F64_Peripheral_Base EFM32HG322F64 Peripheral Memory Map
bogdanm 0:9b334a45a8ff 276 * @{
bogdanm 0:9b334a45a8ff 277 *****************************************************************************/
bogdanm 0:9b334a45a8ff 278
bogdanm 0:9b334a45a8ff 279 #define AES_BASE (0x400E0000UL) /**< AES base address */
bogdanm 0:9b334a45a8ff 280 #define DMA_BASE (0x400C2000UL) /**< DMA base address */
bogdanm 0:9b334a45a8ff 281 #define USB_BASE (0x400C4000UL) /**< USB base address */
bogdanm 0:9b334a45a8ff 282 #define MSC_BASE (0x400C0000UL) /**< MSC base address */
bogdanm 0:9b334a45a8ff 283 #define EMU_BASE (0x400C6000UL) /**< EMU base address */
bogdanm 0:9b334a45a8ff 284 #define RMU_BASE (0x400CA000UL) /**< RMU base address */
bogdanm 0:9b334a45a8ff 285 #define CMU_BASE (0x400C8000UL) /**< CMU base address */
bogdanm 0:9b334a45a8ff 286 #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
bogdanm 0:9b334a45a8ff 287 #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
bogdanm 0:9b334a45a8ff 288 #define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
bogdanm 0:9b334a45a8ff 289 #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
bogdanm 0:9b334a45a8ff 290 #define USART0_BASE (0x4000C000UL) /**< USART0 base address */
bogdanm 0:9b334a45a8ff 291 #define USART1_BASE (0x4000C400UL) /**< USART1 base address */
bogdanm 0:9b334a45a8ff 292 #define PRS_BASE (0x400CC000UL) /**< PRS base address */
bogdanm 0:9b334a45a8ff 293 #define IDAC0_BASE (0x40004000UL) /**< IDAC0 base address */
bogdanm 0:9b334a45a8ff 294 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */
bogdanm 0:9b334a45a8ff 295 #define VCMP_BASE (0x40000000UL) /**< VCMP base address */
bogdanm 0:9b334a45a8ff 296 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
bogdanm 0:9b334a45a8ff 297 #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
bogdanm 0:9b334a45a8ff 298 #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
bogdanm 0:9b334a45a8ff 299 #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
bogdanm 0:9b334a45a8ff 300 #define RTC_BASE (0x40080000UL) /**< RTC base address */
bogdanm 0:9b334a45a8ff 301 #define WDOG_BASE (0x40088000UL) /**< WDOG base address */
bogdanm 0:9b334a45a8ff 302 #define MTB_BASE (0xF0040000UL) /**< MTB base address */
bogdanm 0:9b334a45a8ff 303 #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
bogdanm 0:9b334a45a8ff 304 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
bogdanm 0:9b334a45a8ff 305 #define ROMTABLE_BASE (0xF00FFFD0UL) /**< ROMTABLE base address */
bogdanm 0:9b334a45a8ff 306 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
bogdanm 0:9b334a45a8ff 307 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
bogdanm 0:9b334a45a8ff 308
bogdanm 0:9b334a45a8ff 309 /** @} End of group EFM32HG322F64_Peripheral_Base */
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 312 * @defgroup EFM32HG322F64_Peripheral_Declaration EFM32HG322F64 Peripheral Declarations
bogdanm 0:9b334a45a8ff 313 * @{
bogdanm 0:9b334a45a8ff 314 *****************************************************************************/
bogdanm 0:9b334a45a8ff 315
bogdanm 0:9b334a45a8ff 316 #define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
bogdanm 0:9b334a45a8ff 317 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
bogdanm 0:9b334a45a8ff 318 #define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
bogdanm 0:9b334a45a8ff 319 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
bogdanm 0:9b334a45a8ff 320 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
bogdanm 0:9b334a45a8ff 321 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
bogdanm 0:9b334a45a8ff 322 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
bogdanm 0:9b334a45a8ff 323 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
bogdanm 0:9b334a45a8ff 324 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
bogdanm 0:9b334a45a8ff 325 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
bogdanm 0:9b334a45a8ff 326 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
bogdanm 0:9b334a45a8ff 327 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
bogdanm 0:9b334a45a8ff 328 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
bogdanm 0:9b334a45a8ff 329 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
bogdanm 0:9b334a45a8ff 330 #define IDAC0 ((IDAC_TypeDef *) IDAC0_BASE) /**< IDAC0 base pointer */
bogdanm 0:9b334a45a8ff 331 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
bogdanm 0:9b334a45a8ff 332 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
bogdanm 0:9b334a45a8ff 333 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
bogdanm 0:9b334a45a8ff 334 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
bogdanm 0:9b334a45a8ff 335 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
bogdanm 0:9b334a45a8ff 336 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
bogdanm 0:9b334a45a8ff 337 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
bogdanm 0:9b334a45a8ff 338 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
bogdanm 0:9b334a45a8ff 339 #define MTB ((MTB_TypeDef *) MTB_BASE) /**< MTB base pointer */
bogdanm 0:9b334a45a8ff 340 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
bogdanm 0:9b334a45a8ff 341 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
bogdanm 0:9b334a45a8ff 342 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
bogdanm 0:9b334a45a8ff 343
bogdanm 0:9b334a45a8ff 344 /** @} End of group EFM32HG322F64_Peripheral_Declaration */
bogdanm 0:9b334a45a8ff 345
bogdanm 0:9b334a45a8ff 346 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 347 * @defgroup EFM32HG322F64_BitFields EFM32HG322F64 Bit Fields
bogdanm 0:9b334a45a8ff 348 * @{
bogdanm 0:9b334a45a8ff 349 *****************************************************************************/
bogdanm 0:9b334a45a8ff 350
bogdanm 0:9b334a45a8ff 351 #include "efm32hg_prs_signals.h"
bogdanm 0:9b334a45a8ff 352 #include "efm32hg_dmareq.h"
bogdanm 0:9b334a45a8ff 353 #include "efm32hg_dmactrl.h"
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 356 * @defgroup EFM32HG322F64_UNLOCK EFM32HG322F64 Unlock Codes
bogdanm 0:9b334a45a8ff 357 * @{
bogdanm 0:9b334a45a8ff 358 *****************************************************************************/
bogdanm 0:9b334a45a8ff 359 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
bogdanm 0:9b334a45a8ff 360 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
bogdanm 0:9b334a45a8ff 361 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
bogdanm 0:9b334a45a8ff 362 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
bogdanm 0:9b334a45a8ff 363 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
bogdanm 0:9b334a45a8ff 364
bogdanm 0:9b334a45a8ff 365 /** @} End of group EFM32HG322F64_UNLOCK */
bogdanm 0:9b334a45a8ff 366
bogdanm 0:9b334a45a8ff 367 /** @} End of group EFM32HG322F64_BitFields */
bogdanm 0:9b334a45a8ff 368
bogdanm 0:9b334a45a8ff 369 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 370 * @defgroup EFM32HG322F64_Alternate_Function EFM32HG322F64 Alternate Function
bogdanm 0:9b334a45a8ff 371 * @{
bogdanm 0:9b334a45a8ff 372 *****************************************************************************/
bogdanm 0:9b334a45a8ff 373
bogdanm 0:9b334a45a8ff 374 #include "efm32hg_af_ports.h"
bogdanm 0:9b334a45a8ff 375 #include "efm32hg_af_pins.h"
bogdanm 0:9b334a45a8ff 376
bogdanm 0:9b334a45a8ff 377 /** @} End of group EFM32HG322F64_Alternate_Function */
bogdanm 0:9b334a45a8ff 378
bogdanm 0:9b334a45a8ff 379 /**************************************************************************//**
bogdanm 0:9b334a45a8ff 380 * @brief Set the value of a bit field within a register.
bogdanm 0:9b334a45a8ff 381 *
bogdanm 0:9b334a45a8ff 382 * @param REG
bogdanm 0:9b334a45a8ff 383 * The register to update
bogdanm 0:9b334a45a8ff 384 * @param MASK
bogdanm 0:9b334a45a8ff 385 * The mask for the bit field to update
bogdanm 0:9b334a45a8ff 386 * @param VALUE
bogdanm 0:9b334a45a8ff 387 * The value to write to the bit field
bogdanm 0:9b334a45a8ff 388 * @param OFFSET
bogdanm 0:9b334a45a8ff 389 * The number of bits that the field is offset within the register.
bogdanm 0:9b334a45a8ff 390 * 0 (zero) means LSB.
bogdanm 0:9b334a45a8ff 391 *****************************************************************************/
bogdanm 0:9b334a45a8ff 392 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
bogdanm 0:9b334a45a8ff 393 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
bogdanm 0:9b334a45a8ff 394
bogdanm 0:9b334a45a8ff 395 /** @} End of group EFM32HG322F64 */
bogdanm 0:9b334a45a8ff 396
bogdanm 0:9b334a45a8ff 397 /** @} End of group Parts */
bogdanm 0:9b334a45a8ff 398
bogdanm 0:9b334a45a8ff 399 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 400 }
bogdanm 0:9b334a45a8ff 401 #endif
mbed_official 50:a417edff4437 402 #endif /* EFM32HG322F64_H */