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targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_rcc.h@0:9b334a45a8ff, 2015-10-01 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Oct 01 15:25:22 2015 +0300
- Revision:
- 0:9b334a45a8ff
Initial commit on mbed-dev
Replaces mbed-src (now inactive)
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /** |
| bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 3 | * @file stm32f30x_rcc.h |
| bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
| bogdanm | 0:9b334a45a8ff | 5 | * @version V1.1.0 |
| bogdanm | 0:9b334a45a8ff | 6 | * @date 27-February-2014 |
| bogdanm | 0:9b334a45a8ff | 7 | * @brief This file contains all the functions prototypes for the RCC |
| bogdanm | 0:9b334a45a8ff | 8 | * firmware library. |
| bogdanm | 0:9b334a45a8ff | 9 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 10 | * @attention |
| bogdanm | 0:9b334a45a8ff | 11 | * |
| bogdanm | 0:9b334a45a8ff | 12 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| bogdanm | 0:9b334a45a8ff | 13 | * |
| bogdanm | 0:9b334a45a8ff | 14 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 0:9b334a45a8ff | 15 | * are permitted provided that the following conditions are met: |
| bogdanm | 0:9b334a45a8ff | 16 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 17 | * this list of conditions and the following disclaimer. |
| bogdanm | 0:9b334a45a8ff | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 19 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 0:9b334a45a8ff | 20 | * and/or other materials provided with the distribution. |
| bogdanm | 0:9b334a45a8ff | 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 0:9b334a45a8ff | 22 | * may be used to endorse or promote products derived from this software |
| bogdanm | 0:9b334a45a8ff | 23 | * without specific prior written permission. |
| bogdanm | 0:9b334a45a8ff | 24 | * |
| bogdanm | 0:9b334a45a8ff | 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 0:9b334a45a8ff | 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 0:9b334a45a8ff | 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 0:9b334a45a8ff | 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 0:9b334a45a8ff | 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 0:9b334a45a8ff | 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 0:9b334a45a8ff | 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 0:9b334a45a8ff | 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 0:9b334a45a8ff | 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 0:9b334a45a8ff | 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 0:9b334a45a8ff | 35 | * |
| bogdanm | 0:9b334a45a8ff | 36 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 37 | */ |
| bogdanm | 0:9b334a45a8ff | 38 | |
| bogdanm | 0:9b334a45a8ff | 39 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 40 | #ifndef __STM32F30x_RCC_H |
| bogdanm | 0:9b334a45a8ff | 41 | #define __STM32F30x_RCC_H |
| bogdanm | 0:9b334a45a8ff | 42 | |
| bogdanm | 0:9b334a45a8ff | 43 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 44 | extern "C" { |
| bogdanm | 0:9b334a45a8ff | 45 | #endif |
| bogdanm | 0:9b334a45a8ff | 46 | |
| bogdanm | 0:9b334a45a8ff | 47 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 48 | #include "stm32f30x.h" |
| bogdanm | 0:9b334a45a8ff | 49 | |
| bogdanm | 0:9b334a45a8ff | 50 | /** @addtogroup STM32F30x_StdPeriph_Driver |
| bogdanm | 0:9b334a45a8ff | 51 | * @{ |
| bogdanm | 0:9b334a45a8ff | 52 | */ |
| bogdanm | 0:9b334a45a8ff | 53 | |
| bogdanm | 0:9b334a45a8ff | 54 | /** @addtogroup RCC |
| bogdanm | 0:9b334a45a8ff | 55 | * @{ |
| bogdanm | 0:9b334a45a8ff | 56 | */ |
| bogdanm | 0:9b334a45a8ff | 57 | |
| bogdanm | 0:9b334a45a8ff | 58 | /* Exported types ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 59 | |
| bogdanm | 0:9b334a45a8ff | 60 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 61 | { |
| bogdanm | 0:9b334a45a8ff | 62 | uint32_t SYSCLK_Frequency; |
| bogdanm | 0:9b334a45a8ff | 63 | uint32_t HCLK_Frequency; |
| bogdanm | 0:9b334a45a8ff | 64 | uint32_t PCLK1_Frequency; |
| bogdanm | 0:9b334a45a8ff | 65 | uint32_t PCLK2_Frequency; |
| bogdanm | 0:9b334a45a8ff | 66 | uint32_t ADC12CLK_Frequency; |
| bogdanm | 0:9b334a45a8ff | 67 | uint32_t ADC34CLK_Frequency; |
| bogdanm | 0:9b334a45a8ff | 68 | uint32_t I2C1CLK_Frequency; |
| bogdanm | 0:9b334a45a8ff | 69 | uint32_t I2C2CLK_Frequency; |
| bogdanm | 0:9b334a45a8ff | 70 | uint32_t I2C3CLK_Frequency; |
| bogdanm | 0:9b334a45a8ff | 71 | uint32_t TIM1CLK_Frequency; |
| bogdanm | 0:9b334a45a8ff | 72 | uint32_t HRTIM1CLK_Frequency; |
| bogdanm | 0:9b334a45a8ff | 73 | uint32_t TIM8CLK_Frequency; |
| bogdanm | 0:9b334a45a8ff | 74 | uint32_t USART1CLK_Frequency; |
| bogdanm | 0:9b334a45a8ff | 75 | uint32_t USART2CLK_Frequency; |
| bogdanm | 0:9b334a45a8ff | 76 | uint32_t USART3CLK_Frequency; |
| bogdanm | 0:9b334a45a8ff | 77 | uint32_t UART4CLK_Frequency; |
| bogdanm | 0:9b334a45a8ff | 78 | uint32_t UART5CLK_Frequency; |
| bogdanm | 0:9b334a45a8ff | 79 | uint32_t TIM15CLK_Frequency; |
| bogdanm | 0:9b334a45a8ff | 80 | uint32_t TIM16CLK_Frequency; |
| bogdanm | 0:9b334a45a8ff | 81 | uint32_t TIM17CLK_Frequency; |
| bogdanm | 0:9b334a45a8ff | 82 | }RCC_ClocksTypeDef; |
| bogdanm | 0:9b334a45a8ff | 83 | |
| bogdanm | 0:9b334a45a8ff | 84 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 85 | |
| bogdanm | 0:9b334a45a8ff | 86 | /** @defgroup RCC_Exported_Constants |
| bogdanm | 0:9b334a45a8ff | 87 | * @{ |
| bogdanm | 0:9b334a45a8ff | 88 | */ |
| bogdanm | 0:9b334a45a8ff | 89 | |
| bogdanm | 0:9b334a45a8ff | 90 | /** @defgroup RCC_HSE_configuration |
| bogdanm | 0:9b334a45a8ff | 91 | * @{ |
| bogdanm | 0:9b334a45a8ff | 92 | */ |
| bogdanm | 0:9b334a45a8ff | 93 | |
| bogdanm | 0:9b334a45a8ff | 94 | #define RCC_HSE_OFF ((uint8_t)0x00) |
| bogdanm | 0:9b334a45a8ff | 95 | #define RCC_HSE_ON ((uint8_t)0x01) |
| bogdanm | 0:9b334a45a8ff | 96 | #define RCC_HSE_Bypass ((uint8_t)0x05) |
| bogdanm | 0:9b334a45a8ff | 97 | #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ |
| bogdanm | 0:9b334a45a8ff | 98 | ((HSE) == RCC_HSE_Bypass)) |
| bogdanm | 0:9b334a45a8ff | 99 | |
| bogdanm | 0:9b334a45a8ff | 100 | /** |
| bogdanm | 0:9b334a45a8ff | 101 | * @} |
| bogdanm | 0:9b334a45a8ff | 102 | */ |
| bogdanm | 0:9b334a45a8ff | 103 | |
| bogdanm | 0:9b334a45a8ff | 104 | /** @defgroup RCC_PLL_Clock_Source |
| bogdanm | 0:9b334a45a8ff | 105 | * @{ |
| bogdanm | 0:9b334a45a8ff | 106 | */ |
| bogdanm | 0:9b334a45a8ff | 107 | |
| bogdanm | 0:9b334a45a8ff | 108 | #define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2 |
| bogdanm | 0:9b334a45a8ff | 109 | #define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_PREDIV1 |
| bogdanm | 0:9b334a45a8ff | 110 | |
| bogdanm | 0:9b334a45a8ff | 111 | #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ |
| bogdanm | 0:9b334a45a8ff | 112 | ((SOURCE) == RCC_PLLSource_PREDIV1)) |
| bogdanm | 0:9b334a45a8ff | 113 | /** |
| bogdanm | 0:9b334a45a8ff | 114 | * @} |
| bogdanm | 0:9b334a45a8ff | 115 | */ |
| bogdanm | 0:9b334a45a8ff | 116 | |
| bogdanm | 0:9b334a45a8ff | 117 | /** @defgroup RCC_PLL_Multiplication_Factor |
| bogdanm | 0:9b334a45a8ff | 118 | * @{ |
| bogdanm | 0:9b334a45a8ff | 119 | */ |
| bogdanm | 0:9b334a45a8ff | 120 | |
| bogdanm | 0:9b334a45a8ff | 121 | #define RCC_PLLMul_2 RCC_CFGR_PLLMULL2 |
| bogdanm | 0:9b334a45a8ff | 122 | #define RCC_PLLMul_3 RCC_CFGR_PLLMULL3 |
| bogdanm | 0:9b334a45a8ff | 123 | #define RCC_PLLMul_4 RCC_CFGR_PLLMULL4 |
| bogdanm | 0:9b334a45a8ff | 124 | #define RCC_PLLMul_5 RCC_CFGR_PLLMULL5 |
| bogdanm | 0:9b334a45a8ff | 125 | #define RCC_PLLMul_6 RCC_CFGR_PLLMULL6 |
| bogdanm | 0:9b334a45a8ff | 126 | #define RCC_PLLMul_7 RCC_CFGR_PLLMULL7 |
| bogdanm | 0:9b334a45a8ff | 127 | #define RCC_PLLMul_8 RCC_CFGR_PLLMULL8 |
| bogdanm | 0:9b334a45a8ff | 128 | #define RCC_PLLMul_9 RCC_CFGR_PLLMULL9 |
| bogdanm | 0:9b334a45a8ff | 129 | #define RCC_PLLMul_10 RCC_CFGR_PLLMULL10 |
| bogdanm | 0:9b334a45a8ff | 130 | #define RCC_PLLMul_11 RCC_CFGR_PLLMULL11 |
| bogdanm | 0:9b334a45a8ff | 131 | #define RCC_PLLMul_12 RCC_CFGR_PLLMULL12 |
| bogdanm | 0:9b334a45a8ff | 132 | #define RCC_PLLMul_13 RCC_CFGR_PLLMULL13 |
| bogdanm | 0:9b334a45a8ff | 133 | #define RCC_PLLMul_14 RCC_CFGR_PLLMULL14 |
| bogdanm | 0:9b334a45a8ff | 134 | #define RCC_PLLMul_15 RCC_CFGR_PLLMULL15 |
| bogdanm | 0:9b334a45a8ff | 135 | #define RCC_PLLMul_16 RCC_CFGR_PLLMULL16 |
| bogdanm | 0:9b334a45a8ff | 136 | #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ |
| bogdanm | 0:9b334a45a8ff | 137 | ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ |
| bogdanm | 0:9b334a45a8ff | 138 | ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ |
| bogdanm | 0:9b334a45a8ff | 139 | ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ |
| bogdanm | 0:9b334a45a8ff | 140 | ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ |
| bogdanm | 0:9b334a45a8ff | 141 | ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ |
| bogdanm | 0:9b334a45a8ff | 142 | ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ |
| bogdanm | 0:9b334a45a8ff | 143 | ((MUL) == RCC_PLLMul_16)) |
| bogdanm | 0:9b334a45a8ff | 144 | /** |
| bogdanm | 0:9b334a45a8ff | 145 | * @} |
| bogdanm | 0:9b334a45a8ff | 146 | */ |
| bogdanm | 0:9b334a45a8ff | 147 | |
| bogdanm | 0:9b334a45a8ff | 148 | /** @defgroup RCC_PREDIV1_division_factor |
| bogdanm | 0:9b334a45a8ff | 149 | * @{ |
| bogdanm | 0:9b334a45a8ff | 150 | */ |
| bogdanm | 0:9b334a45a8ff | 151 | #define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1 |
| bogdanm | 0:9b334a45a8ff | 152 | #define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2 |
| bogdanm | 0:9b334a45a8ff | 153 | #define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3 |
| bogdanm | 0:9b334a45a8ff | 154 | #define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4 |
| bogdanm | 0:9b334a45a8ff | 155 | #define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5 |
| bogdanm | 0:9b334a45a8ff | 156 | #define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6 |
| bogdanm | 0:9b334a45a8ff | 157 | #define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7 |
| bogdanm | 0:9b334a45a8ff | 158 | #define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8 |
| bogdanm | 0:9b334a45a8ff | 159 | #define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9 |
| bogdanm | 0:9b334a45a8ff | 160 | #define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10 |
| bogdanm | 0:9b334a45a8ff | 161 | #define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11 |
| bogdanm | 0:9b334a45a8ff | 162 | #define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12 |
| bogdanm | 0:9b334a45a8ff | 163 | #define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13 |
| bogdanm | 0:9b334a45a8ff | 164 | #define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14 |
| bogdanm | 0:9b334a45a8ff | 165 | #define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15 |
| bogdanm | 0:9b334a45a8ff | 166 | #define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16 |
| bogdanm | 0:9b334a45a8ff | 167 | |
| bogdanm | 0:9b334a45a8ff | 168 | #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ |
| bogdanm | 0:9b334a45a8ff | 169 | ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ |
| bogdanm | 0:9b334a45a8ff | 170 | ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ |
| bogdanm | 0:9b334a45a8ff | 171 | ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ |
| bogdanm | 0:9b334a45a8ff | 172 | ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ |
| bogdanm | 0:9b334a45a8ff | 173 | ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ |
| bogdanm | 0:9b334a45a8ff | 174 | ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ |
| bogdanm | 0:9b334a45a8ff | 175 | ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) |
| bogdanm | 0:9b334a45a8ff | 176 | /** |
| bogdanm | 0:9b334a45a8ff | 177 | * @} |
| bogdanm | 0:9b334a45a8ff | 178 | */ |
| bogdanm | 0:9b334a45a8ff | 179 | |
| bogdanm | 0:9b334a45a8ff | 180 | /** @defgroup RCC_System_Clock_Source |
| bogdanm | 0:9b334a45a8ff | 181 | * @{ |
| bogdanm | 0:9b334a45a8ff | 182 | */ |
| bogdanm | 0:9b334a45a8ff | 183 | |
| bogdanm | 0:9b334a45a8ff | 184 | #define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI |
| bogdanm | 0:9b334a45a8ff | 185 | #define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE |
| bogdanm | 0:9b334a45a8ff | 186 | #define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL |
| bogdanm | 0:9b334a45a8ff | 187 | #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ |
| bogdanm | 0:9b334a45a8ff | 188 | ((SOURCE) == RCC_SYSCLKSource_HSE) || \ |
| bogdanm | 0:9b334a45a8ff | 189 | ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) |
| bogdanm | 0:9b334a45a8ff | 190 | /** |
| bogdanm | 0:9b334a45a8ff | 191 | * @} |
| bogdanm | 0:9b334a45a8ff | 192 | */ |
| bogdanm | 0:9b334a45a8ff | 193 | |
| bogdanm | 0:9b334a45a8ff | 194 | /** @defgroup RCC_AHB_Clock_Source |
| bogdanm | 0:9b334a45a8ff | 195 | * @{ |
| bogdanm | 0:9b334a45a8ff | 196 | */ |
| bogdanm | 0:9b334a45a8ff | 197 | |
| bogdanm | 0:9b334a45a8ff | 198 | #define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1 |
| bogdanm | 0:9b334a45a8ff | 199 | #define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2 |
| bogdanm | 0:9b334a45a8ff | 200 | #define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4 |
| bogdanm | 0:9b334a45a8ff | 201 | #define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8 |
| bogdanm | 0:9b334a45a8ff | 202 | #define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16 |
| bogdanm | 0:9b334a45a8ff | 203 | #define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64 |
| bogdanm | 0:9b334a45a8ff | 204 | #define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128 |
| bogdanm | 0:9b334a45a8ff | 205 | #define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256 |
| bogdanm | 0:9b334a45a8ff | 206 | #define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512 |
| bogdanm | 0:9b334a45a8ff | 207 | #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ |
| bogdanm | 0:9b334a45a8ff | 208 | ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ |
| bogdanm | 0:9b334a45a8ff | 209 | ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ |
| bogdanm | 0:9b334a45a8ff | 210 | ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ |
| bogdanm | 0:9b334a45a8ff | 211 | ((HCLK) == RCC_SYSCLK_Div512)) |
| bogdanm | 0:9b334a45a8ff | 212 | /** |
| bogdanm | 0:9b334a45a8ff | 213 | * @} |
| bogdanm | 0:9b334a45a8ff | 214 | */ |
| bogdanm | 0:9b334a45a8ff | 215 | |
| bogdanm | 0:9b334a45a8ff | 216 | /** @defgroup RCC_APB1_APB2_clock_source |
| bogdanm | 0:9b334a45a8ff | 217 | * @{ |
| bogdanm | 0:9b334a45a8ff | 218 | */ |
| bogdanm | 0:9b334a45a8ff | 219 | |
| bogdanm | 0:9b334a45a8ff | 220 | #define RCC_HCLK_Div1 ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 221 | #define RCC_HCLK_Div2 ((uint32_t)0x00000400) |
| bogdanm | 0:9b334a45a8ff | 222 | #define RCC_HCLK_Div4 ((uint32_t)0x00000500) |
| bogdanm | 0:9b334a45a8ff | 223 | #define RCC_HCLK_Div8 ((uint32_t)0x00000600) |
| bogdanm | 0:9b334a45a8ff | 224 | #define RCC_HCLK_Div16 ((uint32_t)0x00000700) |
| bogdanm | 0:9b334a45a8ff | 225 | #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ |
| bogdanm | 0:9b334a45a8ff | 226 | ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ |
| bogdanm | 0:9b334a45a8ff | 227 | ((PCLK) == RCC_HCLK_Div16)) |
| bogdanm | 0:9b334a45a8ff | 228 | /** |
| bogdanm | 0:9b334a45a8ff | 229 | * @} |
| bogdanm | 0:9b334a45a8ff | 230 | */ |
| bogdanm | 0:9b334a45a8ff | 231 | |
| bogdanm | 0:9b334a45a8ff | 232 | /** @defgroup RCC_ADC_clock_source |
| bogdanm | 0:9b334a45a8ff | 233 | * @{ |
| bogdanm | 0:9b334a45a8ff | 234 | */ |
| bogdanm | 0:9b334a45a8ff | 235 | |
| bogdanm | 0:9b334a45a8ff | 236 | /* ADC1 & ADC2 */ |
| bogdanm | 0:9b334a45a8ff | 237 | #define RCC_ADC12PLLCLK_OFF ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 238 | #define RCC_ADC12PLLCLK_Div1 ((uint32_t)0x00000100) |
| bogdanm | 0:9b334a45a8ff | 239 | #define RCC_ADC12PLLCLK_Div2 ((uint32_t)0x00000110) |
| bogdanm | 0:9b334a45a8ff | 240 | #define RCC_ADC12PLLCLK_Div4 ((uint32_t)0x00000120) |
| bogdanm | 0:9b334a45a8ff | 241 | #define RCC_ADC12PLLCLK_Div6 ((uint32_t)0x00000130) |
| bogdanm | 0:9b334a45a8ff | 242 | #define RCC_ADC12PLLCLK_Div8 ((uint32_t)0x00000140) |
| bogdanm | 0:9b334a45a8ff | 243 | #define RCC_ADC12PLLCLK_Div10 ((uint32_t)0x00000150) |
| bogdanm | 0:9b334a45a8ff | 244 | #define RCC_ADC12PLLCLK_Div12 ((uint32_t)0x00000160) |
| bogdanm | 0:9b334a45a8ff | 245 | #define RCC_ADC12PLLCLK_Div16 ((uint32_t)0x00000170) |
| bogdanm | 0:9b334a45a8ff | 246 | #define RCC_ADC12PLLCLK_Div32 ((uint32_t)0x00000180) |
| bogdanm | 0:9b334a45a8ff | 247 | #define RCC_ADC12PLLCLK_Div64 ((uint32_t)0x00000190) |
| bogdanm | 0:9b334a45a8ff | 248 | #define RCC_ADC12PLLCLK_Div128 ((uint32_t)0x000001A0) |
| bogdanm | 0:9b334a45a8ff | 249 | #define RCC_ADC12PLLCLK_Div256 ((uint32_t)0x000001B0) |
| bogdanm | 0:9b334a45a8ff | 250 | |
| bogdanm | 0:9b334a45a8ff | 251 | /* ADC3 & ADC4 */ |
| bogdanm | 0:9b334a45a8ff | 252 | #define RCC_ADC34PLLCLK_OFF ((uint32_t)0x10000000) |
| bogdanm | 0:9b334a45a8ff | 253 | #define RCC_ADC34PLLCLK_Div1 ((uint32_t)0x10002000) |
| bogdanm | 0:9b334a45a8ff | 254 | #define RCC_ADC34PLLCLK_Div2 ((uint32_t)0x10002200) |
| bogdanm | 0:9b334a45a8ff | 255 | #define RCC_ADC34PLLCLK_Div4 ((uint32_t)0x10002400) |
| bogdanm | 0:9b334a45a8ff | 256 | #define RCC_ADC34PLLCLK_Div6 ((uint32_t)0x10002600) |
| bogdanm | 0:9b334a45a8ff | 257 | #define RCC_ADC34PLLCLK_Div8 ((uint32_t)0x10002800) |
| bogdanm | 0:9b334a45a8ff | 258 | #define RCC_ADC34PLLCLK_Div10 ((uint32_t)0x10002A00) |
| bogdanm | 0:9b334a45a8ff | 259 | #define RCC_ADC34PLLCLK_Div12 ((uint32_t)0x10002C00) |
| bogdanm | 0:9b334a45a8ff | 260 | #define RCC_ADC34PLLCLK_Div16 ((uint32_t)0x10002E00) |
| bogdanm | 0:9b334a45a8ff | 261 | #define RCC_ADC34PLLCLK_Div32 ((uint32_t)0x10003000) |
| bogdanm | 0:9b334a45a8ff | 262 | #define RCC_ADC34PLLCLK_Div64 ((uint32_t)0x10003200) |
| bogdanm | 0:9b334a45a8ff | 263 | #define RCC_ADC34PLLCLK_Div128 ((uint32_t)0x10003400) |
| bogdanm | 0:9b334a45a8ff | 264 | #define RCC_ADC34PLLCLK_Div256 ((uint32_t)0x10003600) |
| bogdanm | 0:9b334a45a8ff | 265 | |
| bogdanm | 0:9b334a45a8ff | 266 | #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_Div1) || \ |
| bogdanm | 0:9b334a45a8ff | 267 | ((ADCCLK) == RCC_ADC12PLLCLK_Div2) || ((ADCCLK) == RCC_ADC12PLLCLK_Div4) || \ |
| bogdanm | 0:9b334a45a8ff | 268 | ((ADCCLK) == RCC_ADC12PLLCLK_Div6) || ((ADCCLK) == RCC_ADC12PLLCLK_Div8) || \ |
| bogdanm | 0:9b334a45a8ff | 269 | ((ADCCLK) == RCC_ADC12PLLCLK_Div10) || ((ADCCLK) == RCC_ADC12PLLCLK_Div12) || \ |
| bogdanm | 0:9b334a45a8ff | 270 | ((ADCCLK) == RCC_ADC12PLLCLK_Div16) || ((ADCCLK) == RCC_ADC12PLLCLK_Div32) || \ |
| bogdanm | 0:9b334a45a8ff | 271 | ((ADCCLK) == RCC_ADC12PLLCLK_Div64) || ((ADCCLK) == RCC_ADC12PLLCLK_Div128) || \ |
| bogdanm | 0:9b334a45a8ff | 272 | ((ADCCLK) == RCC_ADC12PLLCLK_Div256) || ((ADCCLK) == RCC_ADC34PLLCLK_OFF) || \ |
| bogdanm | 0:9b334a45a8ff | 273 | ((ADCCLK) == RCC_ADC34PLLCLK_Div1) || ((ADCCLK) == RCC_ADC34PLLCLK_Div2) || \ |
| bogdanm | 0:9b334a45a8ff | 274 | ((ADCCLK) == RCC_ADC34PLLCLK_Div4) || ((ADCCLK) == RCC_ADC34PLLCLK_Div6) || \ |
| bogdanm | 0:9b334a45a8ff | 275 | ((ADCCLK) == RCC_ADC34PLLCLK_Div8) || ((ADCCLK) == RCC_ADC34PLLCLK_Div10) || \ |
| bogdanm | 0:9b334a45a8ff | 276 | ((ADCCLK) == RCC_ADC34PLLCLK_Div12) || ((ADCCLK) == RCC_ADC34PLLCLK_Div16) || \ |
| bogdanm | 0:9b334a45a8ff | 277 | ((ADCCLK) == RCC_ADC34PLLCLK_Div32) || ((ADCCLK) == RCC_ADC34PLLCLK_Div64) || \ |
| bogdanm | 0:9b334a45a8ff | 278 | ((ADCCLK) == RCC_ADC34PLLCLK_Div128) || ((ADCCLK) == RCC_ADC34PLLCLK_Div256)) |
| bogdanm | 0:9b334a45a8ff | 279 | |
| bogdanm | 0:9b334a45a8ff | 280 | /** |
| bogdanm | 0:9b334a45a8ff | 281 | * @} |
| bogdanm | 0:9b334a45a8ff | 282 | */ |
| bogdanm | 0:9b334a45a8ff | 283 | |
| bogdanm | 0:9b334a45a8ff | 284 | /** @defgroup RCC_TIM_clock_source |
| bogdanm | 0:9b334a45a8ff | 285 | * @{ |
| bogdanm | 0:9b334a45a8ff | 286 | */ |
| bogdanm | 0:9b334a45a8ff | 287 | |
| bogdanm | 0:9b334a45a8ff | 288 | #define RCC_TIM1CLK_HCLK ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 289 | #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW |
| bogdanm | 0:9b334a45a8ff | 290 | |
| bogdanm | 0:9b334a45a8ff | 291 | #define RCC_TIM8CLK_HCLK ((uint32_t)0x10000000) |
| bogdanm | 0:9b334a45a8ff | 292 | #define RCC_TIM8CLK_PLLCLK ((uint32_t)0x10000200) |
| bogdanm | 0:9b334a45a8ff | 293 | |
| bogdanm | 0:9b334a45a8ff | 294 | #define RCC_TIM15CLK_HCLK ((uint32_t)0x20000000) |
| bogdanm | 0:9b334a45a8ff | 295 | #define RCC_TIM15CLK_PLLCLK ((uint32_t)0x20000400) |
| bogdanm | 0:9b334a45a8ff | 296 | |
| bogdanm | 0:9b334a45a8ff | 297 | #define RCC_TIM16CLK_HCLK ((uint32_t)0x30000000) |
| bogdanm | 0:9b334a45a8ff | 298 | #define RCC_TIM16CLK_PLLCLK ((uint32_t)0x30000800) |
| bogdanm | 0:9b334a45a8ff | 299 | |
| bogdanm | 0:9b334a45a8ff | 300 | #define RCC_TIM17CLK_HCLK ((uint32_t)0x40000000) |
| bogdanm | 0:9b334a45a8ff | 301 | #define RCC_TIM17CLK_PLLCLK ((uint32_t)0x40002000) |
| bogdanm | 0:9b334a45a8ff | 302 | |
| bogdanm | 0:9b334a45a8ff | 303 | #define IS_RCC_TIMCLK(TIMCLK) (((TIMCLK) == RCC_TIM1CLK_HCLK) || ((TIMCLK) == RCC_TIM1CLK_PLLCLK) || \ |
| bogdanm | 0:9b334a45a8ff | 304 | ((TIMCLK) == RCC_TIM8CLK_HCLK) || ((TIMCLK) == RCC_TIM8CLK_PLLCLK) || \ |
| bogdanm | 0:9b334a45a8ff | 305 | ((TIMCLK) == RCC_TIM15CLK_HCLK) || ((TIMCLK) == RCC_TIM15CLK_PLLCLK) || \ |
| bogdanm | 0:9b334a45a8ff | 306 | ((TIMCLK) == RCC_TIM16CLK_HCLK) || ((TIMCLK) == RCC_TIM16CLK_PLLCLK) || \ |
| bogdanm | 0:9b334a45a8ff | 307 | ((TIMCLK) == RCC_TIM17CLK_HCLK) || ((TIMCLK) == RCC_TIM17CLK_PLLCLK)) |
| bogdanm | 0:9b334a45a8ff | 308 | |
| bogdanm | 0:9b334a45a8ff | 309 | /** |
| bogdanm | 0:9b334a45a8ff | 310 | * @} |
| bogdanm | 0:9b334a45a8ff | 311 | */ |
| bogdanm | 0:9b334a45a8ff | 312 | |
| bogdanm | 0:9b334a45a8ff | 313 | /** @defgroup RCC_HRTIM_clock_source |
| bogdanm | 0:9b334a45a8ff | 314 | * @{ |
| bogdanm | 0:9b334a45a8ff | 315 | */ |
| bogdanm | 0:9b334a45a8ff | 316 | |
| bogdanm | 0:9b334a45a8ff | 317 | #define RCC_HRTIM1CLK_HCLK ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 318 | #define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW |
| bogdanm | 0:9b334a45a8ff | 319 | |
| bogdanm | 0:9b334a45a8ff | 320 | #define IS_RCC_HRTIMCLK(HRTIMCLK) (((HRTIMCLK) == RCC_HRTIM1CLK_HCLK) || ((HRTIMCLK) == RCC_HRTIM1CLK_PLLCLK)) |
| bogdanm | 0:9b334a45a8ff | 321 | |
| bogdanm | 0:9b334a45a8ff | 322 | /** |
| bogdanm | 0:9b334a45a8ff | 323 | * @} |
| bogdanm | 0:9b334a45a8ff | 324 | */ |
| bogdanm | 0:9b334a45a8ff | 325 | |
| bogdanm | 0:9b334a45a8ff | 326 | /** @defgroup RCC_I2C_clock_source |
| bogdanm | 0:9b334a45a8ff | 327 | * @{ |
| bogdanm | 0:9b334a45a8ff | 328 | */ |
| bogdanm | 0:9b334a45a8ff | 329 | |
| bogdanm | 0:9b334a45a8ff | 330 | #define RCC_I2C1CLK_HSI ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 331 | #define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW |
| bogdanm | 0:9b334a45a8ff | 332 | |
| bogdanm | 0:9b334a45a8ff | 333 | #define RCC_I2C2CLK_HSI ((uint32_t)0x10000000) |
| bogdanm | 0:9b334a45a8ff | 334 | #define RCC_I2C2CLK_SYSCLK ((uint32_t)0x10000020) |
| bogdanm | 0:9b334a45a8ff | 335 | |
| bogdanm | 0:9b334a45a8ff | 336 | #define RCC_I2C3CLK_HSI ((uint32_t)0x20000000) |
| bogdanm | 0:9b334a45a8ff | 337 | #define RCC_I2C3CLK_SYSCLK ((uint32_t)0x20000040) |
| bogdanm | 0:9b334a45a8ff | 338 | |
| bogdanm | 0:9b334a45a8ff | 339 | #define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK) || \ |
| bogdanm | 0:9b334a45a8ff | 340 | ((I2CCLK) == RCC_I2C2CLK_HSI) || ((I2CCLK) == RCC_I2C2CLK_SYSCLK) || \ |
| bogdanm | 0:9b334a45a8ff | 341 | ((I2CCLK) == RCC_I2C3CLK_HSI) || ((I2CCLK) == RCC_I2C3CLK_SYSCLK)) |
| bogdanm | 0:9b334a45a8ff | 342 | |
| bogdanm | 0:9b334a45a8ff | 343 | /** |
| bogdanm | 0:9b334a45a8ff | 344 | * @} |
| bogdanm | 0:9b334a45a8ff | 345 | */ |
| bogdanm | 0:9b334a45a8ff | 346 | |
| bogdanm | 0:9b334a45a8ff | 347 | /** @defgroup RCC_USART_clock_source |
| bogdanm | 0:9b334a45a8ff | 348 | * @{ |
| bogdanm | 0:9b334a45a8ff | 349 | */ |
| bogdanm | 0:9b334a45a8ff | 350 | |
| bogdanm | 0:9b334a45a8ff | 351 | #define RCC_USART1CLK_PCLK ((uint32_t)0x10000000) |
| bogdanm | 0:9b334a45a8ff | 352 | #define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001) |
| bogdanm | 0:9b334a45a8ff | 353 | #define RCC_USART1CLK_LSE ((uint32_t)0x10000002) |
| bogdanm | 0:9b334a45a8ff | 354 | #define RCC_USART1CLK_HSI ((uint32_t)0x10000003) |
| bogdanm | 0:9b334a45a8ff | 355 | |
| bogdanm | 0:9b334a45a8ff | 356 | #define RCC_USART2CLK_PCLK ((uint32_t)0x20000000) |
| bogdanm | 0:9b334a45a8ff | 357 | #define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000) |
| bogdanm | 0:9b334a45a8ff | 358 | #define RCC_USART2CLK_LSE ((uint32_t)0x20020000) |
| bogdanm | 0:9b334a45a8ff | 359 | #define RCC_USART2CLK_HSI ((uint32_t)0x20030000) |
| bogdanm | 0:9b334a45a8ff | 360 | |
| bogdanm | 0:9b334a45a8ff | 361 | #define RCC_USART3CLK_PCLK ((uint32_t)0x30000000) |
| bogdanm | 0:9b334a45a8ff | 362 | #define RCC_USART3CLK_SYSCLK ((uint32_t)0x30040000) |
| bogdanm | 0:9b334a45a8ff | 363 | #define RCC_USART3CLK_LSE ((uint32_t)0x30080000) |
| bogdanm | 0:9b334a45a8ff | 364 | #define RCC_USART3CLK_HSI ((uint32_t)0x300C0000) |
| bogdanm | 0:9b334a45a8ff | 365 | |
| bogdanm | 0:9b334a45a8ff | 366 | #define RCC_UART4CLK_PCLK ((uint32_t)0x40000000) |
| bogdanm | 0:9b334a45a8ff | 367 | #define RCC_UART4CLK_SYSCLK ((uint32_t)0x40100000) |
| bogdanm | 0:9b334a45a8ff | 368 | #define RCC_UART4CLK_LSE ((uint32_t)0x40200000) |
| bogdanm | 0:9b334a45a8ff | 369 | #define RCC_UART4CLK_HSI ((uint32_t)0x40300000) |
| bogdanm | 0:9b334a45a8ff | 370 | |
| bogdanm | 0:9b334a45a8ff | 371 | #define RCC_UART5CLK_PCLK ((uint32_t)0x50000000) |
| bogdanm | 0:9b334a45a8ff | 372 | #define RCC_UART5CLK_SYSCLK ((uint32_t)0x50400000) |
| bogdanm | 0:9b334a45a8ff | 373 | #define RCC_UART5CLK_LSE ((uint32_t)0x50800000) |
| bogdanm | 0:9b334a45a8ff | 374 | #define RCC_UART5CLK_HSI ((uint32_t)0x50C00000) |
| bogdanm | 0:9b334a45a8ff | 375 | |
| bogdanm | 0:9b334a45a8ff | 376 | #define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \ |
| bogdanm | 0:9b334a45a8ff | 377 | ((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI) ||\ |
| bogdanm | 0:9b334a45a8ff | 378 | ((USARTCLK) == RCC_USART2CLK_PCLK) || ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \ |
| bogdanm | 0:9b334a45a8ff | 379 | ((USARTCLK) == RCC_USART2CLK_LSE) || ((USARTCLK) == RCC_USART2CLK_HSI) || \ |
| bogdanm | 0:9b334a45a8ff | 380 | ((USARTCLK) == RCC_USART3CLK_PCLK) || ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \ |
| bogdanm | 0:9b334a45a8ff | 381 | ((USARTCLK) == RCC_USART3CLK_LSE) || ((USARTCLK) == RCC_USART3CLK_HSI) || \ |
| bogdanm | 0:9b334a45a8ff | 382 | ((USARTCLK) == RCC_UART4CLK_PCLK) || ((USARTCLK) == RCC_UART4CLK_SYSCLK) || \ |
| bogdanm | 0:9b334a45a8ff | 383 | ((USARTCLK) == RCC_UART4CLK_LSE) || ((USARTCLK) == RCC_UART4CLK_HSI) || \ |
| bogdanm | 0:9b334a45a8ff | 384 | ((USARTCLK) == RCC_UART5CLK_PCLK) || ((USARTCLK) == RCC_UART5CLK_SYSCLK) || \ |
| bogdanm | 0:9b334a45a8ff | 385 | ((USARTCLK) == RCC_UART5CLK_LSE) || ((USARTCLK) == RCC_UART5CLK_HSI)) |
| bogdanm | 0:9b334a45a8ff | 386 | |
| bogdanm | 0:9b334a45a8ff | 387 | /** |
| bogdanm | 0:9b334a45a8ff | 388 | * @} |
| bogdanm | 0:9b334a45a8ff | 389 | */ |
| bogdanm | 0:9b334a45a8ff | 390 | |
| bogdanm | 0:9b334a45a8ff | 391 | /** @defgroup RCC_Interrupt_Source |
| bogdanm | 0:9b334a45a8ff | 392 | * @{ |
| bogdanm | 0:9b334a45a8ff | 393 | */ |
| bogdanm | 0:9b334a45a8ff | 394 | |
| bogdanm | 0:9b334a45a8ff | 395 | #define RCC_IT_LSIRDY ((uint8_t)0x01) |
| bogdanm | 0:9b334a45a8ff | 396 | #define RCC_IT_LSERDY ((uint8_t)0x02) |
| bogdanm | 0:9b334a45a8ff | 397 | #define RCC_IT_HSIRDY ((uint8_t)0x04) |
| bogdanm | 0:9b334a45a8ff | 398 | #define RCC_IT_HSERDY ((uint8_t)0x08) |
| bogdanm | 0:9b334a45a8ff | 399 | #define RCC_IT_PLLRDY ((uint8_t)0x10) |
| bogdanm | 0:9b334a45a8ff | 400 | #define RCC_IT_CSS ((uint8_t)0x80) |
| bogdanm | 0:9b334a45a8ff | 401 | |
| bogdanm | 0:9b334a45a8ff | 402 | #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00)) |
| bogdanm | 0:9b334a45a8ff | 403 | |
| bogdanm | 0:9b334a45a8ff | 404 | #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ |
| bogdanm | 0:9b334a45a8ff | 405 | ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ |
| bogdanm | 0:9b334a45a8ff | 406 | ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) |
| bogdanm | 0:9b334a45a8ff | 407 | |
| bogdanm | 0:9b334a45a8ff | 408 | |
| bogdanm | 0:9b334a45a8ff | 409 | #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00)) |
| bogdanm | 0:9b334a45a8ff | 410 | |
| bogdanm | 0:9b334a45a8ff | 411 | /** |
| bogdanm | 0:9b334a45a8ff | 412 | * @} |
| bogdanm | 0:9b334a45a8ff | 413 | */ |
| bogdanm | 0:9b334a45a8ff | 414 | |
| bogdanm | 0:9b334a45a8ff | 415 | /** @defgroup RCC_LSE_configuration |
| bogdanm | 0:9b334a45a8ff | 416 | * @{ |
| bogdanm | 0:9b334a45a8ff | 417 | */ |
| bogdanm | 0:9b334a45a8ff | 418 | |
| bogdanm | 0:9b334a45a8ff | 419 | #define RCC_LSE_OFF ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 420 | #define RCC_LSE_ON RCC_BDCR_LSEON |
| bogdanm | 0:9b334a45a8ff | 421 | #define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP)) |
| bogdanm | 0:9b334a45a8ff | 422 | #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ |
| bogdanm | 0:9b334a45a8ff | 423 | ((LSE) == RCC_LSE_Bypass)) |
| bogdanm | 0:9b334a45a8ff | 424 | /** |
| bogdanm | 0:9b334a45a8ff | 425 | * @} |
| bogdanm | 0:9b334a45a8ff | 426 | */ |
| bogdanm | 0:9b334a45a8ff | 427 | |
| bogdanm | 0:9b334a45a8ff | 428 | /** @defgroup RCC_RTC_Clock_Source |
| bogdanm | 0:9b334a45a8ff | 429 | * @{ |
| bogdanm | 0:9b334a45a8ff | 430 | */ |
| bogdanm | 0:9b334a45a8ff | 431 | |
| bogdanm | 0:9b334a45a8ff | 432 | #define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE |
| bogdanm | 0:9b334a45a8ff | 433 | #define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI |
| bogdanm | 0:9b334a45a8ff | 434 | #define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE |
| bogdanm | 0:9b334a45a8ff | 435 | |
| bogdanm | 0:9b334a45a8ff | 436 | #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ |
| bogdanm | 0:9b334a45a8ff | 437 | ((SOURCE) == RCC_RTCCLKSource_LSI) || \ |
| bogdanm | 0:9b334a45a8ff | 438 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div32)) |
| bogdanm | 0:9b334a45a8ff | 439 | /** |
| bogdanm | 0:9b334a45a8ff | 440 | * @} |
| bogdanm | 0:9b334a45a8ff | 441 | */ |
| bogdanm | 0:9b334a45a8ff | 442 | |
| bogdanm | 0:9b334a45a8ff | 443 | /** @defgroup RCC_I2S_Clock_Source |
| bogdanm | 0:9b334a45a8ff | 444 | * @{ |
| bogdanm | 0:9b334a45a8ff | 445 | */ |
| bogdanm | 0:9b334a45a8ff | 446 | #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) |
| bogdanm | 0:9b334a45a8ff | 447 | #define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) |
| bogdanm | 0:9b334a45a8ff | 448 | |
| bogdanm | 0:9b334a45a8ff | 449 | #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) |
| bogdanm | 0:9b334a45a8ff | 450 | |
| bogdanm | 0:9b334a45a8ff | 451 | /** @defgroup RCC_LSE_Drive_Configuration |
| bogdanm | 0:9b334a45a8ff | 452 | * @{ |
| bogdanm | 0:9b334a45a8ff | 453 | */ |
| bogdanm | 0:9b334a45a8ff | 454 | |
| bogdanm | 0:9b334a45a8ff | 455 | #define RCC_LSEDrive_Low ((uint32_t)0x00000000) |
| bogdanm | 0:9b334a45a8ff | 456 | #define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0 |
| bogdanm | 0:9b334a45a8ff | 457 | #define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1 |
| bogdanm | 0:9b334a45a8ff | 458 | #define RCC_LSEDrive_High RCC_BDCR_LSEDRV |
| bogdanm | 0:9b334a45a8ff | 459 | #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \ |
| bogdanm | 0:9b334a45a8ff | 460 | ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High)) |
| bogdanm | 0:9b334a45a8ff | 461 | /** |
| bogdanm | 0:9b334a45a8ff | 462 | * @} |
| bogdanm | 0:9b334a45a8ff | 463 | */ |
| bogdanm | 0:9b334a45a8ff | 464 | |
| bogdanm | 0:9b334a45a8ff | 465 | /** @defgroup RCC_AHB_Peripherals |
| bogdanm | 0:9b334a45a8ff | 466 | * @{ |
| bogdanm | 0:9b334a45a8ff | 467 | */ |
| bogdanm | 0:9b334a45a8ff | 468 | |
| bogdanm | 0:9b334a45a8ff | 469 | #define RCC_AHBPeriph_ADC34 RCC_AHBENR_ADC34EN |
| bogdanm | 0:9b334a45a8ff | 470 | #define RCC_AHBPeriph_ADC12 RCC_AHBENR_ADC12EN |
| bogdanm | 0:9b334a45a8ff | 471 | #define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN |
| bogdanm | 0:9b334a45a8ff | 472 | #define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN |
| bogdanm | 0:9b334a45a8ff | 473 | #define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN |
| bogdanm | 0:9b334a45a8ff | 474 | #define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN |
| bogdanm | 0:9b334a45a8ff | 475 | #define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN |
| bogdanm | 0:9b334a45a8ff | 476 | #define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN |
| bogdanm | 0:9b334a45a8ff | 477 | #define RCC_AHBPeriph_TS RCC_AHBENR_TSEN |
| bogdanm | 0:9b334a45a8ff | 478 | #define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN |
| bogdanm | 0:9b334a45a8ff | 479 | #define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN |
| bogdanm | 0:9b334a45a8ff | 480 | #define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN |
| bogdanm | 0:9b334a45a8ff | 481 | #define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN |
| bogdanm | 0:9b334a45a8ff | 482 | #define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN |
| bogdanm | 0:9b334a45a8ff | 483 | |
| bogdanm | 0:9b334a45a8ff | 484 | #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFA8) == 0x00) && ((PERIPH) != 0x00)) |
| bogdanm | 0:9b334a45a8ff | 485 | #define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xCE81FFFF) == 0x00) && ((PERIPH) != 0x00)) |
| bogdanm | 0:9b334a45a8ff | 486 | |
| bogdanm | 0:9b334a45a8ff | 487 | /** |
| bogdanm | 0:9b334a45a8ff | 488 | * @} |
| bogdanm | 0:9b334a45a8ff | 489 | */ |
| bogdanm | 0:9b334a45a8ff | 490 | |
| bogdanm | 0:9b334a45a8ff | 491 | /** @defgroup RCC_APB2_Peripherals |
| bogdanm | 0:9b334a45a8ff | 492 | * @{ |
| bogdanm | 0:9b334a45a8ff | 493 | */ |
| bogdanm | 0:9b334a45a8ff | 494 | |
| bogdanm | 0:9b334a45a8ff | 495 | #define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN |
| bogdanm | 0:9b334a45a8ff | 496 | #define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN |
| bogdanm | 0:9b334a45a8ff | 497 | #define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN |
| bogdanm | 0:9b334a45a8ff | 498 | #define RCC_APB2Periph_TIM8 RCC_APB2ENR_TIM8EN |
| bogdanm | 0:9b334a45a8ff | 499 | #define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN |
| bogdanm | 0:9b334a45a8ff | 500 | #define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN |
| bogdanm | 0:9b334a45a8ff | 501 | #define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN |
| bogdanm | 0:9b334a45a8ff | 502 | #define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN |
| bogdanm | 0:9b334a45a8ff | 503 | #define RCC_APB2Periph_HRTIM1 RCC_APB2ENR_HRTIM1 |
| bogdanm | 0:9b334a45a8ff | 504 | |
| bogdanm | 0:9b334a45a8ff | 505 | #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xDFF887FE) == 0x00) && ((PERIPH) != 0x00)) |
| bogdanm | 0:9b334a45a8ff | 506 | |
| bogdanm | 0:9b334a45a8ff | 507 | /** |
| bogdanm | 0:9b334a45a8ff | 508 | * @} |
| bogdanm | 0:9b334a45a8ff | 509 | */ |
| bogdanm | 0:9b334a45a8ff | 510 | |
| bogdanm | 0:9b334a45a8ff | 511 | /** @defgroup RCC_APB1_Peripherals |
| bogdanm | 0:9b334a45a8ff | 512 | * @{ |
| bogdanm | 0:9b334a45a8ff | 513 | */ |
| bogdanm | 0:9b334a45a8ff | 514 | #define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN |
| bogdanm | 0:9b334a45a8ff | 515 | #define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN |
| bogdanm | 0:9b334a45a8ff | 516 | #define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN |
| bogdanm | 0:9b334a45a8ff | 517 | #define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN |
| bogdanm | 0:9b334a45a8ff | 518 | #define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN |
| bogdanm | 0:9b334a45a8ff | 519 | #define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN |
| bogdanm | 0:9b334a45a8ff | 520 | #define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN |
| bogdanm | 0:9b334a45a8ff | 521 | #define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN |
| bogdanm | 0:9b334a45a8ff | 522 | #define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN |
| bogdanm | 0:9b334a45a8ff | 523 | #define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN |
| bogdanm | 0:9b334a45a8ff | 524 | #define RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN |
| bogdanm | 0:9b334a45a8ff | 525 | #define RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN |
| bogdanm | 0:9b334a45a8ff | 526 | #define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN |
| bogdanm | 0:9b334a45a8ff | 527 | #define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN |
| bogdanm | 0:9b334a45a8ff | 528 | #define RCC_APB1Periph_USB RCC_APB1ENR_USBEN |
| bogdanm | 0:9b334a45a8ff | 529 | #define RCC_APB1Periph_CAN1 RCC_APB1ENR_CAN1EN |
| bogdanm | 0:9b334a45a8ff | 530 | #define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN |
| bogdanm | 0:9b334a45a8ff | 531 | #define RCC_APB1Periph_DAC1 RCC_APB1ENR_DAC1EN |
| bogdanm | 0:9b334a45a8ff | 532 | #define RCC_APB1Periph_I2C3 RCC_APB1ENR_I2C3EN |
| bogdanm | 0:9b334a45a8ff | 533 | #define RCC_APB1Periph_DAC2 RCC_APB1ENR_DAC2EN |
| bogdanm | 0:9b334a45a8ff | 534 | #define RCC_APB1Periph_DAC RCC_APB1Periph_DAC1 |
| bogdanm | 0:9b334a45a8ff | 535 | |
| bogdanm | 0:9b334a45a8ff | 536 | |
| bogdanm | 0:9b334a45a8ff | 537 | #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x890137C8) == 0x00) && ((PERIPH) != 0x00)) |
| bogdanm | 0:9b334a45a8ff | 538 | /** |
| bogdanm | 0:9b334a45a8ff | 539 | * @} |
| bogdanm | 0:9b334a45a8ff | 540 | */ |
| bogdanm | 0:9b334a45a8ff | 541 | |
| bogdanm | 0:9b334a45a8ff | 542 | /** @defgroup RCC_MCO_Clock_Source |
| bogdanm | 0:9b334a45a8ff | 543 | * @{ |
| bogdanm | 0:9b334a45a8ff | 544 | */ |
| bogdanm | 0:9b334a45a8ff | 545 | |
| bogdanm | 0:9b334a45a8ff | 546 | #define RCC_MCOSource_NoClock ((uint8_t)0x00) |
| bogdanm | 0:9b334a45a8ff | 547 | #define RCC_MCOSource_LSI ((uint8_t)0x02) |
| bogdanm | 0:9b334a45a8ff | 548 | #define RCC_MCOSource_LSE ((uint8_t)0x03) |
| bogdanm | 0:9b334a45a8ff | 549 | #define RCC_MCOSource_SYSCLK ((uint8_t)0x04) |
| bogdanm | 0:9b334a45a8ff | 550 | #define RCC_MCOSource_HSI ((uint8_t)0x05) |
| bogdanm | 0:9b334a45a8ff | 551 | #define RCC_MCOSource_HSE ((uint8_t)0x06) |
| bogdanm | 0:9b334a45a8ff | 552 | #define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07) |
| bogdanm | 0:9b334a45a8ff | 553 | |
| bogdanm | 0:9b334a45a8ff | 554 | #define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) ||((SOURCE) == RCC_MCOSource_SYSCLK) ||\ |
| bogdanm | 0:9b334a45a8ff | 555 | ((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_HSE) || \ |
| bogdanm | 0:9b334a45a8ff | 556 | ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE) || \ |
| bogdanm | 0:9b334a45a8ff | 557 | ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)) |
| bogdanm | 0:9b334a45a8ff | 558 | /** |
| bogdanm | 0:9b334a45a8ff | 559 | * @} |
| bogdanm | 0:9b334a45a8ff | 560 | */ |
| bogdanm | 0:9b334a45a8ff | 561 | |
| bogdanm | 0:9b334a45a8ff | 562 | /** @defgroup RCC_MCOPrescaler |
| bogdanm | 0:9b334a45a8ff | 563 | * @{ |
| bogdanm | 0:9b334a45a8ff | 564 | */ |
| bogdanm | 0:9b334a45a8ff | 565 | |
| bogdanm | 0:9b334a45a8ff | 566 | #define RCC_MCOPrescaler_1 RCC_CFGR_MCO_PRE_1 |
| bogdanm | 0:9b334a45a8ff | 567 | #define RCC_MCOPrescaler_2 RCC_CFGR_MCO_PRE_2 |
| bogdanm | 0:9b334a45a8ff | 568 | #define RCC_MCOPrescaler_4 RCC_CFGR_MCO_PRE_4 |
| bogdanm | 0:9b334a45a8ff | 569 | #define RCC_MCOPrescaler_8 RCC_CFGR_MCO_PRE_8 |
| bogdanm | 0:9b334a45a8ff | 570 | #define RCC_MCOPrescaler_16 RCC_CFGR_MCO_PRE_16 |
| bogdanm | 0:9b334a45a8ff | 571 | #define RCC_MCOPrescaler_32 RCC_CFGR_MCO_PRE_32 |
| bogdanm | 0:9b334a45a8ff | 572 | #define RCC_MCOPrescaler_64 RCC_CFGR_MCO_PRE_64 |
| bogdanm | 0:9b334a45a8ff | 573 | #define RCC_MCOPrescaler_128 RCC_CFGR_MCO_PRE_128 |
| bogdanm | 0:9b334a45a8ff | 574 | |
| bogdanm | 0:9b334a45a8ff | 575 | #define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \ |
| bogdanm | 0:9b334a45a8ff | 576 | ((PRESCALER) == RCC_MCOPrescaler_2) || \ |
| bogdanm | 0:9b334a45a8ff | 577 | ((PRESCALER) == RCC_MCOPrescaler_4) || \ |
| bogdanm | 0:9b334a45a8ff | 578 | ((PRESCALER) == RCC_MCOPrescaler_8) || \ |
| bogdanm | 0:9b334a45a8ff | 579 | ((PRESCALER) == RCC_MCOPrescaler_16) || \ |
| bogdanm | 0:9b334a45a8ff | 580 | ((PRESCALER) == RCC_MCOPrescaler_32) || \ |
| bogdanm | 0:9b334a45a8ff | 581 | ((PRESCALER) == RCC_MCOPrescaler_64) || \ |
| bogdanm | 0:9b334a45a8ff | 582 | ((PRESCALER) == RCC_MCOPrescaler_128)) |
| bogdanm | 0:9b334a45a8ff | 583 | /** |
| bogdanm | 0:9b334a45a8ff | 584 | * @} |
| bogdanm | 0:9b334a45a8ff | 585 | */ |
| bogdanm | 0:9b334a45a8ff | 586 | |
| bogdanm | 0:9b334a45a8ff | 587 | /** @defgroup RCC_USB_Device_clock_source |
| bogdanm | 0:9b334a45a8ff | 588 | * @{ |
| bogdanm | 0:9b334a45a8ff | 589 | */ |
| bogdanm | 0:9b334a45a8ff | 590 | |
| bogdanm | 0:9b334a45a8ff | 591 | #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) |
| bogdanm | 0:9b334a45a8ff | 592 | #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) |
| bogdanm | 0:9b334a45a8ff | 593 | |
| bogdanm | 0:9b334a45a8ff | 594 | #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ |
| bogdanm | 0:9b334a45a8ff | 595 | ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) |
| bogdanm | 0:9b334a45a8ff | 596 | /** |
| bogdanm | 0:9b334a45a8ff | 597 | * @} |
| bogdanm | 0:9b334a45a8ff | 598 | */ |
| bogdanm | 0:9b334a45a8ff | 599 | |
| bogdanm | 0:9b334a45a8ff | 600 | /** @defgroup RCC_Flag |
| bogdanm | 0:9b334a45a8ff | 601 | * @{ |
| bogdanm | 0:9b334a45a8ff | 602 | */ |
| bogdanm | 0:9b334a45a8ff | 603 | #define RCC_FLAG_HSIRDY ((uint8_t)0x01) |
| bogdanm | 0:9b334a45a8ff | 604 | #define RCC_FLAG_HSERDY ((uint8_t)0x11) |
| bogdanm | 0:9b334a45a8ff | 605 | #define RCC_FLAG_PLLRDY ((uint8_t)0x19) |
| bogdanm | 0:9b334a45a8ff | 606 | #define RCC_FLAG_MCOF ((uint8_t)0x9C) |
| bogdanm | 0:9b334a45a8ff | 607 | #define RCC_FLAG_LSERDY ((uint8_t)0x21) |
| bogdanm | 0:9b334a45a8ff | 608 | #define RCC_FLAG_LSIRDY ((uint8_t)0x41) |
| bogdanm | 0:9b334a45a8ff | 609 | #define RCC_FLAG_OBLRST ((uint8_t)0x59) |
| bogdanm | 0:9b334a45a8ff | 610 | #define RCC_FLAG_PINRST ((uint8_t)0x5A) |
| bogdanm | 0:9b334a45a8ff | 611 | #define RCC_FLAG_PORRST ((uint8_t)0x5B) |
| bogdanm | 0:9b334a45a8ff | 612 | #define RCC_FLAG_SFTRST ((uint8_t)0x5C) |
| bogdanm | 0:9b334a45a8ff | 613 | #define RCC_FLAG_IWDGRST ((uint8_t)0x5D) |
| bogdanm | 0:9b334a45a8ff | 614 | #define RCC_FLAG_WWDGRST ((uint8_t)0x5E) |
| bogdanm | 0:9b334a45a8ff | 615 | #define RCC_FLAG_LPWRRST ((uint8_t)0x5F) |
| bogdanm | 0:9b334a45a8ff | 616 | |
| bogdanm | 0:9b334a45a8ff | 617 | #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ |
| bogdanm | 0:9b334a45a8ff | 618 | ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ |
| bogdanm | 0:9b334a45a8ff | 619 | ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \ |
| bogdanm | 0:9b334a45a8ff | 620 | ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ |
| bogdanm | 0:9b334a45a8ff | 621 | ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ |
| bogdanm | 0:9b334a45a8ff | 622 | ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \ |
| bogdanm | 0:9b334a45a8ff | 623 | ((FLAG) == RCC_FLAG_MCOF)) |
| bogdanm | 0:9b334a45a8ff | 624 | |
| bogdanm | 0:9b334a45a8ff | 625 | #define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) |
| bogdanm | 0:9b334a45a8ff | 626 | |
| bogdanm | 0:9b334a45a8ff | 627 | /** |
| bogdanm | 0:9b334a45a8ff | 628 | * @} |
| bogdanm | 0:9b334a45a8ff | 629 | */ |
| bogdanm | 0:9b334a45a8ff | 630 | |
| bogdanm | 0:9b334a45a8ff | 631 | /** |
| bogdanm | 0:9b334a45a8ff | 632 | * @} |
| bogdanm | 0:9b334a45a8ff | 633 | */ |
| bogdanm | 0:9b334a45a8ff | 634 | |
| bogdanm | 0:9b334a45a8ff | 635 | /* Exported macro ------------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 636 | /* Exported functions ------------------------------------------------------- */ |
| bogdanm | 0:9b334a45a8ff | 637 | |
| bogdanm | 0:9b334a45a8ff | 638 | /* Function used to set the RCC clock configuration to the default reset state */ |
| bogdanm | 0:9b334a45a8ff | 639 | void RCC_DeInit(void); |
| bogdanm | 0:9b334a45a8ff | 640 | |
| bogdanm | 0:9b334a45a8ff | 641 | /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ |
| bogdanm | 0:9b334a45a8ff | 642 | void RCC_HSEConfig(uint8_t RCC_HSE); |
| bogdanm | 0:9b334a45a8ff | 643 | ErrorStatus RCC_WaitForHSEStartUp(void); |
| bogdanm | 0:9b334a45a8ff | 644 | void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); |
| bogdanm | 0:9b334a45a8ff | 645 | void RCC_HSICmd(FunctionalState NewState); |
| bogdanm | 0:9b334a45a8ff | 646 | void RCC_LSEConfig(uint32_t RCC_LSE); |
| bogdanm | 0:9b334a45a8ff | 647 | void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive); |
| bogdanm | 0:9b334a45a8ff | 648 | void RCC_LSICmd(FunctionalState NewState); |
| bogdanm | 0:9b334a45a8ff | 649 | void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); |
| bogdanm | 0:9b334a45a8ff | 650 | void RCC_PLLCmd(FunctionalState NewState); |
| bogdanm | 0:9b334a45a8ff | 651 | void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div); |
| bogdanm | 0:9b334a45a8ff | 652 | void RCC_ClockSecuritySystemCmd(FunctionalState NewState); |
| bogdanm | 0:9b334a45a8ff | 653 | #ifdef STM32F303xC |
| bogdanm | 0:9b334a45a8ff | 654 | void RCC_MCOConfig(uint8_t RCC_MCOSource); |
| bogdanm | 0:9b334a45a8ff | 655 | #else |
| bogdanm | 0:9b334a45a8ff | 656 | void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler); |
| bogdanm | 0:9b334a45a8ff | 657 | #endif /* STM32F303xC */ |
| bogdanm | 0:9b334a45a8ff | 658 | |
| bogdanm | 0:9b334a45a8ff | 659 | /* System, AHB and APB busses clocks configuration functions ******************/ |
| bogdanm | 0:9b334a45a8ff | 660 | void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); |
| bogdanm | 0:9b334a45a8ff | 661 | uint8_t RCC_GetSYSCLKSource(void); |
| bogdanm | 0:9b334a45a8ff | 662 | void RCC_HCLKConfig(uint32_t RCC_SYSCLK); |
| bogdanm | 0:9b334a45a8ff | 663 | void RCC_PCLK1Config(uint32_t RCC_HCLK); |
| bogdanm | 0:9b334a45a8ff | 664 | void RCC_PCLK2Config(uint32_t RCC_HCLK); |
| bogdanm | 0:9b334a45a8ff | 665 | void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); |
| bogdanm | 0:9b334a45a8ff | 666 | |
| bogdanm | 0:9b334a45a8ff | 667 | /* Peripheral clocks configuration functions **********************************/ |
| bogdanm | 0:9b334a45a8ff | 668 | void RCC_ADCCLKConfig(uint32_t RCC_PLLCLK); |
| bogdanm | 0:9b334a45a8ff | 669 | void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK); |
| bogdanm | 0:9b334a45a8ff | 670 | void RCC_TIMCLKConfig(uint32_t RCC_TIMCLK); |
| bogdanm | 0:9b334a45a8ff | 671 | void RCC_HRTIM1CLKConfig(uint32_t RCC_HRTIMCLK); |
| bogdanm | 0:9b334a45a8ff | 672 | void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); |
| bogdanm | 0:9b334a45a8ff | 673 | void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK); |
| bogdanm | 0:9b334a45a8ff | 674 | void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); |
| bogdanm | 0:9b334a45a8ff | 675 | |
| bogdanm | 0:9b334a45a8ff | 676 | void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); |
| bogdanm | 0:9b334a45a8ff | 677 | void RCC_RTCCLKCmd(FunctionalState NewState); |
| bogdanm | 0:9b334a45a8ff | 678 | void RCC_BackupResetCmd(FunctionalState NewState); |
| bogdanm | 0:9b334a45a8ff | 679 | |
| bogdanm | 0:9b334a45a8ff | 680 | void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); |
| bogdanm | 0:9b334a45a8ff | 681 | void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); |
| bogdanm | 0:9b334a45a8ff | 682 | void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); |
| bogdanm | 0:9b334a45a8ff | 683 | |
| bogdanm | 0:9b334a45a8ff | 684 | void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); |
| bogdanm | 0:9b334a45a8ff | 685 | void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); |
| bogdanm | 0:9b334a45a8ff | 686 | void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); |
| bogdanm | 0:9b334a45a8ff | 687 | |
| bogdanm | 0:9b334a45a8ff | 688 | /* Interrupts and flags management functions **********************************/ |
| bogdanm | 0:9b334a45a8ff | 689 | void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); |
| bogdanm | 0:9b334a45a8ff | 690 | FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); |
| bogdanm | 0:9b334a45a8ff | 691 | void RCC_ClearFlag(void); |
| bogdanm | 0:9b334a45a8ff | 692 | ITStatus RCC_GetITStatus(uint8_t RCC_IT); |
| bogdanm | 0:9b334a45a8ff | 693 | void RCC_ClearITPendingBit(uint8_t RCC_IT); |
| bogdanm | 0:9b334a45a8ff | 694 | |
| bogdanm | 0:9b334a45a8ff | 695 | #ifdef __cplusplus |
| bogdanm | 0:9b334a45a8ff | 696 | } |
| bogdanm | 0:9b334a45a8ff | 697 | #endif |
| bogdanm | 0:9b334a45a8ff | 698 | |
| bogdanm | 0:9b334a45a8ff | 699 | #endif /* __STM32F30x_RCC_H */ |
| bogdanm | 0:9b334a45a8ff | 700 | |
| bogdanm | 0:9b334a45a8ff | 701 | /** |
| bogdanm | 0:9b334a45a8ff | 702 | * @} |
| bogdanm | 0:9b334a45a8ff | 703 | */ |
| bogdanm | 0:9b334a45a8ff | 704 | |
| bogdanm | 0:9b334a45a8ff | 705 | /** |
| bogdanm | 0:9b334a45a8ff | 706 | * @} |
| bogdanm | 0:9b334a45a8ff | 707 | */ |
| bogdanm | 0:9b334a45a8ff | 708 | |
| bogdanm | 0:9b334a45a8ff | 709 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |