Julien Cassette / mbed-dev

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targets/cmsis/TARGET_STM/TARGET_STM32F3XX/stm32f30x_hrtim.c@79:9f34958201cc, 2016-03-14 (annotated)

Committer:
jcassette
Date:
Mon Mar 14 14:20:17 2016 +0000
Revision:
79:9f34958201cc
Parent:
0:9b334a45a8ff 
FRDM-K64F AnalogIn: add support for ADC channels with no mapped pins

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f30x_hrtim.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.1.0
bogdanm 0:9b334a45a8ff 6 * @date 27-February-2014
bogdanm 0:9b334a45a8ff 7 * @brief HRTIMx module driver.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 10 * functionalities of the HRTIMx peripheral:
bogdanm 0:9b334a45a8ff 11 * + Initialization/de-initialization methods
bogdanm 0:9b334a45a8ff 12 * + I/O operation methods
bogdanm 0:9b334a45a8ff 13 * + Peripheral Control methods
bogdanm 0:9b334a45a8ff 14 *
bogdanm 0:9b334a45a8ff 15 @verbatim
bogdanm 0:9b334a45a8ff 16 ================================================================================
bogdanm 0:9b334a45a8ff 17 ##### <HRTIM specific features> #####
bogdanm 0:9b334a45a8ff 18 ================================================================================
bogdanm 0:9b334a45a8ff 19
bogdanm 0:9b334a45a8ff 20 [..] < HRTIM introduction:
bogdanm 0:9b334a45a8ff 21 (#) The high-resolution timer can generate up to 10 digital signals with
bogdanm 0:9b334a45a8ff 22 highly accurate timings.
bogdanm 0:9b334a45a8ff 23 It is primarily intended to drive power conversion systems such as
bogdanm 0:9b334a45a8ff 24 switch mode power supplies or lighting systems,
bogdanm 0:9b334a45a8ff 25 but can be of general purpose usage, whenever a very fine timing
bogdanm 0:9b334a45a8ff 26 resolution is expected.
bogdanm 0:9b334a45a8ff 27
bogdanm 0:9b334a45a8ff 28 (#) Its modular architecture allows to generate either independent or
bogdanm 0:9b334a45a8ff 29 coupled waveforms.
bogdanm 0:9b334a45a8ff 30 The wave-shape is defined by self-contained timings
bogdanm 0:9b334a45a8ff 31 (using counters and compare units) and a broad range of external events,
bogdanm 0:9b334a45a8ff 32 such as analog or digital feedbacks and synchronisation signals.
bogdanm 0:9b334a45a8ff 33 This allows to produce a large variety of control signal (PWM, phase-shifted,
bogdanm 0:9b334a45a8ff 34 constant Ton,...) and address most of conversion topologies.
bogdanm 0:9b334a45a8ff 35
bogdanm 0:9b334a45a8ff 36 (#) For control and monitoring purposes, the timer has also timing measure
bogdanm 0:9b334a45a8ff 37 capabilities and links to built-in ADC and DAC converters.
bogdanm 0:9b334a45a8ff 38 Last, it features light-load management mode and is able to handle
bogdanm 0:9b334a45a8ff 39 various fault schemes for safe shut-down purposes.
bogdanm 0:9b334a45a8ff 40
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 43 ================================================================================
bogdanm 0:9b334a45a8ff 44 [..] This driver provides functions to configure and program the HRTIM
bogdanm 0:9b334a45a8ff 45 of all stm32f33x devices.
bogdanm 0:9b334a45a8ff 46 These functions are split in 9 groups:
bogdanm 0:9b334a45a8ff 47
bogdanm 0:9b334a45a8ff 48 (#) HRTIM Simple TimeBase management: this group includes all needed functions
bogdanm 0:9b334a45a8ff 49 to configure the HRTIM Timebase unit:
bogdanm 0:9b334a45a8ff 50 (++) Initializes the HRTIMx timer in simple time base mode
bogdanm 0:9b334a45a8ff 51 (++) Start/Stop the time base generation
bogdanm 0:9b334a45a8ff 52 (++) Deinitialize the HRTIM peripheral
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54
bogdanm 0:9b334a45a8ff 55 (#) HRTIM simple Output Compare management: this group includes all needed
bogdanm 0:9b334a45a8ff 56 functions to configure the Compare unit used in Output compare mode:
bogdanm 0:9b334a45a8ff 57 (++) Initializes the HRTIMx timer time base unit
bogdanm 0:9b334a45a8ff 58 (++) Configure the compare unit in in simple Output Compare mode
bogdanm 0:9b334a45a8ff 59 (++) Start/Stop the Output compare generation
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 (#) HRTIM simple PWM management: this group includes all needed
bogdanm 0:9b334a45a8ff 62 functions to configure the Compare unit used in PWM mode:
bogdanm 0:9b334a45a8ff 63 (++) Initializes the HRTIMx timer time base unit
bogdanm 0:9b334a45a8ff 64 (++) Configure the compare unit in in simple PWM mode
bogdanm 0:9b334a45a8ff 65 (++) Start/Stop the PWM generation
bogdanm 0:9b334a45a8ff 66
bogdanm 0:9b334a45a8ff 67 (#) HRTIM simple Capture management: this group includes all needed
bogdanm 0:9b334a45a8ff 68 functions to configure the Capture unit used in Capture mode:
bogdanm 0:9b334a45a8ff 69 (++) Initializes the HRTIMx timer time base unit
bogdanm 0:9b334a45a8ff 70 (++) Configure the compare unit in in simple Capture mode
bogdanm 0:9b334a45a8ff 71 (++) Start/Stop the Capture mode
bogdanm 0:9b334a45a8ff 72
bogdanm 0:9b334a45a8ff 73 (#) HRTIM simple One Pulse management: this group includes all needed
bogdanm 0:9b334a45a8ff 74 functions to configure the Capture unit and Compare unit used in One Pulse mode:
bogdanm 0:9b334a45a8ff 75 (++) Initializes the HRTIMx timer time base unit
bogdanm 0:9b334a45a8ff 76 (++) Configure the compare unit and the capture unit in in simple One Pulse mode
bogdanm 0:9b334a45a8ff 77 (++) Start/Stop the One Pulse mode generation
bogdanm 0:9b334a45a8ff 78
bogdanm 0:9b334a45a8ff 79 (#) HRTIM Waveform management: this group includes all needed
bogdanm 0:9b334a45a8ff 80 functions to configure the HRTIM possible waveform mode:
bogdanm 0:9b334a45a8ff 81 (++) Initializes the HRTIMx timer Master time base unit
bogdanm 0:9b334a45a8ff 82 (++) Initializes the HRTIMx timer Slaves time base unit
bogdanm 0:9b334a45a8ff 83 (++) Configures the HRTIMx timer Compare unit
bogdanm 0:9b334a45a8ff 84 (++) Configures the HRTIMx Slave timer Capture unit
bogdanm 0:9b334a45a8ff 85 (++) Configures the HRTIMx timer Output unit
bogdanm 0:9b334a45a8ff 86 (++) Configures the HRTIMx timer DeadTime / Chopper / Burst features
bogdanm 0:9b334a45a8ff 87 (++) Configures the HRTIMx timer Fault / External event features
bogdanm 0:9b334a45a8ff 88 (++) Configures the HRTIMx timer Synchronization features: Internal/External connection, DACs,...
bogdanm 0:9b334a45a8ff 89 (++) Configures the HRTIMx timer Synchronization features: ADCs Triggers
bogdanm 0:9b334a45a8ff 90 (++) HRTIMx timer Outputs Start/Stop
bogdanm 0:9b334a45a8ff 91 (++) Start/Stop the HRTIMx Timer counters
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 (#) HRTIM interrupts, DMA and flags management
bogdanm 0:9b334a45a8ff 94 (++) Enable/Disable interrupt sources
bogdanm 0:9b334a45a8ff 95 (++) Get flags status
bogdanm 0:9b334a45a8ff 96 (++) Clear flags/ Pending bits
bogdanm 0:9b334a45a8ff 97 (++) Enable/Disable DMA requests
bogdanm 0:9b334a45a8ff 98 (++) Configure DMA burst mode
bogdanm 0:9b334a45a8ff 99
bogdanm 0:9b334a45a8ff 100 (#) TIM specific interface management, this group includes all
bogdanm 0:9b334a45a8ff 101 needed functions to use the specific TIM interface:
bogdanm 0:9b334a45a8ff 102 (++) HRTIMx timer DLL calibration
bogdanm 0:9b334a45a8ff 103
bogdanm 0:9b334a45a8ff 104 @endverbatim
bogdanm 0:9b334a45a8ff 105 ******************************************************************************
bogdanm 0:9b334a45a8ff 106 * @attention
bogdanm 0:9b334a45a8ff 107 *
bogdanm 0:9b334a45a8ff 108 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 109 *
bogdanm 0:9b334a45a8ff 110 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 111 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 112 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 113 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 114 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 115 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 116 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 117 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 118 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 119 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 120 *
bogdanm 0:9b334a45a8ff 121 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 122 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 123 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 124 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 125 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 126 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 127 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 128 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 129 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 130 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 131 *
bogdanm 0:9b334a45a8ff 132 ******************************************************************************
bogdanm 0:9b334a45a8ff 133 */
bogdanm 0:9b334a45a8ff 134 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 135 #include "stm32f30x_hrtim.h"
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 /** @addtogroup STM32F30x_StdPeriph_Driver
bogdanm 0:9b334a45a8ff 138 * @{
bogdanm 0:9b334a45a8ff 139 */
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 /** @defgroup HRTIM
bogdanm 0:9b334a45a8ff 142 * @brief HRTIM driver module
bogdanm 0:9b334a45a8ff 143 * @{
bogdanm 0:9b334a45a8ff 144 */
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 147 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 148 #define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
bogdanm 0:9b334a45a8ff 149 HRTIM_FLTR_FLT2EN |\
bogdanm 0:9b334a45a8ff 150 HRTIM_FLTR_FLT3EN |\
bogdanm 0:9b334a45a8ff 151 HRTIM_FLTR_FLT4EN | \
bogdanm 0:9b334a45a8ff 152 HRTIM_FLTR_FLT5EN)
bogdanm 0:9b334a45a8ff 153
bogdanm 0:9b334a45a8ff 154 #define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER |\
bogdanm 0:9b334a45a8ff 155 HRTIM_TIMUPDATETRIGGER_TIMER_A |\
bogdanm 0:9b334a45a8ff 156 HRTIM_TIMUPDATETRIGGER_TIMER_B |\
bogdanm 0:9b334a45a8ff 157 HRTIM_TIMUPDATETRIGGER_TIMER_C |\
bogdanm 0:9b334a45a8ff 158 HRTIM_TIMUPDATETRIGGER_TIMER_D |\
bogdanm 0:9b334a45a8ff 159 HRTIM_TIMUPDATETRIGGER_TIMER_E)
bogdanm 0:9b334a45a8ff 160
bogdanm 0:9b334a45a8ff 161 #define HRTIM_TIM_OFFSET (uint32_t)0x00000080
bogdanm 0:9b334a45a8ff 162 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 163 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 164 static uint32_t TimerIdxToTimerId[] =
bogdanm 0:9b334a45a8ff 165 {
bogdanm 0:9b334a45a8ff 166 HRTIM_TIMERID_TIMER_A,
bogdanm 0:9b334a45a8ff 167 HRTIM_TIMERID_TIMER_B,
bogdanm 0:9b334a45a8ff 168 HRTIM_TIMERID_TIMER_C,
bogdanm 0:9b334a45a8ff 169 HRTIM_TIMERID_TIMER_D,
bogdanm 0:9b334a45a8ff 170 HRTIM_TIMERID_TIMER_E,
bogdanm 0:9b334a45a8ff 171 HRTIM_TIMERID_MASTER,
bogdanm 0:9b334a45a8ff 172 };
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 175 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 176 static void HRTIM_MasterBase_Config(HRTIM_TypeDef* HRTIMx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruc);
bogdanm 0:9b334a45a8ff 177 static void HRTIM_TimingUnitBase_Config(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
bogdanm 0:9b334a45a8ff 178 static void HRTIM_MasterWaveform_Config(HRTIM_TypeDef * HRTIMx, HRTIM_TimerInitTypeDef * TimerInit);
bogdanm 0:9b334a45a8ff 179 static void HRTIM_TimingUnitWaveform_Config(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 180 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 181 HRTIM_TimerInitTypeDef * TimerInit);
bogdanm 0:9b334a45a8ff 182 static void HRTIM_CompareUnitConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 183 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 184 uint32_t CompareUnit,
bogdanm 0:9b334a45a8ff 185 HRTIM_CompareCfgTypeDef * CompareCfg);
bogdanm 0:9b334a45a8ff 186 static void HRTIM_CaptureUnitConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 187 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 188 uint32_t CaptureUnit,
bogdanm 0:9b334a45a8ff 189 uint32_t Event);
bogdanm 0:9b334a45a8ff 190 static void HRTIM_OutputConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 191 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 192 uint32_t Output,
bogdanm 0:9b334a45a8ff 193 HRTIM_OutputCfgTypeDef * OutputCfg);
bogdanm 0:9b334a45a8ff 194 static void HRTIM_ExternalEventConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 195 uint32_t Event,
bogdanm 0:9b334a45a8ff 196 HRTIM_EventCfgTypeDef * EventCfg);
bogdanm 0:9b334a45a8ff 197 static void HRTIM_TIM_ResetConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 198 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 199 uint32_t Event);
bogdanm 0:9b334a45a8ff 200 /** @defgroup HRTIM_Private_Functions
bogdanm 0:9b334a45a8ff 201 * @{
bogdanm 0:9b334a45a8ff 202 */
bogdanm 0:9b334a45a8ff 203
bogdanm 0:9b334a45a8ff 204 /** @defgroup HRTIM_Group1 Initialization/de-initialization methods
bogdanm 0:9b334a45a8ff 205 * @brief Initialization and Configuration functions
bogdanm 0:9b334a45a8ff 206 *
bogdanm 0:9b334a45a8ff 207 @verbatim
bogdanm 0:9b334a45a8ff 208 ===============================================================================
bogdanm 0:9b334a45a8ff 209 ##### Initialization/de-initialization methods #####
bogdanm 0:9b334a45a8ff 210 ===============================================================================
bogdanm 0:9b334a45a8ff 211 [..] This section provides functions allowing to:
bogdanm 0:9b334a45a8ff 212 (+)Initializes timer in basic time base mode
bogdanm 0:9b334a45a8ff 213 (+)Initializes timer in basic OC mode
bogdanm 0:9b334a45a8ff 214 (+)Initializes timer in basic PWM mode
bogdanm 0:9b334a45a8ff 215 (+)Initializes timer in basic Capture mode
bogdanm 0:9b334a45a8ff 216 (+)Initializes timer in One Pulse mode
bogdanm 0:9b334a45a8ff 217 (+)Initializes a timer operating in waveform mode
bogdanm 0:9b334a45a8ff 218 (+)De-initializes the HRTIMx timer
bogdanm 0:9b334a45a8ff 219
bogdanm 0:9b334a45a8ff 220 @endverbatim
bogdanm 0:9b334a45a8ff 221 * @{
bogdanm 0:9b334a45a8ff 222 */
bogdanm 0:9b334a45a8ff 223
bogdanm 0:9b334a45a8ff 224 /**
bogdanm 0:9b334a45a8ff 225 * @brief Initializes the HRTIMx timer in basic time base mode
bogdanm 0:9b334a45a8ff 226 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 227 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 228 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 229 * @arg 0x0 for master timer
bogdanm 0:9b334a45a8ff 230 * @arg 0x1 to 0x5 for timers A to E
bogdanm 0:9b334a45a8ff 231 * @note The time-base unit initialization parameters specify:
bogdanm 0:9b334a45a8ff 232 * The timer counter operating mode (continuous, one shot)
bogdanm 0:9b334a45a8ff 233 * The timer clock prescaler
bogdanm 0:9b334a45a8ff 234 * The timer period
bogdanm 0:9b334a45a8ff 235 * The timer repetition counter.
bogdanm 0:9b334a45a8ff 236 * @retval None
bogdanm 0:9b334a45a8ff 237 */
bogdanm 0:9b334a45a8ff 238 void HRTIM_SimpleBase_Init(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
bogdanm 0:9b334a45a8ff 239 {
bogdanm 0:9b334a45a8ff 240 /* Check the parameters */
bogdanm 0:9b334a45a8ff 241 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
bogdanm 0:9b334a45a8ff 242 assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
bogdanm 0:9b334a45a8ff 243
bogdanm 0:9b334a45a8ff 244 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
bogdanm 0:9b334a45a8ff 245 {
bogdanm 0:9b334a45a8ff 246 /* Configure master timer */
bogdanm 0:9b334a45a8ff 247 HRTIM_MasterBase_Config(HRTIMx, HRTIM_BaseInitStruct);
bogdanm 0:9b334a45a8ff 248 }
bogdanm 0:9b334a45a8ff 249 else
bogdanm 0:9b334a45a8ff 250 {
bogdanm 0:9b334a45a8ff 251 /* Configure timing unit */
bogdanm 0:9b334a45a8ff 252 HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
bogdanm 0:9b334a45a8ff 253 }
bogdanm 0:9b334a45a8ff 254 }
bogdanm 0:9b334a45a8ff 255
bogdanm 0:9b334a45a8ff 256 /**
bogdanm 0:9b334a45a8ff 257 * @brief De-initializes a timer operating in all mode
bogdanm 0:9b334a45a8ff 258 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 259 * @retval None
bogdanm 0:9b334a45a8ff 260 */
bogdanm 0:9b334a45a8ff 261 void HRTIM_DeInit(HRTIM_TypeDef* HRTIMx)
bogdanm 0:9b334a45a8ff 262 {
bogdanm 0:9b334a45a8ff 263 /* Check the parameters */
bogdanm 0:9b334a45a8ff 264 RCC_APB2PeriphResetCmd(RCC_APB2Periph_HRTIM1, ENABLE);
bogdanm 0:9b334a45a8ff 265 RCC_APB2PeriphResetCmd(RCC_APB2Periph_HRTIM1, DISABLE);
bogdanm 0:9b334a45a8ff 266 }
bogdanm 0:9b334a45a8ff 267
bogdanm 0:9b334a45a8ff 268 /**
bogdanm 0:9b334a45a8ff 269 * @brief Initializes the HRTIMx timer in basic output compare mode
bogdanm 0:9b334a45a8ff 270 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 271 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 272 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 273 * @arg 0x1 to 0x5 for timers A to E
bogdanm 0:9b334a45a8ff 274 * @note Initializes the time-base unit of the timer and prepare it to
bogdanm 0:9b334a45a8ff 275 * operate in output compare mode
bogdanm 0:9b334a45a8ff 276 * @retval None
bogdanm 0:9b334a45a8ff 277 */
bogdanm 0:9b334a45a8ff 278 void HRTIM_SimpleOC_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
bogdanm 0:9b334a45a8ff 279 {
bogdanm 0:9b334a45a8ff 280 /* Check the parameters */
bogdanm 0:9b334a45a8ff 281 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
bogdanm 0:9b334a45a8ff 282 assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
bogdanm 0:9b334a45a8ff 283
bogdanm 0:9b334a45a8ff 284 /* Configure timing unit */
bogdanm 0:9b334a45a8ff 285 HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
bogdanm 0:9b334a45a8ff 286 }
bogdanm 0:9b334a45a8ff 287
bogdanm 0:9b334a45a8ff 288 /**
bogdanm 0:9b334a45a8ff 289 * @brief Initializes the HRTIMx timer in basic PWM mode
bogdanm 0:9b334a45a8ff 290 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 291 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 292 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 293 * @arg 0x1 to 0x5 for timers A to E
bogdanm 0:9b334a45a8ff 294 * @note Initializes the time-base unit of the timer and prepare it to
bogdanm 0:9b334a45a8ff 295 * operate in capture mode
bogdanm 0:9b334a45a8ff 296 * @retval None
bogdanm 0:9b334a45a8ff 297 */
bogdanm 0:9b334a45a8ff 298 void HRTIM_SimplePWM_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
bogdanm 0:9b334a45a8ff 299 {
bogdanm 0:9b334a45a8ff 300 /* Check the parameters */
bogdanm 0:9b334a45a8ff 301 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
bogdanm 0:9b334a45a8ff 302 assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304 /* Configure timing unit */
bogdanm 0:9b334a45a8ff 305 HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
bogdanm 0:9b334a45a8ff 306 }
bogdanm 0:9b334a45a8ff 307
bogdanm 0:9b334a45a8ff 308 /**
bogdanm 0:9b334a45a8ff 309 * @brief Initializes a timer operating in basic capture mode
bogdanm 0:9b334a45a8ff 310 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 311 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 312 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 313 * @arg 0x1 to 0x5 for timers A to E
bogdanm 0:9b334a45a8ff 314 * @retval None
bogdanm 0:9b334a45a8ff 315 */
bogdanm 0:9b334a45a8ff 316 void HRTIM_SimpleCapture_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
bogdanm 0:9b334a45a8ff 317 {
bogdanm 0:9b334a45a8ff 318 /* Check the parameters */
bogdanm 0:9b334a45a8ff 319 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
bogdanm 0:9b334a45a8ff 320 assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
bogdanm 0:9b334a45a8ff 321
bogdanm 0:9b334a45a8ff 322 /* Configure timing unit */
bogdanm 0:9b334a45a8ff 323 HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
bogdanm 0:9b334a45a8ff 324 }
bogdanm 0:9b334a45a8ff 325
bogdanm 0:9b334a45a8ff 326 /**
bogdanm 0:9b334a45a8ff 327 * @brief Initializes the HRTIMx timer in basic one pulse mode
bogdanm 0:9b334a45a8ff 328 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 329 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 330 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 331 * @arg 0x1 to 0x5 for timers A to E
bogdanm 0:9b334a45a8ff 332 * @note Initializes the time-base unit of the timer and prepare it to
bogdanm 0:9b334a45a8ff 333 * operate in one pulse mode. In this mode the counter operates
bogdanm 0:9b334a45a8ff 334 * in single shot mode (retriggerable or not)
bogdanm 0:9b334a45a8ff 335 * @retval None
bogdanm 0:9b334a45a8ff 336 */
bogdanm 0:9b334a45a8ff 337 void HRTIM_SimpleOnePulse_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
bogdanm 0:9b334a45a8ff 338 {
bogdanm 0:9b334a45a8ff 339 /* Check the parameters */
bogdanm 0:9b334a45a8ff 340 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
bogdanm 0:9b334a45a8ff 341 assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
bogdanm 0:9b334a45a8ff 342
bogdanm 0:9b334a45a8ff 343 /* Configure timing unit */
bogdanm 0:9b334a45a8ff 344 HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
bogdanm 0:9b334a45a8ff 345 }
bogdanm 0:9b334a45a8ff 346
bogdanm 0:9b334a45a8ff 347 /**
bogdanm 0:9b334a45a8ff 348 * @brief Initializes a timer operating in waveform mode
bogdanm 0:9b334a45a8ff 349 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 350 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 351 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 352 * @arg 0x0 for master timer
bogdanm 0:9b334a45a8ff 353 * @arg 0x1 to 0x5 for timers A to E
bogdanm 0:9b334a45a8ff 354 * @param pTimerInit: pointer to the timer initialization data structure
bogdanm 0:9b334a45a8ff 355 * @retval None
bogdanm 0:9b334a45a8ff 356 */
bogdanm 0:9b334a45a8ff 357 void HRTIM_Waveform_Init(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 358 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 359 HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct,
bogdanm 0:9b334a45a8ff 360 HRTIM_TimerInitTypeDef* HRTIM_TimerInitStruct)
bogdanm 0:9b334a45a8ff 361 {
bogdanm 0:9b334a45a8ff 362 /* Check the parameters */
bogdanm 0:9b334a45a8ff 363 assert_param(IS_HRTIM_HALFMODE(HRTIM_TimerInitStruct->HalfModeEnable));
bogdanm 0:9b334a45a8ff 364 assert_param(IS_HRTIM_SYNCSTART(HRTIM_TimerInitStruct->StartOnSync));
bogdanm 0:9b334a45a8ff 365 assert_param(IS_HRTIM_SYNCRESET(HRTIM_TimerInitStruct->ResetOnSync));
bogdanm 0:9b334a45a8ff 366 assert_param(IS_HRTIM_DACSYNC(HRTIM_TimerInitStruct->DACSynchro));
bogdanm 0:9b334a45a8ff 367 assert_param(IS_HRTIM_PRELOAD(HRTIM_TimerInitStruct->PreloadEnable));
bogdanm 0:9b334a45a8ff 368 assert_param(IS_HRTIM_TIMERBURSTMODE(HRTIM_TimerInitStruct->BurstMode));
bogdanm 0:9b334a45a8ff 369 assert_param(IS_HRTIM_UPDATEONREPETITION(HRTIM_TimerInitStruct->RepetitionUpdate));
bogdanm 0:9b334a45a8ff 370
bogdanm 0:9b334a45a8ff 371 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
bogdanm 0:9b334a45a8ff 372 {
bogdanm 0:9b334a45a8ff 373 /* Check parameters */
bogdanm 0:9b334a45a8ff 374 assert_param(IS_HRTIM_UPDATEGATING_MASTER(HRTIM_TimerInitStruct->UpdateGating));
bogdanm 0:9b334a45a8ff 375
bogdanm 0:9b334a45a8ff 376 /* Configure master timer */
bogdanm 0:9b334a45a8ff 377 HRTIM_MasterBase_Config(HRTIMx, HRTIM_BaseInitStruct);
bogdanm 0:9b334a45a8ff 378 HRTIM_MasterWaveform_Config(HRTIMx, HRTIM_TimerInitStruct);
bogdanm 0:9b334a45a8ff 379 }
bogdanm 0:9b334a45a8ff 380 else
bogdanm 0:9b334a45a8ff 381 {
bogdanm 0:9b334a45a8ff 382 /* Check parameters */
bogdanm 0:9b334a45a8ff 383 assert_param(IS_HRTIM_UPDATEGATING_TIM(HRTIM_TimerInitStruct->UpdateGating));
bogdanm 0:9b334a45a8ff 384
bogdanm 0:9b334a45a8ff 385 /* Configure timing unit */
bogdanm 0:9b334a45a8ff 386 HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
bogdanm 0:9b334a45a8ff 387 HRTIM_TimingUnitWaveform_Config(HRTIMx, TimerIdx, HRTIM_TimerInitStruct);
bogdanm 0:9b334a45a8ff 388 }
bogdanm 0:9b334a45a8ff 389 }
bogdanm 0:9b334a45a8ff 390
bogdanm 0:9b334a45a8ff 391 /**
bogdanm 0:9b334a45a8ff 392 * @}
bogdanm 0:9b334a45a8ff 393 */
bogdanm 0:9b334a45a8ff 394
bogdanm 0:9b334a45a8ff 395 /** @defgroup HRTIM_Group2 I/O operation methods
bogdanm 0:9b334a45a8ff 396 * @brief Data transfers functions
bogdanm 0:9b334a45a8ff 397 *
bogdanm 0:9b334a45a8ff 398 @verbatim
bogdanm 0:9b334a45a8ff 399 ===============================================================================
bogdanm 0:9b334a45a8ff 400 ##### IO operation methods #####
bogdanm 0:9b334a45a8ff 401 ===============================================================================
bogdanm 0:9b334a45a8ff 402 [..]
bogdanm 0:9b334a45a8ff 403 This subsection provides a set of functions allowing to manage the HRTIMx data
bogdanm 0:9b334a45a8ff 404 transfers.
bogdanm 0:9b334a45a8ff 405 (+) Starts the DLL calibration.
bogdanm 0:9b334a45a8ff 406 (+) Starts / stops the counter of a timer operating in basic time base mode
bogdanm 0:9b334a45a8ff 407 (+) Starts / stops the output compare signal generation on the designed timer output
bogdanm 0:9b334a45a8ff 408 (+) Starts / stops the PWM output signal generation on the designed timer output
bogdanm 0:9b334a45a8ff 409 (+) Enables / disables a basic capture on the designed capture unit
bogdanm 0:9b334a45a8ff 410
bogdanm 0:9b334a45a8ff 411 @endverbatim
bogdanm 0:9b334a45a8ff 412 * @{
bogdanm 0:9b334a45a8ff 413 */
bogdanm 0:9b334a45a8ff 414
bogdanm 0:9b334a45a8ff 415 /**
bogdanm 0:9b334a45a8ff 416 * @brief Starts the DLL calibration
bogdanm 0:9b334a45a8ff 417 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 418 * @param CalibrationRate: DLL calibration period
bogdanm 0:9b334a45a8ff 419 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 420 * @arg HRTIM_CALIBRATIONRATE_7300: 7.3 ms
bogdanm 0:9b334a45a8ff 421 * @arg HRTIM_CALIBRATIONRATE_910: 910 us
bogdanm 0:9b334a45a8ff 422 * @arg HRTIM_CALIBRATIONRATE_114: 114 us
bogdanm 0:9b334a45a8ff 423 * @arg HRTIM_CALIBRATIONRATE_14: 14 us
bogdanm 0:9b334a45a8ff 424 * @retval None
bogdanm 0:9b334a45a8ff 425 */
bogdanm 0:9b334a45a8ff 426 void HRTIM_DLLCalibrationStart(HRTIM_TypeDef * HRTIMx, uint32_t CalibrationRate)
bogdanm 0:9b334a45a8ff 427 {
bogdanm 0:9b334a45a8ff 428 uint32_t HRTIM_dllcr;
bogdanm 0:9b334a45a8ff 429
bogdanm 0:9b334a45a8ff 430 /* Check the parameters */
bogdanm 0:9b334a45a8ff 431 assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
bogdanm 0:9b334a45a8ff 432
bogdanm 0:9b334a45a8ff 433 /* Configure DLL Calibration */
bogdanm 0:9b334a45a8ff 434 HRTIM_dllcr = (HRTIMx->HRTIM_COMMON).DLLCR;
bogdanm 0:9b334a45a8ff 435
bogdanm 0:9b334a45a8ff 436 /* Set the Calibration rate */
bogdanm 0:9b334a45a8ff 437 HRTIM_dllcr &= ~(HRTIM_DLLCR_CALRTE);
bogdanm 0:9b334a45a8ff 438 HRTIM_dllcr |= CalibrationRate;
bogdanm 0:9b334a45a8ff 439
bogdanm 0:9b334a45a8ff 440 /* Start DLL calibration */
bogdanm 0:9b334a45a8ff 441 HRTIM_dllcr |= HRTIM_DLLCR_CAL;
bogdanm 0:9b334a45a8ff 442
bogdanm 0:9b334a45a8ff 443 /* Update HRTIMx register */
bogdanm 0:9b334a45a8ff 444 (HRTIMx->HRTIM_COMMON).DLLCR = HRTIM_dllcr;
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 }
bogdanm 0:9b334a45a8ff 447 /**
bogdanm 0:9b334a45a8ff 448 * @brief Starts the counter of a timer operating in basic time base mode
bogdanm 0:9b334a45a8ff 449 * @param HRTIMx: pointer to HRTIM peripheral
bogdanm 0:9b334a45a8ff 450 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 451 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 452 * @arg 0x5 for master timer
bogdanm 0:9b334a45a8ff 453 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 454 * @retval None
bogdanm 0:9b334a45a8ff 455 */
bogdanm 0:9b334a45a8ff 456 void HRTIM_SimpleBaseStart(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx)
bogdanm 0:9b334a45a8ff 457 {
bogdanm 0:9b334a45a8ff 458 /* Check the parameters */
bogdanm 0:9b334a45a8ff 459 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
bogdanm 0:9b334a45a8ff 460
bogdanm 0:9b334a45a8ff 461 /* Enable the timer counter */
bogdanm 0:9b334a45a8ff 462 __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
bogdanm 0:9b334a45a8ff 463 }
bogdanm 0:9b334a45a8ff 464
bogdanm 0:9b334a45a8ff 465 /**
bogdanm 0:9b334a45a8ff 466 * @brief Stops the counter of a timer operating in basic time base mode
bogdanm 0:9b334a45a8ff 467 * @param HRTIMx: pointer to HRTIM peripheral
bogdanm 0:9b334a45a8ff 468 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 469 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 470 * @arg 0x5 for master timer
bogdanm 0:9b334a45a8ff 471 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 472 * @retval None
bogdanm 0:9b334a45a8ff 473 */
bogdanm 0:9b334a45a8ff 474 void HRTIM_SimpleBaseStop(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx)
bogdanm 0:9b334a45a8ff 475 {
bogdanm 0:9b334a45a8ff 476 /* Check the parameters */
bogdanm 0:9b334a45a8ff 477 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
bogdanm 0:9b334a45a8ff 478
bogdanm 0:9b334a45a8ff 479 /* Disable the timer counter */
bogdanm 0:9b334a45a8ff 480 __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
bogdanm 0:9b334a45a8ff 481 }
bogdanm 0:9b334a45a8ff 482
bogdanm 0:9b334a45a8ff 483 /**
bogdanm 0:9b334a45a8ff 484 * @brief Starts the output compare signal generation on the designed timer output
bogdanm 0:9b334a45a8ff 485 * @param HRTIMx: pointer to HRTIM peripheral
bogdanm 0:9b334a45a8ff 486 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 487 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 488 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 489 * @param OCChannel: Timer output
bogdanm 0:9b334a45a8ff 490 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 491 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
bogdanm 0:9b334a45a8ff 492 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
bogdanm 0:9b334a45a8ff 493 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
bogdanm 0:9b334a45a8ff 494 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
bogdanm 0:9b334a45a8ff 495 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
bogdanm 0:9b334a45a8ff 496 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
bogdanm 0:9b334a45a8ff 497 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
bogdanm 0:9b334a45a8ff 498 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
bogdanm 0:9b334a45a8ff 499 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
bogdanm 0:9b334a45a8ff 500 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
bogdanm 0:9b334a45a8ff 501 * @retval None
bogdanm 0:9b334a45a8ff 502 */
bogdanm 0:9b334a45a8ff 503 void HRTIM_SimpleOCStart(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 504 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 505 uint32_t OCChannel)
bogdanm 0:9b334a45a8ff 506 {
bogdanm 0:9b334a45a8ff 507 /* Check the parameters */
bogdanm 0:9b334a45a8ff 508 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
bogdanm 0:9b334a45a8ff 509
bogdanm 0:9b334a45a8ff 510 /* Enable the timer output */
bogdanm 0:9b334a45a8ff 511 (HRTIMx->HRTIM_COMMON).OENR |= OCChannel;
bogdanm 0:9b334a45a8ff 512
bogdanm 0:9b334a45a8ff 513 /* Enable the timer counter */
bogdanm 0:9b334a45a8ff 514 __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
bogdanm 0:9b334a45a8ff 515
bogdanm 0:9b334a45a8ff 516 }
bogdanm 0:9b334a45a8ff 517
bogdanm 0:9b334a45a8ff 518 /**
bogdanm 0:9b334a45a8ff 519 * @brief Stops the output compare signal generation on the designed timer output
bogdanm 0:9b334a45a8ff 520 * @param HRTIMx: pointer to HRTIM peripheral
bogdanm 0:9b334a45a8ff 521 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 522 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 523 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 524 * @param OCChannel: Timer output
bogdanm 0:9b334a45a8ff 525 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 526 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
bogdanm 0:9b334a45a8ff 527 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
bogdanm 0:9b334a45a8ff 528 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
bogdanm 0:9b334a45a8ff 529 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
bogdanm 0:9b334a45a8ff 530 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
bogdanm 0:9b334a45a8ff 531 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
bogdanm 0:9b334a45a8ff 532 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
bogdanm 0:9b334a45a8ff 533 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
bogdanm 0:9b334a45a8ff 534 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
bogdanm 0:9b334a45a8ff 535 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
bogdanm 0:9b334a45a8ff 536 * @retval None
bogdanm 0:9b334a45a8ff 537 */
bogdanm 0:9b334a45a8ff 538 void HRTIM_SimpleOCStop(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 539 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 540 uint32_t OCChannel)
bogdanm 0:9b334a45a8ff 541 {
bogdanm 0:9b334a45a8ff 542 /* Check the parameters */
bogdanm 0:9b334a45a8ff 543 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
bogdanm 0:9b334a45a8ff 544
bogdanm 0:9b334a45a8ff 545 /* Disable the timer output */
bogdanm 0:9b334a45a8ff 546 HRTIMx->HRTIM_COMMON.DISR |= OCChannel;
bogdanm 0:9b334a45a8ff 547
bogdanm 0:9b334a45a8ff 548 /* Disable the timer counter */
bogdanm 0:9b334a45a8ff 549 __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
bogdanm 0:9b334a45a8ff 550 }
bogdanm 0:9b334a45a8ff 551
bogdanm 0:9b334a45a8ff 552 /**
bogdanm 0:9b334a45a8ff 553 * @brief Starts the PWM output signal generation on the designed timer output
bogdanm 0:9b334a45a8ff 554 * @param HRTIMx: pointer to HRTIM peripheral
bogdanm 0:9b334a45a8ff 555 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 556 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 557 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 558 * @param PWMChannel: Timer output
bogdanm 0:9b334a45a8ff 559 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 560 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
bogdanm 0:9b334a45a8ff 561 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
bogdanm 0:9b334a45a8ff 562 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
bogdanm 0:9b334a45a8ff 563 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
bogdanm 0:9b334a45a8ff 564 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
bogdanm 0:9b334a45a8ff 565 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
bogdanm 0:9b334a45a8ff 566 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
bogdanm 0:9b334a45a8ff 567 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
bogdanm 0:9b334a45a8ff 568 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
bogdanm 0:9b334a45a8ff 569 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
bogdanm 0:9b334a45a8ff 570 * @retval None
bogdanm 0:9b334a45a8ff 571 */
bogdanm 0:9b334a45a8ff 572 void HRTIM_SimplePWMStart(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 573 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 574 uint32_t PWMChannel)
bogdanm 0:9b334a45a8ff 575 {
bogdanm 0:9b334a45a8ff 576 /* Check the parameters */
bogdanm 0:9b334a45a8ff 577 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
bogdanm 0:9b334a45a8ff 578
bogdanm 0:9b334a45a8ff 579 /* Enable the timer output */
bogdanm 0:9b334a45a8ff 580 HRTIMx->HRTIM_COMMON.OENR |= PWMChannel;
bogdanm 0:9b334a45a8ff 581
bogdanm 0:9b334a45a8ff 582 /* Enable the timer counter */
bogdanm 0:9b334a45a8ff 583 __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
bogdanm 0:9b334a45a8ff 584 }
bogdanm 0:9b334a45a8ff 585
bogdanm 0:9b334a45a8ff 586 /**
bogdanm 0:9b334a45a8ff 587 * @brief Stops the PWM output signal generation on the designed timer output
bogdanm 0:9b334a45a8ff 588 * @param HRTIMx: pointer to HRTIM peripheral
bogdanm 0:9b334a45a8ff 589 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 590 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 591 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 592 * @param PWMChannel: Timer output
bogdanm 0:9b334a45a8ff 593 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 594 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
bogdanm 0:9b334a45a8ff 595 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
bogdanm 0:9b334a45a8ff 596 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
bogdanm 0:9b334a45a8ff 597 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
bogdanm 0:9b334a45a8ff 598 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
bogdanm 0:9b334a45a8ff 599 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
bogdanm 0:9b334a45a8ff 600 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
bogdanm 0:9b334a45a8ff 601 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
bogdanm 0:9b334a45a8ff 602 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
bogdanm 0:9b334a45a8ff 603 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
bogdanm 0:9b334a45a8ff 604 * @retval None
bogdanm 0:9b334a45a8ff 605 */
bogdanm 0:9b334a45a8ff 606 void HRTIM_SimplePWMStop(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 607 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 608 uint32_t PWMChannel)
bogdanm 0:9b334a45a8ff 609 {
bogdanm 0:9b334a45a8ff 610 /* Check the parameters */
bogdanm 0:9b334a45a8ff 611 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
bogdanm 0:9b334a45a8ff 612
bogdanm 0:9b334a45a8ff 613 /* Disable the timer output */
bogdanm 0:9b334a45a8ff 614 HRTIMx->HRTIM_COMMON.DISR |= PWMChannel;
bogdanm 0:9b334a45a8ff 615
bogdanm 0:9b334a45a8ff 616 /* Disable the timer counter */
bogdanm 0:9b334a45a8ff 617 __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
bogdanm 0:9b334a45a8ff 618 }
bogdanm 0:9b334a45a8ff 619
bogdanm 0:9b334a45a8ff 620 /**
bogdanm 0:9b334a45a8ff 621 * @brief Enables a basic capture on the designed capture unit
bogdanm 0:9b334a45a8ff 622 * @param HRTIMx: pointer to HRTIM peripheral
bogdanm 0:9b334a45a8ff 623 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 624 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 625 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 626 * @param CaptureChannel: Timer output
bogdanm 0:9b334a45a8ff 627 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 628 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
bogdanm 0:9b334a45a8ff 629 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
bogdanm 0:9b334a45a8ff 630 * @retval None
bogdanm 0:9b334a45a8ff 631 * @note The external event triggering the capture is available for all timing
bogdanm 0:9b334a45a8ff 632 * units. It can be used directly and is active as soon as the timing
bogdanm 0:9b334a45a8ff 633 * unit counter is enabled.
bogdanm 0:9b334a45a8ff 634 */
bogdanm 0:9b334a45a8ff 635 void HRTIM_SimpleCaptureStart(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 636 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 637 uint32_t CaptureChannel)
bogdanm 0:9b334a45a8ff 638 {
bogdanm 0:9b334a45a8ff 639 /* Enable the timer counter */
bogdanm 0:9b334a45a8ff 640 __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
bogdanm 0:9b334a45a8ff 641
bogdanm 0:9b334a45a8ff 642 }
bogdanm 0:9b334a45a8ff 643
bogdanm 0:9b334a45a8ff 644 /**
bogdanm 0:9b334a45a8ff 645 * @brief Disables a basic capture on the designed capture unit
bogdanm 0:9b334a45a8ff 646 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 647 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 648 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 649 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 650 * @param CaptureChannel: Timer output
bogdanm 0:9b334a45a8ff 651 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 652 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
bogdanm 0:9b334a45a8ff 653 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
bogdanm 0:9b334a45a8ff 654 * @retval None
bogdanm 0:9b334a45a8ff 655 */
bogdanm 0:9b334a45a8ff 656 void HRTIM_SimpleCaptureStop(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 657 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 658 uint32_t CaptureChannel)
bogdanm 0:9b334a45a8ff 659 {
bogdanm 0:9b334a45a8ff 660 /* Check the parameters */
bogdanm 0:9b334a45a8ff 661 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
bogdanm 0:9b334a45a8ff 662 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
bogdanm 0:9b334a45a8ff 663
bogdanm 0:9b334a45a8ff 664 /* Set the capture unit trigger */
bogdanm 0:9b334a45a8ff 665 switch (CaptureChannel)
bogdanm 0:9b334a45a8ff 666 {
bogdanm 0:9b334a45a8ff 667 case HRTIM_CAPTUREUNIT_1:
bogdanm 0:9b334a45a8ff 668 {
bogdanm 0:9b334a45a8ff 669 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
bogdanm 0:9b334a45a8ff 670 }
bogdanm 0:9b334a45a8ff 671 break;
bogdanm 0:9b334a45a8ff 672 case HRTIM_CAPTUREUNIT_2:
bogdanm 0:9b334a45a8ff 673 {
bogdanm 0:9b334a45a8ff 674 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
bogdanm 0:9b334a45a8ff 675 }
bogdanm 0:9b334a45a8ff 676 break;
bogdanm 0:9b334a45a8ff 677 default:
bogdanm 0:9b334a45a8ff 678 break;
bogdanm 0:9b334a45a8ff 679 }
bogdanm 0:9b334a45a8ff 680
bogdanm 0:9b334a45a8ff 681 /* Disable the timer counter */
bogdanm 0:9b334a45a8ff 682 if ((HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
bogdanm 0:9b334a45a8ff 683 (HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
bogdanm 0:9b334a45a8ff 684 {
bogdanm 0:9b334a45a8ff 685 __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
bogdanm 0:9b334a45a8ff 686 }
bogdanm 0:9b334a45a8ff 687
bogdanm 0:9b334a45a8ff 688 }
bogdanm 0:9b334a45a8ff 689
bogdanm 0:9b334a45a8ff 690 /**
bogdanm 0:9b334a45a8ff 691 * @brief Enables the basic one pulse signal generation on the designed output
bogdanm 0:9b334a45a8ff 692 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 693 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 694 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 695 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 696 * @param OnePulseChannel: Timer output
bogdanm 0:9b334a45a8ff 697 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 698 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
bogdanm 0:9b334a45a8ff 699 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
bogdanm 0:9b334a45a8ff 700 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
bogdanm 0:9b334a45a8ff 701 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
bogdanm 0:9b334a45a8ff 702 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
bogdanm 0:9b334a45a8ff 703 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
bogdanm 0:9b334a45a8ff 704 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
bogdanm 0:9b334a45a8ff 705 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
bogdanm 0:9b334a45a8ff 706 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
bogdanm 0:9b334a45a8ff 707 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
bogdanm 0:9b334a45a8ff 708 * @retval None
bogdanm 0:9b334a45a8ff 709 */
bogdanm 0:9b334a45a8ff 710 void HRTIM_SimpleOnePulseStart(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 711 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 712 uint32_t OnePulseChannel)
bogdanm 0:9b334a45a8ff 713 {
bogdanm 0:9b334a45a8ff 714 /* Check the parameters */
bogdanm 0:9b334a45a8ff 715 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
bogdanm 0:9b334a45a8ff 716
bogdanm 0:9b334a45a8ff 717 /* Enable the timer output */
bogdanm 0:9b334a45a8ff 718 HRTIMx->HRTIM_COMMON.OENR |= OnePulseChannel;
bogdanm 0:9b334a45a8ff 719
bogdanm 0:9b334a45a8ff 720 /* Enable the timer counter */
bogdanm 0:9b334a45a8ff 721 __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
bogdanm 0:9b334a45a8ff 722 }
bogdanm 0:9b334a45a8ff 723
bogdanm 0:9b334a45a8ff 724 /**
bogdanm 0:9b334a45a8ff 725 * @brief Disables the basic one pulse signal generation on the designed output
bogdanm 0:9b334a45a8ff 726 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 727 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 728 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 729 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 730 * @param OnePulseChannel: Timer output
bogdanm 0:9b334a45a8ff 731 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 732 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
bogdanm 0:9b334a45a8ff 733 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
bogdanm 0:9b334a45a8ff 734 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
bogdanm 0:9b334a45a8ff 735 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
bogdanm 0:9b334a45a8ff 736 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
bogdanm 0:9b334a45a8ff 737 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
bogdanm 0:9b334a45a8ff 738 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
bogdanm 0:9b334a45a8ff 739 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
bogdanm 0:9b334a45a8ff 740 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
bogdanm 0:9b334a45a8ff 741 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
bogdanm 0:9b334a45a8ff 742 * @retval None
bogdanm 0:9b334a45a8ff 743 */
bogdanm 0:9b334a45a8ff 744 void HRTIM_SimpleOnePulseStop(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 745 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 746 uint32_t OnePulseChannel)
bogdanm 0:9b334a45a8ff 747 {
bogdanm 0:9b334a45a8ff 748 /* Check the parameters */
bogdanm 0:9b334a45a8ff 749 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
bogdanm 0:9b334a45a8ff 750
bogdanm 0:9b334a45a8ff 751 /* Disable the timer output */
bogdanm 0:9b334a45a8ff 752 HRTIMx->HRTIM_COMMON.DISR |= OnePulseChannel;
bogdanm 0:9b334a45a8ff 753
bogdanm 0:9b334a45a8ff 754 /* Disable the timer counter */
bogdanm 0:9b334a45a8ff 755 __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
bogdanm 0:9b334a45a8ff 756 }
bogdanm 0:9b334a45a8ff 757
bogdanm 0:9b334a45a8ff 758 /**
bogdanm 0:9b334a45a8ff 759 * @brief Starts the counter of the designated timer(s) operating in waveform mode
bogdanm 0:9b334a45a8ff 760 * Timers can be combined (ORed) to allow for simultaneous counter start
bogdanm 0:9b334a45a8ff 761 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 762 * @param TimersToStart: Timer counter(s) to start
bogdanm 0:9b334a45a8ff 763 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 764 * @arg HRTIM_TIMERID_MASTER
bogdanm 0:9b334a45a8ff 765 * @arg HRTIM_TIMERID_TIMER_A
bogdanm 0:9b334a45a8ff 766 * @arg HRTIM_TIMERID_TIMER_B
bogdanm 0:9b334a45a8ff 767 * @arg HRTIM_TIMERID_TIMER_C
bogdanm 0:9b334a45a8ff 768 * @arg HRTIM_TIMERID_TIMER_D
bogdanm 0:9b334a45a8ff 769 * @arg HRTIM_TIMERID_TIMER_E
bogdanm 0:9b334a45a8ff 770 * @retval None
bogdanm 0:9b334a45a8ff 771 */
bogdanm 0:9b334a45a8ff 772 void HRTIM_WaveformCounterStart(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 773 uint32_t TimersToStart)
bogdanm 0:9b334a45a8ff 774 {
bogdanm 0:9b334a45a8ff 775 /* Enable timer(s) counter */
bogdanm 0:9b334a45a8ff 776 HRTIMx->HRTIM_MASTER.MCR |= TimersToStart;
bogdanm 0:9b334a45a8ff 777 }
bogdanm 0:9b334a45a8ff 778
bogdanm 0:9b334a45a8ff 779 /**
bogdanm 0:9b334a45a8ff 780 * @brief Stops the counter of the designated timer(s) operating in waveform mode
bogdanm 0:9b334a45a8ff 781 * Timers can be combined (ORed) to allow for simultaneous counter stop
bogdanm 0:9b334a45a8ff 782 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 783 * @param TimersToStop: Timer counter(s) to stop
bogdanm 0:9b334a45a8ff 784 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 785 * @arg HRTIM_TIMER_MASTER
bogdanm 0:9b334a45a8ff 786 * @arg HRTIM_TIMER_A
bogdanm 0:9b334a45a8ff 787 * @arg HRTIM_TIMER_B
bogdanm 0:9b334a45a8ff 788 * @arg HRTIM_TIMER_C
bogdanm 0:9b334a45a8ff 789 * @arg HRTIM_TIMER_D
bogdanm 0:9b334a45a8ff 790 * @arg HRTIM_TIMER_E
bogdanm 0:9b334a45a8ff 791 * @retval None
bogdanm 0:9b334a45a8ff 792 */
bogdanm 0:9b334a45a8ff 793 void HRTIM_WaveformCounterStop(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 794 uint32_t TimersToStop)
bogdanm 0:9b334a45a8ff 795 {
bogdanm 0:9b334a45a8ff 796 /* Disable timer(s) counter */
bogdanm 0:9b334a45a8ff 797 HRTIMx->HRTIM_MASTER.MCR &= ~TimersToStop;
bogdanm 0:9b334a45a8ff 798 }
bogdanm 0:9b334a45a8ff 799
bogdanm 0:9b334a45a8ff 800 /**
bogdanm 0:9b334a45a8ff 801 * @brief Enables the generation of the waveform signal on the designated output(s)
bogdanm 0:9b334a45a8ff 802 * Outputs can be combined (ORed) to allow for simultaneous output enabling
bogdanm 0:9b334a45a8ff 803 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 804 * @param OutputsToStart: Timer output(s) to enable
bogdanm 0:9b334a45a8ff 805 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 806 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
bogdanm 0:9b334a45a8ff 807 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
bogdanm 0:9b334a45a8ff 808 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
bogdanm 0:9b334a45a8ff 809 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
bogdanm 0:9b334a45a8ff 810 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
bogdanm 0:9b334a45a8ff 811 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
bogdanm 0:9b334a45a8ff 812 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
bogdanm 0:9b334a45a8ff 813 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
bogdanm 0:9b334a45a8ff 814 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
bogdanm 0:9b334a45a8ff 815 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
bogdanm 0:9b334a45a8ff 816 * @retval None
bogdanm 0:9b334a45a8ff 817 */
bogdanm 0:9b334a45a8ff 818 void HRTIM_WaveformOutputStart(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 819 uint32_t OutputsToStart)
bogdanm 0:9b334a45a8ff 820 {
bogdanm 0:9b334a45a8ff 821 /* Enable the HRTIM outputs */
bogdanm 0:9b334a45a8ff 822 HRTIMx->HRTIM_COMMON.OENR = OutputsToStart;
bogdanm 0:9b334a45a8ff 823 }
bogdanm 0:9b334a45a8ff 824
bogdanm 0:9b334a45a8ff 825 /**
bogdanm 0:9b334a45a8ff 826 * @brief Disables the generation of the waveform signal on the designated output(s)
bogdanm 0:9b334a45a8ff 827 * Outputs can be combined (ORed) to allow for simultaneous output disabling
bogdanm 0:9b334a45a8ff 828 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 829 * @param OutputsToStop: Timer output(s) to disable
bogdanm 0:9b334a45a8ff 830 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 831 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
bogdanm 0:9b334a45a8ff 832 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
bogdanm 0:9b334a45a8ff 833 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
bogdanm 0:9b334a45a8ff 834 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
bogdanm 0:9b334a45a8ff 835 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
bogdanm 0:9b334a45a8ff 836 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
bogdanm 0:9b334a45a8ff 837 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
bogdanm 0:9b334a45a8ff 838 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
bogdanm 0:9b334a45a8ff 839 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
bogdanm 0:9b334a45a8ff 840 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
bogdanm 0:9b334a45a8ff 841 * @retval None
bogdanm 0:9b334a45a8ff 842 */
bogdanm 0:9b334a45a8ff 843 void HRTIM_WaveformOutputStop(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 844 uint32_t OutputsToStop)
bogdanm 0:9b334a45a8ff 845 {
bogdanm 0:9b334a45a8ff 846 /* Disable the HRTIM outputs */
bogdanm 0:9b334a45a8ff 847 HRTIMx->HRTIM_COMMON.DISR = OutputsToStop;
bogdanm 0:9b334a45a8ff 848 }
bogdanm 0:9b334a45a8ff 849
bogdanm 0:9b334a45a8ff 850 /**
bogdanm 0:9b334a45a8ff 851 * @brief Enables or disables the Master and slaves interrupt request
bogdanm 0:9b334a45a8ff 852 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 853 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 854 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 855 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 856 * @param HRTIM_IT: specifies the HRTIM interrupts sources to be enabled or disabled.
bogdanm 0:9b334a45a8ff 857 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 858 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt source
bogdanm 0:9b334a45a8ff 859 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt source
bogdanm 0:9b334a45a8ff 860 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt Interrupt source
bogdanm 0:9b334a45a8ff 861 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 Interrupt source
bogdanm 0:9b334a45a8ff 862 * @arg HRTIM_MASTER_IT_MREP: Master Repetition Interrupt source
bogdanm 0:9b334a45a8ff 863 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input Interrupt source
bogdanm 0:9b334a45a8ff 864 * @arg HRTIM_MASTER_IT_MUPD: Master update Interrupt source
bogdanm 0:9b334a45a8ff 865 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 Interrupt source
bogdanm 0:9b334a45a8ff 866 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 Interrupt source
bogdanm 0:9b334a45a8ff 867 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 Interrupt source
bogdanm 0:9b334a45a8ff 868 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 Interrupt source
bogdanm 0:9b334a45a8ff 869 * @arg HRTIM_TIM_IT_REP: Timer repetition Interrupt source
bogdanm 0:9b334a45a8ff 870 * @arg HRTIM_TIM_IT_UPD: Timer update Interrupt source
bogdanm 0:9b334a45a8ff 871 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 Interrupt source
bogdanm 0:9b334a45a8ff 872 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 Interrupt source
bogdanm 0:9b334a45a8ff 873 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set Interrupt source
bogdanm 0:9b334a45a8ff 874 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset Interrupt source
bogdanm 0:9b334a45a8ff 875 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set Interrupt source
bogdanm 0:9b334a45a8ff 876 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset Interrupt source
bogdanm 0:9b334a45a8ff 877 * @arg HRTIM_TIM_IT_RST: Timer reset Interrupt source
bogdanm 0:9b334a45a8ff 878 * @arg HRTIM_TIM_IT_DLYPRT1: Timer delay protection Interrupt source
bogdanm 0:9b334a45a8ff 879 * @param NewState: new state of the TIM interrupts.
bogdanm 0:9b334a45a8ff 880 * This parameter can be: ENABLE or DISABLE.
bogdanm 0:9b334a45a8ff 881 * @retval None
bogdanm 0:9b334a45a8ff 882 */
bogdanm 0:9b334a45a8ff 883 void HRTIM_ITConfig(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT, FunctionalState NewState)
bogdanm 0:9b334a45a8ff 884 {
bogdanm 0:9b334a45a8ff 885 if(TimerIdx != HRTIM_TIMERINDEX_MASTER)
bogdanm 0:9b334a45a8ff 886 {
bogdanm 0:9b334a45a8ff 887 if(NewState != DISABLE)
bogdanm 0:9b334a45a8ff 888 {
bogdanm 0:9b334a45a8ff 889 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER |= HRTIM_IT;
bogdanm 0:9b334a45a8ff 890 }
bogdanm 0:9b334a45a8ff 891 else
bogdanm 0:9b334a45a8ff 892 {
bogdanm 0:9b334a45a8ff 893 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER &= ~HRTIM_IT;
bogdanm 0:9b334a45a8ff 894 }
bogdanm 0:9b334a45a8ff 895 }
bogdanm 0:9b334a45a8ff 896 else
bogdanm 0:9b334a45a8ff 897 {
bogdanm 0:9b334a45a8ff 898 if(NewState != DISABLE)
bogdanm 0:9b334a45a8ff 899 {
bogdanm 0:9b334a45a8ff 900 HRTIMx->HRTIM_MASTER.MDIER |= HRTIM_IT;
bogdanm 0:9b334a45a8ff 901 }
bogdanm 0:9b334a45a8ff 902 else
bogdanm 0:9b334a45a8ff 903 {
bogdanm 0:9b334a45a8ff 904 HRTIMx->HRTIM_MASTER.MDIER &= ~HRTIM_IT;
bogdanm 0:9b334a45a8ff 905 }
bogdanm 0:9b334a45a8ff 906 }
bogdanm 0:9b334a45a8ff 907 }
bogdanm 0:9b334a45a8ff 908
bogdanm 0:9b334a45a8ff 909 /**
bogdanm 0:9b334a45a8ff 910 * @brief Enables or disables the common interrupt request
bogdanm 0:9b334a45a8ff 911 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 912 * @param HRTIM_IT: specifies the HRTIM interrupts sources to be enabled or disabled.
bogdanm 0:9b334a45a8ff 913 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 914 * @arg HRTIM_IT_FLT1: Fault 1 interrupt source
bogdanm 0:9b334a45a8ff 915 * @arg HRTIM_IT_FLT2: Fault 2 interrupt source
bogdanm 0:9b334a45a8ff 916 * @arg HRTIM_IT_FLT3: Fault 3 interrupt Interrupt source
bogdanm 0:9b334a45a8ff 917 * @arg HRTIM_IT_FLT4: Fault 4 Interrupt source
bogdanm 0:9b334a45a8ff 918 * @arg HRTIM_IT_FLT5: Fault 5 Interrupt source
bogdanm 0:9b334a45a8ff 919 * @arg HRTIM_IT_SYSFLT: System Fault Interrupt source
bogdanm 0:9b334a45a8ff 920 * @arg HRTIM_IT_DLLRDY: DLL ready Interrupt source
bogdanm 0:9b334a45a8ff 921 * @arg HRTIM_IT_BMPER: Burst mode period Interrupt source
bogdanm 0:9b334a45a8ff 922 * @param NewState: new state of the TIM interrupts.
bogdanm 0:9b334a45a8ff 923 * This parameter can be: ENABLE or DISABLE.
bogdanm 0:9b334a45a8ff 924 * @retval None
bogdanm 0:9b334a45a8ff 925 */
bogdanm 0:9b334a45a8ff 926 void HRTIM_ITCommonConfig(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT, FunctionalState NewState)
bogdanm 0:9b334a45a8ff 927 {
bogdanm 0:9b334a45a8ff 928 if(NewState != DISABLE)
bogdanm 0:9b334a45a8ff 929 {
bogdanm 0:9b334a45a8ff 930 HRTIMx->HRTIM_COMMON.IER |= HRTIM_CommonIT;
bogdanm 0:9b334a45a8ff 931 }
bogdanm 0:9b334a45a8ff 932 else
bogdanm 0:9b334a45a8ff 933 {
bogdanm 0:9b334a45a8ff 934 HRTIMx->HRTIM_COMMON.IER &= ~HRTIM_CommonIT;
bogdanm 0:9b334a45a8ff 935 }
bogdanm 0:9b334a45a8ff 936 }
bogdanm 0:9b334a45a8ff 937
bogdanm 0:9b334a45a8ff 938 /**
bogdanm 0:9b334a45a8ff 939 * @brief Clears the Master and slaves interrupt flags
bogdanm 0:9b334a45a8ff 940 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 941 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 942 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 943 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 944 * @param HRTIM_FLAG: specifies the HRTIM flags sources to be cleared.
bogdanm 0:9b334a45a8ff 945 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 946 * @arg HRTIM_MASTER_FLAG_MCMP1: Master compare 1 interrupt flag
bogdanm 0:9b334a45a8ff 947 * @arg HRTIM_MASTER_FLAG_MCMP2: Master compare 2 interrupt flag
bogdanm 0:9b334a45a8ff 948 * @arg HRTIM_MASTER_FLAG_MCMP3: Master compare 3 interrupt Interrupt flag
bogdanm 0:9b334a45a8ff 949 * @arg HRTIM_MASTER_FLAG_MCMP4: Master compare 4 Interrupt flag
bogdanm 0:9b334a45a8ff 950 * @arg HRTIM_MASTER_FLAG_MREP: Master Repetition Interrupt flag
bogdanm 0:9b334a45a8ff 951 * @arg HRTIM_MASTER_FLAG_SYNC: Synchronization input Interrupt flag
bogdanm 0:9b334a45a8ff 952 * @arg HRTIM_MASTER_FLAG_MUPD: Master update Interrupt flag
bogdanm 0:9b334a45a8ff 953 * @arg HRTIM_TIM_FLAG_CMP1: Timer compare 1 Interrupt flag
bogdanm 0:9b334a45a8ff 954 * @arg HRTIM_TIM_FLAG_CMP2: Timer compare 2 Interrupt flag
bogdanm 0:9b334a45a8ff 955 * @arg HRTIM_TIM_FLAG_CMP3: Timer compare 3 Interrupt flag
bogdanm 0:9b334a45a8ff 956 * @arg HRTIM_TIM_FLAG_CMP4: Timer compare 4 Interrupt flag
bogdanm 0:9b334a45a8ff 957 * @arg HRTIM_TIM_FLAG_REP: Timer repetition Interrupt flag
bogdanm 0:9b334a45a8ff 958 * @arg HRTIM_TIM_FLAG_UPD: Timer update Interrupt flag
bogdanm 0:9b334a45a8ff 959 * @arg HRTIM_TIM_FLAG_CPT1: Timer capture 1 Interrupt flag
bogdanm 0:9b334a45a8ff 960 * @arg HRTIM_TIM_FLAG_CPT2: Timer capture 2 Interrupt flag
bogdanm 0:9b334a45a8ff 961 * @arg HRTIM_TIM_FLAG_SET1: Timer output 1 set Interrupt flag
bogdanm 0:9b334a45a8ff 962 * @arg HRTIM_TIM_FLAG_RST1: Timer output 1 reset Interrupt flag
bogdanm 0:9b334a45a8ff 963 * @arg HRTIM_TIM_FLAG_SET2: Timer output 2 set Interrupt flag
bogdanm 0:9b334a45a8ff 964 * @arg HRTIM_TIM_FLAG_RST2: Timer output 2 reset Interrupt flag
bogdanm 0:9b334a45a8ff 965 * @arg HRTIM_TIM_FLAG_RST: Timer reset Interrupt flag
bogdanm 0:9b334a45a8ff 966 * @arg HRTIM_TIM_FLAG_DLYPRT1: Timer delay protection Interrupt flag
bogdanm 0:9b334a45a8ff 967 * @retval None
bogdanm 0:9b334a45a8ff 968 */
bogdanm 0:9b334a45a8ff 969 void HRTIM_ClearFlag(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG)
bogdanm 0:9b334a45a8ff 970 {
bogdanm 0:9b334a45a8ff 971 if(TimerIdx != HRTIM_TIMERINDEX_MASTER)
bogdanm 0:9b334a45a8ff 972 {
bogdanm 0:9b334a45a8ff 973 HRTIMx->HRTIM_MASTER.MICR |= HRTIM_FLAG;
bogdanm 0:9b334a45a8ff 974 }
bogdanm 0:9b334a45a8ff 975 else
bogdanm 0:9b334a45a8ff 976 {
bogdanm 0:9b334a45a8ff 977 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxICR |= HRTIM_FLAG;
bogdanm 0:9b334a45a8ff 978 }
bogdanm 0:9b334a45a8ff 979 }
bogdanm 0:9b334a45a8ff 980
bogdanm 0:9b334a45a8ff 981 /**
bogdanm 0:9b334a45a8ff 982 * @brief Clears the common interrupt flags
bogdanm 0:9b334a45a8ff 983 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 984 * @param HRTIM_FLAG: specifies the HRTIM flags to be cleared.
bogdanm 0:9b334a45a8ff 985 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 986 * @arg HRTIM_FLAG_FLT1: Fault 1 interrupt flag
bogdanm 0:9b334a45a8ff 987 * @arg HRTIM_FLAG_FLT2: Fault 2 interrupt flag
bogdanm 0:9b334a45a8ff 988 * @arg HRTIM_FLAG_FLT3: Fault 3 interrupt Interrupt flag
bogdanm 0:9b334a45a8ff 989 * @arg HRTIM_FLAG_FLT4: Fault 4 Interrupt flag
bogdanm 0:9b334a45a8ff 990 * @arg HRTIM_FLAG_FLT5: Fault 5 Interrupt flag
bogdanm 0:9b334a45a8ff 991 * @arg HRTIM_FLAG_SYSFLT: System Fault Interrupt flag
bogdanm 0:9b334a45a8ff 992 * @arg HRTIM_FLAG_DLLRDY: DLL ready Interrupt flag
bogdanm 0:9b334a45a8ff 993 * @arg HRTIM_FLAG_BMPER: Burst mode period Interrupt flag
bogdanm 0:9b334a45a8ff 994 * @retval None
bogdanm 0:9b334a45a8ff 995 */
bogdanm 0:9b334a45a8ff 996 void HRTIM_ClearCommonFlag(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG)
bogdanm 0:9b334a45a8ff 997 {
bogdanm 0:9b334a45a8ff 998 HRTIMx->HRTIM_COMMON.ICR |= HRTIM_CommonFLAG;
bogdanm 0:9b334a45a8ff 999 }
bogdanm 0:9b334a45a8ff 1000
bogdanm 0:9b334a45a8ff 1001 /**
bogdanm 0:9b334a45a8ff 1002 * @brief Clears the Master and slaves interrupt request pending bits
bogdanm 0:9b334a45a8ff 1003 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 1004 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 1005 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1006 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 1007 * @param HRTIM_IT: specifies the HRTIM interrupts sources to be enabled or disabled.
bogdanm 0:9b334a45a8ff 1008 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 1009 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt source
bogdanm 0:9b334a45a8ff 1010 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt source
bogdanm 0:9b334a45a8ff 1011 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt Interrupt source
bogdanm 0:9b334a45a8ff 1012 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 Interrupt source
bogdanm 0:9b334a45a8ff 1013 * @arg HRTIM_MASTER_IT_MREP: Master Repetition Interrupt source
bogdanm 0:9b334a45a8ff 1014 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input Interrupt source
bogdanm 0:9b334a45a8ff 1015 * @arg HRTIM_MASTER_IT_MUPD: Master update Interrupt source
bogdanm 0:9b334a45a8ff 1016 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 Interrupt source
bogdanm 0:9b334a45a8ff 1017 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 Interrupt source
bogdanm 0:9b334a45a8ff 1018 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 Interrupt source
bogdanm 0:9b334a45a8ff 1019 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 Interrupt source
bogdanm 0:9b334a45a8ff 1020 * @arg HRTIM_TIM_IT_REP: Timer repetition Interrupt source
bogdanm 0:9b334a45a8ff 1021 * @arg HRTIM_TIM_IT_UPD: Timer update Interrupt source
bogdanm 0:9b334a45a8ff 1022 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 Interrupt source
bogdanm 0:9b334a45a8ff 1023 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 Interrupt source
bogdanm 0:9b334a45a8ff 1024 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set Interrupt source
bogdanm 0:9b334a45a8ff 1025 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset Interrupt source
bogdanm 0:9b334a45a8ff 1026 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set Interrupt source
bogdanm 0:9b334a45a8ff 1027 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset Interrupt source
bogdanm 0:9b334a45a8ff 1028 * @arg HRTIM_TIM_IT_RST: Timer reset Interrupt source
bogdanm 0:9b334a45a8ff 1029 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection Interrupt source
bogdanm 0:9b334a45a8ff 1030 * @retval None
bogdanm 0:9b334a45a8ff 1031 */
bogdanm 0:9b334a45a8ff 1032 void HRTIM_ClearITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT)
bogdanm 0:9b334a45a8ff 1033 {
bogdanm 0:9b334a45a8ff 1034 if(TimerIdx != HRTIM_TIMERINDEX_MASTER)
bogdanm 0:9b334a45a8ff 1035 {
bogdanm 0:9b334a45a8ff 1036 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxICR |= HRTIM_IT;
bogdanm 0:9b334a45a8ff 1037 }
bogdanm 0:9b334a45a8ff 1038 else
bogdanm 0:9b334a45a8ff 1039 {
bogdanm 0:9b334a45a8ff 1040 HRTIMx->HRTIM_MASTER.MICR |= HRTIM_IT;
bogdanm 0:9b334a45a8ff 1041 }
bogdanm 0:9b334a45a8ff 1042 }
bogdanm 0:9b334a45a8ff 1043
bogdanm 0:9b334a45a8ff 1044 /**
bogdanm 0:9b334a45a8ff 1045 * @brief Clears the common interrupt pending bits
bogdanm 0:9b334a45a8ff 1046 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 1047 * @param HRTIM_IT: specifies the HRTIM interrupts sources to be cleared.
bogdanm 0:9b334a45a8ff 1048 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 1049 * @arg HRTIM_IT_FLT1: Fault 1 interrupt source
bogdanm 0:9b334a45a8ff 1050 * @arg HRTIM_IT_FLT2: Fault 2 interrupt source
bogdanm 0:9b334a45a8ff 1051 * @arg HRTIM_IT_FLT3: Fault 3 interrupt Interrupt source
bogdanm 0:9b334a45a8ff 1052 * @arg HRTIM_IT_FLT4: Fault 4 Interrupt source
bogdanm 0:9b334a45a8ff 1053 * @arg HRTIM_IT_FLT5: Fault 5 Interrupt source
bogdanm 0:9b334a45a8ff 1054 * @arg HRTIM_IT_SYSFLT: System Fault Interrupt source
bogdanm 0:9b334a45a8ff 1055 * @arg HRTIM_IT_DLLRDY: DLL ready Interrupt source
bogdanm 0:9b334a45a8ff 1056 * @arg HRTIM_IT_BMPER: Burst mode period Interrupt source
bogdanm 0:9b334a45a8ff 1057 * @retval None
bogdanm 0:9b334a45a8ff 1058 */
bogdanm 0:9b334a45a8ff 1059 void HRTIM_ClearCommonITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT)
bogdanm 0:9b334a45a8ff 1060 {
bogdanm 0:9b334a45a8ff 1061 HRTIMx->HRTIM_COMMON.ICR |= HRTIM_CommonIT;
bogdanm 0:9b334a45a8ff 1062 }
bogdanm 0:9b334a45a8ff 1063
bogdanm 0:9b334a45a8ff 1064
bogdanm 0:9b334a45a8ff 1065 /**
bogdanm 0:9b334a45a8ff 1066 * @brief Checks whether the specified HRTIM flag is set or not.
bogdanm 0:9b334a45a8ff 1067 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 1068 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 1069 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1070 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 1071 * @param HRTIM_FLAG: specifies the HRTIM flags to check.
bogdanm 0:9b334a45a8ff 1072 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 1073 * @arg HRTIM_MASTER_FLAG_MCMP1: Master compare 1 interrupt flag
bogdanm 0:9b334a45a8ff 1074 * @arg HRTIM_MASTER_FLAG_MCMP2: Master compare 2 interrupt flag
bogdanm 0:9b334a45a8ff 1075 * @arg HRTIM_MASTER_FLAG_MCMP3: Master compare 3 interrupt Interrupt flag
bogdanm 0:9b334a45a8ff 1076 * @arg HRTIM_MASTER_FLAG_MCMP4: Master compare 4 Interrupt flag
bogdanm 0:9b334a45a8ff 1077 * @arg HRTIM_MASTER_FLAG_MREP: Master Repetition Interrupt flag
bogdanm 0:9b334a45a8ff 1078 * @arg HRTIM_MASTER_FLAG_SYNC: Synchronization input Interrupt flag
bogdanm 0:9b334a45a8ff 1079 * @arg HRTIM_MASTER_FLAG_MUPD: Master update Interrupt flag
bogdanm 0:9b334a45a8ff 1080 * @arg HRTIM_TIM_FLAG_CMP1: Timer compare 1 Interrupt flag
bogdanm 0:9b334a45a8ff 1081 * @arg HRTIM_TIM_FLAG_CMP2: Timer compare 2 Interrupt flag
bogdanm 0:9b334a45a8ff 1082 * @arg HRTIM_TIM_FLAG_CMP3: Timer compare 3 Interrupt flag
bogdanm 0:9b334a45a8ff 1083 * @arg HRTIM_TIM_FLAG_CMP4: Timer compare 4 Interrupt flag
bogdanm 0:9b334a45a8ff 1084 * @arg HRTIM_TIM_FLAG_REP: Timer repetition Interrupt flag
bogdanm 0:9b334a45a8ff 1085 * @arg HRTIM_TIM_FLAG_UPD: Timer update Interrupt flag
bogdanm 0:9b334a45a8ff 1086 * @arg HRTIM_TIM_FLAG_CPT1: Timer capture 1 Interrupt flag
bogdanm 0:9b334a45a8ff 1087 * @arg HRTIM_TIM_FLAG_CPT2: Timer capture 2 Interrupt flag
bogdanm 0:9b334a45a8ff 1088 * @arg HRTIM_TIM_FLAG_SET1: Timer output 1 set Interrupt flag
bogdanm 0:9b334a45a8ff 1089 * @arg HRTIM_TIM_FLAG_RST1: Timer output 1 reset Interrupt flag
bogdanm 0:9b334a45a8ff 1090 * @arg HRTIM_TIM_FLAG_SET2: Timer output 2 set Interrupt flag
bogdanm 0:9b334a45a8ff 1091 * @arg HRTIM_TIM_FLAG_RST2: Timer output 2 reset Interrupt flag
bogdanm 0:9b334a45a8ff 1092 * @arg HRTIM_TIM_FLAG_RST: Timer reset Interrupt flag
bogdanm 0:9b334a45a8ff 1093 * @arg HRTIM_TIM_FLAG_DLYPRT: Timer delay protection Interrupt flag
bogdanm 0:9b334a45a8ff 1094 * @retval The new state of HRTIM_FLAG (SET or RESET).
bogdanm 0:9b334a45a8ff 1095 */
bogdanm 0:9b334a45a8ff 1096 FlagStatus HRTIM_GetFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG)
bogdanm 0:9b334a45a8ff 1097 {
bogdanm 0:9b334a45a8ff 1098 FlagStatus bitstatus = RESET;
bogdanm 0:9b334a45a8ff 1099
bogdanm 0:9b334a45a8ff 1100 if(TimerIdx != HRTIM_TIMERINDEX_MASTER)
bogdanm 0:9b334a45a8ff 1101 {
bogdanm 0:9b334a45a8ff 1102 if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_FLAG) != RESET)
bogdanm 0:9b334a45a8ff 1103 {
bogdanm 0:9b334a45a8ff 1104 bitstatus = SET;
bogdanm 0:9b334a45a8ff 1105 }
bogdanm 0:9b334a45a8ff 1106 else
bogdanm 0:9b334a45a8ff 1107 {
bogdanm 0:9b334a45a8ff 1108 bitstatus = RESET;
bogdanm 0:9b334a45a8ff 1109 }
bogdanm 0:9b334a45a8ff 1110 }
bogdanm 0:9b334a45a8ff 1111 else
bogdanm 0:9b334a45a8ff 1112 {
bogdanm 0:9b334a45a8ff 1113 if ((HRTIMx->HRTIM_MASTER.MISR & HRTIM_FLAG) != RESET)
bogdanm 0:9b334a45a8ff 1114 {
bogdanm 0:9b334a45a8ff 1115 bitstatus = SET;
bogdanm 0:9b334a45a8ff 1116 }
bogdanm 0:9b334a45a8ff 1117 else
bogdanm 0:9b334a45a8ff 1118 {
bogdanm 0:9b334a45a8ff 1119 bitstatus = RESET;
bogdanm 0:9b334a45a8ff 1120 }
bogdanm 0:9b334a45a8ff 1121 }
bogdanm 0:9b334a45a8ff 1122 return bitstatus;
bogdanm 0:9b334a45a8ff 1123 }
bogdanm 0:9b334a45a8ff 1124
bogdanm 0:9b334a45a8ff 1125 /**
bogdanm 0:9b334a45a8ff 1126 * @brief Checks whether the specified HRTIM common flag is set or not.
bogdanm 0:9b334a45a8ff 1127 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 1128 * @param HRTIM_FLAG: specifies the HRTIM flags to check.
bogdanm 0:9b334a45a8ff 1129 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 1130 * @arg HRTIM_FLAG_FLT1: Fault 1 interrupt flag
bogdanm 0:9b334a45a8ff 1131 * @arg HRTIM_FLAG_FLT2: Fault 2 interrupt flag
bogdanm 0:9b334a45a8ff 1132 * @arg HRTIM_FLAG_FLT3: Fault 3 interrupt Interrupt flag
bogdanm 0:9b334a45a8ff 1133 * @arg HRTIM_FLAG_FLT4: Fault 4 Interrupt flag
bogdanm 0:9b334a45a8ff 1134 * @arg HRTIM_FLAG_FLT5: Fault 5 Interrupt flag
bogdanm 0:9b334a45a8ff 1135 * @arg HRTIM_FLAG_SYSFLT: System Fault Interrupt flag
bogdanm 0:9b334a45a8ff 1136 * @arg HRTIM_FLAG_DLLRDY: DLL ready Interrupt flag
bogdanm 0:9b334a45a8ff 1137 * @arg HRTIM_FLAG_BMPER: Burst mode period Interrupt flag
bogdanm 0:9b334a45a8ff 1138 * @retval The new state of HRTIM_FLAG (SET or RESET).
bogdanm 0:9b334a45a8ff 1139 */
bogdanm 0:9b334a45a8ff 1140 FlagStatus HRTIM_GetCommonFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG)
bogdanm 0:9b334a45a8ff 1141 {
bogdanm 0:9b334a45a8ff 1142 FlagStatus bitstatus = RESET;
bogdanm 0:9b334a45a8ff 1143
bogdanm 0:9b334a45a8ff 1144 if((HRTIMx->HRTIM_COMMON.ISR & HRTIM_CommonFLAG) != RESET)
bogdanm 0:9b334a45a8ff 1145 {
bogdanm 0:9b334a45a8ff 1146 bitstatus = SET;
bogdanm 0:9b334a45a8ff 1147 }
bogdanm 0:9b334a45a8ff 1148 else
bogdanm 0:9b334a45a8ff 1149 {
bogdanm 0:9b334a45a8ff 1150 bitstatus = RESET;
bogdanm 0:9b334a45a8ff 1151 }
bogdanm 0:9b334a45a8ff 1152 return bitstatus;
bogdanm 0:9b334a45a8ff 1153 }
bogdanm 0:9b334a45a8ff 1154
bogdanm 0:9b334a45a8ff 1155 /**
bogdanm 0:9b334a45a8ff 1156 * @brief Checks whether the specified HRTIM interrupt has occurred or not.
bogdanm 0:9b334a45a8ff 1157 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 1158 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 1159 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1160 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 1161 * @param HRTIM_IT: specifies the HRTIM flags sources to be cleared.
bogdanm 0:9b334a45a8ff 1162 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 1163 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt
bogdanm 0:9b334a45a8ff 1164 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt
bogdanm 0:9b334a45a8ff 1165 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt Interrupt
bogdanm 0:9b334a45a8ff 1166 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 Interrupt
bogdanm 0:9b334a45a8ff 1167 * @arg HRTIM_MASTER_IT_MREP: Master Repetition Interrupt
bogdanm 0:9b334a45a8ff 1168 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input Interrupt
bogdanm 0:9b334a45a8ff 1169 * @arg HRTIM_MASTER_IT_MUPD: Master update Interrupt
bogdanm 0:9b334a45a8ff 1170 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 Interrupt
bogdanm 0:9b334a45a8ff 1171 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 Interrupt
bogdanm 0:9b334a45a8ff 1172 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 Interrupt
bogdanm 0:9b334a45a8ff 1173 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 Interrupt
bogdanm 0:9b334a45a8ff 1174 * @arg HRTIM_TIM_IT_REP: Timer repetition Interrupt
bogdanm 0:9b334a45a8ff 1175 * @arg HRTIM_TIM_IT_UPD: Timer update Interrupt
bogdanm 0:9b334a45a8ff 1176 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 Interrupt
bogdanm 0:9b334a45a8ff 1177 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 Interrupt
bogdanm 0:9b334a45a8ff 1178 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set Interrupt
bogdanm 0:9b334a45a8ff 1179 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset Interrupt
bogdanm 0:9b334a45a8ff 1180 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set Interrupt
bogdanm 0:9b334a45a8ff 1181 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset Interrupt
bogdanm 0:9b334a45a8ff 1182 * @arg HRTIM_TIM_IT_RST: Timer reset Interrupt
bogdanm 0:9b334a45a8ff 1183 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection Interrupt
bogdanm 0:9b334a45a8ff 1184 * @retval The new state of the HRTIM_IT(SET or RESET).
bogdanm 0:9b334a45a8ff 1185 */
bogdanm 0:9b334a45a8ff 1186 ITStatus HRTIM_GetITStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT)
bogdanm 0:9b334a45a8ff 1187 {
bogdanm 0:9b334a45a8ff 1188 ITStatus bitstatus = RESET;
bogdanm 0:9b334a45a8ff 1189 uint16_t itstatus = 0x0, itenable = 0x0;
bogdanm 0:9b334a45a8ff 1190
bogdanm 0:9b334a45a8ff 1191 if(TimerIdx != HRTIM_TIMERINDEX_MASTER)
bogdanm 0:9b334a45a8ff 1192 {
bogdanm 0:9b334a45a8ff 1193 itstatus = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_IT;
bogdanm 0:9b334a45a8ff 1194
bogdanm 0:9b334a45a8ff 1195 itenable = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER & HRTIM_IT;
bogdanm 0:9b334a45a8ff 1196 if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
bogdanm 0:9b334a45a8ff 1197 {
bogdanm 0:9b334a45a8ff 1198 bitstatus = SET;
bogdanm 0:9b334a45a8ff 1199 }
bogdanm 0:9b334a45a8ff 1200 else
bogdanm 0:9b334a45a8ff 1201 {
bogdanm 0:9b334a45a8ff 1202 bitstatus = RESET;
bogdanm 0:9b334a45a8ff 1203 }
bogdanm 0:9b334a45a8ff 1204 }
bogdanm 0:9b334a45a8ff 1205 else
bogdanm 0:9b334a45a8ff 1206 {
bogdanm 0:9b334a45a8ff 1207 itstatus = HRTIMx->HRTIM_MASTER.MISR & HRTIM_IT;
bogdanm 0:9b334a45a8ff 1208
bogdanm 0:9b334a45a8ff 1209 itenable = HRTIMx->HRTIM_MASTER.MDIER & HRTIM_IT;
bogdanm 0:9b334a45a8ff 1210 if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
bogdanm 0:9b334a45a8ff 1211 {
bogdanm 0:9b334a45a8ff 1212 bitstatus = SET;
bogdanm 0:9b334a45a8ff 1213 }
bogdanm 0:9b334a45a8ff 1214 else
bogdanm 0:9b334a45a8ff 1215 {
bogdanm 0:9b334a45a8ff 1216 bitstatus = RESET;
bogdanm 0:9b334a45a8ff 1217 }
bogdanm 0:9b334a45a8ff 1218 }
bogdanm 0:9b334a45a8ff 1219 return bitstatus;
bogdanm 0:9b334a45a8ff 1220 }
bogdanm 0:9b334a45a8ff 1221
bogdanm 0:9b334a45a8ff 1222 /**
bogdanm 0:9b334a45a8ff 1223 * @brief Checks whether the specified HRTIM common interrupt has occurred or not.
bogdanm 0:9b334a45a8ff 1224 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 1225 * @param HRTIM_IT: specifies the HRTIM interrupt source to check.
bogdanm 0:9b334a45a8ff 1226 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 1227 * @arg HRTIM_IT_FLT1: Fault 1 interrupt
bogdanm 0:9b334a45a8ff 1228 * @arg HRTIM_IT_FLT2: Fault 2 interrupt
bogdanm 0:9b334a45a8ff 1229 * @arg HRTIM_IT_FLT3: Fault 3 interrupt Interrupt
bogdanm 0:9b334a45a8ff 1230 * @arg HRTIM_IT_FLT4: Fault 4 Interrupt
bogdanm 0:9b334a45a8ff 1231 * @arg HRTIM_IT_FLT5: Fault 5 Interrupt
bogdanm 0:9b334a45a8ff 1232 * @arg HRTIM_IT_SYSFLT: System Fault Interrupt
bogdanm 0:9b334a45a8ff 1233 * @arg HRTIM_IT_DLLRDY: DLL ready Interrupt flag
bogdanm 0:9b334a45a8ff 1234 * @arg HRTIM_IT_BMPER: Burst mode period Interrupt
bogdanm 0:9b334a45a8ff 1235 * @retval The new state of HRTIM_FLAG (SET or RESET).
bogdanm 0:9b334a45a8ff 1236 */
bogdanm 0:9b334a45a8ff 1237 ITStatus HRTIM_GetCommonITStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT)
bogdanm 0:9b334a45a8ff 1238 {
bogdanm 0:9b334a45a8ff 1239 ITStatus bitstatus = RESET;
bogdanm 0:9b334a45a8ff 1240 uint16_t itstatus = 0x0, itenable = 0x0;
bogdanm 0:9b334a45a8ff 1241
bogdanm 0:9b334a45a8ff 1242 itstatus = HRTIMx->HRTIM_COMMON.ISR & HRTIM_CommonIT;
bogdanm 0:9b334a45a8ff 1243 itenable = HRTIMx->HRTIM_COMMON.IER & HRTIM_CommonIT;
bogdanm 0:9b334a45a8ff 1244
bogdanm 0:9b334a45a8ff 1245 if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
bogdanm 0:9b334a45a8ff 1246 {
bogdanm 0:9b334a45a8ff 1247 bitstatus = SET;
bogdanm 0:9b334a45a8ff 1248 }
bogdanm 0:9b334a45a8ff 1249 else
bogdanm 0:9b334a45a8ff 1250 {
bogdanm 0:9b334a45a8ff 1251 bitstatus = RESET;
bogdanm 0:9b334a45a8ff 1252 }
bogdanm 0:9b334a45a8ff 1253
bogdanm 0:9b334a45a8ff 1254 return bitstatus;
bogdanm 0:9b334a45a8ff 1255 }
bogdanm 0:9b334a45a8ff 1256
bogdanm 0:9b334a45a8ff 1257 /**
bogdanm 0:9b334a45a8ff 1258 * @brief Enables or disables the HRTIMx's DMA Requests.
bogdanm 0:9b334a45a8ff 1259 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 1260 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 1261 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1262 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 1263 * @param HRTIM_DMA: specifies the DMA Request sources.
bogdanm 0:9b334a45a8ff 1264 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 1265 * @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA request source
bogdanm 0:9b334a45a8ff 1266 * @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA request source
bogdanm 0:9b334a45a8ff 1267 * @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA request source
bogdanm 0:9b334a45a8ff 1268 * @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA request source
bogdanm 0:9b334a45a8ff 1269 * @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA request source
bogdanm 0:9b334a45a8ff 1270 * @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA request source
bogdanm 0:9b334a45a8ff 1271 * @arg HRTIM_MASTER_DMA_MUPD:Master update DMA request source
bogdanm 0:9b334a45a8ff 1272 * @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA request source
bogdanm 0:9b334a45a8ff 1273 * @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA request source
bogdanm 0:9b334a45a8ff 1274 * @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA request source
bogdanm 0:9b334a45a8ff 1275 * @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA request source
bogdanm 0:9b334a45a8ff 1276 * @arg HRTIM_TIM_DMA_REP: Timer repetition DMA request source
bogdanm 0:9b334a45a8ff 1277 * @arg HRTIM_TIM_DMA_UPD: Timer update DMA request source
bogdanm 0:9b334a45a8ff 1278 * @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA request source
bogdanm 0:9b334a45a8ff 1279 * @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA request source
bogdanm 0:9b334a45a8ff 1280 * @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA request source
bogdanm 0:9b334a45a8ff 1281 * @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA request source
bogdanm 0:9b334a45a8ff 1282 * @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA request source
bogdanm 0:9b334a45a8ff 1283 * @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA request source
bogdanm 0:9b334a45a8ff 1284 * @arg HRTIM_TIM_DMA_RST: Timer reset DMA request source
bogdanm 0:9b334a45a8ff 1285 * @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA request source
bogdanm 0:9b334a45a8ff 1286 * @param NewState: new state of the DMA Request sources.
bogdanm 0:9b334a45a8ff 1287 * This parameter can be: ENABLE or DISABLE.
bogdanm 0:9b334a45a8ff 1288 * @retval None
bogdanm 0:9b334a45a8ff 1289 */
bogdanm 0:9b334a45a8ff 1290 void HRTIM_DMACmd(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_DMA, FunctionalState NewState)
bogdanm 0:9b334a45a8ff 1291 {
bogdanm 0:9b334a45a8ff 1292 if(TimerIdx != HRTIM_TIMERINDEX_MASTER)
bogdanm 0:9b334a45a8ff 1293 {
bogdanm 0:9b334a45a8ff 1294 if(NewState != DISABLE)
bogdanm 0:9b334a45a8ff 1295 {
bogdanm 0:9b334a45a8ff 1296 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER |= HRTIM_DMA;
bogdanm 0:9b334a45a8ff 1297 }
bogdanm 0:9b334a45a8ff 1298 else
bogdanm 0:9b334a45a8ff 1299 {
bogdanm 0:9b334a45a8ff 1300 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER &= ~HRTIM_DMA;
bogdanm 0:9b334a45a8ff 1301 }
bogdanm 0:9b334a45a8ff 1302 }
bogdanm 0:9b334a45a8ff 1303 else
bogdanm 0:9b334a45a8ff 1304 {
bogdanm 0:9b334a45a8ff 1305 if(NewState != DISABLE)
bogdanm 0:9b334a45a8ff 1306 {
bogdanm 0:9b334a45a8ff 1307 HRTIMx->HRTIM_MASTER.MDIER |= HRTIM_DMA;
bogdanm 0:9b334a45a8ff 1308 }
bogdanm 0:9b334a45a8ff 1309 else
bogdanm 0:9b334a45a8ff 1310 {
bogdanm 0:9b334a45a8ff 1311 HRTIMx->HRTIM_MASTER.MDIER &= ~HRTIM_DMA;
bogdanm 0:9b334a45a8ff 1312 }
bogdanm 0:9b334a45a8ff 1313 }
bogdanm 0:9b334a45a8ff 1314 }
bogdanm 0:9b334a45a8ff 1315
bogdanm 0:9b334a45a8ff 1316 /**
bogdanm 0:9b334a45a8ff 1317 * @}
bogdanm 0:9b334a45a8ff 1318 */
bogdanm 0:9b334a45a8ff 1319
bogdanm 0:9b334a45a8ff 1320 /** @defgroup HRTIM_Group3 Peripheral Control methods
bogdanm 0:9b334a45a8ff 1321 * @brief management functions
bogdanm 0:9b334a45a8ff 1322 *
bogdanm 0:9b334a45a8ff 1323 @verbatim
bogdanm 0:9b334a45a8ff 1324 ===============================================================================
bogdanm 0:9b334a45a8ff 1325 ##### Peripheral Control methods #####
bogdanm 0:9b334a45a8ff 1326 ===============================================================================
bogdanm 0:9b334a45a8ff 1327 [..]
bogdanm 0:9b334a45a8ff 1328 This subsection provides a set of functions allowing to control the HRTIMx data
bogdanm 0:9b334a45a8ff 1329 transfers.
bogdanm 0:9b334a45a8ff 1330
bogdanm 0:9b334a45a8ff 1331 @endverbatim
bogdanm 0:9b334a45a8ff 1332 * @{
bogdanm 0:9b334a45a8ff 1333 */
bogdanm 0:9b334a45a8ff 1334
bogdanm 0:9b334a45a8ff 1335 /**
bogdanm 0:9b334a45a8ff 1336 * @brief Configures an output in basic output compare mode
bogdanm 0:9b334a45a8ff 1337 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 1338 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 1339 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1340 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 1341 * @param OCChannel: Timer output
bogdanm 0:9b334a45a8ff 1342 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1343 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
bogdanm 0:9b334a45a8ff 1344 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
bogdanm 0:9b334a45a8ff 1345 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
bogdanm 0:9b334a45a8ff 1346 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
bogdanm 0:9b334a45a8ff 1347 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
bogdanm 0:9b334a45a8ff 1348 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
bogdanm 0:9b334a45a8ff 1349 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
bogdanm 0:9b334a45a8ff 1350 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
bogdanm 0:9b334a45a8ff 1351 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
bogdanm 0:9b334a45a8ff 1352 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
bogdanm 0:9b334a45a8ff 1353 * @param pBasicOCChannelCfg: pointer to the basic output compare output configuration structure
bogdanm 0:9b334a45a8ff 1354 * @note When the timer operates in basic output compare mode:
bogdanm 0:9b334a45a8ff 1355 * Output 1 is implicitely controled by the compare unit 1
bogdanm 0:9b334a45a8ff 1356 * Output 2 is implicitely controled by the compare unit 2
bogdanm 0:9b334a45a8ff 1357 * Output Set/Reset crossbar is set according to the selected output compare mode:
bogdanm 0:9b334a45a8ff 1358 * Toggle: SETxyR = RSTxyR = CMPy
bogdanm 0:9b334a45a8ff 1359 * Active: SETxyR = CMPy, RSTxyR = 0
bogdanm 0:9b334a45a8ff 1360 * Inactive: SETxy =0, RSTxy = CMPy
bogdanm 0:9b334a45a8ff 1361 * @retval None
bogdanm 0:9b334a45a8ff 1362 */
bogdanm 0:9b334a45a8ff 1363 void HRTIM_SimpleOCChannelConfig(HRTIM_TypeDef * HRTIM_,
bogdanm 0:9b334a45a8ff 1364 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 1365 uint32_t OCChannel,
bogdanm 0:9b334a45a8ff 1366 HRTIM_BasicOCChannelCfgTypeDef* pBasicOCChannelCfg)
bogdanm 0:9b334a45a8ff 1367 {
bogdanm 0:9b334a45a8ff 1368 uint32_t CompareUnit = HRTIM_COMPAREUNIT_1;
bogdanm 0:9b334a45a8ff 1369 HRTIM_CompareCfgTypeDef CompareCfg;
bogdanm 0:9b334a45a8ff 1370 HRTIM_OutputCfgTypeDef OutputCfg;
bogdanm 0:9b334a45a8ff 1371
bogdanm 0:9b334a45a8ff 1372 /* Check parameters */
bogdanm 0:9b334a45a8ff 1373 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
bogdanm 0:9b334a45a8ff 1374 assert_param(IS_HRTIM_BASICOCMODE(pBasicOCChannelCfg->Mode));
bogdanm 0:9b334a45a8ff 1375 assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicOCChannelCfg->Polarity));
bogdanm 0:9b334a45a8ff 1376 assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicOCChannelCfg->IdleState));
bogdanm 0:9b334a45a8ff 1377
bogdanm 0:9b334a45a8ff 1378 /* Configure timer compare unit */
bogdanm 0:9b334a45a8ff 1379 switch (OCChannel)
bogdanm 0:9b334a45a8ff 1380 {
bogdanm 0:9b334a45a8ff 1381 case HRTIM_OUTPUT_TA1:
bogdanm 0:9b334a45a8ff 1382 case HRTIM_OUTPUT_TB1:
bogdanm 0:9b334a45a8ff 1383 case HRTIM_OUTPUT_TC1:
bogdanm 0:9b334a45a8ff 1384 case HRTIM_OUTPUT_TD1:
bogdanm 0:9b334a45a8ff 1385 case HRTIM_OUTPUT_TE1:
bogdanm 0:9b334a45a8ff 1386 {
bogdanm 0:9b334a45a8ff 1387 CompareUnit = HRTIM_COMPAREUNIT_1;
bogdanm 0:9b334a45a8ff 1388 }
bogdanm 0:9b334a45a8ff 1389 break;
bogdanm 0:9b334a45a8ff 1390 case HRTIM_OUTPUT_TA2:
bogdanm 0:9b334a45a8ff 1391 case HRTIM_OUTPUT_TB2:
bogdanm 0:9b334a45a8ff 1392 case HRTIM_OUTPUT_TC2:
bogdanm 0:9b334a45a8ff 1393 case HRTIM_OUTPUT_TD2:
bogdanm 0:9b334a45a8ff 1394 case HRTIM_OUTPUT_TE2:
bogdanm 0:9b334a45a8ff 1395 {
bogdanm 0:9b334a45a8ff 1396 CompareUnit = HRTIM_COMPAREUNIT_2;
bogdanm 0:9b334a45a8ff 1397 }
bogdanm 0:9b334a45a8ff 1398 break;
bogdanm 0:9b334a45a8ff 1399 default:
bogdanm 0:9b334a45a8ff 1400 break;
bogdanm 0:9b334a45a8ff 1401 }
bogdanm 0:9b334a45a8ff 1402
bogdanm 0:9b334a45a8ff 1403 CompareCfg.CompareValue = pBasicOCChannelCfg->Pulse;
bogdanm 0:9b334a45a8ff 1404 CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
bogdanm 0:9b334a45a8ff 1405 CompareCfg.AutoDelayedTimeout = 0;
bogdanm 0:9b334a45a8ff 1406
bogdanm 0:9b334a45a8ff 1407 HRTIM_CompareUnitConfig(HRTIM_,
bogdanm 0:9b334a45a8ff 1408 TimerIdx,
bogdanm 0:9b334a45a8ff 1409 CompareUnit,
bogdanm 0:9b334a45a8ff 1410 &CompareCfg);
bogdanm 0:9b334a45a8ff 1411
bogdanm 0:9b334a45a8ff 1412 /* Configure timer output */
bogdanm 0:9b334a45a8ff 1413 OutputCfg.Polarity = pBasicOCChannelCfg->Polarity;
bogdanm 0:9b334a45a8ff 1414 OutputCfg.IdleState = pBasicOCChannelCfg->IdleState;
bogdanm 0:9b334a45a8ff 1415 OutputCfg.FaultState = HRTIM_OUTPUTFAULTSTATE_NONE;
bogdanm 0:9b334a45a8ff 1416 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
bogdanm 0:9b334a45a8ff 1417 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
bogdanm 0:9b334a45a8ff 1418 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
bogdanm 0:9b334a45a8ff 1419
bogdanm 0:9b334a45a8ff 1420 switch (pBasicOCChannelCfg->Mode)
bogdanm 0:9b334a45a8ff 1421 {
bogdanm 0:9b334a45a8ff 1422 case HRTIM_BASICOCMODE_TOGGLE:
bogdanm 0:9b334a45a8ff 1423 {
bogdanm 0:9b334a45a8ff 1424 if (CompareUnit == HRTIM_COMPAREUNIT_1)
bogdanm 0:9b334a45a8ff 1425 {
bogdanm 0:9b334a45a8ff 1426 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
bogdanm 0:9b334a45a8ff 1427 }
bogdanm 0:9b334a45a8ff 1428 else
bogdanm 0:9b334a45a8ff 1429 {
bogdanm 0:9b334a45a8ff 1430 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
bogdanm 0:9b334a45a8ff 1431 }
bogdanm 0:9b334a45a8ff 1432 OutputCfg.ResetSource = OutputCfg.SetSource;
bogdanm 0:9b334a45a8ff 1433 }
bogdanm 0:9b334a45a8ff 1434 break;
bogdanm 0:9b334a45a8ff 1435 case HRTIM_BASICOCMODE_ACTIVE:
bogdanm 0:9b334a45a8ff 1436 {
bogdanm 0:9b334a45a8ff 1437 if (CompareUnit == HRTIM_COMPAREUNIT_1)
bogdanm 0:9b334a45a8ff 1438 {
bogdanm 0:9b334a45a8ff 1439 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
bogdanm 0:9b334a45a8ff 1440 }
bogdanm 0:9b334a45a8ff 1441 else
bogdanm 0:9b334a45a8ff 1442 {
bogdanm 0:9b334a45a8ff 1443 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
bogdanm 0:9b334a45a8ff 1444 }
bogdanm 0:9b334a45a8ff 1445 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
bogdanm 0:9b334a45a8ff 1446 }
bogdanm 0:9b334a45a8ff 1447 break;
bogdanm 0:9b334a45a8ff 1448 case HRTIM_BASICOCMODE_INACTIVE:
bogdanm 0:9b334a45a8ff 1449 {
bogdanm 0:9b334a45a8ff 1450 if (CompareUnit == HRTIM_COMPAREUNIT_1)
bogdanm 0:9b334a45a8ff 1451 {
bogdanm 0:9b334a45a8ff 1452 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
bogdanm 0:9b334a45a8ff 1453 }
bogdanm 0:9b334a45a8ff 1454 else
bogdanm 0:9b334a45a8ff 1455 {
bogdanm 0:9b334a45a8ff 1456 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
bogdanm 0:9b334a45a8ff 1457 }
bogdanm 0:9b334a45a8ff 1458 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
bogdanm 0:9b334a45a8ff 1459 }
bogdanm 0:9b334a45a8ff 1460 break;
bogdanm 0:9b334a45a8ff 1461 default:
bogdanm 0:9b334a45a8ff 1462 break;
bogdanm 0:9b334a45a8ff 1463 }
bogdanm 0:9b334a45a8ff 1464
bogdanm 0:9b334a45a8ff 1465 HRTIM_OutputConfig(HRTIM_, TimerIdx, OCChannel, &OutputCfg);
bogdanm 0:9b334a45a8ff 1466 }
bogdanm 0:9b334a45a8ff 1467
bogdanm 0:9b334a45a8ff 1468 /**
bogdanm 0:9b334a45a8ff 1469 * @brief Configures an output in basic PWM mode
bogdanm 0:9b334a45a8ff 1470 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 1471 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 1472 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1473 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 1474 * @param PWMChannel: Timer output
bogdanm 0:9b334a45a8ff 1475 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1476 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
bogdanm 0:9b334a45a8ff 1477 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
bogdanm 0:9b334a45a8ff 1478 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
bogdanm 0:9b334a45a8ff 1479 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
bogdanm 0:9b334a45a8ff 1480 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
bogdanm 0:9b334a45a8ff 1481 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
bogdanm 0:9b334a45a8ff 1482 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
bogdanm 0:9b334a45a8ff 1483 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
bogdanm 0:9b334a45a8ff 1484 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
bogdanm 0:9b334a45a8ff 1485 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
bogdanm 0:9b334a45a8ff 1486 * @param pBasicPWMChannelCfg: pointer to the basic PWM output configuration structure
bogdanm 0:9b334a45a8ff 1487 * @note When the timer operates in basic PWM output mode:
bogdanm 0:9b334a45a8ff 1488 * Output 1 is implicitly controled by the compare unit 1
bogdanm 0:9b334a45a8ff 1489 * Output 2 is implicitly controled by the compare unit 2
bogdanm 0:9b334a45a8ff 1490 * Output Set/Reset crossbar is set as follows:
bogdanm 0:9b334a45a8ff 1491 * Output 1: SETx1R = CMP1, RSTx1R = PER
bogdanm 0:9b334a45a8ff 1492 * Output 2: SETx2R = CMP2, RST2R = PER
bogdanm 0:9b334a45a8ff 1493 * @retval None
bogdanm 0:9b334a45a8ff 1494 */
bogdanm 0:9b334a45a8ff 1495 void HRTIM_SimplePWMChannelConfig(HRTIM_TypeDef * HRTIM_,
bogdanm 0:9b334a45a8ff 1496 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 1497 uint32_t PWMChannel,
bogdanm 0:9b334a45a8ff 1498 HRTIM_BasicPWMChannelCfgTypeDef* pBasicPWMChannelCfg)
bogdanm 0:9b334a45a8ff 1499 {
bogdanm 0:9b334a45a8ff 1500 uint32_t CompareUnit = HRTIM_COMPAREUNIT_1;
bogdanm 0:9b334a45a8ff 1501 HRTIM_CompareCfgTypeDef CompareCfg;
bogdanm 0:9b334a45a8ff 1502 HRTIM_OutputCfgTypeDef OutputCfg;
bogdanm 0:9b334a45a8ff 1503
bogdanm 0:9b334a45a8ff 1504 /* Check parameters */
bogdanm 0:9b334a45a8ff 1505 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
bogdanm 0:9b334a45a8ff 1506 assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicPWMChannelCfg->Polarity));
bogdanm 0:9b334a45a8ff 1507 assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicPWMChannelCfg->IdleState));
bogdanm 0:9b334a45a8ff 1508
bogdanm 0:9b334a45a8ff 1509 /* Configure timer compare unit */
bogdanm 0:9b334a45a8ff 1510 switch (PWMChannel)
bogdanm 0:9b334a45a8ff 1511 {
bogdanm 0:9b334a45a8ff 1512 case HRTIM_OUTPUT_TA1:
bogdanm 0:9b334a45a8ff 1513 case HRTIM_OUTPUT_TB1:
bogdanm 0:9b334a45a8ff 1514 case HRTIM_OUTPUT_TC1:
bogdanm 0:9b334a45a8ff 1515 case HRTIM_OUTPUT_TD1:
bogdanm 0:9b334a45a8ff 1516 case HRTIM_OUTPUT_TE1:
bogdanm 0:9b334a45a8ff 1517 {
bogdanm 0:9b334a45a8ff 1518 CompareUnit = HRTIM_COMPAREUNIT_1;
bogdanm 0:9b334a45a8ff 1519 }
bogdanm 0:9b334a45a8ff 1520 break;
bogdanm 0:9b334a45a8ff 1521 case HRTIM_OUTPUT_TA2:
bogdanm 0:9b334a45a8ff 1522 case HRTIM_OUTPUT_TB2:
bogdanm 0:9b334a45a8ff 1523 case HRTIM_OUTPUT_TC2:
bogdanm 0:9b334a45a8ff 1524 case HRTIM_OUTPUT_TD2:
bogdanm 0:9b334a45a8ff 1525 case HRTIM_OUTPUT_TE2:
bogdanm 0:9b334a45a8ff 1526 {
bogdanm 0:9b334a45a8ff 1527 CompareUnit = HRTIM_COMPAREUNIT_2;
bogdanm 0:9b334a45a8ff 1528 }
bogdanm 0:9b334a45a8ff 1529 break;
bogdanm 0:9b334a45a8ff 1530 default:
bogdanm 0:9b334a45a8ff 1531 break;
bogdanm 0:9b334a45a8ff 1532 }
bogdanm 0:9b334a45a8ff 1533
bogdanm 0:9b334a45a8ff 1534 CompareCfg.CompareValue = pBasicPWMChannelCfg->Pulse;
bogdanm 0:9b334a45a8ff 1535 CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
bogdanm 0:9b334a45a8ff 1536 CompareCfg.AutoDelayedTimeout = 0;
bogdanm 0:9b334a45a8ff 1537
bogdanm 0:9b334a45a8ff 1538 HRTIM_CompareUnitConfig(HRTIM_,
bogdanm 0:9b334a45a8ff 1539 TimerIdx,
bogdanm 0:9b334a45a8ff 1540 CompareUnit,
bogdanm 0:9b334a45a8ff 1541 &CompareCfg);
bogdanm 0:9b334a45a8ff 1542
bogdanm 0:9b334a45a8ff 1543 /* Configure timer output */
bogdanm 0:9b334a45a8ff 1544 OutputCfg.Polarity = pBasicPWMChannelCfg->Polarity;
bogdanm 0:9b334a45a8ff 1545 OutputCfg.IdleState = pBasicPWMChannelCfg->IdleState;
bogdanm 0:9b334a45a8ff 1546 OutputCfg.FaultState = HRTIM_OUTPUTFAULTSTATE_NONE;
bogdanm 0:9b334a45a8ff 1547 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
bogdanm 0:9b334a45a8ff 1548 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
bogdanm 0:9b334a45a8ff 1549 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
bogdanm 0:9b334a45a8ff 1550
bogdanm 0:9b334a45a8ff 1551 if (CompareUnit == HRTIM_COMPAREUNIT_1)
bogdanm 0:9b334a45a8ff 1552 {
bogdanm 0:9b334a45a8ff 1553 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
bogdanm 0:9b334a45a8ff 1554 }
bogdanm 0:9b334a45a8ff 1555 else
bogdanm 0:9b334a45a8ff 1556 {
bogdanm 0:9b334a45a8ff 1557 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
bogdanm 0:9b334a45a8ff 1558 }
bogdanm 0:9b334a45a8ff 1559 OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
bogdanm 0:9b334a45a8ff 1560
bogdanm 0:9b334a45a8ff 1561 HRTIM_OutputConfig(HRTIM_, TimerIdx, PWMChannel, &OutputCfg);
bogdanm 0:9b334a45a8ff 1562 }
bogdanm 0:9b334a45a8ff 1563
bogdanm 0:9b334a45a8ff 1564 /**
bogdanm 0:9b334a45a8ff 1565 * @brief Configures a basic capture
bogdanm 0:9b334a45a8ff 1566 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 1567 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 1568 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1569 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 1570 * @param CaptureChannel: Capture unit
bogdanm 0:9b334a45a8ff 1571 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1572 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
bogdanm 0:9b334a45a8ff 1573 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
bogdanm 0:9b334a45a8ff 1574 * @param pBasicCaptureChannelCfg: pointer to the basic capture configuration structure
bogdanm 0:9b334a45a8ff 1575 * @note When the timer operates in basic capture mode the capture is triggered
bogdanm 0:9b334a45a8ff 1576 * by the designated external event and GPIO input is implicitly used as event source.
bogdanm 0:9b334a45a8ff 1577 * The cature can be triggered by a rising edge, a falling edge or both
bogdanm 0:9b334a45a8ff 1578 * edges on event channel.
bogdanm 0:9b334a45a8ff 1579 * @retval None
bogdanm 0:9b334a45a8ff 1580 */
bogdanm 0:9b334a45a8ff 1581 void HRTIM_SimpleCaptureChannelConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 1582 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 1583 uint32_t CaptureChannel,
bogdanm 0:9b334a45a8ff 1584 HRTIM_BasicCaptureChannelCfgTypeDef* pBasicCaptureChannelCfg)
bogdanm 0:9b334a45a8ff 1585 {
bogdanm 0:9b334a45a8ff 1586 HRTIM_EventCfgTypeDef EventCfg;
bogdanm 0:9b334a45a8ff 1587
bogdanm 0:9b334a45a8ff 1588 /* Check parameters */
bogdanm 0:9b334a45a8ff 1589 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
bogdanm 0:9b334a45a8ff 1590 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
bogdanm 0:9b334a45a8ff 1591 assert_param(IS_HRTIM_EVENT(pBasicCaptureChannelCfg->Event));
bogdanm 0:9b334a45a8ff 1592 assert_param(IS_HRTIM_EVENTPOLARITY(pBasicCaptureChannelCfg->EventPolarity));
bogdanm 0:9b334a45a8ff 1593 assert_param(IS_HRTIM_EVENTSENSITIVITY(pBasicCaptureChannelCfg->EventSensitivity));
bogdanm 0:9b334a45a8ff 1594 assert_param(IS_HRTIM_EVENTFILTER(pBasicCaptureChannelCfg->EventFilter));
bogdanm 0:9b334a45a8ff 1595
bogdanm 0:9b334a45a8ff 1596 /* Configure external event channel */
bogdanm 0:9b334a45a8ff 1597 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
bogdanm 0:9b334a45a8ff 1598 EventCfg.Filter = pBasicCaptureChannelCfg->EventFilter;
bogdanm 0:9b334a45a8ff 1599 EventCfg.Polarity = pBasicCaptureChannelCfg->EventPolarity;
bogdanm 0:9b334a45a8ff 1600 EventCfg.Sensitivity = pBasicCaptureChannelCfg->EventSensitivity;
bogdanm 0:9b334a45a8ff 1601 EventCfg.Source = HRTIM_EVENTSRC_1;
bogdanm 0:9b334a45a8ff 1602
bogdanm 0:9b334a45a8ff 1603 HRTIM_ExternalEventConfig(HRTIMx,
bogdanm 0:9b334a45a8ff 1604 pBasicCaptureChannelCfg->Event,
bogdanm 0:9b334a45a8ff 1605 &EventCfg);
bogdanm 0:9b334a45a8ff 1606
bogdanm 0:9b334a45a8ff 1607 /* Memorize capture trigger (will be configured when the capture is started */
bogdanm 0:9b334a45a8ff 1608 HRTIM_CaptureUnitConfig(HRTIMx,
bogdanm 0:9b334a45a8ff 1609 TimerIdx,
bogdanm 0:9b334a45a8ff 1610 CaptureChannel,
bogdanm 0:9b334a45a8ff 1611 pBasicCaptureChannelCfg->Event);
bogdanm 0:9b334a45a8ff 1612 }
bogdanm 0:9b334a45a8ff 1613
bogdanm 0:9b334a45a8ff 1614 /**
bogdanm 0:9b334a45a8ff 1615 * @brief Configures an output basic one pulse mode
bogdanm 0:9b334a45a8ff 1616 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 1617 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 1618 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1619 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 1620 * @param OnePulseChannel: Timer output
bogdanm 0:9b334a45a8ff 1621 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1622 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
bogdanm 0:9b334a45a8ff 1623 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
bogdanm 0:9b334a45a8ff 1624 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
bogdanm 0:9b334a45a8ff 1625 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
bogdanm 0:9b334a45a8ff 1626 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
bogdanm 0:9b334a45a8ff 1627 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
bogdanm 0:9b334a45a8ff 1628 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
bogdanm 0:9b334a45a8ff 1629 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
bogdanm 0:9b334a45a8ff 1630 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
bogdanm 0:9b334a45a8ff 1631 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
bogdanm 0:9b334a45a8ff 1632 * @param pBasicOnePulseChannelCfg: pointer to the basic one pulse output configuration structure
bogdanm 0:9b334a45a8ff 1633 * @note When the timer operates in basic one pulse mode:
bogdanm 0:9b334a45a8ff 1634 * the timer counter is implicitly started by the reset event,
bogdanm 0:9b334a45a8ff 1635 * the reset of the timer counter is triggered by the designated external event
bogdanm 0:9b334a45a8ff 1636 * GPIO input is implicitly used as event source,
bogdanm 0:9b334a45a8ff 1637 * Output 1 is implicitly controled by the compare unit 1,
bogdanm 0:9b334a45a8ff 1638 * Output 2 is implicitly controled by the compare unit 2.
bogdanm 0:9b334a45a8ff 1639 * Output Set/Reset crossbar is set as follows:
bogdanm 0:9b334a45a8ff 1640 * Output 1: SETx1R = CMP1, RSTx1R = PER
bogdanm 0:9b334a45a8ff 1641 * Output 2: SETx2R = CMP2, RST2R = PER
bogdanm 0:9b334a45a8ff 1642 * The counter mode should be HRTIM_MODE_SINGLESHOT_RETRIGGERABLE
bogdanm 0:9b334a45a8ff 1643 * @retval None
bogdanm 0:9b334a45a8ff 1644 */
bogdanm 0:9b334a45a8ff 1645 void HRTIM_SimpleOnePulseChannelConfig(HRTIM_TypeDef * HRTIM_,
bogdanm 0:9b334a45a8ff 1646 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 1647 uint32_t OnePulseChannel,
bogdanm 0:9b334a45a8ff 1648 HRTIM_BasicOnePulseChannelCfgTypeDef* pBasicOnePulseChannelCfg)
bogdanm 0:9b334a45a8ff 1649 {
bogdanm 0:9b334a45a8ff 1650 uint32_t CompareUnit = HRTIM_COMPAREUNIT_1;
bogdanm 0:9b334a45a8ff 1651 HRTIM_CompareCfgTypeDef CompareCfg;
bogdanm 0:9b334a45a8ff 1652 HRTIM_OutputCfgTypeDef OutputCfg;
bogdanm 0:9b334a45a8ff 1653 HRTIM_EventCfgTypeDef EventCfg;
bogdanm 0:9b334a45a8ff 1654
bogdanm 0:9b334a45a8ff 1655 /* Check parameters */
bogdanm 0:9b334a45a8ff 1656 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
bogdanm 0:9b334a45a8ff 1657 assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicOnePulseChannelCfg->OutputPolarity));
bogdanm 0:9b334a45a8ff 1658 assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicOnePulseChannelCfg->OutputIdleState));
bogdanm 0:9b334a45a8ff 1659 assert_param(IS_HRTIM_EVENT(pBasicOnePulseChannelCfg->Event));
bogdanm 0:9b334a45a8ff 1660 assert_param(IS_HRTIM_EVENTPOLARITY(pBasicOnePulseChannelCfg->EventPolarity));
bogdanm 0:9b334a45a8ff 1661 assert_param(IS_HRTIM_EVENTSENSITIVITY(pBasicOnePulseChannelCfg->EventSensitivity));
bogdanm 0:9b334a45a8ff 1662 assert_param(IS_HRTIM_EVENTFILTER(pBasicOnePulseChannelCfg->EventFilter));
bogdanm 0:9b334a45a8ff 1663
bogdanm 0:9b334a45a8ff 1664 /* Configure timer compare unit */
bogdanm 0:9b334a45a8ff 1665 switch (OnePulseChannel)
bogdanm 0:9b334a45a8ff 1666 {
bogdanm 0:9b334a45a8ff 1667 case HRTIM_OUTPUT_TA1:
bogdanm 0:9b334a45a8ff 1668 case HRTIM_OUTPUT_TB1:
bogdanm 0:9b334a45a8ff 1669 case HRTIM_OUTPUT_TC1:
bogdanm 0:9b334a45a8ff 1670 case HRTIM_OUTPUT_TD1:
bogdanm 0:9b334a45a8ff 1671 case HRTIM_OUTPUT_TE1:
bogdanm 0:9b334a45a8ff 1672 {
bogdanm 0:9b334a45a8ff 1673 CompareUnit = HRTIM_COMPAREUNIT_1;
bogdanm 0:9b334a45a8ff 1674 }
bogdanm 0:9b334a45a8ff 1675 break;
bogdanm 0:9b334a45a8ff 1676 case HRTIM_OUTPUT_TA2:
bogdanm 0:9b334a45a8ff 1677 case HRTIM_OUTPUT_TB2:
bogdanm 0:9b334a45a8ff 1678 case HRTIM_OUTPUT_TC2:
bogdanm 0:9b334a45a8ff 1679 case HRTIM_OUTPUT_TD2:
bogdanm 0:9b334a45a8ff 1680 case HRTIM_OUTPUT_TE2:
bogdanm 0:9b334a45a8ff 1681 {
bogdanm 0:9b334a45a8ff 1682 CompareUnit = HRTIM_COMPAREUNIT_2;
bogdanm 0:9b334a45a8ff 1683 }
bogdanm 0:9b334a45a8ff 1684 break;
bogdanm 0:9b334a45a8ff 1685 default:
bogdanm 0:9b334a45a8ff 1686 break;
bogdanm 0:9b334a45a8ff 1687 }
bogdanm 0:9b334a45a8ff 1688
bogdanm 0:9b334a45a8ff 1689 CompareCfg.CompareValue = pBasicOnePulseChannelCfg->Pulse;
bogdanm 0:9b334a45a8ff 1690 CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
bogdanm 0:9b334a45a8ff 1691 CompareCfg.AutoDelayedTimeout = 0;
bogdanm 0:9b334a45a8ff 1692
bogdanm 0:9b334a45a8ff 1693 HRTIM_CompareUnitConfig(HRTIM_,
bogdanm 0:9b334a45a8ff 1694 TimerIdx,
bogdanm 0:9b334a45a8ff 1695 CompareUnit,
bogdanm 0:9b334a45a8ff 1696 &CompareCfg);
bogdanm 0:9b334a45a8ff 1697
bogdanm 0:9b334a45a8ff 1698 /* Configure timer output */
bogdanm 0:9b334a45a8ff 1699 OutputCfg.Polarity = pBasicOnePulseChannelCfg->OutputPolarity;
bogdanm 0:9b334a45a8ff 1700 OutputCfg.IdleState = pBasicOnePulseChannelCfg->OutputIdleState;
bogdanm 0:9b334a45a8ff 1701 OutputCfg.FaultState = HRTIM_OUTPUTFAULTSTATE_NONE;
bogdanm 0:9b334a45a8ff 1702 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
bogdanm 0:9b334a45a8ff 1703 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
bogdanm 0:9b334a45a8ff 1704 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
bogdanm 0:9b334a45a8ff 1705
bogdanm 0:9b334a45a8ff 1706 if (CompareUnit == HRTIM_COMPAREUNIT_1)
bogdanm 0:9b334a45a8ff 1707 {
bogdanm 0:9b334a45a8ff 1708 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
bogdanm 0:9b334a45a8ff 1709 }
bogdanm 0:9b334a45a8ff 1710 else
bogdanm 0:9b334a45a8ff 1711 {
bogdanm 0:9b334a45a8ff 1712 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
bogdanm 0:9b334a45a8ff 1713 }
bogdanm 0:9b334a45a8ff 1714 OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
bogdanm 0:9b334a45a8ff 1715
bogdanm 0:9b334a45a8ff 1716 HRTIM_OutputConfig(HRTIM_,
bogdanm 0:9b334a45a8ff 1717 TimerIdx,
bogdanm 0:9b334a45a8ff 1718 OnePulseChannel,
bogdanm 0:9b334a45a8ff 1719 &OutputCfg);
bogdanm 0:9b334a45a8ff 1720
bogdanm 0:9b334a45a8ff 1721 /* Configure external event channel */
bogdanm 0:9b334a45a8ff 1722 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
bogdanm 0:9b334a45a8ff 1723 EventCfg.Filter = pBasicOnePulseChannelCfg->EventFilter;
bogdanm 0:9b334a45a8ff 1724 EventCfg.Polarity = pBasicOnePulseChannelCfg->EventPolarity;
bogdanm 0:9b334a45a8ff 1725 EventCfg.Sensitivity = pBasicOnePulseChannelCfg->EventSensitivity;
bogdanm 0:9b334a45a8ff 1726 EventCfg.Source = HRTIM_EVENTSRC_1;
bogdanm 0:9b334a45a8ff 1727
bogdanm 0:9b334a45a8ff 1728 HRTIM_ExternalEventConfig(HRTIM_,
bogdanm 0:9b334a45a8ff 1729 pBasicOnePulseChannelCfg->Event,
bogdanm 0:9b334a45a8ff 1730 &EventCfg);
bogdanm 0:9b334a45a8ff 1731
bogdanm 0:9b334a45a8ff 1732 /* Configure the timer reset register */
bogdanm 0:9b334a45a8ff 1733 HRTIM_TIM_ResetConfig(HRTIM_,
bogdanm 0:9b334a45a8ff 1734 TimerIdx,
bogdanm 0:9b334a45a8ff 1735 pBasicOnePulseChannelCfg->Event);
bogdanm 0:9b334a45a8ff 1736 }
bogdanm 0:9b334a45a8ff 1737
bogdanm 0:9b334a45a8ff 1738 /**
bogdanm 0:9b334a45a8ff 1739 * @brief Configures the general behavior of a timer operating in waveform mode
bogdanm 0:9b334a45a8ff 1740 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 1741 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 1742 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1743 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 1744 * @param pTimerCfg: pointer to the timer configuration structure
bogdanm 0:9b334a45a8ff 1745 * @note When the timer operates in waveform mode, all the features supported by
bogdanm 0:9b334a45a8ff 1746 * the HRTIMx are available without any limitation.
bogdanm 0:9b334a45a8ff 1747 * @retval None
bogdanm 0:9b334a45a8ff 1748 */
bogdanm 0:9b334a45a8ff 1749 void HRTIM_WaveformTimerConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 1750 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 1751 HRTIM_TimerCfgTypeDef * pTimerCfg)
bogdanm 0:9b334a45a8ff 1752 {
bogdanm 0:9b334a45a8ff 1753 uint32_t HRTIM_timcr;
bogdanm 0:9b334a45a8ff 1754 uint32_t HRTIM_timfltr;
bogdanm 0:9b334a45a8ff 1755 uint32_t HRTIM_timoutr;
bogdanm 0:9b334a45a8ff 1756 uint32_t HRTIM_timrstr;
bogdanm 0:9b334a45a8ff 1757
bogdanm 0:9b334a45a8ff 1758 /* Check parameters */
bogdanm 0:9b334a45a8ff 1759 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
bogdanm 0:9b334a45a8ff 1760 assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
bogdanm 0:9b334a45a8ff 1761 assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
bogdanm 0:9b334a45a8ff 1762 assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
bogdanm 0:9b334a45a8ff 1763 assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->DeadTimeInsertion));
bogdanm 0:9b334a45a8ff 1764 assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->DelayedProtectionMode));
bogdanm 0:9b334a45a8ff 1765 assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
bogdanm 0:9b334a45a8ff 1766 assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
bogdanm 0:9b334a45a8ff 1767 assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
bogdanm 0:9b334a45a8ff 1768
bogdanm 0:9b334a45a8ff 1769 /* Configure timing unit (Timer A to Timer E) */
bogdanm 0:9b334a45a8ff 1770 HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
bogdanm 0:9b334a45a8ff 1771 HRTIM_timfltr = HRTIMx->HRTIM_TIMERx[TimerIdx].FLTxR;
bogdanm 0:9b334a45a8ff 1772 HRTIM_timoutr = HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR;
bogdanm 0:9b334a45a8ff 1773 HRTIM_timrstr = HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR;
bogdanm 0:9b334a45a8ff 1774
bogdanm 0:9b334a45a8ff 1775 /* Set the push-pull mode */
bogdanm 0:9b334a45a8ff 1776 HRTIM_timcr &= ~(HRTIM_TIMCR_PSHPLL);
bogdanm 0:9b334a45a8ff 1777 HRTIM_timcr |= pTimerCfg->PushPull;
bogdanm 0:9b334a45a8ff 1778
bogdanm 0:9b334a45a8ff 1779 /* Enable/Disable registers update on timer counter reset */
bogdanm 0:9b334a45a8ff 1780 HRTIM_timcr &= ~(HRTIM_TIMCR_TRSTU);
bogdanm 0:9b334a45a8ff 1781 HRTIM_timcr |= pTimerCfg->ResetUpdate;
bogdanm 0:9b334a45a8ff 1782
bogdanm 0:9b334a45a8ff 1783 /* Set the timer update trigger */
bogdanm 0:9b334a45a8ff 1784 HRTIM_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
bogdanm 0:9b334a45a8ff 1785 HRTIM_timcr |= pTimerCfg->UpdateTrigger;
bogdanm 0:9b334a45a8ff 1786
bogdanm 0:9b334a45a8ff 1787 /* Enable/Disable the fault channel at timer level */
bogdanm 0:9b334a45a8ff 1788 HRTIM_timfltr &= ~(HRTIM_FLTR_FLTxEN);
bogdanm 0:9b334a45a8ff 1789 HRTIM_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
bogdanm 0:9b334a45a8ff 1790
bogdanm 0:9b334a45a8ff 1791 /* Lock/Unlock fault sources at timer level */
bogdanm 0:9b334a45a8ff 1792 HRTIM_timfltr &= ~(HRTIM_FLTR_FLTCLK);
bogdanm 0:9b334a45a8ff 1793 HRTIM_timfltr |= pTimerCfg->FaultLock;
bogdanm 0:9b334a45a8ff 1794
bogdanm 0:9b334a45a8ff 1795 /* Enable/Disable dead time insertion at timer level */
bogdanm 0:9b334a45a8ff 1796 HRTIM_timoutr &= ~(HRTIM_OUTR_DTEN);
bogdanm 0:9b334a45a8ff 1797 HRTIM_timoutr |= pTimerCfg->DeadTimeInsertion;
bogdanm 0:9b334a45a8ff 1798
bogdanm 0:9b334a45a8ff 1799 /* Enable/Disable delayed protection at timer level */
bogdanm 0:9b334a45a8ff 1800 HRTIM_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN);
bogdanm 0:9b334a45a8ff 1801 HRTIM_timoutr |= pTimerCfg->DelayedProtectionMode;
bogdanm 0:9b334a45a8ff 1802
bogdanm 0:9b334a45a8ff 1803 /* Set the timer counter reset trigger */
bogdanm 0:9b334a45a8ff 1804 HRTIM_timrstr = pTimerCfg->ResetTrigger;
bogdanm 0:9b334a45a8ff 1805
bogdanm 0:9b334a45a8ff 1806 /* Update the HRTIMx registers */
bogdanm 0:9b334a45a8ff 1807 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
bogdanm 0:9b334a45a8ff 1808 HRTIMx->HRTIM_TIMERx[TimerIdx].FLTxR = HRTIM_timfltr;
bogdanm 0:9b334a45a8ff 1809 HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR = HRTIM_timoutr;
bogdanm 0:9b334a45a8ff 1810 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_timrstr;
bogdanm 0:9b334a45a8ff 1811 }
bogdanm 0:9b334a45a8ff 1812
bogdanm 0:9b334a45a8ff 1813 /**
bogdanm 0:9b334a45a8ff 1814 * @brief Configures the compare unit of a timer operating in waveform mode
bogdanm 0:9b334a45a8ff 1815 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 1816 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 1817 * 0xFF for master timer
bogdanm 0:9b334a45a8ff 1818 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1819 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 1820 * @param CompareUnit: Compare unit to configure
bogdanm 0:9b334a45a8ff 1821 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1822 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
bogdanm 0:9b334a45a8ff 1823 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
bogdanm 0:9b334a45a8ff 1824 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
bogdanm 0:9b334a45a8ff 1825 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
bogdanm 0:9b334a45a8ff 1826 * @param pCompareCfg: pointer to the compare unit configuration structure
bogdanm 0:9b334a45a8ff 1827 * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
bogdanm 0:9b334a45a8ff 1828 * application has to configure separately the capture unit. Capture unit
bogdanm 0:9b334a45a8ff 1829 * to configure in that case depends on the compare unit auto delayed mode
bogdanm 0:9b334a45a8ff 1830 * is applied to (see below):
bogdanm 0:9b334a45a8ff 1831 * Auto delayed on output compare 2: capture unit 1 must be configured
bogdanm 0:9b334a45a8ff 1832 * Auto delayed on output compare 4: capture unit 2 must be configured
bogdanm 0:9b334a45a8ff 1833 * @retval None
bogdanm 0:9b334a45a8ff 1834 */
bogdanm 0:9b334a45a8ff 1835 void HRTIM_WaveformCompareConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 1836 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 1837 uint32_t CompareUnit,
bogdanm 0:9b334a45a8ff 1838 HRTIM_CompareCfgTypeDef* pCompareCfg)
bogdanm 0:9b334a45a8ff 1839 {
bogdanm 0:9b334a45a8ff 1840 uint32_t HRTIM_timcr;
bogdanm 0:9b334a45a8ff 1841
bogdanm 0:9b334a45a8ff 1842 /* Check parameters */
bogdanm 0:9b334a45a8ff 1843 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
bogdanm 0:9b334a45a8ff 1844 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
bogdanm 0:9b334a45a8ff 1845
bogdanm 0:9b334a45a8ff 1846 /* Configure the compare unit */
bogdanm 0:9b334a45a8ff 1847 switch (CompareUnit)
bogdanm 0:9b334a45a8ff 1848 {
bogdanm 0:9b334a45a8ff 1849 case HRTIM_COMPAREUNIT_1:
bogdanm 0:9b334a45a8ff 1850 {
bogdanm 0:9b334a45a8ff 1851 /* Set the compare value */
bogdanm 0:9b334a45a8ff 1852 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
bogdanm 0:9b334a45a8ff 1853 }
bogdanm 0:9b334a45a8ff 1854 break;
bogdanm 0:9b334a45a8ff 1855 case HRTIM_COMPAREUNIT_2:
bogdanm 0:9b334a45a8ff 1856 {
bogdanm 0:9b334a45a8ff 1857 /* Set the compare value */
bogdanm 0:9b334a45a8ff 1858 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
bogdanm 0:9b334a45a8ff 1859
bogdanm 0:9b334a45a8ff 1860 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
bogdanm 0:9b334a45a8ff 1861 {
bogdanm 0:9b334a45a8ff 1862 /* Configure auto-delayed mode */
bogdanm 0:9b334a45a8ff 1863 HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
bogdanm 0:9b334a45a8ff 1864 HRTIM_timcr &= ~HRTIM_TIMCR_DELCMP2;
bogdanm 0:9b334a45a8ff 1865 HRTIM_timcr |= pCompareCfg->AutoDelayedMode;
bogdanm 0:9b334a45a8ff 1866 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
bogdanm 0:9b334a45a8ff 1867
bogdanm 0:9b334a45a8ff 1868 /* Set the compare value for timeout compare unit (if any) */
bogdanm 0:9b334a45a8ff 1869 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
bogdanm 0:9b334a45a8ff 1870 {
bogdanm 0:9b334a45a8ff 1871 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
bogdanm 0:9b334a45a8ff 1872 }
bogdanm 0:9b334a45a8ff 1873 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
bogdanm 0:9b334a45a8ff 1874 {
bogdanm 0:9b334a45a8ff 1875 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
bogdanm 0:9b334a45a8ff 1876 }
bogdanm 0:9b334a45a8ff 1877 }
bogdanm 0:9b334a45a8ff 1878 }
bogdanm 0:9b334a45a8ff 1879 break;
bogdanm 0:9b334a45a8ff 1880 case HRTIM_COMPAREUNIT_3:
bogdanm 0:9b334a45a8ff 1881 {
bogdanm 0:9b334a45a8ff 1882 /* Set the compare value */
bogdanm 0:9b334a45a8ff 1883 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
bogdanm 0:9b334a45a8ff 1884 }
bogdanm 0:9b334a45a8ff 1885 break;
bogdanm 0:9b334a45a8ff 1886 case HRTIM_COMPAREUNIT_4:
bogdanm 0:9b334a45a8ff 1887 {
bogdanm 0:9b334a45a8ff 1888 /* Set the compare value */
bogdanm 0:9b334a45a8ff 1889 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
bogdanm 0:9b334a45a8ff 1890
bogdanm 0:9b334a45a8ff 1891 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
bogdanm 0:9b334a45a8ff 1892 {
bogdanm 0:9b334a45a8ff 1893 /* Configure auto-delayed mode */
bogdanm 0:9b334a45a8ff 1894 HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
bogdanm 0:9b334a45a8ff 1895 HRTIM_timcr &= ~HRTIM_TIMCR_DELCMP4;
bogdanm 0:9b334a45a8ff 1896 HRTIM_timcr |= (pCompareCfg->AutoDelayedMode << 2);
bogdanm 0:9b334a45a8ff 1897 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
bogdanm 0:9b334a45a8ff 1898
bogdanm 0:9b334a45a8ff 1899 /* Set the compare value for timeout compare unit (if any) */
bogdanm 0:9b334a45a8ff 1900 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
bogdanm 0:9b334a45a8ff 1901 {
bogdanm 0:9b334a45a8ff 1902 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
bogdanm 0:9b334a45a8ff 1903 }
bogdanm 0:9b334a45a8ff 1904 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
bogdanm 0:9b334a45a8ff 1905 {
bogdanm 0:9b334a45a8ff 1906 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
bogdanm 0:9b334a45a8ff 1907 }
bogdanm 0:9b334a45a8ff 1908 }
bogdanm 0:9b334a45a8ff 1909 }
bogdanm 0:9b334a45a8ff 1910 break;
bogdanm 0:9b334a45a8ff 1911 default:
bogdanm 0:9b334a45a8ff 1912 break;
bogdanm 0:9b334a45a8ff 1913 }
bogdanm 0:9b334a45a8ff 1914 }
bogdanm 0:9b334a45a8ff 1915
bogdanm 0:9b334a45a8ff 1916 /**
bogdanm 0:9b334a45a8ff 1917 * @brief Sets the HRTIMx Master Comparex Register value
bogdanm 0:9b334a45a8ff 1918 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 1919 * @param CompareUnit: Compare unit to configure
bogdanm 0:9b334a45a8ff 1920 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1921 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
bogdanm 0:9b334a45a8ff 1922 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
bogdanm 0:9b334a45a8ff 1923 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
bogdanm 0:9b334a45a8ff 1924 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
bogdanm 0:9b334a45a8ff 1925 * @param Compare: specifies the Comparex register new value
bogdanm 0:9b334a45a8ff 1926 * @retval None
bogdanm 0:9b334a45a8ff 1927 */
bogdanm 0:9b334a45a8ff 1928 void HRTIM_MasterSetCompare(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 1929 uint32_t CompareUnit,
bogdanm 0:9b334a45a8ff 1930 uint32_t Compare)
bogdanm 0:9b334a45a8ff 1931 {
bogdanm 0:9b334a45a8ff 1932 /* Check parameters */
bogdanm 0:9b334a45a8ff 1933 assert_param(IS_HRTIM_COMPAREUNIT(CompareUnit));
bogdanm 0:9b334a45a8ff 1934
bogdanm 0:9b334a45a8ff 1935 /* Configure the compare unit */
bogdanm 0:9b334a45a8ff 1936 switch (CompareUnit)
bogdanm 0:9b334a45a8ff 1937 {
bogdanm 0:9b334a45a8ff 1938 case HRTIM_COMPAREUNIT_1:
bogdanm 0:9b334a45a8ff 1939 {
bogdanm 0:9b334a45a8ff 1940 /* Set the compare value */
bogdanm 0:9b334a45a8ff 1941 HRTIMx->HRTIM_MASTER.MCMP1R = Compare;
bogdanm 0:9b334a45a8ff 1942 }
bogdanm 0:9b334a45a8ff 1943 break;
bogdanm 0:9b334a45a8ff 1944 case HRTIM_COMPAREUNIT_2:
bogdanm 0:9b334a45a8ff 1945 {
bogdanm 0:9b334a45a8ff 1946 /* Set the compare value */
bogdanm 0:9b334a45a8ff 1947 HRTIMx->HRTIM_MASTER.MCMP2R = Compare;
bogdanm 0:9b334a45a8ff 1948 }
bogdanm 0:9b334a45a8ff 1949 break;
bogdanm 0:9b334a45a8ff 1950 case HRTIM_COMPAREUNIT_3:
bogdanm 0:9b334a45a8ff 1951 {
bogdanm 0:9b334a45a8ff 1952 /* Set the compare value */
bogdanm 0:9b334a45a8ff 1953 HRTIMx->HRTIM_MASTER.MCMP3R = Compare;
bogdanm 0:9b334a45a8ff 1954 }
bogdanm 0:9b334a45a8ff 1955 break;
bogdanm 0:9b334a45a8ff 1956 case HRTIM_COMPAREUNIT_4:
bogdanm 0:9b334a45a8ff 1957 {
bogdanm 0:9b334a45a8ff 1958 /* Set the compare value */
bogdanm 0:9b334a45a8ff 1959 HRTIMx->HRTIM_MASTER.MCMP4R = Compare;
bogdanm 0:9b334a45a8ff 1960 }
bogdanm 0:9b334a45a8ff 1961 break;
bogdanm 0:9b334a45a8ff 1962 default:
bogdanm 0:9b334a45a8ff 1963 break;
bogdanm 0:9b334a45a8ff 1964 }
bogdanm 0:9b334a45a8ff 1965 }
bogdanm 0:9b334a45a8ff 1966 /**
bogdanm 0:9b334a45a8ff 1967 * @brief Configures the capture unit of a timer operating in waveform mode
bogdanm 0:9b334a45a8ff 1968 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 1969 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 1970 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1971 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 1972 * @param CaptureChannel: Capture unit to configure
bogdanm 0:9b334a45a8ff 1973 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1974 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
bogdanm 0:9b334a45a8ff 1975 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
bogdanm 0:9b334a45a8ff 1976 * @param pCaptureCfg: pointer to the compare unit configuration structure
bogdanm 0:9b334a45a8ff 1977 * @retval None
bogdanm 0:9b334a45a8ff 1978 */
bogdanm 0:9b334a45a8ff 1979 void HRTIM_WaveformCaptureConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 1980 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 1981 uint32_t CaptureUnit,
bogdanm 0:9b334a45a8ff 1982 HRTIM_CaptureCfgTypeDef* pCaptureCfg)
bogdanm 0:9b334a45a8ff 1983 {
bogdanm 0:9b334a45a8ff 1984 /* Configure the capture unit */
bogdanm 0:9b334a45a8ff 1985 switch (CaptureUnit)
bogdanm 0:9b334a45a8ff 1986 {
bogdanm 0:9b334a45a8ff 1987 case HRTIM_CAPTUREUNIT_1:
bogdanm 0:9b334a45a8ff 1988 {
bogdanm 0:9b334a45a8ff 1989 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = pCaptureCfg->Trigger;
bogdanm 0:9b334a45a8ff 1990 }
bogdanm 0:9b334a45a8ff 1991 break;
bogdanm 0:9b334a45a8ff 1992 case HRTIM_CAPTUREUNIT_2:
bogdanm 0:9b334a45a8ff 1993 {
bogdanm 0:9b334a45a8ff 1994 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = pCaptureCfg->Trigger;
bogdanm 0:9b334a45a8ff 1995 }
bogdanm 0:9b334a45a8ff 1996 break;
bogdanm 0:9b334a45a8ff 1997 default:
bogdanm 0:9b334a45a8ff 1998 break;
bogdanm 0:9b334a45a8ff 1999 }
bogdanm 0:9b334a45a8ff 2000 }
bogdanm 0:9b334a45a8ff 2001
bogdanm 0:9b334a45a8ff 2002 /**
bogdanm 0:9b334a45a8ff 2003 * @brief Configures the output of a timer operating in waveform mode
bogdanm 0:9b334a45a8ff 2004 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 2005 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 2006 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2007 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 2008 * @param Output: Timer output
bogdanm 0:9b334a45a8ff 2009 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2010 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
bogdanm 0:9b334a45a8ff 2011 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
bogdanm 0:9b334a45a8ff 2012 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
bogdanm 0:9b334a45a8ff 2013 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
bogdanm 0:9b334a45a8ff 2014 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
bogdanm 0:9b334a45a8ff 2015 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
bogdanm 0:9b334a45a8ff 2016 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
bogdanm 0:9b334a45a8ff 2017 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
bogdanm 0:9b334a45a8ff 2018 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
bogdanm 0:9b334a45a8ff 2019 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
bogdanm 0:9b334a45a8ff 2020 * @param pOutputCfg: pointer to the timer output configuration structure
bogdanm 0:9b334a45a8ff 2021 * @retval None
bogdanm 0:9b334a45a8ff 2022 */
bogdanm 0:9b334a45a8ff 2023 void HRTIM_WaveformOutputConfig(HRTIM_TypeDef * HRTIM_,
bogdanm 0:9b334a45a8ff 2024 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 2025 uint32_t Output,
bogdanm 0:9b334a45a8ff 2026 HRTIM_OutputCfgTypeDef * pOutputCfg)
bogdanm 0:9b334a45a8ff 2027 {
bogdanm 0:9b334a45a8ff 2028 /* Check parameters */
bogdanm 0:9b334a45a8ff 2029 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
bogdanm 0:9b334a45a8ff 2030 assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
bogdanm 0:9b334a45a8ff 2031 assert_param(IS_HRTIM_OUTPUTIDLESTATE(pOutputCfg->IdleState));
bogdanm 0:9b334a45a8ff 2032 assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
bogdanm 0:9b334a45a8ff 2033 assert_param(IS_HRTIM_OUTPUTFAULTSTATE(pOutputCfg->FaultState));
bogdanm 0:9b334a45a8ff 2034 assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
bogdanm 0:9b334a45a8ff 2035 assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
bogdanm 0:9b334a45a8ff 2036
bogdanm 0:9b334a45a8ff 2037 /* Configure the timer output */
bogdanm 0:9b334a45a8ff 2038 HRTIM_OutputConfig(HRTIM_, TimerIdx, Output, pOutputCfg);
bogdanm 0:9b334a45a8ff 2039 }
bogdanm 0:9b334a45a8ff 2040
bogdanm 0:9b334a45a8ff 2041 /**
bogdanm 0:9b334a45a8ff 2042 * @brief Configures the event filtering capabilities of a timer (blanking, windowing)
bogdanm 0:9b334a45a8ff 2043 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 2044 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 2045 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2046 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 2047 * @param Event: external event for which timer event filtering must be configured
bogdanm 0:9b334a45a8ff 2048 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2049 * @arg HRTIM_EVENT_1: External event 1
bogdanm 0:9b334a45a8ff 2050 * @arg HRTIM_EVENT_2: External event 2
bogdanm 0:9b334a45a8ff 2051 * @arg HRTIM_EVENT_3: External event 3
bogdanm 0:9b334a45a8ff 2052 * @arg HRTIM_EVENT_4: External event 4
bogdanm 0:9b334a45a8ff 2053 * @arg HRTIM_EVENT_5: External event 5
bogdanm 0:9b334a45a8ff 2054 * @arg HRTIM_EVENT_6: External event 6
bogdanm 0:9b334a45a8ff 2055 * @arg HRTIM_EVENT_7: External event 7
bogdanm 0:9b334a45a8ff 2056 * @arg HRTIM_EVENT_8: External event 8
bogdanm 0:9b334a45a8ff 2057 * @arg HRTIM_EVENT_9: External event 9
bogdanm 0:9b334a45a8ff 2058 * @arg HRTIM_EVENT_10: External event 10
bogdanm 0:9b334a45a8ff 2059 * @param pTimerEventFilteringCfg: pointer to the timer event filtering configuration structure
bogdanm 0:9b334a45a8ff 2060 * @retval None
bogdanm 0:9b334a45a8ff 2061 */
bogdanm 0:9b334a45a8ff 2062 void HRTIM_TimerEventFilteringConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 2063 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 2064 uint32_t Event,
bogdanm 0:9b334a45a8ff 2065 HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
bogdanm 0:9b334a45a8ff 2066 {
bogdanm 0:9b334a45a8ff 2067 uint32_t HRTIM_eefr;
bogdanm 0:9b334a45a8ff 2068
bogdanm 0:9b334a45a8ff 2069 /* Check parameters */
bogdanm 0:9b334a45a8ff 2070 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
bogdanm 0:9b334a45a8ff 2071 assert_param(IS_HRTIM_EVENT(Event));
bogdanm 0:9b334a45a8ff 2072 assert_param(IS_HRTIM_TIMEVENTFILTER(pTimerEventFilteringCfg->Filter));
bogdanm 0:9b334a45a8ff 2073 assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
bogdanm 0:9b334a45a8ff 2074
bogdanm 0:9b334a45a8ff 2075 /* Configure timer event filtering capabilities */
bogdanm 0:9b334a45a8ff 2076 switch (Event)
bogdanm 0:9b334a45a8ff 2077 {
bogdanm 0:9b334a45a8ff 2078 case HRTIM_TIMEVENTFILTER_NONE:
bogdanm 0:9b334a45a8ff 2079 {
bogdanm 0:9b334a45a8ff 2080 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = 0;
bogdanm 0:9b334a45a8ff 2081 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = 0;
bogdanm 0:9b334a45a8ff 2082 }
bogdanm 0:9b334a45a8ff 2083 break;
bogdanm 0:9b334a45a8ff 2084 case HRTIM_EVENT_1:
bogdanm 0:9b334a45a8ff 2085 {
bogdanm 0:9b334a45a8ff 2086 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
bogdanm 0:9b334a45a8ff 2087 HRTIM_eefr &= ~(HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH);
bogdanm 0:9b334a45a8ff 2088 HRTIM_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
bogdanm 0:9b334a45a8ff 2089 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
bogdanm 0:9b334a45a8ff 2090 }
bogdanm 0:9b334a45a8ff 2091 break;
bogdanm 0:9b334a45a8ff 2092 case HRTIM_EVENT_2:
bogdanm 0:9b334a45a8ff 2093 {
bogdanm 0:9b334a45a8ff 2094 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
bogdanm 0:9b334a45a8ff 2095 HRTIM_eefr &= ~(HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH);
bogdanm 0:9b334a45a8ff 2096 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6);
bogdanm 0:9b334a45a8ff 2097 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
bogdanm 0:9b334a45a8ff 2098 }
bogdanm 0:9b334a45a8ff 2099 break;
bogdanm 0:9b334a45a8ff 2100 case HRTIM_EVENT_3:
bogdanm 0:9b334a45a8ff 2101 {
bogdanm 0:9b334a45a8ff 2102 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
bogdanm 0:9b334a45a8ff 2103 HRTIM_eefr &= ~(HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH);
bogdanm 0:9b334a45a8ff 2104 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12);
bogdanm 0:9b334a45a8ff 2105 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
bogdanm 0:9b334a45a8ff 2106 }
bogdanm 0:9b334a45a8ff 2107 break;
bogdanm 0:9b334a45a8ff 2108 case HRTIM_EVENT_4:
bogdanm 0:9b334a45a8ff 2109 {
bogdanm 0:9b334a45a8ff 2110 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
bogdanm 0:9b334a45a8ff 2111 HRTIM_eefr &= ~(HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH);
bogdanm 0:9b334a45a8ff 2112 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18);
bogdanm 0:9b334a45a8ff 2113 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
bogdanm 0:9b334a45a8ff 2114 }
bogdanm 0:9b334a45a8ff 2115 break;
bogdanm 0:9b334a45a8ff 2116 case HRTIM_EVENT_5:
bogdanm 0:9b334a45a8ff 2117 {
bogdanm 0:9b334a45a8ff 2118 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
bogdanm 0:9b334a45a8ff 2119 HRTIM_eefr &= ~(HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH);
bogdanm 0:9b334a45a8ff 2120 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24);
bogdanm 0:9b334a45a8ff 2121 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
bogdanm 0:9b334a45a8ff 2122 }
bogdanm 0:9b334a45a8ff 2123 break;
bogdanm 0:9b334a45a8ff 2124 case HRTIM_EVENT_6:
bogdanm 0:9b334a45a8ff 2125 {
bogdanm 0:9b334a45a8ff 2126 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
bogdanm 0:9b334a45a8ff 2127 HRTIM_eefr &= ~(HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH);
bogdanm 0:9b334a45a8ff 2128 HRTIM_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
bogdanm 0:9b334a45a8ff 2129 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
bogdanm 0:9b334a45a8ff 2130 }
bogdanm 0:9b334a45a8ff 2131 break;
bogdanm 0:9b334a45a8ff 2132 case HRTIM_EVENT_7:
bogdanm 0:9b334a45a8ff 2133 {
bogdanm 0:9b334a45a8ff 2134 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
bogdanm 0:9b334a45a8ff 2135 HRTIM_eefr &= ~(HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH);
bogdanm 0:9b334a45a8ff 2136 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6);
bogdanm 0:9b334a45a8ff 2137 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
bogdanm 0:9b334a45a8ff 2138 }
bogdanm 0:9b334a45a8ff 2139 break;
bogdanm 0:9b334a45a8ff 2140 case HRTIM_EVENT_8:
bogdanm 0:9b334a45a8ff 2141 {
bogdanm 0:9b334a45a8ff 2142 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
bogdanm 0:9b334a45a8ff 2143 HRTIM_eefr &= ~(HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH);
bogdanm 0:9b334a45a8ff 2144 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12);
bogdanm 0:9b334a45a8ff 2145 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
bogdanm 0:9b334a45a8ff 2146 }
bogdanm 0:9b334a45a8ff 2147 break;
bogdanm 0:9b334a45a8ff 2148 case HRTIM_EVENT_9:
bogdanm 0:9b334a45a8ff 2149 {
bogdanm 0:9b334a45a8ff 2150 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
bogdanm 0:9b334a45a8ff 2151 HRTIM_eefr &= ~(HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH);
bogdanm 0:9b334a45a8ff 2152 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18);
bogdanm 0:9b334a45a8ff 2153 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
bogdanm 0:9b334a45a8ff 2154 }
bogdanm 0:9b334a45a8ff 2155 break;
bogdanm 0:9b334a45a8ff 2156 case HRTIM_EVENT_10:
bogdanm 0:9b334a45a8ff 2157 {
bogdanm 0:9b334a45a8ff 2158 HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
bogdanm 0:9b334a45a8ff 2159 HRTIM_eefr &= ~(HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH);
bogdanm 0:9b334a45a8ff 2160 HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24);
bogdanm 0:9b334a45a8ff 2161 HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
bogdanm 0:9b334a45a8ff 2162 }
bogdanm 0:9b334a45a8ff 2163 break;
bogdanm 0:9b334a45a8ff 2164 default:
bogdanm 0:9b334a45a8ff 2165 break;
bogdanm 0:9b334a45a8ff 2166 }
bogdanm 0:9b334a45a8ff 2167 }
bogdanm 0:9b334a45a8ff 2168
bogdanm 0:9b334a45a8ff 2169 /**
bogdanm 0:9b334a45a8ff 2170 * @brief Configures the dead time insertion feature for a timer
bogdanm 0:9b334a45a8ff 2171 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 2172 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 2173 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2174 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 2175 * @param pDeadTimeCfg: pointer to the dead time insertion configuration structure
bogdanm 0:9b334a45a8ff 2176 * @retval None
bogdanm 0:9b334a45a8ff 2177 */
bogdanm 0:9b334a45a8ff 2178 void HRTIM_DeadTimeConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 2179 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 2180 HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
bogdanm 0:9b334a45a8ff 2181 {
bogdanm 0:9b334a45a8ff 2182 uint32_t HRTIM_dtr;
bogdanm 0:9b334a45a8ff 2183
bogdanm 0:9b334a45a8ff 2184 /* Check parameters */
bogdanm 0:9b334a45a8ff 2185 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
bogdanm 0:9b334a45a8ff 2186 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
bogdanm 0:9b334a45a8ff 2187 assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
bogdanm 0:9b334a45a8ff 2188 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
bogdanm 0:9b334a45a8ff 2189 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
bogdanm 0:9b334a45a8ff 2190 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
bogdanm 0:9b334a45a8ff 2191 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
bogdanm 0:9b334a45a8ff 2192
bogdanm 0:9b334a45a8ff 2193 HRTIM_dtr = HRTIMx->HRTIM_TIMERx[TimerIdx].DTxR;
bogdanm 0:9b334a45a8ff 2194
bogdanm 0:9b334a45a8ff 2195 /* Clear timer dead times configuration */
bogdanm 0:9b334a45a8ff 2196 HRTIM_dtr &= ~(HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
bogdanm 0:9b334a45a8ff 2197 HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_SDTF |
bogdanm 0:9b334a45a8ff 2198 HRTIM_DTR_SDTR | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK);
bogdanm 0:9b334a45a8ff 2199
bogdanm 0:9b334a45a8ff 2200 /* Set timer dead times configuration */
bogdanm 0:9b334a45a8ff 2201 HRTIM_dtr |= (pDeadTimeCfg->Prescaler << 10);
bogdanm 0:9b334a45a8ff 2202 HRTIM_dtr |= pDeadTimeCfg->RisingValue;
bogdanm 0:9b334a45a8ff 2203 HRTIM_dtr |= pDeadTimeCfg->RisingSign;
bogdanm 0:9b334a45a8ff 2204 HRTIM_dtr |= pDeadTimeCfg->RisingSignLock;
bogdanm 0:9b334a45a8ff 2205 HRTIM_dtr |= pDeadTimeCfg->RisingLock;
bogdanm 0:9b334a45a8ff 2206 HRTIM_dtr |= (pDeadTimeCfg->FallingValue << 16);
bogdanm 0:9b334a45a8ff 2207 HRTIM_dtr |= pDeadTimeCfg->FallingSign;
bogdanm 0:9b334a45a8ff 2208 HRTIM_dtr |= pDeadTimeCfg->FallingSignLock;
bogdanm 0:9b334a45a8ff 2209 HRTIM_dtr |= pDeadTimeCfg->FallingLock;
bogdanm 0:9b334a45a8ff 2210
bogdanm 0:9b334a45a8ff 2211 /* Update the HRTIMx registers */
bogdanm 0:9b334a45a8ff 2212 HRTIMx->HRTIM_TIMERx[TimerIdx].DTxR = HRTIM_dtr;
bogdanm 0:9b334a45a8ff 2213 }
bogdanm 0:9b334a45a8ff 2214
bogdanm 0:9b334a45a8ff 2215 /**
bogdanm 0:9b334a45a8ff 2216 * @brief Configures the chopper mode feature for a timer
bogdanm 0:9b334a45a8ff 2217 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 2218 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 2219 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2220 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 2221 * @param pChopperModeCfg: pointer to the chopper mode configuration structure
bogdanm 0:9b334a45a8ff 2222 * @retval None
bogdanm 0:9b334a45a8ff 2223 */
bogdanm 0:9b334a45a8ff 2224 void HRTIM_ChopperModeConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 2225 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 2226 HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
bogdanm 0:9b334a45a8ff 2227 {
bogdanm 0:9b334a45a8ff 2228 uint32_t HRTIM_chpr;
bogdanm 0:9b334a45a8ff 2229
bogdanm 0:9b334a45a8ff 2230 /* Check parameters */
bogdanm 0:9b334a45a8ff 2231 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
bogdanm 0:9b334a45a8ff 2232
bogdanm 0:9b334a45a8ff 2233 HRTIM_chpr = HRTIMx->HRTIM_TIMERx[TimerIdx].CHPxR;
bogdanm 0:9b334a45a8ff 2234
bogdanm 0:9b334a45a8ff 2235 /* Clear timer chopper mode configuration */
bogdanm 0:9b334a45a8ff 2236 HRTIM_chpr &= ~(HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW);
bogdanm 0:9b334a45a8ff 2237
bogdanm 0:9b334a45a8ff 2238 /* Set timer chopper mode configuration */
bogdanm 0:9b334a45a8ff 2239 HRTIM_chpr |= pChopperModeCfg->CarrierFreq;
bogdanm 0:9b334a45a8ff 2240 HRTIM_chpr |= (pChopperModeCfg->DutyCycle << 4);
bogdanm 0:9b334a45a8ff 2241 HRTIM_chpr |= (pChopperModeCfg->StartPulse << 7);
bogdanm 0:9b334a45a8ff 2242
bogdanm 0:9b334a45a8ff 2243 /* Update the HRTIMx registers */
bogdanm 0:9b334a45a8ff 2244 HRTIMx->HRTIM_TIMERx[TimerIdx].CHPxR = HRTIM_chpr;
bogdanm 0:9b334a45a8ff 2245 }
bogdanm 0:9b334a45a8ff 2246
bogdanm 0:9b334a45a8ff 2247 /**
bogdanm 0:9b334a45a8ff 2248 * @brief Configures the burst DMA controller for a timer
bogdanm 0:9b334a45a8ff 2249 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 2250 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 2251 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2252 * @arg 0x5 for master timer
bogdanm 0:9b334a45a8ff 2253 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 2254 * @param RegistersToUpdate: registers to be written by DMA
bogdanm 0:9b334a45a8ff 2255 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 2256 * @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
bogdanm 0:9b334a45a8ff 2257 * @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
bogdanm 0:9b334a45a8ff 2258 * @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
bogdanm 0:9b334a45a8ff 2259 * @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
bogdanm 0:9b334a45a8ff 2260 * @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
bogdanm 0:9b334a45a8ff 2261 * @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
bogdanm 0:9b334a45a8ff 2262 * @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
bogdanm 0:9b334a45a8ff 2263 * @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
bogdanm 0:9b334a45a8ff 2264 * @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
bogdanm 0:9b334a45a8ff 2265 * @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
bogdanm 0:9b334a45a8ff 2266 * @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
bogdanm 0:9b334a45a8ff 2267 * @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
bogdanm 0:9b334a45a8ff 2268 * @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
bogdanm 0:9b334a45a8ff 2269 * @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
bogdanm 0:9b334a45a8ff 2270 * @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
bogdanm 0:9b334a45a8ff 2271 * @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
bogdanm 0:9b334a45a8ff 2272 * @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
bogdanm 0:9b334a45a8ff 2273 * @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
bogdanm 0:9b334a45a8ff 2274 * @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
bogdanm 0:9b334a45a8ff 2275 * @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
bogdanm 0:9b334a45a8ff 2276 * @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
bogdanm 0:9b334a45a8ff 2277 * @retval None
bogdanm 0:9b334a45a8ff 2278 */
bogdanm 0:9b334a45a8ff 2279 void HRTIM_BurstDMAConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 2280 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 2281 uint32_t RegistersToUpdate)
bogdanm 0:9b334a45a8ff 2282 {
bogdanm 0:9b334a45a8ff 2283 /* Check parameters */
bogdanm 0:9b334a45a8ff 2284 assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
bogdanm 0:9b334a45a8ff 2285
bogdanm 0:9b334a45a8ff 2286 /* Set the burst DMA timer update register */
bogdanm 0:9b334a45a8ff 2287 switch (TimerIdx)
bogdanm 0:9b334a45a8ff 2288 {
bogdanm 0:9b334a45a8ff 2289 case HRTIM_TIMERINDEX_TIMER_A:
bogdanm 0:9b334a45a8ff 2290 {
bogdanm 0:9b334a45a8ff 2291 HRTIMx->HRTIM_COMMON.BDTAUPR = RegistersToUpdate;
bogdanm 0:9b334a45a8ff 2292 }
bogdanm 0:9b334a45a8ff 2293 break;
bogdanm 0:9b334a45a8ff 2294 case HRTIM_TIMERINDEX_TIMER_B:
bogdanm 0:9b334a45a8ff 2295 {
bogdanm 0:9b334a45a8ff 2296 HRTIMx->HRTIM_COMMON.BDTBUPR = RegistersToUpdate;
bogdanm 0:9b334a45a8ff 2297 }
bogdanm 0:9b334a45a8ff 2298 break;
bogdanm 0:9b334a45a8ff 2299 case HRTIM_TIMERINDEX_TIMER_C:
bogdanm 0:9b334a45a8ff 2300 {
bogdanm 0:9b334a45a8ff 2301 HRTIMx->HRTIM_COMMON.BDTCUPR = RegistersToUpdate;
bogdanm 0:9b334a45a8ff 2302 }
bogdanm 0:9b334a45a8ff 2303 break;
bogdanm 0:9b334a45a8ff 2304 case HRTIM_TIMERINDEX_TIMER_D:
bogdanm 0:9b334a45a8ff 2305 {
bogdanm 0:9b334a45a8ff 2306 HRTIMx->HRTIM_COMMON.BDTDUPR = RegistersToUpdate;
bogdanm 0:9b334a45a8ff 2307 }
bogdanm 0:9b334a45a8ff 2308 break;
bogdanm 0:9b334a45a8ff 2309 case HRTIM_TIMERINDEX_TIMER_E:
bogdanm 0:9b334a45a8ff 2310 {
bogdanm 0:9b334a45a8ff 2311 HRTIMx->HRTIM_COMMON.BDTEUPR = RegistersToUpdate;
bogdanm 0:9b334a45a8ff 2312 }
bogdanm 0:9b334a45a8ff 2313 break;
bogdanm 0:9b334a45a8ff 2314 case HRTIM_TIMERINDEX_MASTER:
bogdanm 0:9b334a45a8ff 2315 {
bogdanm 0:9b334a45a8ff 2316 HRTIMx->HRTIM_COMMON.BDMUPDR = RegistersToUpdate;
bogdanm 0:9b334a45a8ff 2317 }
bogdanm 0:9b334a45a8ff 2318 break;
bogdanm 0:9b334a45a8ff 2319 default:
bogdanm 0:9b334a45a8ff 2320 break;
bogdanm 0:9b334a45a8ff 2321 }
bogdanm 0:9b334a45a8ff 2322 }
bogdanm 0:9b334a45a8ff 2323
bogdanm 0:9b334a45a8ff 2324 /**
bogdanm 0:9b334a45a8ff 2325 * @brief Configures the external input/output synchronization of the HRTIMx
bogdanm 0:9b334a45a8ff 2326 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 2327 * @param pSynchroCfg: pointer to the input/output synchronization configuration structure
bogdanm 0:9b334a45a8ff 2328 * @retval None
bogdanm 0:9b334a45a8ff 2329 */
bogdanm 0:9b334a45a8ff 2330 void HRTIM_SynchronizationConfig(HRTIM_TypeDef *HRTIMx, HRTIM_SynchroCfgTypeDef * pSynchroCfg)
bogdanm 0:9b334a45a8ff 2331 {
bogdanm 0:9b334a45a8ff 2332 uint32_t HRTIM_mcr;
bogdanm 0:9b334a45a8ff 2333
bogdanm 0:9b334a45a8ff 2334 /* Check parameters */
bogdanm 0:9b334a45a8ff 2335 assert_param(IS_HRTIM_SYNCINPUTSOURCE(pSynchroCfg->SyncInputSource));
bogdanm 0:9b334a45a8ff 2336 assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(pSynchroCfg->SyncOutputSource));
bogdanm 0:9b334a45a8ff 2337 assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(pSynchroCfg->SyncOutputPolarity));
bogdanm 0:9b334a45a8ff 2338
bogdanm 0:9b334a45a8ff 2339 HRTIM_mcr = HRTIMx->HRTIM_MASTER.MCR;
bogdanm 0:9b334a45a8ff 2340
bogdanm 0:9b334a45a8ff 2341 /* Set the synchronization input source */
bogdanm 0:9b334a45a8ff 2342 HRTIM_mcr &= ~(HRTIM_MCR_SYNC_IN);
bogdanm 0:9b334a45a8ff 2343 HRTIM_mcr |= pSynchroCfg->SyncInputSource;
bogdanm 0:9b334a45a8ff 2344
bogdanm 0:9b334a45a8ff 2345 /* Set the event to be sent on the synchronization output */
bogdanm 0:9b334a45a8ff 2346 HRTIM_mcr &= ~(HRTIM_MCR_SYNC_SRC);
bogdanm 0:9b334a45a8ff 2347 HRTIM_mcr |= pSynchroCfg->SyncOutputSource;
bogdanm 0:9b334a45a8ff 2348
bogdanm 0:9b334a45a8ff 2349 /* Set the polarity of the synchronization output */
bogdanm 0:9b334a45a8ff 2350 HRTIM_mcr &= ~(HRTIM_MCR_SYNC_OUT);
bogdanm 0:9b334a45a8ff 2351 HRTIM_mcr |= pSynchroCfg->SyncOutputPolarity;
bogdanm 0:9b334a45a8ff 2352
bogdanm 0:9b334a45a8ff 2353 /* Update the HRTIMx registers */
bogdanm 0:9b334a45a8ff 2354 HRTIMx->HRTIM_MASTER.MCR = HRTIM_mcr;
bogdanm 0:9b334a45a8ff 2355 }
bogdanm 0:9b334a45a8ff 2356
bogdanm 0:9b334a45a8ff 2357 /**
bogdanm 0:9b334a45a8ff 2358 * @brief Configures the burst mode feature of the HRTIMx
bogdanm 0:9b334a45a8ff 2359 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 2360 * @param pBurstModeCfg: pointer to the burst mode configuration structure
bogdanm 0:9b334a45a8ff 2361 * @retval None
bogdanm 0:9b334a45a8ff 2362 */
bogdanm 0:9b334a45a8ff 2363 void HRTIM_BurstModeConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 2364 HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
bogdanm 0:9b334a45a8ff 2365 {
bogdanm 0:9b334a45a8ff 2366 uint32_t HRTIM_bmcr;
bogdanm 0:9b334a45a8ff 2367
bogdanm 0:9b334a45a8ff 2368 /* Check parameters */
bogdanm 0:9b334a45a8ff 2369 assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
bogdanm 0:9b334a45a8ff 2370 assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
bogdanm 0:9b334a45a8ff 2371 assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
bogdanm 0:9b334a45a8ff 2372 assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
bogdanm 0:9b334a45a8ff 2373
bogdanm 0:9b334a45a8ff 2374 HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
bogdanm 0:9b334a45a8ff 2375
bogdanm 0:9b334a45a8ff 2376 /* Set the burst mode operating mode */
bogdanm 0:9b334a45a8ff 2377 HRTIM_bmcr &= ~(HRTIM_BMCR_BMOM);
bogdanm 0:9b334a45a8ff 2378 HRTIM_bmcr |= pBurstModeCfg->Mode;
bogdanm 0:9b334a45a8ff 2379
bogdanm 0:9b334a45a8ff 2380 /* Set the burst mode clock source */
bogdanm 0:9b334a45a8ff 2381 HRTIM_bmcr &= ~(HRTIM_BMCR_BMCLK);
bogdanm 0:9b334a45a8ff 2382 HRTIM_bmcr |= pBurstModeCfg->ClockSource;
bogdanm 0:9b334a45a8ff 2383
bogdanm 0:9b334a45a8ff 2384 /* Set the burst mode prescaler */
bogdanm 0:9b334a45a8ff 2385 HRTIM_bmcr &= ~(HRTIM_BMCR_BMPSC);
bogdanm 0:9b334a45a8ff 2386 HRTIM_bmcr |= pBurstModeCfg->Prescaler;
bogdanm 0:9b334a45a8ff 2387
bogdanm 0:9b334a45a8ff 2388 /* Enable/disable burst mode registers preload */
bogdanm 0:9b334a45a8ff 2389 HRTIM_bmcr &= ~(HRTIM_BMCR_BMPREN);
bogdanm 0:9b334a45a8ff 2390 HRTIM_bmcr |= pBurstModeCfg->PreloadEnable;
bogdanm 0:9b334a45a8ff 2391
bogdanm 0:9b334a45a8ff 2392 /* Set the burst mode trigger */
bogdanm 0:9b334a45a8ff 2393 HRTIMx->HRTIM_COMMON.BMTRGR = pBurstModeCfg->Trigger;
bogdanm 0:9b334a45a8ff 2394
bogdanm 0:9b334a45a8ff 2395 /* Set the burst mode compare value */
bogdanm 0:9b334a45a8ff 2396 HRTIMx->HRTIM_COMMON.BMCMPR = pBurstModeCfg->IdleDuration;
bogdanm 0:9b334a45a8ff 2397
bogdanm 0:9b334a45a8ff 2398 /* Set the burst mode period */
bogdanm 0:9b334a45a8ff 2399 HRTIMx->HRTIM_COMMON.BMPER = pBurstModeCfg->Period;
bogdanm 0:9b334a45a8ff 2400
bogdanm 0:9b334a45a8ff 2401 /* Update the HRTIMx registers */
bogdanm 0:9b334a45a8ff 2402 HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
bogdanm 0:9b334a45a8ff 2403 }
bogdanm 0:9b334a45a8ff 2404
bogdanm 0:9b334a45a8ff 2405 /**
bogdanm 0:9b334a45a8ff 2406 * @brief Configures the conditioning of an external event
bogdanm 0:9b334a45a8ff 2407 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 2408 * @param Event: external event to configure
bogdanm 0:9b334a45a8ff 2409 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2410 * @arg HRTIM_EVENT_1: External event 1
bogdanm 0:9b334a45a8ff 2411 * @arg HRTIM_EVENT_2: External event 2
bogdanm 0:9b334a45a8ff 2412 * @arg HRTIM_EVENT_3: External event 3
bogdanm 0:9b334a45a8ff 2413 * @arg HRTIM_EVENT_4: External event 4
bogdanm 0:9b334a45a8ff 2414 * @arg HRTIM_EVENT_5: External event 5
bogdanm 0:9b334a45a8ff 2415 * @arg HRTIM_EVENT_6: External event 6
bogdanm 0:9b334a45a8ff 2416 * @arg HRTIM_EVENT_7: External event 7
bogdanm 0:9b334a45a8ff 2417 * @arg HRTIM_EVENT_8: External event 8
bogdanm 0:9b334a45a8ff 2418 * @arg HRTIM_EVENT_9: External event 9
bogdanm 0:9b334a45a8ff 2419 * @arg HRTIM_EVENT_10: External event 10
bogdanm 0:9b334a45a8ff 2420 * @param pEventCfg: pointer to the event conditioning configuration structure
bogdanm 0:9b334a45a8ff 2421 * @retval None
bogdanm 0:9b334a45a8ff 2422 */
bogdanm 0:9b334a45a8ff 2423 void HRTIM_EventConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 2424 uint32_t Event,
bogdanm 0:9b334a45a8ff 2425 HRTIM_EventCfgTypeDef* pEventCfg)
bogdanm 0:9b334a45a8ff 2426 {
bogdanm 0:9b334a45a8ff 2427 /* Check parameters */
bogdanm 0:9b334a45a8ff 2428 assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
bogdanm 0:9b334a45a8ff 2429 assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Polarity));
bogdanm 0:9b334a45a8ff 2430 assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
bogdanm 0:9b334a45a8ff 2431 assert_param(IS_HRTIM_EVENTFASTMODE(pEventCfg->FastMode));
bogdanm 0:9b334a45a8ff 2432 assert_param(IS_HRTIM_EVENTFILTER(pEventCfg->Filter));
bogdanm 0:9b334a45a8ff 2433
bogdanm 0:9b334a45a8ff 2434 /* Configure the event channel */
bogdanm 0:9b334a45a8ff 2435 HRTIM_ExternalEventConfig(HRTIMx, Event, pEventCfg);
bogdanm 0:9b334a45a8ff 2436
bogdanm 0:9b334a45a8ff 2437 }
bogdanm 0:9b334a45a8ff 2438
bogdanm 0:9b334a45a8ff 2439 /**
bogdanm 0:9b334a45a8ff 2440 * @brief Configures the external event conditioning block prescaler
bogdanm 0:9b334a45a8ff 2441 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 2442 * @param Prescaler: Prescaler value
bogdanm 0:9b334a45a8ff 2443 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2444 * @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIMx
bogdanm 0:9b334a45a8ff 2445 * @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIMx / 2
bogdanm 0:9b334a45a8ff 2446 * @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIMx / 4
bogdanm 0:9b334a45a8ff 2447 * @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIMx / 8
bogdanm 0:9b334a45a8ff 2448 * @retval None
bogdanm 0:9b334a45a8ff 2449 */
bogdanm 0:9b334a45a8ff 2450 void HRTIM_EventPrescalerConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 2451 uint32_t Prescaler)
bogdanm 0:9b334a45a8ff 2452 {
bogdanm 0:9b334a45a8ff 2453 uint32_t HRTIM_eecr3;
bogdanm 0:9b334a45a8ff 2454
bogdanm 0:9b334a45a8ff 2455 /* Check parameters */
bogdanm 0:9b334a45a8ff 2456 assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
bogdanm 0:9b334a45a8ff 2457
bogdanm 0:9b334a45a8ff 2458 /* Set the external event prescaler */
bogdanm 0:9b334a45a8ff 2459 HRTIM_eecr3 = HRTIMx->HRTIM_COMMON.EECR3;
bogdanm 0:9b334a45a8ff 2460 HRTIM_eecr3 &= ~(HRTIM_EECR3_EEVSD);
bogdanm 0:9b334a45a8ff 2461 HRTIM_eecr3 |= Prescaler;
bogdanm 0:9b334a45a8ff 2462
bogdanm 0:9b334a45a8ff 2463 /* Update the HRTIMx registers */
bogdanm 0:9b334a45a8ff 2464 HRTIMx->HRTIM_COMMON.EECR3 = HRTIM_eecr3;
bogdanm 0:9b334a45a8ff 2465 }
bogdanm 0:9b334a45a8ff 2466
bogdanm 0:9b334a45a8ff 2467 /**
bogdanm 0:9b334a45a8ff 2468 * @brief Configures the conditioning of fault input
bogdanm 0:9b334a45a8ff 2469 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 2470 * @param Fault: fault input to configure
bogdanm 0:9b334a45a8ff 2471 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2472 * @arg HRTIM_FAULT_1: Fault input 1
bogdanm 0:9b334a45a8ff 2473 * @arg HRTIM_FAULT_2: Fault input 2
bogdanm 0:9b334a45a8ff 2474 * @arg HRTIM_FAULT_3: Fault input 3
bogdanm 0:9b334a45a8ff 2475 * @arg HRTIM_FAULT_4: Fault input 4
bogdanm 0:9b334a45a8ff 2476 * @arg HRTIM_FAULT_5: Fault input 5
bogdanm 0:9b334a45a8ff 2477 * @param pFaultCfg: pointer to the fault conditioning configuration structure
bogdanm 0:9b334a45a8ff 2478 * @retval None
bogdanm 0:9b334a45a8ff 2479 */
bogdanm 0:9b334a45a8ff 2480 void HRTIM_FaultConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 2481 HRTIM_FaultCfgTypeDef* pFaultCfg,
bogdanm 0:9b334a45a8ff 2482 uint32_t Fault)
bogdanm 0:9b334a45a8ff 2483 {
bogdanm 0:9b334a45a8ff 2484 uint32_t HRTIM_fltinr1;
bogdanm 0:9b334a45a8ff 2485 uint32_t HRTIM_fltinr2;
bogdanm 0:9b334a45a8ff 2486
bogdanm 0:9b334a45a8ff 2487 /* Check parameters */
bogdanm 0:9b334a45a8ff 2488 assert_param(IS_HRTIM_FAULT(Fault));
bogdanm 0:9b334a45a8ff 2489 assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
bogdanm 0:9b334a45a8ff 2490 assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
bogdanm 0:9b334a45a8ff 2491 assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
bogdanm 0:9b334a45a8ff 2492 assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
bogdanm 0:9b334a45a8ff 2493
bogdanm 0:9b334a45a8ff 2494 /* Configure fault channel */
bogdanm 0:9b334a45a8ff 2495 HRTIM_fltinr1 = HRTIMx->HRTIM_COMMON.FLTINxR1;
bogdanm 0:9b334a45a8ff 2496 HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2;
bogdanm 0:9b334a45a8ff 2497
bogdanm 0:9b334a45a8ff 2498 switch (Fault)
bogdanm 0:9b334a45a8ff 2499 {
bogdanm 0:9b334a45a8ff 2500 case HRTIM_FAULT_1:
bogdanm 0:9b334a45a8ff 2501 {
bogdanm 0:9b334a45a8ff 2502 HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
bogdanm 0:9b334a45a8ff 2503 HRTIM_fltinr1 |= pFaultCfg->Polarity;
bogdanm 0:9b334a45a8ff 2504 HRTIM_fltinr1 |= pFaultCfg->Source;
bogdanm 0:9b334a45a8ff 2505 HRTIM_fltinr1 |= pFaultCfg->Filter;
bogdanm 0:9b334a45a8ff 2506 HRTIM_fltinr1 |= pFaultCfg->Lock;
bogdanm 0:9b334a45a8ff 2507 }
bogdanm 0:9b334a45a8ff 2508 break;
bogdanm 0:9b334a45a8ff 2509 case HRTIM_FAULT_2:
bogdanm 0:9b334a45a8ff 2510 {
bogdanm 0:9b334a45a8ff 2511 HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
bogdanm 0:9b334a45a8ff 2512 HRTIM_fltinr1 |= (pFaultCfg->Polarity << 8);
bogdanm 0:9b334a45a8ff 2513 HRTIM_fltinr1 |= (pFaultCfg->Source << 8);
bogdanm 0:9b334a45a8ff 2514 HRTIM_fltinr1 |= (pFaultCfg->Filter << 8);
bogdanm 0:9b334a45a8ff 2515 HRTIM_fltinr1 |= (pFaultCfg->Lock << 8);
bogdanm 0:9b334a45a8ff 2516 }
bogdanm 0:9b334a45a8ff 2517 break;
bogdanm 0:9b334a45a8ff 2518 case HRTIM_FAULT_3:
bogdanm 0:9b334a45a8ff 2519 {
bogdanm 0:9b334a45a8ff 2520 HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
bogdanm 0:9b334a45a8ff 2521 HRTIM_fltinr1 |= (pFaultCfg->Polarity << 16);
bogdanm 0:9b334a45a8ff 2522 HRTIM_fltinr1 |= (pFaultCfg->Source << 16);
bogdanm 0:9b334a45a8ff 2523 HRTIM_fltinr1 |= (pFaultCfg->Filter << 16);
bogdanm 0:9b334a45a8ff 2524 HRTIM_fltinr1 |= (pFaultCfg->Lock << 16);
bogdanm 0:9b334a45a8ff 2525 }
bogdanm 0:9b334a45a8ff 2526 break;
bogdanm 0:9b334a45a8ff 2527 case HRTIM_FAULT_4:
bogdanm 0:9b334a45a8ff 2528 {
bogdanm 0:9b334a45a8ff 2529 HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
bogdanm 0:9b334a45a8ff 2530 HRTIM_fltinr1 |= (pFaultCfg->Polarity << 24);
bogdanm 0:9b334a45a8ff 2531 HRTIM_fltinr1 |= (pFaultCfg->Source << 24);
bogdanm 0:9b334a45a8ff 2532 HRTIM_fltinr1 |= (pFaultCfg->Filter << 24);
bogdanm 0:9b334a45a8ff 2533 HRTIM_fltinr1 |= (pFaultCfg->Lock << 24);
bogdanm 0:9b334a45a8ff 2534 }
bogdanm 0:9b334a45a8ff 2535 break;
bogdanm 0:9b334a45a8ff 2536 case HRTIM_FAULT_5:
bogdanm 0:9b334a45a8ff 2537 {
bogdanm 0:9b334a45a8ff 2538 HRTIM_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
bogdanm 0:9b334a45a8ff 2539 HRTIM_fltinr2 |= pFaultCfg->Polarity;
bogdanm 0:9b334a45a8ff 2540 HRTIM_fltinr2 |= pFaultCfg->Source;
bogdanm 0:9b334a45a8ff 2541 HRTIM_fltinr2 |= pFaultCfg->Filter;
bogdanm 0:9b334a45a8ff 2542 HRTIM_fltinr2 |= pFaultCfg->Lock;
bogdanm 0:9b334a45a8ff 2543 }
bogdanm 0:9b334a45a8ff 2544 break;
bogdanm 0:9b334a45a8ff 2545 default:
bogdanm 0:9b334a45a8ff 2546 break;
bogdanm 0:9b334a45a8ff 2547 }
bogdanm 0:9b334a45a8ff 2548
bogdanm 0:9b334a45a8ff 2549 /* Update the HRTIMx registers */
bogdanm 0:9b334a45a8ff 2550 HRTIMx->HRTIM_COMMON.FLTINxR1 = HRTIM_fltinr1;
bogdanm 0:9b334a45a8ff 2551 HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2;
bogdanm 0:9b334a45a8ff 2552 }
bogdanm 0:9b334a45a8ff 2553
bogdanm 0:9b334a45a8ff 2554 /**
bogdanm 0:9b334a45a8ff 2555 * @brief Configures the fault conditioning block prescaler
bogdanm 0:9b334a45a8ff 2556 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 2557 * @param Prescaler: Prescaler value
bogdanm 0:9b334a45a8ff 2558 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2559 * @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIMx
bogdanm 0:9b334a45a8ff 2560 * @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIMx / 2
bogdanm 0:9b334a45a8ff 2561 * @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIMx / 4
bogdanm 0:9b334a45a8ff 2562 * @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIMx / 8
bogdanm 0:9b334a45a8ff 2563 * @retval None
bogdanm 0:9b334a45a8ff 2564 */
bogdanm 0:9b334a45a8ff 2565 void HRTIM_FaultPrescalerConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 2566 uint32_t Prescaler)
bogdanm 0:9b334a45a8ff 2567 {
bogdanm 0:9b334a45a8ff 2568 uint32_t HRTIM_fltinr2;
bogdanm 0:9b334a45a8ff 2569
bogdanm 0:9b334a45a8ff 2570 /* Check parameters */
bogdanm 0:9b334a45a8ff 2571 assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
bogdanm 0:9b334a45a8ff 2572
bogdanm 0:9b334a45a8ff 2573 /* Set the external event prescaler */
bogdanm 0:9b334a45a8ff 2574 HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2;
bogdanm 0:9b334a45a8ff 2575 HRTIM_fltinr2 &= ~(HRTIM_FLTINR2_FLTSD);
bogdanm 0:9b334a45a8ff 2576 HRTIM_fltinr2 |= Prescaler;
bogdanm 0:9b334a45a8ff 2577
bogdanm 0:9b334a45a8ff 2578 /* Update the HRTIMx registers */
bogdanm 0:9b334a45a8ff 2579 HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2;
bogdanm 0:9b334a45a8ff 2580 }
bogdanm 0:9b334a45a8ff 2581
bogdanm 0:9b334a45a8ff 2582 /**
bogdanm 0:9b334a45a8ff 2583 * @brief Enables or disables the HRTIMx Fault mode.
bogdanm 0:9b334a45a8ff 2584 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 2585 * @param Fault: fault input to configure
bogdanm 0:9b334a45a8ff 2586 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2587 * @arg HRTIM_FAULT_1: Fault input 1
bogdanm 0:9b334a45a8ff 2588 * @arg HRTIM_FAULT_2: Fault input 2
bogdanm 0:9b334a45a8ff 2589 * @arg HRTIM_FAULT_3: Fault input 3
bogdanm 0:9b334a45a8ff 2590 * @arg HRTIM_FAULT_4: Fault input 4
bogdanm 0:9b334a45a8ff 2591 * @arg HRTIM_FAULT_5: Fault input 5
bogdanm 0:9b334a45a8ff 2592 * @param Enable: Fault mode controller enabling
bogdanm 0:9b334a45a8ff 2593 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2594 * @arg HRTIM_FAULT_ENABLED: Fault mode enabled
bogdanm 0:9b334a45a8ff 2595 * @arg HRTIM_FAULT_DISABLED: Fault mode disabled
bogdanm 0:9b334a45a8ff 2596 * @retval None
bogdanm 0:9b334a45a8ff 2597 */
bogdanm 0:9b334a45a8ff 2598 void HRTIM_FaultModeCtl(HRTIM_TypeDef * HRTIMx, uint32_t Fault, uint32_t Enable)
bogdanm 0:9b334a45a8ff 2599 {
bogdanm 0:9b334a45a8ff 2600 uint32_t HRTIM_fltinr1;
bogdanm 0:9b334a45a8ff 2601 uint32_t HRTIM_fltinr2;
bogdanm 0:9b334a45a8ff 2602
bogdanm 0:9b334a45a8ff 2603 /* Check parameters */
bogdanm 0:9b334a45a8ff 2604 assert_param(IS_HRTIM_FAULT(Fault));
bogdanm 0:9b334a45a8ff 2605 assert_param(IS_HRTIM_FAULTCTL(Enable));
bogdanm 0:9b334a45a8ff 2606
bogdanm 0:9b334a45a8ff 2607 /* Configure fault channel */
bogdanm 0:9b334a45a8ff 2608 HRTIM_fltinr1 = HRTIMx->HRTIM_COMMON.FLTINxR1;
bogdanm 0:9b334a45a8ff 2609 HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2;
bogdanm 0:9b334a45a8ff 2610
bogdanm 0:9b334a45a8ff 2611 switch (Fault)
bogdanm 0:9b334a45a8ff 2612 {
bogdanm 0:9b334a45a8ff 2613 case HRTIM_FAULT_1:
bogdanm 0:9b334a45a8ff 2614 {
bogdanm 0:9b334a45a8ff 2615 HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT1E;
bogdanm 0:9b334a45a8ff 2616 HRTIM_fltinr1 |= Enable;
bogdanm 0:9b334a45a8ff 2617 }
bogdanm 0:9b334a45a8ff 2618 break;
bogdanm 0:9b334a45a8ff 2619 case HRTIM_FAULT_2:
bogdanm 0:9b334a45a8ff 2620 {
bogdanm 0:9b334a45a8ff 2621 HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT2E;
bogdanm 0:9b334a45a8ff 2622 HRTIM_fltinr1 |= (Enable<< 8);
bogdanm 0:9b334a45a8ff 2623 }
bogdanm 0:9b334a45a8ff 2624 break;
bogdanm 0:9b334a45a8ff 2625 case HRTIM_FAULT_3:
bogdanm 0:9b334a45a8ff 2626 {
bogdanm 0:9b334a45a8ff 2627 HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT3E;
bogdanm 0:9b334a45a8ff 2628 HRTIM_fltinr1 |= (Enable << 16);
bogdanm 0:9b334a45a8ff 2629 }
bogdanm 0:9b334a45a8ff 2630 break;
bogdanm 0:9b334a45a8ff 2631 case HRTIM_FAULT_4:
bogdanm 0:9b334a45a8ff 2632 {
bogdanm 0:9b334a45a8ff 2633 HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT4E;
bogdanm 0:9b334a45a8ff 2634 HRTIM_fltinr1 |= (Enable << 24);
bogdanm 0:9b334a45a8ff 2635 }
bogdanm 0:9b334a45a8ff 2636 break;
bogdanm 0:9b334a45a8ff 2637 case HRTIM_FAULT_5:
bogdanm 0:9b334a45a8ff 2638 {
bogdanm 0:9b334a45a8ff 2639 HRTIM_fltinr2 &= ~HRTIM_FLTINR2_FLT5E;
bogdanm 0:9b334a45a8ff 2640 HRTIM_fltinr2 |= Enable;
bogdanm 0:9b334a45a8ff 2641 }
bogdanm 0:9b334a45a8ff 2642 break;
bogdanm 0:9b334a45a8ff 2643 default:
bogdanm 0:9b334a45a8ff 2644 break;
bogdanm 0:9b334a45a8ff 2645 }
bogdanm 0:9b334a45a8ff 2646
bogdanm 0:9b334a45a8ff 2647 /* Update the HRTIMx registers */
bogdanm 0:9b334a45a8ff 2648 HRTIMx->HRTIM_COMMON.FLTINxR1 = HRTIM_fltinr1;
bogdanm 0:9b334a45a8ff 2649 HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2;
bogdanm 0:9b334a45a8ff 2650 }
bogdanm 0:9b334a45a8ff 2651
bogdanm 0:9b334a45a8ff 2652 /**
bogdanm 0:9b334a45a8ff 2653 * @brief Configures both the ADC trigger register update source and the ADC
bogdanm 0:9b334a45a8ff 2654 * trigger source.
bogdanm 0:9b334a45a8ff 2655 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 2656 * @param ADC trigger: ADC trigger to configure
bogdanm 0:9b334a45a8ff 2657 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2658 * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
bogdanm 0:9b334a45a8ff 2659 * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
bogdanm 0:9b334a45a8ff 2660 * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
bogdanm 0:9b334a45a8ff 2661 * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
bogdanm 0:9b334a45a8ff 2662 * @param pADCTriggerCfg: pointer to the ADC trigger configuration structure
bogdanm 0:9b334a45a8ff 2663 * @retval None
bogdanm 0:9b334a45a8ff 2664 */
bogdanm 0:9b334a45a8ff 2665 void HRTIM_ADCTriggerConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 2666 uint32_t ADCTrigger,
bogdanm 0:9b334a45a8ff 2667 HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
bogdanm 0:9b334a45a8ff 2668 {
bogdanm 0:9b334a45a8ff 2669 uint32_t HRTIM_cr1;
bogdanm 0:9b334a45a8ff 2670
bogdanm 0:9b334a45a8ff 2671 /* Check parameters */
bogdanm 0:9b334a45a8ff 2672 assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
bogdanm 0:9b334a45a8ff 2673 assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
bogdanm 0:9b334a45a8ff 2674
bogdanm 0:9b334a45a8ff 2675 /* Set the ADC trigger update source */
bogdanm 0:9b334a45a8ff 2676 HRTIM_cr1 = HRTIMx->HRTIM_COMMON.CR1;
bogdanm 0:9b334a45a8ff 2677
bogdanm 0:9b334a45a8ff 2678 switch (ADCTrigger)
bogdanm 0:9b334a45a8ff 2679 {
bogdanm 0:9b334a45a8ff 2680 case HRTIM_ADCTRIGGER_1:
bogdanm 0:9b334a45a8ff 2681 {
bogdanm 0:9b334a45a8ff 2682 HRTIM_cr1 &= ~(HRTIM_CR1_ADC1USRC);
bogdanm 0:9b334a45a8ff 2683 HRTIM_cr1 |= pADCTriggerCfg->UpdateSource;
bogdanm 0:9b334a45a8ff 2684
bogdanm 0:9b334a45a8ff 2685 /* Set the ADC trigger 1 source */
bogdanm 0:9b334a45a8ff 2686 HRTIMx->HRTIM_COMMON.ADC1R = pADCTriggerCfg->Trigger;
bogdanm 0:9b334a45a8ff 2687 }
bogdanm 0:9b334a45a8ff 2688 break;
bogdanm 0:9b334a45a8ff 2689 case HRTIM_ADCTRIGGER_2:
bogdanm 0:9b334a45a8ff 2690 {
bogdanm 0:9b334a45a8ff 2691 HRTIM_cr1 &= ~(HRTIM_CR1_ADC2USRC);
bogdanm 0:9b334a45a8ff 2692 HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 3);
bogdanm 0:9b334a45a8ff 2693
bogdanm 0:9b334a45a8ff 2694 /* Set the ADC trigger 2 source */
bogdanm 0:9b334a45a8ff 2695 HRTIMx->HRTIM_COMMON.ADC2R = pADCTriggerCfg->Trigger;
bogdanm 0:9b334a45a8ff 2696 }
bogdanm 0:9b334a45a8ff 2697 break;
bogdanm 0:9b334a45a8ff 2698 case HRTIM_ADCTRIGGER_3:
bogdanm 0:9b334a45a8ff 2699 {
bogdanm 0:9b334a45a8ff 2700 HRTIM_cr1 &= ~(HRTIM_CR1_ADC3USRC);
bogdanm 0:9b334a45a8ff 2701 HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 6);
bogdanm 0:9b334a45a8ff 2702
bogdanm 0:9b334a45a8ff 2703 /* Set the ADC trigger 3 source */
bogdanm 0:9b334a45a8ff 2704 HRTIMx->HRTIM_COMMON.ADC3R = pADCTriggerCfg->Trigger;
bogdanm 0:9b334a45a8ff 2705 }
bogdanm 0:9b334a45a8ff 2706 case HRTIM_ADCTRIGGER_4:
bogdanm 0:9b334a45a8ff 2707 {
bogdanm 0:9b334a45a8ff 2708 HRTIM_cr1 &= ~(HRTIM_CR1_ADC4USRC);
bogdanm 0:9b334a45a8ff 2709 HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 9);
bogdanm 0:9b334a45a8ff 2710
bogdanm 0:9b334a45a8ff 2711 /* Set the ADC trigger 4 source */
bogdanm 0:9b334a45a8ff 2712 HRTIMx->HRTIM_COMMON.ADC4R = pADCTriggerCfg->Trigger;
bogdanm 0:9b334a45a8ff 2713 }
bogdanm 0:9b334a45a8ff 2714 break;
bogdanm 0:9b334a45a8ff 2715 default:
bogdanm 0:9b334a45a8ff 2716 break;
bogdanm 0:9b334a45a8ff 2717 }
bogdanm 0:9b334a45a8ff 2718
bogdanm 0:9b334a45a8ff 2719 /* Update the HRTIMx registers */
bogdanm 0:9b334a45a8ff 2720 HRTIMx->HRTIM_COMMON.CR1 = HRTIM_cr1;
bogdanm 0:9b334a45a8ff 2721 }
bogdanm 0:9b334a45a8ff 2722
bogdanm 0:9b334a45a8ff 2723
bogdanm 0:9b334a45a8ff 2724 /**
bogdanm 0:9b334a45a8ff 2725 * @brief Enables or disables the HRTIMx burst mode controller.
bogdanm 0:9b334a45a8ff 2726 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 2727 * @param Enable: Burst mode controller enabling
bogdanm 0:9b334a45a8ff 2728 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2729 * @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
bogdanm 0:9b334a45a8ff 2730 * @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
bogdanm 0:9b334a45a8ff 2731 * @retval None
bogdanm 0:9b334a45a8ff 2732 */
bogdanm 0:9b334a45a8ff 2733 void HRTIM_BurstModeCtl(HRTIM_TypeDef * HRTIMx, uint32_t Enable)
bogdanm 0:9b334a45a8ff 2734 {
bogdanm 0:9b334a45a8ff 2735 uint32_t HRTIM_bmcr;
bogdanm 0:9b334a45a8ff 2736
bogdanm 0:9b334a45a8ff 2737 /* Check parameters */
bogdanm 0:9b334a45a8ff 2738 assert_param(IS_HRTIM_BURSTMODECTL(Enable));
bogdanm 0:9b334a45a8ff 2739
bogdanm 0:9b334a45a8ff 2740 /* Enable/Disable the burst mode controller */
bogdanm 0:9b334a45a8ff 2741 HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
bogdanm 0:9b334a45a8ff 2742 HRTIM_bmcr &= ~(HRTIM_BMCR_BME);
bogdanm 0:9b334a45a8ff 2743 HRTIM_bmcr |= Enable;
bogdanm 0:9b334a45a8ff 2744
bogdanm 0:9b334a45a8ff 2745 /* Update the HRTIMx registers */
bogdanm 0:9b334a45a8ff 2746 HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
bogdanm 0:9b334a45a8ff 2747 }
bogdanm 0:9b334a45a8ff 2748
bogdanm 0:9b334a45a8ff 2749 /**
bogdanm 0:9b334a45a8ff 2750 * @brief Triggers a software capture on the designed capture unit
bogdanm 0:9b334a45a8ff 2751 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 2752 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 2753 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2754 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 2755 * @param CaptureUnit: Capture unit to trig
bogdanm 0:9b334a45a8ff 2756 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2757 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
bogdanm 0:9b334a45a8ff 2758 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
bogdanm 0:9b334a45a8ff 2759 * @retval None
bogdanm 0:9b334a45a8ff 2760 * @note The 'software capture' bit in the capure configuration register is
bogdanm 0:9b334a45a8ff 2761 * automatically reset by hardware
bogdanm 0:9b334a45a8ff 2762 */
bogdanm 0:9b334a45a8ff 2763 void HRTIM_SoftwareCapture(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 2764 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 2765 uint32_t CaptureUnit)
bogdanm 0:9b334a45a8ff 2766 {
bogdanm 0:9b334a45a8ff 2767 /* Check parameters */
bogdanm 0:9b334a45a8ff 2768 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
bogdanm 0:9b334a45a8ff 2769 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
bogdanm 0:9b334a45a8ff 2770
bogdanm 0:9b334a45a8ff 2771 /* Force a software capture on concerned capture unit */
bogdanm 0:9b334a45a8ff 2772 switch (CaptureUnit)
bogdanm 0:9b334a45a8ff 2773 {
bogdanm 0:9b334a45a8ff 2774 case HRTIM_CAPTUREUNIT_1:
bogdanm 0:9b334a45a8ff 2775 {
bogdanm 0:9b334a45a8ff 2776 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR |= HRTIM_CPT1CR_SWCPT;
bogdanm 0:9b334a45a8ff 2777 }
bogdanm 0:9b334a45a8ff 2778 break;
bogdanm 0:9b334a45a8ff 2779 case HRTIM_CAPTUREUNIT_2:
bogdanm 0:9b334a45a8ff 2780 {
bogdanm 0:9b334a45a8ff 2781 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR |= HRTIM_CPT2CR_SWCPT;
bogdanm 0:9b334a45a8ff 2782 }
bogdanm 0:9b334a45a8ff 2783 break;
bogdanm 0:9b334a45a8ff 2784 default:
bogdanm 0:9b334a45a8ff 2785 break;
bogdanm 0:9b334a45a8ff 2786 }
bogdanm 0:9b334a45a8ff 2787 }
bogdanm 0:9b334a45a8ff 2788
bogdanm 0:9b334a45a8ff 2789 /**
bogdanm 0:9b334a45a8ff 2790 * @brief Triggers the update of the registers of one or several timers
bogdanm 0:9b334a45a8ff 2791 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 2792 * @param TimersToUpdate: timers concerned with the software register update
bogdanm 0:9b334a45a8ff 2793 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 2794 * @arg HRTIM_TIMERUPDATE_MASTER
bogdanm 0:9b334a45a8ff 2795 * @arg HRTIM_TIMERUPDATE_A
bogdanm 0:9b334a45a8ff 2796 * @arg HRTIM_TIMERUPDATE_B
bogdanm 0:9b334a45a8ff 2797 * @arg HRTIM_TIMERUPDATE_C
bogdanm 0:9b334a45a8ff 2798 * @arg HRTIM_TIMERUPDATE_D
bogdanm 0:9b334a45a8ff 2799 * @arg HRTIM_TIMERUPDATE_E
bogdanm 0:9b334a45a8ff 2800 * @retval None
bogdanm 0:9b334a45a8ff 2801 * @note The 'software update' bits in the HRTIMx control register 2 register are
bogdanm 0:9b334a45a8ff 2802 * automatically reset by hardware
bogdanm 0:9b334a45a8ff 2803 */
bogdanm 0:9b334a45a8ff 2804 void HRTIM_SoftwareUpdate(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 2805 uint32_t TimersToUpdate)
bogdanm 0:9b334a45a8ff 2806 {
bogdanm 0:9b334a45a8ff 2807 /* Check parameters */
bogdanm 0:9b334a45a8ff 2808 assert_param(IS_HRTIM_TIMERUPDATE(TimersToUpdate));
bogdanm 0:9b334a45a8ff 2809
bogdanm 0:9b334a45a8ff 2810 /* Force timer(s) registers update */
bogdanm 0:9b334a45a8ff 2811 HRTIMx->HRTIM_COMMON.CR2 |= TimersToUpdate;
bogdanm 0:9b334a45a8ff 2812
bogdanm 0:9b334a45a8ff 2813 }
bogdanm 0:9b334a45a8ff 2814
bogdanm 0:9b334a45a8ff 2815 /**
bogdanm 0:9b334a45a8ff 2816 * @brief Triggers the reset of one or several timers
bogdanm 0:9b334a45a8ff 2817 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 2818 * @param TimersToUpdate: timers concerned with the software counter reset
bogdanm 0:9b334a45a8ff 2819 * This parameter can be any combination of the following values:
bogdanm 0:9b334a45a8ff 2820 * @arg HRTIM_TIMER_MASTER
bogdanm 0:9b334a45a8ff 2821 * @arg HRTIM_TIMER_A
bogdanm 0:9b334a45a8ff 2822 * @arg HRTIM_TIMER_B
bogdanm 0:9b334a45a8ff 2823 * @arg HRTIM_TIMER_C
bogdanm 0:9b334a45a8ff 2824 * @arg HRTIM_TIMER_D
bogdanm 0:9b334a45a8ff 2825 * @arg HRTIM_TIMER_E
bogdanm 0:9b334a45a8ff 2826 * @retval None
bogdanm 0:9b334a45a8ff 2827 * @note The 'software reset' bits in the HRTIMx control register 2 are
bogdanm 0:9b334a45a8ff 2828 * automatically reset by hardware
bogdanm 0:9b334a45a8ff 2829 */
bogdanm 0:9b334a45a8ff 2830 void HRTIM_SoftwareReset(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 2831 uint32_t TimersToReset)
bogdanm 0:9b334a45a8ff 2832 {
bogdanm 0:9b334a45a8ff 2833 /* Check parameters */
bogdanm 0:9b334a45a8ff 2834 assert_param(IS_HRTIM_TIMERRESET(TimersToReset));
bogdanm 0:9b334a45a8ff 2835
bogdanm 0:9b334a45a8ff 2836 /* Force timer(s) registers update */
bogdanm 0:9b334a45a8ff 2837 HRTIMx->HRTIM_COMMON.CR2 |= TimersToReset;
bogdanm 0:9b334a45a8ff 2838
bogdanm 0:9b334a45a8ff 2839 }
bogdanm 0:9b334a45a8ff 2840
bogdanm 0:9b334a45a8ff 2841 /**
bogdanm 0:9b334a45a8ff 2842 * @brief Forces the timer output to its active or inactive state
bogdanm 0:9b334a45a8ff 2843 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 2844 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 2845 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2846 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 2847 * @param Output: Timer output
bogdanm 0:9b334a45a8ff 2848 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2849 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
bogdanm 0:9b334a45a8ff 2850 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
bogdanm 0:9b334a45a8ff 2851 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
bogdanm 0:9b334a45a8ff 2852 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
bogdanm 0:9b334a45a8ff 2853 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
bogdanm 0:9b334a45a8ff 2854 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
bogdanm 0:9b334a45a8ff 2855 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
bogdanm 0:9b334a45a8ff 2856 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
bogdanm 0:9b334a45a8ff 2857 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
bogdanm 0:9b334a45a8ff 2858 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
bogdanm 0:9b334a45a8ff 2859 * @param OutputLevel: indicates whether the output is forced to its active or inactive state
bogdanm 0:9b334a45a8ff 2860 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2861 * @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active state
bogdanm 0:9b334a45a8ff 2862 * @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive state
bogdanm 0:9b334a45a8ff 2863 * @retval None
bogdanm 0:9b334a45a8ff 2864 * @note The 'software set/reset trigger' bit in the output set/reset registers
bogdanm 0:9b334a45a8ff 2865 * is automatically reset by hardware
bogdanm 0:9b334a45a8ff 2866 */
bogdanm 0:9b334a45a8ff 2867 void HRTIM_WaveformSetOutputLevel(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 2868 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 2869 uint32_t Output,
bogdanm 0:9b334a45a8ff 2870 uint32_t OutputLevel)
bogdanm 0:9b334a45a8ff 2871 {
bogdanm 0:9b334a45a8ff 2872 /* Check parameters */
bogdanm 0:9b334a45a8ff 2873 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
bogdanm 0:9b334a45a8ff 2874 assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
bogdanm 0:9b334a45a8ff 2875
bogdanm 0:9b334a45a8ff 2876 /* Force timer output level */
bogdanm 0:9b334a45a8ff 2877 switch (Output)
bogdanm 0:9b334a45a8ff 2878 {
bogdanm 0:9b334a45a8ff 2879 case HRTIM_OUTPUT_TA1:
bogdanm 0:9b334a45a8ff 2880 case HRTIM_OUTPUT_TB1:
bogdanm 0:9b334a45a8ff 2881 case HRTIM_OUTPUT_TC1:
bogdanm 0:9b334a45a8ff 2882 case HRTIM_OUTPUT_TD1:
bogdanm 0:9b334a45a8ff 2883 case HRTIM_OUTPUT_TE1:
bogdanm 0:9b334a45a8ff 2884 {
bogdanm 0:9b334a45a8ff 2885 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
bogdanm 0:9b334a45a8ff 2886 {
bogdanm 0:9b334a45a8ff 2887 /* Force output to its active state */
bogdanm 0:9b334a45a8ff 2888 HRTIMx->HRTIM_TIMERx[TimerIdx].SETx1R |= HRTIM_SET1R_SST;
bogdanm 0:9b334a45a8ff 2889 }
bogdanm 0:9b334a45a8ff 2890 else
bogdanm 0:9b334a45a8ff 2891 {
bogdanm 0:9b334a45a8ff 2892 /* Force output to its inactive state */
bogdanm 0:9b334a45a8ff 2893 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx1R |= HRTIM_RST1R_SRT;
bogdanm 0:9b334a45a8ff 2894 }
bogdanm 0:9b334a45a8ff 2895 }
bogdanm 0:9b334a45a8ff 2896 break;
bogdanm 0:9b334a45a8ff 2897 case HRTIM_OUTPUT_TA2:
bogdanm 0:9b334a45a8ff 2898 case HRTIM_OUTPUT_TB2:
bogdanm 0:9b334a45a8ff 2899 case HRTIM_OUTPUT_TC2:
bogdanm 0:9b334a45a8ff 2900 case HRTIM_OUTPUT_TD2:
bogdanm 0:9b334a45a8ff 2901 case HRTIM_OUTPUT_TE2:
bogdanm 0:9b334a45a8ff 2902 {
bogdanm 0:9b334a45a8ff 2903 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
bogdanm 0:9b334a45a8ff 2904 {
bogdanm 0:9b334a45a8ff 2905 /* Force output to its active state */
bogdanm 0:9b334a45a8ff 2906 HRTIMx->HRTIM_TIMERx[TimerIdx].SETx2R |= HRTIM_SET2R_SST;
bogdanm 0:9b334a45a8ff 2907 }
bogdanm 0:9b334a45a8ff 2908 else
bogdanm 0:9b334a45a8ff 2909 {
bogdanm 0:9b334a45a8ff 2910 /* Force output to its inactive state */
bogdanm 0:9b334a45a8ff 2911 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx2R |= HRTIM_RST2R_SRT;
bogdanm 0:9b334a45a8ff 2912 }
bogdanm 0:9b334a45a8ff 2913 }
bogdanm 0:9b334a45a8ff 2914 break;
bogdanm 0:9b334a45a8ff 2915 default:
bogdanm 0:9b334a45a8ff 2916 break;
bogdanm 0:9b334a45a8ff 2917 }
bogdanm 0:9b334a45a8ff 2918 }
bogdanm 0:9b334a45a8ff 2919
bogdanm 0:9b334a45a8ff 2920
bogdanm 0:9b334a45a8ff 2921 /**
bogdanm 0:9b334a45a8ff 2922 * @}
bogdanm 0:9b334a45a8ff 2923 */
bogdanm 0:9b334a45a8ff 2924
bogdanm 0:9b334a45a8ff 2925 /** @defgroup HRTIM_Group4 Peripheral State methods
bogdanm 0:9b334a45a8ff 2926 * @brief Peripheral State functions
bogdanm 0:9b334a45a8ff 2927 *
bogdanm 0:9b334a45a8ff 2928 @verbatim
bogdanm 0:9b334a45a8ff 2929 ===============================================================================
bogdanm 0:9b334a45a8ff 2930 ##### Peripheral State methods #####
bogdanm 0:9b334a45a8ff 2931 ===============================================================================
bogdanm 0:9b334a45a8ff 2932 [..]
bogdanm 0:9b334a45a8ff 2933 This subsection permit to get in run-time the status of the peripheral
bogdanm 0:9b334a45a8ff 2934 and the data flow.
bogdanm 0:9b334a45a8ff 2935
bogdanm 0:9b334a45a8ff 2936 @endverbatim
bogdanm 0:9b334a45a8ff 2937 * @{
bogdanm 0:9b334a45a8ff 2938 */
bogdanm 0:9b334a45a8ff 2939
bogdanm 0:9b334a45a8ff 2940 /**
bogdanm 0:9b334a45a8ff 2941 * @brief Returns actual value of the capture register of the designated capture unit
bogdanm 0:9b334a45a8ff 2942 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 2943 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 2944 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2945 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 2946 * @param CaptureUnit: Capture unit to trig
bogdanm 0:9b334a45a8ff 2947 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2948 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
bogdanm 0:9b334a45a8ff 2949 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
bogdanm 0:9b334a45a8ff 2950 * @retval Captured value
bogdanm 0:9b334a45a8ff 2951 */
bogdanm 0:9b334a45a8ff 2952 uint32_t HRTIM_GetCapturedValue(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 2953 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 2954 uint32_t CaptureUnit)
bogdanm 0:9b334a45a8ff 2955 {
bogdanm 0:9b334a45a8ff 2956 uint32_t captured_value = 0;
bogdanm 0:9b334a45a8ff 2957
bogdanm 0:9b334a45a8ff 2958 /* Check parameters */
bogdanm 0:9b334a45a8ff 2959 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
bogdanm 0:9b334a45a8ff 2960 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
bogdanm 0:9b334a45a8ff 2961
bogdanm 0:9b334a45a8ff 2962 /* Read captured value */
bogdanm 0:9b334a45a8ff 2963 switch (CaptureUnit)
bogdanm 0:9b334a45a8ff 2964 {
bogdanm 0:9b334a45a8ff 2965 case HRTIM_CAPTUREUNIT_1:
bogdanm 0:9b334a45a8ff 2966 {
bogdanm 0:9b334a45a8ff 2967 captured_value = HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xR;
bogdanm 0:9b334a45a8ff 2968 }
bogdanm 0:9b334a45a8ff 2969 break;
bogdanm 0:9b334a45a8ff 2970 case HRTIM_CAPTUREUNIT_2:
bogdanm 0:9b334a45a8ff 2971 {
bogdanm 0:9b334a45a8ff 2972 captured_value = HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xR;
bogdanm 0:9b334a45a8ff 2973 }
bogdanm 0:9b334a45a8ff 2974 break;
bogdanm 0:9b334a45a8ff 2975 default:
bogdanm 0:9b334a45a8ff 2976 break;
bogdanm 0:9b334a45a8ff 2977 }
bogdanm 0:9b334a45a8ff 2978
bogdanm 0:9b334a45a8ff 2979 return captured_value;
bogdanm 0:9b334a45a8ff 2980 }
bogdanm 0:9b334a45a8ff 2981
bogdanm 0:9b334a45a8ff 2982 /**
bogdanm 0:9b334a45a8ff 2983 * @brief Returns actual level (active or inactive) of the designated output
bogdanm 0:9b334a45a8ff 2984 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 2985 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 2986 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2987 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 2988 * @param Output: Timer output
bogdanm 0:9b334a45a8ff 2989 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 2990 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
bogdanm 0:9b334a45a8ff 2991 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
bogdanm 0:9b334a45a8ff 2992 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
bogdanm 0:9b334a45a8ff 2993 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
bogdanm 0:9b334a45a8ff 2994 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
bogdanm 0:9b334a45a8ff 2995 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
bogdanm 0:9b334a45a8ff 2996 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
bogdanm 0:9b334a45a8ff 2997 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
bogdanm 0:9b334a45a8ff 2998 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
bogdanm 0:9b334a45a8ff 2999 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
bogdanm 0:9b334a45a8ff 3000 * @retval Output level
bogdanm 0:9b334a45a8ff 3001 * @note Returned output level is taken before the output stage (chopper,
bogdanm 0:9b334a45a8ff 3002 * polarity).
bogdanm 0:9b334a45a8ff 3003 */
bogdanm 0:9b334a45a8ff 3004 uint32_t HRTIM_WaveformGetOutputLevel(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 3005 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 3006 uint32_t Output)
bogdanm 0:9b334a45a8ff 3007 {
bogdanm 0:9b334a45a8ff 3008 uint32_t output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
bogdanm 0:9b334a45a8ff 3009
bogdanm 0:9b334a45a8ff 3010 /* Check parameters */
bogdanm 0:9b334a45a8ff 3011 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
bogdanm 0:9b334a45a8ff 3012
bogdanm 0:9b334a45a8ff 3013 /* Read the output level */
bogdanm 0:9b334a45a8ff 3014 switch (Output)
bogdanm 0:9b334a45a8ff 3015 {
bogdanm 0:9b334a45a8ff 3016 case HRTIM_OUTPUT_TA1:
bogdanm 0:9b334a45a8ff 3017 case HRTIM_OUTPUT_TB1:
bogdanm 0:9b334a45a8ff 3018 case HRTIM_OUTPUT_TC1:
bogdanm 0:9b334a45a8ff 3019 case HRTIM_OUTPUT_TD1:
bogdanm 0:9b334a45a8ff 3020 case HRTIM_OUTPUT_TE1:
bogdanm 0:9b334a45a8ff 3021 {
bogdanm 0:9b334a45a8ff 3022 if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != RESET)
bogdanm 0:9b334a45a8ff 3023 {
bogdanm 0:9b334a45a8ff 3024 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
bogdanm 0:9b334a45a8ff 3025 }
bogdanm 0:9b334a45a8ff 3026 else
bogdanm 0:9b334a45a8ff 3027 {
bogdanm 0:9b334a45a8ff 3028 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
bogdanm 0:9b334a45a8ff 3029 }
bogdanm 0:9b334a45a8ff 3030 }
bogdanm 0:9b334a45a8ff 3031 break;
bogdanm 0:9b334a45a8ff 3032 case HRTIM_OUTPUT_TA2:
bogdanm 0:9b334a45a8ff 3033 case HRTIM_OUTPUT_TB2:
bogdanm 0:9b334a45a8ff 3034 case HRTIM_OUTPUT_TC2:
bogdanm 0:9b334a45a8ff 3035 case HRTIM_OUTPUT_TD2:
bogdanm 0:9b334a45a8ff 3036 case HRTIM_OUTPUT_TE2:
bogdanm 0:9b334a45a8ff 3037 {
bogdanm 0:9b334a45a8ff 3038 if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != RESET)
bogdanm 0:9b334a45a8ff 3039 {
bogdanm 0:9b334a45a8ff 3040 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
bogdanm 0:9b334a45a8ff 3041 }
bogdanm 0:9b334a45a8ff 3042 else
bogdanm 0:9b334a45a8ff 3043 {
bogdanm 0:9b334a45a8ff 3044 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
bogdanm 0:9b334a45a8ff 3045 }
bogdanm 0:9b334a45a8ff 3046 }
bogdanm 0:9b334a45a8ff 3047 break;
bogdanm 0:9b334a45a8ff 3048 default:
bogdanm 0:9b334a45a8ff 3049 break;
bogdanm 0:9b334a45a8ff 3050 }
bogdanm 0:9b334a45a8ff 3051
bogdanm 0:9b334a45a8ff 3052 return output_level;
bogdanm 0:9b334a45a8ff 3053 }
bogdanm 0:9b334a45a8ff 3054
bogdanm 0:9b334a45a8ff 3055 /**
bogdanm 0:9b334a45a8ff 3056 * @brief Returns actual state (RUN, IDLE, FAULT) of the designated output
bogdanm 0:9b334a45a8ff 3057 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 3058 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 3059 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 3060 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 3061 * @param Output: Timer output
bogdanm 0:9b334a45a8ff 3062 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 3063 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
bogdanm 0:9b334a45a8ff 3064 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
bogdanm 0:9b334a45a8ff 3065 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
bogdanm 0:9b334a45a8ff 3066 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
bogdanm 0:9b334a45a8ff 3067 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
bogdanm 0:9b334a45a8ff 3068 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
bogdanm 0:9b334a45a8ff 3069 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
bogdanm 0:9b334a45a8ff 3070 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
bogdanm 0:9b334a45a8ff 3071 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
bogdanm 0:9b334a45a8ff 3072 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
bogdanm 0:9b334a45a8ff 3073 * @retval Output state
bogdanm 0:9b334a45a8ff 3074 */
bogdanm 0:9b334a45a8ff 3075 uint32_t HRTIM_WaveformGetOutputState(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 3076 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 3077 uint32_t Output)
bogdanm 0:9b334a45a8ff 3078 {
bogdanm 0:9b334a45a8ff 3079 uint32_t output_bit = 0;
bogdanm 0:9b334a45a8ff 3080 uint32_t output_state = HRTIM_OUTPUTSTATE_IDLE;
bogdanm 0:9b334a45a8ff 3081
bogdanm 0:9b334a45a8ff 3082 /* Check parameters */
bogdanm 0:9b334a45a8ff 3083 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
bogdanm 0:9b334a45a8ff 3084
bogdanm 0:9b334a45a8ff 3085 /* Set output state according to output control status and output disable status */
bogdanm 0:9b334a45a8ff 3086 switch (Output)
bogdanm 0:9b334a45a8ff 3087 {
bogdanm 0:9b334a45a8ff 3088 case HRTIM_OUTPUT_TA1:
bogdanm 0:9b334a45a8ff 3089 {
bogdanm 0:9b334a45a8ff 3090 output_bit = HRTIM_OENR_TA1OEN;
bogdanm 0:9b334a45a8ff 3091 }
bogdanm 0:9b334a45a8ff 3092 break;
bogdanm 0:9b334a45a8ff 3093 case HRTIM_OUTPUT_TA2:
bogdanm 0:9b334a45a8ff 3094 {
bogdanm 0:9b334a45a8ff 3095 output_bit = HRTIM_OENR_TA2OEN;
bogdanm 0:9b334a45a8ff 3096 }
bogdanm 0:9b334a45a8ff 3097 break;
bogdanm 0:9b334a45a8ff 3098 case HRTIM_OUTPUT_TB1:
bogdanm 0:9b334a45a8ff 3099 {
bogdanm 0:9b334a45a8ff 3100 output_bit = HRTIM_OENR_TB1OEN;
bogdanm 0:9b334a45a8ff 3101 }
bogdanm 0:9b334a45a8ff 3102 break;
bogdanm 0:9b334a45a8ff 3103 case HRTIM_OUTPUT_TB2:
bogdanm 0:9b334a45a8ff 3104 {
bogdanm 0:9b334a45a8ff 3105 output_bit = HRTIM_OENR_TB2OEN;
bogdanm 0:9b334a45a8ff 3106 }
bogdanm 0:9b334a45a8ff 3107 break;
bogdanm 0:9b334a45a8ff 3108 case HRTIM_OUTPUT_TC1:
bogdanm 0:9b334a45a8ff 3109 {
bogdanm 0:9b334a45a8ff 3110 output_bit = HRTIM_OENR_TC1OEN;
bogdanm 0:9b334a45a8ff 3111 }
bogdanm 0:9b334a45a8ff 3112 break;
bogdanm 0:9b334a45a8ff 3113 case HRTIM_OUTPUT_TC2:
bogdanm 0:9b334a45a8ff 3114 {
bogdanm 0:9b334a45a8ff 3115 output_bit = HRTIM_OENR_TC2OEN;
bogdanm 0:9b334a45a8ff 3116 }
bogdanm 0:9b334a45a8ff 3117 break;
bogdanm 0:9b334a45a8ff 3118 case HRTIM_OUTPUT_TD1:
bogdanm 0:9b334a45a8ff 3119 {
bogdanm 0:9b334a45a8ff 3120 output_bit = HRTIM_OENR_TD1OEN;
bogdanm 0:9b334a45a8ff 3121 }
bogdanm 0:9b334a45a8ff 3122 break;
bogdanm 0:9b334a45a8ff 3123 case HRTIM_OUTPUT_TD2:
bogdanm 0:9b334a45a8ff 3124 {
bogdanm 0:9b334a45a8ff 3125 output_bit = HRTIM_OENR_TD2OEN;
bogdanm 0:9b334a45a8ff 3126 }
bogdanm 0:9b334a45a8ff 3127 break;
bogdanm 0:9b334a45a8ff 3128 case HRTIM_OUTPUT_TE1:
bogdanm 0:9b334a45a8ff 3129 {
bogdanm 0:9b334a45a8ff 3130 output_bit = HRTIM_OENR_TE1OEN;
bogdanm 0:9b334a45a8ff 3131 }
bogdanm 0:9b334a45a8ff 3132 break;
bogdanm 0:9b334a45a8ff 3133 case HRTIM_OUTPUT_TE2:
bogdanm 0:9b334a45a8ff 3134 {
bogdanm 0:9b334a45a8ff 3135 output_bit = HRTIM_OENR_TE2OEN;
bogdanm 0:9b334a45a8ff 3136 }
bogdanm 0:9b334a45a8ff 3137 break;
bogdanm 0:9b334a45a8ff 3138 default:
bogdanm 0:9b334a45a8ff 3139 break;
bogdanm 0:9b334a45a8ff 3140 }
bogdanm 0:9b334a45a8ff 3141
bogdanm 0:9b334a45a8ff 3142 if ((HRTIMx->HRTIM_COMMON.OENR & output_bit) != RESET)
bogdanm 0:9b334a45a8ff 3143 {
bogdanm 0:9b334a45a8ff 3144 /* Output is enabled: output in RUN state (whatever ouput disable status is)*/
bogdanm 0:9b334a45a8ff 3145 output_state = HRTIM_OUTPUTSTATE_RUN;
bogdanm 0:9b334a45a8ff 3146 }
bogdanm 0:9b334a45a8ff 3147 else
bogdanm 0:9b334a45a8ff 3148 {
bogdanm 0:9b334a45a8ff 3149 if ((HRTIMx->HRTIM_COMMON.ODSR & output_bit) != RESET)
bogdanm 0:9b334a45a8ff 3150 {
bogdanm 0:9b334a45a8ff 3151 /* Output is disabled: output in FAULT state */
bogdanm 0:9b334a45a8ff 3152 output_state = HRTIM_OUTPUTSTATE_FAULT;
bogdanm 0:9b334a45a8ff 3153 }
bogdanm 0:9b334a45a8ff 3154 else
bogdanm 0:9b334a45a8ff 3155 {
bogdanm 0:9b334a45a8ff 3156 /* Output is disabled: output in IDLE state */
bogdanm 0:9b334a45a8ff 3157 output_state = HRTIM_OUTPUTSTATE_IDLE;
bogdanm 0:9b334a45a8ff 3158 }
bogdanm 0:9b334a45a8ff 3159 }
bogdanm 0:9b334a45a8ff 3160
bogdanm 0:9b334a45a8ff 3161 return(output_state);
bogdanm 0:9b334a45a8ff 3162 }
bogdanm 0:9b334a45a8ff 3163
bogdanm 0:9b334a45a8ff 3164 /**
bogdanm 0:9b334a45a8ff 3165 * @brief Returns the level (active or inactive) of the designated output
bogdanm 0:9b334a45a8ff 3166 * when the delayed protection was triggered
bogdanm 0:9b334a45a8ff 3167 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 3168 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 3169 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 3170 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 3171 * @param Output: Timer output
bogdanm 0:9b334a45a8ff 3172 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 3173 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
bogdanm 0:9b334a45a8ff 3174 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
bogdanm 0:9b334a45a8ff 3175 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
bogdanm 0:9b334a45a8ff 3176 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
bogdanm 0:9b334a45a8ff 3177 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
bogdanm 0:9b334a45a8ff 3178 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
bogdanm 0:9b334a45a8ff 3179 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
bogdanm 0:9b334a45a8ff 3180 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
bogdanm 0:9b334a45a8ff 3181 * @arg HRTIM_OUTPUT_TD1: Timer E - Output 1
bogdanm 0:9b334a45a8ff 3182 * @arg HRTIM_OUTPUT_TD2: Timer E - Output 2
bogdanm 0:9b334a45a8ff 3183 * @retval Delayed protection status
bogdanm 0:9b334a45a8ff 3184 */
bogdanm 0:9b334a45a8ff 3185 uint32_t HRTIM_GetDelayedProtectionStatus(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 3186 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 3187 uint32_t Output)
bogdanm 0:9b334a45a8ff 3188 {
bogdanm 0:9b334a45a8ff 3189 uint32_t delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
bogdanm 0:9b334a45a8ff 3190
bogdanm 0:9b334a45a8ff 3191 /* Check parameters */
bogdanm 0:9b334a45a8ff 3192 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
bogdanm 0:9b334a45a8ff 3193
bogdanm 0:9b334a45a8ff 3194 /* Read the delayed protection status */
bogdanm 0:9b334a45a8ff 3195 switch (Output)
bogdanm 0:9b334a45a8ff 3196 {
bogdanm 0:9b334a45a8ff 3197 case HRTIM_OUTPUT_TA1:
bogdanm 0:9b334a45a8ff 3198 case HRTIM_OUTPUT_TB1:
bogdanm 0:9b334a45a8ff 3199 case HRTIM_OUTPUT_TC1:
bogdanm 0:9b334a45a8ff 3200 case HRTIM_OUTPUT_TD1:
bogdanm 0:9b334a45a8ff 3201 case HRTIM_OUTPUT_TE1:
bogdanm 0:9b334a45a8ff 3202 {
bogdanm 0:9b334a45a8ff 3203 if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != RESET)
bogdanm 0:9b334a45a8ff 3204 {
bogdanm 0:9b334a45a8ff 3205 /* Output 1 was active when the delayed idle protection was triggered */
bogdanm 0:9b334a45a8ff 3206 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
bogdanm 0:9b334a45a8ff 3207 }
bogdanm 0:9b334a45a8ff 3208 else
bogdanm 0:9b334a45a8ff 3209 {
bogdanm 0:9b334a45a8ff 3210 /* Output 1 was inactive when the delayed idle protection was triggered */
bogdanm 0:9b334a45a8ff 3211 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
bogdanm 0:9b334a45a8ff 3212 }
bogdanm 0:9b334a45a8ff 3213 }
bogdanm 0:9b334a45a8ff 3214 break;
bogdanm 0:9b334a45a8ff 3215 case HRTIM_OUTPUT_TA2:
bogdanm 0:9b334a45a8ff 3216 case HRTIM_OUTPUT_TB2:
bogdanm 0:9b334a45a8ff 3217 case HRTIM_OUTPUT_TC2:
bogdanm 0:9b334a45a8ff 3218 case HRTIM_OUTPUT_TD2:
bogdanm 0:9b334a45a8ff 3219 case HRTIM_OUTPUT_TE2:
bogdanm 0:9b334a45a8ff 3220 {
bogdanm 0:9b334a45a8ff 3221 if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != RESET)
bogdanm 0:9b334a45a8ff 3222 {
bogdanm 0:9b334a45a8ff 3223 /* Output 2 was active when the delayed idle protection was triggered */
bogdanm 0:9b334a45a8ff 3224 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
bogdanm 0:9b334a45a8ff 3225 }
bogdanm 0:9b334a45a8ff 3226 else
bogdanm 0:9b334a45a8ff 3227 {
bogdanm 0:9b334a45a8ff 3228 /* Output 2 was inactive when the delayed idle protection was triggered */
bogdanm 0:9b334a45a8ff 3229 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
bogdanm 0:9b334a45a8ff 3230 }
bogdanm 0:9b334a45a8ff 3231 }
bogdanm 0:9b334a45a8ff 3232 break;
bogdanm 0:9b334a45a8ff 3233 default:
bogdanm 0:9b334a45a8ff 3234 break;
bogdanm 0:9b334a45a8ff 3235 }
bogdanm 0:9b334a45a8ff 3236
bogdanm 0:9b334a45a8ff 3237 return delayed_protection_status;
bogdanm 0:9b334a45a8ff 3238 }
bogdanm 0:9b334a45a8ff 3239
bogdanm 0:9b334a45a8ff 3240 /**
bogdanm 0:9b334a45a8ff 3241 * @brief Returns the actual status (active or inactive) of the burst mode controller
bogdanm 0:9b334a45a8ff 3242 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 3243 * @retval Burst mode controller status
bogdanm 0:9b334a45a8ff 3244 */
bogdanm 0:9b334a45a8ff 3245 uint32_t HRTIM_GetBurstStatus(HRTIM_TypeDef * HRTIMx)
bogdanm 0:9b334a45a8ff 3246 {
bogdanm 0:9b334a45a8ff 3247 uint32_t burst_mode_status;
bogdanm 0:9b334a45a8ff 3248
bogdanm 0:9b334a45a8ff 3249 /* Read burst mode status */
bogdanm 0:9b334a45a8ff 3250 burst_mode_status = (HRTIMx->HRTIM_COMMON.BMCR & HRTIM_BMCR_BMSTAT);
bogdanm 0:9b334a45a8ff 3251
bogdanm 0:9b334a45a8ff 3252 return burst_mode_status;
bogdanm 0:9b334a45a8ff 3253 }
bogdanm 0:9b334a45a8ff 3254
bogdanm 0:9b334a45a8ff 3255 /**
bogdanm 0:9b334a45a8ff 3256 * @brief Indicates on which output the signal is currently active (when the
bogdanm 0:9b334a45a8ff 3257 * push pull mode is enabled)
bogdanm 0:9b334a45a8ff 3258 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 3259 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 3260 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 3261 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 3262 * @retval Burst mode controller status
bogdanm 0:9b334a45a8ff 3263 */
bogdanm 0:9b334a45a8ff 3264 uint32_t HRTIM_GetCurrentPushPullStatus(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 3265 uint32_t TimerIdx)
bogdanm 0:9b334a45a8ff 3266 {
bogdanm 0:9b334a45a8ff 3267 uint32_t current_pushpull_status;
bogdanm 0:9b334a45a8ff 3268
bogdanm 0:9b334a45a8ff 3269 /* Check the parameters */
bogdanm 0:9b334a45a8ff 3270 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
bogdanm 0:9b334a45a8ff 3271
bogdanm 0:9b334a45a8ff 3272 /* Read current push pull status */
bogdanm 0:9b334a45a8ff 3273 current_pushpull_status = (HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
bogdanm 0:9b334a45a8ff 3274
bogdanm 0:9b334a45a8ff 3275 return current_pushpull_status;
bogdanm 0:9b334a45a8ff 3276 }
bogdanm 0:9b334a45a8ff 3277
bogdanm 0:9b334a45a8ff 3278
bogdanm 0:9b334a45a8ff 3279 /**
bogdanm 0:9b334a45a8ff 3280 * @brief Indicates on which output the signal was applied, in push-pull mode
bogdanm 0:9b334a45a8ff 3281 balanced fault mode or delayed idle mode, when the protection was triggered
bogdanm 0:9b334a45a8ff 3282 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 3283 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 3284 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 3285 * @arg 0x0 to 0x4 for timers A to E
bogdanm 0:9b334a45a8ff 3286 * @retval Idle Push Pull Status
bogdanm 0:9b334a45a8ff 3287 */
bogdanm 0:9b334a45a8ff 3288 uint32_t HRTIM_GetIdlePushPullStatus(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 3289 uint32_t TimerIdx)
bogdanm 0:9b334a45a8ff 3290 {
bogdanm 0:9b334a45a8ff 3291 uint32_t idle_pushpull_status;
bogdanm 0:9b334a45a8ff 3292
bogdanm 0:9b334a45a8ff 3293 /* Check the parameters */
bogdanm 0:9b334a45a8ff 3294 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
bogdanm 0:9b334a45a8ff 3295
bogdanm 0:9b334a45a8ff 3296 /* Read current push pull status */
bogdanm 0:9b334a45a8ff 3297 idle_pushpull_status = (HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
bogdanm 0:9b334a45a8ff 3298
bogdanm 0:9b334a45a8ff 3299 return idle_pushpull_status;
bogdanm 0:9b334a45a8ff 3300 }
bogdanm 0:9b334a45a8ff 3301
bogdanm 0:9b334a45a8ff 3302 /**
bogdanm 0:9b334a45a8ff 3303 * @brief Configures the master timer time base
bogdanm 0:9b334a45a8ff 3304 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 3305 * @retval None
bogdanm 0:9b334a45a8ff 3306 */
bogdanm 0:9b334a45a8ff 3307 void HRTIM_MasterBase_Config(HRTIM_TypeDef * HRTIMx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
bogdanm 0:9b334a45a8ff 3308 {
bogdanm 0:9b334a45a8ff 3309 /* Set the prescaler ratio */
bogdanm 0:9b334a45a8ff 3310 HRTIMx->HRTIM_MASTER.MCR &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
bogdanm 0:9b334a45a8ff 3311 HRTIMx->HRTIM_MASTER.MCR |= (uint32_t)HRTIM_BaseInitStruct->PrescalerRatio;
bogdanm 0:9b334a45a8ff 3312
bogdanm 0:9b334a45a8ff 3313 /* Set the operating mode */
bogdanm 0:9b334a45a8ff 3314 HRTIMx->HRTIM_MASTER.MCR &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
bogdanm 0:9b334a45a8ff 3315 HRTIMx->HRTIM_MASTER.MCR |= (uint32_t)HRTIM_BaseInitStruct->Mode;
bogdanm 0:9b334a45a8ff 3316
bogdanm 0:9b334a45a8ff 3317 /* Update the HRTIMx registers */
bogdanm 0:9b334a45a8ff 3318 HRTIMx->HRTIM_MASTER.MPER = HRTIM_BaseInitStruct->Period;
bogdanm 0:9b334a45a8ff 3319 HRTIMx->HRTIM_MASTER.MREP = HRTIM_BaseInitStruct->RepetitionCounter;
bogdanm 0:9b334a45a8ff 3320 }
bogdanm 0:9b334a45a8ff 3321
bogdanm 0:9b334a45a8ff 3322 /**
bogdanm 0:9b334a45a8ff 3323 * @brief Configures timing unit (timer A to timer E) time base
bogdanm 0:9b334a45a8ff 3324 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 3325 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 3326 * @retval None
bogdanm 0:9b334a45a8ff 3327 */
bogdanm 0:9b334a45a8ff 3328 void HRTIM_TimingUnitBase_Config(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
bogdanm 0:9b334a45a8ff 3329 {
bogdanm 0:9b334a45a8ff 3330 /* Set the prescaler ratio */
bogdanm 0:9b334a45a8ff 3331 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
bogdanm 0:9b334a45a8ff 3332 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR |= (uint32_t)HRTIM_BaseInitStruct->PrescalerRatio;
bogdanm 0:9b334a45a8ff 3333
bogdanm 0:9b334a45a8ff 3334 /* Set the operating mode */
bogdanm 0:9b334a45a8ff 3335 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
bogdanm 0:9b334a45a8ff 3336 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR |= (uint32_t)HRTIM_BaseInitStruct->Mode;
bogdanm 0:9b334a45a8ff 3337
bogdanm 0:9b334a45a8ff 3338 /* Update the HRTIMx registers */
bogdanm 0:9b334a45a8ff 3339 HRTIMx->HRTIM_TIMERx[TimerIdx].PERxR = HRTIM_BaseInitStruct->Period;
bogdanm 0:9b334a45a8ff 3340 HRTIMx->HRTIM_TIMERx[TimerIdx].REPxR = HRTIM_BaseInitStruct->RepetitionCounter;
bogdanm 0:9b334a45a8ff 3341 }
bogdanm 0:9b334a45a8ff 3342
bogdanm 0:9b334a45a8ff 3343 /**
bogdanm 0:9b334a45a8ff 3344 * @brief Configures the master timer in waveform mode
bogdanm 0:9b334a45a8ff 3345 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 3346 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 3347 * @param pTimerInit: pointer to the timer initialization data structure
bogdanm 0:9b334a45a8ff 3348 * @retval None
bogdanm 0:9b334a45a8ff 3349 */
bogdanm 0:9b334a45a8ff 3350 void HRTIM_MasterWaveform_Config(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 3351 HRTIM_TimerInitTypeDef * pTimerInit)
bogdanm 0:9b334a45a8ff 3352 {
bogdanm 0:9b334a45a8ff 3353 uint32_t HRTIM_mcr;
bogdanm 0:9b334a45a8ff 3354 uint32_t HRTIM_bmcr;
bogdanm 0:9b334a45a8ff 3355
bogdanm 0:9b334a45a8ff 3356 /* Configure master timer */
bogdanm 0:9b334a45a8ff 3357 HRTIM_mcr = HRTIMx->HRTIM_MASTER.MCR;
bogdanm 0:9b334a45a8ff 3358 HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
bogdanm 0:9b334a45a8ff 3359
bogdanm 0:9b334a45a8ff 3360 /* Enable/Disable the half mode */
bogdanm 0:9b334a45a8ff 3361 HRTIM_mcr &= ~(HRTIM_MCR_HALF);
bogdanm 0:9b334a45a8ff 3362 HRTIM_mcr |= pTimerInit->HalfModeEnable;
bogdanm 0:9b334a45a8ff 3363
bogdanm 0:9b334a45a8ff 3364 /* Enable/Disable the timer start upon synchronization event reception */
bogdanm 0:9b334a45a8ff 3365 HRTIM_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
bogdanm 0:9b334a45a8ff 3366 HRTIM_mcr |= pTimerInit->StartOnSync;
bogdanm 0:9b334a45a8ff 3367
bogdanm 0:9b334a45a8ff 3368 /* Enable/Disable the timer reset upon synchronization event reception */
bogdanm 0:9b334a45a8ff 3369 HRTIM_mcr &= ~(HRTIM_MCR_SYNCRSTM);
bogdanm 0:9b334a45a8ff 3370 HRTIM_mcr |= pTimerInit->ResetOnSync;
bogdanm 0:9b334a45a8ff 3371
bogdanm 0:9b334a45a8ff 3372 /* Enable/Disable the DAC synchronization event generation */
bogdanm 0:9b334a45a8ff 3373 HRTIM_mcr &= ~(HRTIM_MCR_DACSYNC);
bogdanm 0:9b334a45a8ff 3374 HRTIM_mcr |= pTimerInit->DACSynchro;
bogdanm 0:9b334a45a8ff 3375
bogdanm 0:9b334a45a8ff 3376 /* Enable/Disable preload mechanism for timer registers */
bogdanm 0:9b334a45a8ff 3377 HRTIM_mcr &= ~(HRTIM_MCR_PREEN);
bogdanm 0:9b334a45a8ff 3378 HRTIM_mcr |= pTimerInit->PreloadEnable;
bogdanm 0:9b334a45a8ff 3379
bogdanm 0:9b334a45a8ff 3380 /* Master timer registers update handling */
bogdanm 0:9b334a45a8ff 3381 HRTIM_mcr &= ~(HRTIM_MCR_BRSTDMA);
bogdanm 0:9b334a45a8ff 3382 HRTIM_mcr |= (pTimerInit->UpdateGating << 2);
bogdanm 0:9b334a45a8ff 3383
bogdanm 0:9b334a45a8ff 3384 /* Enable/Disable registers update on repetition */
bogdanm 0:9b334a45a8ff 3385 HRTIM_mcr &= ~(HRTIM_MCR_MREPU);
bogdanm 0:9b334a45a8ff 3386 HRTIM_mcr |= pTimerInit->RepetitionUpdate;
bogdanm 0:9b334a45a8ff 3387
bogdanm 0:9b334a45a8ff 3388 /* Set the timer burst mode */
bogdanm 0:9b334a45a8ff 3389 HRTIM_bmcr &= ~(HRTIM_BMCR_MTBM);
bogdanm 0:9b334a45a8ff 3390 HRTIM_bmcr |= pTimerInit->BurstMode;
bogdanm 0:9b334a45a8ff 3391
bogdanm 0:9b334a45a8ff 3392 /* Update the HRTIMx registers */
bogdanm 0:9b334a45a8ff 3393 HRTIMx->HRTIM_MASTER.MCR = HRTIM_mcr;
bogdanm 0:9b334a45a8ff 3394 HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
bogdanm 0:9b334a45a8ff 3395
bogdanm 0:9b334a45a8ff 3396 }
bogdanm 0:9b334a45a8ff 3397
bogdanm 0:9b334a45a8ff 3398 /**
bogdanm 0:9b334a45a8ff 3399 * @brief Configures timing unit (timer A to timer E) in waveform mode
bogdanm 0:9b334a45a8ff 3400 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 3401 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 3402 * @param pTimerInit: pointer to the timer initialization data structure
bogdanm 0:9b334a45a8ff 3403 * @retval None
bogdanm 0:9b334a45a8ff 3404 */
bogdanm 0:9b334a45a8ff 3405 void HRTIM_TimingUnitWaveform_Config(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 3406 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 3407 HRTIM_TimerInitTypeDef * pTimerInit)
bogdanm 0:9b334a45a8ff 3408 {
bogdanm 0:9b334a45a8ff 3409 uint32_t HRTIM_timcr;
bogdanm 0:9b334a45a8ff 3410 uint32_t HRTIM_bmcr;
bogdanm 0:9b334a45a8ff 3411
bogdanm 0:9b334a45a8ff 3412 /* Configure timing unit */
bogdanm 0:9b334a45a8ff 3413 HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
bogdanm 0:9b334a45a8ff 3414 HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
bogdanm 0:9b334a45a8ff 3415
bogdanm 0:9b334a45a8ff 3416 /* Enable/Disable the half mode */
bogdanm 0:9b334a45a8ff 3417 HRTIM_timcr &= ~(HRTIM_TIMCR_HALF);
bogdanm 0:9b334a45a8ff 3418 HRTIM_timcr |= pTimerInit->HalfModeEnable;
bogdanm 0:9b334a45a8ff 3419
bogdanm 0:9b334a45a8ff 3420 /* Enable/Disable the timer start upon synchronization event reception */
bogdanm 0:9b334a45a8ff 3421 HRTIM_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
bogdanm 0:9b334a45a8ff 3422 HRTIM_timcr |= pTimerInit->StartOnSync;
bogdanm 0:9b334a45a8ff 3423
bogdanm 0:9b334a45a8ff 3424 /* Enable/Disable the timer reset upon synchronization event reception */
bogdanm 0:9b334a45a8ff 3425 HRTIM_timcr &= ~(HRTIM_TIMCR_SYNCRST);
bogdanm 0:9b334a45a8ff 3426 HRTIM_timcr |= pTimerInit->ResetOnSync;
bogdanm 0:9b334a45a8ff 3427
bogdanm 0:9b334a45a8ff 3428 /* Enable/Disable the DAC synchronization event generation */
bogdanm 0:9b334a45a8ff 3429 HRTIM_timcr &= ~(HRTIM_TIMCR_DACSYNC);
bogdanm 0:9b334a45a8ff 3430 HRTIM_timcr |= pTimerInit->DACSynchro;
bogdanm 0:9b334a45a8ff 3431
bogdanm 0:9b334a45a8ff 3432 /* Enable/Disable preload mechanism for timer registers */
bogdanm 0:9b334a45a8ff 3433 HRTIM_timcr &= ~(HRTIM_TIMCR_PREEN);
bogdanm 0:9b334a45a8ff 3434 HRTIM_timcr |= pTimerInit->PreloadEnable;
bogdanm 0:9b334a45a8ff 3435
bogdanm 0:9b334a45a8ff 3436 /* Timing unit registers update handling */
bogdanm 0:9b334a45a8ff 3437 HRTIM_timcr &= ~(HRTIM_TIMCR_UPDGAT);
bogdanm 0:9b334a45a8ff 3438 HRTIM_timcr |= pTimerInit->UpdateGating;
bogdanm 0:9b334a45a8ff 3439
bogdanm 0:9b334a45a8ff 3440 /* Enable/Disable registers update on repetition */
bogdanm 0:9b334a45a8ff 3441 HRTIM_timcr &= ~(HRTIM_TIMCR_TREPU);
bogdanm 0:9b334a45a8ff 3442 if (pTimerInit->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
bogdanm 0:9b334a45a8ff 3443 {
bogdanm 0:9b334a45a8ff 3444 HRTIM_timcr |= HRTIM_TIMCR_TREPU;
bogdanm 0:9b334a45a8ff 3445 }
bogdanm 0:9b334a45a8ff 3446
bogdanm 0:9b334a45a8ff 3447 /* Set the timer burst mode */
bogdanm 0:9b334a45a8ff 3448 switch (TimerIdx)
bogdanm 0:9b334a45a8ff 3449 {
bogdanm 0:9b334a45a8ff 3450 case HRTIM_TIMERINDEX_TIMER_A:
bogdanm 0:9b334a45a8ff 3451 {
bogdanm 0:9b334a45a8ff 3452 HRTIM_bmcr &= ~(HRTIM_BMCR_TABM);
bogdanm 0:9b334a45a8ff 3453 HRTIM_bmcr |= ( pTimerInit->BurstMode << 1);
bogdanm 0:9b334a45a8ff 3454 }
bogdanm 0:9b334a45a8ff 3455 break;
bogdanm 0:9b334a45a8ff 3456 case HRTIM_TIMERINDEX_TIMER_B:
bogdanm 0:9b334a45a8ff 3457 {
bogdanm 0:9b334a45a8ff 3458 HRTIM_bmcr &= ~(HRTIM_BMCR_TBBM);
bogdanm 0:9b334a45a8ff 3459 HRTIM_bmcr |= ( pTimerInit->BurstMode << 2);
bogdanm 0:9b334a45a8ff 3460 }
bogdanm 0:9b334a45a8ff 3461 break;
bogdanm 0:9b334a45a8ff 3462 case HRTIM_TIMERINDEX_TIMER_C:
bogdanm 0:9b334a45a8ff 3463 {
bogdanm 0:9b334a45a8ff 3464 HRTIM_bmcr &= ~(HRTIM_BMCR_TCBM);
bogdanm 0:9b334a45a8ff 3465 HRTIM_bmcr |= ( pTimerInit->BurstMode << 3);
bogdanm 0:9b334a45a8ff 3466 }
bogdanm 0:9b334a45a8ff 3467 break;
bogdanm 0:9b334a45a8ff 3468 case HRTIM_TIMERINDEX_TIMER_D:
bogdanm 0:9b334a45a8ff 3469 {
bogdanm 0:9b334a45a8ff 3470 HRTIM_bmcr &= ~(HRTIM_BMCR_TDBM);
bogdanm 0:9b334a45a8ff 3471 HRTIM_bmcr |= ( pTimerInit->BurstMode << 4);
bogdanm 0:9b334a45a8ff 3472 }
bogdanm 0:9b334a45a8ff 3473 break;
bogdanm 0:9b334a45a8ff 3474 case HRTIM_TIMERINDEX_TIMER_E:
bogdanm 0:9b334a45a8ff 3475 {
bogdanm 0:9b334a45a8ff 3476 HRTIM_bmcr &= ~(HRTIM_BMCR_TEBM);
bogdanm 0:9b334a45a8ff 3477 HRTIM_bmcr |= ( pTimerInit->BurstMode << 5);
bogdanm 0:9b334a45a8ff 3478 }
bogdanm 0:9b334a45a8ff 3479 break;
bogdanm 0:9b334a45a8ff 3480 default:
bogdanm 0:9b334a45a8ff 3481 break;
bogdanm 0:9b334a45a8ff 3482 }
bogdanm 0:9b334a45a8ff 3483
bogdanm 0:9b334a45a8ff 3484 /* Update the HRTIMx registers */
bogdanm 0:9b334a45a8ff 3485 HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
bogdanm 0:9b334a45a8ff 3486 HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
bogdanm 0:9b334a45a8ff 3487 }
bogdanm 0:9b334a45a8ff 3488
bogdanm 0:9b334a45a8ff 3489 /**
bogdanm 0:9b334a45a8ff 3490 * @brief Configures a compare unit
bogdanm 0:9b334a45a8ff 3491 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 3492 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 3493 * @param CompareUnit: Compare unit identifier
bogdanm 0:9b334a45a8ff 3494 * @param pCompareCfg: pointer to the compare unit configuration data structure
bogdanm 0:9b334a45a8ff 3495 * @retval None
bogdanm 0:9b334a45a8ff 3496 */
bogdanm 0:9b334a45a8ff 3497 void HRTIM_CompareUnitConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 3498 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 3499 uint32_t CompareUnit,
bogdanm 0:9b334a45a8ff 3500 HRTIM_CompareCfgTypeDef * pCompareCfg)
bogdanm 0:9b334a45a8ff 3501 {
bogdanm 0:9b334a45a8ff 3502 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
bogdanm 0:9b334a45a8ff 3503 {
bogdanm 0:9b334a45a8ff 3504 /* Configure the compare unit of the master timer */
bogdanm 0:9b334a45a8ff 3505 switch (CompareUnit)
bogdanm 0:9b334a45a8ff 3506 {
bogdanm 0:9b334a45a8ff 3507 case HRTIM_COMPAREUNIT_1:
bogdanm 0:9b334a45a8ff 3508 {
bogdanm 0:9b334a45a8ff 3509 HRTIMx->HRTIM_MASTER.MCMP1R = pCompareCfg->CompareValue;
bogdanm 0:9b334a45a8ff 3510 }
bogdanm 0:9b334a45a8ff 3511 break;
bogdanm 0:9b334a45a8ff 3512 case HRTIM_COMPAREUNIT_2:
bogdanm 0:9b334a45a8ff 3513 {
bogdanm 0:9b334a45a8ff 3514 HRTIMx->HRTIM_MASTER.MCMP2R = pCompareCfg->CompareValue;
bogdanm 0:9b334a45a8ff 3515 }
bogdanm 0:9b334a45a8ff 3516 break;
bogdanm 0:9b334a45a8ff 3517 case HRTIM_COMPAREUNIT_3:
bogdanm 0:9b334a45a8ff 3518 {
bogdanm 0:9b334a45a8ff 3519 HRTIMx->HRTIM_MASTER.MCMP3R = pCompareCfg->CompareValue;
bogdanm 0:9b334a45a8ff 3520 }
bogdanm 0:9b334a45a8ff 3521 break;
bogdanm 0:9b334a45a8ff 3522 case HRTIM_COMPAREUNIT_4:
bogdanm 0:9b334a45a8ff 3523 {
bogdanm 0:9b334a45a8ff 3524 HRTIMx->HRTIM_MASTER.MCMP4R = pCompareCfg->CompareValue;
bogdanm 0:9b334a45a8ff 3525 }
bogdanm 0:9b334a45a8ff 3526 break;
bogdanm 0:9b334a45a8ff 3527 default:
bogdanm 0:9b334a45a8ff 3528 break;
bogdanm 0:9b334a45a8ff 3529 }
bogdanm 0:9b334a45a8ff 3530 }
bogdanm 0:9b334a45a8ff 3531 else
bogdanm 0:9b334a45a8ff 3532 {
bogdanm 0:9b334a45a8ff 3533 /* Configure the compare unit of the timing unit */
bogdanm 0:9b334a45a8ff 3534 switch (CompareUnit)
bogdanm 0:9b334a45a8ff 3535 {
bogdanm 0:9b334a45a8ff 3536 case HRTIM_COMPAREUNIT_1:
bogdanm 0:9b334a45a8ff 3537 {
bogdanm 0:9b334a45a8ff 3538 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
bogdanm 0:9b334a45a8ff 3539 }
bogdanm 0:9b334a45a8ff 3540 break;
bogdanm 0:9b334a45a8ff 3541 case HRTIM_COMPAREUNIT_2:
bogdanm 0:9b334a45a8ff 3542 {
bogdanm 0:9b334a45a8ff 3543 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
bogdanm 0:9b334a45a8ff 3544 }
bogdanm 0:9b334a45a8ff 3545 break;
bogdanm 0:9b334a45a8ff 3546 case HRTIM_COMPAREUNIT_3:
bogdanm 0:9b334a45a8ff 3547 {
bogdanm 0:9b334a45a8ff 3548 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
bogdanm 0:9b334a45a8ff 3549 }
bogdanm 0:9b334a45a8ff 3550 break;
bogdanm 0:9b334a45a8ff 3551 case HRTIM_COMPAREUNIT_4:
bogdanm 0:9b334a45a8ff 3552 {
bogdanm 0:9b334a45a8ff 3553 HRTIMx->HRTIM_TIMERx[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
bogdanm 0:9b334a45a8ff 3554 }
bogdanm 0:9b334a45a8ff 3555 break;
bogdanm 0:9b334a45a8ff 3556 default:
bogdanm 0:9b334a45a8ff 3557 break;
bogdanm 0:9b334a45a8ff 3558 }
bogdanm 0:9b334a45a8ff 3559 }
bogdanm 0:9b334a45a8ff 3560 }
bogdanm 0:9b334a45a8ff 3561
bogdanm 0:9b334a45a8ff 3562 /**
bogdanm 0:9b334a45a8ff 3563 * @brief Configures a capture unit
bogdanm 0:9b334a45a8ff 3564 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 3565 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 3566 * @param CaptureUnit: Capture unit identifier
bogdanm 0:9b334a45a8ff 3567 * @param pCaptureCfg: pointer to the compare unit configuration data structure
bogdanm 0:9b334a45a8ff 3568 * @retval None
bogdanm 0:9b334a45a8ff 3569 */
bogdanm 0:9b334a45a8ff 3570 void HRTIM_CaptureUnitConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 3571 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 3572 uint32_t CaptureUnit,
bogdanm 0:9b334a45a8ff 3573 uint32_t Event)
bogdanm 0:9b334a45a8ff 3574 {
bogdanm 0:9b334a45a8ff 3575 uint32_t CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
bogdanm 0:9b334a45a8ff 3576
bogdanm 0:9b334a45a8ff 3577 switch (Event)
bogdanm 0:9b334a45a8ff 3578 {
bogdanm 0:9b334a45a8ff 3579 case HRTIM_EVENT_1:
bogdanm 0:9b334a45a8ff 3580 {
bogdanm 0:9b334a45a8ff 3581 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
bogdanm 0:9b334a45a8ff 3582 }
bogdanm 0:9b334a45a8ff 3583 break;
bogdanm 0:9b334a45a8ff 3584 case HRTIM_EVENT_2:
bogdanm 0:9b334a45a8ff 3585 {
bogdanm 0:9b334a45a8ff 3586 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
bogdanm 0:9b334a45a8ff 3587 }
bogdanm 0:9b334a45a8ff 3588 break;
bogdanm 0:9b334a45a8ff 3589 case HRTIM_EVENT_3:
bogdanm 0:9b334a45a8ff 3590 {
bogdanm 0:9b334a45a8ff 3591 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
bogdanm 0:9b334a45a8ff 3592 }
bogdanm 0:9b334a45a8ff 3593 break;
bogdanm 0:9b334a45a8ff 3594 case HRTIM_EVENT_4:
bogdanm 0:9b334a45a8ff 3595 {
bogdanm 0:9b334a45a8ff 3596 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
bogdanm 0:9b334a45a8ff 3597 }
bogdanm 0:9b334a45a8ff 3598 break;
bogdanm 0:9b334a45a8ff 3599 case HRTIM_EVENT_5:
bogdanm 0:9b334a45a8ff 3600 {
bogdanm 0:9b334a45a8ff 3601 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
bogdanm 0:9b334a45a8ff 3602 }
bogdanm 0:9b334a45a8ff 3603 break;
bogdanm 0:9b334a45a8ff 3604 case HRTIM_EVENT_6:
bogdanm 0:9b334a45a8ff 3605 {
bogdanm 0:9b334a45a8ff 3606 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
bogdanm 0:9b334a45a8ff 3607 }
bogdanm 0:9b334a45a8ff 3608 break;
bogdanm 0:9b334a45a8ff 3609 case HRTIM_EVENT_7:
bogdanm 0:9b334a45a8ff 3610 {
bogdanm 0:9b334a45a8ff 3611 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
bogdanm 0:9b334a45a8ff 3612 }
bogdanm 0:9b334a45a8ff 3613 break;
bogdanm 0:9b334a45a8ff 3614 case HRTIM_EVENT_8:
bogdanm 0:9b334a45a8ff 3615 {
bogdanm 0:9b334a45a8ff 3616 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
bogdanm 0:9b334a45a8ff 3617 }
bogdanm 0:9b334a45a8ff 3618 break;
bogdanm 0:9b334a45a8ff 3619 case HRTIM_EVENT_9:
bogdanm 0:9b334a45a8ff 3620 {
bogdanm 0:9b334a45a8ff 3621 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
bogdanm 0:9b334a45a8ff 3622 }
bogdanm 0:9b334a45a8ff 3623 break;
bogdanm 0:9b334a45a8ff 3624 case HRTIM_EVENT_10:
bogdanm 0:9b334a45a8ff 3625 {
bogdanm 0:9b334a45a8ff 3626 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
bogdanm 0:9b334a45a8ff 3627 }
bogdanm 0:9b334a45a8ff 3628 break;
bogdanm 0:9b334a45a8ff 3629 default:
bogdanm 0:9b334a45a8ff 3630 break;
bogdanm 0:9b334a45a8ff 3631
bogdanm 0:9b334a45a8ff 3632 }
bogdanm 0:9b334a45a8ff 3633 switch (CaptureUnit)
bogdanm 0:9b334a45a8ff 3634 {
bogdanm 0:9b334a45a8ff 3635 case HRTIM_CAPTUREUNIT_1:
bogdanm 0:9b334a45a8ff 3636 {
bogdanm 0:9b334a45a8ff 3637 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = CaptureTrigger;
bogdanm 0:9b334a45a8ff 3638 }
bogdanm 0:9b334a45a8ff 3639 break;
bogdanm 0:9b334a45a8ff 3640 case HRTIM_CAPTUREUNIT_2:
bogdanm 0:9b334a45a8ff 3641 {
bogdanm 0:9b334a45a8ff 3642 HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = CaptureTrigger;
bogdanm 0:9b334a45a8ff 3643 }
bogdanm 0:9b334a45a8ff 3644 break;
bogdanm 0:9b334a45a8ff 3645 default:
bogdanm 0:9b334a45a8ff 3646 break;
bogdanm 0:9b334a45a8ff 3647 }
bogdanm 0:9b334a45a8ff 3648 }
bogdanm 0:9b334a45a8ff 3649
bogdanm 0:9b334a45a8ff 3650 /**
bogdanm 0:9b334a45a8ff 3651 * @brief Configures the output of a timing unit
bogdanm 0:9b334a45a8ff 3652 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 3653 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 3654 * @param Output: timing unit output identifier
bogdanm 0:9b334a45a8ff 3655 * @param pOutputCfg: pointer to the output configuration data structure
bogdanm 0:9b334a45a8ff 3656 * @retval None
bogdanm 0:9b334a45a8ff 3657 */
bogdanm 0:9b334a45a8ff 3658 void HRTIM_OutputConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 3659 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 3660 uint32_t Output,
bogdanm 0:9b334a45a8ff 3661 HRTIM_OutputCfgTypeDef * pOutputCfg)
bogdanm 0:9b334a45a8ff 3662 {
bogdanm 0:9b334a45a8ff 3663 uint32_t HRTIM_outr;
bogdanm 0:9b334a45a8ff 3664 uint32_t shift = 0;
bogdanm 0:9b334a45a8ff 3665
bogdanm 0:9b334a45a8ff 3666 HRTIM_outr = HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR;
bogdanm 0:9b334a45a8ff 3667
bogdanm 0:9b334a45a8ff 3668 switch (Output)
bogdanm 0:9b334a45a8ff 3669 {
bogdanm 0:9b334a45a8ff 3670 case HRTIM_OUTPUT_TA1:
bogdanm 0:9b334a45a8ff 3671 case HRTIM_OUTPUT_TB1:
bogdanm 0:9b334a45a8ff 3672 case HRTIM_OUTPUT_TC1:
bogdanm 0:9b334a45a8ff 3673 case HRTIM_OUTPUT_TD1:
bogdanm 0:9b334a45a8ff 3674 case HRTIM_OUTPUT_TE1:
bogdanm 0:9b334a45a8ff 3675 {
bogdanm 0:9b334a45a8ff 3676 /* Set the output set/reset crossbar */
bogdanm 0:9b334a45a8ff 3677 HRTIMx->HRTIM_TIMERx[TimerIdx].SETx1R = pOutputCfg->SetSource;
bogdanm 0:9b334a45a8ff 3678 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
bogdanm 0:9b334a45a8ff 3679
bogdanm 0:9b334a45a8ff 3680 shift = 0;
bogdanm 0:9b334a45a8ff 3681 }
bogdanm 0:9b334a45a8ff 3682 break;
bogdanm 0:9b334a45a8ff 3683 case HRTIM_OUTPUT_TA2:
bogdanm 0:9b334a45a8ff 3684 case HRTIM_OUTPUT_TB2:
bogdanm 0:9b334a45a8ff 3685 case HRTIM_OUTPUT_TC2:
bogdanm 0:9b334a45a8ff 3686 case HRTIM_OUTPUT_TD2:
bogdanm 0:9b334a45a8ff 3687 case HRTIM_OUTPUT_TE2:
bogdanm 0:9b334a45a8ff 3688 {
bogdanm 0:9b334a45a8ff 3689 /* Set the output set/reset crossbar */
bogdanm 0:9b334a45a8ff 3690 HRTIMx->HRTIM_TIMERx[TimerIdx].SETx2R = pOutputCfg->SetSource;
bogdanm 0:9b334a45a8ff 3691 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
bogdanm 0:9b334a45a8ff 3692
bogdanm 0:9b334a45a8ff 3693 shift = 16;
bogdanm 0:9b334a45a8ff 3694 }
bogdanm 0:9b334a45a8ff 3695 break;
bogdanm 0:9b334a45a8ff 3696 default:
bogdanm 0:9b334a45a8ff 3697 break;
bogdanm 0:9b334a45a8ff 3698 }
bogdanm 0:9b334a45a8ff 3699
bogdanm 0:9b334a45a8ff 3700 /* Clear output config */
bogdanm 0:9b334a45a8ff 3701 HRTIM_outr &= ~((HRTIM_OUTR_POL1 |
bogdanm 0:9b334a45a8ff 3702 HRTIM_OUTR_IDLM1 |
bogdanm 0:9b334a45a8ff 3703 HRTIM_OUTR_IDLES1|
bogdanm 0:9b334a45a8ff 3704 HRTIM_OUTR_FAULT1|
bogdanm 0:9b334a45a8ff 3705 HRTIM_OUTR_CHP1 |
bogdanm 0:9b334a45a8ff 3706 HRTIM_OUTR_DIDL1) << shift);
bogdanm 0:9b334a45a8ff 3707
bogdanm 0:9b334a45a8ff 3708 /* Set the polarity */
bogdanm 0:9b334a45a8ff 3709 HRTIM_outr |= (pOutputCfg->Polarity << shift);
bogdanm 0:9b334a45a8ff 3710
bogdanm 0:9b334a45a8ff 3711 /* Set the IDLE mode */
bogdanm 0:9b334a45a8ff 3712 HRTIM_outr |= (pOutputCfg->IdleMode << shift);
bogdanm 0:9b334a45a8ff 3713
bogdanm 0:9b334a45a8ff 3714 /* Set the IDLE state */
bogdanm 0:9b334a45a8ff 3715 HRTIM_outr |= (pOutputCfg->IdleState << shift);
bogdanm 0:9b334a45a8ff 3716
bogdanm 0:9b334a45a8ff 3717 /* Set the FAULT state */
bogdanm 0:9b334a45a8ff 3718 HRTIM_outr |= (pOutputCfg->FaultState << shift);
bogdanm 0:9b334a45a8ff 3719
bogdanm 0:9b334a45a8ff 3720 /* Set the chopper mode */
bogdanm 0:9b334a45a8ff 3721 HRTIM_outr |= (pOutputCfg->ChopperModeEnable << shift);
bogdanm 0:9b334a45a8ff 3722
bogdanm 0:9b334a45a8ff 3723 /* Set the burst mode entry mode */
bogdanm 0:9b334a45a8ff 3724 HRTIM_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
bogdanm 0:9b334a45a8ff 3725
bogdanm 0:9b334a45a8ff 3726 /* Update HRTIMx register */
bogdanm 0:9b334a45a8ff 3727 HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR = HRTIM_outr;
bogdanm 0:9b334a45a8ff 3728 }
bogdanm 0:9b334a45a8ff 3729
bogdanm 0:9b334a45a8ff 3730 /**
bogdanm 0:9b334a45a8ff 3731 * @brief Configures an external event channel
bogdanm 0:9b334a45a8ff 3732 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 3733 * @param Event: Event channel identifier
bogdanm 0:9b334a45a8ff 3734 * @param pEventCfg: pointer to the event channel configuration data structure
bogdanm 0:9b334a45a8ff 3735 * @retval None
bogdanm 0:9b334a45a8ff 3736 */
bogdanm 0:9b334a45a8ff 3737 static void HRTIM_ExternalEventConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 3738 uint32_t Event,
bogdanm 0:9b334a45a8ff 3739 HRTIM_EventCfgTypeDef *pEventCfg)
bogdanm 0:9b334a45a8ff 3740 {
bogdanm 0:9b334a45a8ff 3741 uint32_t hrtim_eecr1;
bogdanm 0:9b334a45a8ff 3742 uint32_t hrtim_eecr2;
bogdanm 0:9b334a45a8ff 3743 uint32_t hrtim_eecr3;
bogdanm 0:9b334a45a8ff 3744
bogdanm 0:9b334a45a8ff 3745 /* Configure external event channel */
bogdanm 0:9b334a45a8ff 3746 hrtim_eecr1 = HRTIMx->HRTIM_COMMON.EECR1;
bogdanm 0:9b334a45a8ff 3747 hrtim_eecr2 = HRTIMx->HRTIM_COMMON.EECR2;
bogdanm 0:9b334a45a8ff 3748 hrtim_eecr3 = HRTIMx->HRTIM_COMMON.EECR3;
bogdanm 0:9b334a45a8ff 3749
bogdanm 0:9b334a45a8ff 3750 switch (Event)
bogdanm 0:9b334a45a8ff 3751 {
bogdanm 0:9b334a45a8ff 3752 case HRTIM_EVENT_1:
bogdanm 0:9b334a45a8ff 3753 {
bogdanm 0:9b334a45a8ff 3754 hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
bogdanm 0:9b334a45a8ff 3755 hrtim_eecr1 |= pEventCfg->Source;
bogdanm 0:9b334a45a8ff 3756 hrtim_eecr1 |= pEventCfg->Polarity;
bogdanm 0:9b334a45a8ff 3757 hrtim_eecr1 |= pEventCfg->Sensitivity;
bogdanm 0:9b334a45a8ff 3758 /* Update the HRTIM registers (all bit fields but EE1FAST bit) */
bogdanm 0:9b334a45a8ff 3759 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
bogdanm 0:9b334a45a8ff 3760 /* Update the HRTIM registers (EE1FAST bit) */
bogdanm 0:9b334a45a8ff 3761 hrtim_eecr1 |= pEventCfg->FastMode;
bogdanm 0:9b334a45a8ff 3762 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
bogdanm 0:9b334a45a8ff 3763 }
bogdanm 0:9b334a45a8ff 3764 break;
bogdanm 0:9b334a45a8ff 3765 case HRTIM_EVENT_2:
bogdanm 0:9b334a45a8ff 3766 {
bogdanm 0:9b334a45a8ff 3767 hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
bogdanm 0:9b334a45a8ff 3768 hrtim_eecr1 |= (pEventCfg->Source << 6);
bogdanm 0:9b334a45a8ff 3769 hrtim_eecr1 |= (pEventCfg->Polarity << 6);
bogdanm 0:9b334a45a8ff 3770 hrtim_eecr1 |= (pEventCfg->Sensitivity << 6);
bogdanm 0:9b334a45a8ff 3771 /* Update the HRTIM registers (all bit fields but EE2FAST bit) */
bogdanm 0:9b334a45a8ff 3772 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
bogdanm 0:9b334a45a8ff 3773 /* Update the HRTIM registers (EE2FAST bit) */
bogdanm 0:9b334a45a8ff 3774 hrtim_eecr1 |= (pEventCfg->FastMode << 6);
bogdanm 0:9b334a45a8ff 3775 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
bogdanm 0:9b334a45a8ff 3776 }
bogdanm 0:9b334a45a8ff 3777 break;
bogdanm 0:9b334a45a8ff 3778 case HRTIM_EVENT_3:
bogdanm 0:9b334a45a8ff 3779 {
bogdanm 0:9b334a45a8ff 3780 hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
bogdanm 0:9b334a45a8ff 3781 hrtim_eecr1 |= (pEventCfg->Source << 12);
bogdanm 0:9b334a45a8ff 3782 hrtim_eecr1 |= (pEventCfg->Polarity << 12);
bogdanm 0:9b334a45a8ff 3783 hrtim_eecr1 |= (pEventCfg->Sensitivity << 12);
bogdanm 0:9b334a45a8ff 3784 /* Update the HRTIM registers (all bit fields but EE3FAST bit) */
bogdanm 0:9b334a45a8ff 3785 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
bogdanm 0:9b334a45a8ff 3786 /* Update the HRTIM registers (EE3FAST bit) */
bogdanm 0:9b334a45a8ff 3787 hrtim_eecr1 |= (pEventCfg->FastMode << 12);
bogdanm 0:9b334a45a8ff 3788 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
bogdanm 0:9b334a45a8ff 3789 }
bogdanm 0:9b334a45a8ff 3790 break;
bogdanm 0:9b334a45a8ff 3791 case HRTIM_EVENT_4:
bogdanm 0:9b334a45a8ff 3792 {
bogdanm 0:9b334a45a8ff 3793 hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
bogdanm 0:9b334a45a8ff 3794 hrtim_eecr1 |= (pEventCfg->Source << 18);
bogdanm 0:9b334a45a8ff 3795 hrtim_eecr1 |= (pEventCfg->Polarity << 18);
bogdanm 0:9b334a45a8ff 3796 hrtim_eecr1 |= (pEventCfg->Sensitivity << 18);
bogdanm 0:9b334a45a8ff 3797 /* Update the HRTIM registers (all bit fields but EE4FAST bit) */
bogdanm 0:9b334a45a8ff 3798 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
bogdanm 0:9b334a45a8ff 3799 /* Update the HRTIM registers (EE4FAST bit) */
bogdanm 0:9b334a45a8ff 3800 hrtim_eecr1 |= (pEventCfg->FastMode << 18);
bogdanm 0:9b334a45a8ff 3801 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
bogdanm 0:9b334a45a8ff 3802 }
bogdanm 0:9b334a45a8ff 3803 break;
bogdanm 0:9b334a45a8ff 3804 case HRTIM_EVENT_5:
bogdanm 0:9b334a45a8ff 3805 {
bogdanm 0:9b334a45a8ff 3806 hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
bogdanm 0:9b334a45a8ff 3807 hrtim_eecr1 |= (pEventCfg->Source << 24);
bogdanm 0:9b334a45a8ff 3808 hrtim_eecr1 |= (pEventCfg->Polarity << 24);
bogdanm 0:9b334a45a8ff 3809 hrtim_eecr1 |= (pEventCfg->Sensitivity << 24);
bogdanm 0:9b334a45a8ff 3810 /* Update the HRTIM registers (all bit fields but EE5FAST bit) */
bogdanm 0:9b334a45a8ff 3811 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
bogdanm 0:9b334a45a8ff 3812 /* Update the HRTIM registers (EE5FAST bit) */
bogdanm 0:9b334a45a8ff 3813 hrtim_eecr1 |= (pEventCfg->FastMode << 24);
bogdanm 0:9b334a45a8ff 3814 HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
bogdanm 0:9b334a45a8ff 3815 }
bogdanm 0:9b334a45a8ff 3816 break;
bogdanm 0:9b334a45a8ff 3817 case HRTIM_EVENT_6:
bogdanm 0:9b334a45a8ff 3818 {
bogdanm 0:9b334a45a8ff 3819 hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
bogdanm 0:9b334a45a8ff 3820 hrtim_eecr2 |= pEventCfg->Source;
bogdanm 0:9b334a45a8ff 3821 hrtim_eecr2 |= pEventCfg->Polarity;
bogdanm 0:9b334a45a8ff 3822 hrtim_eecr2 |= pEventCfg->Sensitivity;
bogdanm 0:9b334a45a8ff 3823 hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
bogdanm 0:9b334a45a8ff 3824 hrtim_eecr3 |= pEventCfg->Filter;
bogdanm 0:9b334a45a8ff 3825 /* Update the HRTIM registers */
bogdanm 0:9b334a45a8ff 3826 HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
bogdanm 0:9b334a45a8ff 3827 HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
bogdanm 0:9b334a45a8ff 3828 }
bogdanm 0:9b334a45a8ff 3829 break;
bogdanm 0:9b334a45a8ff 3830 case HRTIM_EVENT_7:
bogdanm 0:9b334a45a8ff 3831 {
bogdanm 0:9b334a45a8ff 3832 hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
bogdanm 0:9b334a45a8ff 3833 hrtim_eecr2 |= (pEventCfg->Source << 6);
bogdanm 0:9b334a45a8ff 3834 hrtim_eecr2 |= (pEventCfg->Polarity << 6);
bogdanm 0:9b334a45a8ff 3835 hrtim_eecr2 |= (pEventCfg->Sensitivity << 6);
bogdanm 0:9b334a45a8ff 3836 hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
bogdanm 0:9b334a45a8ff 3837 hrtim_eecr3 |= (pEventCfg->Filter << 6);
bogdanm 0:9b334a45a8ff 3838 /* Update the HRTIM registers */
bogdanm 0:9b334a45a8ff 3839 HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
bogdanm 0:9b334a45a8ff 3840 HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
bogdanm 0:9b334a45a8ff 3841 }
bogdanm 0:9b334a45a8ff 3842 break;
bogdanm 0:9b334a45a8ff 3843 case HRTIM_EVENT_8:
bogdanm 0:9b334a45a8ff 3844 {
bogdanm 0:9b334a45a8ff 3845 hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
bogdanm 0:9b334a45a8ff 3846 hrtim_eecr2 |= (pEventCfg->Source << 12);
bogdanm 0:9b334a45a8ff 3847 hrtim_eecr2 |= (pEventCfg->Polarity << 12);
bogdanm 0:9b334a45a8ff 3848 hrtim_eecr2 |= (pEventCfg->Sensitivity << 12);
bogdanm 0:9b334a45a8ff 3849 hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
bogdanm 0:9b334a45a8ff 3850 hrtim_eecr3 |= (pEventCfg->Filter << 12);
bogdanm 0:9b334a45a8ff 3851 /* Update the HRTIM registers */
bogdanm 0:9b334a45a8ff 3852 HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
bogdanm 0:9b334a45a8ff 3853 HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
bogdanm 0:9b334a45a8ff 3854 }
bogdanm 0:9b334a45a8ff 3855 break;
bogdanm 0:9b334a45a8ff 3856 case HRTIM_EVENT_9:
bogdanm 0:9b334a45a8ff 3857 {
bogdanm 0:9b334a45a8ff 3858 hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
bogdanm 0:9b334a45a8ff 3859 hrtim_eecr2 |= (pEventCfg->Source << 18);
bogdanm 0:9b334a45a8ff 3860 hrtim_eecr2 |= (pEventCfg->Polarity << 18);
bogdanm 0:9b334a45a8ff 3861 hrtim_eecr2 |= (pEventCfg->Sensitivity << 18);
bogdanm 0:9b334a45a8ff 3862 hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
bogdanm 0:9b334a45a8ff 3863 hrtim_eecr3 |= (pEventCfg->Filter << 18);
bogdanm 0:9b334a45a8ff 3864 /* Update the HRTIM registers */
bogdanm 0:9b334a45a8ff 3865 HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
bogdanm 0:9b334a45a8ff 3866 HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
bogdanm 0:9b334a45a8ff 3867 }
bogdanm 0:9b334a45a8ff 3868 break;
bogdanm 0:9b334a45a8ff 3869 case HRTIM_EVENT_10:
bogdanm 0:9b334a45a8ff 3870 {
bogdanm 0:9b334a45a8ff 3871 hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
bogdanm 0:9b334a45a8ff 3872 hrtim_eecr2 |= (pEventCfg->Source << 24);
bogdanm 0:9b334a45a8ff 3873 hrtim_eecr2 |= (pEventCfg->Polarity << 24);
bogdanm 0:9b334a45a8ff 3874 hrtim_eecr2 |= (pEventCfg->Sensitivity << 24);
bogdanm 0:9b334a45a8ff 3875 hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
bogdanm 0:9b334a45a8ff 3876 hrtim_eecr3 |= (pEventCfg->Filter << 24);
bogdanm 0:9b334a45a8ff 3877 /* Update the HRTIM registers */
bogdanm 0:9b334a45a8ff 3878 HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
bogdanm 0:9b334a45a8ff 3879 HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
bogdanm 0:9b334a45a8ff 3880 }
bogdanm 0:9b334a45a8ff 3881 break;
bogdanm 0:9b334a45a8ff 3882 default:
bogdanm 0:9b334a45a8ff 3883 break;
bogdanm 0:9b334a45a8ff 3884 }
bogdanm 0:9b334a45a8ff 3885 }
bogdanm 0:9b334a45a8ff 3886
bogdanm 0:9b334a45a8ff 3887 /**
bogdanm 0:9b334a45a8ff 3888 * @brief Configures the timer counter reset
bogdanm 0:9b334a45a8ff 3889 * @param HRTIMx: pointer to HRTIMx peripheral
bogdanm 0:9b334a45a8ff 3890 * @param TimerIdx: Timer index
bogdanm 0:9b334a45a8ff 3891 * @param Event: Event channel identifier
bogdanm 0:9b334a45a8ff 3892 * @retval None
bogdanm 0:9b334a45a8ff 3893 */
bogdanm 0:9b334a45a8ff 3894 void HRTIM_TIM_ResetConfig(HRTIM_TypeDef * HRTIMx,
bogdanm 0:9b334a45a8ff 3895 uint32_t TimerIdx,
bogdanm 0:9b334a45a8ff 3896 uint32_t Event)
bogdanm 0:9b334a45a8ff 3897 {
bogdanm 0:9b334a45a8ff 3898 switch (Event)
bogdanm 0:9b334a45a8ff 3899 {
bogdanm 0:9b334a45a8ff 3900 case HRTIM_EVENT_1:
bogdanm 0:9b334a45a8ff 3901 {
bogdanm 0:9b334a45a8ff 3902 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
bogdanm 0:9b334a45a8ff 3903 }
bogdanm 0:9b334a45a8ff 3904 break;
bogdanm 0:9b334a45a8ff 3905 case HRTIM_EVENT_2:
bogdanm 0:9b334a45a8ff 3906 {
bogdanm 0:9b334a45a8ff 3907 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
bogdanm 0:9b334a45a8ff 3908 }
bogdanm 0:9b334a45a8ff 3909 break;
bogdanm 0:9b334a45a8ff 3910 case HRTIM_EVENT_3:
bogdanm 0:9b334a45a8ff 3911 {
bogdanm 0:9b334a45a8ff 3912 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
bogdanm 0:9b334a45a8ff 3913 }
bogdanm 0:9b334a45a8ff 3914 break;
bogdanm 0:9b334a45a8ff 3915 case HRTIM_EVENT_4:
bogdanm 0:9b334a45a8ff 3916 {
bogdanm 0:9b334a45a8ff 3917 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
bogdanm 0:9b334a45a8ff 3918 }
bogdanm 0:9b334a45a8ff 3919 break;
bogdanm 0:9b334a45a8ff 3920 case HRTIM_EVENT_5:
bogdanm 0:9b334a45a8ff 3921 {
bogdanm 0:9b334a45a8ff 3922 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
bogdanm 0:9b334a45a8ff 3923 }
bogdanm 0:9b334a45a8ff 3924 break;
bogdanm 0:9b334a45a8ff 3925 case HRTIM_EVENT_6:
bogdanm 0:9b334a45a8ff 3926 {
bogdanm 0:9b334a45a8ff 3927 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
bogdanm 0:9b334a45a8ff 3928 }
bogdanm 0:9b334a45a8ff 3929 break;
bogdanm 0:9b334a45a8ff 3930 case HRTIM_EVENT_7:
bogdanm 0:9b334a45a8ff 3931 {
bogdanm 0:9b334a45a8ff 3932 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
bogdanm 0:9b334a45a8ff 3933 }
bogdanm 0:9b334a45a8ff 3934 break;
bogdanm 0:9b334a45a8ff 3935 case HRTIM_EVENT_8:
bogdanm 0:9b334a45a8ff 3936 {
bogdanm 0:9b334a45a8ff 3937 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
bogdanm 0:9b334a45a8ff 3938 }
bogdanm 0:9b334a45a8ff 3939 break;
bogdanm 0:9b334a45a8ff 3940 case HRTIM_EVENT_9:
bogdanm 0:9b334a45a8ff 3941 {
bogdanm 0:9b334a45a8ff 3942 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
bogdanm 0:9b334a45a8ff 3943 }
bogdanm 0:9b334a45a8ff 3944 break;
bogdanm 0:9b334a45a8ff 3945 case HRTIM_EVENT_10:
bogdanm 0:9b334a45a8ff 3946 {
bogdanm 0:9b334a45a8ff 3947 HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
bogdanm 0:9b334a45a8ff 3948 }
bogdanm 0:9b334a45a8ff 3949 break;
bogdanm 0:9b334a45a8ff 3950 default:
bogdanm 0:9b334a45a8ff 3951 break;
bogdanm 0:9b334a45a8ff 3952 }
bogdanm 0:9b334a45a8ff 3953 }
bogdanm 0:9b334a45a8ff 3954 /**
bogdanm 0:9b334a45a8ff 3955 * @}
bogdanm 0:9b334a45a8ff 3956 */
bogdanm 0:9b334a45a8ff 3957 /**
bogdanm 0:9b334a45a8ff 3958 * @}
bogdanm 0:9b334a45a8ff 3959 */
bogdanm 0:9b334a45a8ff 3960
bogdanm 0:9b334a45a8ff 3961 /**
bogdanm 0:9b334a45a8ff 3962 * @}
bogdanm 0:9b334a45a8ff 3963 */
bogdanm 0:9b334a45a8ff 3964
bogdanm 0:9b334a45a8ff 3965 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bogdanm 0:9b334a45a8ff 3966
bogdanm 0:9b334a45a8ff 3967
bogdanm 0:9b334a45a8ff 3968