Janek Mann / mbed-src-openwear

mbed library sources modified for open wear

Dependents:   openwear-lifelogger-example

Fork of mbed-src by mbed official

targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/gpio_irq_api.c@254:181b5e179739, 2014-07-10 (annotated)

Committer:
mbed_official
Date:
Thu Jul 10 09:00:09 2014 +0100
Revision:
254:181b5e179739
Parent:
251:de9a1e4ffd79
Child:
286:31249416b6f9
Synchronized with git revision ffef32f2bc6fb88a72a992e85a9e9df0982d7eff



Full URL: https://github.com/mbedmicro/mbed/commit/ffef32f2bc6fb88a72a992e85a9e9df0982d7eff/



[KLxxZ] Increased KLxxZs interrupt handling speed

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * Licensed under the Apache License, Version 2.0 (the "License");
emilmont 10:3bc89ef62ce7 5 * you may not use this file except in compliance with the License.
emilmont 10:3bc89ef62ce7 6 * You may obtain a copy of the License at
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * http://www.apache.org/licenses/LICENSE-2.0
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * Unless required by applicable law or agreed to in writing, software
emilmont 10:3bc89ef62ce7 11 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 10:3bc89ef62ce7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 10:3bc89ef62ce7 13 * See the License for the specific language governing permissions and
emilmont 10:3bc89ef62ce7 14 * limitations under the License.
emilmont 10:3bc89ef62ce7 15 */
emilmont 10:3bc89ef62ce7 16 #include <stddef.h>
emilmont 10:3bc89ef62ce7 17 #include "cmsis.h"
emilmont 10:3bc89ef62ce7 18
emilmont 10:3bc89ef62ce7 19 #include "gpio_irq_api.h"
mbed_official 113:65a335a675de 20 #include "gpio_api.h"
mbed_official 251:de9a1e4ffd79 21 #include "error.h"
emilmont 10:3bc89ef62ce7 22
emilmont 10:3bc89ef62ce7 23 #define CHANNEL_NUM 64
emilmont 10:3bc89ef62ce7 24
emilmont 10:3bc89ef62ce7 25 static uint32_t channel_ids[CHANNEL_NUM] = {0};
emilmont 10:3bc89ef62ce7 26 static gpio_irq_handler irq_handler;
emilmont 10:3bc89ef62ce7 27
emilmont 10:3bc89ef62ce7 28 #define IRQ_DISABLED (0)
emilmont 10:3bc89ef62ce7 29 #define IRQ_RAISING_EDGE PORT_PCR_IRQC(9)
emilmont 10:3bc89ef62ce7 30 #define IRQ_FALLING_EDGE PORT_PCR_IRQC(10)
emilmont 10:3bc89ef62ce7 31 #define IRQ_EITHER_EDGE PORT_PCR_IRQC(11)
emilmont 10:3bc89ef62ce7 32
mbed_official 254:181b5e179739 33 const uint32_t search_bits[] = {0x0000FFFF, 0x000000FF, 0x0000000F, 0x00000003, 0x00000001};
mbed_official 254:181b5e179739 34
emilmont 10:3bc89ef62ce7 35 static void handle_interrupt_in(PORT_Type *port, int ch_base) {
mbed_official 254:181b5e179739 36 uint32_t isfr;
mbed_official 254:181b5e179739 37 uint8_t location;
emilmont 10:3bc89ef62ce7 38
mbed_official 254:181b5e179739 39 while((isfr = port->ISFR) != 0) {
mbed_official 254:181b5e179739 40 location = 0;
mbed_official 254:181b5e179739 41 for (int i = 0; i < 5; i++) {
mbed_official 254:181b5e179739 42 if (!(isfr & (search_bits[i] << location)))
mbed_official 254:181b5e179739 43 location += 1 << (4 - i);
mbed_official 254:181b5e179739 44 }
mbed_official 254:181b5e179739 45
mbed_official 254:181b5e179739 46 uint32_t id = channel_ids[ch_base + location];
mbed_official 254:181b5e179739 47 if (id == 0) {
mbed_official 254:181b5e179739 48 continue;
mbed_official 254:181b5e179739 49 }
emilmont 10:3bc89ef62ce7 50
mbed_official 254:181b5e179739 51 FGPIO_Type *gpio;
mbed_official 254:181b5e179739 52 gpio_irq_event event = IRQ_NONE;
mbed_official 254:181b5e179739 53 switch (port->PCR[location] & PORT_PCR_IRQC_MASK) {
mbed_official 254:181b5e179739 54 case IRQ_RAISING_EDGE:
mbed_official 254:181b5e179739 55 event = IRQ_RISE;
mbed_official 254:181b5e179739 56 break;
emilmont 10:3bc89ef62ce7 57
mbed_official 254:181b5e179739 58 case IRQ_FALLING_EDGE:
mbed_official 254:181b5e179739 59 event = IRQ_FALL;
mbed_official 254:181b5e179739 60 break;
emilmont 10:3bc89ef62ce7 61
mbed_official 254:181b5e179739 62 case IRQ_EITHER_EDGE:
mbed_official 254:181b5e179739 63 gpio = (port == PORTA) ? (FPTA) : (FPTD);
mbed_official 254:181b5e179739 64 event = (gpio->PDIR & (1 << location)) ? (IRQ_RISE) : (IRQ_FALL);
mbed_official 254:181b5e179739 65 break;
emilmont 10:3bc89ef62ce7 66 }
mbed_official 254:181b5e179739 67 if (event != IRQ_NONE) {
mbed_official 254:181b5e179739 68 irq_handler(id, event);
mbed_official 254:181b5e179739 69 }
mbed_official 254:181b5e179739 70 port->ISFR = 1 << location;
emilmont 10:3bc89ef62ce7 71 }
emilmont 10:3bc89ef62ce7 72 }
emilmont 10:3bc89ef62ce7 73
emilmont 10:3bc89ef62ce7 74 void gpio_irqA(void) {handle_interrupt_in(PORTA, 0);}
emilmont 10:3bc89ef62ce7 75 void gpio_irqD(void) {handle_interrupt_in(PORTD, 32);}
emilmont 10:3bc89ef62ce7 76
emilmont 10:3bc89ef62ce7 77 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
emilmont 10:3bc89ef62ce7 78 if (pin == NC) return -1;
emilmont 10:3bc89ef62ce7 79
emilmont 10:3bc89ef62ce7 80 irq_handler = handler;
emilmont 10:3bc89ef62ce7 81
emilmont 10:3bc89ef62ce7 82 obj->port = pin >> PORT_SHIFT;
emilmont 10:3bc89ef62ce7 83 obj->pin = (pin & 0x7F) >> 2;
emilmont 10:3bc89ef62ce7 84
emilmont 10:3bc89ef62ce7 85 uint32_t ch_base, vector;
emilmont 10:3bc89ef62ce7 86 IRQn_Type irq_n;
emilmont 10:3bc89ef62ce7 87 switch (obj->port) {
emilmont 10:3bc89ef62ce7 88 case PortA:
emilmont 10:3bc89ef62ce7 89 ch_base = 0; irq_n = PORTA_IRQn; vector = (uint32_t)gpio_irqA;
emilmont 10:3bc89ef62ce7 90 break;
emilmont 10:3bc89ef62ce7 91
emilmont 10:3bc89ef62ce7 92 case PortD:
emilmont 10:3bc89ef62ce7 93 ch_base = 32; irq_n = PORTD_IRQn; vector = (uint32_t)gpio_irqD;
emilmont 10:3bc89ef62ce7 94 break;
emilmont 10:3bc89ef62ce7 95
emilmont 10:3bc89ef62ce7 96 default:
mbed_official 158:3121b9889f7b 97 error("gpio_irq only supported on port A and D");
emilmont 10:3bc89ef62ce7 98 break;
emilmont 10:3bc89ef62ce7 99 }
emilmont 10:3bc89ef62ce7 100 NVIC_SetVector(irq_n, vector);
emilmont 10:3bc89ef62ce7 101 NVIC_EnableIRQ(irq_n);
emilmont 10:3bc89ef62ce7 102
emilmont 10:3bc89ef62ce7 103 obj->ch = ch_base + obj->pin;
emilmont 10:3bc89ef62ce7 104 channel_ids[obj->ch] = id;
emilmont 10:3bc89ef62ce7 105
emilmont 10:3bc89ef62ce7 106 return 0;
emilmont 10:3bc89ef62ce7 107 }
emilmont 10:3bc89ef62ce7 108
emilmont 10:3bc89ef62ce7 109 void gpio_irq_free(gpio_irq_t *obj) {
emilmont 10:3bc89ef62ce7 110 channel_ids[obj->ch] = 0;
emilmont 10:3bc89ef62ce7 111 }
emilmont 10:3bc89ef62ce7 112
emilmont 10:3bc89ef62ce7 113 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
emilmont 10:3bc89ef62ce7 114 PORT_Type *port = (PORT_Type *)(PORTA_BASE + 0x1000 * obj->port);
emilmont 10:3bc89ef62ce7 115
emilmont 10:3bc89ef62ce7 116 uint32_t irq_settings = IRQ_DISABLED;
emilmont 10:3bc89ef62ce7 117
emilmont 10:3bc89ef62ce7 118 switch (port->PCR[obj->pin] & PORT_PCR_IRQC_MASK) {
emilmont 10:3bc89ef62ce7 119 case IRQ_DISABLED:
emilmont 10:3bc89ef62ce7 120 if (enable) {
emilmont 10:3bc89ef62ce7 121 irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_FALLING_EDGE);
emilmont 10:3bc89ef62ce7 122 }
emilmont 10:3bc89ef62ce7 123 break;
emilmont 10:3bc89ef62ce7 124
emilmont 10:3bc89ef62ce7 125 case IRQ_RAISING_EDGE:
emilmont 10:3bc89ef62ce7 126 if (enable) {
emilmont 10:3bc89ef62ce7 127 irq_settings = (event == IRQ_RISE) ? (IRQ_RAISING_EDGE) : (IRQ_EITHER_EDGE);
emilmont 10:3bc89ef62ce7 128 } else {
emilmont 10:3bc89ef62ce7 129 if (event == IRQ_FALL)
emilmont 10:3bc89ef62ce7 130 irq_settings = IRQ_RAISING_EDGE;
emilmont 10:3bc89ef62ce7 131 }
emilmont 10:3bc89ef62ce7 132 break;
emilmont 10:3bc89ef62ce7 133
emilmont 10:3bc89ef62ce7 134 case IRQ_FALLING_EDGE:
emilmont 10:3bc89ef62ce7 135 if (enable) {
emilmont 10:3bc89ef62ce7 136 irq_settings = (event == IRQ_FALL) ? (IRQ_FALLING_EDGE) : (IRQ_EITHER_EDGE);
emilmont 10:3bc89ef62ce7 137 } else {
emilmont 10:3bc89ef62ce7 138 if (event == IRQ_RISE)
emilmont 10:3bc89ef62ce7 139 irq_settings = IRQ_FALLING_EDGE;
emilmont 10:3bc89ef62ce7 140 }
emilmont 10:3bc89ef62ce7 141 break;
emilmont 10:3bc89ef62ce7 142
emilmont 10:3bc89ef62ce7 143 case IRQ_EITHER_EDGE:
emilmont 10:3bc89ef62ce7 144 if (enable) {
emilmont 10:3bc89ef62ce7 145 irq_settings = IRQ_EITHER_EDGE;
emilmont 10:3bc89ef62ce7 146 } else {
emilmont 10:3bc89ef62ce7 147 irq_settings = (event == IRQ_RISE) ? (IRQ_FALLING_EDGE) : (IRQ_RAISING_EDGE);
emilmont 10:3bc89ef62ce7 148 }
emilmont 10:3bc89ef62ce7 149 break;
emilmont 10:3bc89ef62ce7 150 }
emilmont 10:3bc89ef62ce7 151
emilmont 10:3bc89ef62ce7 152 // Interrupt configuration and clear interrupt
emilmont 10:3bc89ef62ce7 153 port->PCR[obj->pin] = (port->PCR[obj->pin] & ~PORT_PCR_IRQC_MASK) | irq_settings | PORT_PCR_ISF_MASK;
emilmont 10:3bc89ef62ce7 154 }
mbed_official 35:371630885ad6 155
mbed_official 35:371630885ad6 156 void gpio_irq_enable(gpio_irq_t *obj) {
mbed_official 35:371630885ad6 157 if (obj->port == PortA) {
mbed_official 35:371630885ad6 158 NVIC_EnableIRQ(PORTA_IRQn);
mbed_official 35:371630885ad6 159 } else if (obj->port == PortD) {
mbed_official 35:371630885ad6 160 NVIC_EnableIRQ(PORTD_IRQn);
mbed_official 35:371630885ad6 161 }
mbed_official 35:371630885ad6 162 }
mbed_official 35:371630885ad6 163
mbed_official 35:371630885ad6 164 void gpio_irq_disable(gpio_irq_t *obj) {
mbed_official 35:371630885ad6 165 if (obj->port == PortA) {
mbed_official 35:371630885ad6 166 NVIC_DisableIRQ(PORTA_IRQn);
mbed_official 35:371630885ad6 167 } else if (obj->port == PortD) {
mbed_official 35:371630885ad6 168 NVIC_DisableIRQ(PORTD_IRQn);
mbed_official 35:371630885ad6 169 }
mbed_official 35:371630885ad6 170 }