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TARGET_LPC4088_EA/LPC407x_8x_177x_8x.h@71:7ec3cb6bbcc4, 2013-11-29 (annotated)

Committer:
jalp89
Date:
Fri Nov 29 09:39:46 2013 +0000
Revision:
71:7ec3cb6bbcc4
Parent:
70:673126e12c73 
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bogdanm 70:673126e12c73 1 /****************************************************************************************************//**
bogdanm 70:673126e12c73 2 * $Id$ LPC407x_8x_177x_8x.h 2012-04-25
bogdanm 70:673126e12c73 3 *//**
bogdanm 70:673126e12c73 4 * @file LPC407x_8x_177x_8x.h
bogdanm 70:673126e12c73 5 *
bogdanm 70:673126e12c73 6 * @brief CMSIS Cortex-M4 Cortex-M3 Peripheral Access Layer Header File for
bogdanm 70:673126e12c73 7 * NXP LPC407x_8x_177x_8x.
bogdanm 70:673126e12c73 8 * @version V0.7
bogdanm 70:673126e12c73 9 * @date 20. June 2012
bogdanm 70:673126e12c73 10 * @author NXP MCU SW Application Team
bogdanm 70:673126e12c73 11 *
bogdanm 70:673126e12c73 12 * Copyright(C) 2012, NXP Semiconductor
bogdanm 70:673126e12c73 13 * All rights reserved.
bogdanm 70:673126e12c73 14 *
bogdanm 70:673126e12c73 15 ***********************************************************************
bogdanm 70:673126e12c73 16 * Software that is described herein is for illustrative purposes only
bogdanm 70:673126e12c73 17 * which provides customers with programming information regarding the
bogdanm 70:673126e12c73 18 * products. This software is supplied "AS IS" without any warranties.
bogdanm 70:673126e12c73 19 * NXP Semiconductors assumes no responsibility or liability for the
bogdanm 70:673126e12c73 20 * use of the software, conveys no license or title under any patent,
bogdanm 70:673126e12c73 21 * copyright, or mask work right to the product. NXP Semiconductors
bogdanm 70:673126e12c73 22 * reserves the right to make changes in the software without
bogdanm 70:673126e12c73 23 * notification. NXP Semiconductors also make no representation or
bogdanm 70:673126e12c73 24 * warranty that such application will be suitable for the specified
bogdanm 70:673126e12c73 25 * use without further testing or modification.
bogdanm 70:673126e12c73 26 * Permission to use, copy, modify, and distribute this software and its
bogdanm 70:673126e12c73 27 * documentation is hereby granted, under NXP Semiconductors'
bogdanm 70:673126e12c73 28 * relevant copyright in the software, without fee, provided that it
bogdanm 70:673126e12c73 29 * is used in conjunction with NXP Semiconductors microcontrollers. This
bogdanm 70:673126e12c73 30 * copyright, permission, and disclaimer notice must appear in all copies of
bogdanm 70:673126e12c73 31 * this code.
bogdanm 70:673126e12c73 32 **********************************************************************/
bogdanm 70:673126e12c73 33
bogdanm 70:673126e12c73 34 #ifndef __LPC407x_8x_177x_8x_H__
bogdanm 70:673126e12c73 35 #define __LPC407x_8x_177x_8x_H__
bogdanm 70:673126e12c73 36
bogdanm 70:673126e12c73 37 #if defined(__CORTEX_M4) && !defined(CORE_M4)
bogdanm 70:673126e12c73 38 #define CORE_M4
bogdanm 70:673126e12c73 39 #endif
bogdanm 70:673126e12c73 40
bogdanm 70:673126e12c73 41 // ##################
bogdanm 70:673126e12c73 42 // Code Red - excluded extern "C" as unrequired
bogdanm 70:673126e12c73 43 // ##################
bogdanm 70:673126e12c73 44 #if 0
bogdanm 70:673126e12c73 45 #ifdef __cplusplus
bogdanm 70:673126e12c73 46 extern "C" {
bogdanm 70:673126e12c73 47 #endif
bogdanm 70:673126e12c73 48 #endif
bogdanm 70:673126e12c73 49
bogdanm 70:673126e12c73 50
bogdanm 70:673126e12c73 51 /* ------------------------- Interrupt Number Definition ------------------------ */
bogdanm 70:673126e12c73 52
bogdanm 70:673126e12c73 53 typedef enum IRQn
bogdanm 70:673126e12c73 54 {
bogdanm 70:673126e12c73 55 /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
bogdanm 70:673126e12c73 56 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
bogdanm 70:673126e12c73 57 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
bogdanm 70:673126e12c73 58 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
bogdanm 70:673126e12c73 59 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
bogdanm 70:673126e12c73 60 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
bogdanm 70:673126e12c73 61 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
bogdanm 70:673126e12c73 62 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
bogdanm 70:673126e12c73 63 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
bogdanm 70:673126e12c73 64 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
bogdanm 70:673126e12c73 65 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
bogdanm 70:673126e12c73 66
bogdanm 70:673126e12c73 67 /****** LPC407x_8x_177x_8x Specific Interrupt Numbers *******************************************************/
bogdanm 70:673126e12c73 68 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
bogdanm 70:673126e12c73 69 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
bogdanm 70:673126e12c73 70 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
bogdanm 70:673126e12c73 71 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
bogdanm 70:673126e12c73 72 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
bogdanm 70:673126e12c73 73 UART0_IRQn = 5, /*!< UART0 Interrupt */
bogdanm 70:673126e12c73 74 UART1_IRQn = 6, /*!< UART1 Interrupt */
bogdanm 70:673126e12c73 75 UART2_IRQn = 7, /*!< UART2 Interrupt */
bogdanm 70:673126e12c73 76 UART3_IRQn = 8, /*!< UART3 Interrupt */
bogdanm 70:673126e12c73 77 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
bogdanm 70:673126e12c73 78 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
bogdanm 70:673126e12c73 79 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
bogdanm 70:673126e12c73 80 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
bogdanm 70:673126e12c73 81 Reserved0_IRQn = 13, /*!< Reserved */
bogdanm 70:673126e12c73 82 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
bogdanm 70:673126e12c73 83 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
bogdanm 70:673126e12c73 84 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
bogdanm 70:673126e12c73 85 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
bogdanm 70:673126e12c73 86 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
bogdanm 70:673126e12c73 87 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
bogdanm 70:673126e12c73 88 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
bogdanm 70:673126e12c73 89 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
bogdanm 70:673126e12c73 90 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
bogdanm 70:673126e12c73 91 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
bogdanm 70:673126e12c73 92 USB_IRQn = 24, /*!< USB Interrupt */
bogdanm 70:673126e12c73 93 CAN_IRQn = 25, /*!< CAN Interrupt */
bogdanm 70:673126e12c73 94 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
bogdanm 70:673126e12c73 95 I2S_IRQn = 27, /*!< I2S Interrupt */
bogdanm 70:673126e12c73 96 ENET_IRQn = 28, /*!< Ethernet Interrupt */
bogdanm 70:673126e12c73 97 MCI_IRQn = 29, /*!< SD/MMC card I/F Interrupt */
bogdanm 70:673126e12c73 98 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
bogdanm 70:673126e12c73 99 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
bogdanm 70:673126e12c73 100 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
bogdanm 70:673126e12c73 101 USBActivity_IRQn = 33, /*!< USB Activity interrupt */
bogdanm 70:673126e12c73 102 CANActivity_IRQn = 34, /*!< CAN Activity interrupt */
bogdanm 70:673126e12c73 103 UART4_IRQn = 35, /*!< UART4 Interrupt */
bogdanm 70:673126e12c73 104 SSP2_IRQn = 36, /*!< SSP2 Interrupt */
bogdanm 70:673126e12c73 105 LCD_IRQn = 37, /*!< LCD Interrupt */
bogdanm 70:673126e12c73 106 GPIO_IRQn = 38, /*!< GPIO Interrupt */
bogdanm 70:673126e12c73 107 PWM0_IRQn = 39, /*!< 39 PWM0 */
bogdanm 70:673126e12c73 108 EEPROM_IRQn = 40, /*!< 40 EEPROM */
bogdanm 70:673126e12c73 109 CMP0_IRQn = 41, /*!< 41 CMP0 */
bogdanm 70:673126e12c73 110 CMP1_IRQn = 42 /*!< 42 CMP1 */
bogdanm 70:673126e12c73 111 } IRQn_Type;
bogdanm 70:673126e12c73 112
bogdanm 70:673126e12c73 113 /* ================================================================================ */
bogdanm 70:673126e12c73 114 /* ================ Processor and Core Peripheral Section ================ */
bogdanm 70:673126e12c73 115 /* ================================================================================ */
bogdanm 70:673126e12c73 116 #ifdef CORE_M4
bogdanm 70:673126e12c73 117 /* ----------------Configuration of the cm4 Processor and Core Peripherals---------------- */
bogdanm 70:673126e12c73 118 #define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */
bogdanm 70:673126e12c73 119 #define __MPU_PRESENT 1 /*!< MPU present or not */
bogdanm 70:673126e12c73 120 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
bogdanm 70:673126e12c73 121 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 70:673126e12c73 122 #define __FPU_PRESENT 1 /*!< FPU present or not */
bogdanm 70:673126e12c73 123
bogdanm 70:673126e12c73 124
bogdanm 70:673126e12c73 125 #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
bogdanm 70:673126e12c73 126 #else
bogdanm 70:673126e12c73 127 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
bogdanm 70:673126e12c73 128 #define __MPU_PRESENT 1 /*!< MPU present or not */
bogdanm 70:673126e12c73 129 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
bogdanm 70:673126e12c73 130 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 70:673126e12c73 131
bogdanm 70:673126e12c73 132
bogdanm 70:673126e12c73 133 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
bogdanm 70:673126e12c73 134
bogdanm 70:673126e12c73 135 #endif
bogdanm 70:673126e12c73 136
bogdanm 70:673126e12c73 137 #include "system_LPC407x_8x_177x_8x.h" /*!< LPC408x_7x System */
bogdanm 70:673126e12c73 138
bogdanm 70:673126e12c73 139
bogdanm 70:673126e12c73 140
bogdanm 70:673126e12c73 141
bogdanm 70:673126e12c73 142
bogdanm 70:673126e12c73 143
bogdanm 70:673126e12c73 144 /* ================================================================================ */
bogdanm 70:673126e12c73 145 /* ================ Device Specific Peripheral Section ================ */
bogdanm 70:673126e12c73 146 /* ================================================================================ */
bogdanm 70:673126e12c73 147
bogdanm 70:673126e12c73 148 #if defined ( __CC_ARM )
bogdanm 70:673126e12c73 149 #pragma anon_unions
bogdanm 70:673126e12c73 150 #endif
bogdanm 70:673126e12c73 151
bogdanm 70:673126e12c73 152 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
bogdanm 70:673126e12c73 153 typedef struct /* Common Registers */
bogdanm 70:673126e12c73 154 {
bogdanm 70:673126e12c73 155 __I uint32_t IntStat;
bogdanm 70:673126e12c73 156 __I uint32_t IntTCStat;
bogdanm 70:673126e12c73 157 __O uint32_t IntTCClear;
bogdanm 70:673126e12c73 158 __I uint32_t IntErrStat;
bogdanm 70:673126e12c73 159 __O uint32_t IntErrClr;
bogdanm 70:673126e12c73 160 __I uint32_t RawIntTCStat;
bogdanm 70:673126e12c73 161 __I uint32_t RawIntErrStat;
bogdanm 70:673126e12c73 162 __I uint32_t EnbldChns;
bogdanm 70:673126e12c73 163 __IO uint32_t SoftBReq;
bogdanm 70:673126e12c73 164 __IO uint32_t SoftSReq;
bogdanm 70:673126e12c73 165 __IO uint32_t SoftLBReq;
bogdanm 70:673126e12c73 166 __IO uint32_t SoftLSReq;
bogdanm 70:673126e12c73 167 __IO uint32_t Config;
bogdanm 70:673126e12c73 168 __IO uint32_t Sync;
bogdanm 70:673126e12c73 169 } LPC_GPDMA_TypeDef;
bogdanm 70:673126e12c73 170
bogdanm 70:673126e12c73 171 typedef struct /* Channel Registers */
bogdanm 70:673126e12c73 172 {
bogdanm 70:673126e12c73 173 __IO uint32_t CSrcAddr;
bogdanm 70:673126e12c73 174 __IO uint32_t CDestAddr;
bogdanm 70:673126e12c73 175 __IO uint32_t CLLI;
bogdanm 70:673126e12c73 176 __IO uint32_t CControl;
bogdanm 70:673126e12c73 177 __IO uint32_t CConfig;
bogdanm 70:673126e12c73 178 } LPC_GPDMACH_TypeDef;
bogdanm 70:673126e12c73 179
bogdanm 70:673126e12c73 180 /*------------- System Control (SC) ------------------------------------------*/
bogdanm 70:673126e12c73 181 typedef struct
bogdanm 70:673126e12c73 182 {
bogdanm 70:673126e12c73 183 __IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */
bogdanm 70:673126e12c73 184 uint32_t RESERVED0[31];
bogdanm 70:673126e12c73 185 __IO uint32_t PLL0CON; /*!< Offset: 0x080 (R/W) PLL0 Control Register */
bogdanm 70:673126e12c73 186 __IO uint32_t PLL0CFG; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */
bogdanm 70:673126e12c73 187 __I uint32_t PLL0STAT; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */
bogdanm 70:673126e12c73 188 __O uint32_t PLL0FEED; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */
bogdanm 70:673126e12c73 189 uint32_t RESERVED1[4];
bogdanm 70:673126e12c73 190 __IO uint32_t PLL1CON; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */
bogdanm 70:673126e12c73 191 __IO uint32_t PLL1CFG; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */
bogdanm 70:673126e12c73 192 __I uint32_t PLL1STAT; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */
bogdanm 70:673126e12c73 193 __O uint32_t PLL1FEED; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */
bogdanm 70:673126e12c73 194 uint32_t RESERVED2[4];
bogdanm 70:673126e12c73 195 __IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */
bogdanm 70:673126e12c73 196 __IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */
bogdanm 70:673126e12c73 197 __IO uint32_t PCONP1; /*!< Offset: 0x0C8 (R/W) Power Control for Peripherals Register */
bogdanm 70:673126e12c73 198 uint32_t RESERVED3[13];
bogdanm 70:673126e12c73 199 __IO uint32_t EMCCLKSEL; /*!< Offset: 0x100 (R/W) External Memory Controller Clock Selection Register */
bogdanm 70:673126e12c73 200 __IO uint32_t CCLKSEL; /*!< Offset: 0x104 (R/W) CPU Clock Selection Register */
bogdanm 70:673126e12c73 201 __IO uint32_t USBCLKSEL; /*!< Offset: 0x108 (R/W) USB Clock Selection Register */
bogdanm 70:673126e12c73 202 __IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */
bogdanm 70:673126e12c73 203 __IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */
bogdanm 70:673126e12c73 204 __IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */
bogdanm 70:673126e12c73 205 uint32_t RESERVED4[10];
bogdanm 70:673126e12c73 206 __IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */
bogdanm 70:673126e12c73 207 uint32_t RESERVED5[1];
bogdanm 70:673126e12c73 208 __IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */
bogdanm 70:673126e12c73 209 __IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */
bogdanm 70:673126e12c73 210 uint32_t RESERVED6[12];
bogdanm 70:673126e12c73 211 __IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */
bogdanm 70:673126e12c73 212 uint32_t RESERVED7[7];
bogdanm 70:673126e12c73 213 __IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */
bogdanm 70:673126e12c73 214 __IO uint32_t IRCTRIM; /*!< Offset: 0x1A4 (R/W) Clock Dividers */
bogdanm 70:673126e12c73 215 __IO uint32_t PCLKSEL; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Selection Register */
bogdanm 70:673126e12c73 216 uint32_t RESERVED8;
bogdanm 70:673126e12c73 217 __IO uint32_t PBOOST; /*!< Offset: 0x1B0 (R/W) Power Boost control register */
bogdanm 70:673126e12c73 218 __IO uint32_t SPIFICLKSEL;
bogdanm 70:673126e12c73 219 __IO uint32_t LCD_CFG; /*!< Offset: 0x1B8 (R/W) LCD Configuration and clocking control Register */
bogdanm 70:673126e12c73 220 uint32_t RESERVED10[1];
bogdanm 70:673126e12c73 221 __IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */
bogdanm 70:673126e12c73 222 __IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */
bogdanm 70:673126e12c73 223 __IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */
bogdanm 70:673126e12c73 224 __IO uint32_t RSTCON0; /*!< Offset: 0x1CC (R/W) RESET Control0 Register */
bogdanm 70:673126e12c73 225 __IO uint32_t RSTCON1; /*!< Offset: 0x1D0 (R/W) RESET Control1 Register */
bogdanm 70:673126e12c73 226 uint32_t RESERVED11[2];
bogdanm 70:673126e12c73 227 __IO uint32_t EMCDLYCTL; /*!< Offset: 0x1DC (R/W) SDRAM programmable delays */
bogdanm 70:673126e12c73 228 __IO uint32_t EMCCAL; /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */
bogdanm 70:673126e12c73 229 } LPC_SC_TypeDef;
bogdanm 70:673126e12c73 230 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
bogdanm 70:673126e12c73 231 typedef struct
bogdanm 70:673126e12c73 232 {
bogdanm 70:673126e12c73 233 __IO uint32_t MAC1; /* MAC Registers */
bogdanm 70:673126e12c73 234 __IO uint32_t MAC2;
bogdanm 70:673126e12c73 235 __IO uint32_t IPGT;
bogdanm 70:673126e12c73 236 __IO uint32_t IPGR;
bogdanm 70:673126e12c73 237 __IO uint32_t CLRT;
bogdanm 70:673126e12c73 238 __IO uint32_t MAXF;
bogdanm 70:673126e12c73 239 __IO uint32_t SUPP;
bogdanm 70:673126e12c73 240 __IO uint32_t TEST;
bogdanm 70:673126e12c73 241 __IO uint32_t MCFG;
bogdanm 70:673126e12c73 242 __IO uint32_t MCMD;
bogdanm 70:673126e12c73 243 __IO uint32_t MADR;
bogdanm 70:673126e12c73 244 __O uint32_t MWTD;
bogdanm 70:673126e12c73 245 __I uint32_t MRDD;
bogdanm 70:673126e12c73 246 __I uint32_t MIND;
bogdanm 70:673126e12c73 247 uint32_t RESERVED0[2];
bogdanm 70:673126e12c73 248 __IO uint32_t SA0;
bogdanm 70:673126e12c73 249 __IO uint32_t SA1;
bogdanm 70:673126e12c73 250 __IO uint32_t SA2;
bogdanm 70:673126e12c73 251 uint32_t RESERVED1[45];
bogdanm 70:673126e12c73 252 __IO uint32_t Command; /* Control Registers */
bogdanm 70:673126e12c73 253 __I uint32_t Status;
bogdanm 70:673126e12c73 254 __IO uint32_t RxDescriptor;
bogdanm 70:673126e12c73 255 __IO uint32_t RxStatus;
bogdanm 70:673126e12c73 256 __IO uint32_t RxDescriptorNumber;
bogdanm 70:673126e12c73 257 __I uint32_t RxProduceIndex;
bogdanm 70:673126e12c73 258 __IO uint32_t RxConsumeIndex;
bogdanm 70:673126e12c73 259 __IO uint32_t TxDescriptor;
bogdanm 70:673126e12c73 260 __IO uint32_t TxStatus;
bogdanm 70:673126e12c73 261 __IO uint32_t TxDescriptorNumber;
bogdanm 70:673126e12c73 262 __IO uint32_t TxProduceIndex;
bogdanm 70:673126e12c73 263 __I uint32_t TxConsumeIndex;
bogdanm 70:673126e12c73 264 uint32_t RESERVED2[10];
bogdanm 70:673126e12c73 265 __I uint32_t TSV0;
bogdanm 70:673126e12c73 266 __I uint32_t TSV1;
bogdanm 70:673126e12c73 267 __I uint32_t RSV;
bogdanm 70:673126e12c73 268 uint32_t RESERVED3[3];
bogdanm 70:673126e12c73 269 __IO uint32_t FlowControlCounter;
bogdanm 70:673126e12c73 270 __I uint32_t FlowControlStatus;
bogdanm 70:673126e12c73 271 uint32_t RESERVED4[34];
bogdanm 70:673126e12c73 272 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
bogdanm 70:673126e12c73 273 __I uint32_t RxFilterWoLStatus;
bogdanm 70:673126e12c73 274 __O uint32_t RxFilterWoLClear;
bogdanm 70:673126e12c73 275 uint32_t RESERVED5;
bogdanm 70:673126e12c73 276 __IO uint32_t HashFilterL;
bogdanm 70:673126e12c73 277 __IO uint32_t HashFilterH;
bogdanm 70:673126e12c73 278 uint32_t RESERVED6[882];
bogdanm 70:673126e12c73 279 __I uint32_t IntStatus; /* Module Control Registers */
bogdanm 70:673126e12c73 280 __IO uint32_t IntEnable;
bogdanm 70:673126e12c73 281 __O uint32_t IntClear;
bogdanm 70:673126e12c73 282 __O uint32_t IntSet;
bogdanm 70:673126e12c73 283 uint32_t RESERVED7;
bogdanm 70:673126e12c73 284 __IO uint32_t PowerDown;
bogdanm 70:673126e12c73 285 uint32_t RESERVED8;
bogdanm 70:673126e12c73 286 __IO uint32_t Module_ID;
bogdanm 70:673126e12c73 287 } LPC_EMAC_TypeDef;
bogdanm 70:673126e12c73 288
bogdanm 70:673126e12c73 289 /*------------- LCD controller (LCD) -----------------------------------------*/
bogdanm 70:673126e12c73 290 typedef struct
bogdanm 70:673126e12c73 291 {
bogdanm 70:673126e12c73 292 __IO uint32_t TIMH; /* LCD Registers */
bogdanm 70:673126e12c73 293 __IO uint32_t TIMV;
bogdanm 70:673126e12c73 294 __IO uint32_t POL;
bogdanm 70:673126e12c73 295 __IO uint32_t LE;
bogdanm 70:673126e12c73 296 __IO uint32_t UPBASE;
bogdanm 70:673126e12c73 297 __IO uint32_t LPBASE;
bogdanm 70:673126e12c73 298 __IO uint32_t CTRL;
bogdanm 70:673126e12c73 299 __IO uint32_t INTMSK;
bogdanm 70:673126e12c73 300 __I uint32_t INTRAW;
bogdanm 70:673126e12c73 301 __I uint32_t INTSTAT;
bogdanm 70:673126e12c73 302 __O uint32_t INTCLR;
bogdanm 70:673126e12c73 303 __I uint32_t UPCURR;
bogdanm 70:673126e12c73 304 __I uint32_t LPCURR;
bogdanm 70:673126e12c73 305 uint32_t RESERVED0[115];
bogdanm 70:673126e12c73 306 __IO uint32_t PAL[128];
bogdanm 70:673126e12c73 307 uint32_t RESERVED1[256];
bogdanm 70:673126e12c73 308 __IO uint32_t CRSR_IMG[256];
bogdanm 70:673126e12c73 309 __IO uint32_t CRSR_CTRL;
bogdanm 70:673126e12c73 310 __IO uint32_t CRSR_CFG;
bogdanm 70:673126e12c73 311 __IO uint32_t CRSR_PAL0;
bogdanm 70:673126e12c73 312 __IO uint32_t CRSR_PAL1;
bogdanm 70:673126e12c73 313 __IO uint32_t CRSR_XY;
bogdanm 70:673126e12c73 314 __IO uint32_t CRSR_CLIP;
bogdanm 70:673126e12c73 315 uint32_t RESERVED2[2];
bogdanm 70:673126e12c73 316 __IO uint32_t CRSR_INTMSK;
bogdanm 70:673126e12c73 317 __O uint32_t CRSR_INTCLR;
bogdanm 70:673126e12c73 318 __I uint32_t CRSR_INTRAW;
bogdanm 70:673126e12c73 319 __I uint32_t CRSR_INTSTAT;
bogdanm 70:673126e12c73 320 } LPC_LCD_TypeDef;
bogdanm 70:673126e12c73 321
bogdanm 70:673126e12c73 322 /*------------- Universal Serial Bus (USB) -----------------------------------*/
bogdanm 70:673126e12c73 323 typedef struct
bogdanm 70:673126e12c73 324 {
bogdanm 70:673126e12c73 325 __I uint32_t Revision; /* USB Host Registers */
bogdanm 70:673126e12c73 326 __IO uint32_t Control;
bogdanm 70:673126e12c73 327 __IO uint32_t CommandStatus;
bogdanm 70:673126e12c73 328 __IO uint32_t InterruptStatus;
bogdanm 70:673126e12c73 329 __IO uint32_t InterruptEnable;
bogdanm 70:673126e12c73 330 __IO uint32_t InterruptDisable;
bogdanm 70:673126e12c73 331 __IO uint32_t HCCA;
bogdanm 70:673126e12c73 332 __I uint32_t PeriodCurrentED;
bogdanm 70:673126e12c73 333 __IO uint32_t ControlHeadED;
bogdanm 70:673126e12c73 334 __IO uint32_t ControlCurrentED;
bogdanm 70:673126e12c73 335 __IO uint32_t BulkHeadED;
bogdanm 70:673126e12c73 336 __IO uint32_t BulkCurrentED;
bogdanm 70:673126e12c73 337 __I uint32_t DoneHead;
bogdanm 70:673126e12c73 338 __IO uint32_t FmInterval;
bogdanm 70:673126e12c73 339 __I uint32_t FmRemaining;
bogdanm 70:673126e12c73 340 __I uint32_t FmNumber;
bogdanm 70:673126e12c73 341 __IO uint32_t PeriodicStart;
bogdanm 70:673126e12c73 342 __IO uint32_t LSTreshold;
bogdanm 70:673126e12c73 343 __IO uint32_t RhDescriptorA;
bogdanm 70:673126e12c73 344 __IO uint32_t RhDescriptorB;
bogdanm 70:673126e12c73 345 __IO uint32_t RhStatus;
bogdanm 70:673126e12c73 346 __IO uint32_t RhPortStatus1;
bogdanm 70:673126e12c73 347 __IO uint32_t RhPortStatus2;
bogdanm 70:673126e12c73 348 uint32_t RESERVED0[40];
bogdanm 70:673126e12c73 349 __I uint32_t Module_ID;
bogdanm 70:673126e12c73 350
bogdanm 70:673126e12c73 351 __I uint32_t IntSt; /* USB On-The-Go Registers */
bogdanm 70:673126e12c73 352 __IO uint32_t IntEn;
bogdanm 70:673126e12c73 353 __O uint32_t IntSet;
bogdanm 70:673126e12c73 354 __O uint32_t IntClr;
bogdanm 70:673126e12c73 355 __IO uint32_t StCtrl;
bogdanm 70:673126e12c73 356 __IO uint32_t Tmr;
bogdanm 70:673126e12c73 357 uint32_t RESERVED1[58];
bogdanm 70:673126e12c73 358
bogdanm 70:673126e12c73 359 __I uint32_t DevIntSt; /* USB Device Interrupt Registers */
bogdanm 70:673126e12c73 360 __IO uint32_t DevIntEn;
bogdanm 70:673126e12c73 361 __O uint32_t DevIntClr;
bogdanm 70:673126e12c73 362 __O uint32_t DevIntSet;
bogdanm 70:673126e12c73 363
bogdanm 70:673126e12c73 364 __O uint32_t CmdCode; /* USB Device SIE Command Registers */
bogdanm 70:673126e12c73 365 __I uint32_t CmdData;
bogdanm 70:673126e12c73 366
bogdanm 70:673126e12c73 367 __I uint32_t RxData; /* USB Device Transfer Registers */
bogdanm 70:673126e12c73 368 __O uint32_t TxData;
bogdanm 70:673126e12c73 369 __I uint32_t RxPLen;
bogdanm 70:673126e12c73 370 __O uint32_t TxPLen;
bogdanm 70:673126e12c73 371 __IO uint32_t Ctrl;
bogdanm 70:673126e12c73 372 __O uint32_t DevIntPri;
bogdanm 70:673126e12c73 373
bogdanm 70:673126e12c73 374 __I uint32_t EpIntSt; /* USB Device Endpoint Interrupt Regs */
bogdanm 70:673126e12c73 375 __IO uint32_t EpIntEn;
bogdanm 70:673126e12c73 376 __O uint32_t EpIntClr;
bogdanm 70:673126e12c73 377 __O uint32_t EpIntSet;
bogdanm 70:673126e12c73 378 __O uint32_t EpIntPri;
bogdanm 70:673126e12c73 379
bogdanm 70:673126e12c73 380 __IO uint32_t ReEp; /* USB Device Endpoint Realization Reg*/
bogdanm 70:673126e12c73 381 __O uint32_t EpInd;
bogdanm 70:673126e12c73 382 __IO uint32_t MaxPSize;
bogdanm 70:673126e12c73 383
bogdanm 70:673126e12c73 384 __I uint32_t DMARSt; /* USB Device DMA Registers */
bogdanm 70:673126e12c73 385 __O uint32_t DMARClr;
bogdanm 70:673126e12c73 386 __O uint32_t DMARSet;
bogdanm 70:673126e12c73 387 uint32_t RESERVED2[9];
bogdanm 70:673126e12c73 388 __IO uint32_t UDCAH;
bogdanm 70:673126e12c73 389 __I uint32_t EpDMASt;
bogdanm 70:673126e12c73 390 __O uint32_t EpDMAEn;
bogdanm 70:673126e12c73 391 __O uint32_t EpDMADis;
bogdanm 70:673126e12c73 392 __I uint32_t DMAIntSt;
bogdanm 70:673126e12c73 393 __IO uint32_t DMAIntEn;
bogdanm 70:673126e12c73 394 uint32_t RESERVED3[2];
bogdanm 70:673126e12c73 395 __I uint32_t EoTIntSt;
bogdanm 70:673126e12c73 396 __O uint32_t EoTIntClr;
bogdanm 70:673126e12c73 397 __O uint32_t EoTIntSet;
bogdanm 70:673126e12c73 398 __I uint32_t NDDRIntSt;
bogdanm 70:673126e12c73 399 __O uint32_t NDDRIntClr;
bogdanm 70:673126e12c73 400 __O uint32_t NDDRIntSet;
bogdanm 70:673126e12c73 401 __I uint32_t SysErrIntSt;
bogdanm 70:673126e12c73 402 __O uint32_t SysErrIntClr;
bogdanm 70:673126e12c73 403 __O uint32_t SysErrIntSet;
bogdanm 70:673126e12c73 404 uint32_t RESERVED4[15];
bogdanm 70:673126e12c73 405
bogdanm 70:673126e12c73 406 union {
bogdanm 70:673126e12c73 407 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
bogdanm 70:673126e12c73 408 __O uint32_t I2C_TX;
bogdanm 70:673126e12c73 409 };
bogdanm 70:673126e12c73 410 __IO uint32_t I2C_STS;
bogdanm 70:673126e12c73 411 __IO uint32_t I2C_CTL;
bogdanm 70:673126e12c73 412 __IO uint32_t I2C_CLKHI;
bogdanm 70:673126e12c73 413 __O uint32_t I2C_CLKLO;
bogdanm 70:673126e12c73 414 uint32_t RESERVED5[824];
bogdanm 70:673126e12c73 415
bogdanm 70:673126e12c73 416 union {
bogdanm 70:673126e12c73 417 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
bogdanm 70:673126e12c73 418 __IO uint32_t OTGClkCtrl;
bogdanm 70:673126e12c73 419 };
bogdanm 70:673126e12c73 420 union {
bogdanm 70:673126e12c73 421 __I uint32_t USBClkSt;
bogdanm 70:673126e12c73 422 __I uint32_t OTGClkSt;
bogdanm 70:673126e12c73 423 };
bogdanm 70:673126e12c73 424 } LPC_USB_TypeDef;
bogdanm 70:673126e12c73 425
bogdanm 70:673126e12c73 426 /*------------- CRC Engine (CRC) -----------------------------------------*/
bogdanm 70:673126e12c73 427 typedef struct
bogdanm 70:673126e12c73 428 {
bogdanm 70:673126e12c73 429 __IO uint32_t MODE;
bogdanm 70:673126e12c73 430 __IO uint32_t SEED;
bogdanm 70:673126e12c73 431 union {
bogdanm 70:673126e12c73 432 __I uint32_t SUM;
bogdanm 70:673126e12c73 433 struct {
bogdanm 70:673126e12c73 434 __O uint32_t DATA;
bogdanm 70:673126e12c73 435 } WR_DATA_DWORD;
bogdanm 70:673126e12c73 436
bogdanm 70:673126e12c73 437 struct {
bogdanm 70:673126e12c73 438 __O uint16_t DATA;
bogdanm 70:673126e12c73 439 uint16_t RESERVED;
bogdanm 70:673126e12c73 440 }WR_DATA_WORD;
bogdanm 70:673126e12c73 441
bogdanm 70:673126e12c73 442 struct {
bogdanm 70:673126e12c73 443 __O uint8_t DATA;
bogdanm 70:673126e12c73 444 uint8_t RESERVED[3];
bogdanm 70:673126e12c73 445 }WR_DATA_BYTE;
bogdanm 70:673126e12c73 446 };
bogdanm 70:673126e12c73 447 } LPC_CRC_TypeDef;
bogdanm 70:673126e12c73 448 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
bogdanm 70:673126e12c73 449 typedef struct
bogdanm 70:673126e12c73 450 {
bogdanm 70:673126e12c73 451 __IO uint32_t DIR;
bogdanm 70:673126e12c73 452 uint32_t RESERVED0[3];
bogdanm 70:673126e12c73 453 __IO uint32_t MASK;
bogdanm 70:673126e12c73 454 __IO uint32_t PIN;
bogdanm 70:673126e12c73 455 __IO uint32_t SET;
bogdanm 70:673126e12c73 456 __O uint32_t CLR;
bogdanm 70:673126e12c73 457 } LPC_GPIO_TypeDef;
bogdanm 70:673126e12c73 458
bogdanm 70:673126e12c73 459 typedef struct
bogdanm 70:673126e12c73 460 {
bogdanm 70:673126e12c73 461 __I uint32_t IntStatus;
bogdanm 70:673126e12c73 462 __I uint32_t IO0IntStatR;
bogdanm 70:673126e12c73 463 __I uint32_t IO0IntStatF;
bogdanm 70:673126e12c73 464 __O uint32_t IO0IntClr;
bogdanm 70:673126e12c73 465 __IO uint32_t IO0IntEnR;
bogdanm 70:673126e12c73 466 __IO uint32_t IO0IntEnF;
bogdanm 70:673126e12c73 467 uint32_t RESERVED0[3];
bogdanm 70:673126e12c73 468 __I uint32_t IO2IntStatR;
bogdanm 70:673126e12c73 469 __I uint32_t IO2IntStatF;
bogdanm 70:673126e12c73 470 __O uint32_t IO2IntClr;
bogdanm 70:673126e12c73 471 __IO uint32_t IO2IntEnR;
bogdanm 70:673126e12c73 472 __IO uint32_t IO2IntEnF;
bogdanm 70:673126e12c73 473 } LPC_GPIOINT_TypeDef;
bogdanm 70:673126e12c73 474
bogdanm 70:673126e12c73 475 /*------------- External Memory Controller (EMC) -----------------------------*/
bogdanm 70:673126e12c73 476 typedef struct
bogdanm 70:673126e12c73 477 {
bogdanm 70:673126e12c73 478 __IO uint32_t Control;
bogdanm 70:673126e12c73 479 __I uint32_t Status;
bogdanm 70:673126e12c73 480 __IO uint32_t Config;
bogdanm 70:673126e12c73 481 uint32_t RESERVED0[5];
bogdanm 70:673126e12c73 482 __IO uint32_t DynamicControl;
bogdanm 70:673126e12c73 483 __IO uint32_t DynamicRefresh;
bogdanm 70:673126e12c73 484 __IO uint32_t DynamicReadConfig;
bogdanm 70:673126e12c73 485 uint32_t RESERVED1[1];
bogdanm 70:673126e12c73 486 __IO uint32_t DynamicRP;
bogdanm 70:673126e12c73 487 __IO uint32_t DynamicRAS;
bogdanm 70:673126e12c73 488 __IO uint32_t DynamicSREX;
bogdanm 70:673126e12c73 489 __IO uint32_t DynamicAPR;
bogdanm 70:673126e12c73 490 __IO uint32_t DynamicDAL;
bogdanm 70:673126e12c73 491 __IO uint32_t DynamicWR;
bogdanm 70:673126e12c73 492 __IO uint32_t DynamicRC;
bogdanm 70:673126e12c73 493 __IO uint32_t DynamicRFC;
bogdanm 70:673126e12c73 494 __IO uint32_t DynamicXSR;
bogdanm 70:673126e12c73 495 __IO uint32_t DynamicRRD;
bogdanm 70:673126e12c73 496 __IO uint32_t DynamicMRD;
bogdanm 70:673126e12c73 497 uint32_t RESERVED2[9];
bogdanm 70:673126e12c73 498 __IO uint32_t StaticExtendedWait;
bogdanm 70:673126e12c73 499 uint32_t RESERVED3[31];
bogdanm 70:673126e12c73 500 __IO uint32_t DynamicConfig0;
bogdanm 70:673126e12c73 501 __IO uint32_t DynamicRasCas0;
bogdanm 70:673126e12c73 502 uint32_t RESERVED4[6];
bogdanm 70:673126e12c73 503 __IO uint32_t DynamicConfig1;
bogdanm 70:673126e12c73 504 __IO uint32_t DynamicRasCas1;
bogdanm 70:673126e12c73 505 uint32_t RESERVED5[6];
bogdanm 70:673126e12c73 506 __IO uint32_t DynamicConfig2;
bogdanm 70:673126e12c73 507 __IO uint32_t DynamicRasCas2;
bogdanm 70:673126e12c73 508 uint32_t RESERVED6[6];
bogdanm 70:673126e12c73 509 __IO uint32_t DynamicConfig3;
bogdanm 70:673126e12c73 510 __IO uint32_t DynamicRasCas3;
bogdanm 70:673126e12c73 511 uint32_t RESERVED7[38];
bogdanm 70:673126e12c73 512 __IO uint32_t StaticConfig0;
bogdanm 70:673126e12c73 513 __IO uint32_t StaticWaitWen0;
bogdanm 70:673126e12c73 514 __IO uint32_t StaticWaitOen0;
bogdanm 70:673126e12c73 515 __IO uint32_t StaticWaitRd0;
bogdanm 70:673126e12c73 516 __IO uint32_t StaticWaitPage0;
bogdanm 70:673126e12c73 517 __IO uint32_t StaticWaitWr0;
bogdanm 70:673126e12c73 518 __IO uint32_t StaticWaitTurn0;
bogdanm 70:673126e12c73 519 uint32_t RESERVED8[1];
bogdanm 70:673126e12c73 520 __IO uint32_t StaticConfig1;
bogdanm 70:673126e12c73 521 __IO uint32_t StaticWaitWen1;
bogdanm 70:673126e12c73 522 __IO uint32_t StaticWaitOen1;
bogdanm 70:673126e12c73 523 __IO uint32_t StaticWaitRd1;
bogdanm 70:673126e12c73 524 __IO uint32_t StaticWaitPage1;
bogdanm 70:673126e12c73 525 __IO uint32_t StaticWaitWr1;
bogdanm 70:673126e12c73 526 __IO uint32_t StaticWaitTurn1;
bogdanm 70:673126e12c73 527 uint32_t RESERVED9[1];
bogdanm 70:673126e12c73 528 __IO uint32_t StaticConfig2;
bogdanm 70:673126e12c73 529 __IO uint32_t StaticWaitWen2;
bogdanm 70:673126e12c73 530 __IO uint32_t StaticWaitOen2;
bogdanm 70:673126e12c73 531 __IO uint32_t StaticWaitRd2;
bogdanm 70:673126e12c73 532 __IO uint32_t StaticWaitPage2;
bogdanm 70:673126e12c73 533 __IO uint32_t StaticWaitWr2;
bogdanm 70:673126e12c73 534 __IO uint32_t StaticWaitTurn2;
bogdanm 70:673126e12c73 535 uint32_t RESERVED10[1];
bogdanm 70:673126e12c73 536 __IO uint32_t StaticConfig3;
bogdanm 70:673126e12c73 537 __IO uint32_t StaticWaitWen3;
bogdanm 70:673126e12c73 538 __IO uint32_t StaticWaitOen3;
bogdanm 70:673126e12c73 539 __IO uint32_t StaticWaitRd3;
bogdanm 70:673126e12c73 540 __IO uint32_t StaticWaitPage3;
bogdanm 70:673126e12c73 541 __IO uint32_t StaticWaitWr3;
bogdanm 70:673126e12c73 542 __IO uint32_t StaticWaitTurn3;
bogdanm 70:673126e12c73 543 } LPC_EMC_TypeDef;
bogdanm 70:673126e12c73 544
bogdanm 70:673126e12c73 545 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
bogdanm 70:673126e12c73 546 typedef struct
bogdanm 70:673126e12c73 547 {
bogdanm 70:673126e12c73 548 __IO uint8_t MOD;
bogdanm 70:673126e12c73 549 uint8_t RESERVED0[3];
bogdanm 70:673126e12c73 550 __IO uint32_t TC;
bogdanm 70:673126e12c73 551 __O uint8_t FEED;
bogdanm 70:673126e12c73 552 uint8_t RESERVED1[3];
bogdanm 70:673126e12c73 553 __I uint32_t TV;
bogdanm 70:673126e12c73 554 uint32_t RESERVED2;
bogdanm 70:673126e12c73 555 __IO uint32_t WARNINT;
bogdanm 70:673126e12c73 556 __IO uint32_t WINDOW;
bogdanm 70:673126e12c73 557 } LPC_WDT_TypeDef;
bogdanm 70:673126e12c73 558
bogdanm 70:673126e12c73 559 /*------------- Timer (TIM) --------------------------------------------------*/
bogdanm 70:673126e12c73 560 typedef struct
bogdanm 70:673126e12c73 561 {
bogdanm 70:673126e12c73 562 __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
bogdanm 70:673126e12c73 563 __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
bogdanm 70:673126e12c73 564 __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
bogdanm 70:673126e12c73 565 __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
bogdanm 70:673126e12c73 566 __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
bogdanm 70:673126e12c73 567 __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
bogdanm 70:673126e12c73 568 __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
bogdanm 70:673126e12c73 569 __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
bogdanm 70:673126e12c73 570 __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
bogdanm 70:673126e12c73 571 __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
bogdanm 70:673126e12c73 572 __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
bogdanm 70:673126e12c73 573 __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
bogdanm 70:673126e12c73 574 __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
bogdanm 70:673126e12c73 575 uint32_t RESERVED0[2];
bogdanm 70:673126e12c73 576 __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */
bogdanm 70:673126e12c73 577 uint32_t RESERVED1[12];
bogdanm 70:673126e12c73 578 __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */
bogdanm 70:673126e12c73 579 } LPC_TIM_TypeDef;
bogdanm 70:673126e12c73 580
bogdanm 70:673126e12c73 581
bogdanm 70:673126e12c73 582 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
bogdanm 70:673126e12c73 583 typedef struct
bogdanm 70:673126e12c73 584 {
bogdanm 70:673126e12c73 585 __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
bogdanm 70:673126e12c73 586 __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
bogdanm 70:673126e12c73 587 __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
bogdanm 70:673126e12c73 588 __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
bogdanm 70:673126e12c73 589 __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
bogdanm 70:673126e12c73 590 __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
bogdanm 70:673126e12c73 591 __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
bogdanm 70:673126e12c73 592 __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
bogdanm 70:673126e12c73 593 __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
bogdanm 70:673126e12c73 594 __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
bogdanm 70:673126e12c73 595 __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
bogdanm 70:673126e12c73 596 __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
bogdanm 70:673126e12c73 597 __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
bogdanm 70:673126e12c73 598 __I uint32_t CR2; /*!< Offset: 0x034 Capture Register 2 (R/ ) */
bogdanm 70:673126e12c73 599 __I uint32_t CR3; /*!< Offset: 0x038 Capture Register 3 (R/ ) */
bogdanm 70:673126e12c73 600 uint32_t RESERVED0;
bogdanm 70:673126e12c73 601 __IO uint32_t MR4; /*!< Offset: 0x040 Match Register 4 (R/W) */
bogdanm 70:673126e12c73 602 __IO uint32_t MR5; /*!< Offset: 0x044 Match Register 5 (R/W) */
bogdanm 70:673126e12c73 603 __IO uint32_t MR6; /*!< Offset: 0x048 Match Register 6 (R/W) */
bogdanm 70:673126e12c73 604 __IO uint32_t PCR; /*!< Offset: 0x04C PWM Control Register (R/W) */
bogdanm 70:673126e12c73 605 __IO uint32_t LER; /*!< Offset: 0x050 Load Enable Register (R/W) */
bogdanm 70:673126e12c73 606 uint32_t RESERVED1[7];
bogdanm 70:673126e12c73 607 __IO uint32_t CTCR; /*!< Offset: 0x070 Counter Control Register (R/W) */
bogdanm 70:673126e12c73 608 } LPC_PWM_TypeDef;
bogdanm 70:673126e12c73 609
bogdanm 70:673126e12c73 610 /*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/
bogdanm 70:673126e12c73 611 /* There are three types of UARTs on the chip:
bogdanm 70:673126e12c73 612 (1) UART0,UART2, and UART3 are the standard UART.
bogdanm 70:673126e12c73 613 (2) UART1 is the standard with modem capability.
bogdanm 70:673126e12c73 614 (3) USART(UART4) is the sync/async UART with smart card capability.
bogdanm 70:673126e12c73 615 More details can be found on the Users Manual. */
bogdanm 70:673126e12c73 616
bogdanm 70:673126e12c73 617 #if 0
bogdanm 70:673126e12c73 618 typedef struct
bogdanm 70:673126e12c73 619 {
bogdanm 70:673126e12c73 620 union {
bogdanm 70:673126e12c73 621 __I uint8_t RBR;
bogdanm 70:673126e12c73 622 __O uint8_t THR;
bogdanm 70:673126e12c73 623 __IO uint8_t DLL;
bogdanm 70:673126e12c73 624 uint32_t RESERVED0;
bogdanm 70:673126e12c73 625 };
bogdanm 70:673126e12c73 626 union {
bogdanm 70:673126e12c73 627 __IO uint8_t DLM;
bogdanm 70:673126e12c73 628 __IO uint32_t IER;
bogdanm 70:673126e12c73 629 };
bogdanm 70:673126e12c73 630 union {
bogdanm 70:673126e12c73 631 __I uint32_t IIR;
bogdanm 70:673126e12c73 632 __O uint8_t FCR;
bogdanm 70:673126e12c73 633 };
bogdanm 70:673126e12c73 634 __IO uint8_t LCR;
bogdanm 70:673126e12c73 635 uint8_t RESERVED1[7];
bogdanm 70:673126e12c73 636 __I uint8_t LSR;
bogdanm 70:673126e12c73 637 uint8_t RESERVED2[7];
bogdanm 70:673126e12c73 638 __IO uint8_t SCR;
bogdanm 70:673126e12c73 639 uint8_t RESERVED3[3];
bogdanm 70:673126e12c73 640 __IO uint32_t ACR;
bogdanm 70:673126e12c73 641 __IO uint8_t ICR;
bogdanm 70:673126e12c73 642 uint8_t RESERVED4[3];
bogdanm 70:673126e12c73 643 __IO uint8_t FDR;
bogdanm 70:673126e12c73 644 uint8_t RESERVED5[7];
bogdanm 70:673126e12c73 645 __IO uint8_t TER;
bogdanm 70:673126e12c73 646 uint8_t RESERVED6[39];
bogdanm 70:673126e12c73 647 __I uint8_t FIFOLVL;
bogdanm 70:673126e12c73 648 } LPC_UART_TypeDef;
bogdanm 70:673126e12c73 649 #else
bogdanm 70:673126e12c73 650 typedef struct
bogdanm 70:673126e12c73 651 {
bogdanm 70:673126e12c73 652 union
bogdanm 70:673126e12c73 653 {
bogdanm 70:673126e12c73 654 __I uint8_t RBR;
bogdanm 70:673126e12c73 655 __O uint8_t THR;
bogdanm 70:673126e12c73 656 __IO uint8_t DLL;
bogdanm 70:673126e12c73 657 uint32_t RESERVED0;
bogdanm 70:673126e12c73 658 };
bogdanm 70:673126e12c73 659 union
bogdanm 70:673126e12c73 660 {
bogdanm 70:673126e12c73 661 __IO uint8_t DLM;
bogdanm 70:673126e12c73 662 __IO uint32_t IER;
bogdanm 70:673126e12c73 663 };
bogdanm 70:673126e12c73 664 union
bogdanm 70:673126e12c73 665 {
bogdanm 70:673126e12c73 666 __I uint32_t IIR;
bogdanm 70:673126e12c73 667 __O uint8_t FCR;
bogdanm 70:673126e12c73 668 };
bogdanm 70:673126e12c73 669 __IO uint8_t LCR;
bogdanm 70:673126e12c73 670 uint8_t RESERVED1[7];//Reserved
bogdanm 70:673126e12c73 671 __I uint8_t LSR;
bogdanm 70:673126e12c73 672 uint8_t RESERVED2[7];//Reserved
bogdanm 70:673126e12c73 673 __IO uint8_t SCR;
bogdanm 70:673126e12c73 674 uint8_t RESERVED3[3];//Reserved
bogdanm 70:673126e12c73 675 __IO uint32_t ACR;
bogdanm 70:673126e12c73 676 __IO uint8_t ICR;
bogdanm 70:673126e12c73 677 uint8_t RESERVED4[3];//Reserved
bogdanm 70:673126e12c73 678 __IO uint8_t FDR;
bogdanm 70:673126e12c73 679 uint8_t RESERVED5[7];//Reserved
bogdanm 70:673126e12c73 680 __IO uint8_t TER;
bogdanm 70:673126e12c73 681 uint8_t RESERVED8[27];//Reserved
bogdanm 70:673126e12c73 682 __IO uint8_t RS485CTRL;
bogdanm 70:673126e12c73 683 uint8_t RESERVED9[3];//Reserved
bogdanm 70:673126e12c73 684 __IO uint8_t ADRMATCH;
bogdanm 70:673126e12c73 685 uint8_t RESERVED10[3];//Reserved
bogdanm 70:673126e12c73 686 __IO uint8_t RS485DLY;
bogdanm 70:673126e12c73 687 uint8_t RESERVED11[3];//Reserved
bogdanm 70:673126e12c73 688 __I uint8_t FIFOLVL;
bogdanm 70:673126e12c73 689 }LPC_UART_TypeDef;
bogdanm 70:673126e12c73 690 #endif
bogdanm 70:673126e12c73 691
bogdanm 70:673126e12c73 692
bogdanm 70:673126e12c73 693 typedef struct
bogdanm 70:673126e12c73 694 {
bogdanm 70:673126e12c73 695 union {
bogdanm 70:673126e12c73 696 __I uint8_t RBR;
bogdanm 70:673126e12c73 697 __O uint8_t THR;
bogdanm 70:673126e12c73 698 __IO uint8_t DLL;
bogdanm 70:673126e12c73 699 uint32_t RESERVED0;
bogdanm 70:673126e12c73 700 };
bogdanm 70:673126e12c73 701 union {
bogdanm 70:673126e12c73 702 __IO uint8_t DLM;
bogdanm 70:673126e12c73 703 __IO uint32_t IER;
bogdanm 70:673126e12c73 704 };
bogdanm 70:673126e12c73 705 union {
bogdanm 70:673126e12c73 706 __I uint32_t IIR;
bogdanm 70:673126e12c73 707 __O uint8_t FCR;
bogdanm 70:673126e12c73 708 };
bogdanm 70:673126e12c73 709 __IO uint8_t LCR;
bogdanm 70:673126e12c73 710 uint8_t RESERVED1[3];
bogdanm 70:673126e12c73 711 __IO uint8_t MCR;
bogdanm 70:673126e12c73 712 uint8_t RESERVED2[3];
bogdanm 70:673126e12c73 713 __I uint8_t LSR;
bogdanm 70:673126e12c73 714 uint8_t RESERVED3[3];
bogdanm 70:673126e12c73 715 __I uint8_t MSR;
bogdanm 70:673126e12c73 716 uint8_t RESERVED4[3];
bogdanm 70:673126e12c73 717 __IO uint8_t SCR;
bogdanm 70:673126e12c73 718 uint8_t RESERVED5[3];
bogdanm 70:673126e12c73 719 __IO uint32_t ACR;
bogdanm 70:673126e12c73 720 uint32_t RESERVED6;
bogdanm 70:673126e12c73 721 __IO uint32_t FDR;
bogdanm 70:673126e12c73 722 uint32_t RESERVED7;
bogdanm 70:673126e12c73 723 __IO uint8_t TER;
bogdanm 70:673126e12c73 724 uint8_t RESERVED8[27];
bogdanm 70:673126e12c73 725 __IO uint8_t RS485CTRL;
bogdanm 70:673126e12c73 726 uint8_t RESERVED9[3];
bogdanm 70:673126e12c73 727 __IO uint8_t ADRMATCH;
bogdanm 70:673126e12c73 728 uint8_t RESERVED10[3];
bogdanm 70:673126e12c73 729 __IO uint8_t RS485DLY;
bogdanm 70:673126e12c73 730 uint8_t RESERVED11[3];
bogdanm 70:673126e12c73 731 __I uint8_t FIFOLVL;
bogdanm 70:673126e12c73 732 } LPC_UART1_TypeDef;
bogdanm 70:673126e12c73 733
bogdanm 70:673126e12c73 734 typedef struct
bogdanm 70:673126e12c73 735 {
bogdanm 70:673126e12c73 736 union {
bogdanm 70:673126e12c73 737 __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */
bogdanm 70:673126e12c73 738 __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */
bogdanm 70:673126e12c73 739 __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
bogdanm 70:673126e12c73 740 };
bogdanm 70:673126e12c73 741 union {
bogdanm 70:673126e12c73 742 __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
bogdanm 70:673126e12c73 743 __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
bogdanm 70:673126e12c73 744 };
bogdanm 70:673126e12c73 745 union {
bogdanm 70:673126e12c73 746 __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
bogdanm 70:673126e12c73 747 __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */
bogdanm 70:673126e12c73 748 };
bogdanm 70:673126e12c73 749 __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */
bogdanm 70:673126e12c73 750 __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */
bogdanm 70:673126e12c73 751 __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */
bogdanm 70:673126e12c73 752 __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */
bogdanm 70:673126e12c73 753 __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */
bogdanm 70:673126e12c73 754 __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
bogdanm 70:673126e12c73 755 __IO uint32_t ICR; /*!< Offset: 0x024 irDA Control Register (R/W) */
bogdanm 70:673126e12c73 756 __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */
bogdanm 70:673126e12c73 757 __IO uint32_t OSR; /*!< Offset: 0x02C Over sampling Register (R/W) */
bogdanm 70:673126e12c73 758 __O uint32_t POP; /*!< Offset: 0x030 NHP Pop Register (W) */
bogdanm 70:673126e12c73 759 __IO uint32_t MODE; /*!< Offset: 0x034 NHP Mode selection Register (W) */
bogdanm 70:673126e12c73 760 uint32_t RESERVED0[2];
bogdanm 70:673126e12c73 761 __IO uint32_t HDEN; /*!< Offset: 0x040 Half duplex Enable Register (R/W) */
bogdanm 70:673126e12c73 762 uint32_t RESERVED1;
bogdanm 70:673126e12c73 763 __IO uint32_t SCI_CTRL; /*!< Offset: 0x048 Smart card Interface Control Register (R/W) */
bogdanm 70:673126e12c73 764 __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
bogdanm 70:673126e12c73 765 __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
bogdanm 70:673126e12c73 766 __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
bogdanm 70:673126e12c73 767 __IO uint32_t SYNCCTRL; /*!< Offset: 0x058 Synchronous Mode Control Register (R/W ) */
bogdanm 70:673126e12c73 768 __IO uint32_t TER; /*!< Offset: 0x05C Transmit Enable Register (R/W) */
bogdanm 70:673126e12c73 769 uint32_t RESERVED2[989];
bogdanm 70:673126e12c73 770 __I uint32_t CFG; /*!< Offset: 0xFD4 Configuration Register (R) */
bogdanm 70:673126e12c73 771 __O uint32_t INTCE; /*!< Offset: 0xFD8 Interrupt Clear Enable Register (W) */
bogdanm 70:673126e12c73 772 __O uint32_t INTSE; /*!< Offset: 0xFDC Interrupt Set Enable Register (W) */
bogdanm 70:673126e12c73 773 __I uint32_t INTS; /*!< Offset: 0xFE0 Interrupt Status Register (R) */
bogdanm 70:673126e12c73 774 __I uint32_t INTE; /*!< Offset: 0xFE4 Interrupt Enable Register (R) */
bogdanm 70:673126e12c73 775 __O uint32_t INTCS; /*!< Offset: 0xFE8 Interrupt Clear Status Register (W) */
bogdanm 70:673126e12c73 776 __O uint32_t INTSS; /*!< Offset: 0xFEC Interrupt Set Status Register (W) */
bogdanm 70:673126e12c73 777 uint32_t RESERVED3[3];
bogdanm 70:673126e12c73 778 __I uint32_t MID; /*!< Offset: 0xFFC Module Identification Register (R) */
bogdanm 70:673126e12c73 779 } LPC_UART4_TypeDef;
bogdanm 70:673126e12c73 780 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
bogdanm 70:673126e12c73 781 typedef struct
bogdanm 70:673126e12c73 782 {
bogdanm 70:673126e12c73 783 __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */
bogdanm 70:673126e12c73 784 __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */
bogdanm 70:673126e12c73 785 __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */
bogdanm 70:673126e12c73 786 __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
bogdanm 70:673126e12c73 787 __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
bogdanm 70:673126e12c73 788 __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
bogdanm 70:673126e12c73 789 __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
bogdanm 70:673126e12c73 790 __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */
bogdanm 70:673126e12c73 791 __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
bogdanm 70:673126e12c73 792 __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
bogdanm 70:673126e12c73 793 __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
bogdanm 70:673126e12c73 794 __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */
bogdanm 70:673126e12c73 795 __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
bogdanm 70:673126e12c73 796 __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
bogdanm 70:673126e12c73 797 __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
bogdanm 70:673126e12c73 798 __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
bogdanm 70:673126e12c73 799 } LPC_I2C_TypeDef;
bogdanm 70:673126e12c73 800
bogdanm 70:673126e12c73 801 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
bogdanm 70:673126e12c73 802 typedef struct
bogdanm 70:673126e12c73 803 {
bogdanm 70:673126e12c73 804 __IO uint8_t ILR;
bogdanm 70:673126e12c73 805 uint8_t RESERVED0[7];
bogdanm 70:673126e12c73 806 __IO uint8_t CCR;
bogdanm 70:673126e12c73 807 uint8_t RESERVED1[3];
bogdanm 70:673126e12c73 808 __IO uint8_t CIIR;
bogdanm 70:673126e12c73 809 uint8_t RESERVED2[3];
bogdanm 70:673126e12c73 810 __IO uint8_t AMR;
bogdanm 70:673126e12c73 811 uint8_t RESERVED3[3];
bogdanm 70:673126e12c73 812 __I uint32_t CTIME0;
bogdanm 70:673126e12c73 813 __I uint32_t CTIME1;
bogdanm 70:673126e12c73 814 __I uint32_t CTIME2;
bogdanm 70:673126e12c73 815 __IO uint8_t SEC;
bogdanm 70:673126e12c73 816 uint8_t RESERVED4[3];
bogdanm 70:673126e12c73 817 __IO uint8_t MIN;
bogdanm 70:673126e12c73 818 uint8_t RESERVED5[3];
bogdanm 70:673126e12c73 819 __IO uint8_t HOUR;
bogdanm 70:673126e12c73 820 uint8_t RESERVED6[3];
bogdanm 70:673126e12c73 821 __IO uint8_t DOM;
bogdanm 70:673126e12c73 822 uint8_t RESERVED7[3];
bogdanm 70:673126e12c73 823 __IO uint8_t DOW;
bogdanm 70:673126e12c73 824 uint8_t RESERVED8[3];
bogdanm 70:673126e12c73 825 __IO uint16_t DOY;
bogdanm 70:673126e12c73 826 uint16_t RESERVED9;
bogdanm 70:673126e12c73 827 __IO uint8_t MONTH;
bogdanm 70:673126e12c73 828 uint8_t RESERVED10[3];
bogdanm 70:673126e12c73 829 __IO uint16_t YEAR;
bogdanm 70:673126e12c73 830 uint16_t RESERVED11;
bogdanm 70:673126e12c73 831 __IO uint32_t CALIBRATION;
bogdanm 70:673126e12c73 832 __IO uint32_t GPREG0;
bogdanm 70:673126e12c73 833 __IO uint32_t GPREG1;
bogdanm 70:673126e12c73 834 __IO uint32_t GPREG2;
bogdanm 70:673126e12c73 835 __IO uint32_t GPREG3;
bogdanm 70:673126e12c73 836 __IO uint32_t GPREG4;
bogdanm 70:673126e12c73 837 __IO uint8_t RTC_AUXEN;
bogdanm 70:673126e12c73 838 uint8_t RESERVED12[3];
bogdanm 70:673126e12c73 839 __IO uint8_t RTC_AUX;
bogdanm 70:673126e12c73 840 uint8_t RESERVED13[3];
bogdanm 70:673126e12c73 841 __IO uint8_t ALSEC;
bogdanm 70:673126e12c73 842 uint8_t RESERVED14[3];
bogdanm 70:673126e12c73 843 __IO uint8_t ALMIN;
bogdanm 70:673126e12c73 844 uint8_t RESERVED15[3];
bogdanm 70:673126e12c73 845 __IO uint8_t ALHOUR;
bogdanm 70:673126e12c73 846 uint8_t RESERVED16[3];
bogdanm 70:673126e12c73 847 __IO uint8_t ALDOM;
bogdanm 70:673126e12c73 848 uint8_t RESERVED17[3];
bogdanm 70:673126e12c73 849 __IO uint8_t ALDOW;
bogdanm 70:673126e12c73 850 uint8_t RESERVED18[3];
bogdanm 70:673126e12c73 851 __IO uint16_t ALDOY;
bogdanm 70:673126e12c73 852 uint16_t RESERVED19;
bogdanm 70:673126e12c73 853 __IO uint8_t ALMON;
bogdanm 70:673126e12c73 854 uint8_t RESERVED20[3];
bogdanm 70:673126e12c73 855 __IO uint16_t ALYEAR;
bogdanm 70:673126e12c73 856 uint16_t RESERVED21;
bogdanm 70:673126e12c73 857 __IO uint32_t ERSTATUS;
bogdanm 70:673126e12c73 858 __IO uint32_t ERCONTROL;
bogdanm 70:673126e12c73 859 __IO uint32_t ERCOUNTERS;
bogdanm 70:673126e12c73 860 uint32_t RESERVED22;
bogdanm 70:673126e12c73 861 __IO uint32_t ERFIRSTSTAMP0;
bogdanm 70:673126e12c73 862 __IO uint32_t ERFIRSTSTAMP1;
bogdanm 70:673126e12c73 863 __IO uint32_t ERFIRSTSTAMP2;
bogdanm 70:673126e12c73 864 uint32_t RESERVED23;
bogdanm 70:673126e12c73 865 __IO uint32_t ERLASTSTAMP0;
bogdanm 70:673126e12c73 866 __IO uint32_t ERLASTSTAMP1;
bogdanm 70:673126e12c73 867 __IO uint32_t ERLASTSTAMP2;
bogdanm 70:673126e12c73 868 } LPC_RTC_TypeDef;
bogdanm 70:673126e12c73 869
bogdanm 70:673126e12c73 870
bogdanm 70:673126e12c73 871
bogdanm 70:673126e12c73 872 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
bogdanm 70:673126e12c73 873 typedef struct
bogdanm 70:673126e12c73 874 {
bogdanm 70:673126e12c73 875 __IO uint32_t P0_0; /* 0x000 */
bogdanm 70:673126e12c73 876 __IO uint32_t P0_1;
bogdanm 70:673126e12c73 877 __IO uint32_t P0_2;
bogdanm 70:673126e12c73 878 __IO uint32_t P0_3;
bogdanm 70:673126e12c73 879 __IO uint32_t P0_4;
bogdanm 70:673126e12c73 880 __IO uint32_t P0_5;
bogdanm 70:673126e12c73 881 __IO uint32_t P0_6;
bogdanm 70:673126e12c73 882 __IO uint32_t P0_7;
bogdanm 70:673126e12c73 883
bogdanm 70:673126e12c73 884 __IO uint32_t P0_8; /* 0x020 */
bogdanm 70:673126e12c73 885 __IO uint32_t P0_9;
bogdanm 70:673126e12c73 886 __IO uint32_t P0_10;
bogdanm 70:673126e12c73 887 __IO uint32_t P0_11;
bogdanm 70:673126e12c73 888 __IO uint32_t P0_12;
bogdanm 70:673126e12c73 889 __IO uint32_t P0_13;
bogdanm 70:673126e12c73 890 __IO uint32_t P0_14;
bogdanm 70:673126e12c73 891 __IO uint32_t P0_15;
bogdanm 70:673126e12c73 892
bogdanm 70:673126e12c73 893 __IO uint32_t P0_16; /* 0x040 */
bogdanm 70:673126e12c73 894 __IO uint32_t P0_17;
bogdanm 70:673126e12c73 895 __IO uint32_t P0_18;
bogdanm 70:673126e12c73 896 __IO uint32_t P0_19;
bogdanm 70:673126e12c73 897 __IO uint32_t P0_20;
bogdanm 70:673126e12c73 898 __IO uint32_t P0_21;
bogdanm 70:673126e12c73 899 __IO uint32_t P0_22;
bogdanm 70:673126e12c73 900 __IO uint32_t P0_23;
bogdanm 70:673126e12c73 901
bogdanm 70:673126e12c73 902 __IO uint32_t P0_24; /* 0x060 */
bogdanm 70:673126e12c73 903 __IO uint32_t P0_25;
bogdanm 70:673126e12c73 904 __IO uint32_t P0_26;
bogdanm 70:673126e12c73 905 __IO uint32_t P0_27;
bogdanm 70:673126e12c73 906 __IO uint32_t P0_28;
bogdanm 70:673126e12c73 907 __IO uint32_t P0_29;
bogdanm 70:673126e12c73 908 __IO uint32_t P0_30;
bogdanm 70:673126e12c73 909 __IO uint32_t P0_31;
bogdanm 70:673126e12c73 910
bogdanm 70:673126e12c73 911 __IO uint32_t P1_0; /* 0x080 */
bogdanm 70:673126e12c73 912 __IO uint32_t P1_1;
bogdanm 70:673126e12c73 913 __IO uint32_t P1_2;
bogdanm 70:673126e12c73 914 __IO uint32_t P1_3;
bogdanm 70:673126e12c73 915 __IO uint32_t P1_4;
bogdanm 70:673126e12c73 916 __IO uint32_t P1_5;
bogdanm 70:673126e12c73 917 __IO uint32_t P1_6;
bogdanm 70:673126e12c73 918 __IO uint32_t P1_7;
bogdanm 70:673126e12c73 919
bogdanm 70:673126e12c73 920 __IO uint32_t P1_8; /* 0x0A0 */
bogdanm 70:673126e12c73 921 __IO uint32_t P1_9;
bogdanm 70:673126e12c73 922 __IO uint32_t P1_10;
bogdanm 70:673126e12c73 923 __IO uint32_t P1_11;
bogdanm 70:673126e12c73 924 __IO uint32_t P1_12;
bogdanm 70:673126e12c73 925 __IO uint32_t P1_13;
bogdanm 70:673126e12c73 926 __IO uint32_t P1_14;
bogdanm 70:673126e12c73 927 __IO uint32_t P1_15;
bogdanm 70:673126e12c73 928
bogdanm 70:673126e12c73 929 __IO uint32_t P1_16; /* 0x0C0 */
bogdanm 70:673126e12c73 930 __IO uint32_t P1_17;
bogdanm 70:673126e12c73 931 __IO uint32_t P1_18;
bogdanm 70:673126e12c73 932 __IO uint32_t P1_19;
bogdanm 70:673126e12c73 933 __IO uint32_t P1_20;
bogdanm 70:673126e12c73 934 __IO uint32_t P1_21;
bogdanm 70:673126e12c73 935 __IO uint32_t P1_22;
bogdanm 70:673126e12c73 936 __IO uint32_t P1_23;
bogdanm 70:673126e12c73 937
bogdanm 70:673126e12c73 938 __IO uint32_t P1_24; /* 0x0E0 */
bogdanm 70:673126e12c73 939 __IO uint32_t P1_25;
bogdanm 70:673126e12c73 940 __IO uint32_t P1_26;
bogdanm 70:673126e12c73 941 __IO uint32_t P1_27;
bogdanm 70:673126e12c73 942 __IO uint32_t P1_28;
bogdanm 70:673126e12c73 943 __IO uint32_t P1_29;
bogdanm 70:673126e12c73 944 __IO uint32_t P1_30;
bogdanm 70:673126e12c73 945 __IO uint32_t P1_31;
bogdanm 70:673126e12c73 946
bogdanm 70:673126e12c73 947 __IO uint32_t P2_0; /* 0x100 */
bogdanm 70:673126e12c73 948 __IO uint32_t P2_1;
bogdanm 70:673126e12c73 949 __IO uint32_t P2_2;
bogdanm 70:673126e12c73 950 __IO uint32_t P2_3;
bogdanm 70:673126e12c73 951 __IO uint32_t P2_4;
bogdanm 70:673126e12c73 952 __IO uint32_t P2_5;
bogdanm 70:673126e12c73 953 __IO uint32_t P2_6;
bogdanm 70:673126e12c73 954 __IO uint32_t P2_7;
bogdanm 70:673126e12c73 955
bogdanm 70:673126e12c73 956 __IO uint32_t P2_8; /* 0x120 */
bogdanm 70:673126e12c73 957 __IO uint32_t P2_9;
bogdanm 70:673126e12c73 958 __IO uint32_t P2_10;
bogdanm 70:673126e12c73 959 __IO uint32_t P2_11;
bogdanm 70:673126e12c73 960 __IO uint32_t P2_12;
bogdanm 70:673126e12c73 961 __IO uint32_t P2_13;
bogdanm 70:673126e12c73 962 __IO uint32_t P2_14;
bogdanm 70:673126e12c73 963 __IO uint32_t P2_15;
bogdanm 70:673126e12c73 964
bogdanm 70:673126e12c73 965 __IO uint32_t P2_16; /* 0x140 */
bogdanm 70:673126e12c73 966 __IO uint32_t P2_17;
bogdanm 70:673126e12c73 967 __IO uint32_t P2_18;
bogdanm 70:673126e12c73 968 __IO uint32_t P2_19;
bogdanm 70:673126e12c73 969 __IO uint32_t P2_20;
bogdanm 70:673126e12c73 970 __IO uint32_t P2_21;
bogdanm 70:673126e12c73 971 __IO uint32_t P2_22;
bogdanm 70:673126e12c73 972 __IO uint32_t P2_23;
bogdanm 70:673126e12c73 973
bogdanm 70:673126e12c73 974 __IO uint32_t P2_24; /* 0x160 */
bogdanm 70:673126e12c73 975 __IO uint32_t P2_25;
bogdanm 70:673126e12c73 976 __IO uint32_t P2_26;
bogdanm 70:673126e12c73 977 __IO uint32_t P2_27;
bogdanm 70:673126e12c73 978 __IO uint32_t P2_28;
bogdanm 70:673126e12c73 979 __IO uint32_t P2_29;
bogdanm 70:673126e12c73 980 __IO uint32_t P2_30;
bogdanm 70:673126e12c73 981 __IO uint32_t P2_31;
bogdanm 70:673126e12c73 982
bogdanm 70:673126e12c73 983 __IO uint32_t P3_0; /* 0x180 */
bogdanm 70:673126e12c73 984 __IO uint32_t P3_1;
bogdanm 70:673126e12c73 985 __IO uint32_t P3_2;
bogdanm 70:673126e12c73 986 __IO uint32_t P3_3;
bogdanm 70:673126e12c73 987 __IO uint32_t P3_4;
bogdanm 70:673126e12c73 988 __IO uint32_t P3_5;
bogdanm 70:673126e12c73 989 __IO uint32_t P3_6;
bogdanm 70:673126e12c73 990 __IO uint32_t P3_7;
bogdanm 70:673126e12c73 991
bogdanm 70:673126e12c73 992 __IO uint32_t P3_8; /* 0x1A0 */
bogdanm 70:673126e12c73 993 __IO uint32_t P3_9;
bogdanm 70:673126e12c73 994 __IO uint32_t P3_10;
bogdanm 70:673126e12c73 995 __IO uint32_t P3_11;
bogdanm 70:673126e12c73 996 __IO uint32_t P3_12;
bogdanm 70:673126e12c73 997 __IO uint32_t P3_13;
bogdanm 70:673126e12c73 998 __IO uint32_t P3_14;
bogdanm 70:673126e12c73 999 __IO uint32_t P3_15;
bogdanm 70:673126e12c73 1000
bogdanm 70:673126e12c73 1001 __IO uint32_t P3_16; /* 0x1C0 */
bogdanm 70:673126e12c73 1002 __IO uint32_t P3_17;
bogdanm 70:673126e12c73 1003 __IO uint32_t P3_18;
bogdanm 70:673126e12c73 1004 __IO uint32_t P3_19;
bogdanm 70:673126e12c73 1005 __IO uint32_t P3_20;
bogdanm 70:673126e12c73 1006 __IO uint32_t P3_21;
bogdanm 70:673126e12c73 1007 __IO uint32_t P3_22;
bogdanm 70:673126e12c73 1008 __IO uint32_t P3_23;
bogdanm 70:673126e12c73 1009
bogdanm 70:673126e12c73 1010 __IO uint32_t P3_24; /* 0x1E0 */
bogdanm 70:673126e12c73 1011 __IO uint32_t P3_25;
bogdanm 70:673126e12c73 1012 __IO uint32_t P3_26;
bogdanm 70:673126e12c73 1013 __IO uint32_t P3_27;
bogdanm 70:673126e12c73 1014 __IO uint32_t P3_28;
bogdanm 70:673126e12c73 1015 __IO uint32_t P3_29;
bogdanm 70:673126e12c73 1016 __IO uint32_t P3_30;
bogdanm 70:673126e12c73 1017 __IO uint32_t P3_31;
bogdanm 70:673126e12c73 1018
bogdanm 70:673126e12c73 1019 __IO uint32_t P4_0; /* 0x200 */
bogdanm 70:673126e12c73 1020 __IO uint32_t P4_1;
bogdanm 70:673126e12c73 1021 __IO uint32_t P4_2;
bogdanm 70:673126e12c73 1022 __IO uint32_t P4_3;
bogdanm 70:673126e12c73 1023 __IO uint32_t P4_4;
bogdanm 70:673126e12c73 1024 __IO uint32_t P4_5;
bogdanm 70:673126e12c73 1025 __IO uint32_t P4_6;
bogdanm 70:673126e12c73 1026 __IO uint32_t P4_7;
bogdanm 70:673126e12c73 1027
bogdanm 70:673126e12c73 1028 __IO uint32_t P4_8; /* 0x220 */
bogdanm 70:673126e12c73 1029 __IO uint32_t P4_9;
bogdanm 70:673126e12c73 1030 __IO uint32_t P4_10;
bogdanm 70:673126e12c73 1031 __IO uint32_t P4_11;
bogdanm 70:673126e12c73 1032 __IO uint32_t P4_12;
bogdanm 70:673126e12c73 1033 __IO uint32_t P4_13;
bogdanm 70:673126e12c73 1034 __IO uint32_t P4_14;
bogdanm 70:673126e12c73 1035 __IO uint32_t P4_15;
bogdanm 70:673126e12c73 1036
bogdanm 70:673126e12c73 1037 __IO uint32_t P4_16; /* 0x240 */
bogdanm 70:673126e12c73 1038 __IO uint32_t P4_17;
bogdanm 70:673126e12c73 1039 __IO uint32_t P4_18;
bogdanm 70:673126e12c73 1040 __IO uint32_t P4_19;
bogdanm 70:673126e12c73 1041 __IO uint32_t P4_20;
bogdanm 70:673126e12c73 1042 __IO uint32_t P4_21;
bogdanm 70:673126e12c73 1043 __IO uint32_t P4_22;
bogdanm 70:673126e12c73 1044 __IO uint32_t P4_23;
bogdanm 70:673126e12c73 1045
bogdanm 70:673126e12c73 1046 __IO uint32_t P4_24; /* 0x260 */
bogdanm 70:673126e12c73 1047 __IO uint32_t P4_25;
bogdanm 70:673126e12c73 1048 __IO uint32_t P4_26;
bogdanm 70:673126e12c73 1049 __IO uint32_t P4_27;
bogdanm 70:673126e12c73 1050 __IO uint32_t P4_28;
bogdanm 70:673126e12c73 1051 __IO uint32_t P4_29;
bogdanm 70:673126e12c73 1052 __IO uint32_t P4_30;
bogdanm 70:673126e12c73 1053 __IO uint32_t P4_31;
bogdanm 70:673126e12c73 1054
bogdanm 70:673126e12c73 1055 __IO uint32_t P5_0; /* 0x280 */
bogdanm 70:673126e12c73 1056 __IO uint32_t P5_1;
bogdanm 70:673126e12c73 1057 __IO uint32_t P5_2;
bogdanm 70:673126e12c73 1058 __IO uint32_t P5_3;
bogdanm 70:673126e12c73 1059 __IO uint32_t P5_4; /* 0x290 */
bogdanm 70:673126e12c73 1060 } LPC_IOCON_TypeDef;
bogdanm 70:673126e12c73 1061
bogdanm 70:673126e12c73 1062
bogdanm 70:673126e12c73 1063
bogdanm 70:673126e12c73 1064
bogdanm 70:673126e12c73 1065
bogdanm 70:673126e12c73 1066
bogdanm 70:673126e12c73 1067 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
bogdanm 70:673126e12c73 1068 typedef struct
bogdanm 70:673126e12c73 1069 {
bogdanm 70:673126e12c73 1070 __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */
bogdanm 70:673126e12c73 1071 __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */
bogdanm 70:673126e12c73 1072 __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */
bogdanm 70:673126e12c73 1073 __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */
bogdanm 70:673126e12c73 1074 __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */
bogdanm 70:673126e12c73 1075 __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
bogdanm 70:673126e12c73 1076 __IO uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */
bogdanm 70:673126e12c73 1077 __IO uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */
bogdanm 70:673126e12c73 1078 __IO uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */
bogdanm 70:673126e12c73 1079 __IO uint32_t DMACR;
bogdanm 70:673126e12c73 1080 } LPC_SSP_TypeDef;
bogdanm 70:673126e12c73 1081
bogdanm 70:673126e12c73 1082 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
bogdanm 70:673126e12c73 1083 typedef struct
bogdanm 70:673126e12c73 1084 {
bogdanm 70:673126e12c73 1085 __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */
bogdanm 70:673126e12c73 1086 __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */
bogdanm 70:673126e12c73 1087 uint32_t RESERVED0;
bogdanm 70:673126e12c73 1088 __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */
bogdanm 70:673126e12c73 1089 __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
bogdanm 70:673126e12c73 1090 __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */
bogdanm 70:673126e12c73 1091 __IO uint32_t ADTRM;
bogdanm 70:673126e12c73 1092 } LPC_ADC_TypeDef;
bogdanm 70:673126e12c73 1093
bogdanm 70:673126e12c73 1094 /*------------- Controller Area Network (CAN) --------------------------------*/
bogdanm 70:673126e12c73 1095 typedef struct
bogdanm 70:673126e12c73 1096 {
bogdanm 70:673126e12c73 1097 __IO uint32_t mask[512]; /* ID Masks */
bogdanm 70:673126e12c73 1098 } LPC_CANAF_RAM_TypeDef;
bogdanm 70:673126e12c73 1099
bogdanm 70:673126e12c73 1100 typedef struct /* Acceptance Filter Registers */
bogdanm 70:673126e12c73 1101 {
bogdanm 70:673126e12c73 1102 ///Offset: 0x00000000 - Acceptance Filter Register
bogdanm 70:673126e12c73 1103 __IO uint32_t AFMR;
bogdanm 70:673126e12c73 1104
bogdanm 70:673126e12c73 1105 ///Offset: 0x00000004 - Standard Frame Individual Start Address Register
bogdanm 70:673126e12c73 1106 __IO uint32_t SFF_sa;
bogdanm 70:673126e12c73 1107
bogdanm 70:673126e12c73 1108 ///Offset: 0x00000008 - Standard Frame Group Start Address Register
bogdanm 70:673126e12c73 1109 __IO uint32_t SFF_GRP_sa;
bogdanm 70:673126e12c73 1110
bogdanm 70:673126e12c73 1111 ///Offset: 0x0000000C - Extended Frame Start Address Register
bogdanm 70:673126e12c73 1112 __IO uint32_t EFF_sa;
bogdanm 70:673126e12c73 1113
bogdanm 70:673126e12c73 1114 ///Offset: 0x00000010 - Extended Frame Group Start Address Register
bogdanm 70:673126e12c73 1115 __IO uint32_t EFF_GRP_sa;
bogdanm 70:673126e12c73 1116
bogdanm 70:673126e12c73 1117 ///Offset: 0x00000014 - End of AF Tables register
bogdanm 70:673126e12c73 1118 __IO uint32_t ENDofTable;
bogdanm 70:673126e12c73 1119
bogdanm 70:673126e12c73 1120 ///Offset: 0x00000018 - LUT Error Address register
bogdanm 70:673126e12c73 1121 __I uint32_t LUTerrAd;
bogdanm 70:673126e12c73 1122
bogdanm 70:673126e12c73 1123 ///Offset: 0x0000001C - LUT Error Register
bogdanm 70:673126e12c73 1124 __I uint32_t LUTerr;
bogdanm 70:673126e12c73 1125
bogdanm 70:673126e12c73 1126 ///Offset: 0x00000020 - CAN Central Transmit Status Register
bogdanm 70:673126e12c73 1127 __IO uint32_t FCANIE;
bogdanm 70:673126e12c73 1128
bogdanm 70:673126e12c73 1129 ///Offset: 0x00000024 - FullCAN Interrupt and Capture registers 0
bogdanm 70:673126e12c73 1130 __IO uint32_t FCANIC0;
bogdanm 70:673126e12c73 1131
bogdanm 70:673126e12c73 1132 ///Offset: 0x00000028 - FullCAN Interrupt and Capture registers 1
bogdanm 70:673126e12c73 1133 __IO uint32_t FCANIC1;
bogdanm 70:673126e12c73 1134 } LPC_CANAF_TypeDef;
bogdanm 70:673126e12c73 1135
bogdanm 70:673126e12c73 1136 typedef struct /* Central Registers */
bogdanm 70:673126e12c73 1137 {
bogdanm 70:673126e12c73 1138 __I uint32_t TxSR;
bogdanm 70:673126e12c73 1139 __I uint32_t RxSR;
bogdanm 70:673126e12c73 1140 __I uint32_t MSR;
bogdanm 70:673126e12c73 1141 } LPC_CANCR_TypeDef;
bogdanm 70:673126e12c73 1142
bogdanm 70:673126e12c73 1143 typedef struct /* Controller Registers */
bogdanm 70:673126e12c73 1144 {
bogdanm 70:673126e12c73 1145 ///Offset: 0x00000000 - Controls the operating mode of the CAN Controller
bogdanm 70:673126e12c73 1146 __IO uint32_t MOD;
bogdanm 70:673126e12c73 1147
bogdanm 70:673126e12c73 1148 ///Offset: 0x00000004 - Command bits that affect the state
bogdanm 70:673126e12c73 1149 __O uint32_t CMR;
bogdanm 70:673126e12c73 1150
bogdanm 70:673126e12c73 1151 ///Offset: 0x00000008 - Global Controller Status and Error Counters
bogdanm 70:673126e12c73 1152 __IO uint32_t GSR;
bogdanm 70:673126e12c73 1153
bogdanm 70:673126e12c73 1154 ///Offset: 0x0000000C - Interrupt status, Arbitration Lost Capture, Error Code Capture
bogdanm 70:673126e12c73 1155 __I uint32_t ICR;
bogdanm 70:673126e12c73 1156
bogdanm 70:673126e12c73 1157 ///Offset: 0x00000010 - Interrupt Enable Register
bogdanm 70:673126e12c73 1158 __IO uint32_t IER;
bogdanm 70:673126e12c73 1159
bogdanm 70:673126e12c73 1160 ///Offset: 0x00000014 - Bus Timing Register
bogdanm 70:673126e12c73 1161 __IO uint32_t BTR;
bogdanm 70:673126e12c73 1162
bogdanm 70:673126e12c73 1163 ///Offset: 0x00000018 - Error Warning Limit
bogdanm 70:673126e12c73 1164 __IO uint32_t EWL;
bogdanm 70:673126e12c73 1165
bogdanm 70:673126e12c73 1166 ///Offset: 0x0000001C - Status Register
bogdanm 70:673126e12c73 1167 __I uint32_t SR;
bogdanm 70:673126e12c73 1168
bogdanm 70:673126e12c73 1169 ///Offset: 0x00000020 - Receive frame status
bogdanm 70:673126e12c73 1170 __IO uint32_t RFS;
bogdanm 70:673126e12c73 1171
bogdanm 70:673126e12c73 1172 ///Offset: 0x00000024 - Received Identifier
bogdanm 70:673126e12c73 1173 __IO uint32_t RID;
bogdanm 70:673126e12c73 1174
bogdanm 70:673126e12c73 1175 ///Offset: 0x00000028 - Received data bytes 1-4
bogdanm 70:673126e12c73 1176 __IO uint32_t RDA;
bogdanm 70:673126e12c73 1177
bogdanm 70:673126e12c73 1178 ///Offset: 0x0000002C - Received data bytes 5-8
bogdanm 70:673126e12c73 1179 __IO uint32_t RDB;
bogdanm 70:673126e12c73 1180
bogdanm 70:673126e12c73 1181 ///Offset: 0x00000030 - Transmit frame info (Tx Buffer 1)
bogdanm 70:673126e12c73 1182 __IO uint32_t TFI1;
bogdanm 70:673126e12c73 1183
bogdanm 70:673126e12c73 1184 ///Offset: 0x00000034 - Transmit Identifier (Tx Buffer 1)
bogdanm 70:673126e12c73 1185 __IO uint32_t TID1;
bogdanm 70:673126e12c73 1186
bogdanm 70:673126e12c73 1187 ///Offset: 0x00000038 - Transmit data bytes 1-4 (Tx Buffer 1)
bogdanm 70:673126e12c73 1188 __IO uint32_t TDA1;
bogdanm 70:673126e12c73 1189
bogdanm 70:673126e12c73 1190 ///Offset: 0x0000003C - Transmit data bytes 5-8 (Tx Buffer 1)
bogdanm 70:673126e12c73 1191 __IO uint32_t TDB1;
bogdanm 70:673126e12c73 1192
bogdanm 70:673126e12c73 1193 ///Offset: 0x00000040 - Transmit frame info (Tx Buffer 2)
bogdanm 70:673126e12c73 1194 __IO uint32_t TFI2;
bogdanm 70:673126e12c73 1195
bogdanm 70:673126e12c73 1196 ///Offset: 0x00000044 - Transmit Identifier (Tx Buffer 2)
bogdanm 70:673126e12c73 1197 __IO uint32_t TID2;
bogdanm 70:673126e12c73 1198
bogdanm 70:673126e12c73 1199 ///Offset: 0x00000048 - Transmit data bytes 1-4 (Tx Buffer 2)
bogdanm 70:673126e12c73 1200 __IO uint32_t TDA2;
bogdanm 70:673126e12c73 1201
bogdanm 70:673126e12c73 1202 ///Offset: 0x0000004C - Transmit data bytes 5-8 (Tx Buffer 2)
bogdanm 70:673126e12c73 1203 __IO uint32_t TDB2;
bogdanm 70:673126e12c73 1204
bogdanm 70:673126e12c73 1205 ///Offset: 0x00000050 - Transmit frame info (Tx Buffer 3)
bogdanm 70:673126e12c73 1206 __IO uint32_t TFI3;
bogdanm 70:673126e12c73 1207
bogdanm 70:673126e12c73 1208 ///Offset: 0x00000054 - Transmit Identifier (Tx Buffer 3)
bogdanm 70:673126e12c73 1209 __IO uint32_t TID3;
bogdanm 70:673126e12c73 1210
bogdanm 70:673126e12c73 1211 ///Offset: 0x00000058 - Transmit data bytes 1-4 (Tx Buffer 3)
bogdanm 70:673126e12c73 1212 __IO uint32_t TDA3;
bogdanm 70:673126e12c73 1213
bogdanm 70:673126e12c73 1214 ///Offset: 0x0000005C - Transmit data bytes 5-8 (Tx Buffer 3)
bogdanm 70:673126e12c73 1215 __IO uint32_t TDB3;
bogdanm 70:673126e12c73 1216 } LPC_CAN_TypeDef;
bogdanm 70:673126e12c73 1217
bogdanm 70:673126e12c73 1218 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
bogdanm 70:673126e12c73 1219 typedef struct
bogdanm 70:673126e12c73 1220 {
bogdanm 70:673126e12c73 1221 __IO uint32_t CR;
bogdanm 70:673126e12c73 1222 __IO uint32_t CTRL;
bogdanm 70:673126e12c73 1223 __IO uint32_t CNTVAL;
bogdanm 70:673126e12c73 1224 } LPC_DAC_TypeDef;
bogdanm 70:673126e12c73 1225
bogdanm 70:673126e12c73 1226
bogdanm 70:673126e12c73 1227 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
bogdanm 70:673126e12c73 1228 typedef struct
bogdanm 70:673126e12c73 1229 {
bogdanm 70:673126e12c73 1230 __IO uint32_t DAO;
bogdanm 70:673126e12c73 1231 __IO uint32_t DAI;
bogdanm 70:673126e12c73 1232 __O uint32_t TXFIFO;
bogdanm 70:673126e12c73 1233 __I uint32_t RXFIFO;
bogdanm 70:673126e12c73 1234 __I uint32_t STATE;
bogdanm 70:673126e12c73 1235 __IO uint32_t DMA1;
bogdanm 70:673126e12c73 1236 __IO uint32_t DMA2;
bogdanm 70:673126e12c73 1237 __IO uint32_t IRQ;
bogdanm 70:673126e12c73 1238 __IO uint32_t TXRATE;
bogdanm 70:673126e12c73 1239 __IO uint32_t RXRATE;
bogdanm 70:673126e12c73 1240 __IO uint32_t TXBITRATE;
bogdanm 70:673126e12c73 1241 __IO uint32_t RXBITRATE;
bogdanm 70:673126e12c73 1242 __IO uint32_t TXMODE;
bogdanm 70:673126e12c73 1243 __IO uint32_t RXMODE;
bogdanm 70:673126e12c73 1244 } LPC_I2S_TypeDef;
bogdanm 70:673126e12c73 1245
bogdanm 70:673126e12c73 1246
bogdanm 70:673126e12c73 1247
bogdanm 70:673126e12c73 1248
bogdanm 70:673126e12c73 1249
bogdanm 70:673126e12c73 1250
bogdanm 70:673126e12c73 1251 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
bogdanm 70:673126e12c73 1252 typedef struct
bogdanm 70:673126e12c73 1253 {
bogdanm 70:673126e12c73 1254 __I uint32_t CON;
bogdanm 70:673126e12c73 1255 __O uint32_t CON_SET;
bogdanm 70:673126e12c73 1256 __O uint32_t CON_CLR;
bogdanm 70:673126e12c73 1257 __I uint32_t CAPCON;
bogdanm 70:673126e12c73 1258 __O uint32_t CAPCON_SET;
bogdanm 70:673126e12c73 1259 __O uint32_t CAPCON_CLR;
bogdanm 70:673126e12c73 1260 __IO uint32_t TC0;
bogdanm 70:673126e12c73 1261 __IO uint32_t TC1;
bogdanm 70:673126e12c73 1262 __IO uint32_t TC2;
bogdanm 70:673126e12c73 1263 __IO uint32_t LIM0;
bogdanm 70:673126e12c73 1264 __IO uint32_t LIM1;
bogdanm 70:673126e12c73 1265 __IO uint32_t LIM2;
bogdanm 70:673126e12c73 1266 __IO uint32_t MAT0;
bogdanm 70:673126e12c73 1267 __IO uint32_t MAT1;
bogdanm 70:673126e12c73 1268 __IO uint32_t MAT2;
bogdanm 70:673126e12c73 1269 __IO uint32_t DT;
bogdanm 70:673126e12c73 1270 __IO uint32_t CP;
bogdanm 70:673126e12c73 1271 __IO uint32_t CAP0;
bogdanm 70:673126e12c73 1272 __IO uint32_t CAP1;
bogdanm 70:673126e12c73 1273 __IO uint32_t CAP2;
bogdanm 70:673126e12c73 1274 __I uint32_t INTEN;
bogdanm 70:673126e12c73 1275 __O uint32_t INTEN_SET;
bogdanm 70:673126e12c73 1276 __O uint32_t INTEN_CLR;
bogdanm 70:673126e12c73 1277 __I uint32_t CNTCON;
bogdanm 70:673126e12c73 1278 __O uint32_t CNTCON_SET;
bogdanm 70:673126e12c73 1279 __O uint32_t CNTCON_CLR;
bogdanm 70:673126e12c73 1280 __I uint32_t INTF;
bogdanm 70:673126e12c73 1281 __O uint32_t INTF_SET;
bogdanm 70:673126e12c73 1282 __O uint32_t INTF_CLR;
bogdanm 70:673126e12c73 1283 __O uint32_t CAP_CLR;
bogdanm 70:673126e12c73 1284 } LPC_MCPWM_TypeDef;
bogdanm 70:673126e12c73 1285
bogdanm 70:673126e12c73 1286 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
bogdanm 70:673126e12c73 1287 typedef struct
bogdanm 70:673126e12c73 1288 {
bogdanm 70:673126e12c73 1289 __O uint32_t CON;
bogdanm 70:673126e12c73 1290 __I uint32_t STAT;
bogdanm 70:673126e12c73 1291 __IO uint32_t CONF;
bogdanm 70:673126e12c73 1292 __I uint32_t POS;
bogdanm 70:673126e12c73 1293 __IO uint32_t MAXPOS;
bogdanm 70:673126e12c73 1294 __IO uint32_t CMPOS0;
bogdanm 70:673126e12c73 1295 __IO uint32_t CMPOS1;
bogdanm 70:673126e12c73 1296 __IO uint32_t CMPOS2;
bogdanm 70:673126e12c73 1297 __I uint32_t INXCNT;
bogdanm 70:673126e12c73 1298 __IO uint32_t INXCMP0;
bogdanm 70:673126e12c73 1299 __IO uint32_t LOAD;
bogdanm 70:673126e12c73 1300 __I uint32_t TIME;
bogdanm 70:673126e12c73 1301 __I uint32_t VEL;
bogdanm 70:673126e12c73 1302 __I uint32_t CAP;
bogdanm 70:673126e12c73 1303 __IO uint32_t VELCOMP;
bogdanm 70:673126e12c73 1304 __IO uint32_t FILTERPHA;
bogdanm 70:673126e12c73 1305 __IO uint32_t FILTERPHB;
bogdanm 70:673126e12c73 1306 __IO uint32_t FILTERINX;
bogdanm 70:673126e12c73 1307 __IO uint32_t WINDOW;
bogdanm 70:673126e12c73 1308 __IO uint32_t INXCMP1;
bogdanm 70:673126e12c73 1309 __IO uint32_t INXCMP2;
bogdanm 70:673126e12c73 1310 uint32_t RESERVED0[993];
bogdanm 70:673126e12c73 1311 __O uint32_t IEC;
bogdanm 70:673126e12c73 1312 __O uint32_t IES;
bogdanm 70:673126e12c73 1313 __I uint32_t INTSTAT;
bogdanm 70:673126e12c73 1314 __I uint32_t IE;
bogdanm 70:673126e12c73 1315 __O uint32_t CLR;
bogdanm 70:673126e12c73 1316 __O uint32_t SET;
bogdanm 70:673126e12c73 1317 } LPC_QEI_TypeDef;
bogdanm 70:673126e12c73 1318
bogdanm 70:673126e12c73 1319 /*------------- SD/MMC card Interface (MCI)-----------------------------------*/
bogdanm 70:673126e12c73 1320 typedef struct
bogdanm 70:673126e12c73 1321 {
bogdanm 70:673126e12c73 1322 __IO uint32_t POWER;
bogdanm 70:673126e12c73 1323 __IO uint32_t CLOCK;
bogdanm 70:673126e12c73 1324 __IO uint32_t ARGUMENT;
bogdanm 70:673126e12c73 1325 __IO uint32_t COMMAND;
bogdanm 70:673126e12c73 1326 __I uint32_t RESP_CMD;
bogdanm 70:673126e12c73 1327 __I uint32_t RESP0;
bogdanm 70:673126e12c73 1328 __I uint32_t RESP1;
bogdanm 70:673126e12c73 1329 __I uint32_t RESP2;
bogdanm 70:673126e12c73 1330 __I uint32_t RESP3;
bogdanm 70:673126e12c73 1331 __IO uint32_t DATATMR;
bogdanm 70:673126e12c73 1332 __IO uint32_t DATALEN;
bogdanm 70:673126e12c73 1333 __IO uint32_t DATACTRL;
bogdanm 70:673126e12c73 1334 __I uint32_t DATACNT;
bogdanm 70:673126e12c73 1335 __I uint32_t STATUS;
bogdanm 70:673126e12c73 1336 __O uint32_t CLEAR;
bogdanm 70:673126e12c73 1337 __IO uint32_t MASK0;
bogdanm 70:673126e12c73 1338 uint32_t RESERVED0[2];
bogdanm 70:673126e12c73 1339 __I uint32_t FIFOCNT;
bogdanm 70:673126e12c73 1340 uint32_t RESERVED1[13];
bogdanm 70:673126e12c73 1341 __IO uint32_t FIFO[16];
bogdanm 70:673126e12c73 1342 } LPC_MCI_TypeDef;
bogdanm 70:673126e12c73 1343
bogdanm 70:673126e12c73 1344
bogdanm 70:673126e12c73 1345
bogdanm 70:673126e12c73 1346
bogdanm 70:673126e12c73 1347
bogdanm 70:673126e12c73 1348
bogdanm 70:673126e12c73 1349
bogdanm 70:673126e12c73 1350
bogdanm 70:673126e12c73 1351
bogdanm 70:673126e12c73 1352
bogdanm 70:673126e12c73 1353 /*------------- EEPROM Controller (EEPROM) -----------------------------------*/
bogdanm 70:673126e12c73 1354 typedef struct
bogdanm 70:673126e12c73 1355 {
bogdanm 70:673126e12c73 1356 __IO uint32_t CMD; /* 0x0080 */
bogdanm 70:673126e12c73 1357 __IO uint32_t ADDR;
bogdanm 70:673126e12c73 1358 __IO uint32_t WDATA;
bogdanm 70:673126e12c73 1359 __IO uint32_t RDATA;
bogdanm 70:673126e12c73 1360 __IO uint32_t WSTATE; /* 0x0090 */
bogdanm 70:673126e12c73 1361 __IO uint32_t CLKDIV;
bogdanm 70:673126e12c73 1362 __IO uint32_t PWRDWN; /* 0x0098 */
bogdanm 70:673126e12c73 1363 uint32_t RESERVED0[975];
bogdanm 70:673126e12c73 1364 __IO uint32_t INT_CLR_ENABLE; /* 0x0FD8 */
bogdanm 70:673126e12c73 1365 __IO uint32_t INT_SET_ENABLE;
bogdanm 70:673126e12c73 1366 __IO uint32_t INT_STATUS; /* 0x0FE0 */
bogdanm 70:673126e12c73 1367 __IO uint32_t INT_ENABLE;
bogdanm 70:673126e12c73 1368 __IO uint32_t INT_CLR_STATUS;
bogdanm 70:673126e12c73 1369 __IO uint32_t INT_SET_STATUS;
bogdanm 70:673126e12c73 1370 } LPC_EEPROM_TypeDef;
bogdanm 70:673126e12c73 1371
bogdanm 70:673126e12c73 1372
bogdanm 70:673126e12c73 1373 /*------------- COMPARATOR ----------------------------------------------------*/
bogdanm 70:673126e12c73 1374
bogdanm 70:673126e12c73 1375 typedef struct { /*!< (@ 0x40020000) COMPARATOR Structure */
bogdanm 70:673126e12c73 1376 __IO uint32_t CTRL; /*!< (@ 0x40020000) Comparator block control register */
bogdanm 70:673126e12c73 1377 __IO uint32_t CTRL0; /*!< (@ 0x40020004) Comparator 0 control register */
bogdanm 70:673126e12c73 1378 __IO uint32_t CTRL1; /*!< (@ 0x40020008) Comparator 1 control register */
bogdanm 70:673126e12c73 1379 } LPC_COMPARATOR_Type;
bogdanm 70:673126e12c73 1380
bogdanm 70:673126e12c73 1381
bogdanm 70:673126e12c73 1382 #if defined ( __CC_ARM )
bogdanm 70:673126e12c73 1383 #pragma no_anon_unions
bogdanm 70:673126e12c73 1384 #endif
bogdanm 70:673126e12c73 1385
bogdanm 70:673126e12c73 1386 /******************************************************************************/
bogdanm 70:673126e12c73 1387 /* Peripheral memory map */
bogdanm 70:673126e12c73 1388 /******************************************************************************/
bogdanm 70:673126e12c73 1389 /* Base addresses */
bogdanm 70:673126e12c73 1390 #define LPC_FLASH_BASE (0x00000000UL)
bogdanm 70:673126e12c73 1391 #define LPC_RAM_BASE (0x10000000UL)
bogdanm 70:673126e12c73 1392 #define LPC_PERI_RAM_BASE (0x20000000UL)
bogdanm 70:673126e12c73 1393 #define LPC_APB0_BASE (0x40000000UL)
bogdanm 70:673126e12c73 1394 #define LPC_APB1_BASE (0x40080000UL)
bogdanm 70:673126e12c73 1395 #define LPC_AHBRAM1_BASE (0x20004000UL)
bogdanm 70:673126e12c73 1396 #define LPC_AHB_BASE (0x20080000UL)
bogdanm 70:673126e12c73 1397 #define LPC_CM3_BASE (0xE0000000UL)
bogdanm 70:673126e12c73 1398
bogdanm 70:673126e12c73 1399 /* APB0 peripherals */
bogdanm 70:673126e12c73 1400 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
bogdanm 70:673126e12c73 1401 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
bogdanm 70:673126e12c73 1402 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
bogdanm 70:673126e12c73 1403 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
bogdanm 70:673126e12c73 1404 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
bogdanm 70:673126e12c73 1405 #define LPC_PWM0_BASE (LPC_APB0_BASE + 0x14000)
bogdanm 70:673126e12c73 1406 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
bogdanm 70:673126e12c73 1407 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
bogdanm 70:673126e12c73 1408 #define LPC_COMPARATOR_BASE (LPC_APB0_BASE + 0x20000)
bogdanm 70:673126e12c73 1409 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
bogdanm 70:673126e12c73 1410 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
bogdanm 70:673126e12c73 1411 #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x2C000)
bogdanm 70:673126e12c73 1412 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
bogdanm 70:673126e12c73 1413 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
bogdanm 70:673126e12c73 1414 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
bogdanm 70:673126e12c73 1415 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
bogdanm 70:673126e12c73 1416 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
bogdanm 70:673126e12c73 1417 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
bogdanm 70:673126e12c73 1418 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
bogdanm 70:673126e12c73 1419 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
bogdanm 70:673126e12c73 1420
bogdanm 70:673126e12c73 1421 /* APB1 peripherals */
bogdanm 70:673126e12c73 1422 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
bogdanm 70:673126e12c73 1423 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
bogdanm 70:673126e12c73 1424 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
bogdanm 70:673126e12c73 1425 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
bogdanm 70:673126e12c73 1426 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
bogdanm 70:673126e12c73 1427 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
bogdanm 70:673126e12c73 1428 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
bogdanm 70:673126e12c73 1429 #define LPC_UART4_BASE (LPC_APB1_BASE + 0x24000)
bogdanm 70:673126e12c73 1430 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
bogdanm 70:673126e12c73 1431 #define LPC_SSP2_BASE (LPC_APB1_BASE + 0x2C000)
bogdanm 70:673126e12c73 1432 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
bogdanm 70:673126e12c73 1433 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
bogdanm 70:673126e12c73 1434 #define LPC_MCI_BASE (LPC_APB1_BASE + 0x40000)
bogdanm 70:673126e12c73 1435 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
bogdanm 70:673126e12c73 1436
bogdanm 70:673126e12c73 1437 /* AHB peripherals */
bogdanm 70:673126e12c73 1438 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x00000)
bogdanm 70:673126e12c73 1439 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x00100)
bogdanm 70:673126e12c73 1440 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x00120)
bogdanm 70:673126e12c73 1441 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x00140)
bogdanm 70:673126e12c73 1442 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x00160)
bogdanm 70:673126e12c73 1443 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x00180)
bogdanm 70:673126e12c73 1444 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x001A0)
bogdanm 70:673126e12c73 1445 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x001C0)
bogdanm 70:673126e12c73 1446 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x001E0)
bogdanm 70:673126e12c73 1447 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x04000)
bogdanm 70:673126e12c73 1448 #define LPC_LCD_BASE (LPC_AHB_BASE + 0x08000)
bogdanm 70:673126e12c73 1449 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
bogdanm 70:673126e12c73 1450 #define LPC_CRC_BASE (LPC_AHB_BASE + 0x10000)
bogdanm 70:673126e12c73 1451 #define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x18000)
bogdanm 70:673126e12c73 1452 #define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x18020)
bogdanm 70:673126e12c73 1453 #define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x18040)
bogdanm 70:673126e12c73 1454 #define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x18060)
bogdanm 70:673126e12c73 1455 #define LPC_GPIO4_BASE (LPC_AHB_BASE + 0x18080)
bogdanm 70:673126e12c73 1456 #define LPC_GPIO5_BASE (LPC_AHB_BASE + 0x180A0)
bogdanm 70:673126e12c73 1457 #define LPC_EMC_BASE (LPC_AHB_BASE + 0x1C000)
bogdanm 70:673126e12c73 1458
bogdanm 70:673126e12c73 1459 #define LPC_EEPROM_BASE (LPC_FLASH_BASE+ 0x200080)
bogdanm 70:673126e12c73 1460
bogdanm 70:673126e12c73 1461
bogdanm 70:673126e12c73 1462 /******************************************************************************/
bogdanm 70:673126e12c73 1463 /* Peripheral declaration */
bogdanm 70:673126e12c73 1464 /******************************************************************************/
bogdanm 70:673126e12c73 1465 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
bogdanm 70:673126e12c73 1466 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
bogdanm 70:673126e12c73 1467 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
bogdanm 70:673126e12c73 1468 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
bogdanm 70:673126e12c73 1469 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
bogdanm 70:673126e12c73 1470 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
bogdanm 70:673126e12c73 1471 #define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE )
bogdanm 70:673126e12c73 1472 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
bogdanm 70:673126e12c73 1473 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
bogdanm 70:673126e12c73 1474 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
bogdanm 70:673126e12c73 1475 #define LPC_UART4 ((LPC_UART4_TypeDef *) LPC_UART4_BASE )
bogdanm 70:673126e12c73 1476 #define LPC_PWM0 ((LPC_PWM_TypeDef *) LPC_PWM0_BASE )
bogdanm 70:673126e12c73 1477 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
bogdanm 70:673126e12c73 1478 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
bogdanm 70:673126e12c73 1479 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
bogdanm 70:673126e12c73 1480 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
bogdanm 70:673126e12c73 1481 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
bogdanm 70:673126e12c73 1482 #define LPC_COMPARATOR ((LPC_COMPARATOR_Type *) LPC_COMPARATOR_BASE)
bogdanm 70:673126e12c73 1483 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
bogdanm 70:673126e12c73 1484 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
bogdanm 70:673126e12c73 1485 #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
bogdanm 70:673126e12c73 1486 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
bogdanm 70:673126e12c73 1487 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
bogdanm 70:673126e12c73 1488 #define LPC_SSP2 ((LPC_SSP_TypeDef *) LPC_SSP2_BASE )
bogdanm 70:673126e12c73 1489 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
bogdanm 70:673126e12c73 1490 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
bogdanm 70:673126e12c73 1491 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
bogdanm 70:673126e12c73 1492 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
bogdanm 70:673126e12c73 1493 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
bogdanm 70:673126e12c73 1494 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
bogdanm 70:673126e12c73 1495 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
bogdanm 70:673126e12c73 1496 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
bogdanm 70:673126e12c73 1497 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
bogdanm 70:673126e12c73 1498 #define LPC_MCI ((LPC_MCI_TypeDef *) LPC_MCI_BASE )
bogdanm 70:673126e12c73 1499 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
bogdanm 70:673126e12c73 1500 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
bogdanm 70:673126e12c73 1501 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
bogdanm 70:673126e12c73 1502 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
bogdanm 70:673126e12c73 1503 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
bogdanm 70:673126e12c73 1504 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
bogdanm 70:673126e12c73 1505 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
bogdanm 70:673126e12c73 1506 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
bogdanm 70:673126e12c73 1507 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
bogdanm 70:673126e12c73 1508 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
bogdanm 70:673126e12c73 1509 #define LPC_LCD ((LPC_LCD_TypeDef *) LPC_LCD_BASE )
bogdanm 70:673126e12c73 1510 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
bogdanm 70:673126e12c73 1511 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
bogdanm 70:673126e12c73 1512 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
bogdanm 70:673126e12c73 1513 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
bogdanm 70:673126e12c73 1514 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
bogdanm 70:673126e12c73 1515 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
bogdanm 70:673126e12c73 1516 #define LPC_GPIO5 ((LPC_GPIO_TypeDef *) LPC_GPIO5_BASE )
bogdanm 70:673126e12c73 1517 #define LPC_EMC ((LPC_EMC_TypeDef *) LPC_EMC_BASE )
bogdanm 70:673126e12c73 1518 #define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
bogdanm 70:673126e12c73 1519 #define LPC_EEPROM ((LPC_EEPROM_TypeDef *) LPC_EEPROM_BASE )
bogdanm 70:673126e12c73 1520
bogdanm 70:673126e12c73 1521
bogdanm 70:673126e12c73 1522
bogdanm 70:673126e12c73 1523 #endif // __LPC407x_8x_177x_8x_H__