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TARGET_LPC2368/vector_defns.h@71:7ec3cb6bbcc4, 2013-11-29 (annotated)

Committer:
jalp89
Date:
Fri Nov 29 09:39:46 2013 +0000
Revision:
71:7ec3cb6bbcc4
Parent:
66:9c8f0e3462fb 
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Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 66:9c8f0e3462fb 1 /* mbed Microcontroller Library - Vectors
bogdanm 66:9c8f0e3462fb 2 * Copyright (c) 2006-2009 ARM Limited. All rights reserved.
bogdanm 66:9c8f0e3462fb 3 */
bogdanm 66:9c8f0e3462fb 4
bogdanm 66:9c8f0e3462fb 5 #ifndef MBED_VECTOR_DEFNS_H
bogdanm 66:9c8f0e3462fb 6 #define MBED_VECTOR_DEFNS_H
bogdanm 66:9c8f0e3462fb 7
bogdanm 66:9c8f0e3462fb 8 // Assember Macros
bogdanm 66:9c8f0e3462fb 9 #ifdef __ARMCC_VERSION
bogdanm 66:9c8f0e3462fb 10 #define EXPORT(x) EXPORT x
bogdanm 66:9c8f0e3462fb 11 #define WEAK_EXPORT(x) EXPORT x [WEAK]
bogdanm 66:9c8f0e3462fb 12 #define IMPORT(x) IMPORT x
bogdanm 66:9c8f0e3462fb 13 #define LABEL(x) x
bogdanm 66:9c8f0e3462fb 14 #else
bogdanm 66:9c8f0e3462fb 15 #define EXPORT(x) .global x
bogdanm 66:9c8f0e3462fb 16 #define WEAK_EXPORT(x) .weak x
bogdanm 66:9c8f0e3462fb 17 #define IMPORT(x) .global x
bogdanm 66:9c8f0e3462fb 18 #define LABEL(x) x:
bogdanm 66:9c8f0e3462fb 19 #endif
bogdanm 66:9c8f0e3462fb 20
bogdanm 66:9c8f0e3462fb 21 // RealMonitor
bogdanm 66:9c8f0e3462fb 22 // Requires RAM (0x40000040-0x4000011F) to be allocated by the linker
bogdanm 66:9c8f0e3462fb 23
bogdanm 66:9c8f0e3462fb 24 // RealMonitor entry points
bogdanm 66:9c8f0e3462fb 25 #define rm_init_entry 0x7fffff91
bogdanm 66:9c8f0e3462fb 26 #define rm_undef_handler 0x7fffffa0
bogdanm 66:9c8f0e3462fb 27 #define rm_prefetchabort_handler 0x7fffffb0
bogdanm 66:9c8f0e3462fb 28 #define rm_dataabort_handler 0x7fffffc0
bogdanm 66:9c8f0e3462fb 29 #define rm_irqhandler2 0x7fffffe0
bogdanm 66:9c8f0e3462fb 30 //#define rm_RunningToStopped 0x7ffff808 // ARM - MBED64
bogdanm 66:9c8f0e3462fb 31 #define rm_RunningToStopped 0x7ffff820 // ARM - PHAT40
bogdanm 66:9c8f0e3462fb 32
bogdanm 66:9c8f0e3462fb 33 // Unofficial RealMonitor entry points and variables
bogdanm 66:9c8f0e3462fb 34 #define RM_MSG_SWI 0x00940000
bogdanm 66:9c8f0e3462fb 35 #define StateP 0x40000040
bogdanm 66:9c8f0e3462fb 36
bogdanm 66:9c8f0e3462fb 37 // VIC register addresses
bogdanm 66:9c8f0e3462fb 38 #define VIC_Base 0xfffff000
bogdanm 66:9c8f0e3462fb 39 #define VICAddress_Offset 0xf00
bogdanm 66:9c8f0e3462fb 40 #define VICVectAddr0_Offset 0x100
bogdanm 66:9c8f0e3462fb 41 #define VICVectAddr2_Offset 0x108
bogdanm 66:9c8f0e3462fb 42 #define VICVectAddr3_Offset 0x10c
bogdanm 66:9c8f0e3462fb 43 #define VICVectAddr31_Offset 0x17c
bogdanm 66:9c8f0e3462fb 44 #define VICIntEnClr_Offset 0x014
bogdanm 66:9c8f0e3462fb 45 #define VICIntEnClr (*(volatile unsigned long *)(VIC_Base + 0x014))
bogdanm 66:9c8f0e3462fb 46 #define VICVectAddr2 (*(volatile unsigned long *)(VIC_Base + 0x108))
bogdanm 66:9c8f0e3462fb 47 #define VICVectAddr3 (*(volatile unsigned long *)(VIC_Base + 0x10C))
bogdanm 66:9c8f0e3462fb 48
bogdanm 66:9c8f0e3462fb 49 // ARM Mode bits and Interrupt flags in PSRs
bogdanm 66:9c8f0e3462fb 50 #define Mode_USR 0x10
bogdanm 66:9c8f0e3462fb 51 #define Mode_FIQ 0x11
bogdanm 66:9c8f0e3462fb 52 #define Mode_IRQ 0x12
bogdanm 66:9c8f0e3462fb 53 #define Mode_SVC 0x13
bogdanm 66:9c8f0e3462fb 54 #define Mode_ABT 0x17
bogdanm 66:9c8f0e3462fb 55 #define Mode_UND 0x1B
bogdanm 66:9c8f0e3462fb 56 #define Mode_SYS 0x1F
bogdanm 66:9c8f0e3462fb 57 #define I_Bit 0x80 // when I bit is set, IRQ is disabled
bogdanm 66:9c8f0e3462fb 58 #define F_Bit 0x40 // when F bit is set, FIQ is disabled
bogdanm 66:9c8f0e3462fb 59
bogdanm 66:9c8f0e3462fb 60 // MCU RAM
bogdanm 66:9c8f0e3462fb 61 #define LPC2368_RAM_ADDRESS 0x40000000 // RAM Base
bogdanm 66:9c8f0e3462fb 62 #define LPC2368_RAM_SIZE 0x8000 // 32KB
bogdanm 66:9c8f0e3462fb 63
bogdanm 66:9c8f0e3462fb 64 // ISR Stack Allocation
bogdanm 66:9c8f0e3462fb 65 #define UND_stack_size 0x00000040
bogdanm 66:9c8f0e3462fb 66 #define SVC_stack_size 0x00000040
bogdanm 66:9c8f0e3462fb 67 #define ABT_stack_size 0x00000040
bogdanm 66:9c8f0e3462fb 68 #define FIQ_stack_size 0x00000000
bogdanm 66:9c8f0e3462fb 69 #define IRQ_stack_size 0x00000040
bogdanm 66:9c8f0e3462fb 70
bogdanm 66:9c8f0e3462fb 71 #define ISR_stack_size (UND_stack_size + SVC_stack_size + ABT_stack_size + FIQ_stack_size + IRQ_stack_size)
bogdanm 66:9c8f0e3462fb 72
bogdanm 66:9c8f0e3462fb 73 // Full Descending Stack, so top-most stack points to just above the top of RAM
bogdanm 66:9c8f0e3462fb 74 #define LPC2368_STACK_TOP (LPC2368_RAM_ADDRESS + LPC2368_RAM_SIZE)
bogdanm 66:9c8f0e3462fb 75 #define USR_STACK_TOP (LPC2368_STACK_TOP - ISR_stack_size)
bogdanm 66:9c8f0e3462fb 76
bogdanm 66:9c8f0e3462fb 77 #endif