Diff: targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.c

Revision:

610:813dcc80987e

Parent:

573:ad23fe03a082

--- a/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.c	Fri Aug 14 12:45:09 2015 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.c	Fri Aug 14 13:15:17 2015 +0100
@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f7xx_hal_rcc.c
   * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    12-May-2015
+  * @version V1.0.1
+  * @date    25-June-2015
   * @brief   RCC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Reset and Clock Control (RCC) peripheral:
@@ -48,8 +48,8 @@
           after the clock enable bit is set on the hardware register
 
     [..]  
-      Workarounds:
-	  (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+      Implemented Workaround:
+      (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
           inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
 
   @endverbatim