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targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_rcc_ex.h@637:ed69428d4850, 2015-12-22 (annotated)
- Committer:
- jaerts
- Date:
- Tue Dec 22 13:22:16 2015 +0000
- Revision:
- 637:ed69428d4850
- Parent:
- 610:813dcc80987e
Add very shady LPC1768 CAN Filter implementation
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 610:813dcc80987e | 1 | /** |
mbed_official | 610:813dcc80987e | 2 | ****************************************************************************** |
mbed_official | 610:813dcc80987e | 3 | * @file stm32l4xx_hal_rcc_ex.h |
mbed_official | 610:813dcc80987e | 4 | * @author MCD Application Team |
mbed_official | 610:813dcc80987e | 5 | * @version V1.0.0 |
mbed_official | 610:813dcc80987e | 6 | * @date 26-June-2015 |
mbed_official | 610:813dcc80987e | 7 | * @brief Header file of RCC HAL Extended module. |
mbed_official | 610:813dcc80987e | 8 | ****************************************************************************** |
mbed_official | 610:813dcc80987e | 9 | * @attention |
mbed_official | 610:813dcc80987e | 10 | * |
mbed_official | 610:813dcc80987e | 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
mbed_official | 610:813dcc80987e | 12 | * |
mbed_official | 610:813dcc80987e | 13 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 610:813dcc80987e | 14 | * are permitted provided that the following conditions are met: |
mbed_official | 610:813dcc80987e | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 610:813dcc80987e | 16 | * this list of conditions and the following disclaimer. |
mbed_official | 610:813dcc80987e | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 610:813dcc80987e | 18 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 610:813dcc80987e | 19 | * and/or other materials provided with the distribution. |
mbed_official | 610:813dcc80987e | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 610:813dcc80987e | 21 | * may be used to endorse or promote products derived from this software |
mbed_official | 610:813dcc80987e | 22 | * without specific prior written permission. |
mbed_official | 610:813dcc80987e | 23 | * |
mbed_official | 610:813dcc80987e | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 610:813dcc80987e | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 610:813dcc80987e | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 610:813dcc80987e | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 610:813dcc80987e | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 610:813dcc80987e | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 610:813dcc80987e | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 610:813dcc80987e | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 610:813dcc80987e | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 610:813dcc80987e | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 610:813dcc80987e | 34 | * |
mbed_official | 610:813dcc80987e | 35 | ****************************************************************************** |
mbed_official | 610:813dcc80987e | 36 | */ |
mbed_official | 610:813dcc80987e | 37 | |
mbed_official | 610:813dcc80987e | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
mbed_official | 610:813dcc80987e | 39 | #ifndef __STM32L4xx_HAL_RCC_EX_H |
mbed_official | 610:813dcc80987e | 40 | #define __STM32L4xx_HAL_RCC_EX_H |
mbed_official | 610:813dcc80987e | 41 | |
mbed_official | 610:813dcc80987e | 42 | #ifdef __cplusplus |
mbed_official | 610:813dcc80987e | 43 | extern "C" { |
mbed_official | 610:813dcc80987e | 44 | #endif |
mbed_official | 610:813dcc80987e | 45 | |
mbed_official | 610:813dcc80987e | 46 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 610:813dcc80987e | 47 | #include "stm32l4xx_hal_def.h" |
mbed_official | 610:813dcc80987e | 48 | |
mbed_official | 610:813dcc80987e | 49 | /** @addtogroup STM32L4xx_HAL_Driver |
mbed_official | 610:813dcc80987e | 50 | * @{ |
mbed_official | 610:813dcc80987e | 51 | */ |
mbed_official | 610:813dcc80987e | 52 | |
mbed_official | 610:813dcc80987e | 53 | /** @addtogroup RCCEx |
mbed_official | 610:813dcc80987e | 54 | * @{ |
mbed_official | 610:813dcc80987e | 55 | */ |
mbed_official | 610:813dcc80987e | 56 | |
mbed_official | 610:813dcc80987e | 57 | /* Exported types ------------------------------------------------------------*/ |
mbed_official | 610:813dcc80987e | 58 | |
mbed_official | 610:813dcc80987e | 59 | /** @defgroup RCCEx_Exported_Types RCCEx Exported Types |
mbed_official | 610:813dcc80987e | 60 | * @{ |
mbed_official | 610:813dcc80987e | 61 | */ |
mbed_official | 610:813dcc80987e | 62 | |
mbed_official | 610:813dcc80987e | 63 | /** |
mbed_official | 610:813dcc80987e | 64 | * @brief PLLSAI1 Clock structure definition |
mbed_official | 610:813dcc80987e | 65 | */ |
mbed_official | 610:813dcc80987e | 66 | typedef struct |
mbed_official | 610:813dcc80987e | 67 | { |
mbed_official | 610:813dcc80987e | 68 | |
mbed_official | 610:813dcc80987e | 69 | uint32_t PLLSAI1N; /*!< PLLSAI1N: specifies the multiplication factor for PLLSAI1 VCO output clock. |
mbed_official | 610:813dcc80987e | 70 | This parameter must be a number between 8 and 86. */ |
mbed_official | 610:813dcc80987e | 71 | |
mbed_official | 610:813dcc80987e | 72 | uint32_t PLLSAI1P; /*!< PLLSAI1P: specifies the division factor for SAI clock. |
mbed_official | 610:813dcc80987e | 73 | This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ |
mbed_official | 610:813dcc80987e | 74 | |
mbed_official | 610:813dcc80987e | 75 | uint32_t PLLSAI1Q; /*!< PLLSAI1Q: specifies the division factor for USB/RNG/SDMMC1 clock. |
mbed_official | 610:813dcc80987e | 76 | This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */ |
mbed_official | 610:813dcc80987e | 77 | |
mbed_official | 610:813dcc80987e | 78 | uint32_t PLLSAI1R; /*!< PLLSAI1R: specifies the division factor for ADC clock. |
mbed_official | 610:813dcc80987e | 79 | This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ |
mbed_official | 610:813dcc80987e | 80 | |
mbed_official | 610:813dcc80987e | 81 | uint32_t PLLSAI1ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI1 output clock to be enabled. |
mbed_official | 610:813dcc80987e | 82 | This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */ |
mbed_official | 610:813dcc80987e | 83 | }RCC_PLLSAI1InitTypeDef; |
mbed_official | 610:813dcc80987e | 84 | |
mbed_official | 610:813dcc80987e | 85 | /** |
mbed_official | 610:813dcc80987e | 86 | * @brief PLLSAI2 Clock structure definition |
mbed_official | 610:813dcc80987e | 87 | */ |
mbed_official | 610:813dcc80987e | 88 | typedef struct |
mbed_official | 610:813dcc80987e | 89 | { |
mbed_official | 610:813dcc80987e | 90 | |
mbed_official | 610:813dcc80987e | 91 | uint32_t PLLSAI2N; /*!< PLLSAI2N: specifies the multiplication factor for PLLSAI2 VCO output clock. |
mbed_official | 610:813dcc80987e | 92 | This parameter must be a number between 8 and 86. */ |
mbed_official | 610:813dcc80987e | 93 | |
mbed_official | 610:813dcc80987e | 94 | uint32_t PLLSAI2P; /*!< PLLSAI2P: specifies the division factor for SAI clock. |
mbed_official | 610:813dcc80987e | 95 | This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ |
mbed_official | 610:813dcc80987e | 96 | |
mbed_official | 610:813dcc80987e | 97 | uint32_t PLLSAI2R; /*!< PLLSAI2R: specifies the division factor for ADC clock. |
mbed_official | 610:813dcc80987e | 98 | This parameter must be a value of @ref RCC_PLLR_Clock_Divider */ |
mbed_official | 610:813dcc80987e | 99 | |
mbed_official | 610:813dcc80987e | 100 | uint32_t PLLSAI2ClockOut; /*!< PLLSAIClockOut: specifies PLLSAI2 output clock to be enabled. |
mbed_official | 610:813dcc80987e | 101 | This parameter must be a value of @ref RCC_PLLSAI2_Clock_Output */ |
mbed_official | 610:813dcc80987e | 102 | }RCC_PLLSAI2InitTypeDef; |
mbed_official | 610:813dcc80987e | 103 | |
mbed_official | 610:813dcc80987e | 104 | /** |
mbed_official | 610:813dcc80987e | 105 | * @brief RCC extended clocks structure definition |
mbed_official | 610:813dcc80987e | 106 | */ |
mbed_official | 610:813dcc80987e | 107 | typedef struct |
mbed_official | 610:813dcc80987e | 108 | { |
mbed_official | 610:813dcc80987e | 109 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
mbed_official | 610:813dcc80987e | 110 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
mbed_official | 610:813dcc80987e | 111 | |
mbed_official | 610:813dcc80987e | 112 | RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters. |
mbed_official | 610:813dcc80987e | 113 | This parameter will be used only when PLLSAI1 is selected as Clock Source for SAI1, USB/RNG/SDMMC1 or ADC */ |
mbed_official | 610:813dcc80987e | 114 | |
mbed_official | 610:813dcc80987e | 115 | RCC_PLLSAI2InitTypeDef PLLSAI2; /*!< PLLSAI2 structure parameters. |
mbed_official | 610:813dcc80987e | 116 | This parameter will be used only when PLLSAI2 is selected as Clock Source for SAI2 or ADC */ |
mbed_official | 610:813dcc80987e | 117 | |
mbed_official | 610:813dcc80987e | 118 | uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. |
mbed_official | 610:813dcc80987e | 119 | This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ |
mbed_official | 610:813dcc80987e | 120 | |
mbed_official | 610:813dcc80987e | 121 | uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. |
mbed_official | 610:813dcc80987e | 122 | This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ |
mbed_official | 610:813dcc80987e | 123 | |
mbed_official | 610:813dcc80987e | 124 | uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. |
mbed_official | 610:813dcc80987e | 125 | This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ |
mbed_official | 610:813dcc80987e | 126 | |
mbed_official | 610:813dcc80987e | 127 | uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. |
mbed_official | 610:813dcc80987e | 128 | This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ |
mbed_official | 610:813dcc80987e | 129 | |
mbed_official | 610:813dcc80987e | 130 | uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. |
mbed_official | 610:813dcc80987e | 131 | This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ |
mbed_official | 610:813dcc80987e | 132 | |
mbed_official | 610:813dcc80987e | 133 | uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. |
mbed_official | 610:813dcc80987e | 134 | This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ |
mbed_official | 610:813dcc80987e | 135 | |
mbed_official | 610:813dcc80987e | 136 | uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. |
mbed_official | 610:813dcc80987e | 137 | This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ |
mbed_official | 610:813dcc80987e | 138 | |
mbed_official | 610:813dcc80987e | 139 | uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. |
mbed_official | 610:813dcc80987e | 140 | This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ |
mbed_official | 610:813dcc80987e | 141 | |
mbed_official | 610:813dcc80987e | 142 | uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. |
mbed_official | 610:813dcc80987e | 143 | This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ |
mbed_official | 610:813dcc80987e | 144 | |
mbed_official | 610:813dcc80987e | 145 | uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. |
mbed_official | 610:813dcc80987e | 146 | This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ |
mbed_official | 610:813dcc80987e | 147 | |
mbed_official | 610:813dcc80987e | 148 | uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. |
mbed_official | 610:813dcc80987e | 149 | This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ |
mbed_official | 610:813dcc80987e | 150 | |
mbed_official | 610:813dcc80987e | 151 | uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. |
mbed_official | 610:813dcc80987e | 152 | This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ |
mbed_official | 610:813dcc80987e | 153 | |
mbed_official | 610:813dcc80987e | 154 | uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source. |
mbed_official | 610:813dcc80987e | 155 | This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ |
mbed_official | 610:813dcc80987e | 156 | |
mbed_official | 610:813dcc80987e | 157 | #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) |
mbed_official | 610:813dcc80987e | 158 | |
mbed_official | 610:813dcc80987e | 159 | uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for SDMMC1 and RNG). |
mbed_official | 610:813dcc80987e | 160 | This parameter can be a value of @ref RCCEx_USB_Clock_Source */ |
mbed_official | 610:813dcc80987e | 161 | |
mbed_official | 610:813dcc80987e | 162 | #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
mbed_official | 610:813dcc80987e | 163 | |
mbed_official | 610:813dcc80987e | 164 | uint32_t Sdmmc1ClockSelection; /*!< Specifies SDMMC1 clock source (warning: same source for USB and RNG). |
mbed_official | 610:813dcc80987e | 165 | This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ |
mbed_official | 610:813dcc80987e | 166 | |
mbed_official | 610:813dcc80987e | 167 | uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB and SDMMC1). |
mbed_official | 610:813dcc80987e | 168 | This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ |
mbed_official | 610:813dcc80987e | 169 | |
mbed_official | 610:813dcc80987e | 170 | uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source. |
mbed_official | 610:813dcc80987e | 171 | This parameter can be a value of @ref RCCEx_ADC_Clock_Source */ |
mbed_official | 610:813dcc80987e | 172 | |
mbed_official | 610:813dcc80987e | 173 | uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 clock source. |
mbed_official | 610:813dcc80987e | 174 | This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */ |
mbed_official | 610:813dcc80987e | 175 | |
mbed_official | 610:813dcc80987e | 176 | uint32_t DfsdmClockSelection; /*!< Specifies DFSDM clock source. |
mbed_official | 610:813dcc80987e | 177 | This parameter can be a value of @ref RCCEx_DFSDM_Clock_Source */ |
mbed_official | 610:813dcc80987e | 178 | |
mbed_official | 610:813dcc80987e | 179 | uint32_t RTCClockSelection; /*!< Specifies RTC clock source. |
mbed_official | 610:813dcc80987e | 180 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
mbed_official | 610:813dcc80987e | 181 | }RCC_PeriphCLKInitTypeDef; |
mbed_official | 610:813dcc80987e | 182 | |
mbed_official | 610:813dcc80987e | 183 | /** |
mbed_official | 610:813dcc80987e | 184 | * @} |
mbed_official | 610:813dcc80987e | 185 | */ |
mbed_official | 610:813dcc80987e | 186 | |
mbed_official | 610:813dcc80987e | 187 | /* Exported constants --------------------------------------------------------*/ |
mbed_official | 610:813dcc80987e | 188 | /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants |
mbed_official | 610:813dcc80987e | 189 | * @{ |
mbed_official | 610:813dcc80987e | 190 | */ |
mbed_official | 610:813dcc80987e | 191 | |
mbed_official | 610:813dcc80987e | 192 | /** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source |
mbed_official | 610:813dcc80987e | 193 | * @{ |
mbed_official | 610:813dcc80987e | 194 | */ |
mbed_official | 610:813dcc80987e | 195 | #define RCC_LSCOSOURCE_LSI (uint32_t)0x00000000 /*!< LSI selection for low speed clock output */ |
mbed_official | 610:813dcc80987e | 196 | #define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ |
mbed_official | 610:813dcc80987e | 197 | /** |
mbed_official | 610:813dcc80987e | 198 | * @} |
mbed_official | 610:813dcc80987e | 199 | */ |
mbed_official | 610:813dcc80987e | 200 | |
mbed_official | 610:813dcc80987e | 201 | /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection |
mbed_official | 610:813dcc80987e | 202 | * @{ |
mbed_official | 610:813dcc80987e | 203 | */ |
mbed_official | 610:813dcc80987e | 204 | #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) |
mbed_official | 610:813dcc80987e | 205 | #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) |
mbed_official | 610:813dcc80987e | 206 | #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004) |
mbed_official | 610:813dcc80987e | 207 | #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008) |
mbed_official | 610:813dcc80987e | 208 | #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010) |
mbed_official | 610:813dcc80987e | 209 | #define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000020) |
mbed_official | 610:813dcc80987e | 210 | #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000040) |
mbed_official | 610:813dcc80987e | 211 | #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000080) |
mbed_official | 610:813dcc80987e | 212 | #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100) |
mbed_official | 610:813dcc80987e | 213 | #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000200) |
mbed_official | 610:813dcc80987e | 214 | #define RCC_PERIPHCLK_LPTIM2 ((uint32_t)0x00000400) |
mbed_official | 610:813dcc80987e | 215 | #define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000800) |
mbed_official | 610:813dcc80987e | 216 | #define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00001000) |
mbed_official | 610:813dcc80987e | 217 | #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) |
mbed_official | 610:813dcc80987e | 218 | #define RCC_PERIPHCLK_USB ((uint32_t)0x00002000) |
mbed_official | 610:813dcc80987e | 219 | #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
mbed_official | 610:813dcc80987e | 220 | #define RCC_PERIPHCLK_ADC ((uint32_t)0x00004000) |
mbed_official | 610:813dcc80987e | 221 | #define RCC_PERIPHCLK_SWPMI1 ((uint32_t)0x00008000) |
mbed_official | 610:813dcc80987e | 222 | #define RCC_PERIPHCLK_DFSDM ((uint32_t)0x00010000) |
mbed_official | 610:813dcc80987e | 223 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00020000) |
mbed_official | 610:813dcc80987e | 224 | #define RCC_PERIPHCLK_RNG ((uint32_t)0x00040000) |
mbed_official | 610:813dcc80987e | 225 | #define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00080000) |
mbed_official | 610:813dcc80987e | 226 | /** |
mbed_official | 610:813dcc80987e | 227 | * @} |
mbed_official | 610:813dcc80987e | 228 | */ |
mbed_official | 610:813dcc80987e | 229 | |
mbed_official | 610:813dcc80987e | 230 | |
mbed_official | 610:813dcc80987e | 231 | /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source |
mbed_official | 610:813dcc80987e | 232 | * @{ |
mbed_official | 610:813dcc80987e | 233 | */ |
mbed_official | 610:813dcc80987e | 234 | #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000) |
mbed_official | 610:813dcc80987e | 235 | #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 |
mbed_official | 610:813dcc80987e | 236 | #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 |
mbed_official | 610:813dcc80987e | 237 | #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) |
mbed_official | 610:813dcc80987e | 238 | /** |
mbed_official | 610:813dcc80987e | 239 | * @} |
mbed_official | 610:813dcc80987e | 240 | */ |
mbed_official | 610:813dcc80987e | 241 | |
mbed_official | 610:813dcc80987e | 242 | /** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source |
mbed_official | 610:813dcc80987e | 243 | * @{ |
mbed_official | 610:813dcc80987e | 244 | */ |
mbed_official | 610:813dcc80987e | 245 | #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
mbed_official | 610:813dcc80987e | 246 | #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 |
mbed_official | 610:813dcc80987e | 247 | #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 |
mbed_official | 610:813dcc80987e | 248 | #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) |
mbed_official | 610:813dcc80987e | 249 | /** |
mbed_official | 610:813dcc80987e | 250 | * @} |
mbed_official | 610:813dcc80987e | 251 | */ |
mbed_official | 610:813dcc80987e | 252 | |
mbed_official | 610:813dcc80987e | 253 | /** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source |
mbed_official | 610:813dcc80987e | 254 | * @{ |
mbed_official | 610:813dcc80987e | 255 | */ |
mbed_official | 610:813dcc80987e | 256 | #define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
mbed_official | 610:813dcc80987e | 257 | #define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0 |
mbed_official | 610:813dcc80987e | 258 | #define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1 |
mbed_official | 610:813dcc80987e | 259 | #define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1) |
mbed_official | 610:813dcc80987e | 260 | /** |
mbed_official | 610:813dcc80987e | 261 | * @} |
mbed_official | 610:813dcc80987e | 262 | */ |
mbed_official | 610:813dcc80987e | 263 | |
mbed_official | 610:813dcc80987e | 264 | /** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source |
mbed_official | 610:813dcc80987e | 265 | * @{ |
mbed_official | 610:813dcc80987e | 266 | */ |
mbed_official | 610:813dcc80987e | 267 | #define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
mbed_official | 610:813dcc80987e | 268 | #define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0 |
mbed_official | 610:813dcc80987e | 269 | #define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1 |
mbed_official | 610:813dcc80987e | 270 | #define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1) |
mbed_official | 610:813dcc80987e | 271 | /** |
mbed_official | 610:813dcc80987e | 272 | * @} |
mbed_official | 610:813dcc80987e | 273 | */ |
mbed_official | 610:813dcc80987e | 274 | |
mbed_official | 610:813dcc80987e | 275 | /** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source |
mbed_official | 610:813dcc80987e | 276 | * @{ |
mbed_official | 610:813dcc80987e | 277 | */ |
mbed_official | 610:813dcc80987e | 278 | #define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
mbed_official | 610:813dcc80987e | 279 | #define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0 |
mbed_official | 610:813dcc80987e | 280 | #define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1 |
mbed_official | 610:813dcc80987e | 281 | #define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1) |
mbed_official | 610:813dcc80987e | 282 | /** |
mbed_official | 610:813dcc80987e | 283 | * @} |
mbed_official | 610:813dcc80987e | 284 | */ |
mbed_official | 610:813dcc80987e | 285 | |
mbed_official | 610:813dcc80987e | 286 | /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source |
mbed_official | 610:813dcc80987e | 287 | * @{ |
mbed_official | 610:813dcc80987e | 288 | */ |
mbed_official | 610:813dcc80987e | 289 | #define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
mbed_official | 610:813dcc80987e | 290 | #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 |
mbed_official | 610:813dcc80987e | 291 | #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 |
mbed_official | 610:813dcc80987e | 292 | #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) |
mbed_official | 610:813dcc80987e | 293 | /** |
mbed_official | 610:813dcc80987e | 294 | * @} |
mbed_official | 610:813dcc80987e | 295 | */ |
mbed_official | 610:813dcc80987e | 296 | |
mbed_official | 610:813dcc80987e | 297 | /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source |
mbed_official | 610:813dcc80987e | 298 | * @{ |
mbed_official | 610:813dcc80987e | 299 | */ |
mbed_official | 610:813dcc80987e | 300 | #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
mbed_official | 610:813dcc80987e | 301 | #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 |
mbed_official | 610:813dcc80987e | 302 | #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 |
mbed_official | 610:813dcc80987e | 303 | /** |
mbed_official | 610:813dcc80987e | 304 | * @} |
mbed_official | 610:813dcc80987e | 305 | */ |
mbed_official | 610:813dcc80987e | 306 | |
mbed_official | 610:813dcc80987e | 307 | /** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source |
mbed_official | 610:813dcc80987e | 308 | * @{ |
mbed_official | 610:813dcc80987e | 309 | */ |
mbed_official | 610:813dcc80987e | 310 | #define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
mbed_official | 610:813dcc80987e | 311 | #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0 |
mbed_official | 610:813dcc80987e | 312 | #define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1 |
mbed_official | 610:813dcc80987e | 313 | /** |
mbed_official | 610:813dcc80987e | 314 | * @} |
mbed_official | 610:813dcc80987e | 315 | */ |
mbed_official | 610:813dcc80987e | 316 | |
mbed_official | 610:813dcc80987e | 317 | /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source |
mbed_official | 610:813dcc80987e | 318 | * @{ |
mbed_official | 610:813dcc80987e | 319 | */ |
mbed_official | 610:813dcc80987e | 320 | #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000) |
mbed_official | 610:813dcc80987e | 321 | #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 |
mbed_official | 610:813dcc80987e | 322 | #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 |
mbed_official | 610:813dcc80987e | 323 | /** |
mbed_official | 610:813dcc80987e | 324 | * @} |
mbed_official | 610:813dcc80987e | 325 | */ |
mbed_official | 610:813dcc80987e | 326 | |
mbed_official | 610:813dcc80987e | 327 | /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source |
mbed_official | 610:813dcc80987e | 328 | * @{ |
mbed_official | 610:813dcc80987e | 329 | */ |
mbed_official | 610:813dcc80987e | 330 | #define RCC_SAI1CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000) |
mbed_official | 610:813dcc80987e | 331 | #define RCC_SAI1CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI1SEL_0 |
mbed_official | 610:813dcc80987e | 332 | #define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_1 |
mbed_official | 610:813dcc80987e | 333 | #define RCC_SAI1CLKSOURCE_PIN RCC_CCIPR_SAI1SEL |
mbed_official | 610:813dcc80987e | 334 | /** |
mbed_official | 610:813dcc80987e | 335 | * @} |
mbed_official | 610:813dcc80987e | 336 | */ |
mbed_official | 610:813dcc80987e | 337 | |
mbed_official | 610:813dcc80987e | 338 | /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source |
mbed_official | 610:813dcc80987e | 339 | * @{ |
mbed_official | 610:813dcc80987e | 340 | */ |
mbed_official | 610:813dcc80987e | 341 | #define RCC_SAI2CLKSOURCE_PLLSAI1 ((uint32_t)0x00000000) |
mbed_official | 610:813dcc80987e | 342 | #define RCC_SAI2CLKSOURCE_PLLSAI2 RCC_CCIPR_SAI2SEL_0 |
mbed_official | 610:813dcc80987e | 343 | #define RCC_SAI2CLKSOURCE_PLL RCC_CCIPR_SAI2SEL_1 |
mbed_official | 610:813dcc80987e | 344 | #define RCC_SAI2CLKSOURCE_PIN RCC_CCIPR_SAI2SEL |
mbed_official | 610:813dcc80987e | 345 | /** |
mbed_official | 610:813dcc80987e | 346 | * @} |
mbed_official | 610:813dcc80987e | 347 | */ |
mbed_official | 610:813dcc80987e | 348 | |
mbed_official | 610:813dcc80987e | 349 | /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source |
mbed_official | 610:813dcc80987e | 350 | * @{ |
mbed_official | 610:813dcc80987e | 351 | */ |
mbed_official | 610:813dcc80987e | 352 | #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000) |
mbed_official | 610:813dcc80987e | 353 | #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 |
mbed_official | 610:813dcc80987e | 354 | #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 |
mbed_official | 610:813dcc80987e | 355 | #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL |
mbed_official | 610:813dcc80987e | 356 | /** |
mbed_official | 610:813dcc80987e | 357 | * @} |
mbed_official | 610:813dcc80987e | 358 | */ |
mbed_official | 610:813dcc80987e | 359 | |
mbed_official | 610:813dcc80987e | 360 | /** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source |
mbed_official | 610:813dcc80987e | 361 | * @{ |
mbed_official | 610:813dcc80987e | 362 | */ |
mbed_official | 610:813dcc80987e | 363 | #define RCC_LPTIM2CLKSOURCE_PCLK ((uint32_t)0x00000000) |
mbed_official | 610:813dcc80987e | 364 | #define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR_LPTIM2SEL_0 |
mbed_official | 610:813dcc80987e | 365 | #define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR_LPTIM2SEL_1 |
mbed_official | 610:813dcc80987e | 366 | #define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR_LPTIM2SEL |
mbed_official | 610:813dcc80987e | 367 | /** |
mbed_official | 610:813dcc80987e | 368 | * @} |
mbed_official | 610:813dcc80987e | 369 | */ |
mbed_official | 610:813dcc80987e | 370 | |
mbed_official | 610:813dcc80987e | 371 | /** @defgroup RCCEx_SDMMC1_Clock_Source SDMMC1 Clock Source |
mbed_official | 610:813dcc80987e | 372 | * @{ |
mbed_official | 610:813dcc80987e | 373 | */ |
mbed_official | 610:813dcc80987e | 374 | #define RCC_SDMMC1CLKSOURCE_NONE ((uint32_t)0x00000000) |
mbed_official | 610:813dcc80987e | 375 | #define RCC_SDMMC1CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 |
mbed_official | 610:813dcc80987e | 376 | #define RCC_SDMMC1CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 |
mbed_official | 610:813dcc80987e | 377 | #define RCC_SDMMC1CLKSOURCE_MSI RCC_CCIPR_CLK48SEL |
mbed_official | 610:813dcc80987e | 378 | /** |
mbed_official | 610:813dcc80987e | 379 | * @} |
mbed_official | 610:813dcc80987e | 380 | */ |
mbed_official | 610:813dcc80987e | 381 | |
mbed_official | 610:813dcc80987e | 382 | /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source |
mbed_official | 610:813dcc80987e | 383 | * @{ |
mbed_official | 610:813dcc80987e | 384 | */ |
mbed_official | 610:813dcc80987e | 385 | #define RCC_RNGCLKSOURCE_NONE ((uint32_t)0x00000000) |
mbed_official | 610:813dcc80987e | 386 | #define RCC_RNGCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 |
mbed_official | 610:813dcc80987e | 387 | #define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 |
mbed_official | 610:813dcc80987e | 388 | #define RCC_RNGCLKSOURCE_MSI RCC_CCIPR_CLK48SEL |
mbed_official | 610:813dcc80987e | 389 | /** |
mbed_official | 610:813dcc80987e | 390 | * @} |
mbed_official | 610:813dcc80987e | 391 | */ |
mbed_official | 610:813dcc80987e | 392 | |
mbed_official | 610:813dcc80987e | 393 | #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) |
mbed_official | 610:813dcc80987e | 394 | /** @defgroup RCCEx_USB_Clock_Source USB Clock Source |
mbed_official | 610:813dcc80987e | 395 | * @{ |
mbed_official | 610:813dcc80987e | 396 | */ |
mbed_official | 610:813dcc80987e | 397 | #define RCC_USBCLKSOURCE_NONE ((uint32_t)0x00000000) |
mbed_official | 610:813dcc80987e | 398 | #define RCC_USBCLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 |
mbed_official | 610:813dcc80987e | 399 | #define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 |
mbed_official | 610:813dcc80987e | 400 | #define RCC_USBCLKSOURCE_MSI RCC_CCIPR_CLK48SEL |
mbed_official | 610:813dcc80987e | 401 | /** |
mbed_official | 610:813dcc80987e | 402 | * @} |
mbed_official | 610:813dcc80987e | 403 | */ |
mbed_official | 610:813dcc80987e | 404 | #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
mbed_official | 610:813dcc80987e | 405 | |
mbed_official | 610:813dcc80987e | 406 | /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source |
mbed_official | 610:813dcc80987e | 407 | * @{ |
mbed_official | 610:813dcc80987e | 408 | */ |
mbed_official | 610:813dcc80987e | 409 | #define RCC_ADCCLKSOURCE_NONE ((uint32_t)0x00000000) |
mbed_official | 610:813dcc80987e | 410 | #define RCC_ADCCLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 |
mbed_official | 610:813dcc80987e | 411 | #define RCC_ADCCLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 |
mbed_official | 610:813dcc80987e | 412 | #define RCC_ADCCLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL |
mbed_official | 610:813dcc80987e | 413 | /** |
mbed_official | 610:813dcc80987e | 414 | * @} |
mbed_official | 610:813dcc80987e | 415 | */ |
mbed_official | 610:813dcc80987e | 416 | |
mbed_official | 610:813dcc80987e | 417 | /** @defgroup RCCEx_SWPMI1_Clock_Source SWPMI1 Clock Source |
mbed_official | 610:813dcc80987e | 418 | * @{ |
mbed_official | 610:813dcc80987e | 419 | */ |
mbed_official | 610:813dcc80987e | 420 | #define RCC_SWPMI1CLKSOURCE_PCLK ((uint32_t)0x00000000) |
mbed_official | 610:813dcc80987e | 421 | #define RCC_SWPMI1CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL |
mbed_official | 610:813dcc80987e | 422 | /** |
mbed_official | 610:813dcc80987e | 423 | * @} |
mbed_official | 610:813dcc80987e | 424 | */ |
mbed_official | 610:813dcc80987e | 425 | |
mbed_official | 610:813dcc80987e | 426 | /** @defgroup RCCEx_DFSDM_Clock_Source DFSDM Clock Source |
mbed_official | 610:813dcc80987e | 427 | * @{ |
mbed_official | 610:813dcc80987e | 428 | */ |
mbed_official | 610:813dcc80987e | 429 | #define RCC_DFSDMCLKSOURCE_PCLK ((uint32_t)0x00000000) |
mbed_official | 610:813dcc80987e | 430 | #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_CCIPR_DFSDMSEL |
mbed_official | 610:813dcc80987e | 431 | /** |
mbed_official | 610:813dcc80987e | 432 | * @} |
mbed_official | 610:813dcc80987e | 433 | */ |
mbed_official | 610:813dcc80987e | 434 | |
mbed_official | 610:813dcc80987e | 435 | /** |
mbed_official | 610:813dcc80987e | 436 | * @} |
mbed_official | 610:813dcc80987e | 437 | */ |
mbed_official | 610:813dcc80987e | 438 | |
mbed_official | 610:813dcc80987e | 439 | /* Exported macros -----------------------------------------------------------*/ |
mbed_official | 610:813dcc80987e | 440 | /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros |
mbed_official | 610:813dcc80987e | 441 | * @{ |
mbed_official | 610:813dcc80987e | 442 | */ |
mbed_official | 610:813dcc80987e | 443 | |
mbed_official | 610:813dcc80987e | 444 | /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable |
mbed_official | 610:813dcc80987e | 445 | * @brief Enable or disable the AHB2 peripheral clock. |
mbed_official | 610:813dcc80987e | 446 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 610:813dcc80987e | 447 | * is disabled and the application software has to enable this clock before |
mbed_official | 610:813dcc80987e | 448 | * using it. |
mbed_official | 610:813dcc80987e | 449 | * @{ |
mbed_official | 610:813dcc80987e | 450 | */ |
mbed_official | 610:813dcc80987e | 451 | |
mbed_official | 610:813dcc80987e | 452 | #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) |
mbed_official | 610:813dcc80987e | 453 | #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ |
mbed_official | 610:813dcc80987e | 454 | __IO uint32_t tmpreg; \ |
mbed_official | 610:813dcc80987e | 455 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ |
mbed_official | 610:813dcc80987e | 456 | /* Delay after an RCC peripheral clock enabling */ \ |
mbed_official | 610:813dcc80987e | 457 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); \ |
mbed_official | 610:813dcc80987e | 458 | UNUSED(tmpreg); \ |
mbed_official | 610:813dcc80987e | 459 | } while(0) |
mbed_official | 610:813dcc80987e | 460 | |
mbed_official | 610:813dcc80987e | 461 | #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN); |
mbed_official | 610:813dcc80987e | 462 | #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
mbed_official | 610:813dcc80987e | 463 | |
mbed_official | 610:813dcc80987e | 464 | |
mbed_official | 610:813dcc80987e | 465 | #if defined(STM32L485xx) || defined(STM32L486xx) |
mbed_official | 610:813dcc80987e | 466 | #define __HAL_RCC_AES_CLK_ENABLE() do { \ |
mbed_official | 610:813dcc80987e | 467 | __IO uint32_t tmpreg; \ |
mbed_official | 610:813dcc80987e | 468 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ |
mbed_official | 610:813dcc80987e | 469 | /* Delay after an RCC peripheral clock enabling */ \ |
mbed_official | 610:813dcc80987e | 470 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \ |
mbed_official | 610:813dcc80987e | 471 | UNUSED(tmpreg); \ |
mbed_official | 610:813dcc80987e | 472 | } while(0) |
mbed_official | 610:813dcc80987e | 473 | |
mbed_official | 610:813dcc80987e | 474 | #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); |
mbed_official | 610:813dcc80987e | 475 | #endif /* STM32L485xx || STM32L486xx */ |
mbed_official | 610:813dcc80987e | 476 | |
mbed_official | 610:813dcc80987e | 477 | /** |
mbed_official | 610:813dcc80987e | 478 | * @} |
mbed_official | 610:813dcc80987e | 479 | */ |
mbed_official | 610:813dcc80987e | 480 | |
mbed_official | 610:813dcc80987e | 481 | /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable |
mbed_official | 610:813dcc80987e | 482 | * @brief Enable or disable the APB1 peripheral clock. |
mbed_official | 610:813dcc80987e | 483 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 610:813dcc80987e | 484 | * is disabled and the application software has to enable this clock before |
mbed_official | 610:813dcc80987e | 485 | * using it. |
mbed_official | 610:813dcc80987e | 486 | * @{ |
mbed_official | 610:813dcc80987e | 487 | */ |
mbed_official | 610:813dcc80987e | 488 | #if defined(STM32L476xx) || defined(STM32L486xx) |
mbed_official | 610:813dcc80987e | 489 | #define __HAL_RCC_LCD_CLK_ENABLE() do { \ |
mbed_official | 610:813dcc80987e | 490 | __IO uint32_t tmpreg; \ |
mbed_official | 610:813dcc80987e | 491 | SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ |
mbed_official | 610:813dcc80987e | 492 | /* Delay after an RCC peripheral clock enabling */ \ |
mbed_official | 610:813dcc80987e | 493 | tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); \ |
mbed_official | 610:813dcc80987e | 494 | UNUSED(tmpreg); \ |
mbed_official | 610:813dcc80987e | 495 | } while(0) |
mbed_official | 610:813dcc80987e | 496 | |
mbed_official | 610:813dcc80987e | 497 | #define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN); |
mbed_official | 610:813dcc80987e | 498 | #endif /* STM32L476xx || STM32L486xx */ |
mbed_official | 610:813dcc80987e | 499 | |
mbed_official | 610:813dcc80987e | 500 | /** |
mbed_official | 610:813dcc80987e | 501 | * @} |
mbed_official | 610:813dcc80987e | 502 | */ |
mbed_official | 610:813dcc80987e | 503 | |
mbed_official | 610:813dcc80987e | 504 | /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status |
mbed_official | 610:813dcc80987e | 505 | * @brief Macros to get the status of the AHB2 peripheral clock. |
mbed_official | 610:813dcc80987e | 506 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 610:813dcc80987e | 507 | * is disabled and the application software has to enable this clock before |
mbed_official | 610:813dcc80987e | 508 | * using it. |
mbed_official | 610:813dcc80987e | 509 | * @{ |
mbed_official | 610:813dcc80987e | 510 | */ |
mbed_official | 610:813dcc80987e | 511 | |
mbed_official | 610:813dcc80987e | 512 | #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L486xx) |
mbed_official | 610:813dcc80987e | 513 | #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) != RESET) |
mbed_official | 610:813dcc80987e | 514 | |
mbed_official | 610:813dcc80987e | 515 | #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN) == RESET) |
mbed_official | 610:813dcc80987e | 516 | #endif /* STM32L475xx || STM32L476xx || STM32L486xx */ |
mbed_official | 610:813dcc80987e | 517 | |
mbed_official | 610:813dcc80987e | 518 | |
mbed_official | 610:813dcc80987e | 519 | #if defined(STM32L485xx) || defined(STM32L486xx) |
mbed_official | 610:813dcc80987e | 520 | #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != RESET) |
mbed_official | 610:813dcc80987e | 521 | |
mbed_official | 610:813dcc80987e | 522 | #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == RESET) |
mbed_official | 610:813dcc80987e | 523 | #endif /* STM32L485xx || STM32L486xx */ |
mbed_official | 610:813dcc80987e | 524 | |
mbed_official | 610:813dcc80987e | 525 | /** |
mbed_official | 610:813dcc80987e | 526 | * @} |
mbed_official | 610:813dcc80987e | 527 | */ |
mbed_official | 610:813dcc80987e | 528 | |
mbed_official | 610:813dcc80987e | 529 | /** @defgroup RCCEx_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status |
mbed_official | 610:813dcc80987e | 530 | * @brief Macros to get the status of the APB1 peripheral clock. |
mbed_official | 610:813dcc80987e | 531 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 610:813dcc80987e | 532 | * is disabled and the application software has to enable this clock before |
mbed_official | 610:813dcc80987e | 533 | * using it. |
mbed_official | 610:813dcc80987e | 534 | * @{ |
mbed_official | 610:813dcc80987e | 535 | */ |
mbed_official | 610:813dcc80987e | 536 | #if defined(STM32L476xx) || defined(STM32L486xx) |
mbed_official | 610:813dcc80987e | 537 | #define __HAL_RCC_LCD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) != RESET) |
mbed_official | 610:813dcc80987e | 538 | |
mbed_official | 610:813dcc80987e | 539 | #define __HAL_RCC_LCD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LCDEN) == RESET) |
mbed_official | 610:813dcc80987e | 540 | #endif /* STM32L476xx || STM32L486xx */ |
mbed_official | 610:813dcc80987e | 541 | |
mbed_official | 610:813dcc80987e | 542 | /** |
mbed_official | 610:813dcc80987e | 543 | * @} |
mbed_official | 610:813dcc80987e | 544 | */ |
mbed_official | 610:813dcc80987e | 545 | |
mbed_official | 610:813dcc80987e | 546 | /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset |
mbed_official | 610:813dcc80987e | 547 | * @brief Force or release AHB2 peripheral reset. |
mbed_official | 610:813dcc80987e | 548 | * @{ |
mbed_official | 610:813dcc80987e | 549 | */ |
mbed_official | 610:813dcc80987e | 550 | |
mbed_official | 610:813dcc80987e | 551 | #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) |
mbed_official | 610:813dcc80987e | 552 | #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) |
mbed_official | 610:813dcc80987e | 553 | |
mbed_official | 610:813dcc80987e | 554 | #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_OTGFSRST) |
mbed_official | 610:813dcc80987e | 555 | #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
mbed_official | 610:813dcc80987e | 556 | |
mbed_official | 610:813dcc80987e | 557 | #if defined(STM32L485xx) || defined(STM32L486xx) |
mbed_official | 610:813dcc80987e | 558 | #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) |
mbed_official | 610:813dcc80987e | 559 | |
mbed_official | 610:813dcc80987e | 560 | #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST) |
mbed_official | 610:813dcc80987e | 561 | #endif /* STM32L485xx || STM32L486xx */ |
mbed_official | 610:813dcc80987e | 562 | |
mbed_official | 610:813dcc80987e | 563 | /** |
mbed_official | 610:813dcc80987e | 564 | * @} |
mbed_official | 610:813dcc80987e | 565 | */ |
mbed_official | 610:813dcc80987e | 566 | |
mbed_official | 610:813dcc80987e | 567 | |
mbed_official | 610:813dcc80987e | 568 | /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset |
mbed_official | 610:813dcc80987e | 569 | * @brief Force or release APB1 peripheral reset. |
mbed_official | 610:813dcc80987e | 570 | * @{ |
mbed_official | 610:813dcc80987e | 571 | */ |
mbed_official | 610:813dcc80987e | 572 | #if defined(STM32L476xx) || defined(STM32L486xx) |
mbed_official | 610:813dcc80987e | 573 | #define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) |
mbed_official | 610:813dcc80987e | 574 | |
mbed_official | 610:813dcc80987e | 575 | #define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LCDRST) |
mbed_official | 610:813dcc80987e | 576 | #endif /* STM32L476xx || STM32L486xx */ |
mbed_official | 610:813dcc80987e | 577 | |
mbed_official | 610:813dcc80987e | 578 | /** |
mbed_official | 610:813dcc80987e | 579 | * @} |
mbed_official | 610:813dcc80987e | 580 | */ |
mbed_official | 610:813dcc80987e | 581 | |
mbed_official | 610:813dcc80987e | 582 | |
mbed_official | 610:813dcc80987e | 583 | /** @defgroup RCCEx_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable |
mbed_official | 610:813dcc80987e | 584 | * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. |
mbed_official | 610:813dcc80987e | 585 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
mbed_official | 610:813dcc80987e | 586 | * power consumption. |
mbed_official | 610:813dcc80987e | 587 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
mbed_official | 610:813dcc80987e | 588 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
mbed_official | 610:813dcc80987e | 589 | * @{ |
mbed_official | 610:813dcc80987e | 590 | */ |
mbed_official | 610:813dcc80987e | 591 | |
mbed_official | 610:813dcc80987e | 592 | #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) |
mbed_official | 610:813dcc80987e | 593 | #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) |
mbed_official | 610:813dcc80987e | 594 | |
mbed_official | 610:813dcc80987e | 595 | #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) |
mbed_official | 610:813dcc80987e | 596 | #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
mbed_official | 610:813dcc80987e | 597 | |
mbed_official | 610:813dcc80987e | 598 | #if defined(STM32L485xx) || defined(STM32L486xx) |
mbed_official | 610:813dcc80987e | 599 | #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) |
mbed_official | 610:813dcc80987e | 600 | |
mbed_official | 610:813dcc80987e | 601 | #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) |
mbed_official | 610:813dcc80987e | 602 | #endif /* STM32L485xx || STM32L486xx */ |
mbed_official | 610:813dcc80987e | 603 | |
mbed_official | 610:813dcc80987e | 604 | /** |
mbed_official | 610:813dcc80987e | 605 | * @} |
mbed_official | 610:813dcc80987e | 606 | */ |
mbed_official | 610:813dcc80987e | 607 | |
mbed_official | 610:813dcc80987e | 608 | |
mbed_official | 610:813dcc80987e | 609 | /** @defgroup RCCEx_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable |
mbed_official | 610:813dcc80987e | 610 | * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. |
mbed_official | 610:813dcc80987e | 611 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
mbed_official | 610:813dcc80987e | 612 | * power consumption. |
mbed_official | 610:813dcc80987e | 613 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
mbed_official | 610:813dcc80987e | 614 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
mbed_official | 610:813dcc80987e | 615 | * @{ |
mbed_official | 610:813dcc80987e | 616 | */ |
mbed_official | 610:813dcc80987e | 617 | |
mbed_official | 610:813dcc80987e | 618 | #if defined(STM32L476xx) || defined(STM32L486xx) |
mbed_official | 610:813dcc80987e | 619 | #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) |
mbed_official | 610:813dcc80987e | 620 | |
mbed_official | 610:813dcc80987e | 621 | #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) |
mbed_official | 610:813dcc80987e | 622 | #endif /* STM32L476xx || STM32L486xx */ |
mbed_official | 610:813dcc80987e | 623 | |
mbed_official | 610:813dcc80987e | 624 | /** |
mbed_official | 610:813dcc80987e | 625 | * @} |
mbed_official | 610:813dcc80987e | 626 | */ |
mbed_official | 610:813dcc80987e | 627 | |
mbed_official | 610:813dcc80987e | 628 | /** @defgroup RCCEx_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enable Disable Status |
mbed_official | 610:813dcc80987e | 629 | * @brief Macros to get the status of the AHB2 peripheral clock during Low Power (Sleep) mode. |
mbed_official | 610:813dcc80987e | 630 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
mbed_official | 610:813dcc80987e | 631 | * power consumption. |
mbed_official | 610:813dcc80987e | 632 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
mbed_official | 610:813dcc80987e | 633 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
mbed_official | 610:813dcc80987e | 634 | * @{ |
mbed_official | 610:813dcc80987e | 635 | */ |
mbed_official | 610:813dcc80987e | 636 | |
mbed_official | 610:813dcc80987e | 637 | #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) |
mbed_official | 610:813dcc80987e | 638 | #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) != RESET) |
mbed_official | 610:813dcc80987e | 639 | |
mbed_official | 610:813dcc80987e | 640 | #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_OTGFSSMEN) == RESET) |
mbed_official | 610:813dcc80987e | 641 | #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
mbed_official | 610:813dcc80987e | 642 | |
mbed_official | 610:813dcc80987e | 643 | #if defined(STM32L485xx) || defined(STM32L486xx) |
mbed_official | 610:813dcc80987e | 644 | #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != RESET) |
mbed_official | 610:813dcc80987e | 645 | |
mbed_official | 610:813dcc80987e | 646 | #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == RESET) |
mbed_official | 610:813dcc80987e | 647 | #endif /* STM32L485xx || STM32L486xx */ |
mbed_official | 610:813dcc80987e | 648 | |
mbed_official | 610:813dcc80987e | 649 | /** |
mbed_official | 610:813dcc80987e | 650 | * @} |
mbed_official | 610:813dcc80987e | 651 | */ |
mbed_official | 610:813dcc80987e | 652 | |
mbed_official | 610:813dcc80987e | 653 | |
mbed_official | 610:813dcc80987e | 654 | /** @defgroup RCCEx_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status |
mbed_official | 610:813dcc80987e | 655 | * @brief Macros to get the status of the APB1 peripheral clock during Low Power (Sleep) mode. |
mbed_official | 610:813dcc80987e | 656 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
mbed_official | 610:813dcc80987e | 657 | * power consumption. |
mbed_official | 610:813dcc80987e | 658 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
mbed_official | 610:813dcc80987e | 659 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
mbed_official | 610:813dcc80987e | 660 | * @{ |
mbed_official | 610:813dcc80987e | 661 | */ |
mbed_official | 610:813dcc80987e | 662 | |
mbed_official | 610:813dcc80987e | 663 | #if defined(STM32L476xx) || defined(STM32L486xx) |
mbed_official | 610:813dcc80987e | 664 | #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) != RESET) |
mbed_official | 610:813dcc80987e | 665 | |
mbed_official | 610:813dcc80987e | 666 | #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LCDSMEN) == RESET) |
mbed_official | 610:813dcc80987e | 667 | #endif /* STM32L476xx || STM32L486xx */ |
mbed_official | 610:813dcc80987e | 668 | |
mbed_official | 610:813dcc80987e | 669 | /** |
mbed_official | 610:813dcc80987e | 670 | * @} |
mbed_official | 610:813dcc80987e | 671 | */ |
mbed_official | 610:813dcc80987e | 672 | |
mbed_official | 610:813dcc80987e | 673 | /** |
mbed_official | 610:813dcc80987e | 674 | * @brief Macro to configure the PLLSAI1 clock multiplication and division factors. |
mbed_official | 610:813dcc80987e | 675 | * |
mbed_official | 610:813dcc80987e | 676 | * @note This function must be used only when the PLLSAI1 is disabled. |
mbed_official | 610:813dcc80987e | 677 | * @note PLLSAI1 clock source is common with the main PLL (configured through |
mbed_official | 610:813dcc80987e | 678 | * __HAL_RCC_PLL_CONFIG() macro) |
mbed_official | 610:813dcc80987e | 679 | * |
mbed_official | 610:813dcc80987e | 680 | * @param __PLLSAI1N__: specifies the multiplication factor for PLLSAI1 VCO output clock. |
mbed_official | 610:813dcc80987e | 681 | * This parameter must be a number between 8 and 86. |
mbed_official | 610:813dcc80987e | 682 | * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO |
mbed_official | 610:813dcc80987e | 683 | * output frequency is between 64 and 344 MHz. |
mbed_official | 610:813dcc80987e | 684 | * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N |
mbed_official | 610:813dcc80987e | 685 | * |
mbed_official | 610:813dcc80987e | 686 | * @param __PLLSAI1P__: specifies the division factor for SAI clock. |
mbed_official | 610:813dcc80987e | 687 | * This parameter must be a number in the range (7 or 17). |
mbed_official | 610:813dcc80987e | 688 | * SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P |
mbed_official | 610:813dcc80987e | 689 | * |
mbed_official | 610:813dcc80987e | 690 | * @param __PLLSAI1Q__: specifies the division factor for USB/RNG/SDMMC1 clock. |
mbed_official | 610:813dcc80987e | 691 | * This parameter must be in the range (2, 4, 6 or 8). |
mbed_official | 610:813dcc80987e | 692 | * USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q |
mbed_official | 610:813dcc80987e | 693 | * |
mbed_official | 610:813dcc80987e | 694 | * @param __PLLSAI1R__: specifies the division factor for SAR ADC clock. |
mbed_official | 610:813dcc80987e | 695 | * This parameter must be in the range (2, 4, 6 or 8). |
mbed_official | 610:813dcc80987e | 696 | * ADC clock frequency = f(PLLSAI1) / PLLSAI1R |
mbed_official | 610:813dcc80987e | 697 | * |
mbed_official | 610:813dcc80987e | 698 | * @retval None |
mbed_official | 610:813dcc80987e | 699 | */ |
mbed_official | 610:813dcc80987e | 700 | #define __HAL_RCC_PLLSAI1_CONFIG(__PLLSAI1N__, __PLLSAI1P__, __PLLSAI1Q__, __PLLSAI1R__) \ |
mbed_official | 610:813dcc80987e | 701 | WRITE_REG(RCC->PLLSAI1CFGR, ((__PLLSAI1N__) << 8U) | (((__PLLSAI1P__) >> 4U) << 17U) | \ |
mbed_official | 610:813dcc80987e | 702 | ((((__PLLSAI1Q__) >> 1U) - 1) << 21U) | ((((__PLLSAI1R__) >> 1U) - 1) << 25U)) |
mbed_official | 610:813dcc80987e | 703 | |
mbed_official | 610:813dcc80987e | 704 | /** |
mbed_official | 610:813dcc80987e | 705 | * @brief Macro to configure the PLLSAI1 clock multiplication factor N. |
mbed_official | 610:813dcc80987e | 706 | * |
mbed_official | 610:813dcc80987e | 707 | * @note This function must be used only when the PLLSAI1 is disabled. |
mbed_official | 610:813dcc80987e | 708 | * @note PLLSAI1 clock source is common with the main PLL (configured through |
mbed_official | 610:813dcc80987e | 709 | * __HAL_RCC_PLL_CONFIG() macro) |
mbed_official | 610:813dcc80987e | 710 | * |
mbed_official | 610:813dcc80987e | 711 | * @param __PLLSAI1N__: specifies the multiplication factor for PLLSAI1 VCO output clock. |
mbed_official | 610:813dcc80987e | 712 | * This parameter must be a number between 8 and 86. |
mbed_official | 610:813dcc80987e | 713 | * @note You have to set the PLLSAI1N parameter correctly to ensure that the VCO |
mbed_official | 610:813dcc80987e | 714 | * output frequency is between 64 and 344 MHz. |
mbed_official | 610:813dcc80987e | 715 | * Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI1N |
mbed_official | 610:813dcc80987e | 716 | * |
mbed_official | 610:813dcc80987e | 717 | * @retval None |
mbed_official | 610:813dcc80987e | 718 | */ |
mbed_official | 610:813dcc80987e | 719 | #define __HAL_RCC_PLLSAI1_MULN_CONFIG(__PLLSAI1N__) \ |
mbed_official | 610:813dcc80987e | 720 | MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N, (__PLLSAI1N__) << 8U) |
mbed_official | 610:813dcc80987e | 721 | |
mbed_official | 610:813dcc80987e | 722 | /** @brief Macro to configure the PLLSAI1 clock division factor P. |
mbed_official | 610:813dcc80987e | 723 | * |
mbed_official | 610:813dcc80987e | 724 | * @note This function must be used only when the PLLSAI1 is disabled. |
mbed_official | 610:813dcc80987e | 725 | * @note PLLSAI1 clock source is common with the main PLL (configured through |
mbed_official | 610:813dcc80987e | 726 | * __HAL_RCC_PLL_CONFIG() macro) |
mbed_official | 610:813dcc80987e | 727 | * |
mbed_official | 610:813dcc80987e | 728 | * @param __PLLSAI1P__: specifies the division factor for SAI clock. |
mbed_official | 610:813dcc80987e | 729 | * This parameter must be a number in the range (7 or 17). |
mbed_official | 610:813dcc80987e | 730 | * Use to set SAI1 clock frequency = f(PLLSAI1) / PLLSAI1P |
mbed_official | 610:813dcc80987e | 731 | * |
mbed_official | 610:813dcc80987e | 732 | * @retval None |
mbed_official | 610:813dcc80987e | 733 | */ |
mbed_official | 610:813dcc80987e | 734 | #define __HAL_RCC_PLLSAI1_DIVP_CONFIG(__PLLSAI1P__) \ |
mbed_official | 610:813dcc80987e | 735 | MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P, ((__PLLSAI1P__) >> 4U) << 17U) |
mbed_official | 610:813dcc80987e | 736 | |
mbed_official | 610:813dcc80987e | 737 | /** @brief Macro to configure the PLLSAI1 clock division factor Q. |
mbed_official | 610:813dcc80987e | 738 | * |
mbed_official | 610:813dcc80987e | 739 | * @note This function must be used only when the PLLSAI1 is disabled. |
mbed_official | 610:813dcc80987e | 740 | * @note PLLSAI1 clock source is common with the main PLL (configured through |
mbed_official | 610:813dcc80987e | 741 | * __HAL_RCC_PLL_CONFIG() macro) |
mbed_official | 610:813dcc80987e | 742 | * |
mbed_official | 610:813dcc80987e | 743 | * @param __PLLSAI1Q__: specifies the division factor for USB/RNG/SDMMC1 clock. |
mbed_official | 610:813dcc80987e | 744 | * This parameter must be in the range (2, 4, 6 or 8). |
mbed_official | 610:813dcc80987e | 745 | * Use to set USB/RNG/SDMMC1 clock frequency = f(PLLSAI1) / PLLSAI1Q |
mbed_official | 610:813dcc80987e | 746 | * |
mbed_official | 610:813dcc80987e | 747 | * @retval None |
mbed_official | 610:813dcc80987e | 748 | */ |
mbed_official | 610:813dcc80987e | 749 | #define __HAL_RCC_PLLSAI1_DIVQ_CONFIG(__PLLSAI1Q__) \ |
mbed_official | 610:813dcc80987e | 750 | MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q, (((__PLLSAI1Q__) >> 1U) - 1) << 21U) |
mbed_official | 610:813dcc80987e | 751 | |
mbed_official | 610:813dcc80987e | 752 | /** @brief Macro to configure the PLLSAI1 clock division factor R. |
mbed_official | 610:813dcc80987e | 753 | * |
mbed_official | 610:813dcc80987e | 754 | * @note This function must be used only when the PLLSAI1 is disabled. |
mbed_official | 610:813dcc80987e | 755 | * @note PLLSAI1 clock source is common with the main PLL (configured through |
mbed_official | 610:813dcc80987e | 756 | * __HAL_RCC_PLL_CONFIG() macro) |
mbed_official | 610:813dcc80987e | 757 | * |
mbed_official | 610:813dcc80987e | 758 | * @param __PLLSAI1R__: specifies the division factor for ADC clock. |
mbed_official | 610:813dcc80987e | 759 | * This parameter must be in the range (2, 4, 6 or 8) |
mbed_official | 610:813dcc80987e | 760 | * Use to set ADC clock frequency = f(PLLSAI1) / PLLSAI1R |
mbed_official | 610:813dcc80987e | 761 | * |
mbed_official | 610:813dcc80987e | 762 | * @retval None |
mbed_official | 610:813dcc80987e | 763 | */ |
mbed_official | 610:813dcc80987e | 764 | #define __HAL_RCC_PLLSAI1_DIVR_CONFIG(__PLLSAI1R__) \ |
mbed_official | 610:813dcc80987e | 765 | MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R, (((__PLLSAI1R__) >> 1U) - 1) << 25U) |
mbed_official | 610:813dcc80987e | 766 | |
mbed_official | 610:813dcc80987e | 767 | /** |
mbed_official | 610:813dcc80987e | 768 | * @brief Macros to enable or disable the PLLSAI1. |
mbed_official | 610:813dcc80987e | 769 | * @note The PLLSAI1 is disabled by hardware when entering STOP and STANDBY modes. |
mbed_official | 610:813dcc80987e | 770 | * @retval None |
mbed_official | 610:813dcc80987e | 771 | */ |
mbed_official | 610:813dcc80987e | 772 | |
mbed_official | 610:813dcc80987e | 773 | #define __HAL_RCC_PLLSAI1_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON) |
mbed_official | 610:813dcc80987e | 774 | |
mbed_official | 610:813dcc80987e | 775 | #define __HAL_RCC_PLLSAI1_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON) |
mbed_official | 610:813dcc80987e | 776 | |
mbed_official | 610:813dcc80987e | 777 | /** |
mbed_official | 610:813dcc80987e | 778 | * @brief Macros to enable or disable each clock output (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1). |
mbed_official | 610:813dcc80987e | 779 | * @note Enabling and disabling those clocks can be done without the need to stop the PLL. |
mbed_official | 610:813dcc80987e | 780 | * This is mainly used to save Power. |
mbed_official | 610:813dcc80987e | 781 | * @param __PLLSAI1_CLOCKOUT__: specifies the PLLSAI1 clock to be output. |
mbed_official | 610:813dcc80987e | 782 | * This parameter can be one or a combination of the following values: |
mbed_official | 610:813dcc80987e | 783 | * @arg RCC_PLLSAI1_SAI1CLK: This clock is used to generate an accurate clock to achieve |
mbed_official | 610:813dcc80987e | 784 | * high-quality audio performance on SAI interface in case. |
mbed_official | 610:813dcc80987e | 785 | * @arg RCC_PLLSAI1_USB2CLK: This clock is used to generate the clock for the USB OTG FS (48 MHz), |
mbed_official | 610:813dcc80987e | 786 | * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz). |
mbed_official | 610:813dcc80987e | 787 | * @arg RCC_PLLSAI1_ADC1CLK: Clock used to clock ADC peripheral. |
mbed_official | 610:813dcc80987e | 788 | * @retval None |
mbed_official | 610:813dcc80987e | 789 | */ |
mbed_official | 610:813dcc80987e | 790 | |
mbed_official | 610:813dcc80987e | 791 | #define __HAL_RCC_PLLSAI1CLKOUT_ENABLE(__PLLSAI1_CLOCKOUT__) SET_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) |
mbed_official | 610:813dcc80987e | 792 | |
mbed_official | 610:813dcc80987e | 793 | #define __HAL_RCC_PLLSAI1CLKOUT_DISABLE(__PLLSAI1_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) |
mbed_official | 610:813dcc80987e | 794 | |
mbed_official | 610:813dcc80987e | 795 | /** |
mbed_official | 610:813dcc80987e | 796 | * @brief Macro to get clock output enable status (PLLSAI1_SAI1, PLLSAI1_USB2 and PLLSAI1_ADC1). |
mbed_official | 610:813dcc80987e | 797 | * @param __PLLSAI1_CLOCKOUT__: specifies the PLLSAI1 clock to be output. |
mbed_official | 610:813dcc80987e | 798 | * This parameter can be one of the following values: |
mbed_official | 610:813dcc80987e | 799 | * @arg RCC_PLLSAI1_SAI1CLK: This clock is used to generate an accurate clock to achieve |
mbed_official | 610:813dcc80987e | 800 | * high-quality audio performance on SAI interface in case. |
mbed_official | 610:813dcc80987e | 801 | * @arg RCC_PLLSAI1_USB2CLK: This clock is used to generate the clock for the USB OTG FS (48 MHz), |
mbed_official | 610:813dcc80987e | 802 | * the random number generator (<=48 MHz) and the SDIO (<= 48 MHz). |
mbed_official | 610:813dcc80987e | 803 | * @arg RCC_PLLSAI1_ADC1CLK: Clock used to clock ADC peripheral. |
mbed_official | 610:813dcc80987e | 804 | * @retval SET / RESET |
mbed_official | 610:813dcc80987e | 805 | */ |
mbed_official | 610:813dcc80987e | 806 | #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) |
mbed_official | 610:813dcc80987e | 807 | |
mbed_official | 610:813dcc80987e | 808 | /** |
mbed_official | 610:813dcc80987e | 809 | * @brief Macro to configure the PLLSAI2 clock multiplication and division factors. |
mbed_official | 610:813dcc80987e | 810 | * |
mbed_official | 610:813dcc80987e | 811 | * @note This function must be used only when the PLLSAI2 is disabled. |
mbed_official | 610:813dcc80987e | 812 | * @note PLLSAI2 clock source is common with the main PLL (configured through |
mbed_official | 610:813dcc80987e | 813 | * __HAL_RCC_PLL_CONFIG() macro) |
mbed_official | 610:813dcc80987e | 814 | * |
mbed_official | 610:813dcc80987e | 815 | * @param __PLLSAI2N__: specifies the multiplication factor for PLLSAI2 VCO output clock. |
mbed_official | 610:813dcc80987e | 816 | * This parameter must be a number between 8 and 86. |
mbed_official | 610:813dcc80987e | 817 | * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO |
mbed_official | 610:813dcc80987e | 818 | * output frequency is between 64 and 344 MHz. |
mbed_official | 610:813dcc80987e | 819 | * |
mbed_official | 610:813dcc80987e | 820 | * @param __PLLSAI2P__: specifies the division factor for SAI clock. |
mbed_official | 610:813dcc80987e | 821 | * This parameter must be a number in the range (7 or 17). |
mbed_official | 610:813dcc80987e | 822 | * |
mbed_official | 610:813dcc80987e | 823 | * |
mbed_official | 610:813dcc80987e | 824 | * @param __PLLSAI2R__: specifies the division factor for SAR ADC clock. |
mbed_official | 610:813dcc80987e | 825 | * This parameter must be in the range (2, 4, 6 or 8) |
mbed_official | 610:813dcc80987e | 826 | * |
mbed_official | 610:813dcc80987e | 827 | * @retval None |
mbed_official | 610:813dcc80987e | 828 | */ |
mbed_official | 610:813dcc80987e | 829 | |
mbed_official | 610:813dcc80987e | 830 | #define __HAL_RCC_PLLSAI2_CONFIG(__PLLSAI2N__, __PLLSAI2P__, __PLLSAI2R__) \ |
mbed_official | 610:813dcc80987e | 831 | WRITE_REG(RCC->PLLSAI2CFGR, ((__PLLSAI2N__) << 8U) | (((__PLLSAI2P__) >> 4U) << 17U) | \ |
mbed_official | 610:813dcc80987e | 832 | ((((__PLLSAI2R__) >> 1U) - 1) << 25U)) |
mbed_official | 610:813dcc80987e | 833 | |
mbed_official | 610:813dcc80987e | 834 | /** |
mbed_official | 610:813dcc80987e | 835 | * @brief Macro to configure the PLLSAI2 clock multiplication factor N. |
mbed_official | 610:813dcc80987e | 836 | * |
mbed_official | 610:813dcc80987e | 837 | * @note This function must be used only when the PLLSAI2 is disabled. |
mbed_official | 610:813dcc80987e | 838 | * @note PLLSAI2 clock source is common with the main PLL (configured through |
mbed_official | 610:813dcc80987e | 839 | * __HAL_RCC_PLL_CONFIG() macro) |
mbed_official | 610:813dcc80987e | 840 | * |
mbed_official | 610:813dcc80987e | 841 | * @param __PLLSAI2N__: specifies the multiplication factor for PLLSAI2 VCO output clock. |
mbed_official | 610:813dcc80987e | 842 | * This parameter must be a number between 8 and 86. |
mbed_official | 610:813dcc80987e | 843 | * @note You have to set the PLLSAI2N parameter correctly to ensure that the VCO |
mbed_official | 610:813dcc80987e | 844 | * output frequency is between 64 and 344 MHz. |
mbed_official | 610:813dcc80987e | 845 | * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLSAI2N |
mbed_official | 610:813dcc80987e | 846 | * |
mbed_official | 610:813dcc80987e | 847 | * @retval None |
mbed_official | 610:813dcc80987e | 848 | */ |
mbed_official | 610:813dcc80987e | 849 | #define __HAL_RCC_PLLSAI2_MULN_CONFIG(__PLLSAI2N__) \ |
mbed_official | 610:813dcc80987e | 850 | MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N, (__PLLSAI2N__) << 8U) |
mbed_official | 610:813dcc80987e | 851 | |
mbed_official | 610:813dcc80987e | 852 | /** @brief Macro to configure the PLLSAI2 clock division factor P. |
mbed_official | 610:813dcc80987e | 853 | * |
mbed_official | 610:813dcc80987e | 854 | * @note This function must be used only when the PLLSAI2 is disabled. |
mbed_official | 610:813dcc80987e | 855 | * @note PLLSAI2 clock source is common with the main PLL (configured through |
mbed_official | 610:813dcc80987e | 856 | * __HAL_RCC_PLL_CONFIG() macro) |
mbed_official | 610:813dcc80987e | 857 | * |
mbed_official | 610:813dcc80987e | 858 | * @param __PLLSAI2P__: specifies the division factor. |
mbed_official | 610:813dcc80987e | 859 | * This parameter must be a number in the range (7 or 17). |
mbed_official | 610:813dcc80987e | 860 | * Use to set SAI2 clock frequency = f(PLLSAI2) / __PLLSAI2P__ |
mbed_official | 610:813dcc80987e | 861 | * |
mbed_official | 610:813dcc80987e | 862 | * @retval None |
mbed_official | 610:813dcc80987e | 863 | */ |
mbed_official | 610:813dcc80987e | 864 | #define __HAL_RCC_PLLSAI2_DIVP_CONFIG(__PLLSAI2P__) \ |
mbed_official | 610:813dcc80987e | 865 | MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P, ((__PLLSAI2P__) >> 4U) << 17U) |
mbed_official | 610:813dcc80987e | 866 | |
mbed_official | 610:813dcc80987e | 867 | /** @brief Macro to configure the PLLSAI2 clock division factor R. |
mbed_official | 610:813dcc80987e | 868 | * |
mbed_official | 610:813dcc80987e | 869 | * @note This function must be used only when the PLLSAI2 is disabled. |
mbed_official | 610:813dcc80987e | 870 | * @note PLLSAI1 clock source is common with the main PLL (configured through |
mbed_official | 610:813dcc80987e | 871 | * __HAL_RCC_PLL_CONFIG() macro) |
mbed_official | 610:813dcc80987e | 872 | * |
mbed_official | 610:813dcc80987e | 873 | * @param __PLLSAI2R__: specifies the division factor. |
mbed_official | 610:813dcc80987e | 874 | * This parameter must be in the range (2, 4, 6 or 8). |
mbed_official | 610:813dcc80987e | 875 | * Use to set ADC clock frequency = f(PLLSAI2) / __PLLSAI2Q__ |
mbed_official | 610:813dcc80987e | 876 | * |
mbed_official | 610:813dcc80987e | 877 | * @retval None |
mbed_official | 610:813dcc80987e | 878 | */ |
mbed_official | 610:813dcc80987e | 879 | #define __HAL_RCC_PLLSAI2_DIVR_CONFIG(__PLLSAI2R__) \ |
mbed_official | 610:813dcc80987e | 880 | MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R, (((__PLLSAI2R__) >> 1U) - 1) << 25U) |
mbed_official | 610:813dcc80987e | 881 | |
mbed_official | 610:813dcc80987e | 882 | /** |
mbed_official | 610:813dcc80987e | 883 | * @brief Macros to enable or disable the PLLSAI2. |
mbed_official | 610:813dcc80987e | 884 | * @note The PLLSAI2 is disabled by hardware when entering STOP and STANDBY modes. |
mbed_official | 610:813dcc80987e | 885 | * @retval None |
mbed_official | 610:813dcc80987e | 886 | */ |
mbed_official | 610:813dcc80987e | 887 | |
mbed_official | 610:813dcc80987e | 888 | #define __HAL_RCC_PLLSAI2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON) |
mbed_official | 610:813dcc80987e | 889 | |
mbed_official | 610:813dcc80987e | 890 | #define __HAL_RCC_PLLSAI2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON) |
mbed_official | 610:813dcc80987e | 891 | |
mbed_official | 610:813dcc80987e | 892 | /** |
mbed_official | 610:813dcc80987e | 893 | * @brief Macros to enable or disable each clock output (PLLSAI2_SAI2 and PLLSAI2_ADC2). |
mbed_official | 610:813dcc80987e | 894 | * @note Enabling and disabling those clocks can be done without the need to stop the PLL. |
mbed_official | 610:813dcc80987e | 895 | * This is mainly used to save Power. |
mbed_official | 610:813dcc80987e | 896 | * @param __PLLSAI2_CLOCKOUT__: specifies the PLLSAI2 clock to be output. |
mbed_official | 610:813dcc80987e | 897 | * This parameter can be one or a combination of the following values: |
mbed_official | 610:813dcc80987e | 898 | * @arg RCC_PLLSAI2_SAI2CLK: This clock is used to generate an accurate clock to achieve |
mbed_official | 610:813dcc80987e | 899 | * high-quality audio performance on SAI interface in case. |
mbed_official | 610:813dcc80987e | 900 | * @arg RCC_PLLSAI2_ADC2CLK: Clock used to clock ADC peripheral. |
mbed_official | 610:813dcc80987e | 901 | * @retval None |
mbed_official | 610:813dcc80987e | 902 | */ |
mbed_official | 610:813dcc80987e | 903 | |
mbed_official | 610:813dcc80987e | 904 | #define __HAL_RCC_PLLSAI2CLKOUT_ENABLE(__PLLSAI2_CLOCKOUT__) SET_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) |
mbed_official | 610:813dcc80987e | 905 | |
mbed_official | 610:813dcc80987e | 906 | #define __HAL_RCC_PLLSAI2CLKOUT_DISABLE(__PLLSAI2_CLOCKOUT__) CLEAR_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) |
mbed_official | 610:813dcc80987e | 907 | |
mbed_official | 610:813dcc80987e | 908 | /** |
mbed_official | 610:813dcc80987e | 909 | * @brief Macro to get clock output enable status (PLLSAI2_SAI2 and PLLSAI2_ADC2). |
mbed_official | 610:813dcc80987e | 910 | * @param __PLLSAI2_CLOCKOUT__: specifies the PLLSAI2 clock to be output. |
mbed_official | 610:813dcc80987e | 911 | * This parameter can be one of the following values: |
mbed_official | 610:813dcc80987e | 912 | * @arg RCC_PLLSAI2_SAI2CLK: This clock is used to generate an accurate clock to achieve |
mbed_official | 610:813dcc80987e | 913 | * high-quality audio performance on SAI interface in case. |
mbed_official | 610:813dcc80987e | 914 | * @arg RCC_PLLSAI2_ADC2CLK: Clock used to clock ADC peripheral. |
mbed_official | 610:813dcc80987e | 915 | * @retval SET / RESET |
mbed_official | 610:813dcc80987e | 916 | */ |
mbed_official | 610:813dcc80987e | 917 | #define __HAL_RCC_GET_PLLSAI2CLKOUT_CONFIG(__PLLSAI2_CLOCKOUT__) READ_BIT(RCC->PLLSAI2CFGR, (__PLLSAI2_CLOCKOUT__)) |
mbed_official | 610:813dcc80987e | 918 | |
mbed_official | 610:813dcc80987e | 919 | /** |
mbed_official | 610:813dcc80987e | 920 | * @brief Macro to configure the SAI1 clock source. |
mbed_official | 610:813dcc80987e | 921 | * @param __SAI1_CLKSOURCE__: defines the SAI1 clock source. This clock is derived |
mbed_official | 610:813dcc80987e | 922 | * from the PLLSAI1, system PLL or external clock (through a dedicated pin). |
mbed_official | 610:813dcc80987e | 923 | * This parameter can be one of the following values: |
mbed_official | 610:813dcc80987e | 924 | * @arg RCC_SAI1CLKSOURCE_PLLSAI1: SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK) |
mbed_official | 610:813dcc80987e | 925 | * @arg RCC_SAI1CLKSOURCE_PLLSAI2: SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) |
mbed_official | 610:813dcc80987e | 926 | * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL "P" clock (PLLSAI3CLK) |
mbed_official | 610:813dcc80987e | 927 | * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock (SAI1_EXTCLK) |
mbed_official | 610:813dcc80987e | 928 | * @retval None |
mbed_official | 610:813dcc80987e | 929 | */ |
mbed_official | 610:813dcc80987e | 930 | #define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ |
mbed_official | 610:813dcc80987e | 931 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__)) |
mbed_official | 610:813dcc80987e | 932 | |
mbed_official | 610:813dcc80987e | 933 | /** @brief Macro to get the SAI1 clock source. |
mbed_official | 610:813dcc80987e | 934 | * @retval The clock source can be one of the following values: |
mbed_official | 610:813dcc80987e | 935 | * @arg RCC_SAI1CLKSOURCE_PLLSAI1: SAI1 clock = PLLSAI1 "P" clock (PLLSAI1CLK) |
mbed_official | 610:813dcc80987e | 936 | * @arg RCC_SAI1CLKSOURCE_PLLSAI2: SAI1 clock = PLLSAI2 "P" clock (PLLSAI2CLK) |
mbed_official | 610:813dcc80987e | 937 | * @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL "P" clock (PLLSAI3CLK) |
mbed_official | 610:813dcc80987e | 938 | * @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock (SAI1_EXTCLK) |
mbed_official | 610:813dcc80987e | 939 | */ |
mbed_official | 610:813dcc80987e | 940 | #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))) |
mbed_official | 610:813dcc80987e | 941 | |
mbed_official | 610:813dcc80987e | 942 | /** |
mbed_official | 610:813dcc80987e | 943 | * @brief Macro to configure the SAI2 clock source. |
mbed_official | 610:813dcc80987e | 944 | * @param __SAI2_CLKSOURCE__: defines the SAI2 clock source. This clock is derived |
mbed_official | 610:813dcc80987e | 945 | * from the PLLSAI2, system PLL or external clock (through a dedicated pin). |
mbed_official | 610:813dcc80987e | 946 | * This parameter can be one of the following values: |
mbed_official | 610:813dcc80987e | 947 | * @arg RCC_SAI2CLKSOURCE_PLLSAI1: SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK) |
mbed_official | 610:813dcc80987e | 948 | * @arg RCC_SAI2CLKSOURCE_PLLSAI2: SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) |
mbed_official | 610:813dcc80987e | 949 | * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL "P" clock (PLLSAI3CLK) |
mbed_official | 610:813dcc80987e | 950 | * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock (SAI2_EXTCLK) |
mbed_official | 610:813dcc80987e | 951 | * @retval None |
mbed_official | 610:813dcc80987e | 952 | */ |
mbed_official | 610:813dcc80987e | 953 | #define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ |
mbed_official | 610:813dcc80987e | 954 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__)) |
mbed_official | 610:813dcc80987e | 955 | |
mbed_official | 610:813dcc80987e | 956 | /** @brief Macro to get the SAI2 clock source. |
mbed_official | 610:813dcc80987e | 957 | * @retval The clock source can be one of the following values: |
mbed_official | 610:813dcc80987e | 958 | * @arg RCC_SAI2CLKSOURCE_PLLSAI1: SAI2 clock = PLLSAI1 "P" clock (PLLSAI1CLK) |
mbed_official | 610:813dcc80987e | 959 | * @arg RCC_SAI2CLKSOURCE_PLLSAI2: SAI2 clock = PLLSAI2 "P" clock (PLLSAI2CLK) |
mbed_official | 610:813dcc80987e | 960 | * @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL "P" clock (PLLSAI3CLK) |
mbed_official | 610:813dcc80987e | 961 | * @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock (SAI2_EXTCLK) |
mbed_official | 610:813dcc80987e | 962 | */ |
mbed_official | 610:813dcc80987e | 963 | #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI2SEL))) |
mbed_official | 610:813dcc80987e | 964 | |
mbed_official | 610:813dcc80987e | 965 | /** @brief Macro to configure the I2C1 clock (I2C1CLK). |
mbed_official | 610:813dcc80987e | 966 | * |
mbed_official | 610:813dcc80987e | 967 | * @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source. |
mbed_official | 610:813dcc80987e | 968 | * This parameter can be one of the following values: |
mbed_official | 610:813dcc80987e | 969 | * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock |
mbed_official | 610:813dcc80987e | 970 | * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock |
mbed_official | 610:813dcc80987e | 971 | * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock |
mbed_official | 610:813dcc80987e | 972 | * @retval None |
mbed_official | 610:813dcc80987e | 973 | */ |
mbed_official | 610:813dcc80987e | 974 | #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ |
mbed_official | 610:813dcc80987e | 975 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) |
mbed_official | 610:813dcc80987e | 976 | |
mbed_official | 610:813dcc80987e | 977 | /** @brief Macro to get the I2C1 clock source. |
mbed_official | 610:813dcc80987e | 978 | * @retval The clock source can be one of the following values: |
mbed_official | 610:813dcc80987e | 979 | * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock |
mbed_official | 610:813dcc80987e | 980 | * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock |
mbed_official | 610:813dcc80987e | 981 | * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock |
mbed_official | 610:813dcc80987e | 982 | */ |
mbed_official | 610:813dcc80987e | 983 | #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))) |
mbed_official | 610:813dcc80987e | 984 | |
mbed_official | 610:813dcc80987e | 985 | /** @brief Macro to configure the I2C2 clock (I2C2CLK). |
mbed_official | 610:813dcc80987e | 986 | * |
mbed_official | 610:813dcc80987e | 987 | * @param __I2C2_CLKSOURCE__: specifies the I2C2 clock source. |
mbed_official | 610:813dcc80987e | 988 | * This parameter can be one of the following values: |
mbed_official | 610:813dcc80987e | 989 | * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock |
mbed_official | 610:813dcc80987e | 990 | * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock |
mbed_official | 610:813dcc80987e | 991 | * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock |
mbed_official | 610:813dcc80987e | 992 | * @retval None |
mbed_official | 610:813dcc80987e | 993 | */ |
mbed_official | 610:813dcc80987e | 994 | #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ |
mbed_official | 610:813dcc80987e | 995 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) |
mbed_official | 610:813dcc80987e | 996 | |
mbed_official | 610:813dcc80987e | 997 | /** @brief Macro to get the I2C2 clock source. |
mbed_official | 610:813dcc80987e | 998 | * @retval The clock source can be one of the following values: |
mbed_official | 610:813dcc80987e | 999 | * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock |
mbed_official | 610:813dcc80987e | 1000 | * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock |
mbed_official | 610:813dcc80987e | 1001 | * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock |
mbed_official | 610:813dcc80987e | 1002 | */ |
mbed_official | 610:813dcc80987e | 1003 | #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))) |
mbed_official | 610:813dcc80987e | 1004 | |
mbed_official | 610:813dcc80987e | 1005 | /** @brief Macro to configure the I2C3 clock (I2C3CLK). |
mbed_official | 610:813dcc80987e | 1006 | * |
mbed_official | 610:813dcc80987e | 1007 | * @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source. |
mbed_official | 610:813dcc80987e | 1008 | * This parameter can be one of the following values: |
mbed_official | 610:813dcc80987e | 1009 | * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock |
mbed_official | 610:813dcc80987e | 1010 | * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock |
mbed_official | 610:813dcc80987e | 1011 | * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock |
mbed_official | 610:813dcc80987e | 1012 | * @retval None |
mbed_official | 610:813dcc80987e | 1013 | */ |
mbed_official | 610:813dcc80987e | 1014 | #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ |
mbed_official | 610:813dcc80987e | 1015 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) |
mbed_official | 610:813dcc80987e | 1016 | |
mbed_official | 610:813dcc80987e | 1017 | /** @brief Macro to get the I2C3 clock source. |
mbed_official | 610:813dcc80987e | 1018 | * @retval The clock source can be one of the following values: |
mbed_official | 610:813dcc80987e | 1019 | * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock |
mbed_official | 610:813dcc80987e | 1020 | * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock |
mbed_official | 610:813dcc80987e | 1021 | * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock |
mbed_official | 610:813dcc80987e | 1022 | */ |
mbed_official | 610:813dcc80987e | 1023 | #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))) |
mbed_official | 610:813dcc80987e | 1024 | |
mbed_official | 610:813dcc80987e | 1025 | /** @brief Macro to configure the USART1 clock (USART1CLK). |
mbed_official | 610:813dcc80987e | 1026 | * |
mbed_official | 610:813dcc80987e | 1027 | * @param __USART1_CLKSOURCE__: specifies the USART1 clock source. |
mbed_official | 610:813dcc80987e | 1028 | * This parameter can be one of the following values: |
mbed_official | 610:813dcc80987e | 1029 | * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock |
mbed_official | 610:813dcc80987e | 1030 | * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock |
mbed_official | 610:813dcc80987e | 1031 | * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock |
mbed_official | 610:813dcc80987e | 1032 | * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock |
mbed_official | 610:813dcc80987e | 1033 | * @retval None |
mbed_official | 610:813dcc80987e | 1034 | */ |
mbed_official | 610:813dcc80987e | 1035 | #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ |
mbed_official | 610:813dcc80987e | 1036 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) |
mbed_official | 610:813dcc80987e | 1037 | |
mbed_official | 610:813dcc80987e | 1038 | /** @brief Macro to get the USART1 clock source. |
mbed_official | 610:813dcc80987e | 1039 | * @retval The clock source can be one of the following values: |
mbed_official | 610:813dcc80987e | 1040 | * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock |
mbed_official | 610:813dcc80987e | 1041 | * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock |
mbed_official | 610:813dcc80987e | 1042 | * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock |
mbed_official | 610:813dcc80987e | 1043 | * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock |
mbed_official | 610:813dcc80987e | 1044 | */ |
mbed_official | 610:813dcc80987e | 1045 | #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))) |
mbed_official | 610:813dcc80987e | 1046 | |
mbed_official | 610:813dcc80987e | 1047 | /** @brief Macro to configure the USART2 clock (USART2CLK). |
mbed_official | 610:813dcc80987e | 1048 | * |
mbed_official | 610:813dcc80987e | 1049 | * @param __USART2_CLKSOURCE__: specifies the USART2 clock source. |
mbed_official | 610:813dcc80987e | 1050 | * This parameter can be one of the following values: |
mbed_official | 610:813dcc80987e | 1051 | * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock |
mbed_official | 610:813dcc80987e | 1052 | * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock |
mbed_official | 610:813dcc80987e | 1053 | * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock |
mbed_official | 610:813dcc80987e | 1054 | * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock |
mbed_official | 610:813dcc80987e | 1055 | * @retval None |
mbed_official | 610:813dcc80987e | 1056 | */ |
mbed_official | 610:813dcc80987e | 1057 | #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ |
mbed_official | 610:813dcc80987e | 1058 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) |
mbed_official | 610:813dcc80987e | 1059 | |
mbed_official | 610:813dcc80987e | 1060 | /** @brief Macro to get the USART2 clock source. |
mbed_official | 610:813dcc80987e | 1061 | * @retval The clock source can be one of the following values: |
mbed_official | 610:813dcc80987e | 1062 | * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock |
mbed_official | 610:813dcc80987e | 1063 | * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock |
mbed_official | 610:813dcc80987e | 1064 | * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock |
mbed_official | 610:813dcc80987e | 1065 | * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock |
mbed_official | 610:813dcc80987e | 1066 | */ |
mbed_official | 610:813dcc80987e | 1067 | #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))) |
mbed_official | 610:813dcc80987e | 1068 | |
mbed_official | 610:813dcc80987e | 1069 | /** @brief Macro to configure the USART3 clock (USART3CLK). |
mbed_official | 610:813dcc80987e | 1070 | * |
mbed_official | 610:813dcc80987e | 1071 | * @param __USART3_CLKSOURCE__: specifies the USART3 clock source. |
mbed_official | 610:813dcc80987e | 1072 | * This parameter can be one of the following values: |
mbed_official | 610:813dcc80987e | 1073 | * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock |
mbed_official | 610:813dcc80987e | 1074 | * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock |
mbed_official | 610:813dcc80987e | 1075 | * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock |
mbed_official | 610:813dcc80987e | 1076 | * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock |
mbed_official | 610:813dcc80987e | 1077 | * @retval None |
mbed_official | 610:813dcc80987e | 1078 | */ |
mbed_official | 610:813dcc80987e | 1079 | #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ |
mbed_official | 610:813dcc80987e | 1080 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) |
mbed_official | 610:813dcc80987e | 1081 | |
mbed_official | 610:813dcc80987e | 1082 | /** @brief Macro to get the USART3 clock source. |
mbed_official | 610:813dcc80987e | 1083 | * @retval The clock source can be one of the following values: |
mbed_official | 610:813dcc80987e | 1084 | * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock |
mbed_official | 610:813dcc80987e | 1085 | * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock |
mbed_official | 610:813dcc80987e | 1086 | * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock |
mbed_official | 610:813dcc80987e | 1087 | * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock |
mbed_official | 610:813dcc80987e | 1088 | */ |
mbed_official | 610:813dcc80987e | 1089 | #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))) |
mbed_official | 610:813dcc80987e | 1090 | |
mbed_official | 610:813dcc80987e | 1091 | /** @brief Macro to configure the UART4 clock (UART4CLK). |
mbed_official | 610:813dcc80987e | 1092 | * |
mbed_official | 610:813dcc80987e | 1093 | * @param __UART4_CLKSOURCE__: specifies the UART4 clock source. |
mbed_official | 610:813dcc80987e | 1094 | * This parameter can be one of the following values: |
mbed_official | 610:813dcc80987e | 1095 | * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock |
mbed_official | 610:813dcc80987e | 1096 | * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock |
mbed_official | 610:813dcc80987e | 1097 | * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock |
mbed_official | 610:813dcc80987e | 1098 | * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock |
mbed_official | 610:813dcc80987e | 1099 | * @retval None |
mbed_official | 610:813dcc80987e | 1100 | */ |
mbed_official | 610:813dcc80987e | 1101 | #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ |
mbed_official | 610:813dcc80987e | 1102 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) |
mbed_official | 610:813dcc80987e | 1103 | |
mbed_official | 610:813dcc80987e | 1104 | /** @brief Macro to get the UART4 clock source. |
mbed_official | 610:813dcc80987e | 1105 | * @retval The clock source can be one of the following values: |
mbed_official | 610:813dcc80987e | 1106 | * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock |
mbed_official | 610:813dcc80987e | 1107 | * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock |
mbed_official | 610:813dcc80987e | 1108 | * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock |
mbed_official | 610:813dcc80987e | 1109 | * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock |
mbed_official | 610:813dcc80987e | 1110 | */ |
mbed_official | 610:813dcc80987e | 1111 | #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))) |
mbed_official | 610:813dcc80987e | 1112 | |
mbed_official | 610:813dcc80987e | 1113 | /** @brief Macro to configure the UART5 clock (UART5CLK). |
mbed_official | 610:813dcc80987e | 1114 | * |
mbed_official | 610:813dcc80987e | 1115 | * @param __UART5_CLKSOURCE__: specifies the UART5 clock source. |
mbed_official | 610:813dcc80987e | 1116 | * This parameter can be one of the following values: |
mbed_official | 610:813dcc80987e | 1117 | * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock |
mbed_official | 610:813dcc80987e | 1118 | * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock |
mbed_official | 610:813dcc80987e | 1119 | * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock |
mbed_official | 610:813dcc80987e | 1120 | * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock |
mbed_official | 610:813dcc80987e | 1121 | * @retval None |
mbed_official | 610:813dcc80987e | 1122 | */ |
mbed_official | 610:813dcc80987e | 1123 | #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ |
mbed_official | 610:813dcc80987e | 1124 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) |
mbed_official | 610:813dcc80987e | 1125 | |
mbed_official | 610:813dcc80987e | 1126 | /** @brief Macro to get the UART5 clock source. |
mbed_official | 610:813dcc80987e | 1127 | * @retval The clock source can be one of the following values: |
mbed_official | 610:813dcc80987e | 1128 | * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock |
mbed_official | 610:813dcc80987e | 1129 | * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock |
mbed_official | 610:813dcc80987e | 1130 | * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock |
mbed_official | 610:813dcc80987e | 1131 | * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock |
mbed_official | 610:813dcc80987e | 1132 | */ |
mbed_official | 610:813dcc80987e | 1133 | #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL))) |
mbed_official | 610:813dcc80987e | 1134 | |
mbed_official | 610:813dcc80987e | 1135 | /** @brief Macro to configure the LPUART1 clock (LPUART1CLK). |
mbed_official | 610:813dcc80987e | 1136 | * |
mbed_official | 610:813dcc80987e | 1137 | * @param __LPUART1_CLKSOURCE__: specifies the LPUART1 clock source. |
mbed_official | 610:813dcc80987e | 1138 | * This parameter can be one of the following values: |
mbed_official | 610:813dcc80987e | 1139 | * @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock |
mbed_official | 610:813dcc80987e | 1140 | * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock |
mbed_official | 610:813dcc80987e | 1141 | * @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock |
mbed_official | 610:813dcc80987e | 1142 | * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock |
mbed_official | 610:813dcc80987e | 1143 | * @retval None |
mbed_official | 610:813dcc80987e | 1144 | */ |
mbed_official | 610:813dcc80987e | 1145 | #define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ |
mbed_official | 610:813dcc80987e | 1146 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) |
mbed_official | 610:813dcc80987e | 1147 | |
mbed_official | 610:813dcc80987e | 1148 | /** @brief Macro to get the LPUART1 clock source. |
mbed_official | 610:813dcc80987e | 1149 | * @retval The clock source can be one of the following values: |
mbed_official | 610:813dcc80987e | 1150 | * @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock |
mbed_official | 610:813dcc80987e | 1151 | * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock |
mbed_official | 610:813dcc80987e | 1152 | * @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock |
mbed_official | 610:813dcc80987e | 1153 | * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock |
mbed_official | 610:813dcc80987e | 1154 | */ |
mbed_official | 610:813dcc80987e | 1155 | #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))) |
mbed_official | 610:813dcc80987e | 1156 | |
mbed_official | 610:813dcc80987e | 1157 | /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). |
mbed_official | 610:813dcc80987e | 1158 | * |
mbed_official | 610:813dcc80987e | 1159 | * @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source. |
mbed_official | 610:813dcc80987e | 1160 | * This parameter can be one of the following values: |
mbed_official | 610:813dcc80987e | 1161 | * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock |
mbed_official | 610:813dcc80987e | 1162 | * @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPTIM1 clock |
mbed_official | 610:813dcc80987e | 1163 | * @arg RCC_LPTIM1CLKSOURCE_HSI : LSI selected as LPTIM1 clock |
mbed_official | 610:813dcc80987e | 1164 | * @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPTIM1 clock |
mbed_official | 610:813dcc80987e | 1165 | * @retval None |
mbed_official | 610:813dcc80987e | 1166 | */ |
mbed_official | 610:813dcc80987e | 1167 | #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ |
mbed_official | 610:813dcc80987e | 1168 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) |
mbed_official | 610:813dcc80987e | 1169 | |
mbed_official | 610:813dcc80987e | 1170 | /** @brief Macro to get the LPTIM1 clock source. |
mbed_official | 610:813dcc80987e | 1171 | * @retval The clock source can be one of the following values: |
mbed_official | 610:813dcc80987e | 1172 | * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPUART1 clock |
mbed_official | 610:813dcc80987e | 1173 | * @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPUART1 clock |
mbed_official | 610:813dcc80987e | 1174 | * @arg RCC_LPTIM1CLKSOURCE_HSI : System Clock selected as LPUART1 clock |
mbed_official | 610:813dcc80987e | 1175 | * @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPUART1 clock |
mbed_official | 610:813dcc80987e | 1176 | */ |
mbed_official | 610:813dcc80987e | 1177 | #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))) |
mbed_official | 610:813dcc80987e | 1178 | |
mbed_official | 610:813dcc80987e | 1179 | /** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). |
mbed_official | 610:813dcc80987e | 1180 | * |
mbed_official | 610:813dcc80987e | 1181 | * @param __LPTIM2_CLKSOURCE__: specifies the LPTIM2 clock source. |
mbed_official | 610:813dcc80987e | 1182 | * This parameter can be one of the following values: |
mbed_official | 610:813dcc80987e | 1183 | * @arg RCC_LPTIM2CLKSOURCE_PCLK: PCLK selected as LPTIM2 clock |
mbed_official | 610:813dcc80987e | 1184 | * @arg RCC_LPTIM2CLKSOURCE_LSI : HSI selected as LPTIM2 clock |
mbed_official | 610:813dcc80987e | 1185 | * @arg RCC_LPTIM2CLKSOURCE_HSI : LSI selected as LPTIM2 clock |
mbed_official | 610:813dcc80987e | 1186 | * @arg RCC_LPTIM2CLKSOURCE_LSE : LSE selected as LPTIM2 clock |
mbed_official | 610:813dcc80987e | 1187 | * @retval None |
mbed_official | 610:813dcc80987e | 1188 | */ |
mbed_official | 610:813dcc80987e | 1189 | #define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ |
mbed_official | 610:813dcc80987e | 1190 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) |
mbed_official | 610:813dcc80987e | 1191 | |
mbed_official | 610:813dcc80987e | 1192 | /** @brief Macro to get the LPTIM2 clock source. |
mbed_official | 610:813dcc80987e | 1193 | * @retval The clock source can be one of the following values: |
mbed_official | 610:813dcc80987e | 1194 | * @arg RCC_LPTIM2CLKSOURCE_PCLK: PCLK selected as LPUART1 clock |
mbed_official | 610:813dcc80987e | 1195 | * @arg RCC_LPTIM2CLKSOURCE_LSI : HSI selected as LPUART1 clock |
mbed_official | 610:813dcc80987e | 1196 | * @arg RCC_LPTIM2CLKSOURCE_HSI : System Clock selected as LPUART1 clock |
mbed_official | 610:813dcc80987e | 1197 | * @arg RCC_LPTIM2CLKSOURCE_LSE : LSE selected as LPUART1 clock |
mbed_official | 610:813dcc80987e | 1198 | */ |
mbed_official | 610:813dcc80987e | 1199 | #define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM2SEL))) |
mbed_official | 610:813dcc80987e | 1200 | |
mbed_official | 610:813dcc80987e | 1201 | /** @brief Macro to configure the SDMMC1 clock. |
mbed_official | 610:813dcc80987e | 1202 | * |
mbed_official | 610:813dcc80987e | 1203 | * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. |
mbed_official | 610:813dcc80987e | 1204 | * |
mbed_official | 610:813dcc80987e | 1205 | * @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source. |
mbed_official | 610:813dcc80987e | 1206 | * This parameter can be one of the following values: |
mbed_official | 610:813dcc80987e | 1207 | * @arg RCC_SDMMC1CLKSOURCE_NONE: No clock selected as SDMMC1 clock |
mbed_official | 610:813dcc80987e | 1208 | * @arg RCC_SDMMC1CLKSOURCE_MSI: MSI selected as SDMMC1 clock |
mbed_official | 610:813dcc80987e | 1209 | * @arg RCC_SDMMC1CLKSOURCE_PLLSAI1: PLLSAI1 Clock selected as SDMMC1 clock |
mbed_official | 610:813dcc80987e | 1210 | * @arg RCC_SDMMC1CLKSOURCE_PLL: PLL Clock selected as SDMMC1 clock |
mbed_official | 610:813dcc80987e | 1211 | * @retval None |
mbed_official | 610:813dcc80987e | 1212 | */ |
mbed_official | 610:813dcc80987e | 1213 | #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ |
mbed_official | 610:813dcc80987e | 1214 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)) |
mbed_official | 610:813dcc80987e | 1215 | |
mbed_official | 610:813dcc80987e | 1216 | /** @brief Macro to get the SDMMC1 clock. |
mbed_official | 610:813dcc80987e | 1217 | * @retval The clock source can be one of the following values: |
mbed_official | 610:813dcc80987e | 1218 | * @arg RCC_SDMMC1CLKSOURCE_NONE: No clock selected as SDMMC1 clock |
mbed_official | 610:813dcc80987e | 1219 | * @arg RCC_SDMMC1CLKSOURCE_MSI: MSI selected as SDMMC1 clock |
mbed_official | 610:813dcc80987e | 1220 | * @arg RCC_SDMMC1CLKSOURCE_PLLSAI1: PLLSAI1 "Q" clock (PLL48M2CLK) selected as SDMMC1 clock |
mbed_official | 610:813dcc80987e | 1221 | * @arg RCC_SDMMC1CLKSOURCE_PLL: PLL "Q" clock (PLL48M1CLK) selected as SDMMC1 clock |
mbed_official | 610:813dcc80987e | 1222 | */ |
mbed_official | 610:813dcc80987e | 1223 | #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) |
mbed_official | 610:813dcc80987e | 1224 | |
mbed_official | 610:813dcc80987e | 1225 | /** @brief Macro to configure the RNG clock. |
mbed_official | 610:813dcc80987e | 1226 | * |
mbed_official | 610:813dcc80987e | 1227 | * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. |
mbed_official | 610:813dcc80987e | 1228 | * |
mbed_official | 610:813dcc80987e | 1229 | * @param __RNG_CLKSOURCE__: specifies the RNG clock source. |
mbed_official | 610:813dcc80987e | 1230 | * This parameter can be one of the following values: |
mbed_official | 610:813dcc80987e | 1231 | * @arg RCC_RNGCLKSOURCE_NONE: No clock selected as RNG clock |
mbed_official | 610:813dcc80987e | 1232 | * @arg RCC_RNGCLKSOURCE_MSI: MSI selected as RNG clock |
mbed_official | 610:813dcc80987e | 1233 | * @arg RCC_RNGCLKSOURCE_PLLSAI1: PLLSAI1 Clock selected as RNG clock |
mbed_official | 610:813dcc80987e | 1234 | * @arg RCC_RNGCLKSOURCE_PLL: PLL Clock selected as RNG clock |
mbed_official | 610:813dcc80987e | 1235 | * @retval None |
mbed_official | 610:813dcc80987e | 1236 | */ |
mbed_official | 610:813dcc80987e | 1237 | #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \ |
mbed_official | 610:813dcc80987e | 1238 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__RNG_CLKSOURCE__)) |
mbed_official | 610:813dcc80987e | 1239 | |
mbed_official | 610:813dcc80987e | 1240 | /** @brief Macro to get the RNG clock. |
mbed_official | 610:813dcc80987e | 1241 | * @retval The clock source can be one of the following values: |
mbed_official | 610:813dcc80987e | 1242 | * @arg RCC_RNGCLKSOURCE_NONE: No clock selected as RNG clock |
mbed_official | 610:813dcc80987e | 1243 | * @arg RCC_RNGCLKSOURCE_MSI: MSI selected as RNG clock |
mbed_official | 610:813dcc80987e | 1244 | * @arg RCC_RNGCLKSOURCE_PLLSAI1: PLLSAI1 "Q" clock (PLL48M2CLK) selected as RNG clock |
mbed_official | 610:813dcc80987e | 1245 | * @arg RCC_RNGCLKSOURCE_PLL: PLL "Q" clock (PLL48M1CLK) selected as RNG clock |
mbed_official | 610:813dcc80987e | 1246 | */ |
mbed_official | 610:813dcc80987e | 1247 | #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) |
mbed_official | 610:813dcc80987e | 1248 | |
mbed_official | 610:813dcc80987e | 1249 | #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) |
mbed_official | 610:813dcc80987e | 1250 | /** @brief Macro to configure the USB clock (USBCLK). |
mbed_official | 610:813dcc80987e | 1251 | * |
mbed_official | 610:813dcc80987e | 1252 | * @note USB, RNG and SDMMC1 peripherals share the same 48MHz clock source. |
mbed_official | 610:813dcc80987e | 1253 | * |
mbed_official | 610:813dcc80987e | 1254 | * @param __USB_CLKSOURCE__: specifies the USB clock source. |
mbed_official | 610:813dcc80987e | 1255 | * This parameter can be one of the following values: |
mbed_official | 610:813dcc80987e | 1256 | * @arg RCC_USBCLKSOURCE_NONE: No clock selected as 48MHz clock |
mbed_official | 610:813dcc80987e | 1257 | * @arg RCC_USBCLKSOURCE_MSI: MSI selected as USB clock |
mbed_official | 610:813dcc80987e | 1258 | * @arg RCC_USBCLKSOURCE_PLLSAI1: PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock |
mbed_official | 610:813dcc80987e | 1259 | * @arg RCC_USBCLKSOURCE_PLL: PLL "Q" clock (PLL48M1CLK) selected as USB clock |
mbed_official | 610:813dcc80987e | 1260 | * @retval None |
mbed_official | 610:813dcc80987e | 1261 | */ |
mbed_official | 610:813dcc80987e | 1262 | #define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \ |
mbed_official | 610:813dcc80987e | 1263 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (uint32_t)(__USB_CLKSOURCE__)) |
mbed_official | 610:813dcc80987e | 1264 | |
mbed_official | 610:813dcc80987e | 1265 | /** @brief Macro to get the USB clock source. |
mbed_official | 610:813dcc80987e | 1266 | * @retval The clock source can be one of the following values: |
mbed_official | 610:813dcc80987e | 1267 | * @arg RCC_USBCLKSOURCE_NONE: No clock selected as 48MHz clock |
mbed_official | 610:813dcc80987e | 1268 | * @arg RCC_USBCLKSOURCE_MSI: MSI selected as USB clock |
mbed_official | 610:813dcc80987e | 1269 | * @arg RCC_USBCLKSOURCE_PLLSAI1: PLLSAI1 "Q" clock (PLL48M2CLK) selected as USB clock |
mbed_official | 610:813dcc80987e | 1270 | * @arg RCC_USBCLKSOURCE_PLL: PLL "Q" clock (PLL48M1CLK) selected as USB clock |
mbed_official | 610:813dcc80987e | 1271 | */ |
mbed_official | 610:813dcc80987e | 1272 | #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))) |
mbed_official | 610:813dcc80987e | 1273 | |
mbed_official | 610:813dcc80987e | 1274 | #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
mbed_official | 610:813dcc80987e | 1275 | |
mbed_official | 610:813dcc80987e | 1276 | /** @brief Macro to configure the ADC interface clock. |
mbed_official | 610:813dcc80987e | 1277 | * @param __ADC_CLKSOURCE__: specifies the ADC digital interface clock source. |
mbed_official | 610:813dcc80987e | 1278 | * This parameter can be one of the following values: |
mbed_official | 610:813dcc80987e | 1279 | * @arg RCC_ADCCLKSOURCE_PLLSAI1: PLLSAI1 Clock selected as ADC clock |
mbed_official | 610:813dcc80987e | 1280 | * @arg RCC_ADCCLKSOURCE_PLLSAI2: PLLSAI2 Clock selected as ADC clock |
mbed_official | 610:813dcc80987e | 1281 | * @arg RCC_ADCCLKSOURCE_SYSCLK: System Clock selected as ADC clock |
mbed_official | 610:813dcc80987e | 1282 | * @retval None |
mbed_official | 610:813dcc80987e | 1283 | */ |
mbed_official | 610:813dcc80987e | 1284 | #define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__) \ |
mbed_official | 610:813dcc80987e | 1285 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, (uint32_t)(__ADC_CLKSOURCE__)) |
mbed_official | 610:813dcc80987e | 1286 | |
mbed_official | 610:813dcc80987e | 1287 | /** @brief Macro to get the ADC clock source. |
mbed_official | 610:813dcc80987e | 1288 | * @retval The clock source can be one of the following values: |
mbed_official | 610:813dcc80987e | 1289 | * @arg RCC_ADCCLKSOURCE_PLLSAI1: PLLSAI1 Clock selected as ADC clock |
mbed_official | 610:813dcc80987e | 1290 | * @arg RCC_ADCCLKSOURCE_PLLSAI2: PLLSAI2 Clock selected as ADC clock |
mbed_official | 610:813dcc80987e | 1291 | * @arg RCC_ADCCLKSOURCE_SYSCLK: System Clock selected as ADC clock |
mbed_official | 610:813dcc80987e | 1292 | */ |
mbed_official | 610:813dcc80987e | 1293 | #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_ADCSEL))) |
mbed_official | 610:813dcc80987e | 1294 | |
mbed_official | 610:813dcc80987e | 1295 | /** @brief Macro to configure the SWPMI1 clock. |
mbed_official | 610:813dcc80987e | 1296 | * @param __SWPMI1_CLKSOURCE__: specifies the SWPMI1 clock source. |
mbed_official | 610:813dcc80987e | 1297 | * This parameter can be one of the following values: |
mbed_official | 610:813dcc80987e | 1298 | * @arg RCC_SWPMI1CLKSOURCE_PCLK: PCLK Clock selected as SWPMI1 clock |
mbed_official | 610:813dcc80987e | 1299 | * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock |
mbed_official | 610:813dcc80987e | 1300 | * @retval None |
mbed_official | 610:813dcc80987e | 1301 | */ |
mbed_official | 610:813dcc80987e | 1302 | #define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1_CLKSOURCE__) \ |
mbed_official | 610:813dcc80987e | 1303 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, (uint32_t)(__SWPMI1_CLKSOURCE__)) |
mbed_official | 610:813dcc80987e | 1304 | |
mbed_official | 610:813dcc80987e | 1305 | /** @brief Macro to get the SWPMI1 clock source. |
mbed_official | 610:813dcc80987e | 1306 | * @retval The clock source can be one of the following values: |
mbed_official | 610:813dcc80987e | 1307 | * @arg RCC_SWPMI1CLKSOURCE_PCLK: PCLK Clock selected as SWPMI1 clock |
mbed_official | 610:813dcc80987e | 1308 | * @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock |
mbed_official | 610:813dcc80987e | 1309 | */ |
mbed_official | 610:813dcc80987e | 1310 | #define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL))) |
mbed_official | 610:813dcc80987e | 1311 | |
mbed_official | 610:813dcc80987e | 1312 | /** @brief Macro to configure the DFSDM clock. |
mbed_official | 610:813dcc80987e | 1313 | * @param __DFSDM_CLKSOURCE__: specifies the DFSDM clock source. |
mbed_official | 610:813dcc80987e | 1314 | * This parameter can be one of the following values: |
mbed_official | 610:813dcc80987e | 1315 | * @arg RCC_DFSDMCLKSOURCE_PCLK: PCLK Clock selected as DFSDM clock |
mbed_official | 610:813dcc80987e | 1316 | * @arg RCC_DFSDMCLKSOURCE_HSI: HSI Clock selected as DFSDM clock |
mbed_official | 610:813dcc80987e | 1317 | * @retval None |
mbed_official | 610:813dcc80987e | 1318 | */ |
mbed_official | 610:813dcc80987e | 1319 | #define __HAL_RCC_DFSDM_CONFIG(__DFSDM_CLKSOURCE__) \ |
mbed_official | 610:813dcc80987e | 1320 | MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDMSEL, (uint32_t)(__DFSDM_CLKSOURCE__)) |
mbed_official | 610:813dcc80987e | 1321 | |
mbed_official | 610:813dcc80987e | 1322 | /** @brief Macro to get the DFSDM clock source. |
mbed_official | 610:813dcc80987e | 1323 | * @retval The clock source can be one of the following values: |
mbed_official | 610:813dcc80987e | 1324 | * @arg RCC_DFSDMCLKSOURCE_PCLK: PCLK Clock selected as DFSDM clock |
mbed_official | 610:813dcc80987e | 1325 | * @arg RCC_DFSDMCLKSOURCE_HSI: HSI Clock selected as DFSDM clock |
mbed_official | 610:813dcc80987e | 1326 | */ |
mbed_official | 610:813dcc80987e | 1327 | #define __HAL_RCC_GET_DFSDM_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_DFSDMSEL))) |
mbed_official | 610:813dcc80987e | 1328 | |
mbed_official | 610:813dcc80987e | 1329 | |
mbed_official | 610:813dcc80987e | 1330 | /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management |
mbed_official | 610:813dcc80987e | 1331 | * @brief macros to manage the specified RCC Flags and interrupts. |
mbed_official | 610:813dcc80987e | 1332 | * @{ |
mbed_official | 610:813dcc80987e | 1333 | */ |
mbed_official | 610:813dcc80987e | 1334 | |
mbed_official | 610:813dcc80987e | 1335 | /** @brief Enable PLLSAI1RDY interrupt. |
mbed_official | 610:813dcc80987e | 1336 | * @retval None |
mbed_official | 610:813dcc80987e | 1337 | */ |
mbed_official | 610:813dcc80987e | 1338 | #define __HAL_RCC_PLLSAI1_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) |
mbed_official | 610:813dcc80987e | 1339 | |
mbed_official | 610:813dcc80987e | 1340 | /** @brief Disable PLLSAI1RDY interrupt. |
mbed_official | 610:813dcc80987e | 1341 | * @retval None |
mbed_official | 610:813dcc80987e | 1342 | */ |
mbed_official | 610:813dcc80987e | 1343 | #define __HAL_RCC_PLLSAI1_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) |
mbed_official | 610:813dcc80987e | 1344 | |
mbed_official | 610:813dcc80987e | 1345 | /** @brief Clear the PLLSAI1RDY interrupt pending bit. |
mbed_official | 610:813dcc80987e | 1346 | * @retval None |
mbed_official | 610:813dcc80987e | 1347 | */ |
mbed_official | 610:813dcc80987e | 1348 | #define __HAL_RCC_PLLSAI1_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI1RDYC) |
mbed_official | 610:813dcc80987e | 1349 | |
mbed_official | 610:813dcc80987e | 1350 | /** @brief Check whether PLLSAI1RDY interrupt has occurred or not. |
mbed_official | 610:813dcc80987e | 1351 | * @retval TRUE or FALSE. |
mbed_official | 610:813dcc80987e | 1352 | */ |
mbed_official | 610:813dcc80987e | 1353 | #define __HAL_RCC_PLLSAI1_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == RCC_CIFR_PLLSAI1RDYF) |
mbed_official | 610:813dcc80987e | 1354 | |
mbed_official | 610:813dcc80987e | 1355 | /** @brief Check whether the PLLSAI1RDY flag is set or not. |
mbed_official | 610:813dcc80987e | 1356 | * @retval TRUE or FALSE. |
mbed_official | 610:813dcc80987e | 1357 | */ |
mbed_official | 610:813dcc80987e | 1358 | #define __HAL_RCC_PLLSAI1_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY)) |
mbed_official | 610:813dcc80987e | 1359 | |
mbed_official | 610:813dcc80987e | 1360 | /** @brief Enable PLLSAI2RDY interrupt. |
mbed_official | 610:813dcc80987e | 1361 | * @retval None |
mbed_official | 610:813dcc80987e | 1362 | */ |
mbed_official | 610:813dcc80987e | 1363 | #define __HAL_RCC_PLLSAI2_ENABLE_IT() SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) |
mbed_official | 610:813dcc80987e | 1364 | |
mbed_official | 610:813dcc80987e | 1365 | /** @brief Disable PLLSAI2RDY interrupt. |
mbed_official | 610:813dcc80987e | 1366 | * @retval None |
mbed_official | 610:813dcc80987e | 1367 | */ |
mbed_official | 610:813dcc80987e | 1368 | #define __HAL_RCC_PLLSAI2_DISABLE_IT() CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) |
mbed_official | 610:813dcc80987e | 1369 | |
mbed_official | 610:813dcc80987e | 1370 | /** @brief Clear the PLLSAI2RDY interrupt pending bit. |
mbed_official | 610:813dcc80987e | 1371 | * @retval None |
mbed_official | 610:813dcc80987e | 1372 | */ |
mbed_official | 610:813dcc80987e | 1373 | #define __HAL_RCC_PLLSAI2_CLEAR_IT() WRITE_REG(RCC->CICR, RCC_CICR_PLLSAI2RDYC) |
mbed_official | 610:813dcc80987e | 1374 | |
mbed_official | 610:813dcc80987e | 1375 | /** @brief Check whether the PLLSAI2RDY interrupt has occurred or not. |
mbed_official | 610:813dcc80987e | 1376 | * @retval TRUE or FALSE. |
mbed_official | 610:813dcc80987e | 1377 | */ |
mbed_official | 610:813dcc80987e | 1378 | #define __HAL_RCC_PLLSAI2_GET_IT_SOURCE() (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == RCC_CIFR_PLLSAI2RDYF) |
mbed_official | 610:813dcc80987e | 1379 | |
mbed_official | 610:813dcc80987e | 1380 | /** @brief Check whether the PLLSAI2RDY flag is set or not. |
mbed_official | 610:813dcc80987e | 1381 | * @retval TRUE or FALSE. |
mbed_official | 610:813dcc80987e | 1382 | */ |
mbed_official | 610:813dcc80987e | 1383 | #define __HAL_RCC_PLLSAI2_GET_FLAG() (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY)) |
mbed_official | 610:813dcc80987e | 1384 | |
mbed_official | 610:813dcc80987e | 1385 | /** |
mbed_official | 610:813dcc80987e | 1386 | * @} |
mbed_official | 610:813dcc80987e | 1387 | */ |
mbed_official | 610:813dcc80987e | 1388 | |
mbed_official | 610:813dcc80987e | 1389 | /** |
mbed_official | 610:813dcc80987e | 1390 | * @} |
mbed_official | 610:813dcc80987e | 1391 | */ |
mbed_official | 610:813dcc80987e | 1392 | |
mbed_official | 610:813dcc80987e | 1393 | /* Exported functions --------------------------------------------------------*/ |
mbed_official | 610:813dcc80987e | 1394 | /** @addtogroup RCCEx_Exported_Functions |
mbed_official | 610:813dcc80987e | 1395 | * @{ |
mbed_official | 610:813dcc80987e | 1396 | */ |
mbed_official | 610:813dcc80987e | 1397 | |
mbed_official | 610:813dcc80987e | 1398 | /** @addtogroup RCCEx_Exported_Functions_Group1 |
mbed_official | 610:813dcc80987e | 1399 | * @{ |
mbed_official | 610:813dcc80987e | 1400 | */ |
mbed_official | 610:813dcc80987e | 1401 | |
mbed_official | 610:813dcc80987e | 1402 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
mbed_official | 610:813dcc80987e | 1403 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
mbed_official | 610:813dcc80987e | 1404 | uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); |
mbed_official | 610:813dcc80987e | 1405 | |
mbed_official | 610:813dcc80987e | 1406 | /** |
mbed_official | 610:813dcc80987e | 1407 | * @} |
mbed_official | 610:813dcc80987e | 1408 | */ |
mbed_official | 610:813dcc80987e | 1409 | |
mbed_official | 610:813dcc80987e | 1410 | /** @addtogroup RCCEx_Exported_Functions_Group2 |
mbed_official | 610:813dcc80987e | 1411 | * @{ |
mbed_official | 610:813dcc80987e | 1412 | */ |
mbed_official | 610:813dcc80987e | 1413 | |
mbed_official | 610:813dcc80987e | 1414 | HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init); |
mbed_official | 610:813dcc80987e | 1415 | HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void); |
mbed_official | 610:813dcc80987e | 1416 | HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI2(RCC_PLLSAI2InitTypeDef *PLLSAI2Init); |
mbed_official | 610:813dcc80987e | 1417 | HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI2(void); |
mbed_official | 610:813dcc80987e | 1418 | void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); |
mbed_official | 610:813dcc80987e | 1419 | void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange); |
mbed_official | 610:813dcc80987e | 1420 | void HAL_RCCEx_EnableLSECSS(void); |
mbed_official | 610:813dcc80987e | 1421 | void HAL_RCCEx_DisableLSECSS(void); |
mbed_official | 610:813dcc80987e | 1422 | void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); |
mbed_official | 610:813dcc80987e | 1423 | void HAL_RCCEx_DisableLSCO(void); |
mbed_official | 610:813dcc80987e | 1424 | void HAL_RCCEx_EnableMSIPLLMode(void); |
mbed_official | 610:813dcc80987e | 1425 | void HAL_RCCEx_DisableMSIPLLMode(void); |
mbed_official | 610:813dcc80987e | 1426 | |
mbed_official | 610:813dcc80987e | 1427 | /** |
mbed_official | 610:813dcc80987e | 1428 | * @} |
mbed_official | 610:813dcc80987e | 1429 | */ |
mbed_official | 610:813dcc80987e | 1430 | |
mbed_official | 610:813dcc80987e | 1431 | /** |
mbed_official | 610:813dcc80987e | 1432 | * @} |
mbed_official | 610:813dcc80987e | 1433 | */ |
mbed_official | 610:813dcc80987e | 1434 | |
mbed_official | 610:813dcc80987e | 1435 | /* Private macros ------------------------------------------------------------*/ |
mbed_official | 610:813dcc80987e | 1436 | /** @addtogroup RCCEx_Private_Macros |
mbed_official | 610:813dcc80987e | 1437 | * @{ |
mbed_official | 610:813dcc80987e | 1438 | */ |
mbed_official | 610:813dcc80987e | 1439 | |
mbed_official | 610:813dcc80987e | 1440 | #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ |
mbed_official | 610:813dcc80987e | 1441 | ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) |
mbed_official | 610:813dcc80987e | 1442 | |
mbed_official | 610:813dcc80987e | 1443 | #if defined(STM32L471xx) |
mbed_official | 610:813dcc80987e | 1444 | |
mbed_official | 610:813dcc80987e | 1445 | #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ |
mbed_official | 610:813dcc80987e | 1446 | ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
mbed_official | 610:813dcc80987e | 1447 | (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
mbed_official | 610:813dcc80987e | 1448 | (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
mbed_official | 610:813dcc80987e | 1449 | (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
mbed_official | 610:813dcc80987e | 1450 | (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ |
mbed_official | 610:813dcc80987e | 1451 | (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ |
mbed_official | 610:813dcc80987e | 1452 | (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
mbed_official | 610:813dcc80987e | 1453 | (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
mbed_official | 610:813dcc80987e | 1454 | (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
mbed_official | 610:813dcc80987e | 1455 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
mbed_official | 610:813dcc80987e | 1456 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ |
mbed_official | 610:813dcc80987e | 1457 | (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
mbed_official | 610:813dcc80987e | 1458 | (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ |
mbed_official | 610:813dcc80987e | 1459 | (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ |
mbed_official | 610:813dcc80987e | 1460 | (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ |
mbed_official | 610:813dcc80987e | 1461 | (((__SELECTION__) & RCC_PERIPHCLK_DFSDM) == RCC_PERIPHCLK_DFSDM) || \ |
mbed_official | 610:813dcc80987e | 1462 | (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ |
mbed_official | 610:813dcc80987e | 1463 | (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ |
mbed_official | 610:813dcc80987e | 1464 | (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) |
mbed_official | 610:813dcc80987e | 1465 | |
mbed_official | 610:813dcc80987e | 1466 | #else /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
mbed_official | 610:813dcc80987e | 1467 | |
mbed_official | 610:813dcc80987e | 1468 | #define IS_RCC_PERIPHCLOCK(__SELECTION__) \ |
mbed_official | 610:813dcc80987e | 1469 | ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ |
mbed_official | 610:813dcc80987e | 1470 | (((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ |
mbed_official | 610:813dcc80987e | 1471 | (((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ |
mbed_official | 610:813dcc80987e | 1472 | (((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ |
mbed_official | 610:813dcc80987e | 1473 | (((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ |
mbed_official | 610:813dcc80987e | 1474 | (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ |
mbed_official | 610:813dcc80987e | 1475 | (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ |
mbed_official | 610:813dcc80987e | 1476 | (((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ |
mbed_official | 610:813dcc80987e | 1477 | (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ |
mbed_official | 610:813dcc80987e | 1478 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ |
mbed_official | 610:813dcc80987e | 1479 | (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ |
mbed_official | 610:813dcc80987e | 1480 | (((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ |
mbed_official | 610:813dcc80987e | 1481 | (((__SELECTION__) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ |
mbed_official | 610:813dcc80987e | 1482 | (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \ |
mbed_official | 610:813dcc80987e | 1483 | (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \ |
mbed_official | 610:813dcc80987e | 1484 | (((__SELECTION__) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) || \ |
mbed_official | 610:813dcc80987e | 1485 | (((__SELECTION__) & RCC_PERIPHCLK_DFSDM) == RCC_PERIPHCLK_DFSDM) || \ |
mbed_official | 610:813dcc80987e | 1486 | (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ |
mbed_official | 610:813dcc80987e | 1487 | (((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \ |
mbed_official | 610:813dcc80987e | 1488 | (((__SELECTION__) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1)) |
mbed_official | 610:813dcc80987e | 1489 | |
mbed_official | 610:813dcc80987e | 1490 | #endif /* STM32L471xx */ |
mbed_official | 610:813dcc80987e | 1491 | |
mbed_official | 610:813dcc80987e | 1492 | #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ |
mbed_official | 610:813dcc80987e | 1493 | (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ |
mbed_official | 610:813dcc80987e | 1494 | ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ |
mbed_official | 610:813dcc80987e | 1495 | ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ |
mbed_official | 610:813dcc80987e | 1496 | ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) |
mbed_official | 610:813dcc80987e | 1497 | |
mbed_official | 610:813dcc80987e | 1498 | #define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ |
mbed_official | 610:813dcc80987e | 1499 | (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ |
mbed_official | 610:813dcc80987e | 1500 | ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ |
mbed_official | 610:813dcc80987e | 1501 | ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ |
mbed_official | 610:813dcc80987e | 1502 | ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) |
mbed_official | 610:813dcc80987e | 1503 | |
mbed_official | 610:813dcc80987e | 1504 | #define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ |
mbed_official | 610:813dcc80987e | 1505 | (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ |
mbed_official | 610:813dcc80987e | 1506 | ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ |
mbed_official | 610:813dcc80987e | 1507 | ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \ |
mbed_official | 610:813dcc80987e | 1508 | ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI)) |
mbed_official | 610:813dcc80987e | 1509 | |
mbed_official | 610:813dcc80987e | 1510 | #define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ |
mbed_official | 610:813dcc80987e | 1511 | (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ |
mbed_official | 610:813dcc80987e | 1512 | ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \ |
mbed_official | 610:813dcc80987e | 1513 | ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \ |
mbed_official | 610:813dcc80987e | 1514 | ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI)) |
mbed_official | 610:813dcc80987e | 1515 | |
mbed_official | 610:813dcc80987e | 1516 | #define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ |
mbed_official | 610:813dcc80987e | 1517 | (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ |
mbed_official | 610:813dcc80987e | 1518 | ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \ |
mbed_official | 610:813dcc80987e | 1519 | ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \ |
mbed_official | 610:813dcc80987e | 1520 | ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI)) |
mbed_official | 610:813dcc80987e | 1521 | |
mbed_official | 610:813dcc80987e | 1522 | #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ |
mbed_official | 610:813dcc80987e | 1523 | (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ |
mbed_official | 610:813dcc80987e | 1524 | ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ |
mbed_official | 610:813dcc80987e | 1525 | ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ |
mbed_official | 610:813dcc80987e | 1526 | ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) |
mbed_official | 610:813dcc80987e | 1527 | |
mbed_official | 610:813dcc80987e | 1528 | #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ |
mbed_official | 610:813dcc80987e | 1529 | (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ |
mbed_official | 610:813dcc80987e | 1530 | ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ |
mbed_official | 610:813dcc80987e | 1531 | ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) |
mbed_official | 610:813dcc80987e | 1532 | |
mbed_official | 610:813dcc80987e | 1533 | #define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ |
mbed_official | 610:813dcc80987e | 1534 | (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ |
mbed_official | 610:813dcc80987e | 1535 | ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ |
mbed_official | 610:813dcc80987e | 1536 | ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)) |
mbed_official | 610:813dcc80987e | 1537 | |
mbed_official | 610:813dcc80987e | 1538 | #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ |
mbed_official | 610:813dcc80987e | 1539 | (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ |
mbed_official | 610:813dcc80987e | 1540 | ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ |
mbed_official | 610:813dcc80987e | 1541 | ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) |
mbed_official | 610:813dcc80987e | 1542 | |
mbed_official | 610:813dcc80987e | 1543 | #define IS_RCC_SAI1CLK(__SOURCE__) \ |
mbed_official | 610:813dcc80987e | 1544 | (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ |
mbed_official | 610:813dcc80987e | 1545 | ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI2) || \ |
mbed_official | 610:813dcc80987e | 1546 | ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ |
mbed_official | 610:813dcc80987e | 1547 | ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) |
mbed_official | 610:813dcc80987e | 1548 | |
mbed_official | 610:813dcc80987e | 1549 | #define IS_RCC_SAI2CLK(__SOURCE__) \ |
mbed_official | 610:813dcc80987e | 1550 | (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ |
mbed_official | 610:813dcc80987e | 1551 | ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLLSAI2) || \ |
mbed_official | 610:813dcc80987e | 1552 | ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) || \ |
mbed_official | 610:813dcc80987e | 1553 | ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN)) |
mbed_official | 610:813dcc80987e | 1554 | |
mbed_official | 610:813dcc80987e | 1555 | #define IS_RCC_LPTIM1CLK(__SOURCE__) \ |
mbed_official | 610:813dcc80987e | 1556 | (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK) || \ |
mbed_official | 610:813dcc80987e | 1557 | ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ |
mbed_official | 610:813dcc80987e | 1558 | ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ |
mbed_official | 610:813dcc80987e | 1559 | ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) |
mbed_official | 610:813dcc80987e | 1560 | |
mbed_official | 610:813dcc80987e | 1561 | #define IS_RCC_LPTIM2CLK(__SOURCE__) \ |
mbed_official | 610:813dcc80987e | 1562 | (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK) || \ |
mbed_official | 610:813dcc80987e | 1563 | ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ |
mbed_official | 610:813dcc80987e | 1564 | ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ |
mbed_official | 610:813dcc80987e | 1565 | ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) |
mbed_official | 610:813dcc80987e | 1566 | |
mbed_official | 610:813dcc80987e | 1567 | #define IS_RCC_SDMMC1CLKSOURCE(__SOURCE__) \ |
mbed_official | 610:813dcc80987e | 1568 | (((__SOURCE__) == RCC_SDMMC1CLKSOURCE_NONE) || \ |
mbed_official | 610:813dcc80987e | 1569 | ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLLSAI1) || \ |
mbed_official | 610:813dcc80987e | 1570 | ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_PLL) || \ |
mbed_official | 610:813dcc80987e | 1571 | ((__SOURCE__) == RCC_SDMMC1CLKSOURCE_MSI)) |
mbed_official | 610:813dcc80987e | 1572 | |
mbed_official | 610:813dcc80987e | 1573 | #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ |
mbed_official | 610:813dcc80987e | 1574 | (((__SOURCE__) == RCC_RNGCLKSOURCE_NONE) || \ |
mbed_official | 610:813dcc80987e | 1575 | ((__SOURCE__) == RCC_RNGCLKSOURCE_PLLSAI1) || \ |
mbed_official | 610:813dcc80987e | 1576 | ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \ |
mbed_official | 610:813dcc80987e | 1577 | ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI)) |
mbed_official | 610:813dcc80987e | 1578 | |
mbed_official | 610:813dcc80987e | 1579 | #if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) |
mbed_official | 610:813dcc80987e | 1580 | #define IS_RCC_USBCLKSOURCE(__SOURCE__) \ |
mbed_official | 610:813dcc80987e | 1581 | (((__SOURCE__) == RCC_USBCLKSOURCE_NONE) || \ |
mbed_official | 610:813dcc80987e | 1582 | ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ |
mbed_official | 610:813dcc80987e | 1583 | ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ |
mbed_official | 610:813dcc80987e | 1584 | ((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) |
mbed_official | 610:813dcc80987e | 1585 | #endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ |
mbed_official | 610:813dcc80987e | 1586 | |
mbed_official | 610:813dcc80987e | 1587 | #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ |
mbed_official | 610:813dcc80987e | 1588 | (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ |
mbed_official | 610:813dcc80987e | 1589 | ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ |
mbed_official | 610:813dcc80987e | 1590 | ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI2) || \ |
mbed_official | 610:813dcc80987e | 1591 | ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) |
mbed_official | 610:813dcc80987e | 1592 | |
mbed_official | 610:813dcc80987e | 1593 | #define IS_RCC_SWPMI1CLKSOURCE(__SOURCE__) \ |
mbed_official | 610:813dcc80987e | 1594 | (((__SOURCE__) == RCC_SWPMI1CLKSOURCE_PCLK) || \ |
mbed_official | 610:813dcc80987e | 1595 | ((__SOURCE__) == RCC_SWPMI1CLKSOURCE_HSI)) |
mbed_official | 610:813dcc80987e | 1596 | |
mbed_official | 610:813dcc80987e | 1597 | #define IS_RCC_DFSDMCLKSOURCE(__SOURCE__) \ |
mbed_official | 610:813dcc80987e | 1598 | (((__SOURCE__) == RCC_DFSDMCLKSOURCE_PCLK) || \ |
mbed_official | 610:813dcc80987e | 1599 | ((__SOURCE__) == RCC_DFSDMCLKSOURCE_SYSCLK)) |
mbed_official | 610:813dcc80987e | 1600 | |
mbed_official | 610:813dcc80987e | 1601 | |
mbed_official | 610:813dcc80987e | 1602 | #define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8 <= (__VALUE__)) && ((__VALUE__) <= 86)) |
mbed_official | 610:813dcc80987e | 1603 | |
mbed_official | 610:813dcc80987e | 1604 | #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) (((__VALUE__) == 7) || ((__VALUE__) == 17)) |
mbed_official | 610:813dcc80987e | 1605 | |
mbed_official | 610:813dcc80987e | 1606 | #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) (((__VALUE__) == 2 ) || ((__VALUE__) == 4) || \ |
mbed_official | 610:813dcc80987e | 1607 | ((__VALUE__) == 6) || ((__VALUE__) == 8)) |
mbed_official | 610:813dcc80987e | 1608 | |
mbed_official | 610:813dcc80987e | 1609 | #define IS_RCC_PLLSAI1R_VALUE(__VALUE__) (((__VALUE__) == 2 ) || ((__VALUE__) == 4) || \ |
mbed_official | 610:813dcc80987e | 1610 | ((__VALUE__) == 6) || ((__VALUE__) == 8)) |
mbed_official | 610:813dcc80987e | 1611 | |
mbed_official | 610:813dcc80987e | 1612 | #define IS_RCC_PLLSAI2N_VALUE(__VALUE__) ((8 <= (__VALUE__)) && ((__VALUE__) <= 86)) |
mbed_official | 610:813dcc80987e | 1613 | |
mbed_official | 610:813dcc80987e | 1614 | #define IS_RCC_PLLSAI2P_VALUE(__VALUE__) (((__VALUE__) == 7) || ((__VALUE__) == 17)) |
mbed_official | 610:813dcc80987e | 1615 | |
mbed_official | 610:813dcc80987e | 1616 | #define IS_RCC_PLLSAI2R_VALUE(__VALUE__) (((__VALUE__) == 2 ) || ((__VALUE__) == 4) || \ |
mbed_official | 610:813dcc80987e | 1617 | ((__VALUE__) == 6) || ((__VALUE__) == 8)) |
mbed_official | 610:813dcc80987e | 1618 | |
mbed_official | 610:813dcc80987e | 1619 | /** |
mbed_official | 610:813dcc80987e | 1620 | * @} |
mbed_official | 610:813dcc80987e | 1621 | */ |
mbed_official | 610:813dcc80987e | 1622 | |
mbed_official | 610:813dcc80987e | 1623 | /** |
mbed_official | 610:813dcc80987e | 1624 | * @} |
mbed_official | 610:813dcc80987e | 1625 | */ |
mbed_official | 610:813dcc80987e | 1626 | |
mbed_official | 610:813dcc80987e | 1627 | /** |
mbed_official | 610:813dcc80987e | 1628 | * @} |
mbed_official | 610:813dcc80987e | 1629 | */ |
mbed_official | 610:813dcc80987e | 1630 | |
mbed_official | 610:813dcc80987e | 1631 | #ifdef __cplusplus |
mbed_official | 610:813dcc80987e | 1632 | } |
mbed_official | 610:813dcc80987e | 1633 | #endif |
mbed_official | 610:813dcc80987e | 1634 | |
mbed_official | 610:813dcc80987e | 1635 | #endif /* __STM32L4xx_HAL_RCC_EX_H */ |
mbed_official | 610:813dcc80987e | 1636 | |
mbed_official | 610:813dcc80987e | 1637 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |