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targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal.h@637:ed69428d4850, 2015-12-22 (annotated)
- Committer:
- jaerts
- Date:
- Tue Dec 22 13:22:16 2015 +0000
- Revision:
- 637:ed69428d4850
- Parent:
- 610:813dcc80987e
Add very shady LPC1768 CAN Filter implementation
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 610:813dcc80987e | 1 | /** |
| mbed_official | 610:813dcc80987e | 2 | ****************************************************************************** |
| mbed_official | 610:813dcc80987e | 3 | * @file stm32l4xx_hal.h |
| mbed_official | 610:813dcc80987e | 4 | * @author MCD Application Team |
| mbed_official | 610:813dcc80987e | 5 | * @version V1.0.0 |
| mbed_official | 610:813dcc80987e | 6 | * @date 26-June-2015 |
| mbed_official | 610:813dcc80987e | 7 | * @brief This file contains all the functions prototypes for the HAL |
| mbed_official | 610:813dcc80987e | 8 | * module driver. |
| mbed_official | 610:813dcc80987e | 9 | ****************************************************************************** |
| mbed_official | 610:813dcc80987e | 10 | * @attention |
| mbed_official | 610:813dcc80987e | 11 | * |
| mbed_official | 610:813dcc80987e | 12 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| mbed_official | 610:813dcc80987e | 13 | * |
| mbed_official | 610:813dcc80987e | 14 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 610:813dcc80987e | 15 | * are permitted provided that the following conditions are met: |
| mbed_official | 610:813dcc80987e | 16 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 610:813dcc80987e | 17 | * this list of conditions and the following disclaimer. |
| mbed_official | 610:813dcc80987e | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 610:813dcc80987e | 19 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 610:813dcc80987e | 20 | * and/or other materials provided with the distribution. |
| mbed_official | 610:813dcc80987e | 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 610:813dcc80987e | 22 | * may be used to endorse or promote products derived from this software |
| mbed_official | 610:813dcc80987e | 23 | * without specific prior written permission. |
| mbed_official | 610:813dcc80987e | 24 | * |
| mbed_official | 610:813dcc80987e | 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 610:813dcc80987e | 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 610:813dcc80987e | 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 610:813dcc80987e | 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 610:813dcc80987e | 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 610:813dcc80987e | 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 610:813dcc80987e | 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 610:813dcc80987e | 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 610:813dcc80987e | 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 610:813dcc80987e | 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 610:813dcc80987e | 35 | * |
| mbed_official | 610:813dcc80987e | 36 | ****************************************************************************** |
| mbed_official | 610:813dcc80987e | 37 | */ |
| mbed_official | 610:813dcc80987e | 38 | |
| mbed_official | 610:813dcc80987e | 39 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| mbed_official | 610:813dcc80987e | 40 | #ifndef __STM32L4xx_HAL_H |
| mbed_official | 610:813dcc80987e | 41 | #define __STM32L4xx_HAL_H |
| mbed_official | 610:813dcc80987e | 42 | |
| mbed_official | 610:813dcc80987e | 43 | #ifdef __cplusplus |
| mbed_official | 610:813dcc80987e | 44 | extern "C" { |
| mbed_official | 610:813dcc80987e | 45 | #endif |
| mbed_official | 610:813dcc80987e | 46 | |
| mbed_official | 610:813dcc80987e | 47 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 610:813dcc80987e | 48 | #include "stm32l4xx_hal_conf.h" |
| mbed_official | 610:813dcc80987e | 49 | |
| mbed_official | 610:813dcc80987e | 50 | /** @addtogroup STM32L4xx_HAL_Driver |
| mbed_official | 610:813dcc80987e | 51 | * @{ |
| mbed_official | 610:813dcc80987e | 52 | */ |
| mbed_official | 610:813dcc80987e | 53 | |
| mbed_official | 610:813dcc80987e | 54 | /** @addtogroup HAL |
| mbed_official | 610:813dcc80987e | 55 | * @{ |
| mbed_official | 610:813dcc80987e | 56 | */ |
| mbed_official | 610:813dcc80987e | 57 | |
| mbed_official | 610:813dcc80987e | 58 | /* Exported types ------------------------------------------------------------*/ |
| mbed_official | 610:813dcc80987e | 59 | /* Exported constants --------------------------------------------------------*/ |
| mbed_official | 610:813dcc80987e | 60 | /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants |
| mbed_official | 610:813dcc80987e | 61 | * @{ |
| mbed_official | 610:813dcc80987e | 62 | */ |
| mbed_official | 610:813dcc80987e | 63 | |
| mbed_official | 610:813dcc80987e | 64 | /** @defgroup SYSCFG_BootMode Boot Mode |
| mbed_official | 610:813dcc80987e | 65 | * @{ |
| mbed_official | 610:813dcc80987e | 66 | */ |
| mbed_official | 610:813dcc80987e | 67 | #define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000) |
| mbed_official | 610:813dcc80987e | 68 | #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 |
| mbed_official | 610:813dcc80987e | 69 | #define SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1 |
| mbed_official | 610:813dcc80987e | 70 | #define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) |
| mbed_official | 610:813dcc80987e | 71 | #define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) |
| mbed_official | 610:813dcc80987e | 72 | |
| mbed_official | 610:813dcc80987e | 73 | /** |
| mbed_official | 610:813dcc80987e | 74 | * @} |
| mbed_official | 610:813dcc80987e | 75 | */ |
| mbed_official | 610:813dcc80987e | 76 | |
| mbed_official | 610:813dcc80987e | 77 | /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts |
| mbed_official | 610:813dcc80987e | 78 | * @{ |
| mbed_official | 610:813dcc80987e | 79 | */ |
| mbed_official | 610:813dcc80987e | 80 | #define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ |
| mbed_official | 610:813dcc80987e | 81 | #define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ |
| mbed_official | 610:813dcc80987e | 82 | #define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ |
| mbed_official | 610:813dcc80987e | 83 | #define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ |
| mbed_official | 610:813dcc80987e | 84 | #define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ |
| mbed_official | 610:813dcc80987e | 85 | #define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ |
| mbed_official | 610:813dcc80987e | 86 | |
| mbed_official | 610:813dcc80987e | 87 | /** |
| mbed_official | 610:813dcc80987e | 88 | * @} |
| mbed_official | 610:813dcc80987e | 89 | */ |
| mbed_official | 610:813dcc80987e | 90 | |
| mbed_official | 610:813dcc80987e | 91 | /** @defgroup SYSCFG_SRAM2WRP SRAM2 Write protection |
| mbed_official | 610:813dcc80987e | 92 | * @{ |
| mbed_official | 610:813dcc80987e | 93 | */ |
| mbed_official | 610:813dcc80987e | 94 | #define SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */ |
| mbed_official | 610:813dcc80987e | 95 | #define SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */ |
| mbed_official | 610:813dcc80987e | 96 | #define SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */ |
| mbed_official | 610:813dcc80987e | 97 | #define SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */ |
| mbed_official | 610:813dcc80987e | 98 | #define SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */ |
| mbed_official | 610:813dcc80987e | 99 | #define SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */ |
| mbed_official | 610:813dcc80987e | 100 | #define SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */ |
| mbed_official | 610:813dcc80987e | 101 | #define SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */ |
| mbed_official | 610:813dcc80987e | 102 | #define SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */ |
| mbed_official | 610:813dcc80987e | 103 | #define SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */ |
| mbed_official | 610:813dcc80987e | 104 | #define SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */ |
| mbed_official | 610:813dcc80987e | 105 | #define SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */ |
| mbed_official | 610:813dcc80987e | 106 | #define SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */ |
| mbed_official | 610:813dcc80987e | 107 | #define SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */ |
| mbed_official | 610:813dcc80987e | 108 | #define SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */ |
| mbed_official | 610:813dcc80987e | 109 | #define SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */ |
| mbed_official | 610:813dcc80987e | 110 | #define SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */ |
| mbed_official | 610:813dcc80987e | 111 | #define SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */ |
| mbed_official | 610:813dcc80987e | 112 | #define SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */ |
| mbed_official | 610:813dcc80987e | 113 | #define SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */ |
| mbed_official | 610:813dcc80987e | 114 | #define SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */ |
| mbed_official | 610:813dcc80987e | 115 | #define SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */ |
| mbed_official | 610:813dcc80987e | 116 | #define SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */ |
| mbed_official | 610:813dcc80987e | 117 | #define SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */ |
| mbed_official | 610:813dcc80987e | 118 | #define SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */ |
| mbed_official | 610:813dcc80987e | 119 | #define SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */ |
| mbed_official | 610:813dcc80987e | 120 | #define SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */ |
| mbed_official | 610:813dcc80987e | 121 | #define SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */ |
| mbed_official | 610:813dcc80987e | 122 | #define SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */ |
| mbed_official | 610:813dcc80987e | 123 | #define SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */ |
| mbed_official | 610:813dcc80987e | 124 | #define SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */ |
| mbed_official | 610:813dcc80987e | 125 | #define SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */ |
| mbed_official | 610:813dcc80987e | 126 | |
| mbed_official | 610:813dcc80987e | 127 | /** |
| mbed_official | 610:813dcc80987e | 128 | * @} |
| mbed_official | 610:813dcc80987e | 129 | */ |
| mbed_official | 610:813dcc80987e | 130 | |
| mbed_official | 610:813dcc80987e | 131 | /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale |
| mbed_official | 610:813dcc80987e | 132 | * @{ |
| mbed_official | 610:813dcc80987e | 133 | */ |
| mbed_official | 610:813dcc80987e | 134 | #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ |
| mbed_official | 610:813dcc80987e | 135 | #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */ |
| mbed_official | 610:813dcc80987e | 136 | |
| mbed_official | 610:813dcc80987e | 137 | /** |
| mbed_official | 610:813dcc80987e | 138 | * @} |
| mbed_official | 610:813dcc80987e | 139 | */ |
| mbed_official | 610:813dcc80987e | 140 | |
| mbed_official | 610:813dcc80987e | 141 | /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance |
| mbed_official | 610:813dcc80987e | 142 | * @{ |
| mbed_official | 610:813dcc80987e | 143 | */ |
| mbed_official | 610:813dcc80987e | 144 | #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ |
| mbed_official | 610:813dcc80987e | 145 | #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ |
| mbed_official | 610:813dcc80987e | 146 | |
| mbed_official | 610:813dcc80987e | 147 | /** |
| mbed_official | 610:813dcc80987e | 148 | * @} |
| mbed_official | 610:813dcc80987e | 149 | */ |
| mbed_official | 610:813dcc80987e | 150 | |
| mbed_official | 610:813dcc80987e | 151 | /** @defgroup SYSCFG_flags_definition Flags |
| mbed_official | 610:813dcc80987e | 152 | * @{ |
| mbed_official | 610:813dcc80987e | 153 | */ |
| mbed_official | 610:813dcc80987e | 154 | |
| mbed_official | 610:813dcc80987e | 155 | #define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */ |
| mbed_official | 610:813dcc80987e | 156 | #define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */ |
| mbed_official | 610:813dcc80987e | 157 | |
| mbed_official | 610:813dcc80987e | 158 | /** |
| mbed_official | 610:813dcc80987e | 159 | * @} |
| mbed_official | 610:813dcc80987e | 160 | */ |
| mbed_official | 610:813dcc80987e | 161 | |
| mbed_official | 610:813dcc80987e | 162 | /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO |
| mbed_official | 610:813dcc80987e | 163 | * @{ |
| mbed_official | 610:813dcc80987e | 164 | */ |
| mbed_official | 610:813dcc80987e | 165 | |
| mbed_official | 610:813dcc80987e | 166 | /** @brief Fast-mode Plus driving capability on a specific GPIO |
| mbed_official | 610:813dcc80987e | 167 | */ |
| mbed_official | 610:813dcc80987e | 168 | #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ |
| mbed_official | 610:813dcc80987e | 169 | #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ |
| mbed_official | 610:813dcc80987e | 170 | #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ |
| mbed_official | 610:813dcc80987e | 171 | #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ |
| mbed_official | 610:813dcc80987e | 172 | |
| mbed_official | 610:813dcc80987e | 173 | /** |
| mbed_official | 610:813dcc80987e | 174 | * @} |
| mbed_official | 610:813dcc80987e | 175 | */ |
| mbed_official | 610:813dcc80987e | 176 | |
| mbed_official | 610:813dcc80987e | 177 | /** |
| mbed_official | 610:813dcc80987e | 178 | * @} |
| mbed_official | 610:813dcc80987e | 179 | */ |
| mbed_official | 610:813dcc80987e | 180 | |
| mbed_official | 610:813dcc80987e | 181 | /* Exported macros -----------------------------------------------------------*/ |
| mbed_official | 610:813dcc80987e | 182 | |
| mbed_official | 610:813dcc80987e | 183 | /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros |
| mbed_official | 610:813dcc80987e | 184 | * @{ |
| mbed_official | 610:813dcc80987e | 185 | */ |
| mbed_official | 610:813dcc80987e | 186 | |
| mbed_official | 610:813dcc80987e | 187 | /** @brief Freeze/Unfreeze Peripherals in Debug mode |
| mbed_official | 610:813dcc80987e | 188 | */ |
| mbed_official | 610:813dcc80987e | 189 | #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) |
| mbed_official | 610:813dcc80987e | 190 | #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) |
| mbed_official | 610:813dcc80987e | 191 | #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) |
| mbed_official | 610:813dcc80987e | 192 | #endif |
| mbed_official | 610:813dcc80987e | 193 | |
| mbed_official | 610:813dcc80987e | 194 | #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) |
| mbed_official | 610:813dcc80987e | 195 | #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) |
| mbed_official | 610:813dcc80987e | 196 | #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) |
| mbed_official | 610:813dcc80987e | 197 | #endif |
| mbed_official | 610:813dcc80987e | 198 | |
| mbed_official | 610:813dcc80987e | 199 | #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) |
| mbed_official | 610:813dcc80987e | 200 | #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) |
| mbed_official | 610:813dcc80987e | 201 | #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) |
| mbed_official | 610:813dcc80987e | 202 | #endif |
| mbed_official | 610:813dcc80987e | 203 | |
| mbed_official | 610:813dcc80987e | 204 | #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) |
| mbed_official | 610:813dcc80987e | 205 | #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) |
| mbed_official | 610:813dcc80987e | 206 | #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) |
| mbed_official | 610:813dcc80987e | 207 | #endif |
| mbed_official | 610:813dcc80987e | 208 | |
| mbed_official | 610:813dcc80987e | 209 | #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) |
| mbed_official | 610:813dcc80987e | 210 | #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) |
| mbed_official | 610:813dcc80987e | 211 | #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) |
| mbed_official | 610:813dcc80987e | 212 | #endif |
| mbed_official | 610:813dcc80987e | 213 | |
| mbed_official | 610:813dcc80987e | 214 | #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) |
| mbed_official | 610:813dcc80987e | 215 | #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) |
| mbed_official | 610:813dcc80987e | 216 | #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) |
| mbed_official | 610:813dcc80987e | 217 | #endif |
| mbed_official | 610:813dcc80987e | 218 | |
| mbed_official | 610:813dcc80987e | 219 | #if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP) |
| mbed_official | 610:813dcc80987e | 220 | #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) |
| mbed_official | 610:813dcc80987e | 221 | #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) |
| mbed_official | 610:813dcc80987e | 222 | #endif |
| mbed_official | 610:813dcc80987e | 223 | |
| mbed_official | 610:813dcc80987e | 224 | #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) |
| mbed_official | 610:813dcc80987e | 225 | #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) |
| mbed_official | 610:813dcc80987e | 226 | #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) |
| mbed_official | 610:813dcc80987e | 227 | #endif |
| mbed_official | 610:813dcc80987e | 228 | |
| mbed_official | 610:813dcc80987e | 229 | #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) |
| mbed_official | 610:813dcc80987e | 230 | #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) |
| mbed_official | 610:813dcc80987e | 231 | #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) |
| mbed_official | 610:813dcc80987e | 232 | #endif |
| mbed_official | 610:813dcc80987e | 233 | |
| mbed_official | 610:813dcc80987e | 234 | #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) |
| mbed_official | 610:813dcc80987e | 235 | #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) |
| mbed_official | 610:813dcc80987e | 236 | #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) |
| mbed_official | 610:813dcc80987e | 237 | #endif |
| mbed_official | 610:813dcc80987e | 238 | |
| mbed_official | 610:813dcc80987e | 239 | #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) |
| mbed_official | 610:813dcc80987e | 240 | #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) |
| mbed_official | 610:813dcc80987e | 241 | #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) |
| mbed_official | 610:813dcc80987e | 242 | #endif |
| mbed_official | 610:813dcc80987e | 243 | |
| mbed_official | 610:813dcc80987e | 244 | #if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP) |
| mbed_official | 610:813dcc80987e | 245 | #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) |
| mbed_official | 610:813dcc80987e | 246 | #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) |
| mbed_official | 610:813dcc80987e | 247 | #endif |
| mbed_official | 610:813dcc80987e | 248 | |
| mbed_official | 610:813dcc80987e | 249 | #if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP) |
| mbed_official | 610:813dcc80987e | 250 | #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) |
| mbed_official | 610:813dcc80987e | 251 | #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) |
| mbed_official | 610:813dcc80987e | 252 | #endif |
| mbed_official | 610:813dcc80987e | 253 | |
| mbed_official | 610:813dcc80987e | 254 | #if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) |
| mbed_official | 610:813dcc80987e | 255 | #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) |
| mbed_official | 610:813dcc80987e | 256 | #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) |
| mbed_official | 610:813dcc80987e | 257 | #endif |
| mbed_official | 610:813dcc80987e | 258 | |
| mbed_official | 610:813dcc80987e | 259 | #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) |
| mbed_official | 610:813dcc80987e | 260 | #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) |
| mbed_official | 610:813dcc80987e | 261 | #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) |
| mbed_official | 610:813dcc80987e | 262 | #endif |
| mbed_official | 610:813dcc80987e | 263 | |
| mbed_official | 610:813dcc80987e | 264 | #if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP) |
| mbed_official | 610:813dcc80987e | 265 | #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) |
| mbed_official | 610:813dcc80987e | 266 | #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) |
| mbed_official | 610:813dcc80987e | 267 | #endif |
| mbed_official | 610:813dcc80987e | 268 | |
| mbed_official | 610:813dcc80987e | 269 | #if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP) |
| mbed_official | 610:813dcc80987e | 270 | #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) |
| mbed_official | 610:813dcc80987e | 271 | #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) |
| mbed_official | 610:813dcc80987e | 272 | #endif |
| mbed_official | 610:813dcc80987e | 273 | |
| mbed_official | 610:813dcc80987e | 274 | #if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP) |
| mbed_official | 610:813dcc80987e | 275 | #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) |
| mbed_official | 610:813dcc80987e | 276 | #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) |
| mbed_official | 610:813dcc80987e | 277 | #endif |
| mbed_official | 610:813dcc80987e | 278 | |
| mbed_official | 610:813dcc80987e | 279 | #if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP) |
| mbed_official | 610:813dcc80987e | 280 | #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) |
| mbed_official | 610:813dcc80987e | 281 | #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) |
| mbed_official | 610:813dcc80987e | 282 | #endif |
| mbed_official | 610:813dcc80987e | 283 | |
| mbed_official | 610:813dcc80987e | 284 | #if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP) |
| mbed_official | 610:813dcc80987e | 285 | #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) |
| mbed_official | 610:813dcc80987e | 286 | #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) |
| mbed_official | 610:813dcc80987e | 287 | #endif |
| mbed_official | 610:813dcc80987e | 288 | |
| mbed_official | 610:813dcc80987e | 289 | /** |
| mbed_official | 610:813dcc80987e | 290 | * @} |
| mbed_official | 610:813dcc80987e | 291 | */ |
| mbed_official | 610:813dcc80987e | 292 | |
| mbed_official | 610:813dcc80987e | 293 | /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros |
| mbed_official | 610:813dcc80987e | 294 | * @{ |
| mbed_official | 610:813dcc80987e | 295 | */ |
| mbed_official | 610:813dcc80987e | 296 | |
| mbed_official | 610:813dcc80987e | 297 | /** @brief Main Flash memory mapped at 0x00000000. |
| mbed_official | 610:813dcc80987e | 298 | */ |
| mbed_official | 610:813dcc80987e | 299 | #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) |
| mbed_official | 610:813dcc80987e | 300 | |
| mbed_official | 610:813dcc80987e | 301 | /** @brief System Flash memory mapped at 0x00000000. |
| mbed_official | 610:813dcc80987e | 302 | */ |
| mbed_official | 610:813dcc80987e | 303 | #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) |
| mbed_official | 610:813dcc80987e | 304 | |
| mbed_official | 610:813dcc80987e | 305 | /** @brief Embedded SRAM mapped at 0x00000000. |
| mbed_official | 610:813dcc80987e | 306 | */ |
| mbed_official | 610:813dcc80987e | 307 | #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0)) |
| mbed_official | 610:813dcc80987e | 308 | |
| mbed_official | 610:813dcc80987e | 309 | /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000. |
| mbed_official | 610:813dcc80987e | 310 | */ |
| mbed_official | 610:813dcc80987e | 311 | #define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) |
| mbed_official | 610:813dcc80987e | 312 | |
| mbed_official | 610:813dcc80987e | 313 | /** @brief QUADSPI mapped at 0x00000000. |
| mbed_official | 610:813dcc80987e | 314 | */ |
| mbed_official | 610:813dcc80987e | 315 | #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1)) |
| mbed_official | 610:813dcc80987e | 316 | |
| mbed_official | 610:813dcc80987e | 317 | /** |
| mbed_official | 610:813dcc80987e | 318 | * @brief Return the boot mode as configured by user. |
| mbed_official | 610:813dcc80987e | 319 | * @retval The boot mode as configured by user. The returned value can be one |
| mbed_official | 610:813dcc80987e | 320 | * of the following values: |
| mbed_official | 610:813dcc80987e | 321 | * @arg SYSCFG_BOOT_MAINFLASH |
| mbed_official | 610:813dcc80987e | 322 | * @arg SYSCFG_BOOT_SYSTEMFLASH |
| mbed_official | 610:813dcc80987e | 323 | * @arg SYSCFG_BOOT_FMC |
| mbed_official | 610:813dcc80987e | 324 | * @arg SYSCFG_BOOT_SRAM |
| mbed_official | 610:813dcc80987e | 325 | * @arg SYSCFG_BOOT_QUADSPI |
| mbed_official | 610:813dcc80987e | 326 | */ |
| mbed_official | 610:813dcc80987e | 327 | #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) |
| mbed_official | 610:813dcc80987e | 328 | |
| mbed_official | 610:813dcc80987e | 329 | /** @brief SRAM2 page write protection enable macro |
| mbed_official | 610:813dcc80987e | 330 | * @param __SRAM2WRP__: This parameter can be a value of @ref SYSCFG_SRAM2WRP |
| mbed_official | 610:813dcc80987e | 331 | * @note write protection can only be disabled by a system reset |
| mbed_official | 610:813dcc80987e | 332 | */ |
| mbed_official | 610:813dcc80987e | 333 | #define __HAL_SYSCFG_SRAM2_WRP_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ |
| mbed_official | 610:813dcc80987e | 334 | SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\ |
| mbed_official | 610:813dcc80987e | 335 | }while(0) |
| mbed_official | 610:813dcc80987e | 336 | |
| mbed_official | 610:813dcc80987e | 337 | /** @brief SRAM2 page write protection unlock prior to erase |
| mbed_official | 610:813dcc80987e | 338 | * @note Writing a wrong key reactivates the write protection |
| mbed_official | 610:813dcc80987e | 339 | */ |
| mbed_official | 610:813dcc80987e | 340 | #define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\ |
| mbed_official | 610:813dcc80987e | 341 | SYSCFG->SKR = 0x53;\ |
| mbed_official | 610:813dcc80987e | 342 | }while(0) |
| mbed_official | 610:813dcc80987e | 343 | |
| mbed_official | 610:813dcc80987e | 344 | /** @brief SRAM2 erase |
| mbed_official | 610:813dcc80987e | 345 | * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase |
| mbed_official | 610:813dcc80987e | 346 | */ |
| mbed_official | 610:813dcc80987e | 347 | #define __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER) |
| mbed_official | 610:813dcc80987e | 348 | |
| mbed_official | 610:813dcc80987e | 349 | /** @brief Floating Point Unit interrupt enable/disable macros |
| mbed_official | 610:813dcc80987e | 350 | * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts |
| mbed_official | 610:813dcc80987e | 351 | */ |
| mbed_official | 610:813dcc80987e | 352 | #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ |
| mbed_official | 610:813dcc80987e | 353 | SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ |
| mbed_official | 610:813dcc80987e | 354 | }while(0) |
| mbed_official | 610:813dcc80987e | 355 | |
| mbed_official | 610:813dcc80987e | 356 | #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ |
| mbed_official | 610:813dcc80987e | 357 | CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ |
| mbed_official | 610:813dcc80987e | 358 | }while(0) |
| mbed_official | 610:813dcc80987e | 359 | |
| mbed_official | 610:813dcc80987e | 360 | /** @brief SYSCFG Break ECC lock. |
| mbed_official | 610:813dcc80987e | 361 | * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. |
| mbed_official | 610:813dcc80987e | 362 | * @note The selected configuration is locked and can be unlocked only by system reset. |
| mbed_official | 610:813dcc80987e | 363 | */ |
| mbed_official | 610:813dcc80987e | 364 | #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) |
| mbed_official | 610:813dcc80987e | 365 | |
| mbed_official | 610:813dcc80987e | 366 | /** @brief SYSCFG Break Cortex-M4 Lockup lock. |
| mbed_official | 610:813dcc80987e | 367 | * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. |
| mbed_official | 610:813dcc80987e | 368 | * @note The selected configuration is locked and can be unlocked only by system reset. |
| mbed_official | 610:813dcc80987e | 369 | */ |
| mbed_official | 610:813dcc80987e | 370 | #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) |
| mbed_official | 610:813dcc80987e | 371 | |
| mbed_official | 610:813dcc80987e | 372 | /** @brief SYSCFG Break PVD lock. |
| mbed_official | 610:813dcc80987e | 373 | * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register. |
| mbed_official | 610:813dcc80987e | 374 | * @note The selected configuration is locked and can be unlocked only by system reset. |
| mbed_official | 610:813dcc80987e | 375 | */ |
| mbed_official | 610:813dcc80987e | 376 | #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) |
| mbed_official | 610:813dcc80987e | 377 | |
| mbed_official | 610:813dcc80987e | 378 | /** @brief SYSCFG Break SRAM2 parity lock. |
| mbed_official | 610:813dcc80987e | 379 | * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input. |
| mbed_official | 610:813dcc80987e | 380 | * @note The selected configuration is locked and can be unlocked by system reset. |
| mbed_official | 610:813dcc80987e | 381 | */ |
| mbed_official | 610:813dcc80987e | 382 | #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) |
| mbed_official | 610:813dcc80987e | 383 | |
| mbed_official | 610:813dcc80987e | 384 | /** @brief Check SYSCFG flag is set or not. |
| mbed_official | 610:813dcc80987e | 385 | * @param __FLAG__: specifies the flag to check. |
| mbed_official | 610:813dcc80987e | 386 | * This parameter can be one of the following values: |
| mbed_official | 610:813dcc80987e | 387 | * @arg SYSCFG_FLAG_SRAM2_PE: SRAM2 Parity Error Flag |
| mbed_official | 610:813dcc80987e | 388 | * @arg SYSCFG_FLAG_SRAM2_BUSY: SRAM2 Erase Ongoing |
| mbed_official | 610:813dcc80987e | 389 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| mbed_official | 610:813dcc80987e | 390 | */ |
| mbed_official | 610:813dcc80987e | 391 | #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0) ? 1 : 0) |
| mbed_official | 610:813dcc80987e | 392 | |
| mbed_official | 610:813dcc80987e | 393 | /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. |
| mbed_official | 610:813dcc80987e | 394 | */ |
| mbed_official | 610:813dcc80987e | 395 | #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) |
| mbed_official | 610:813dcc80987e | 396 | |
| mbed_official | 610:813dcc80987e | 397 | /** @brief Fast-mode Plus driving capability enable/disable macros |
| mbed_official | 610:813dcc80987e | 398 | * @param __FASTMODEPLUS__: This parameter can be a value of : |
| mbed_official | 610:813dcc80987e | 399 | * @arg SYSCFG_FASTMODEPLUS_PB6: Fast-mode Plus driving capability activation on PB6 |
| mbed_official | 610:813dcc80987e | 400 | * @arg SYSCFG_FASTMODEPLUS_PB7: Fast-mode Plus driving capability activation on PB7 |
| mbed_official | 610:813dcc80987e | 401 | * @arg SYSCFG_FASTMODEPLUS_PB8: Fast-mode Plus driving capability activation on PB8 |
| mbed_official | 610:813dcc80987e | 402 | * @arg SYSCFG_FASTMODEPLUS_PB9: Fast-mode Plus driving capability activation on PB9 |
| mbed_official | 610:813dcc80987e | 403 | */ |
| mbed_official | 610:813dcc80987e | 404 | #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ |
| mbed_official | 610:813dcc80987e | 405 | SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ |
| mbed_official | 610:813dcc80987e | 406 | }while(0) |
| mbed_official | 610:813dcc80987e | 407 | |
| mbed_official | 610:813dcc80987e | 408 | #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ |
| mbed_official | 610:813dcc80987e | 409 | CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ |
| mbed_official | 610:813dcc80987e | 410 | }while(0) |
| mbed_official | 610:813dcc80987e | 411 | |
| mbed_official | 610:813dcc80987e | 412 | /** |
| mbed_official | 610:813dcc80987e | 413 | * @} |
| mbed_official | 610:813dcc80987e | 414 | */ |
| mbed_official | 610:813dcc80987e | 415 | |
| mbed_official | 610:813dcc80987e | 416 | /* Private macros ------------------------------------------------------------*/ |
| mbed_official | 610:813dcc80987e | 417 | /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros |
| mbed_official | 610:813dcc80987e | 418 | * @{ |
| mbed_official | 610:813dcc80987e | 419 | */ |
| mbed_official | 610:813dcc80987e | 420 | |
| mbed_official | 610:813dcc80987e | 421 | #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ |
| mbed_official | 610:813dcc80987e | 422 | (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ |
| mbed_official | 610:813dcc80987e | 423 | (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ |
| mbed_official | 610:813dcc80987e | 424 | (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ |
| mbed_official | 610:813dcc80987e | 425 | (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ |
| mbed_official | 610:813dcc80987e | 426 | (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) |
| mbed_official | 610:813dcc80987e | 427 | |
| mbed_official | 610:813dcc80987e | 428 | #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ |
| mbed_official | 610:813dcc80987e | 429 | ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ |
| mbed_official | 610:813dcc80987e | 430 | ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ |
| mbed_official | 610:813dcc80987e | 431 | ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) |
| mbed_official | 610:813dcc80987e | 432 | |
| mbed_official | 610:813dcc80987e | 433 | #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= 0xFFFFFFFF)) |
| mbed_official | 610:813dcc80987e | 434 | |
| mbed_official | 610:813dcc80987e | 435 | #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ |
| mbed_official | 610:813dcc80987e | 436 | ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1)) |
| mbed_official | 610:813dcc80987e | 437 | |
| mbed_official | 610:813dcc80987e | 438 | #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ |
| mbed_official | 610:813dcc80987e | 439 | ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) |
| mbed_official | 610:813dcc80987e | 440 | |
| mbed_official | 610:813dcc80987e | 441 | #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) |
| mbed_official | 610:813dcc80987e | 442 | |
| mbed_official | 610:813dcc80987e | 443 | |
| mbed_official | 610:813dcc80987e | 444 | #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ |
| mbed_official | 610:813dcc80987e | 445 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ |
| mbed_official | 610:813dcc80987e | 446 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ |
| mbed_official | 610:813dcc80987e | 447 | (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) |
| mbed_official | 610:813dcc80987e | 448 | |
| mbed_official | 610:813dcc80987e | 449 | /** |
| mbed_official | 610:813dcc80987e | 450 | * @} |
| mbed_official | 610:813dcc80987e | 451 | */ |
| mbed_official | 610:813dcc80987e | 452 | |
| mbed_official | 610:813dcc80987e | 453 | /* Exported functions --------------------------------------------------------*/ |
| mbed_official | 610:813dcc80987e | 454 | |
| mbed_official | 610:813dcc80987e | 455 | /** @addtogroup HAL_Exported_Functions |
| mbed_official | 610:813dcc80987e | 456 | * @{ |
| mbed_official | 610:813dcc80987e | 457 | */ |
| mbed_official | 610:813dcc80987e | 458 | |
| mbed_official | 610:813dcc80987e | 459 | /** @addtogroup HAL_Exported_Functions_Group1 |
| mbed_official | 610:813dcc80987e | 460 | * @{ |
| mbed_official | 610:813dcc80987e | 461 | */ |
| mbed_official | 610:813dcc80987e | 462 | |
| mbed_official | 610:813dcc80987e | 463 | /* Initialization and de-initialization functions ******************************/ |
| mbed_official | 610:813dcc80987e | 464 | HAL_StatusTypeDef HAL_Init(void); |
| mbed_official | 610:813dcc80987e | 465 | HAL_StatusTypeDef HAL_DeInit(void); |
| mbed_official | 610:813dcc80987e | 466 | void HAL_MspInit(void); |
| mbed_official | 610:813dcc80987e | 467 | void HAL_MspDeInit(void); |
| mbed_official | 610:813dcc80987e | 468 | HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); |
| mbed_official | 610:813dcc80987e | 469 | |
| mbed_official | 610:813dcc80987e | 470 | /** |
| mbed_official | 610:813dcc80987e | 471 | * @} |
| mbed_official | 610:813dcc80987e | 472 | */ |
| mbed_official | 610:813dcc80987e | 473 | |
| mbed_official | 610:813dcc80987e | 474 | /** @addtogroup HAL_Exported_Functions_Group2 |
| mbed_official | 610:813dcc80987e | 475 | * @{ |
| mbed_official | 610:813dcc80987e | 476 | */ |
| mbed_official | 610:813dcc80987e | 477 | |
| mbed_official | 610:813dcc80987e | 478 | /* Peripheral Control functions ************************************************/ |
| mbed_official | 610:813dcc80987e | 479 | void HAL_IncTick(void); |
| mbed_official | 610:813dcc80987e | 480 | void HAL_Delay(uint32_t Delay); |
| mbed_official | 610:813dcc80987e | 481 | uint32_t HAL_GetTick(void); |
| mbed_official | 610:813dcc80987e | 482 | void HAL_SuspendTick(void); |
| mbed_official | 610:813dcc80987e | 483 | void HAL_ResumeTick(void); |
| mbed_official | 610:813dcc80987e | 484 | uint32_t HAL_GetHalVersion(void); |
| mbed_official | 610:813dcc80987e | 485 | uint32_t HAL_GetREVID(void); |
| mbed_official | 610:813dcc80987e | 486 | uint32_t HAL_GetDEVID(void); |
| mbed_official | 610:813dcc80987e | 487 | |
| mbed_official | 610:813dcc80987e | 488 | /** |
| mbed_official | 610:813dcc80987e | 489 | * @} |
| mbed_official | 610:813dcc80987e | 490 | */ |
| mbed_official | 610:813dcc80987e | 491 | |
| mbed_official | 610:813dcc80987e | 492 | /** @addtogroup HAL_Exported_Functions_Group3 |
| mbed_official | 610:813dcc80987e | 493 | * @{ |
| mbed_official | 610:813dcc80987e | 494 | */ |
| mbed_official | 610:813dcc80987e | 495 | |
| mbed_official | 610:813dcc80987e | 496 | /* DBGMCU Peripheral Control functions *****************************************/ |
| mbed_official | 610:813dcc80987e | 497 | void HAL_DBGMCU_EnableDBGSleepMode(void); |
| mbed_official | 610:813dcc80987e | 498 | void HAL_DBGMCU_DisableDBGSleepMode(void); |
| mbed_official | 610:813dcc80987e | 499 | void HAL_DBGMCU_EnableDBGStopMode(void); |
| mbed_official | 610:813dcc80987e | 500 | void HAL_DBGMCU_DisableDBGStopMode(void); |
| mbed_official | 610:813dcc80987e | 501 | void HAL_DBGMCU_EnableDBGStandbyMode(void); |
| mbed_official | 610:813dcc80987e | 502 | void HAL_DBGMCU_DisableDBGStandbyMode(void); |
| mbed_official | 610:813dcc80987e | 503 | |
| mbed_official | 610:813dcc80987e | 504 | /** |
| mbed_official | 610:813dcc80987e | 505 | * @} |
| mbed_official | 610:813dcc80987e | 506 | */ |
| mbed_official | 610:813dcc80987e | 507 | |
| mbed_official | 610:813dcc80987e | 508 | /** @addtogroup HAL_Exported_Functions_Group4 |
| mbed_official | 610:813dcc80987e | 509 | * @{ |
| mbed_official | 610:813dcc80987e | 510 | */ |
| mbed_official | 610:813dcc80987e | 511 | |
| mbed_official | 610:813dcc80987e | 512 | /* SYSCFG Control functions ****************************************************/ |
| mbed_official | 610:813dcc80987e | 513 | void HAL_SYSCFG_SRAM2Erase(void); |
| mbed_official | 610:813dcc80987e | 514 | void HAL_SYSCFG_EnableMemorySwappingBank(void); |
| mbed_official | 610:813dcc80987e | 515 | void HAL_SYSCFG_DisableMemorySwappingBank(void); |
| mbed_official | 610:813dcc80987e | 516 | |
| mbed_official | 610:813dcc80987e | 517 | void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); |
| mbed_official | 610:813dcc80987e | 518 | void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); |
| mbed_official | 610:813dcc80987e | 519 | void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); |
| mbed_official | 610:813dcc80987e | 520 | HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); |
| mbed_official | 610:813dcc80987e | 521 | void HAL_SYSCFG_DisableVREFBUF(void); |
| mbed_official | 610:813dcc80987e | 522 | |
| mbed_official | 610:813dcc80987e | 523 | /** |
| mbed_official | 610:813dcc80987e | 524 | * @} |
| mbed_official | 610:813dcc80987e | 525 | */ |
| mbed_official | 610:813dcc80987e | 526 | |
| mbed_official | 610:813dcc80987e | 527 | /** |
| mbed_official | 610:813dcc80987e | 528 | * @} |
| mbed_official | 610:813dcc80987e | 529 | */ |
| mbed_official | 610:813dcc80987e | 530 | |
| mbed_official | 610:813dcc80987e | 531 | /** |
| mbed_official | 610:813dcc80987e | 532 | * @} |
| mbed_official | 610:813dcc80987e | 533 | */ |
| mbed_official | 610:813dcc80987e | 534 | |
| mbed_official | 610:813dcc80987e | 535 | /** |
| mbed_official | 610:813dcc80987e | 536 | * @} |
| mbed_official | 610:813dcc80987e | 537 | */ |
| mbed_official | 610:813dcc80987e | 538 | |
| mbed_official | 610:813dcc80987e | 539 | #ifdef __cplusplus |
| mbed_official | 610:813dcc80987e | 540 | } |
| mbed_official | 610:813dcc80987e | 541 | #endif |
| mbed_official | 610:813dcc80987e | 542 | |
| mbed_official | 610:813dcc80987e | 543 | #endif /* __STM32L4xx_HAL_H */ |
| mbed_official | 610:813dcc80987e | 544 | |
| mbed_official | 610:813dcc80987e | 545 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |