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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_sdram.c@637:ed69428d4850, 2015-12-22 (annotated)
- Committer:
- jaerts
- Date:
- Tue Dec 22 13:22:16 2015 +0000
- Revision:
- 637:ed69428d4850
- Parent:
- 610:813dcc80987e
Add very shady LPC1768 CAN Filter implementation
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 573:ad23fe03a082 | 1 | /** |
mbed_official | 573:ad23fe03a082 | 2 | ****************************************************************************** |
mbed_official | 573:ad23fe03a082 | 3 | * @file stm32f7xx_hal_sdram.c |
mbed_official | 573:ad23fe03a082 | 4 | * @author MCD Application Team |
mbed_official | 610:813dcc80987e | 5 | * @version V1.0.1 |
mbed_official | 610:813dcc80987e | 6 | * @date 25-June-2015 |
mbed_official | 573:ad23fe03a082 | 7 | * @brief SDRAM HAL module driver. |
mbed_official | 573:ad23fe03a082 | 8 | * This file provides a generic firmware to drive SDRAM memories mounted |
mbed_official | 573:ad23fe03a082 | 9 | * as external device. |
mbed_official | 573:ad23fe03a082 | 10 | * |
mbed_official | 573:ad23fe03a082 | 11 | @verbatim |
mbed_official | 573:ad23fe03a082 | 12 | ============================================================================== |
mbed_official | 573:ad23fe03a082 | 13 | ##### How to use this driver ##### |
mbed_official | 573:ad23fe03a082 | 14 | ============================================================================== |
mbed_official | 573:ad23fe03a082 | 15 | [..] |
mbed_official | 573:ad23fe03a082 | 16 | This driver is a generic layered driver which contains a set of APIs used to |
mbed_official | 573:ad23fe03a082 | 17 | control SDRAM memories. It uses the FMC layer functions to interface |
mbed_official | 573:ad23fe03a082 | 18 | with SDRAM devices. |
mbed_official | 573:ad23fe03a082 | 19 | The following sequence should be followed to configure the FMC to interface |
mbed_official | 573:ad23fe03a082 | 20 | with SDRAM memories: |
mbed_official | 573:ad23fe03a082 | 21 | |
mbed_official | 573:ad23fe03a082 | 22 | (#) Declare a SDRAM_HandleTypeDef handle structure, for example: |
mbed_official | 573:ad23fe03a082 | 23 | SDRAM_HandleTypeDef hdsram |
mbed_official | 573:ad23fe03a082 | 24 | |
mbed_official | 573:ad23fe03a082 | 25 | (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed |
mbed_official | 573:ad23fe03a082 | 26 | values of the structure member. |
mbed_official | 573:ad23fe03a082 | 27 | |
mbed_official | 573:ad23fe03a082 | 28 | (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined |
mbed_official | 573:ad23fe03a082 | 29 | base register instance for NOR or SDRAM device |
mbed_official | 573:ad23fe03a082 | 30 | |
mbed_official | 573:ad23fe03a082 | 31 | (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example: |
mbed_official | 573:ad23fe03a082 | 32 | FMC_SDRAM_TimingTypeDef Timing; |
mbed_official | 573:ad23fe03a082 | 33 | and fill its fields with the allowed values of the structure member. |
mbed_official | 573:ad23fe03a082 | 34 | |
mbed_official | 573:ad23fe03a082 | 35 | (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function |
mbed_official | 573:ad23fe03a082 | 36 | performs the following sequence: |
mbed_official | 573:ad23fe03a082 | 37 | |
mbed_official | 573:ad23fe03a082 | 38 | (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit() |
mbed_official | 573:ad23fe03a082 | 39 | (##) Control register configuration using the FMC SDRAM interface function |
mbed_official | 573:ad23fe03a082 | 40 | FMC_SDRAM_Init() |
mbed_official | 573:ad23fe03a082 | 41 | (##) Timing register configuration using the FMC SDRAM interface function |
mbed_official | 573:ad23fe03a082 | 42 | FMC_SDRAM_Timing_Init() |
mbed_official | 573:ad23fe03a082 | 43 | (##) Program the SDRAM external device by applying its initialization sequence |
mbed_official | 573:ad23fe03a082 | 44 | according to the device plugged in your hardware. This step is mandatory |
mbed_official | 573:ad23fe03a082 | 45 | for accessing the SDRAM device. |
mbed_official | 573:ad23fe03a082 | 46 | |
mbed_official | 573:ad23fe03a082 | 47 | (#) At this stage you can perform read/write accesses from/to the memory connected |
mbed_official | 573:ad23fe03a082 | 48 | to the SDRAM Bank. You can perform either polling or DMA transfer using the |
mbed_official | 573:ad23fe03a082 | 49 | following APIs: |
mbed_official | 573:ad23fe03a082 | 50 | (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access |
mbed_official | 573:ad23fe03a082 | 51 | (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer |
mbed_official | 573:ad23fe03a082 | 52 | |
mbed_official | 573:ad23fe03a082 | 53 | (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/ |
mbed_official | 573:ad23fe03a082 | 54 | HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or |
mbed_official | 573:ad23fe03a082 | 55 | the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM |
mbed_official | 573:ad23fe03a082 | 56 | device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef |
mbed_official | 573:ad23fe03a082 | 57 | structure. |
mbed_official | 573:ad23fe03a082 | 58 | |
mbed_official | 573:ad23fe03a082 | 59 | (#) You can continuously monitor the SDRAM device HAL state by calling the function |
mbed_official | 573:ad23fe03a082 | 60 | HAL_SDRAM_GetState() |
mbed_official | 573:ad23fe03a082 | 61 | |
mbed_official | 573:ad23fe03a082 | 62 | @endverbatim |
mbed_official | 573:ad23fe03a082 | 63 | ****************************************************************************** |
mbed_official | 573:ad23fe03a082 | 64 | * @attention |
mbed_official | 573:ad23fe03a082 | 65 | * |
mbed_official | 573:ad23fe03a082 | 66 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
mbed_official | 573:ad23fe03a082 | 67 | * |
mbed_official | 573:ad23fe03a082 | 68 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 573:ad23fe03a082 | 69 | * are permitted provided that the following conditions are met: |
mbed_official | 573:ad23fe03a082 | 70 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 573:ad23fe03a082 | 71 | * this list of conditions and the following disclaimer. |
mbed_official | 573:ad23fe03a082 | 72 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 573:ad23fe03a082 | 73 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 573:ad23fe03a082 | 74 | * and/or other materials provided with the distribution. |
mbed_official | 573:ad23fe03a082 | 75 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 573:ad23fe03a082 | 76 | * may be used to endorse or promote products derived from this software |
mbed_official | 573:ad23fe03a082 | 77 | * without specific prior written permission. |
mbed_official | 573:ad23fe03a082 | 78 | * |
mbed_official | 573:ad23fe03a082 | 79 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 573:ad23fe03a082 | 80 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 573:ad23fe03a082 | 81 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 573:ad23fe03a082 | 82 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 573:ad23fe03a082 | 83 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 573:ad23fe03a082 | 84 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 573:ad23fe03a082 | 85 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 573:ad23fe03a082 | 86 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 573:ad23fe03a082 | 87 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 573:ad23fe03a082 | 88 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 573:ad23fe03a082 | 89 | * |
mbed_official | 573:ad23fe03a082 | 90 | ****************************************************************************** |
mbed_official | 573:ad23fe03a082 | 91 | */ |
mbed_official | 573:ad23fe03a082 | 92 | |
mbed_official | 573:ad23fe03a082 | 93 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 94 | #include "stm32f7xx_hal.h" |
mbed_official | 573:ad23fe03a082 | 95 | |
mbed_official | 573:ad23fe03a082 | 96 | /** @addtogroup STM32F7xx_HAL_Driver |
mbed_official | 573:ad23fe03a082 | 97 | * @{ |
mbed_official | 573:ad23fe03a082 | 98 | */ |
mbed_official | 573:ad23fe03a082 | 99 | |
mbed_official | 573:ad23fe03a082 | 100 | /** @defgroup SDRAM SDRAM |
mbed_official | 573:ad23fe03a082 | 101 | * @brief SDRAM driver modules |
mbed_official | 573:ad23fe03a082 | 102 | * @{ |
mbed_official | 573:ad23fe03a082 | 103 | */ |
mbed_official | 573:ad23fe03a082 | 104 | #ifdef HAL_SDRAM_MODULE_ENABLED |
mbed_official | 573:ad23fe03a082 | 105 | |
mbed_official | 573:ad23fe03a082 | 106 | /* Private typedef -----------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 107 | /* Private define ------------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 108 | /* Private macro -------------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 109 | /* Private variables ---------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 110 | /* Private functions ---------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 111 | /* Exported functions --------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 112 | /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions |
mbed_official | 573:ad23fe03a082 | 113 | * @{ |
mbed_official | 573:ad23fe03a082 | 114 | */ |
mbed_official | 573:ad23fe03a082 | 115 | |
mbed_official | 573:ad23fe03a082 | 116 | /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions |
mbed_official | 573:ad23fe03a082 | 117 | * @brief Initialization and Configuration functions |
mbed_official | 573:ad23fe03a082 | 118 | * |
mbed_official | 573:ad23fe03a082 | 119 | @verbatim |
mbed_official | 573:ad23fe03a082 | 120 | ============================================================================== |
mbed_official | 573:ad23fe03a082 | 121 | ##### SDRAM Initialization and de_initialization functions ##### |
mbed_official | 573:ad23fe03a082 | 122 | ============================================================================== |
mbed_official | 573:ad23fe03a082 | 123 | [..] |
mbed_official | 573:ad23fe03a082 | 124 | This section provides functions allowing to initialize/de-initialize |
mbed_official | 573:ad23fe03a082 | 125 | the SDRAM memory |
mbed_official | 573:ad23fe03a082 | 126 | |
mbed_official | 573:ad23fe03a082 | 127 | @endverbatim |
mbed_official | 573:ad23fe03a082 | 128 | * @{ |
mbed_official | 573:ad23fe03a082 | 129 | */ |
mbed_official | 573:ad23fe03a082 | 130 | |
mbed_official | 573:ad23fe03a082 | 131 | /** |
mbed_official | 573:ad23fe03a082 | 132 | * @brief Performs the SDRAM device initialization sequence. |
mbed_official | 573:ad23fe03a082 | 133 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 134 | * the configuration information for SDRAM module. |
mbed_official | 573:ad23fe03a082 | 135 | * @param Timing: Pointer to SDRAM control timing structure |
mbed_official | 573:ad23fe03a082 | 136 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 137 | */ |
mbed_official | 573:ad23fe03a082 | 138 | HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) |
mbed_official | 573:ad23fe03a082 | 139 | { |
mbed_official | 573:ad23fe03a082 | 140 | /* Check the SDRAM handle parameter */ |
mbed_official | 573:ad23fe03a082 | 141 | if(hsdram == NULL) |
mbed_official | 573:ad23fe03a082 | 142 | { |
mbed_official | 573:ad23fe03a082 | 143 | return HAL_ERROR; |
mbed_official | 573:ad23fe03a082 | 144 | } |
mbed_official | 573:ad23fe03a082 | 145 | |
mbed_official | 573:ad23fe03a082 | 146 | if(hsdram->State == HAL_SDRAM_STATE_RESET) |
mbed_official | 573:ad23fe03a082 | 147 | { |
mbed_official | 573:ad23fe03a082 | 148 | /* Allocate lock resource and initialize it */ |
mbed_official | 573:ad23fe03a082 | 149 | hsdram->Lock = HAL_UNLOCKED; |
mbed_official | 573:ad23fe03a082 | 150 | /* Initialize the low level hardware (MSP) */ |
mbed_official | 573:ad23fe03a082 | 151 | HAL_SDRAM_MspInit(hsdram); |
mbed_official | 573:ad23fe03a082 | 152 | } |
mbed_official | 573:ad23fe03a082 | 153 | |
mbed_official | 573:ad23fe03a082 | 154 | /* Initialize the SDRAM controller state */ |
mbed_official | 573:ad23fe03a082 | 155 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
mbed_official | 573:ad23fe03a082 | 156 | |
mbed_official | 573:ad23fe03a082 | 157 | /* Initialize SDRAM control Interface */ |
mbed_official | 573:ad23fe03a082 | 158 | FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); |
mbed_official | 573:ad23fe03a082 | 159 | |
mbed_official | 573:ad23fe03a082 | 160 | /* Initialize SDRAM timing Interface */ |
mbed_official | 573:ad23fe03a082 | 161 | FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); |
mbed_official | 573:ad23fe03a082 | 162 | |
mbed_official | 573:ad23fe03a082 | 163 | /* Update the SDRAM controller state */ |
mbed_official | 573:ad23fe03a082 | 164 | hsdram->State = HAL_SDRAM_STATE_READY; |
mbed_official | 573:ad23fe03a082 | 165 | |
mbed_official | 573:ad23fe03a082 | 166 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 167 | } |
mbed_official | 573:ad23fe03a082 | 168 | |
mbed_official | 573:ad23fe03a082 | 169 | /** |
mbed_official | 573:ad23fe03a082 | 170 | * @brief Perform the SDRAM device initialization sequence. |
mbed_official | 573:ad23fe03a082 | 171 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 172 | * the configuration information for SDRAM module. |
mbed_official | 573:ad23fe03a082 | 173 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 174 | */ |
mbed_official | 573:ad23fe03a082 | 175 | HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) |
mbed_official | 573:ad23fe03a082 | 176 | { |
mbed_official | 573:ad23fe03a082 | 177 | /* Initialize the low level hardware (MSP) */ |
mbed_official | 573:ad23fe03a082 | 178 | HAL_SDRAM_MspDeInit(hsdram); |
mbed_official | 573:ad23fe03a082 | 179 | |
mbed_official | 573:ad23fe03a082 | 180 | /* Configure the SDRAM registers with their reset values */ |
mbed_official | 573:ad23fe03a082 | 181 | FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank); |
mbed_official | 573:ad23fe03a082 | 182 | |
mbed_official | 573:ad23fe03a082 | 183 | /* Reset the SDRAM controller state */ |
mbed_official | 573:ad23fe03a082 | 184 | hsdram->State = HAL_SDRAM_STATE_RESET; |
mbed_official | 573:ad23fe03a082 | 185 | |
mbed_official | 573:ad23fe03a082 | 186 | /* Release Lock */ |
mbed_official | 573:ad23fe03a082 | 187 | __HAL_UNLOCK(hsdram); |
mbed_official | 573:ad23fe03a082 | 188 | |
mbed_official | 573:ad23fe03a082 | 189 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 190 | } |
mbed_official | 573:ad23fe03a082 | 191 | |
mbed_official | 573:ad23fe03a082 | 192 | /** |
mbed_official | 573:ad23fe03a082 | 193 | * @brief SDRAM MSP Init. |
mbed_official | 573:ad23fe03a082 | 194 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 195 | * the configuration information for SDRAM module. |
mbed_official | 573:ad23fe03a082 | 196 | * @retval None |
mbed_official | 573:ad23fe03a082 | 197 | */ |
mbed_official | 573:ad23fe03a082 | 198 | __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) |
mbed_official | 573:ad23fe03a082 | 199 | { |
mbed_official | 573:ad23fe03a082 | 200 | /* NOTE: This function Should not be modified, when the callback is needed, |
mbed_official | 573:ad23fe03a082 | 201 | the HAL_SDRAM_MspInit could be implemented in the user file |
mbed_official | 573:ad23fe03a082 | 202 | */ |
mbed_official | 573:ad23fe03a082 | 203 | } |
mbed_official | 573:ad23fe03a082 | 204 | |
mbed_official | 573:ad23fe03a082 | 205 | /** |
mbed_official | 573:ad23fe03a082 | 206 | * @brief SDRAM MSP DeInit. |
mbed_official | 573:ad23fe03a082 | 207 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 208 | * the configuration information for SDRAM module. |
mbed_official | 573:ad23fe03a082 | 209 | * @retval None |
mbed_official | 573:ad23fe03a082 | 210 | */ |
mbed_official | 573:ad23fe03a082 | 211 | __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) |
mbed_official | 573:ad23fe03a082 | 212 | { |
mbed_official | 573:ad23fe03a082 | 213 | /* NOTE: This function Should not be modified, when the callback is needed, |
mbed_official | 573:ad23fe03a082 | 214 | the HAL_SDRAM_MspDeInit could be implemented in the user file |
mbed_official | 573:ad23fe03a082 | 215 | */ |
mbed_official | 573:ad23fe03a082 | 216 | } |
mbed_official | 573:ad23fe03a082 | 217 | |
mbed_official | 573:ad23fe03a082 | 218 | /** |
mbed_official | 573:ad23fe03a082 | 219 | * @brief This function handles SDRAM refresh error interrupt request. |
mbed_official | 573:ad23fe03a082 | 220 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 221 | * the configuration information for SDRAM module. |
mbed_official | 573:ad23fe03a082 | 222 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 223 | */ |
mbed_official | 573:ad23fe03a082 | 224 | void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) |
mbed_official | 573:ad23fe03a082 | 225 | { |
mbed_official | 573:ad23fe03a082 | 226 | /* Check SDRAM interrupt Rising edge flag */ |
mbed_official | 573:ad23fe03a082 | 227 | if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT)) |
mbed_official | 573:ad23fe03a082 | 228 | { |
mbed_official | 573:ad23fe03a082 | 229 | /* SDRAM refresh error interrupt callback */ |
mbed_official | 573:ad23fe03a082 | 230 | HAL_SDRAM_RefreshErrorCallback(hsdram); |
mbed_official | 573:ad23fe03a082 | 231 | |
mbed_official | 573:ad23fe03a082 | 232 | /* Clear SDRAM refresh error interrupt pending bit */ |
mbed_official | 573:ad23fe03a082 | 233 | __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR); |
mbed_official | 573:ad23fe03a082 | 234 | } |
mbed_official | 573:ad23fe03a082 | 235 | } |
mbed_official | 573:ad23fe03a082 | 236 | |
mbed_official | 573:ad23fe03a082 | 237 | /** |
mbed_official | 573:ad23fe03a082 | 238 | * @brief SDRAM Refresh error callback. |
mbed_official | 573:ad23fe03a082 | 239 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 240 | * the configuration information for SDRAM module. |
mbed_official | 573:ad23fe03a082 | 241 | * @retval None |
mbed_official | 573:ad23fe03a082 | 242 | */ |
mbed_official | 573:ad23fe03a082 | 243 | __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram) |
mbed_official | 573:ad23fe03a082 | 244 | { |
mbed_official | 573:ad23fe03a082 | 245 | /* NOTE: This function Should not be modified, when the callback is needed, |
mbed_official | 573:ad23fe03a082 | 246 | the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file |
mbed_official | 573:ad23fe03a082 | 247 | */ |
mbed_official | 573:ad23fe03a082 | 248 | } |
mbed_official | 573:ad23fe03a082 | 249 | |
mbed_official | 573:ad23fe03a082 | 250 | /** |
mbed_official | 573:ad23fe03a082 | 251 | * @brief DMA transfer complete callback. |
mbed_official | 573:ad23fe03a082 | 252 | * @param hdma: pointer to a DMA_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 253 | * the configuration information for the specified DMA module. |
mbed_official | 573:ad23fe03a082 | 254 | * @retval None |
mbed_official | 573:ad23fe03a082 | 255 | */ |
mbed_official | 573:ad23fe03a082 | 256 | __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) |
mbed_official | 573:ad23fe03a082 | 257 | { |
mbed_official | 573:ad23fe03a082 | 258 | /* NOTE: This function Should not be modified, when the callback is needed, |
mbed_official | 573:ad23fe03a082 | 259 | the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file |
mbed_official | 573:ad23fe03a082 | 260 | */ |
mbed_official | 573:ad23fe03a082 | 261 | } |
mbed_official | 573:ad23fe03a082 | 262 | |
mbed_official | 573:ad23fe03a082 | 263 | /** |
mbed_official | 573:ad23fe03a082 | 264 | * @brief DMA transfer complete error callback. |
mbed_official | 573:ad23fe03a082 | 265 | * @param hdma: DMA handle |
mbed_official | 573:ad23fe03a082 | 266 | * @retval None |
mbed_official | 573:ad23fe03a082 | 267 | */ |
mbed_official | 573:ad23fe03a082 | 268 | __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) |
mbed_official | 573:ad23fe03a082 | 269 | { |
mbed_official | 573:ad23fe03a082 | 270 | /* NOTE: This function Should not be modified, when the callback is needed, |
mbed_official | 573:ad23fe03a082 | 271 | the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file |
mbed_official | 573:ad23fe03a082 | 272 | */ |
mbed_official | 573:ad23fe03a082 | 273 | } |
mbed_official | 573:ad23fe03a082 | 274 | |
mbed_official | 573:ad23fe03a082 | 275 | /** |
mbed_official | 573:ad23fe03a082 | 276 | * @} |
mbed_official | 573:ad23fe03a082 | 277 | */ |
mbed_official | 573:ad23fe03a082 | 278 | |
mbed_official | 573:ad23fe03a082 | 279 | /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions |
mbed_official | 573:ad23fe03a082 | 280 | * @brief Input Output and memory control functions |
mbed_official | 573:ad23fe03a082 | 281 | * |
mbed_official | 573:ad23fe03a082 | 282 | @verbatim |
mbed_official | 573:ad23fe03a082 | 283 | ============================================================================== |
mbed_official | 573:ad23fe03a082 | 284 | ##### SDRAM Input and Output functions ##### |
mbed_official | 573:ad23fe03a082 | 285 | ============================================================================== |
mbed_official | 573:ad23fe03a082 | 286 | [..] |
mbed_official | 573:ad23fe03a082 | 287 | This section provides functions allowing to use and control the SDRAM memory |
mbed_official | 573:ad23fe03a082 | 288 | |
mbed_official | 573:ad23fe03a082 | 289 | @endverbatim |
mbed_official | 573:ad23fe03a082 | 290 | * @{ |
mbed_official | 573:ad23fe03a082 | 291 | */ |
mbed_official | 573:ad23fe03a082 | 292 | |
mbed_official | 573:ad23fe03a082 | 293 | /** |
mbed_official | 573:ad23fe03a082 | 294 | * @brief Reads 8-bit data buffer from the SDRAM memory. |
mbed_official | 573:ad23fe03a082 | 295 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 296 | * the configuration information for SDRAM module. |
mbed_official | 573:ad23fe03a082 | 297 | * @param pAddress: Pointer to read start address |
mbed_official | 573:ad23fe03a082 | 298 | * @param pDstBuffer: Pointer to destination buffer |
mbed_official | 573:ad23fe03a082 | 299 | * @param BufferSize: Size of the buffer to read from memory |
mbed_official | 573:ad23fe03a082 | 300 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 301 | */ |
mbed_official | 573:ad23fe03a082 | 302 | HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) |
mbed_official | 573:ad23fe03a082 | 303 | { |
mbed_official | 573:ad23fe03a082 | 304 | __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; |
mbed_official | 573:ad23fe03a082 | 305 | |
mbed_official | 573:ad23fe03a082 | 306 | /* Process Locked */ |
mbed_official | 573:ad23fe03a082 | 307 | __HAL_LOCK(hsdram); |
mbed_official | 573:ad23fe03a082 | 308 | |
mbed_official | 573:ad23fe03a082 | 309 | /* Check the SDRAM controller state */ |
mbed_official | 573:ad23fe03a082 | 310 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
mbed_official | 573:ad23fe03a082 | 311 | { |
mbed_official | 573:ad23fe03a082 | 312 | return HAL_BUSY; |
mbed_official | 573:ad23fe03a082 | 313 | } |
mbed_official | 573:ad23fe03a082 | 314 | else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) |
mbed_official | 573:ad23fe03a082 | 315 | { |
mbed_official | 573:ad23fe03a082 | 316 | return HAL_ERROR; |
mbed_official | 573:ad23fe03a082 | 317 | } |
mbed_official | 573:ad23fe03a082 | 318 | |
mbed_official | 573:ad23fe03a082 | 319 | /* Read data from source */ |
mbed_official | 573:ad23fe03a082 | 320 | for(; BufferSize != 0; BufferSize--) |
mbed_official | 573:ad23fe03a082 | 321 | { |
mbed_official | 573:ad23fe03a082 | 322 | *pDstBuffer = *(__IO uint8_t *)pSdramAddress; |
mbed_official | 573:ad23fe03a082 | 323 | pDstBuffer++; |
mbed_official | 573:ad23fe03a082 | 324 | pSdramAddress++; |
mbed_official | 573:ad23fe03a082 | 325 | } |
mbed_official | 573:ad23fe03a082 | 326 | |
mbed_official | 573:ad23fe03a082 | 327 | /* Process Unlocked */ |
mbed_official | 573:ad23fe03a082 | 328 | __HAL_UNLOCK(hsdram); |
mbed_official | 573:ad23fe03a082 | 329 | |
mbed_official | 573:ad23fe03a082 | 330 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 331 | } |
mbed_official | 573:ad23fe03a082 | 332 | |
mbed_official | 573:ad23fe03a082 | 333 | |
mbed_official | 573:ad23fe03a082 | 334 | /** |
mbed_official | 573:ad23fe03a082 | 335 | * @brief Writes 8-bit data buffer to SDRAM memory. |
mbed_official | 573:ad23fe03a082 | 336 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 337 | * the configuration information for SDRAM module. |
mbed_official | 573:ad23fe03a082 | 338 | * @param pAddress: Pointer to write start address |
mbed_official | 573:ad23fe03a082 | 339 | * @param pSrcBuffer: Pointer to source buffer to write |
mbed_official | 573:ad23fe03a082 | 340 | * @param BufferSize: Size of the buffer to write to memory |
mbed_official | 573:ad23fe03a082 | 341 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 342 | */ |
mbed_official | 573:ad23fe03a082 | 343 | HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) |
mbed_official | 573:ad23fe03a082 | 344 | { |
mbed_official | 573:ad23fe03a082 | 345 | __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; |
mbed_official | 573:ad23fe03a082 | 346 | uint32_t tmp = 0; |
mbed_official | 573:ad23fe03a082 | 347 | |
mbed_official | 573:ad23fe03a082 | 348 | /* Process Locked */ |
mbed_official | 573:ad23fe03a082 | 349 | __HAL_LOCK(hsdram); |
mbed_official | 573:ad23fe03a082 | 350 | |
mbed_official | 573:ad23fe03a082 | 351 | /* Check the SDRAM controller state */ |
mbed_official | 573:ad23fe03a082 | 352 | tmp = hsdram->State; |
mbed_official | 573:ad23fe03a082 | 353 | |
mbed_official | 573:ad23fe03a082 | 354 | if(tmp == HAL_SDRAM_STATE_BUSY) |
mbed_official | 573:ad23fe03a082 | 355 | { |
mbed_official | 573:ad23fe03a082 | 356 | return HAL_BUSY; |
mbed_official | 573:ad23fe03a082 | 357 | } |
mbed_official | 573:ad23fe03a082 | 358 | else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) |
mbed_official | 573:ad23fe03a082 | 359 | { |
mbed_official | 573:ad23fe03a082 | 360 | return HAL_ERROR; |
mbed_official | 573:ad23fe03a082 | 361 | } |
mbed_official | 573:ad23fe03a082 | 362 | |
mbed_official | 573:ad23fe03a082 | 363 | /* Write data to memory */ |
mbed_official | 573:ad23fe03a082 | 364 | for(; BufferSize != 0; BufferSize--) |
mbed_official | 573:ad23fe03a082 | 365 | { |
mbed_official | 573:ad23fe03a082 | 366 | *(__IO uint8_t *)pSdramAddress = *pSrcBuffer; |
mbed_official | 573:ad23fe03a082 | 367 | pSrcBuffer++; |
mbed_official | 573:ad23fe03a082 | 368 | pSdramAddress++; |
mbed_official | 573:ad23fe03a082 | 369 | } |
mbed_official | 573:ad23fe03a082 | 370 | |
mbed_official | 573:ad23fe03a082 | 371 | /* Process Unlocked */ |
mbed_official | 573:ad23fe03a082 | 372 | __HAL_UNLOCK(hsdram); |
mbed_official | 573:ad23fe03a082 | 373 | |
mbed_official | 573:ad23fe03a082 | 374 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 375 | } |
mbed_official | 573:ad23fe03a082 | 376 | |
mbed_official | 573:ad23fe03a082 | 377 | |
mbed_official | 573:ad23fe03a082 | 378 | /** |
mbed_official | 573:ad23fe03a082 | 379 | * @brief Reads 16-bit data buffer from the SDRAM memory. |
mbed_official | 573:ad23fe03a082 | 380 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 381 | * the configuration information for SDRAM module. |
mbed_official | 573:ad23fe03a082 | 382 | * @param pAddress: Pointer to read start address |
mbed_official | 573:ad23fe03a082 | 383 | * @param pDstBuffer: Pointer to destination buffer |
mbed_official | 573:ad23fe03a082 | 384 | * @param BufferSize: Size of the buffer to read from memory |
mbed_official | 573:ad23fe03a082 | 385 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 386 | */ |
mbed_official | 573:ad23fe03a082 | 387 | HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) |
mbed_official | 573:ad23fe03a082 | 388 | { |
mbed_official | 573:ad23fe03a082 | 389 | __IO uint16_t *pSdramAddress = (uint16_t *)pAddress; |
mbed_official | 573:ad23fe03a082 | 390 | |
mbed_official | 573:ad23fe03a082 | 391 | /* Process Locked */ |
mbed_official | 573:ad23fe03a082 | 392 | __HAL_LOCK(hsdram); |
mbed_official | 573:ad23fe03a082 | 393 | |
mbed_official | 573:ad23fe03a082 | 394 | /* Check the SDRAM controller state */ |
mbed_official | 573:ad23fe03a082 | 395 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
mbed_official | 573:ad23fe03a082 | 396 | { |
mbed_official | 573:ad23fe03a082 | 397 | return HAL_BUSY; |
mbed_official | 573:ad23fe03a082 | 398 | } |
mbed_official | 573:ad23fe03a082 | 399 | else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) |
mbed_official | 573:ad23fe03a082 | 400 | { |
mbed_official | 573:ad23fe03a082 | 401 | return HAL_ERROR; |
mbed_official | 573:ad23fe03a082 | 402 | } |
mbed_official | 573:ad23fe03a082 | 403 | |
mbed_official | 573:ad23fe03a082 | 404 | /* Read data from source */ |
mbed_official | 573:ad23fe03a082 | 405 | for(; BufferSize != 0; BufferSize--) |
mbed_official | 573:ad23fe03a082 | 406 | { |
mbed_official | 573:ad23fe03a082 | 407 | *pDstBuffer = *(__IO uint16_t *)pSdramAddress; |
mbed_official | 573:ad23fe03a082 | 408 | pDstBuffer++; |
mbed_official | 573:ad23fe03a082 | 409 | pSdramAddress++; |
mbed_official | 573:ad23fe03a082 | 410 | } |
mbed_official | 573:ad23fe03a082 | 411 | |
mbed_official | 573:ad23fe03a082 | 412 | /* Process Unlocked */ |
mbed_official | 573:ad23fe03a082 | 413 | __HAL_UNLOCK(hsdram); |
mbed_official | 573:ad23fe03a082 | 414 | |
mbed_official | 573:ad23fe03a082 | 415 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 416 | } |
mbed_official | 573:ad23fe03a082 | 417 | |
mbed_official | 573:ad23fe03a082 | 418 | /** |
mbed_official | 573:ad23fe03a082 | 419 | * @brief Writes 16-bit data buffer to SDRAM memory. |
mbed_official | 573:ad23fe03a082 | 420 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 421 | * the configuration information for SDRAM module. |
mbed_official | 573:ad23fe03a082 | 422 | * @param pAddress: Pointer to write start address |
mbed_official | 573:ad23fe03a082 | 423 | * @param pSrcBuffer: Pointer to source buffer to write |
mbed_official | 573:ad23fe03a082 | 424 | * @param BufferSize: Size of the buffer to write to memory |
mbed_official | 573:ad23fe03a082 | 425 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 426 | */ |
mbed_official | 573:ad23fe03a082 | 427 | HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) |
mbed_official | 573:ad23fe03a082 | 428 | { |
mbed_official | 573:ad23fe03a082 | 429 | __IO uint16_t *pSdramAddress = (uint16_t *)pAddress; |
mbed_official | 573:ad23fe03a082 | 430 | uint32_t tmp = 0; |
mbed_official | 573:ad23fe03a082 | 431 | |
mbed_official | 573:ad23fe03a082 | 432 | /* Process Locked */ |
mbed_official | 573:ad23fe03a082 | 433 | __HAL_LOCK(hsdram); |
mbed_official | 573:ad23fe03a082 | 434 | |
mbed_official | 573:ad23fe03a082 | 435 | /* Check the SDRAM controller state */ |
mbed_official | 573:ad23fe03a082 | 436 | tmp = hsdram->State; |
mbed_official | 573:ad23fe03a082 | 437 | |
mbed_official | 573:ad23fe03a082 | 438 | if(tmp == HAL_SDRAM_STATE_BUSY) |
mbed_official | 573:ad23fe03a082 | 439 | { |
mbed_official | 573:ad23fe03a082 | 440 | return HAL_BUSY; |
mbed_official | 573:ad23fe03a082 | 441 | } |
mbed_official | 573:ad23fe03a082 | 442 | else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) |
mbed_official | 573:ad23fe03a082 | 443 | { |
mbed_official | 573:ad23fe03a082 | 444 | return HAL_ERROR; |
mbed_official | 573:ad23fe03a082 | 445 | } |
mbed_official | 573:ad23fe03a082 | 446 | |
mbed_official | 573:ad23fe03a082 | 447 | /* Write data to memory */ |
mbed_official | 573:ad23fe03a082 | 448 | for(; BufferSize != 0; BufferSize--) |
mbed_official | 573:ad23fe03a082 | 449 | { |
mbed_official | 573:ad23fe03a082 | 450 | *(__IO uint16_t *)pSdramAddress = *pSrcBuffer; |
mbed_official | 573:ad23fe03a082 | 451 | pSrcBuffer++; |
mbed_official | 573:ad23fe03a082 | 452 | pSdramAddress++; |
mbed_official | 573:ad23fe03a082 | 453 | } |
mbed_official | 573:ad23fe03a082 | 454 | |
mbed_official | 573:ad23fe03a082 | 455 | /* Process Unlocked */ |
mbed_official | 573:ad23fe03a082 | 456 | __HAL_UNLOCK(hsdram); |
mbed_official | 573:ad23fe03a082 | 457 | |
mbed_official | 573:ad23fe03a082 | 458 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 459 | } |
mbed_official | 573:ad23fe03a082 | 460 | |
mbed_official | 573:ad23fe03a082 | 461 | /** |
mbed_official | 573:ad23fe03a082 | 462 | * @brief Reads 32-bit data buffer from the SDRAM memory. |
mbed_official | 573:ad23fe03a082 | 463 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 464 | * the configuration information for SDRAM module. |
mbed_official | 573:ad23fe03a082 | 465 | * @param pAddress: Pointer to read start address |
mbed_official | 573:ad23fe03a082 | 466 | * @param pDstBuffer: Pointer to destination buffer |
mbed_official | 573:ad23fe03a082 | 467 | * @param BufferSize: Size of the buffer to read from memory |
mbed_official | 573:ad23fe03a082 | 468 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 469 | */ |
mbed_official | 573:ad23fe03a082 | 470 | HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) |
mbed_official | 573:ad23fe03a082 | 471 | { |
mbed_official | 573:ad23fe03a082 | 472 | __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; |
mbed_official | 573:ad23fe03a082 | 473 | |
mbed_official | 573:ad23fe03a082 | 474 | /* Process Locked */ |
mbed_official | 573:ad23fe03a082 | 475 | __HAL_LOCK(hsdram); |
mbed_official | 573:ad23fe03a082 | 476 | |
mbed_official | 573:ad23fe03a082 | 477 | /* Check the SDRAM controller state */ |
mbed_official | 573:ad23fe03a082 | 478 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
mbed_official | 573:ad23fe03a082 | 479 | { |
mbed_official | 573:ad23fe03a082 | 480 | return HAL_BUSY; |
mbed_official | 573:ad23fe03a082 | 481 | } |
mbed_official | 573:ad23fe03a082 | 482 | else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) |
mbed_official | 573:ad23fe03a082 | 483 | { |
mbed_official | 573:ad23fe03a082 | 484 | return HAL_ERROR; |
mbed_official | 573:ad23fe03a082 | 485 | } |
mbed_official | 573:ad23fe03a082 | 486 | |
mbed_official | 573:ad23fe03a082 | 487 | /* Read data from source */ |
mbed_official | 573:ad23fe03a082 | 488 | for(; BufferSize != 0; BufferSize--) |
mbed_official | 573:ad23fe03a082 | 489 | { |
mbed_official | 573:ad23fe03a082 | 490 | *pDstBuffer = *(__IO uint32_t *)pSdramAddress; |
mbed_official | 573:ad23fe03a082 | 491 | pDstBuffer++; |
mbed_official | 573:ad23fe03a082 | 492 | pSdramAddress++; |
mbed_official | 573:ad23fe03a082 | 493 | } |
mbed_official | 573:ad23fe03a082 | 494 | |
mbed_official | 573:ad23fe03a082 | 495 | /* Process Unlocked */ |
mbed_official | 573:ad23fe03a082 | 496 | __HAL_UNLOCK(hsdram); |
mbed_official | 573:ad23fe03a082 | 497 | |
mbed_official | 573:ad23fe03a082 | 498 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 499 | } |
mbed_official | 573:ad23fe03a082 | 500 | |
mbed_official | 573:ad23fe03a082 | 501 | /** |
mbed_official | 573:ad23fe03a082 | 502 | * @brief Writes 32-bit data buffer to SDRAM memory. |
mbed_official | 573:ad23fe03a082 | 503 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 504 | * the configuration information for SDRAM module. |
mbed_official | 573:ad23fe03a082 | 505 | * @param pAddress: Pointer to write start address |
mbed_official | 573:ad23fe03a082 | 506 | * @param pSrcBuffer: Pointer to source buffer to write |
mbed_official | 573:ad23fe03a082 | 507 | * @param BufferSize: Size of the buffer to write to memory |
mbed_official | 573:ad23fe03a082 | 508 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 509 | */ |
mbed_official | 573:ad23fe03a082 | 510 | HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) |
mbed_official | 573:ad23fe03a082 | 511 | { |
mbed_official | 573:ad23fe03a082 | 512 | __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; |
mbed_official | 573:ad23fe03a082 | 513 | uint32_t tmp = 0; |
mbed_official | 573:ad23fe03a082 | 514 | |
mbed_official | 573:ad23fe03a082 | 515 | /* Process Locked */ |
mbed_official | 573:ad23fe03a082 | 516 | __HAL_LOCK(hsdram); |
mbed_official | 573:ad23fe03a082 | 517 | |
mbed_official | 573:ad23fe03a082 | 518 | /* Check the SDRAM controller state */ |
mbed_official | 573:ad23fe03a082 | 519 | tmp = hsdram->State; |
mbed_official | 573:ad23fe03a082 | 520 | |
mbed_official | 573:ad23fe03a082 | 521 | if(tmp == HAL_SDRAM_STATE_BUSY) |
mbed_official | 573:ad23fe03a082 | 522 | { |
mbed_official | 573:ad23fe03a082 | 523 | return HAL_BUSY; |
mbed_official | 573:ad23fe03a082 | 524 | } |
mbed_official | 573:ad23fe03a082 | 525 | else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) |
mbed_official | 573:ad23fe03a082 | 526 | { |
mbed_official | 573:ad23fe03a082 | 527 | return HAL_ERROR; |
mbed_official | 573:ad23fe03a082 | 528 | } |
mbed_official | 573:ad23fe03a082 | 529 | |
mbed_official | 573:ad23fe03a082 | 530 | /* Write data to memory */ |
mbed_official | 573:ad23fe03a082 | 531 | for(; BufferSize != 0; BufferSize--) |
mbed_official | 573:ad23fe03a082 | 532 | { |
mbed_official | 573:ad23fe03a082 | 533 | *(__IO uint32_t *)pSdramAddress = *pSrcBuffer; |
mbed_official | 573:ad23fe03a082 | 534 | pSrcBuffer++; |
mbed_official | 573:ad23fe03a082 | 535 | pSdramAddress++; |
mbed_official | 573:ad23fe03a082 | 536 | } |
mbed_official | 573:ad23fe03a082 | 537 | |
mbed_official | 573:ad23fe03a082 | 538 | /* Process Unlocked */ |
mbed_official | 573:ad23fe03a082 | 539 | __HAL_UNLOCK(hsdram); |
mbed_official | 573:ad23fe03a082 | 540 | |
mbed_official | 573:ad23fe03a082 | 541 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 542 | } |
mbed_official | 573:ad23fe03a082 | 543 | |
mbed_official | 573:ad23fe03a082 | 544 | /** |
mbed_official | 573:ad23fe03a082 | 545 | * @brief Reads a Words data from the SDRAM memory using DMA transfer. |
mbed_official | 573:ad23fe03a082 | 546 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 547 | * the configuration information for SDRAM module. |
mbed_official | 573:ad23fe03a082 | 548 | * @param pAddress: Pointer to read start address |
mbed_official | 573:ad23fe03a082 | 549 | * @param pDstBuffer: Pointer to destination buffer |
mbed_official | 573:ad23fe03a082 | 550 | * @param BufferSize: Size of the buffer to read from memory |
mbed_official | 573:ad23fe03a082 | 551 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 552 | */ |
mbed_official | 573:ad23fe03a082 | 553 | HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) |
mbed_official | 573:ad23fe03a082 | 554 | { |
mbed_official | 573:ad23fe03a082 | 555 | uint32_t tmp = 0; |
mbed_official | 573:ad23fe03a082 | 556 | |
mbed_official | 573:ad23fe03a082 | 557 | /* Process Locked */ |
mbed_official | 573:ad23fe03a082 | 558 | __HAL_LOCK(hsdram); |
mbed_official | 573:ad23fe03a082 | 559 | |
mbed_official | 573:ad23fe03a082 | 560 | /* Check the SDRAM controller state */ |
mbed_official | 573:ad23fe03a082 | 561 | tmp = hsdram->State; |
mbed_official | 573:ad23fe03a082 | 562 | |
mbed_official | 573:ad23fe03a082 | 563 | if(tmp == HAL_SDRAM_STATE_BUSY) |
mbed_official | 573:ad23fe03a082 | 564 | { |
mbed_official | 573:ad23fe03a082 | 565 | return HAL_BUSY; |
mbed_official | 573:ad23fe03a082 | 566 | } |
mbed_official | 573:ad23fe03a082 | 567 | else if(tmp == HAL_SDRAM_STATE_PRECHARGED) |
mbed_official | 573:ad23fe03a082 | 568 | { |
mbed_official | 573:ad23fe03a082 | 569 | return HAL_ERROR; |
mbed_official | 573:ad23fe03a082 | 570 | } |
mbed_official | 573:ad23fe03a082 | 571 | |
mbed_official | 573:ad23fe03a082 | 572 | /* Configure DMA user callbacks */ |
mbed_official | 573:ad23fe03a082 | 573 | hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; |
mbed_official | 573:ad23fe03a082 | 574 | hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; |
mbed_official | 573:ad23fe03a082 | 575 | |
mbed_official | 573:ad23fe03a082 | 576 | /* Enable the DMA Stream */ |
mbed_official | 573:ad23fe03a082 | 577 | HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); |
mbed_official | 573:ad23fe03a082 | 578 | |
mbed_official | 573:ad23fe03a082 | 579 | /* Process Unlocked */ |
mbed_official | 573:ad23fe03a082 | 580 | __HAL_UNLOCK(hsdram); |
mbed_official | 573:ad23fe03a082 | 581 | |
mbed_official | 573:ad23fe03a082 | 582 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 583 | } |
mbed_official | 573:ad23fe03a082 | 584 | |
mbed_official | 573:ad23fe03a082 | 585 | /** |
mbed_official | 573:ad23fe03a082 | 586 | * @brief Writes a Words data buffer to SDRAM memory using DMA transfer. |
mbed_official | 573:ad23fe03a082 | 587 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 588 | * the configuration information for SDRAM module. |
mbed_official | 573:ad23fe03a082 | 589 | * @param pAddress: Pointer to write start address |
mbed_official | 573:ad23fe03a082 | 590 | * @param pSrcBuffer: Pointer to source buffer to write |
mbed_official | 573:ad23fe03a082 | 591 | * @param BufferSize: Size of the buffer to write to memory |
mbed_official | 573:ad23fe03a082 | 592 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 593 | */ |
mbed_official | 573:ad23fe03a082 | 594 | HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) |
mbed_official | 573:ad23fe03a082 | 595 | { |
mbed_official | 573:ad23fe03a082 | 596 | uint32_t tmp = 0; |
mbed_official | 573:ad23fe03a082 | 597 | |
mbed_official | 573:ad23fe03a082 | 598 | /* Process Locked */ |
mbed_official | 573:ad23fe03a082 | 599 | __HAL_LOCK(hsdram); |
mbed_official | 573:ad23fe03a082 | 600 | |
mbed_official | 573:ad23fe03a082 | 601 | /* Check the SDRAM controller state */ |
mbed_official | 573:ad23fe03a082 | 602 | tmp = hsdram->State; |
mbed_official | 573:ad23fe03a082 | 603 | |
mbed_official | 573:ad23fe03a082 | 604 | if(tmp == HAL_SDRAM_STATE_BUSY) |
mbed_official | 573:ad23fe03a082 | 605 | { |
mbed_official | 573:ad23fe03a082 | 606 | return HAL_BUSY; |
mbed_official | 573:ad23fe03a082 | 607 | } |
mbed_official | 573:ad23fe03a082 | 608 | else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) |
mbed_official | 573:ad23fe03a082 | 609 | { |
mbed_official | 573:ad23fe03a082 | 610 | return HAL_ERROR; |
mbed_official | 573:ad23fe03a082 | 611 | } |
mbed_official | 573:ad23fe03a082 | 612 | |
mbed_official | 573:ad23fe03a082 | 613 | /* Configure DMA user callbacks */ |
mbed_official | 573:ad23fe03a082 | 614 | hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; |
mbed_official | 573:ad23fe03a082 | 615 | hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; |
mbed_official | 573:ad23fe03a082 | 616 | |
mbed_official | 573:ad23fe03a082 | 617 | /* Enable the DMA Stream */ |
mbed_official | 573:ad23fe03a082 | 618 | HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); |
mbed_official | 573:ad23fe03a082 | 619 | |
mbed_official | 573:ad23fe03a082 | 620 | /* Process Unlocked */ |
mbed_official | 573:ad23fe03a082 | 621 | __HAL_UNLOCK(hsdram); |
mbed_official | 573:ad23fe03a082 | 622 | |
mbed_official | 573:ad23fe03a082 | 623 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 624 | } |
mbed_official | 573:ad23fe03a082 | 625 | |
mbed_official | 573:ad23fe03a082 | 626 | /** |
mbed_official | 573:ad23fe03a082 | 627 | * @} |
mbed_official | 573:ad23fe03a082 | 628 | */ |
mbed_official | 573:ad23fe03a082 | 629 | |
mbed_official | 573:ad23fe03a082 | 630 | /** @defgroup SDRAM_Exported_Functions_Group3 Control functions |
mbed_official | 573:ad23fe03a082 | 631 | * @brief management functions |
mbed_official | 573:ad23fe03a082 | 632 | * |
mbed_official | 573:ad23fe03a082 | 633 | @verbatim |
mbed_official | 573:ad23fe03a082 | 634 | ============================================================================== |
mbed_official | 573:ad23fe03a082 | 635 | ##### SDRAM Control functions ##### |
mbed_official | 573:ad23fe03a082 | 636 | ============================================================================== |
mbed_official | 573:ad23fe03a082 | 637 | [..] |
mbed_official | 573:ad23fe03a082 | 638 | This subsection provides a set of functions allowing to control dynamically |
mbed_official | 573:ad23fe03a082 | 639 | the SDRAM interface. |
mbed_official | 573:ad23fe03a082 | 640 | |
mbed_official | 573:ad23fe03a082 | 641 | @endverbatim |
mbed_official | 573:ad23fe03a082 | 642 | * @{ |
mbed_official | 573:ad23fe03a082 | 643 | */ |
mbed_official | 573:ad23fe03a082 | 644 | |
mbed_official | 573:ad23fe03a082 | 645 | /** |
mbed_official | 573:ad23fe03a082 | 646 | * @brief Enables dynamically SDRAM write protection. |
mbed_official | 573:ad23fe03a082 | 647 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 648 | * the configuration information for SDRAM module. |
mbed_official | 573:ad23fe03a082 | 649 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 650 | */ |
mbed_official | 573:ad23fe03a082 | 651 | HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) |
mbed_official | 573:ad23fe03a082 | 652 | { |
mbed_official | 573:ad23fe03a082 | 653 | /* Check the SDRAM controller state */ |
mbed_official | 573:ad23fe03a082 | 654 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
mbed_official | 573:ad23fe03a082 | 655 | { |
mbed_official | 573:ad23fe03a082 | 656 | return HAL_BUSY; |
mbed_official | 573:ad23fe03a082 | 657 | } |
mbed_official | 573:ad23fe03a082 | 658 | |
mbed_official | 573:ad23fe03a082 | 659 | /* Update the SDRAM state */ |
mbed_official | 573:ad23fe03a082 | 660 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
mbed_official | 573:ad23fe03a082 | 661 | |
mbed_official | 573:ad23fe03a082 | 662 | /* Enable write protection */ |
mbed_official | 573:ad23fe03a082 | 663 | FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank); |
mbed_official | 573:ad23fe03a082 | 664 | |
mbed_official | 573:ad23fe03a082 | 665 | /* Update the SDRAM state */ |
mbed_official | 573:ad23fe03a082 | 666 | hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; |
mbed_official | 573:ad23fe03a082 | 667 | |
mbed_official | 573:ad23fe03a082 | 668 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 669 | } |
mbed_official | 573:ad23fe03a082 | 670 | |
mbed_official | 573:ad23fe03a082 | 671 | /** |
mbed_official | 573:ad23fe03a082 | 672 | * @brief Disables dynamically SDRAM write protection. |
mbed_official | 573:ad23fe03a082 | 673 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 674 | * the configuration information for SDRAM module. |
mbed_official | 573:ad23fe03a082 | 675 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 676 | */ |
mbed_official | 573:ad23fe03a082 | 677 | HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) |
mbed_official | 573:ad23fe03a082 | 678 | { |
mbed_official | 573:ad23fe03a082 | 679 | /* Check the SDRAM controller state */ |
mbed_official | 573:ad23fe03a082 | 680 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
mbed_official | 573:ad23fe03a082 | 681 | { |
mbed_official | 573:ad23fe03a082 | 682 | return HAL_BUSY; |
mbed_official | 573:ad23fe03a082 | 683 | } |
mbed_official | 573:ad23fe03a082 | 684 | |
mbed_official | 573:ad23fe03a082 | 685 | /* Update the SDRAM state */ |
mbed_official | 573:ad23fe03a082 | 686 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
mbed_official | 573:ad23fe03a082 | 687 | |
mbed_official | 573:ad23fe03a082 | 688 | /* Disable write protection */ |
mbed_official | 573:ad23fe03a082 | 689 | FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank); |
mbed_official | 573:ad23fe03a082 | 690 | |
mbed_official | 573:ad23fe03a082 | 691 | /* Update the SDRAM state */ |
mbed_official | 573:ad23fe03a082 | 692 | hsdram->State = HAL_SDRAM_STATE_READY; |
mbed_official | 573:ad23fe03a082 | 693 | |
mbed_official | 573:ad23fe03a082 | 694 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 695 | } |
mbed_official | 573:ad23fe03a082 | 696 | |
mbed_official | 573:ad23fe03a082 | 697 | /** |
mbed_official | 573:ad23fe03a082 | 698 | * @brief Sends Command to the SDRAM bank. |
mbed_official | 573:ad23fe03a082 | 699 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 700 | * the configuration information for SDRAM module. |
mbed_official | 573:ad23fe03a082 | 701 | * @param Command: SDRAM command structure |
mbed_official | 573:ad23fe03a082 | 702 | * @param Timeout: Timeout duration |
mbed_official | 573:ad23fe03a082 | 703 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 704 | */ |
mbed_official | 573:ad23fe03a082 | 705 | HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) |
mbed_official | 573:ad23fe03a082 | 706 | { |
mbed_official | 573:ad23fe03a082 | 707 | /* Check the SDRAM controller state */ |
mbed_official | 573:ad23fe03a082 | 708 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
mbed_official | 573:ad23fe03a082 | 709 | { |
mbed_official | 573:ad23fe03a082 | 710 | return HAL_BUSY; |
mbed_official | 573:ad23fe03a082 | 711 | } |
mbed_official | 573:ad23fe03a082 | 712 | |
mbed_official | 573:ad23fe03a082 | 713 | /* Update the SDRAM state */ |
mbed_official | 573:ad23fe03a082 | 714 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
mbed_official | 573:ad23fe03a082 | 715 | |
mbed_official | 573:ad23fe03a082 | 716 | /* Send SDRAM command */ |
mbed_official | 573:ad23fe03a082 | 717 | FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout); |
mbed_official | 573:ad23fe03a082 | 718 | |
mbed_official | 573:ad23fe03a082 | 719 | /* Update the SDRAM controller state state */ |
mbed_official | 573:ad23fe03a082 | 720 | if(Command->CommandMode == FMC_SDRAM_CMD_PALL) |
mbed_official | 573:ad23fe03a082 | 721 | { |
mbed_official | 573:ad23fe03a082 | 722 | hsdram->State = HAL_SDRAM_STATE_PRECHARGED; |
mbed_official | 573:ad23fe03a082 | 723 | } |
mbed_official | 573:ad23fe03a082 | 724 | else |
mbed_official | 573:ad23fe03a082 | 725 | { |
mbed_official | 573:ad23fe03a082 | 726 | hsdram->State = HAL_SDRAM_STATE_READY; |
mbed_official | 573:ad23fe03a082 | 727 | } |
mbed_official | 573:ad23fe03a082 | 728 | |
mbed_official | 573:ad23fe03a082 | 729 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 730 | } |
mbed_official | 573:ad23fe03a082 | 731 | |
mbed_official | 573:ad23fe03a082 | 732 | /** |
mbed_official | 573:ad23fe03a082 | 733 | * @brief Programs the SDRAM Memory Refresh rate. |
mbed_official | 573:ad23fe03a082 | 734 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 735 | * the configuration information for SDRAM module. |
mbed_official | 573:ad23fe03a082 | 736 | * @param RefreshRate: The SDRAM refresh rate value |
mbed_official | 573:ad23fe03a082 | 737 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 738 | */ |
mbed_official | 573:ad23fe03a082 | 739 | HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) |
mbed_official | 573:ad23fe03a082 | 740 | { |
mbed_official | 573:ad23fe03a082 | 741 | /* Check the SDRAM controller state */ |
mbed_official | 573:ad23fe03a082 | 742 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
mbed_official | 573:ad23fe03a082 | 743 | { |
mbed_official | 573:ad23fe03a082 | 744 | return HAL_BUSY; |
mbed_official | 573:ad23fe03a082 | 745 | } |
mbed_official | 573:ad23fe03a082 | 746 | |
mbed_official | 573:ad23fe03a082 | 747 | /* Update the SDRAM state */ |
mbed_official | 573:ad23fe03a082 | 748 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
mbed_official | 573:ad23fe03a082 | 749 | |
mbed_official | 573:ad23fe03a082 | 750 | /* Program the refresh rate */ |
mbed_official | 573:ad23fe03a082 | 751 | FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate); |
mbed_official | 573:ad23fe03a082 | 752 | |
mbed_official | 573:ad23fe03a082 | 753 | /* Update the SDRAM state */ |
mbed_official | 573:ad23fe03a082 | 754 | hsdram->State = HAL_SDRAM_STATE_READY; |
mbed_official | 573:ad23fe03a082 | 755 | |
mbed_official | 573:ad23fe03a082 | 756 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 757 | } |
mbed_official | 573:ad23fe03a082 | 758 | |
mbed_official | 573:ad23fe03a082 | 759 | /** |
mbed_official | 573:ad23fe03a082 | 760 | * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. |
mbed_official | 573:ad23fe03a082 | 761 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 762 | * the configuration information for SDRAM module. |
mbed_official | 573:ad23fe03a082 | 763 | * @param AutoRefreshNumber: The SDRAM auto Refresh number |
mbed_official | 573:ad23fe03a082 | 764 | * @retval HAL status |
mbed_official | 573:ad23fe03a082 | 765 | */ |
mbed_official | 573:ad23fe03a082 | 766 | HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber) |
mbed_official | 573:ad23fe03a082 | 767 | { |
mbed_official | 573:ad23fe03a082 | 768 | /* Check the SDRAM controller state */ |
mbed_official | 573:ad23fe03a082 | 769 | if(hsdram->State == HAL_SDRAM_STATE_BUSY) |
mbed_official | 573:ad23fe03a082 | 770 | { |
mbed_official | 573:ad23fe03a082 | 771 | return HAL_BUSY; |
mbed_official | 573:ad23fe03a082 | 772 | } |
mbed_official | 573:ad23fe03a082 | 773 | |
mbed_official | 573:ad23fe03a082 | 774 | /* Update the SDRAM state */ |
mbed_official | 573:ad23fe03a082 | 775 | hsdram->State = HAL_SDRAM_STATE_BUSY; |
mbed_official | 573:ad23fe03a082 | 776 | |
mbed_official | 573:ad23fe03a082 | 777 | /* Set the Auto-Refresh number */ |
mbed_official | 573:ad23fe03a082 | 778 | FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber); |
mbed_official | 573:ad23fe03a082 | 779 | |
mbed_official | 573:ad23fe03a082 | 780 | /* Update the SDRAM state */ |
mbed_official | 573:ad23fe03a082 | 781 | hsdram->State = HAL_SDRAM_STATE_READY; |
mbed_official | 573:ad23fe03a082 | 782 | |
mbed_official | 573:ad23fe03a082 | 783 | return HAL_OK; |
mbed_official | 573:ad23fe03a082 | 784 | } |
mbed_official | 573:ad23fe03a082 | 785 | |
mbed_official | 573:ad23fe03a082 | 786 | /** |
mbed_official | 573:ad23fe03a082 | 787 | * @brief Returns the SDRAM memory current mode. |
mbed_official | 573:ad23fe03a082 | 788 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 789 | * the configuration information for SDRAM module. |
mbed_official | 573:ad23fe03a082 | 790 | * @retval The SDRAM memory mode. |
mbed_official | 573:ad23fe03a082 | 791 | */ |
mbed_official | 573:ad23fe03a082 | 792 | uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) |
mbed_official | 573:ad23fe03a082 | 793 | { |
mbed_official | 573:ad23fe03a082 | 794 | /* Return the SDRAM memory current mode */ |
mbed_official | 573:ad23fe03a082 | 795 | return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank)); |
mbed_official | 573:ad23fe03a082 | 796 | } |
mbed_official | 573:ad23fe03a082 | 797 | |
mbed_official | 573:ad23fe03a082 | 798 | /** |
mbed_official | 573:ad23fe03a082 | 799 | * @} |
mbed_official | 573:ad23fe03a082 | 800 | */ |
mbed_official | 573:ad23fe03a082 | 801 | |
mbed_official | 573:ad23fe03a082 | 802 | /** @defgroup SDRAM_Exported_Functions_Group4 State functions |
mbed_official | 573:ad23fe03a082 | 803 | * @brief Peripheral State functions |
mbed_official | 573:ad23fe03a082 | 804 | * |
mbed_official | 573:ad23fe03a082 | 805 | @verbatim |
mbed_official | 573:ad23fe03a082 | 806 | ============================================================================== |
mbed_official | 573:ad23fe03a082 | 807 | ##### SDRAM State functions ##### |
mbed_official | 573:ad23fe03a082 | 808 | ============================================================================== |
mbed_official | 573:ad23fe03a082 | 809 | [..] |
mbed_official | 573:ad23fe03a082 | 810 | This subsection permits to get in run-time the status of the SDRAM controller |
mbed_official | 573:ad23fe03a082 | 811 | and the data flow. |
mbed_official | 573:ad23fe03a082 | 812 | |
mbed_official | 573:ad23fe03a082 | 813 | @endverbatim |
mbed_official | 573:ad23fe03a082 | 814 | * @{ |
mbed_official | 573:ad23fe03a082 | 815 | */ |
mbed_official | 573:ad23fe03a082 | 816 | |
mbed_official | 573:ad23fe03a082 | 817 | /** |
mbed_official | 573:ad23fe03a082 | 818 | * @brief Returns the SDRAM state. |
mbed_official | 573:ad23fe03a082 | 819 | * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains |
mbed_official | 573:ad23fe03a082 | 820 | * the configuration information for SDRAM module. |
mbed_official | 573:ad23fe03a082 | 821 | * @retval HAL state |
mbed_official | 573:ad23fe03a082 | 822 | */ |
mbed_official | 573:ad23fe03a082 | 823 | HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) |
mbed_official | 573:ad23fe03a082 | 824 | { |
mbed_official | 573:ad23fe03a082 | 825 | return hsdram->State; |
mbed_official | 573:ad23fe03a082 | 826 | } |
mbed_official | 573:ad23fe03a082 | 827 | |
mbed_official | 573:ad23fe03a082 | 828 | /** |
mbed_official | 573:ad23fe03a082 | 829 | * @} |
mbed_official | 573:ad23fe03a082 | 830 | */ |
mbed_official | 573:ad23fe03a082 | 831 | |
mbed_official | 573:ad23fe03a082 | 832 | /** |
mbed_official | 573:ad23fe03a082 | 833 | * @} |
mbed_official | 573:ad23fe03a082 | 834 | */ |
mbed_official | 573:ad23fe03a082 | 835 | #endif /* HAL_SDRAM_MODULE_ENABLED */ |
mbed_official | 573:ad23fe03a082 | 836 | /** |
mbed_official | 573:ad23fe03a082 | 837 | * @} |
mbed_official | 573:ad23fe03a082 | 838 | */ |
mbed_official | 573:ad23fe03a082 | 839 | |
mbed_official | 573:ad23fe03a082 | 840 | /** |
mbed_official | 573:ad23fe03a082 | 841 | * @} |
mbed_official | 573:ad23fe03a082 | 842 | */ |
mbed_official | 573:ad23fe03a082 | 843 | |
mbed_official | 573:ad23fe03a082 | 844 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |