mbed library sources
Fork of mbed-src by
targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.h@637:ed69428d4850, 2015-12-22 (annotated)
- Committer:
- jaerts
- Date:
- Tue Dec 22 13:22:16 2015 +0000
- Revision:
- 637:ed69428d4850
- Parent:
- 610:813dcc80987e
Add very shady LPC1768 CAN Filter implementation
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 573:ad23fe03a082 | 1 | /** |
mbed_official | 573:ad23fe03a082 | 2 | ****************************************************************************** |
mbed_official | 573:ad23fe03a082 | 3 | * @file stm32f7xx_hal_rcc.h |
mbed_official | 573:ad23fe03a082 | 4 | * @author MCD Application Team |
mbed_official | 610:813dcc80987e | 5 | * @version V1.0.1 |
mbed_official | 610:813dcc80987e | 6 | * @date 25-June-2015 |
mbed_official | 573:ad23fe03a082 | 7 | * @brief Header file of RCC HAL module. |
mbed_official | 573:ad23fe03a082 | 8 | ****************************************************************************** |
mbed_official | 573:ad23fe03a082 | 9 | * @attention |
mbed_official | 573:ad23fe03a082 | 10 | * |
mbed_official | 573:ad23fe03a082 | 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
mbed_official | 573:ad23fe03a082 | 12 | * |
mbed_official | 573:ad23fe03a082 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 573:ad23fe03a082 | 14 | * are permitted provided that the following conditions are met: |
mbed_official | 573:ad23fe03a082 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 573:ad23fe03a082 | 16 | * this list of conditions and the following disclaimer. |
mbed_official | 573:ad23fe03a082 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 573:ad23fe03a082 | 18 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 573:ad23fe03a082 | 19 | * and/or other materials provided with the distribution. |
mbed_official | 573:ad23fe03a082 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 573:ad23fe03a082 | 21 | * may be used to endorse or promote products derived from this software |
mbed_official | 573:ad23fe03a082 | 22 | * without specific prior written permission. |
mbed_official | 573:ad23fe03a082 | 23 | * |
mbed_official | 573:ad23fe03a082 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 573:ad23fe03a082 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 573:ad23fe03a082 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 573:ad23fe03a082 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 573:ad23fe03a082 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 573:ad23fe03a082 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 573:ad23fe03a082 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 573:ad23fe03a082 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 573:ad23fe03a082 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 573:ad23fe03a082 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 573:ad23fe03a082 | 34 | * |
mbed_official | 573:ad23fe03a082 | 35 | ****************************************************************************** |
mbed_official | 573:ad23fe03a082 | 36 | */ |
mbed_official | 573:ad23fe03a082 | 37 | |
mbed_official | 573:ad23fe03a082 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 39 | #ifndef __STM32F7xx_HAL_RCC_H |
mbed_official | 573:ad23fe03a082 | 40 | #define __STM32F7xx_HAL_RCC_H |
mbed_official | 573:ad23fe03a082 | 41 | |
mbed_official | 573:ad23fe03a082 | 42 | #ifdef __cplusplus |
mbed_official | 573:ad23fe03a082 | 43 | extern "C" { |
mbed_official | 573:ad23fe03a082 | 44 | #endif |
mbed_official | 573:ad23fe03a082 | 45 | |
mbed_official | 573:ad23fe03a082 | 46 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 47 | #include "stm32f7xx_hal_def.h" |
mbed_official | 573:ad23fe03a082 | 48 | |
mbed_official | 573:ad23fe03a082 | 49 | /** @addtogroup STM32F7xx_HAL_Driver |
mbed_official | 573:ad23fe03a082 | 50 | * @{ |
mbed_official | 573:ad23fe03a082 | 51 | */ |
mbed_official | 573:ad23fe03a082 | 52 | |
mbed_official | 573:ad23fe03a082 | 53 | /** @addtogroup RCC |
mbed_official | 573:ad23fe03a082 | 54 | * @{ |
mbed_official | 573:ad23fe03a082 | 55 | */ |
mbed_official | 573:ad23fe03a082 | 56 | |
mbed_official | 573:ad23fe03a082 | 57 | /* Exported types ------------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 58 | |
mbed_official | 573:ad23fe03a082 | 59 | /** @defgroup RCC_Exported_Types RCC Exported Types |
mbed_official | 573:ad23fe03a082 | 60 | * @{ |
mbed_official | 573:ad23fe03a082 | 61 | */ |
mbed_official | 573:ad23fe03a082 | 62 | |
mbed_official | 573:ad23fe03a082 | 63 | /** |
mbed_official | 573:ad23fe03a082 | 64 | * @brief RCC PLL configuration structure definition |
mbed_official | 573:ad23fe03a082 | 65 | */ |
mbed_official | 573:ad23fe03a082 | 66 | typedef struct |
mbed_official | 573:ad23fe03a082 | 67 | { |
mbed_official | 573:ad23fe03a082 | 68 | uint32_t PLLState; /*!< The new state of the PLL. |
mbed_official | 573:ad23fe03a082 | 69 | This parameter can be a value of @ref RCC_PLL_Config */ |
mbed_official | 573:ad23fe03a082 | 70 | |
mbed_official | 573:ad23fe03a082 | 71 | uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. |
mbed_official | 573:ad23fe03a082 | 72 | This parameter must be a value of @ref RCC_PLL_Clock_Source */ |
mbed_official | 573:ad23fe03a082 | 73 | |
mbed_official | 573:ad23fe03a082 | 74 | uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. |
mbed_official | 573:ad23fe03a082 | 75 | This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ |
mbed_official | 573:ad23fe03a082 | 76 | |
mbed_official | 573:ad23fe03a082 | 77 | uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. |
mbed_official | 573:ad23fe03a082 | 78 | This parameter must be a number between Min_Data = 192 and Max_Data = 432 */ |
mbed_official | 573:ad23fe03a082 | 79 | |
mbed_official | 573:ad23fe03a082 | 80 | uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). |
mbed_official | 573:ad23fe03a082 | 81 | This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ |
mbed_official | 573:ad23fe03a082 | 82 | |
mbed_official | 573:ad23fe03a082 | 83 | uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks. |
mbed_official | 573:ad23fe03a082 | 84 | This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ |
mbed_official | 573:ad23fe03a082 | 85 | |
mbed_official | 573:ad23fe03a082 | 86 | }RCC_PLLInitTypeDef; |
mbed_official | 573:ad23fe03a082 | 87 | |
mbed_official | 573:ad23fe03a082 | 88 | /** |
mbed_official | 573:ad23fe03a082 | 89 | * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition |
mbed_official | 573:ad23fe03a082 | 90 | */ |
mbed_official | 573:ad23fe03a082 | 91 | typedef struct |
mbed_official | 573:ad23fe03a082 | 92 | { |
mbed_official | 573:ad23fe03a082 | 93 | uint32_t OscillatorType; /*!< The oscillators to be configured. |
mbed_official | 573:ad23fe03a082 | 94 | This parameter can be a value of @ref RCC_Oscillator_Type */ |
mbed_official | 573:ad23fe03a082 | 95 | |
mbed_official | 573:ad23fe03a082 | 96 | uint32_t HSEState; /*!< The new state of the HSE. |
mbed_official | 573:ad23fe03a082 | 97 | This parameter can be a value of @ref RCC_HSE_Config */ |
mbed_official | 573:ad23fe03a082 | 98 | |
mbed_official | 573:ad23fe03a082 | 99 | uint32_t LSEState; /*!< The new state of the LSE. |
mbed_official | 573:ad23fe03a082 | 100 | This parameter can be a value of @ref RCC_LSE_Config */ |
mbed_official | 573:ad23fe03a082 | 101 | |
mbed_official | 573:ad23fe03a082 | 102 | uint32_t HSIState; /*!< The new state of the HSI. |
mbed_official | 573:ad23fe03a082 | 103 | This parameter can be a value of @ref RCC_HSI_Config */ |
mbed_official | 573:ad23fe03a082 | 104 | |
mbed_official | 573:ad23fe03a082 | 105 | uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). |
mbed_official | 573:ad23fe03a082 | 106 | This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ |
mbed_official | 573:ad23fe03a082 | 107 | |
mbed_official | 573:ad23fe03a082 | 108 | uint32_t LSIState; /*!< The new state of the LSI. |
mbed_official | 573:ad23fe03a082 | 109 | This parameter can be a value of @ref RCC_LSI_Config */ |
mbed_official | 573:ad23fe03a082 | 110 | |
mbed_official | 573:ad23fe03a082 | 111 | RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ |
mbed_official | 573:ad23fe03a082 | 112 | |
mbed_official | 573:ad23fe03a082 | 113 | }RCC_OscInitTypeDef; |
mbed_official | 573:ad23fe03a082 | 114 | |
mbed_official | 573:ad23fe03a082 | 115 | /** |
mbed_official | 573:ad23fe03a082 | 116 | * @brief RCC System, AHB and APB busses clock configuration structure definition |
mbed_official | 573:ad23fe03a082 | 117 | */ |
mbed_official | 573:ad23fe03a082 | 118 | typedef struct |
mbed_official | 573:ad23fe03a082 | 119 | { |
mbed_official | 573:ad23fe03a082 | 120 | uint32_t ClockType; /*!< The clock to be configured. |
mbed_official | 573:ad23fe03a082 | 121 | This parameter can be a value of @ref RCC_System_Clock_Type */ |
mbed_official | 573:ad23fe03a082 | 122 | |
mbed_official | 573:ad23fe03a082 | 123 | uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. |
mbed_official | 573:ad23fe03a082 | 124 | This parameter can be a value of @ref RCC_System_Clock_Source */ |
mbed_official | 573:ad23fe03a082 | 125 | |
mbed_official | 573:ad23fe03a082 | 126 | uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). |
mbed_official | 573:ad23fe03a082 | 127 | This parameter can be a value of @ref RCC_AHB_Clock_Source */ |
mbed_official | 573:ad23fe03a082 | 128 | |
mbed_official | 573:ad23fe03a082 | 129 | uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). |
mbed_official | 573:ad23fe03a082 | 130 | This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ |
mbed_official | 573:ad23fe03a082 | 131 | |
mbed_official | 573:ad23fe03a082 | 132 | uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). |
mbed_official | 573:ad23fe03a082 | 133 | This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ |
mbed_official | 573:ad23fe03a082 | 134 | |
mbed_official | 573:ad23fe03a082 | 135 | }RCC_ClkInitTypeDef; |
mbed_official | 573:ad23fe03a082 | 136 | |
mbed_official | 573:ad23fe03a082 | 137 | /** |
mbed_official | 573:ad23fe03a082 | 138 | * @} |
mbed_official | 573:ad23fe03a082 | 139 | */ |
mbed_official | 573:ad23fe03a082 | 140 | |
mbed_official | 573:ad23fe03a082 | 141 | /* Exported constants --------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 142 | /** @defgroup RCC_Exported_Constants RCC Exported Constants |
mbed_official | 573:ad23fe03a082 | 143 | * @{ |
mbed_official | 573:ad23fe03a082 | 144 | */ |
mbed_official | 573:ad23fe03a082 | 145 | |
mbed_official | 573:ad23fe03a082 | 146 | /** @defgroup RCC_Oscillator_Type Oscillator Type |
mbed_official | 573:ad23fe03a082 | 147 | * @{ |
mbed_official | 573:ad23fe03a082 | 148 | */ |
mbed_official | 573:ad23fe03a082 | 149 | #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) |
mbed_official | 573:ad23fe03a082 | 150 | #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) |
mbed_official | 573:ad23fe03a082 | 151 | #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) |
mbed_official | 573:ad23fe03a082 | 152 | #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) |
mbed_official | 573:ad23fe03a082 | 153 | #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) |
mbed_official | 573:ad23fe03a082 | 154 | /** |
mbed_official | 573:ad23fe03a082 | 155 | * @} |
mbed_official | 573:ad23fe03a082 | 156 | */ |
mbed_official | 573:ad23fe03a082 | 157 | |
mbed_official | 573:ad23fe03a082 | 158 | /** @defgroup RCC_HSE_Config RCC HSE Config |
mbed_official | 573:ad23fe03a082 | 159 | * @{ |
mbed_official | 573:ad23fe03a082 | 160 | */ |
mbed_official | 573:ad23fe03a082 | 161 | #define RCC_HSE_OFF ((uint32_t)0x00000000) |
mbed_official | 573:ad23fe03a082 | 162 | #define RCC_HSE_ON RCC_CR_HSEON |
mbed_official | 573:ad23fe03a082 | 163 | #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) |
mbed_official | 573:ad23fe03a082 | 164 | /** |
mbed_official | 573:ad23fe03a082 | 165 | * @} |
mbed_official | 573:ad23fe03a082 | 166 | */ |
mbed_official | 573:ad23fe03a082 | 167 | |
mbed_official | 573:ad23fe03a082 | 168 | /** @defgroup RCC_LSE_Config RCC LSE Config |
mbed_official | 573:ad23fe03a082 | 169 | * @{ |
mbed_official | 573:ad23fe03a082 | 170 | */ |
mbed_official | 573:ad23fe03a082 | 171 | #define RCC_LSE_OFF ((uint32_t)0x00000000) |
mbed_official | 573:ad23fe03a082 | 172 | #define RCC_LSE_ON RCC_BDCR_LSEON |
mbed_official | 573:ad23fe03a082 | 173 | #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) |
mbed_official | 573:ad23fe03a082 | 174 | /** |
mbed_official | 573:ad23fe03a082 | 175 | * @} |
mbed_official | 573:ad23fe03a082 | 176 | */ |
mbed_official | 573:ad23fe03a082 | 177 | |
mbed_official | 573:ad23fe03a082 | 178 | /** @defgroup RCC_HSI_Config RCC HSI Config |
mbed_official | 573:ad23fe03a082 | 179 | * @{ |
mbed_official | 573:ad23fe03a082 | 180 | */ |
mbed_official | 573:ad23fe03a082 | 181 | #define RCC_HSI_OFF ((uint32_t)0x00000000) |
mbed_official | 573:ad23fe03a082 | 182 | #define RCC_HSI_ON RCC_CR_HSION |
mbed_official | 573:ad23fe03a082 | 183 | /** |
mbed_official | 573:ad23fe03a082 | 184 | * @} |
mbed_official | 573:ad23fe03a082 | 185 | */ |
mbed_official | 573:ad23fe03a082 | 186 | |
mbed_official | 573:ad23fe03a082 | 187 | /** @defgroup RCC_LSI_Config RCC LSI Config |
mbed_official | 573:ad23fe03a082 | 188 | * @{ |
mbed_official | 573:ad23fe03a082 | 189 | */ |
mbed_official | 573:ad23fe03a082 | 190 | #define RCC_LSI_OFF ((uint32_t)0x00000000) |
mbed_official | 573:ad23fe03a082 | 191 | #define RCC_LSI_ON RCC_CSR_LSION |
mbed_official | 573:ad23fe03a082 | 192 | /** |
mbed_official | 573:ad23fe03a082 | 193 | * @} |
mbed_official | 573:ad23fe03a082 | 194 | */ |
mbed_official | 573:ad23fe03a082 | 195 | |
mbed_official | 573:ad23fe03a082 | 196 | /** @defgroup RCC_PLL_Config RCC PLL Config |
mbed_official | 573:ad23fe03a082 | 197 | * @{ |
mbed_official | 573:ad23fe03a082 | 198 | */ |
mbed_official | 573:ad23fe03a082 | 199 | #define RCC_PLL_NONE ((uint32_t)0x00000000) |
mbed_official | 573:ad23fe03a082 | 200 | #define RCC_PLL_OFF ((uint32_t)0x00000001) |
mbed_official | 573:ad23fe03a082 | 201 | #define RCC_PLL_ON ((uint32_t)0x00000002) |
mbed_official | 573:ad23fe03a082 | 202 | /** |
mbed_official | 573:ad23fe03a082 | 203 | * @} |
mbed_official | 573:ad23fe03a082 | 204 | */ |
mbed_official | 573:ad23fe03a082 | 205 | |
mbed_official | 573:ad23fe03a082 | 206 | /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider |
mbed_official | 573:ad23fe03a082 | 207 | * @{ |
mbed_official | 573:ad23fe03a082 | 208 | */ |
mbed_official | 573:ad23fe03a082 | 209 | #define RCC_PLLP_DIV2 ((uint32_t)0x00000002) |
mbed_official | 573:ad23fe03a082 | 210 | #define RCC_PLLP_DIV4 ((uint32_t)0x00000004) |
mbed_official | 573:ad23fe03a082 | 211 | #define RCC_PLLP_DIV6 ((uint32_t)0x00000006) |
mbed_official | 573:ad23fe03a082 | 212 | #define RCC_PLLP_DIV8 ((uint32_t)0x00000008) |
mbed_official | 573:ad23fe03a082 | 213 | /** |
mbed_official | 573:ad23fe03a082 | 214 | * @} |
mbed_official | 573:ad23fe03a082 | 215 | */ |
mbed_official | 573:ad23fe03a082 | 216 | |
mbed_official | 573:ad23fe03a082 | 217 | /** @defgroup RCC_PLL_Clock_Source PLL Clock Source |
mbed_official | 573:ad23fe03a082 | 218 | * @{ |
mbed_official | 573:ad23fe03a082 | 219 | */ |
mbed_official | 573:ad23fe03a082 | 220 | #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI |
mbed_official | 573:ad23fe03a082 | 221 | #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE |
mbed_official | 573:ad23fe03a082 | 222 | /** |
mbed_official | 573:ad23fe03a082 | 223 | * @} |
mbed_official | 573:ad23fe03a082 | 224 | */ |
mbed_official | 573:ad23fe03a082 | 225 | |
mbed_official | 573:ad23fe03a082 | 226 | /** @defgroup RCC_System_Clock_Type RCC System Clock Type |
mbed_official | 573:ad23fe03a082 | 227 | * @{ |
mbed_official | 573:ad23fe03a082 | 228 | */ |
mbed_official | 573:ad23fe03a082 | 229 | #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) |
mbed_official | 573:ad23fe03a082 | 230 | #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) |
mbed_official | 573:ad23fe03a082 | 231 | #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) |
mbed_official | 573:ad23fe03a082 | 232 | #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) |
mbed_official | 573:ad23fe03a082 | 233 | /** |
mbed_official | 573:ad23fe03a082 | 234 | * @} |
mbed_official | 573:ad23fe03a082 | 235 | */ |
mbed_official | 573:ad23fe03a082 | 236 | |
mbed_official | 573:ad23fe03a082 | 237 | /** @defgroup RCC_System_Clock_Source RCC System Clock Source |
mbed_official | 573:ad23fe03a082 | 238 | * @{ |
mbed_official | 573:ad23fe03a082 | 239 | */ |
mbed_official | 573:ad23fe03a082 | 240 | #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI |
mbed_official | 573:ad23fe03a082 | 241 | #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE |
mbed_official | 573:ad23fe03a082 | 242 | #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL |
mbed_official | 573:ad23fe03a082 | 243 | /** |
mbed_official | 573:ad23fe03a082 | 244 | * @} |
mbed_official | 573:ad23fe03a082 | 245 | */ |
mbed_official | 573:ad23fe03a082 | 246 | |
mbed_official | 573:ad23fe03a082 | 247 | |
mbed_official | 573:ad23fe03a082 | 248 | /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status |
mbed_official | 573:ad23fe03a082 | 249 | * @{ |
mbed_official | 573:ad23fe03a082 | 250 | */ |
mbed_official | 573:ad23fe03a082 | 251 | #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ |
mbed_official | 573:ad23fe03a082 | 252 | #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ |
mbed_official | 573:ad23fe03a082 | 253 | #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ |
mbed_official | 573:ad23fe03a082 | 254 | /** |
mbed_official | 573:ad23fe03a082 | 255 | * @} |
mbed_official | 573:ad23fe03a082 | 256 | */ |
mbed_official | 573:ad23fe03a082 | 257 | |
mbed_official | 573:ad23fe03a082 | 258 | /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source |
mbed_official | 573:ad23fe03a082 | 259 | * @{ |
mbed_official | 573:ad23fe03a082 | 260 | */ |
mbed_official | 573:ad23fe03a082 | 261 | #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 |
mbed_official | 573:ad23fe03a082 | 262 | #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 |
mbed_official | 573:ad23fe03a082 | 263 | #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 |
mbed_official | 573:ad23fe03a082 | 264 | #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 |
mbed_official | 573:ad23fe03a082 | 265 | #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 |
mbed_official | 573:ad23fe03a082 | 266 | #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 |
mbed_official | 573:ad23fe03a082 | 267 | #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 |
mbed_official | 573:ad23fe03a082 | 268 | #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 |
mbed_official | 573:ad23fe03a082 | 269 | #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 |
mbed_official | 573:ad23fe03a082 | 270 | /** |
mbed_official | 573:ad23fe03a082 | 271 | * @} |
mbed_official | 573:ad23fe03a082 | 272 | */ |
mbed_official | 573:ad23fe03a082 | 273 | |
mbed_official | 573:ad23fe03a082 | 274 | /** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source |
mbed_official | 573:ad23fe03a082 | 275 | * @{ |
mbed_official | 573:ad23fe03a082 | 276 | */ |
mbed_official | 573:ad23fe03a082 | 277 | #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 |
mbed_official | 573:ad23fe03a082 | 278 | #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 |
mbed_official | 573:ad23fe03a082 | 279 | #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 |
mbed_official | 573:ad23fe03a082 | 280 | #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 |
mbed_official | 573:ad23fe03a082 | 281 | #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 |
mbed_official | 573:ad23fe03a082 | 282 | /** |
mbed_official | 573:ad23fe03a082 | 283 | * @} |
mbed_official | 573:ad23fe03a082 | 284 | */ |
mbed_official | 573:ad23fe03a082 | 285 | |
mbed_official | 573:ad23fe03a082 | 286 | /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source |
mbed_official | 573:ad23fe03a082 | 287 | * @{ |
mbed_official | 573:ad23fe03a082 | 288 | */ |
mbed_official | 573:ad23fe03a082 | 289 | #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100) |
mbed_official | 573:ad23fe03a082 | 290 | #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200) |
mbed_official | 573:ad23fe03a082 | 291 | #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300) |
mbed_official | 573:ad23fe03a082 | 292 | #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300) |
mbed_official | 573:ad23fe03a082 | 293 | #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300) |
mbed_official | 573:ad23fe03a082 | 294 | #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300) |
mbed_official | 573:ad23fe03a082 | 295 | #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300) |
mbed_official | 573:ad23fe03a082 | 296 | #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300) |
mbed_official | 573:ad23fe03a082 | 297 | #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300) |
mbed_official | 573:ad23fe03a082 | 298 | #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300) |
mbed_official | 573:ad23fe03a082 | 299 | #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300) |
mbed_official | 573:ad23fe03a082 | 300 | #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300) |
mbed_official | 573:ad23fe03a082 | 301 | #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300) |
mbed_official | 573:ad23fe03a082 | 302 | #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300) |
mbed_official | 573:ad23fe03a082 | 303 | #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300) |
mbed_official | 573:ad23fe03a082 | 304 | #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300) |
mbed_official | 573:ad23fe03a082 | 305 | #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300) |
mbed_official | 573:ad23fe03a082 | 306 | #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300) |
mbed_official | 573:ad23fe03a082 | 307 | #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300) |
mbed_official | 573:ad23fe03a082 | 308 | #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300) |
mbed_official | 573:ad23fe03a082 | 309 | #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300) |
mbed_official | 573:ad23fe03a082 | 310 | #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300) |
mbed_official | 573:ad23fe03a082 | 311 | #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300) |
mbed_official | 573:ad23fe03a082 | 312 | #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300) |
mbed_official | 573:ad23fe03a082 | 313 | #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300) |
mbed_official | 573:ad23fe03a082 | 314 | #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300) |
mbed_official | 573:ad23fe03a082 | 315 | #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300) |
mbed_official | 573:ad23fe03a082 | 316 | #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300) |
mbed_official | 573:ad23fe03a082 | 317 | #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300) |
mbed_official | 573:ad23fe03a082 | 318 | #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300) |
mbed_official | 573:ad23fe03a082 | 319 | #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300) |
mbed_official | 573:ad23fe03a082 | 320 | #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300) |
mbed_official | 573:ad23fe03a082 | 321 | /** |
mbed_official | 573:ad23fe03a082 | 322 | * @} |
mbed_official | 573:ad23fe03a082 | 323 | */ |
mbed_official | 573:ad23fe03a082 | 324 | |
mbed_official | 573:ad23fe03a082 | 325 | |
mbed_official | 573:ad23fe03a082 | 326 | |
mbed_official | 573:ad23fe03a082 | 327 | /** @defgroup RCC_MCO_Index RCC MCO Index |
mbed_official | 573:ad23fe03a082 | 328 | * @{ |
mbed_official | 573:ad23fe03a082 | 329 | */ |
mbed_official | 573:ad23fe03a082 | 330 | #define RCC_MCO1 ((uint32_t)0x00000000) |
mbed_official | 573:ad23fe03a082 | 331 | #define RCC_MCO2 ((uint32_t)0x00000001) |
mbed_official | 573:ad23fe03a082 | 332 | /** |
mbed_official | 573:ad23fe03a082 | 333 | * @} |
mbed_official | 573:ad23fe03a082 | 334 | */ |
mbed_official | 573:ad23fe03a082 | 335 | |
mbed_official | 573:ad23fe03a082 | 336 | /** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source |
mbed_official | 573:ad23fe03a082 | 337 | * @{ |
mbed_official | 573:ad23fe03a082 | 338 | */ |
mbed_official | 573:ad23fe03a082 | 339 | #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000) |
mbed_official | 573:ad23fe03a082 | 340 | #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 |
mbed_official | 573:ad23fe03a082 | 341 | #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 |
mbed_official | 573:ad23fe03a082 | 342 | #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1 |
mbed_official | 573:ad23fe03a082 | 343 | /** |
mbed_official | 573:ad23fe03a082 | 344 | * @} |
mbed_official | 573:ad23fe03a082 | 345 | */ |
mbed_official | 573:ad23fe03a082 | 346 | |
mbed_official | 573:ad23fe03a082 | 347 | /** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source |
mbed_official | 573:ad23fe03a082 | 348 | * @{ |
mbed_official | 573:ad23fe03a082 | 349 | */ |
mbed_official | 573:ad23fe03a082 | 350 | #define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000) |
mbed_official | 573:ad23fe03a082 | 351 | #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 |
mbed_official | 573:ad23fe03a082 | 352 | #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 |
mbed_official | 573:ad23fe03a082 | 353 | #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 |
mbed_official | 573:ad23fe03a082 | 354 | /** |
mbed_official | 573:ad23fe03a082 | 355 | * @} |
mbed_official | 573:ad23fe03a082 | 356 | */ |
mbed_official | 573:ad23fe03a082 | 357 | |
mbed_official | 573:ad23fe03a082 | 358 | /** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler |
mbed_official | 573:ad23fe03a082 | 359 | * @{ |
mbed_official | 573:ad23fe03a082 | 360 | */ |
mbed_official | 573:ad23fe03a082 | 361 | #define RCC_MCODIV_1 ((uint32_t)0x00000000) |
mbed_official | 573:ad23fe03a082 | 362 | #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2 |
mbed_official | 573:ad23fe03a082 | 363 | #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) |
mbed_official | 573:ad23fe03a082 | 364 | #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) |
mbed_official | 573:ad23fe03a082 | 365 | #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE |
mbed_official | 573:ad23fe03a082 | 366 | /** |
mbed_official | 573:ad23fe03a082 | 367 | * @} |
mbed_official | 573:ad23fe03a082 | 368 | */ |
mbed_official | 573:ad23fe03a082 | 369 | |
mbed_official | 573:ad23fe03a082 | 370 | /** @defgroup RCC_Interrupt RCC Interrupt |
mbed_official | 573:ad23fe03a082 | 371 | * @{ |
mbed_official | 573:ad23fe03a082 | 372 | */ |
mbed_official | 573:ad23fe03a082 | 373 | #define RCC_IT_LSIRDY ((uint8_t)0x01) |
mbed_official | 573:ad23fe03a082 | 374 | #define RCC_IT_LSERDY ((uint8_t)0x02) |
mbed_official | 573:ad23fe03a082 | 375 | #define RCC_IT_HSIRDY ((uint8_t)0x04) |
mbed_official | 573:ad23fe03a082 | 376 | #define RCC_IT_HSERDY ((uint8_t)0x08) |
mbed_official | 573:ad23fe03a082 | 377 | #define RCC_IT_PLLRDY ((uint8_t)0x10) |
mbed_official | 573:ad23fe03a082 | 378 | #define RCC_IT_PLLI2SRDY ((uint8_t)0x20) |
mbed_official | 573:ad23fe03a082 | 379 | #define RCC_IT_PLLSAIRDY ((uint8_t)0x40) |
mbed_official | 573:ad23fe03a082 | 380 | #define RCC_IT_CSS ((uint8_t)0x80) |
mbed_official | 573:ad23fe03a082 | 381 | /** |
mbed_official | 573:ad23fe03a082 | 382 | * @} |
mbed_official | 573:ad23fe03a082 | 383 | */ |
mbed_official | 573:ad23fe03a082 | 384 | |
mbed_official | 573:ad23fe03a082 | 385 | /** @defgroup RCC_Flag RCC Flags |
mbed_official | 573:ad23fe03a082 | 386 | * Elements values convention: 0XXYYYYYb |
mbed_official | 573:ad23fe03a082 | 387 | * - YYYYY : Flag position in the register |
mbed_official | 573:ad23fe03a082 | 388 | * - 0XX : Register index |
mbed_official | 573:ad23fe03a082 | 389 | * - 01: CR register |
mbed_official | 573:ad23fe03a082 | 390 | * - 10: BDCR register |
mbed_official | 573:ad23fe03a082 | 391 | * - 11: CSR register |
mbed_official | 573:ad23fe03a082 | 392 | * @{ |
mbed_official | 573:ad23fe03a082 | 393 | */ |
mbed_official | 573:ad23fe03a082 | 394 | /* Flags in the CR register */ |
mbed_official | 573:ad23fe03a082 | 395 | #define RCC_FLAG_HSIRDY ((uint8_t)0x21) |
mbed_official | 573:ad23fe03a082 | 396 | #define RCC_FLAG_HSERDY ((uint8_t)0x31) |
mbed_official | 573:ad23fe03a082 | 397 | #define RCC_FLAG_PLLRDY ((uint8_t)0x39) |
mbed_official | 573:ad23fe03a082 | 398 | #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) |
mbed_official | 573:ad23fe03a082 | 399 | #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3C) |
mbed_official | 573:ad23fe03a082 | 400 | |
mbed_official | 573:ad23fe03a082 | 401 | /* Flags in the BDCR register */ |
mbed_official | 573:ad23fe03a082 | 402 | #define RCC_FLAG_LSERDY ((uint8_t)0x41) |
mbed_official | 573:ad23fe03a082 | 403 | |
mbed_official | 573:ad23fe03a082 | 404 | /* Flags in the CSR register */ |
mbed_official | 573:ad23fe03a082 | 405 | #define RCC_FLAG_LSIRDY ((uint8_t)0x61) |
mbed_official | 573:ad23fe03a082 | 406 | #define RCC_FLAG_BORRST ((uint8_t)0x79) |
mbed_official | 573:ad23fe03a082 | 407 | #define RCC_FLAG_PINRST ((uint8_t)0x7A) |
mbed_official | 573:ad23fe03a082 | 408 | #define RCC_FLAG_PORRST ((uint8_t)0x7B) |
mbed_official | 573:ad23fe03a082 | 409 | #define RCC_FLAG_SFTRST ((uint8_t)0x7C) |
mbed_official | 573:ad23fe03a082 | 410 | #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) |
mbed_official | 573:ad23fe03a082 | 411 | #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) |
mbed_official | 573:ad23fe03a082 | 412 | #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) |
mbed_official | 573:ad23fe03a082 | 413 | /** |
mbed_official | 573:ad23fe03a082 | 414 | * @} |
mbed_official | 573:ad23fe03a082 | 415 | */ |
mbed_official | 573:ad23fe03a082 | 416 | |
mbed_official | 573:ad23fe03a082 | 417 | /** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations |
mbed_official | 573:ad23fe03a082 | 418 | * @{ |
mbed_official | 573:ad23fe03a082 | 419 | */ |
mbed_official | 573:ad23fe03a082 | 420 | #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000) |
mbed_official | 573:ad23fe03a082 | 421 | #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 |
mbed_official | 573:ad23fe03a082 | 422 | #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 |
mbed_official | 573:ad23fe03a082 | 423 | #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV |
mbed_official | 573:ad23fe03a082 | 424 | /** |
mbed_official | 573:ad23fe03a082 | 425 | * @} |
mbed_official | 573:ad23fe03a082 | 426 | */ |
mbed_official | 573:ad23fe03a082 | 427 | |
mbed_official | 573:ad23fe03a082 | 428 | /** |
mbed_official | 573:ad23fe03a082 | 429 | * @} |
mbed_official | 573:ad23fe03a082 | 430 | */ |
mbed_official | 573:ad23fe03a082 | 431 | |
mbed_official | 573:ad23fe03a082 | 432 | /* Exported macro ------------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 433 | /** @defgroup RCC_Exported_Macros RCC Exported Macros |
mbed_official | 573:ad23fe03a082 | 434 | * @{ |
mbed_official | 573:ad23fe03a082 | 435 | */ |
mbed_official | 573:ad23fe03a082 | 436 | |
mbed_official | 573:ad23fe03a082 | 437 | /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable |
mbed_official | 573:ad23fe03a082 | 438 | * @brief Enable or disable the AHB1 peripheral clock. |
mbed_official | 573:ad23fe03a082 | 439 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 573:ad23fe03a082 | 440 | * is disabled and the application software has to enable this clock before |
mbed_official | 573:ad23fe03a082 | 441 | * using it. |
mbed_official | 573:ad23fe03a082 | 442 | * @{ |
mbed_official | 573:ad23fe03a082 | 443 | */ |
mbed_official | 573:ad23fe03a082 | 444 | #define __HAL_RCC_CRC_CLK_ENABLE() do { \ |
mbed_official | 573:ad23fe03a082 | 445 | __IO uint32_t tmpreg; \ |
mbed_official | 573:ad23fe03a082 | 446 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ |
mbed_official | 573:ad23fe03a082 | 447 | /* Delay after an RCC peripheral clock enabling */ \ |
mbed_official | 573:ad23fe03a082 | 448 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ |
mbed_official | 573:ad23fe03a082 | 449 | UNUSED(tmpreg); \ |
mbed_official | 573:ad23fe03a082 | 450 | } while(0) |
mbed_official | 573:ad23fe03a082 | 451 | |
mbed_official | 573:ad23fe03a082 | 452 | #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ |
mbed_official | 573:ad23fe03a082 | 453 | __IO uint32_t tmpreg; \ |
mbed_official | 573:ad23fe03a082 | 454 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ |
mbed_official | 573:ad23fe03a082 | 455 | /* Delay after an RCC peripheral clock enabling */ \ |
mbed_official | 573:ad23fe03a082 | 456 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ |
mbed_official | 573:ad23fe03a082 | 457 | UNUSED(tmpreg); \ |
mbed_official | 573:ad23fe03a082 | 458 | } while(0) |
mbed_official | 573:ad23fe03a082 | 459 | |
mbed_official | 573:ad23fe03a082 | 460 | #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) |
mbed_official | 573:ad23fe03a082 | 461 | #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN)) |
mbed_official | 573:ad23fe03a082 | 462 | |
mbed_official | 573:ad23fe03a082 | 463 | /** |
mbed_official | 573:ad23fe03a082 | 464 | * @} |
mbed_official | 573:ad23fe03a082 | 465 | */ |
mbed_official | 573:ad23fe03a082 | 466 | |
mbed_official | 573:ad23fe03a082 | 467 | /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable |
mbed_official | 573:ad23fe03a082 | 468 | * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. |
mbed_official | 573:ad23fe03a082 | 469 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 573:ad23fe03a082 | 470 | * is disabled and the application software has to enable this clock before |
mbed_official | 573:ad23fe03a082 | 471 | * using it. |
mbed_official | 573:ad23fe03a082 | 472 | * @{ |
mbed_official | 573:ad23fe03a082 | 473 | */ |
mbed_official | 573:ad23fe03a082 | 474 | #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ |
mbed_official | 573:ad23fe03a082 | 475 | __IO uint32_t tmpreg; \ |
mbed_official | 573:ad23fe03a082 | 476 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ |
mbed_official | 573:ad23fe03a082 | 477 | /* Delay after an RCC peripheral clock enabling */ \ |
mbed_official | 573:ad23fe03a082 | 478 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ |
mbed_official | 573:ad23fe03a082 | 479 | UNUSED(tmpreg); \ |
mbed_official | 573:ad23fe03a082 | 480 | } while(0) |
mbed_official | 573:ad23fe03a082 | 481 | |
mbed_official | 573:ad23fe03a082 | 482 | #define __HAL_RCC_PWR_CLK_ENABLE() do { \ |
mbed_official | 573:ad23fe03a082 | 483 | __IO uint32_t tmpreg; \ |
mbed_official | 573:ad23fe03a082 | 484 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ |
mbed_official | 573:ad23fe03a082 | 485 | /* Delay after an RCC peripheral clock enabling */ \ |
mbed_official | 573:ad23fe03a082 | 486 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ |
mbed_official | 573:ad23fe03a082 | 487 | UNUSED(tmpreg); \ |
mbed_official | 573:ad23fe03a082 | 488 | } while(0) |
mbed_official | 573:ad23fe03a082 | 489 | |
mbed_official | 573:ad23fe03a082 | 490 | #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) |
mbed_official | 573:ad23fe03a082 | 491 | #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) |
mbed_official | 573:ad23fe03a082 | 492 | /** |
mbed_official | 573:ad23fe03a082 | 493 | * @} |
mbed_official | 573:ad23fe03a082 | 494 | */ |
mbed_official | 573:ad23fe03a082 | 495 | |
mbed_official | 573:ad23fe03a082 | 496 | /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable |
mbed_official | 573:ad23fe03a082 | 497 | * @brief Enable or disable the High Speed APB (APB2) peripheral clock. |
mbed_official | 573:ad23fe03a082 | 498 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 573:ad23fe03a082 | 499 | * is disabled and the application software has to enable this clock before |
mbed_official | 573:ad23fe03a082 | 500 | * using it. |
mbed_official | 573:ad23fe03a082 | 501 | * @{ |
mbed_official | 573:ad23fe03a082 | 502 | */ |
mbed_official | 573:ad23fe03a082 | 503 | #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ |
mbed_official | 573:ad23fe03a082 | 504 | __IO uint32_t tmpreg; \ |
mbed_official | 573:ad23fe03a082 | 505 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ |
mbed_official | 573:ad23fe03a082 | 506 | /* Delay after an RCC peripheral clock enabling */ \ |
mbed_official | 573:ad23fe03a082 | 507 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ |
mbed_official | 573:ad23fe03a082 | 508 | UNUSED(tmpreg); \ |
mbed_official | 573:ad23fe03a082 | 509 | } while(0) |
mbed_official | 573:ad23fe03a082 | 510 | |
mbed_official | 573:ad23fe03a082 | 511 | #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) |
mbed_official | 573:ad23fe03a082 | 512 | |
mbed_official | 573:ad23fe03a082 | 513 | /** |
mbed_official | 573:ad23fe03a082 | 514 | * @} |
mbed_official | 573:ad23fe03a082 | 515 | */ |
mbed_official | 573:ad23fe03a082 | 516 | |
mbed_official | 573:ad23fe03a082 | 517 | /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status |
mbed_official | 573:ad23fe03a082 | 518 | * @brief Get the enable or disable status of the AHB1 peripheral clock. |
mbed_official | 573:ad23fe03a082 | 519 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 573:ad23fe03a082 | 520 | * is disabled and the application software has to enable this clock before |
mbed_official | 573:ad23fe03a082 | 521 | * using it. |
mbed_official | 573:ad23fe03a082 | 522 | * @{ |
mbed_official | 573:ad23fe03a082 | 523 | */ |
mbed_official | 573:ad23fe03a082 | 524 | #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) |
mbed_official | 573:ad23fe03a082 | 525 | #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET) |
mbed_official | 573:ad23fe03a082 | 526 | |
mbed_official | 573:ad23fe03a082 | 527 | #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) |
mbed_official | 573:ad23fe03a082 | 528 | #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET) |
mbed_official | 573:ad23fe03a082 | 529 | /** |
mbed_official | 573:ad23fe03a082 | 530 | * @} |
mbed_official | 573:ad23fe03a082 | 531 | */ |
mbed_official | 573:ad23fe03a082 | 532 | |
mbed_official | 573:ad23fe03a082 | 533 | /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status |
mbed_official | 573:ad23fe03a082 | 534 | * @brief Get the enable or disable status of the APB1 peripheral clock. |
mbed_official | 573:ad23fe03a082 | 535 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 573:ad23fe03a082 | 536 | * is disabled and the application software has to enable this clock before |
mbed_official | 573:ad23fe03a082 | 537 | * using it. |
mbed_official | 573:ad23fe03a082 | 538 | * @{ |
mbed_official | 573:ad23fe03a082 | 539 | */ |
mbed_official | 573:ad23fe03a082 | 540 | #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) |
mbed_official | 573:ad23fe03a082 | 541 | #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) |
mbed_official | 573:ad23fe03a082 | 542 | |
mbed_official | 573:ad23fe03a082 | 543 | #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) |
mbed_official | 573:ad23fe03a082 | 544 | #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) |
mbed_official | 573:ad23fe03a082 | 545 | /** |
mbed_official | 573:ad23fe03a082 | 546 | * @} |
mbed_official | 573:ad23fe03a082 | 547 | */ |
mbed_official | 573:ad23fe03a082 | 548 | |
mbed_official | 573:ad23fe03a082 | 549 | /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status |
mbed_official | 573:ad23fe03a082 | 550 | * @brief EGet the enable or disable status of the APB2 peripheral clock. |
mbed_official | 573:ad23fe03a082 | 551 | * @note After reset, the peripheral clock (used for registers read/write access) |
mbed_official | 573:ad23fe03a082 | 552 | * is disabled and the application software has to enable this clock before |
mbed_official | 573:ad23fe03a082 | 553 | * using it. |
mbed_official | 573:ad23fe03a082 | 554 | * @{ |
mbed_official | 573:ad23fe03a082 | 555 | */ |
mbed_official | 573:ad23fe03a082 | 556 | #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) |
mbed_official | 573:ad23fe03a082 | 557 | #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) |
mbed_official | 573:ad23fe03a082 | 558 | /** |
mbed_official | 573:ad23fe03a082 | 559 | * @} |
mbed_official | 573:ad23fe03a082 | 560 | */ |
mbed_official | 573:ad23fe03a082 | 561 | |
mbed_official | 573:ad23fe03a082 | 562 | /** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release |
mbed_official | 573:ad23fe03a082 | 563 | * @brief Force or release AHB peripheral reset. |
mbed_official | 573:ad23fe03a082 | 564 | * @{ |
mbed_official | 573:ad23fe03a082 | 565 | */ |
mbed_official | 573:ad23fe03a082 | 566 | #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF) |
mbed_official | 573:ad23fe03a082 | 567 | #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) |
mbed_official | 573:ad23fe03a082 | 568 | #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) |
mbed_official | 573:ad23fe03a082 | 569 | |
mbed_official | 573:ad23fe03a082 | 570 | #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00) |
mbed_official | 573:ad23fe03a082 | 571 | #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) |
mbed_official | 573:ad23fe03a082 | 572 | #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST)) |
mbed_official | 573:ad23fe03a082 | 573 | /** |
mbed_official | 573:ad23fe03a082 | 574 | * @} |
mbed_official | 573:ad23fe03a082 | 575 | */ |
mbed_official | 573:ad23fe03a082 | 576 | |
mbed_official | 573:ad23fe03a082 | 577 | /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset |
mbed_official | 573:ad23fe03a082 | 578 | * @brief Force or release APB1 peripheral reset. |
mbed_official | 573:ad23fe03a082 | 579 | * @{ |
mbed_official | 573:ad23fe03a082 | 580 | */ |
mbed_official | 573:ad23fe03a082 | 581 | #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF) |
mbed_official | 573:ad23fe03a082 | 582 | #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) |
mbed_official | 573:ad23fe03a082 | 583 | #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) |
mbed_official | 573:ad23fe03a082 | 584 | |
mbed_official | 573:ad23fe03a082 | 585 | #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) |
mbed_official | 573:ad23fe03a082 | 586 | #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) |
mbed_official | 573:ad23fe03a082 | 587 | #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) |
mbed_official | 573:ad23fe03a082 | 588 | /** |
mbed_official | 573:ad23fe03a082 | 589 | * @} |
mbed_official | 573:ad23fe03a082 | 590 | */ |
mbed_official | 573:ad23fe03a082 | 591 | |
mbed_official | 573:ad23fe03a082 | 592 | /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset |
mbed_official | 573:ad23fe03a082 | 593 | * @brief Force or release APB2 peripheral reset. |
mbed_official | 573:ad23fe03a082 | 594 | * @{ |
mbed_official | 573:ad23fe03a082 | 595 | */ |
mbed_official | 573:ad23fe03a082 | 596 | #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF) |
mbed_official | 573:ad23fe03a082 | 597 | #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) |
mbed_official | 573:ad23fe03a082 | 598 | |
mbed_official | 573:ad23fe03a082 | 599 | #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) |
mbed_official | 573:ad23fe03a082 | 600 | #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) |
mbed_official | 573:ad23fe03a082 | 601 | |
mbed_official | 573:ad23fe03a082 | 602 | /** |
mbed_official | 573:ad23fe03a082 | 603 | * @} |
mbed_official | 573:ad23fe03a082 | 604 | */ |
mbed_official | 573:ad23fe03a082 | 605 | |
mbed_official | 573:ad23fe03a082 | 606 | /** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable |
mbed_official | 573:ad23fe03a082 | 607 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
mbed_official | 573:ad23fe03a082 | 608 | * power consumption. |
mbed_official | 573:ad23fe03a082 | 609 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
mbed_official | 573:ad23fe03a082 | 610 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
mbed_official | 573:ad23fe03a082 | 611 | * @{ |
mbed_official | 573:ad23fe03a082 | 612 | */ |
mbed_official | 573:ad23fe03a082 | 613 | #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) |
mbed_official | 573:ad23fe03a082 | 614 | #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) |
mbed_official | 573:ad23fe03a082 | 615 | |
mbed_official | 573:ad23fe03a082 | 616 | #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) |
mbed_official | 573:ad23fe03a082 | 617 | #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN)) |
mbed_official | 573:ad23fe03a082 | 618 | |
mbed_official | 573:ad23fe03a082 | 619 | /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. |
mbed_official | 573:ad23fe03a082 | 620 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
mbed_official | 573:ad23fe03a082 | 621 | * power consumption. |
mbed_official | 573:ad23fe03a082 | 622 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
mbed_official | 573:ad23fe03a082 | 623 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
mbed_official | 573:ad23fe03a082 | 624 | */ |
mbed_official | 573:ad23fe03a082 | 625 | #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) |
mbed_official | 573:ad23fe03a082 | 626 | #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) |
mbed_official | 573:ad23fe03a082 | 627 | |
mbed_official | 573:ad23fe03a082 | 628 | #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) |
mbed_official | 573:ad23fe03a082 | 629 | #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) |
mbed_official | 573:ad23fe03a082 | 630 | |
mbed_official | 573:ad23fe03a082 | 631 | /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. |
mbed_official | 573:ad23fe03a082 | 632 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
mbed_official | 573:ad23fe03a082 | 633 | * power consumption. |
mbed_official | 573:ad23fe03a082 | 634 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
mbed_official | 573:ad23fe03a082 | 635 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
mbed_official | 573:ad23fe03a082 | 636 | */ |
mbed_official | 573:ad23fe03a082 | 637 | #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) |
mbed_official | 573:ad23fe03a082 | 638 | #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) |
mbed_official | 573:ad23fe03a082 | 639 | |
mbed_official | 573:ad23fe03a082 | 640 | /** |
mbed_official | 573:ad23fe03a082 | 641 | * @} |
mbed_official | 573:ad23fe03a082 | 642 | */ |
mbed_official | 573:ad23fe03a082 | 643 | |
mbed_official | 573:ad23fe03a082 | 644 | /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status |
mbed_official | 573:ad23fe03a082 | 645 | * @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode. |
mbed_official | 573:ad23fe03a082 | 646 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
mbed_official | 573:ad23fe03a082 | 647 | * power consumption. |
mbed_official | 573:ad23fe03a082 | 648 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
mbed_official | 573:ad23fe03a082 | 649 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
mbed_official | 573:ad23fe03a082 | 650 | * @{ |
mbed_official | 573:ad23fe03a082 | 651 | */ |
mbed_official | 573:ad23fe03a082 | 652 | #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET) |
mbed_official | 573:ad23fe03a082 | 653 | #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET) |
mbed_official | 573:ad23fe03a082 | 654 | |
mbed_official | 573:ad23fe03a082 | 655 | #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET) |
mbed_official | 573:ad23fe03a082 | 656 | #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET) |
mbed_official | 573:ad23fe03a082 | 657 | /** |
mbed_official | 573:ad23fe03a082 | 658 | * @} |
mbed_official | 573:ad23fe03a082 | 659 | */ |
mbed_official | 573:ad23fe03a082 | 660 | |
mbed_official | 573:ad23fe03a082 | 661 | /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status |
mbed_official | 573:ad23fe03a082 | 662 | * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. |
mbed_official | 573:ad23fe03a082 | 663 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
mbed_official | 573:ad23fe03a082 | 664 | * power consumption. |
mbed_official | 573:ad23fe03a082 | 665 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
mbed_official | 573:ad23fe03a082 | 666 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
mbed_official | 573:ad23fe03a082 | 667 | * @{ |
mbed_official | 573:ad23fe03a082 | 668 | */ |
mbed_official | 573:ad23fe03a082 | 669 | #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET) |
mbed_official | 573:ad23fe03a082 | 670 | #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET) |
mbed_official | 573:ad23fe03a082 | 671 | |
mbed_official | 573:ad23fe03a082 | 672 | #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET) |
mbed_official | 573:ad23fe03a082 | 673 | #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET) |
mbed_official | 573:ad23fe03a082 | 674 | /** |
mbed_official | 573:ad23fe03a082 | 675 | * @} |
mbed_official | 573:ad23fe03a082 | 676 | */ |
mbed_official | 573:ad23fe03a082 | 677 | |
mbed_official | 573:ad23fe03a082 | 678 | /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status |
mbed_official | 573:ad23fe03a082 | 679 | * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. |
mbed_official | 573:ad23fe03a082 | 680 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
mbed_official | 573:ad23fe03a082 | 681 | * power consumption. |
mbed_official | 573:ad23fe03a082 | 682 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
mbed_official | 573:ad23fe03a082 | 683 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
mbed_official | 573:ad23fe03a082 | 684 | * @{ |
mbed_official | 573:ad23fe03a082 | 685 | */ |
mbed_official | 573:ad23fe03a082 | 686 | #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET) |
mbed_official | 573:ad23fe03a082 | 687 | #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET) |
mbed_official | 573:ad23fe03a082 | 688 | /** |
mbed_official | 573:ad23fe03a082 | 689 | * @} |
mbed_official | 573:ad23fe03a082 | 690 | */ |
mbed_official | 573:ad23fe03a082 | 691 | |
mbed_official | 573:ad23fe03a082 | 692 | /** @defgroup RCC_HSI_Configuration HSI Configuration |
mbed_official | 573:ad23fe03a082 | 693 | * @{ |
mbed_official | 573:ad23fe03a082 | 694 | */ |
mbed_official | 573:ad23fe03a082 | 695 | |
mbed_official | 573:ad23fe03a082 | 696 | /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). |
mbed_official | 573:ad23fe03a082 | 697 | * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. |
mbed_official | 573:ad23fe03a082 | 698 | * It is used (enabled by hardware) as system clock source after startup |
mbed_official | 573:ad23fe03a082 | 699 | * from Reset, wakeup from STOP and STANDBY mode, or in case of failure |
mbed_official | 573:ad23fe03a082 | 700 | * of the HSE used directly or indirectly as system clock (if the Clock |
mbed_official | 573:ad23fe03a082 | 701 | * Security System CSS is enabled). |
mbed_official | 573:ad23fe03a082 | 702 | * @note HSI can not be stopped if it is used as system clock source. In this case, |
mbed_official | 573:ad23fe03a082 | 703 | * you have to select another source of the system clock then stop the HSI. |
mbed_official | 573:ad23fe03a082 | 704 | * @note After enabling the HSI, the application software should wait on HSIRDY |
mbed_official | 573:ad23fe03a082 | 705 | * flag to be set indicating that HSI clock is stable and can be used as |
mbed_official | 573:ad23fe03a082 | 706 | * system clock source. |
mbed_official | 573:ad23fe03a082 | 707 | * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator |
mbed_official | 573:ad23fe03a082 | 708 | * clock cycles. |
mbed_official | 573:ad23fe03a082 | 709 | */ |
mbed_official | 573:ad23fe03a082 | 710 | #define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION)) |
mbed_official | 573:ad23fe03a082 | 711 | #define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION)) |
mbed_official | 573:ad23fe03a082 | 712 | |
mbed_official | 573:ad23fe03a082 | 713 | /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. |
mbed_official | 573:ad23fe03a082 | 714 | * @note The calibration is used to compensate for the variations in voltage |
mbed_official | 573:ad23fe03a082 | 715 | * and temperature that influence the frequency of the internal HSI RC. |
mbed_official | 573:ad23fe03a082 | 716 | * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value. |
mbed_official | 573:ad23fe03a082 | 717 | * This parameter must be a number between 0 and 0x1F. |
mbed_official | 573:ad23fe03a082 | 718 | */ |
mbed_official | 573:ad23fe03a082 | 719 | #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\ |
mbed_official | 573:ad23fe03a082 | 720 | RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_CR_HSITRIM))) |
mbed_official | 573:ad23fe03a082 | 721 | /** |
mbed_official | 573:ad23fe03a082 | 722 | * @} |
mbed_official | 573:ad23fe03a082 | 723 | */ |
mbed_official | 573:ad23fe03a082 | 724 | |
mbed_official | 573:ad23fe03a082 | 725 | /** @defgroup RCC_LSI_Configuration LSI Configuration |
mbed_official | 573:ad23fe03a082 | 726 | * @{ |
mbed_official | 573:ad23fe03a082 | 727 | */ |
mbed_official | 573:ad23fe03a082 | 728 | |
mbed_official | 573:ad23fe03a082 | 729 | /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). |
mbed_official | 573:ad23fe03a082 | 730 | * @note After enabling the LSI, the application software should wait on |
mbed_official | 573:ad23fe03a082 | 731 | * LSIRDY flag to be set indicating that LSI clock is stable and can |
mbed_official | 573:ad23fe03a082 | 732 | * be used to clock the IWDG and/or the RTC. |
mbed_official | 573:ad23fe03a082 | 733 | * @note LSI can not be disabled if the IWDG is running. |
mbed_official | 573:ad23fe03a082 | 734 | * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator |
mbed_official | 573:ad23fe03a082 | 735 | * clock cycles. |
mbed_official | 573:ad23fe03a082 | 736 | */ |
mbed_official | 573:ad23fe03a082 | 737 | #define __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION)) |
mbed_official | 573:ad23fe03a082 | 738 | #define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION)) |
mbed_official | 573:ad23fe03a082 | 739 | /** |
mbed_official | 573:ad23fe03a082 | 740 | * @} |
mbed_official | 573:ad23fe03a082 | 741 | */ |
mbed_official | 573:ad23fe03a082 | 742 | |
mbed_official | 573:ad23fe03a082 | 743 | /** @defgroup RCC_HSE_Configuration HSE Configuration |
mbed_official | 573:ad23fe03a082 | 744 | * @{ |
mbed_official | 573:ad23fe03a082 | 745 | */ |
mbed_official | 573:ad23fe03a082 | 746 | /** |
mbed_official | 573:ad23fe03a082 | 747 | * @brief Macro to configure the External High Speed oscillator (__HSE__). |
mbed_official | 573:ad23fe03a082 | 748 | * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application |
mbed_official | 573:ad23fe03a082 | 749 | * software should wait on HSERDY flag to be set indicating that HSE clock |
mbed_official | 573:ad23fe03a082 | 750 | * is stable and can be used to clock the PLL and/or system clock. |
mbed_official | 573:ad23fe03a082 | 751 | * @note HSE state can not be changed if it is used directly or through the |
mbed_official | 573:ad23fe03a082 | 752 | * PLL as system clock. In this case, you have to select another source |
mbed_official | 573:ad23fe03a082 | 753 | * of the system clock then change the HSE state (ex. disable it). |
mbed_official | 573:ad23fe03a082 | 754 | * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. |
mbed_official | 573:ad23fe03a082 | 755 | * @note This function reset the CSSON bit, so if the clock security system(CSS) |
mbed_official | 573:ad23fe03a082 | 756 | * was previously enabled you have to enable it again after calling this |
mbed_official | 573:ad23fe03a082 | 757 | * function. |
mbed_official | 573:ad23fe03a082 | 758 | * @param __STATE__: specifies the new state of the HSE. |
mbed_official | 573:ad23fe03a082 | 759 | * This parameter can be one of the following values: |
mbed_official | 573:ad23fe03a082 | 760 | * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after |
mbed_official | 573:ad23fe03a082 | 761 | * 6 HSE oscillator clock cycles. |
mbed_official | 573:ad23fe03a082 | 762 | * @arg RCC_HSE_ON: turn ON the HSE oscillator. |
mbed_official | 573:ad23fe03a082 | 763 | * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. |
mbed_official | 573:ad23fe03a082 | 764 | */ |
mbed_official | 573:ad23fe03a082 | 765 | #define __HAL_RCC_HSE_CONFIG(__STATE__) \ |
mbed_official | 573:ad23fe03a082 | 766 | do { \ |
mbed_official | 573:ad23fe03a082 | 767 | CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ |
mbed_official | 573:ad23fe03a082 | 768 | if((__STATE__) == RCC_HSE_ON) \ |
mbed_official | 573:ad23fe03a082 | 769 | { \ |
mbed_official | 573:ad23fe03a082 | 770 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ |
mbed_official | 573:ad23fe03a082 | 771 | SET_BIT(RCC->CR, RCC_CR_HSEON); \ |
mbed_official | 573:ad23fe03a082 | 772 | } \ |
mbed_official | 573:ad23fe03a082 | 773 | else if((__STATE__) == RCC_HSE_BYPASS) \ |
mbed_official | 573:ad23fe03a082 | 774 | { \ |
mbed_official | 573:ad23fe03a082 | 775 | SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ |
mbed_official | 573:ad23fe03a082 | 776 | SET_BIT(RCC->CR, RCC_CR_HSEON); \ |
mbed_official | 573:ad23fe03a082 | 777 | } \ |
mbed_official | 573:ad23fe03a082 | 778 | else \ |
mbed_official | 573:ad23fe03a082 | 779 | { \ |
mbed_official | 573:ad23fe03a082 | 780 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ |
mbed_official | 573:ad23fe03a082 | 781 | CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ |
mbed_official | 573:ad23fe03a082 | 782 | } \ |
mbed_official | 573:ad23fe03a082 | 783 | } while(0) |
mbed_official | 573:ad23fe03a082 | 784 | /** |
mbed_official | 573:ad23fe03a082 | 785 | * @} |
mbed_official | 573:ad23fe03a082 | 786 | */ |
mbed_official | 573:ad23fe03a082 | 787 | |
mbed_official | 573:ad23fe03a082 | 788 | /** @defgroup RCC_LSE_Configuration LSE Configuration |
mbed_official | 573:ad23fe03a082 | 789 | * @{ |
mbed_official | 573:ad23fe03a082 | 790 | */ |
mbed_official | 573:ad23fe03a082 | 791 | |
mbed_official | 573:ad23fe03a082 | 792 | /** |
mbed_official | 573:ad23fe03a082 | 793 | * @brief Macro to configure the External Low Speed oscillator (LSE). |
mbed_official | 573:ad23fe03a082 | 794 | * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. |
mbed_official | 573:ad23fe03a082 | 795 | * User should request a transition to LSE Off first and then LSE On or LSE Bypass. |
mbed_official | 573:ad23fe03a082 | 796 | * @note As the LSE is in the Backup domain and write access is denied to |
mbed_official | 573:ad23fe03a082 | 797 | * this domain after reset, you have to enable write access using |
mbed_official | 573:ad23fe03a082 | 798 | * HAL_PWR_EnableBkUpAccess() function before to configure the LSE |
mbed_official | 573:ad23fe03a082 | 799 | * (to be done once after reset). |
mbed_official | 573:ad23fe03a082 | 800 | * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application |
mbed_official | 573:ad23fe03a082 | 801 | * software should wait on LSERDY flag to be set indicating that LSE clock |
mbed_official | 573:ad23fe03a082 | 802 | * is stable and can be used to clock the RTC. |
mbed_official | 573:ad23fe03a082 | 803 | * @param __STATE__: specifies the new state of the LSE. |
mbed_official | 573:ad23fe03a082 | 804 | * This parameter can be one of the following values: |
mbed_official | 573:ad23fe03a082 | 805 | * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after |
mbed_official | 573:ad23fe03a082 | 806 | * 6 LSE oscillator clock cycles. |
mbed_official | 573:ad23fe03a082 | 807 | * @arg RCC_LSE_ON: turn ON the LSE oscillator. |
mbed_official | 573:ad23fe03a082 | 808 | * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. |
mbed_official | 573:ad23fe03a082 | 809 | */ |
mbed_official | 573:ad23fe03a082 | 810 | #define __HAL_RCC_LSE_CONFIG(__STATE__) \ |
mbed_official | 573:ad23fe03a082 | 811 | do { \ |
mbed_official | 573:ad23fe03a082 | 812 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
mbed_official | 573:ad23fe03a082 | 813 | if((__STATE__) == RCC_LSE_ON) \ |
mbed_official | 573:ad23fe03a082 | 814 | { \ |
mbed_official | 573:ad23fe03a082 | 815 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ |
mbed_official | 573:ad23fe03a082 | 816 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
mbed_official | 573:ad23fe03a082 | 817 | } \ |
mbed_official | 573:ad23fe03a082 | 818 | else if((__STATE__) == RCC_LSE_BYPASS) \ |
mbed_official | 573:ad23fe03a082 | 819 | { \ |
mbed_official | 573:ad23fe03a082 | 820 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ |
mbed_official | 573:ad23fe03a082 | 821 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
mbed_official | 573:ad23fe03a082 | 822 | } \ |
mbed_official | 573:ad23fe03a082 | 823 | else \ |
mbed_official | 573:ad23fe03a082 | 824 | { \ |
mbed_official | 573:ad23fe03a082 | 825 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ |
mbed_official | 573:ad23fe03a082 | 826 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
mbed_official | 573:ad23fe03a082 | 827 | } \ |
mbed_official | 573:ad23fe03a082 | 828 | } while(0) |
mbed_official | 573:ad23fe03a082 | 829 | /** |
mbed_official | 573:ad23fe03a082 | 830 | * @} |
mbed_official | 573:ad23fe03a082 | 831 | */ |
mbed_official | 573:ad23fe03a082 | 832 | |
mbed_official | 573:ad23fe03a082 | 833 | /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration |
mbed_official | 573:ad23fe03a082 | 834 | * @{ |
mbed_official | 573:ad23fe03a082 | 835 | */ |
mbed_official | 573:ad23fe03a082 | 836 | |
mbed_official | 573:ad23fe03a082 | 837 | /** @brief Macros to enable or disable the RTC clock. |
mbed_official | 573:ad23fe03a082 | 838 | * @note These macros must be used only after the RTC clock source was selected. |
mbed_official | 573:ad23fe03a082 | 839 | */ |
mbed_official | 573:ad23fe03a082 | 840 | #define __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN)) |
mbed_official | 573:ad23fe03a082 | 841 | #define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN)) |
mbed_official | 573:ad23fe03a082 | 842 | |
mbed_official | 573:ad23fe03a082 | 843 | /** @brief Macros to configure the RTC clock (RTCCLK). |
mbed_official | 573:ad23fe03a082 | 844 | * @note As the RTC clock configuration bits are in the Backup domain and write |
mbed_official | 573:ad23fe03a082 | 845 | * access is denied to this domain after reset, you have to enable write |
mbed_official | 573:ad23fe03a082 | 846 | * access using the Power Backup Access macro before to configure |
mbed_official | 573:ad23fe03a082 | 847 | * the RTC clock source (to be done once after reset). |
mbed_official | 573:ad23fe03a082 | 848 | * @note Once the RTC clock is configured it can't be changed unless the |
mbed_official | 573:ad23fe03a082 | 849 | * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by |
mbed_official | 573:ad23fe03a082 | 850 | * a Power On Reset (POR). |
mbed_official | 573:ad23fe03a082 | 851 | * @param __RTCCLKSource__: specifies the RTC clock source. |
mbed_official | 573:ad23fe03a082 | 852 | * This parameter can be one of the following values: |
mbed_official | 573:ad23fe03a082 | 853 | * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. |
mbed_official | 573:ad23fe03a082 | 854 | * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. |
mbed_official | 573:ad23fe03a082 | 855 | * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected |
mbed_official | 573:ad23fe03a082 | 856 | * as RTC clock, where x:[2,31] |
mbed_official | 573:ad23fe03a082 | 857 | * @note If the LSE or LSI is used as RTC clock source, the RTC continues to |
mbed_official | 573:ad23fe03a082 | 858 | * work in STOP and STANDBY modes, and can be used as wakeup source. |
mbed_official | 573:ad23fe03a082 | 859 | * However, when the HSE clock is used as RTC clock source, the RTC |
mbed_official | 573:ad23fe03a082 | 860 | * cannot be used in STOP and STANDBY modes. |
mbed_official | 573:ad23fe03a082 | 861 | * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as |
mbed_official | 573:ad23fe03a082 | 862 | * RTC clock source). |
mbed_official | 573:ad23fe03a082 | 863 | */ |
mbed_official | 573:ad23fe03a082 | 864 | #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ |
mbed_official | 573:ad23fe03a082 | 865 | MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) |
mbed_official | 573:ad23fe03a082 | 866 | |
mbed_official | 573:ad23fe03a082 | 867 | #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ |
mbed_official | 573:ad23fe03a082 | 868 | RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \ |
mbed_official | 573:ad23fe03a082 | 869 | } while (0) |
mbed_official | 573:ad23fe03a082 | 870 | |
mbed_official | 573:ad23fe03a082 | 871 | /** @brief Macros to force or release the Backup domain reset. |
mbed_official | 573:ad23fe03a082 | 872 | * @note This function resets the RTC peripheral (including the backup registers) |
mbed_official | 573:ad23fe03a082 | 873 | * and the RTC clock source selection in RCC_CSR register. |
mbed_official | 573:ad23fe03a082 | 874 | * @note The BKPSRAM is not affected by this reset. |
mbed_official | 573:ad23fe03a082 | 875 | */ |
mbed_official | 573:ad23fe03a082 | 876 | #define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST)) |
mbed_official | 573:ad23fe03a082 | 877 | #define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST)) |
mbed_official | 573:ad23fe03a082 | 878 | /** |
mbed_official | 573:ad23fe03a082 | 879 | * @} |
mbed_official | 573:ad23fe03a082 | 880 | */ |
mbed_official | 573:ad23fe03a082 | 881 | |
mbed_official | 573:ad23fe03a082 | 882 | /** @defgroup RCC_PLL_Configuration PLL Configuration |
mbed_official | 573:ad23fe03a082 | 883 | * @{ |
mbed_official | 573:ad23fe03a082 | 884 | */ |
mbed_official | 573:ad23fe03a082 | 885 | |
mbed_official | 573:ad23fe03a082 | 886 | /** @brief Macros to enable or disable the main PLL. |
mbed_official | 573:ad23fe03a082 | 887 | * @note After enabling the main PLL, the application software should wait on |
mbed_official | 573:ad23fe03a082 | 888 | * PLLRDY flag to be set indicating that PLL clock is stable and can |
mbed_official | 573:ad23fe03a082 | 889 | * be used as system clock source. |
mbed_official | 573:ad23fe03a082 | 890 | * @note The main PLL can not be disabled if it is used as system clock source |
mbed_official | 573:ad23fe03a082 | 891 | * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. |
mbed_official | 573:ad23fe03a082 | 892 | */ |
mbed_official | 573:ad23fe03a082 | 893 | #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) |
mbed_official | 573:ad23fe03a082 | 894 | #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) |
mbed_official | 573:ad23fe03a082 | 895 | |
mbed_official | 573:ad23fe03a082 | 896 | |
mbed_official | 573:ad23fe03a082 | 897 | /** @brief Macro to configure the main PLL clock source, multiplication and division factors. |
mbed_official | 573:ad23fe03a082 | 898 | * @note This function must be used only when the main PLL is disabled. |
mbed_official | 573:ad23fe03a082 | 899 | * @param __RCC_PLLSource__: specifies the PLL entry clock source. |
mbed_official | 573:ad23fe03a082 | 900 | * This parameter can be one of the following values: |
mbed_official | 573:ad23fe03a082 | 901 | * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry |
mbed_official | 573:ad23fe03a082 | 902 | * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry |
mbed_official | 573:ad23fe03a082 | 903 | * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. |
mbed_official | 573:ad23fe03a082 | 904 | * @param __PLLM__: specifies the division factor for PLL VCO input clock |
mbed_official | 573:ad23fe03a082 | 905 | * This parameter must be a number between Min_Data = 2 and Max_Data = 63. |
mbed_official | 573:ad23fe03a082 | 906 | * @note You have to set the PLLM parameter correctly to ensure that the VCO input |
mbed_official | 573:ad23fe03a082 | 907 | * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency |
mbed_official | 573:ad23fe03a082 | 908 | * of 2 MHz to limit PLL jitter. |
mbed_official | 573:ad23fe03a082 | 909 | * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock |
mbed_official | 573:ad23fe03a082 | 910 | * This parameter must be a number between Min_Data = 192 and Max_Data = 432. |
mbed_official | 573:ad23fe03a082 | 911 | * @note You have to set the PLLN parameter correctly to ensure that the VCO |
mbed_official | 573:ad23fe03a082 | 912 | * output frequency is between 192 and 432 MHz. |
mbed_official | 573:ad23fe03a082 | 913 | * @param __PLLP__: specifies the division factor for main system clock (SYSCLK) |
mbed_official | 573:ad23fe03a082 | 914 | * This parameter must be a number in the range {2, 4, 6, or 8}. |
mbed_official | 573:ad23fe03a082 | 915 | * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on |
mbed_official | 573:ad23fe03a082 | 916 | * the System clock frequency. |
mbed_official | 573:ad23fe03a082 | 917 | * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks |
mbed_official | 573:ad23fe03a082 | 918 | * This parameter must be a number between Min_Data = 2 and Max_Data = 15. |
mbed_official | 573:ad23fe03a082 | 919 | * @note If the USB OTG FS is used in your application, you have to set the |
mbed_official | 573:ad23fe03a082 | 920 | * PLLQ parameter correctly to have 48 MHz clock for the USB. However, |
mbed_official | 573:ad23fe03a082 | 921 | * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work |
mbed_official | 573:ad23fe03a082 | 922 | * correctly. |
mbed_official | 573:ad23fe03a082 | 923 | */ |
mbed_official | 573:ad23fe03a082 | 924 | #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\ |
mbed_official | 573:ad23fe03a082 | 925 | (RCC->PLLCFGR = (0x20000000 | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ |
mbed_official | 573:ad23fe03a082 | 926 | ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | (__RCC_PLLSource__) | \ |
mbed_official | 573:ad23fe03a082 | 927 | ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)))) |
mbed_official | 573:ad23fe03a082 | 928 | |
mbed_official | 573:ad23fe03a082 | 929 | /** @brief Macro to configure the PLL clock source. |
mbed_official | 573:ad23fe03a082 | 930 | * @note This function must be used only when the main PLL is disabled. |
mbed_official | 573:ad23fe03a082 | 931 | * @param __PLLSOURCE__: specifies the PLL entry clock source. |
mbed_official | 573:ad23fe03a082 | 932 | * This parameter can be one of the following values: |
mbed_official | 573:ad23fe03a082 | 933 | * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry |
mbed_official | 573:ad23fe03a082 | 934 | * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry |
mbed_official | 573:ad23fe03a082 | 935 | * |
mbed_official | 573:ad23fe03a082 | 936 | */ |
mbed_official | 573:ad23fe03a082 | 937 | #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) |
mbed_official | 573:ad23fe03a082 | 938 | |
mbed_official | 573:ad23fe03a082 | 939 | /** @brief Macro to configure the PLL multiplication factor. |
mbed_official | 573:ad23fe03a082 | 940 | * @note This function must be used only when the main PLL is disabled. |
mbed_official | 573:ad23fe03a082 | 941 | * @param __PLLM__: specifies the division factor for PLL VCO input clock |
mbed_official | 573:ad23fe03a082 | 942 | * This parameter must be a number between Min_Data = 2 and Max_Data = 63. |
mbed_official | 573:ad23fe03a082 | 943 | * @note You have to set the PLLM parameter correctly to ensure that the VCO input |
mbed_official | 573:ad23fe03a082 | 944 | * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency |
mbed_official | 573:ad23fe03a082 | 945 | * of 2 MHz to limit PLL jitter. |
mbed_official | 573:ad23fe03a082 | 946 | * |
mbed_official | 573:ad23fe03a082 | 947 | */ |
mbed_official | 573:ad23fe03a082 | 948 | #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) |
mbed_official | 573:ad23fe03a082 | 949 | /** |
mbed_official | 573:ad23fe03a082 | 950 | * @} |
mbed_official | 573:ad23fe03a082 | 951 | */ |
mbed_official | 573:ad23fe03a082 | 952 | |
mbed_official | 573:ad23fe03a082 | 953 | /** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration |
mbed_official | 573:ad23fe03a082 | 954 | * @{ |
mbed_official | 573:ad23fe03a082 | 955 | */ |
mbed_official | 573:ad23fe03a082 | 956 | |
mbed_official | 573:ad23fe03a082 | 957 | /** @brief Macro to configure the I2S clock source (I2SCLK). |
mbed_official | 573:ad23fe03a082 | 958 | * @note This function must be called before enabling the I2S APB clock. |
mbed_official | 573:ad23fe03a082 | 959 | * @param __SOURCE__: specifies the I2S clock source. |
mbed_official | 573:ad23fe03a082 | 960 | * This parameter can be one of the following values: |
mbed_official | 573:ad23fe03a082 | 961 | * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. |
mbed_official | 573:ad23fe03a082 | 962 | * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin |
mbed_official | 573:ad23fe03a082 | 963 | * used as I2S clock source. |
mbed_official | 573:ad23fe03a082 | 964 | */ |
mbed_official | 573:ad23fe03a082 | 965 | #define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \ |
mbed_official | 573:ad23fe03a082 | 966 | RCC->CFGR |= (__SOURCE__); \ |
mbed_official | 573:ad23fe03a082 | 967 | }while(0) |
mbed_official | 573:ad23fe03a082 | 968 | |
mbed_official | 573:ad23fe03a082 | 969 | /** @brief Macros to enable or disable the PLLI2S. |
mbed_official | 573:ad23fe03a082 | 970 | * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. |
mbed_official | 573:ad23fe03a082 | 971 | */ |
mbed_official | 573:ad23fe03a082 | 972 | #define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON)) |
mbed_official | 573:ad23fe03a082 | 973 | #define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON)) |
mbed_official | 573:ad23fe03a082 | 974 | /** |
mbed_official | 573:ad23fe03a082 | 975 | * @} |
mbed_official | 573:ad23fe03a082 | 976 | */ |
mbed_official | 573:ad23fe03a082 | 977 | |
mbed_official | 573:ad23fe03a082 | 978 | /** @defgroup RCC_Get_Clock_source Get Clock source |
mbed_official | 573:ad23fe03a082 | 979 | * @{ |
mbed_official | 573:ad23fe03a082 | 980 | */ |
mbed_official | 573:ad23fe03a082 | 981 | /** |
mbed_official | 573:ad23fe03a082 | 982 | * @brief Macro to configure the system clock source. |
mbed_official | 573:ad23fe03a082 | 983 | * @param __RCC_SYSCLKSOURCE__: specifies the system clock source. |
mbed_official | 573:ad23fe03a082 | 984 | * This parameter can be one of the following values: |
mbed_official | 573:ad23fe03a082 | 985 | * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. |
mbed_official | 573:ad23fe03a082 | 986 | * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. |
mbed_official | 573:ad23fe03a082 | 987 | * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. |
mbed_official | 573:ad23fe03a082 | 988 | */ |
mbed_official | 573:ad23fe03a082 | 989 | #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) |
mbed_official | 573:ad23fe03a082 | 990 | |
mbed_official | 573:ad23fe03a082 | 991 | /** @brief Macro to get the clock source used as system clock. |
mbed_official | 573:ad23fe03a082 | 992 | * @retval The clock source used as system clock. The returned value can be one |
mbed_official | 573:ad23fe03a082 | 993 | * of the following: |
mbed_official | 573:ad23fe03a082 | 994 | * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. |
mbed_official | 573:ad23fe03a082 | 995 | * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. |
mbed_official | 573:ad23fe03a082 | 996 | * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. |
mbed_official | 573:ad23fe03a082 | 997 | */ |
mbed_official | 573:ad23fe03a082 | 998 | #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)) |
mbed_official | 573:ad23fe03a082 | 999 | |
mbed_official | 573:ad23fe03a082 | 1000 | /** |
mbed_official | 573:ad23fe03a082 | 1001 | * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability. |
mbed_official | 573:ad23fe03a082 | 1002 | * @note As the LSE is in the Backup domain and write access is denied to |
mbed_official | 573:ad23fe03a082 | 1003 | * this domain after reset, you have to enable write access using |
mbed_official | 573:ad23fe03a082 | 1004 | * HAL_PWR_EnableBkUpAccess() function before to configure the LSE |
mbed_official | 573:ad23fe03a082 | 1005 | * (to be done once after reset). |
mbed_official | 573:ad23fe03a082 | 1006 | * @param __RCC_LSEDRIVE__: specifies the new state of the LSE drive capability. |
mbed_official | 573:ad23fe03a082 | 1007 | * This parameter can be one of the following values: |
mbed_official | 573:ad23fe03a082 | 1008 | * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability. |
mbed_official | 573:ad23fe03a082 | 1009 | * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability. |
mbed_official | 573:ad23fe03a082 | 1010 | * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability. |
mbed_official | 573:ad23fe03a082 | 1011 | * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability. |
mbed_official | 573:ad23fe03a082 | 1012 | * @retval None |
mbed_official | 573:ad23fe03a082 | 1013 | */ |
mbed_official | 573:ad23fe03a082 | 1014 | #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \ |
mbed_official | 573:ad23fe03a082 | 1015 | (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) )) |
mbed_official | 573:ad23fe03a082 | 1016 | |
mbed_official | 573:ad23fe03a082 | 1017 | /** @brief Macro to get the oscillator used as PLL clock source. |
mbed_official | 573:ad23fe03a082 | 1018 | * @retval The oscillator used as PLL clock source. The returned value can be one |
mbed_official | 573:ad23fe03a082 | 1019 | * of the following: |
mbed_official | 573:ad23fe03a082 | 1020 | * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. |
mbed_official | 573:ad23fe03a082 | 1021 | * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. |
mbed_official | 573:ad23fe03a082 | 1022 | */ |
mbed_official | 573:ad23fe03a082 | 1023 | #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) |
mbed_official | 573:ad23fe03a082 | 1024 | /** |
mbed_official | 573:ad23fe03a082 | 1025 | * @} |
mbed_official | 573:ad23fe03a082 | 1026 | */ |
mbed_official | 573:ad23fe03a082 | 1027 | |
mbed_official | 573:ad23fe03a082 | 1028 | /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management |
mbed_official | 573:ad23fe03a082 | 1029 | * @brief macros to manage the specified RCC Flags and interrupts. |
mbed_official | 573:ad23fe03a082 | 1030 | * @{ |
mbed_official | 573:ad23fe03a082 | 1031 | */ |
mbed_official | 573:ad23fe03a082 | 1032 | |
mbed_official | 573:ad23fe03a082 | 1033 | /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable |
mbed_official | 573:ad23fe03a082 | 1034 | * the selected interrupts). |
mbed_official | 573:ad23fe03a082 | 1035 | * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. |
mbed_official | 573:ad23fe03a082 | 1036 | * This parameter can be any combination of the following values: |
mbed_official | 573:ad23fe03a082 | 1037 | * @arg RCC_IT_LSIRDY: LSI ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1038 | * @arg RCC_IT_LSERDY: LSE ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1039 | * @arg RCC_IT_HSIRDY: HSI ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1040 | * @arg RCC_IT_HSERDY: HSE ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1041 | * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1042 | * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1043 | */ |
mbed_official | 573:ad23fe03a082 | 1044 | #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) |
mbed_official | 573:ad23fe03a082 | 1045 | |
mbed_official | 573:ad23fe03a082 | 1046 | /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable |
mbed_official | 573:ad23fe03a082 | 1047 | * the selected interrupts). |
mbed_official | 573:ad23fe03a082 | 1048 | * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. |
mbed_official | 573:ad23fe03a082 | 1049 | * This parameter can be any combination of the following values: |
mbed_official | 573:ad23fe03a082 | 1050 | * @arg RCC_IT_LSIRDY: LSI ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1051 | * @arg RCC_IT_LSERDY: LSE ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1052 | * @arg RCC_IT_HSIRDY: HSI ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1053 | * @arg RCC_IT_HSERDY: HSE ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1054 | * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1055 | * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1056 | */ |
mbed_official | 573:ad23fe03a082 | 1057 | #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__)) |
mbed_official | 573:ad23fe03a082 | 1058 | |
mbed_official | 573:ad23fe03a082 | 1059 | /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] |
mbed_official | 573:ad23fe03a082 | 1060 | * bits to clear the selected interrupt pending bits. |
mbed_official | 573:ad23fe03a082 | 1061 | * @param __INTERRUPT__: specifies the interrupt pending bit to clear. |
mbed_official | 573:ad23fe03a082 | 1062 | * This parameter can be any combination of the following values: |
mbed_official | 573:ad23fe03a082 | 1063 | * @arg RCC_IT_LSIRDY: LSI ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1064 | * @arg RCC_IT_LSERDY: LSE ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1065 | * @arg RCC_IT_HSIRDY: HSI ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1066 | * @arg RCC_IT_HSERDY: HSE ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1067 | * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1068 | * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1069 | * @arg RCC_IT_CSS: Clock Security System interrupt |
mbed_official | 573:ad23fe03a082 | 1070 | */ |
mbed_official | 573:ad23fe03a082 | 1071 | #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) |
mbed_official | 573:ad23fe03a082 | 1072 | |
mbed_official | 573:ad23fe03a082 | 1073 | /** @brief Check the RCC's interrupt has occurred or not. |
mbed_official | 573:ad23fe03a082 | 1074 | * @param __INTERRUPT__: specifies the RCC interrupt source to check. |
mbed_official | 573:ad23fe03a082 | 1075 | * This parameter can be one of the following values: |
mbed_official | 573:ad23fe03a082 | 1076 | * @arg RCC_IT_LSIRDY: LSI ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1077 | * @arg RCC_IT_LSERDY: LSE ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1078 | * @arg RCC_IT_HSIRDY: HSI ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1079 | * @arg RCC_IT_HSERDY: HSE ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1080 | * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1081 | * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. |
mbed_official | 573:ad23fe03a082 | 1082 | * @arg RCC_IT_CSS: Clock Security System interrupt |
mbed_official | 573:ad23fe03a082 | 1083 | * @retval The new state of __INTERRUPT__ (TRUE or FALSE). |
mbed_official | 573:ad23fe03a082 | 1084 | */ |
mbed_official | 573:ad23fe03a082 | 1085 | #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) |
mbed_official | 573:ad23fe03a082 | 1086 | |
mbed_official | 573:ad23fe03a082 | 1087 | /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, |
mbed_official | 573:ad23fe03a082 | 1088 | * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. |
mbed_official | 573:ad23fe03a082 | 1089 | */ |
mbed_official | 573:ad23fe03a082 | 1090 | #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) |
mbed_official | 573:ad23fe03a082 | 1091 | |
mbed_official | 573:ad23fe03a082 | 1092 | /** @brief Check RCC flag is set or not. |
mbed_official | 573:ad23fe03a082 | 1093 | * @param __FLAG__: specifies the flag to check. |
mbed_official | 573:ad23fe03a082 | 1094 | * This parameter can be one of the following values: |
mbed_official | 573:ad23fe03a082 | 1095 | * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. |
mbed_official | 573:ad23fe03a082 | 1096 | * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. |
mbed_official | 573:ad23fe03a082 | 1097 | * @arg RCC_FLAG_PLLRDY: Main PLL clock ready. |
mbed_official | 573:ad23fe03a082 | 1098 | * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready. |
mbed_official | 573:ad23fe03a082 | 1099 | * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready. |
mbed_official | 573:ad23fe03a082 | 1100 | * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready. |
mbed_official | 573:ad23fe03a082 | 1101 | * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset. |
mbed_official | 573:ad23fe03a082 | 1102 | * @arg RCC_FLAG_PINRST: Pin reset. |
mbed_official | 573:ad23fe03a082 | 1103 | * @arg RCC_FLAG_PORRST: POR/PDR reset. |
mbed_official | 573:ad23fe03a082 | 1104 | * @arg RCC_FLAG_SFTRST: Software reset. |
mbed_official | 573:ad23fe03a082 | 1105 | * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset. |
mbed_official | 573:ad23fe03a082 | 1106 | * @arg RCC_FLAG_WWDGRST: Window Watchdog reset. |
mbed_official | 573:ad23fe03a082 | 1107 | * @arg RCC_FLAG_LPWRRST: Low Power reset. |
mbed_official | 573:ad23fe03a082 | 1108 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
mbed_official | 573:ad23fe03a082 | 1109 | */ |
mbed_official | 573:ad23fe03a082 | 1110 | #define RCC_FLAG_MASK ((uint8_t)0x1F) |
mbed_official | 573:ad23fe03a082 | 1111 | #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0) |
mbed_official | 573:ad23fe03a082 | 1112 | |
mbed_official | 573:ad23fe03a082 | 1113 | /** |
mbed_official | 573:ad23fe03a082 | 1114 | * @} |
mbed_official | 573:ad23fe03a082 | 1115 | */ |
mbed_official | 573:ad23fe03a082 | 1116 | |
mbed_official | 573:ad23fe03a082 | 1117 | /** |
mbed_official | 573:ad23fe03a082 | 1118 | * @} |
mbed_official | 573:ad23fe03a082 | 1119 | */ |
mbed_official | 573:ad23fe03a082 | 1120 | |
mbed_official | 573:ad23fe03a082 | 1121 | /* Include RCC HAL Extension module */ |
mbed_official | 573:ad23fe03a082 | 1122 | #include "stm32f7xx_hal_rcc_ex.h" |
mbed_official | 573:ad23fe03a082 | 1123 | |
mbed_official | 573:ad23fe03a082 | 1124 | /* Exported functions --------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 1125 | /** @addtogroup RCC_Exported_Functions |
mbed_official | 573:ad23fe03a082 | 1126 | * @{ |
mbed_official | 573:ad23fe03a082 | 1127 | */ |
mbed_official | 573:ad23fe03a082 | 1128 | |
mbed_official | 573:ad23fe03a082 | 1129 | /** @addtogroup RCC_Exported_Functions_Group1 |
mbed_official | 573:ad23fe03a082 | 1130 | * @{ |
mbed_official | 573:ad23fe03a082 | 1131 | */ |
mbed_official | 573:ad23fe03a082 | 1132 | /* Initialization and de-initialization functions ******************************/ |
mbed_official | 573:ad23fe03a082 | 1133 | void HAL_RCC_DeInit(void); |
mbed_official | 573:ad23fe03a082 | 1134 | HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
mbed_official | 573:ad23fe03a082 | 1135 | HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); |
mbed_official | 573:ad23fe03a082 | 1136 | /** |
mbed_official | 573:ad23fe03a082 | 1137 | * @} |
mbed_official | 573:ad23fe03a082 | 1138 | */ |
mbed_official | 573:ad23fe03a082 | 1139 | |
mbed_official | 573:ad23fe03a082 | 1140 | /** @addtogroup RCC_Exported_Functions_Group2 |
mbed_official | 573:ad23fe03a082 | 1141 | * @{ |
mbed_official | 573:ad23fe03a082 | 1142 | */ |
mbed_official | 573:ad23fe03a082 | 1143 | /* Peripheral Control functions ************************************************/ |
mbed_official | 573:ad23fe03a082 | 1144 | void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); |
mbed_official | 573:ad23fe03a082 | 1145 | void HAL_RCC_EnableCSS(void); |
mbed_official | 573:ad23fe03a082 | 1146 | void HAL_RCC_DisableCSS(void); |
mbed_official | 573:ad23fe03a082 | 1147 | uint32_t HAL_RCC_GetSysClockFreq(void); |
mbed_official | 573:ad23fe03a082 | 1148 | uint32_t HAL_RCC_GetHCLKFreq(void); |
mbed_official | 573:ad23fe03a082 | 1149 | uint32_t HAL_RCC_GetPCLK1Freq(void); |
mbed_official | 573:ad23fe03a082 | 1150 | uint32_t HAL_RCC_GetPCLK2Freq(void); |
mbed_official | 573:ad23fe03a082 | 1151 | void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
mbed_official | 573:ad23fe03a082 | 1152 | void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); |
mbed_official | 573:ad23fe03a082 | 1153 | |
mbed_official | 573:ad23fe03a082 | 1154 | /* CSS NMI IRQ handler */ |
mbed_official | 573:ad23fe03a082 | 1155 | void HAL_RCC_NMI_IRQHandler(void); |
mbed_official | 573:ad23fe03a082 | 1156 | |
mbed_official | 573:ad23fe03a082 | 1157 | /* User Callbacks in non blocking mode (IT mode) */ |
mbed_official | 573:ad23fe03a082 | 1158 | void HAL_RCC_CSSCallback(void); |
mbed_official | 573:ad23fe03a082 | 1159 | /** |
mbed_official | 573:ad23fe03a082 | 1160 | * @} |
mbed_official | 573:ad23fe03a082 | 1161 | */ |
mbed_official | 573:ad23fe03a082 | 1162 | |
mbed_official | 573:ad23fe03a082 | 1163 | /** |
mbed_official | 573:ad23fe03a082 | 1164 | * @} |
mbed_official | 573:ad23fe03a082 | 1165 | */ |
mbed_official | 573:ad23fe03a082 | 1166 | |
mbed_official | 573:ad23fe03a082 | 1167 | /* Private types -------------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 1168 | /* Private variables ---------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 1169 | /* Private constants ---------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 1170 | /** @defgroup RCC_Private_Constants RCC Private Constants |
mbed_official | 573:ad23fe03a082 | 1171 | * @{ |
mbed_official | 573:ad23fe03a082 | 1172 | */ |
mbed_official | 573:ad23fe03a082 | 1173 | #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT |
mbed_official | 573:ad23fe03a082 | 1174 | #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
mbed_official | 573:ad23fe03a082 | 1175 | #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
mbed_official | 573:ad23fe03a082 | 1176 | #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
mbed_official | 573:ad23fe03a082 | 1177 | #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ |
mbed_official | 573:ad23fe03a082 | 1178 | |
mbed_official | 573:ad23fe03a082 | 1179 | /** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias |
mbed_official | 573:ad23fe03a082 | 1180 | * @brief RCC registers bit address alias |
mbed_official | 573:ad23fe03a082 | 1181 | * @{ |
mbed_official | 573:ad23fe03a082 | 1182 | */ |
mbed_official | 573:ad23fe03a082 | 1183 | /* CIR register byte 2 (Bits[15:8]) base address */ |
mbed_official | 573:ad23fe03a082 | 1184 | #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) |
mbed_official | 573:ad23fe03a082 | 1185 | |
mbed_official | 573:ad23fe03a082 | 1186 | /* CIR register byte 3 (Bits[23:16]) base address */ |
mbed_official | 573:ad23fe03a082 | 1187 | #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) |
mbed_official | 573:ad23fe03a082 | 1188 | |
mbed_official | 573:ad23fe03a082 | 1189 | #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) |
mbed_official | 573:ad23fe03a082 | 1190 | #define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000) |
mbed_official | 573:ad23fe03a082 | 1191 | /** |
mbed_official | 573:ad23fe03a082 | 1192 | * @} |
mbed_official | 573:ad23fe03a082 | 1193 | */ |
mbed_official | 573:ad23fe03a082 | 1194 | /** |
mbed_official | 573:ad23fe03a082 | 1195 | * @} |
mbed_official | 573:ad23fe03a082 | 1196 | */ |
mbed_official | 573:ad23fe03a082 | 1197 | |
mbed_official | 573:ad23fe03a082 | 1198 | /* Private macros ------------------------------------------------------------*/ |
mbed_official | 573:ad23fe03a082 | 1199 | /** @addtogroup RCC_Private_Macros RCC Private Macros |
mbed_official | 573:ad23fe03a082 | 1200 | * @{ |
mbed_official | 573:ad23fe03a082 | 1201 | */ |
mbed_official | 573:ad23fe03a082 | 1202 | |
mbed_official | 573:ad23fe03a082 | 1203 | /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters |
mbed_official | 573:ad23fe03a082 | 1204 | * @{ |
mbed_official | 573:ad23fe03a082 | 1205 | */ |
mbed_official | 573:ad23fe03a082 | 1206 | #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15) |
mbed_official | 573:ad23fe03a082 | 1207 | |
mbed_official | 573:ad23fe03a082 | 1208 | #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ |
mbed_official | 573:ad23fe03a082 | 1209 | ((HSE) == RCC_HSE_BYPASS)) |
mbed_official | 573:ad23fe03a082 | 1210 | |
mbed_official | 573:ad23fe03a082 | 1211 | #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ |
mbed_official | 573:ad23fe03a082 | 1212 | ((LSE) == RCC_LSE_BYPASS)) |
mbed_official | 573:ad23fe03a082 | 1213 | |
mbed_official | 573:ad23fe03a082 | 1214 | #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) |
mbed_official | 573:ad23fe03a082 | 1215 | |
mbed_official | 573:ad23fe03a082 | 1216 | #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) |
mbed_official | 573:ad23fe03a082 | 1217 | |
mbed_official | 573:ad23fe03a082 | 1218 | #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) |
mbed_official | 573:ad23fe03a082 | 1219 | |
mbed_official | 573:ad23fe03a082 | 1220 | #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ |
mbed_official | 573:ad23fe03a082 | 1221 | ((SOURCE) == RCC_PLLSOURCE_HSE)) |
mbed_official | 573:ad23fe03a082 | 1222 | |
mbed_official | 573:ad23fe03a082 | 1223 | #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ |
mbed_official | 573:ad23fe03a082 | 1224 | ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ |
mbed_official | 573:ad23fe03a082 | 1225 | ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) |
mbed_official | 573:ad23fe03a082 | 1226 | #define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63)) |
mbed_official | 573:ad23fe03a082 | 1227 | |
mbed_official | 573:ad23fe03a082 | 1228 | #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) |
mbed_official | 573:ad23fe03a082 | 1229 | |
mbed_official | 573:ad23fe03a082 | 1230 | #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \ |
mbed_official | 573:ad23fe03a082 | 1231 | ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8)) |
mbed_official | 573:ad23fe03a082 | 1232 | #define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) |
mbed_official | 573:ad23fe03a082 | 1233 | |
mbed_official | 573:ad23fe03a082 | 1234 | #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \ |
mbed_official | 573:ad23fe03a082 | 1235 | ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \ |
mbed_official | 573:ad23fe03a082 | 1236 | ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \ |
mbed_official | 573:ad23fe03a082 | 1237 | ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \ |
mbed_official | 573:ad23fe03a082 | 1238 | ((HCLK) == RCC_SYSCLK_DIV512)) |
mbed_official | 573:ad23fe03a082 | 1239 | |
mbed_official | 573:ad23fe03a082 | 1240 | #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15)) |
mbed_official | 573:ad23fe03a082 | 1241 | |
mbed_official | 573:ad23fe03a082 | 1242 | #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \ |
mbed_official | 573:ad23fe03a082 | 1243 | ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \ |
mbed_official | 573:ad23fe03a082 | 1244 | ((PCLK) == RCC_HCLK_DIV16)) |
mbed_official | 573:ad23fe03a082 | 1245 | |
mbed_official | 573:ad23fe03a082 | 1246 | #define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2)) |
mbed_official | 573:ad23fe03a082 | 1247 | |
mbed_official | 573:ad23fe03a082 | 1248 | |
mbed_official | 573:ad23fe03a082 | 1249 | #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ |
mbed_official | 573:ad23fe03a082 | 1250 | ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK)) |
mbed_official | 573:ad23fe03a082 | 1251 | |
mbed_official | 573:ad23fe03a082 | 1252 | #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \ |
mbed_official | 573:ad23fe03a082 | 1253 | ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) |
mbed_official | 573:ad23fe03a082 | 1254 | |
mbed_official | 573:ad23fe03a082 | 1255 | #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ |
mbed_official | 573:ad23fe03a082 | 1256 | ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ |
mbed_official | 573:ad23fe03a082 | 1257 | ((DIV) == RCC_MCODIV_5)) |
mbed_official | 573:ad23fe03a082 | 1258 | #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) |
mbed_official | 573:ad23fe03a082 | 1259 | |
mbed_official | 573:ad23fe03a082 | 1260 | #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ |
mbed_official | 573:ad23fe03a082 | 1261 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ |
mbed_official | 573:ad23fe03a082 | 1262 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ |
mbed_official | 573:ad23fe03a082 | 1263 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ |
mbed_official | 573:ad23fe03a082 | 1264 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ |
mbed_official | 573:ad23fe03a082 | 1265 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ |
mbed_official | 573:ad23fe03a082 | 1266 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ |
mbed_official | 573:ad23fe03a082 | 1267 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ |
mbed_official | 573:ad23fe03a082 | 1268 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ |
mbed_official | 573:ad23fe03a082 | 1269 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ |
mbed_official | 573:ad23fe03a082 | 1270 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ |
mbed_official | 573:ad23fe03a082 | 1271 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ |
mbed_official | 573:ad23fe03a082 | 1272 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ |
mbed_official | 573:ad23fe03a082 | 1273 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ |
mbed_official | 573:ad23fe03a082 | 1274 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ |
mbed_official | 573:ad23fe03a082 | 1275 | ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31)) |
mbed_official | 573:ad23fe03a082 | 1276 | |
mbed_official | 573:ad23fe03a082 | 1277 | |
mbed_official | 573:ad23fe03a082 | 1278 | #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || \ |
mbed_official | 573:ad23fe03a082 | 1279 | ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \ |
mbed_official | 573:ad23fe03a082 | 1280 | ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \ |
mbed_official | 573:ad23fe03a082 | 1281 | ((DRIVE) == RCC_LSEDRIVE_HIGH)) |
mbed_official | 573:ad23fe03a082 | 1282 | /** |
mbed_official | 573:ad23fe03a082 | 1283 | * @} |
mbed_official | 573:ad23fe03a082 | 1284 | */ |
mbed_official | 573:ad23fe03a082 | 1285 | |
mbed_official | 573:ad23fe03a082 | 1286 | /** |
mbed_official | 573:ad23fe03a082 | 1287 | * @} |
mbed_official | 573:ad23fe03a082 | 1288 | */ |
mbed_official | 573:ad23fe03a082 | 1289 | |
mbed_official | 573:ad23fe03a082 | 1290 | /** |
mbed_official | 573:ad23fe03a082 | 1291 | * @} |
mbed_official | 573:ad23fe03a082 | 1292 | */ |
mbed_official | 573:ad23fe03a082 | 1293 | |
mbed_official | 573:ad23fe03a082 | 1294 | /** |
mbed_official | 573:ad23fe03a082 | 1295 | * @} |
mbed_official | 573:ad23fe03a082 | 1296 | */ |
mbed_official | 573:ad23fe03a082 | 1297 | |
mbed_official | 573:ad23fe03a082 | 1298 | #ifdef __cplusplus |
mbed_official | 573:ad23fe03a082 | 1299 | } |
mbed_official | 573:ad23fe03a082 | 1300 | #endif |
mbed_official | 573:ad23fe03a082 | 1301 | |
mbed_official | 573:ad23fe03a082 | 1302 | #endif /* __STM32F7xx_HAL_RCC_H */ |
mbed_official | 573:ad23fe03a082 | 1303 | |
mbed_official | 573:ad23fe03a082 | 1304 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |