Joris Aerts / mbed-src

mbed library sources

Dependents:   Marvino mbot

Fork of mbed-src by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F3XX/system_stm32f30x.c@637:ed69428d4850, 2015-12-22 (annotated)

Committer:
jaerts
Date:
Tue Dec 22 13:22:16 2015 +0000
Revision:
637:ed69428d4850
Parent:
520:7182721120da 
Add very shady LPC1768 CAN Filter implementation

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 155:8435094ec241 1 /**
mbed_official 155:8435094ec241 2 ******************************************************************************
mbed_official 155:8435094ec241 3 * @file system_stm32f30x.c
mbed_official 155:8435094ec241 4 * @author MCD Application Team
mbed_official 155:8435094ec241 5 * @version V1.0.0
mbed_official 155:8435094ec241 6 * @date 05-March-2014
mbed_official 155:8435094ec241 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
mbed_official 155:8435094ec241 8 * This file contains the system clock configuration for STM32F30x devices,
mbed_official 155:8435094ec241 9 * and is generated by the clock configuration tool
mbed_official 155:8435094ec241 10 * stm32f30x_Clock_Configuration_V1.0.0.xls
mbed_official 155:8435094ec241 11 *
mbed_official 155:8435094ec241 12 * 1. This file provides two functions and one global variable to be called from
mbed_official 155:8435094ec241 13 * user application:
mbed_official 155:8435094ec241 14 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
mbed_official 155:8435094ec241 15 * and Divider factors, AHB/APBx prescalers and Flash settings),
mbed_official 155:8435094ec241 16 * depending on the configuration made in the clock xls tool.
mbed_official 155:8435094ec241 17 * This function is called at startup just after reset and
mbed_official 155:8435094ec241 18 * before branch to main program. This call is made inside
mbed_official 155:8435094ec241 19 * the "startup_stm32f30x.s" file.
mbed_official 155:8435094ec241 20 *
mbed_official 155:8435094ec241 21 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 155:8435094ec241 22 * by the user application to setup the SysTick
mbed_official 155:8435094ec241 23 * timer or configure other parameters.
mbed_official 155:8435094ec241 24 *
mbed_official 155:8435094ec241 25 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 155:8435094ec241 26 * be called whenever the core clock is changed
mbed_official 155:8435094ec241 27 * during program execution.
mbed_official 155:8435094ec241 28 *
mbed_official 155:8435094ec241 29 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
mbed_official 155:8435094ec241 30 * Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
mbed_official 155:8435094ec241 31 * configure the system clock before to branch to main program.
mbed_official 155:8435094ec241 32 *
mbed_official 155:8435094ec241 33 * 3. If the system clock source selected by user fails to startup, the SystemInit()
mbed_official 155:8435094ec241 34 * function will do nothing and HSI still used as system clock source. User can
mbed_official 155:8435094ec241 35 * add some code to deal with this issue inside the SetSysClock() function.
mbed_official 155:8435094ec241 36 *
mbed_official 155:8435094ec241 37 * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
mbed_official 155:8435094ec241 38 * in "stm32f30x.h" file. When HSE is used as system clock source, directly or
mbed_official 155:8435094ec241 39 * through PLL, and you are using different crystal you have to adapt the HSE
mbed_official 155:8435094ec241 40 * value to your own configuration.
mbed_official 155:8435094ec241 41 *
mbed_official 155:8435094ec241 42 * 5. This file configures the system clock as follows:
mbed_official 155:8435094ec241 43 *-----------------------------------------------------------------------------
mbed_official 155:8435094ec241 44 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 155:8435094ec241 45 * | (external 8 MHz clock) | (internal 8 MHz)
mbed_official 155:8435094ec241 46 * | 2- PLL_HSE_XTAL |
mbed_official 155:8435094ec241 47 * | (external 8 MHz xtal) |
mbed_official 155:8435094ec241 48 *-----------------------------------------------------------------------------
mbed_official 155:8435094ec241 49 * SYSCLK(MHz) | 72 | 64
mbed_official 155:8435094ec241 50 *-----------------------------------------------------------------------------
mbed_official 155:8435094ec241 51 * AHBCLK (MHz) | 72 | 64
mbed_official 155:8435094ec241 52 *-----------------------------------------------------------------------------
mbed_official 155:8435094ec241 53 * APB1CLK (MHz) | 36 | 32
mbed_official 155:8435094ec241 54 *-----------------------------------------------------------------------------
mbed_official 155:8435094ec241 55 * APB2CLK (MHz) | 72 | 64
mbed_official 155:8435094ec241 56 *-----------------------------------------------------------------------------
mbed_official 155:8435094ec241 57 * USB capable (48 MHz precise clock) | YES | NO
mbed_official 155:8435094ec241 58 *-----------------------------------------------------------------------------
mbed_official 155:8435094ec241 59 ******************************************************************************
mbed_official 155:8435094ec241 60 * @attention
mbed_official 155:8435094ec241 61 *
mbed_official 155:8435094ec241 62 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 155:8435094ec241 63 *
mbed_official 155:8435094ec241 64 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 155:8435094ec241 65 * are permitted provided that the following conditions are met:
mbed_official 155:8435094ec241 66 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 155:8435094ec241 67 * this list of conditions and the following disclaimer.
mbed_official 155:8435094ec241 68 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 155:8435094ec241 69 * this list of conditions and the following disclaimer in the documentation
mbed_official 155:8435094ec241 70 * and/or other materials provided with the distribution.
mbed_official 155:8435094ec241 71 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 155:8435094ec241 72 * may be used to endorse or promote products derived from this software
mbed_official 155:8435094ec241 73 * without specific prior written permission.
mbed_official 155:8435094ec241 74 *
mbed_official 155:8435094ec241 75 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 155:8435094ec241 76 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 155:8435094ec241 77 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 155:8435094ec241 78 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 155:8435094ec241 79 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 155:8435094ec241 80 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 155:8435094ec241 81 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 155:8435094ec241 82 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 155:8435094ec241 83 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 155:8435094ec241 84 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 155:8435094ec241 85 *
mbed_official 155:8435094ec241 86 ******************************************************************************
mbed_official 155:8435094ec241 87 */
mbed_official 155:8435094ec241 88
mbed_official 155:8435094ec241 89 /** @addtogroup CMSIS
mbed_official 155:8435094ec241 90 * @{
mbed_official 155:8435094ec241 91 */
mbed_official 155:8435094ec241 92
mbed_official 155:8435094ec241 93 /** @addtogroup stm32f30x_system
mbed_official 155:8435094ec241 94 * @{
mbed_official 155:8435094ec241 95 */
mbed_official 155:8435094ec241 96
mbed_official 155:8435094ec241 97 /** @addtogroup STM32F30x_System_Private_Includes
mbed_official 155:8435094ec241 98 * @{
mbed_official 155:8435094ec241 99 */
mbed_official 155:8435094ec241 100
mbed_official 155:8435094ec241 101 #include "stm32f30x.h"
mbed_official 155:8435094ec241 102
mbed_official 155:8435094ec241 103 /**
mbed_official 155:8435094ec241 104 * @}
mbed_official 155:8435094ec241 105 */
mbed_official 155:8435094ec241 106
mbed_official 155:8435094ec241 107 /** @addtogroup STM32F30x_System_Private_TypesDefinitions
mbed_official 155:8435094ec241 108 * @{
mbed_official 155:8435094ec241 109 */
mbed_official 155:8435094ec241 110
mbed_official 155:8435094ec241 111 /**
mbed_official 155:8435094ec241 112 * @}
mbed_official 155:8435094ec241 113 */
mbed_official 155:8435094ec241 114
mbed_official 155:8435094ec241 115 /** @addtogroup STM32F30x_System_Private_Defines
mbed_official 155:8435094ec241 116 * @{
mbed_official 155:8435094ec241 117 */
mbed_official 155:8435094ec241 118
mbed_official 155:8435094ec241 119 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 155:8435094ec241 120 Internal SRAM. */
mbed_official 155:8435094ec241 121 /* #define VECT_TAB_SRAM */
mbed_official 155:8435094ec241 122 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
mbed_official 155:8435094ec241 123 This value must be a multiple of 0x200. */
mbed_official 155:8435094ec241 124 /**
mbed_official 155:8435094ec241 125 * @}
mbed_official 155:8435094ec241 126 */
mbed_official 155:8435094ec241 127
mbed_official 155:8435094ec241 128 /** @addtogroup STM32F30x_System_Private_Macros
mbed_official 155:8435094ec241 129 * @{
mbed_official 155:8435094ec241 130 */
mbed_official 155:8435094ec241 131
mbed_official 155:8435094ec241 132 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 155:8435094ec241 133 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official 155:8435094ec241 134 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 155:8435094ec241 135
mbed_official 155:8435094ec241 136 /**
mbed_official 155:8435094ec241 137 * @}
mbed_official 155:8435094ec241 138 */
mbed_official 155:8435094ec241 139
mbed_official 155:8435094ec241 140 /** @addtogroup STM32F30x_System_Private_Variables
mbed_official 155:8435094ec241 141 * @{
mbed_official 155:8435094ec241 142 */
mbed_official 155:8435094ec241 143
mbed_official 155:8435094ec241 144 uint32_t SystemCoreClock = 64000000; /* Default with HSI. Will be updated if HSE is used */
mbed_official 155:8435094ec241 145
mbed_official 520:7182721120da 146 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 155:8435094ec241 147
mbed_official 155:8435094ec241 148 /**
mbed_official 155:8435094ec241 149 * @}
mbed_official 155:8435094ec241 150 */
mbed_official 155:8435094ec241 151
mbed_official 155:8435094ec241 152 /** @addtogroup STM32F30x_System_Private_FunctionPrototypes
mbed_official 155:8435094ec241 153 * @{
mbed_official 155:8435094ec241 154 */
mbed_official 155:8435094ec241 155
mbed_official 155:8435094ec241 156 void SetSysClock(void);
mbed_official 155:8435094ec241 157
mbed_official 155:8435094ec241 158 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 155:8435094ec241 159 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 155:8435094ec241 160 #endif
mbed_official 155:8435094ec241 161
mbed_official 155:8435094ec241 162 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 155:8435094ec241 163
mbed_official 155:8435094ec241 164 /**
mbed_official 155:8435094ec241 165 * @}
mbed_official 155:8435094ec241 166 */
mbed_official 155:8435094ec241 167
mbed_official 155:8435094ec241 168 /** @addtogroup STM32F30x_System_Private_Functions
mbed_official 155:8435094ec241 169 * @{
mbed_official 155:8435094ec241 170 */
mbed_official 155:8435094ec241 171
mbed_official 155:8435094ec241 172 /**
mbed_official 155:8435094ec241 173 * @brief Setup the microcontroller system
mbed_official 155:8435094ec241 174 * Initialize the Embedded Flash Interface, the PLL and update the
mbed_official 155:8435094ec241 175 * SystemFrequency variable.
mbed_official 155:8435094ec241 176 * @param None
mbed_official 155:8435094ec241 177 * @retval None
mbed_official 155:8435094ec241 178 */
mbed_official 155:8435094ec241 179 void SystemInit(void)
mbed_official 155:8435094ec241 180 {
mbed_official 155:8435094ec241 181 /* FPU settings ------------------------------------------------------------*/
mbed_official 155:8435094ec241 182 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 155:8435094ec241 183 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
mbed_official 155:8435094ec241 184 #endif
mbed_official 155:8435094ec241 185
mbed_official 155:8435094ec241 186 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 155:8435094ec241 187 /* Set HSION bit */
mbed_official 155:8435094ec241 188 RCC->CR |= (uint32_t)0x00000001;
mbed_official 155:8435094ec241 189
mbed_official 155:8435094ec241 190 /* Reset CFGR register */
mbed_official 155:8435094ec241 191 RCC->CFGR &= 0xF87FC00C;
mbed_official 155:8435094ec241 192
mbed_official 155:8435094ec241 193 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 155:8435094ec241 194 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 155:8435094ec241 195
mbed_official 155:8435094ec241 196 /* Reset HSEBYP bit */
mbed_official 155:8435094ec241 197 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 155:8435094ec241 198
mbed_official 155:8435094ec241 199 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
mbed_official 155:8435094ec241 200 RCC->CFGR &= (uint32_t)0xFF80FFFF;
mbed_official 155:8435094ec241 201
mbed_official 155:8435094ec241 202 /* Reset PREDIV1[3:0] bits */
mbed_official 155:8435094ec241 203 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
mbed_official 155:8435094ec241 204
mbed_official 155:8435094ec241 205 /* Reset USARTSW[1:0], I2CSW and TIMs bits */
mbed_official 155:8435094ec241 206 RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
mbed_official 155:8435094ec241 207
mbed_official 155:8435094ec241 208 /* Disable all interrupts */
mbed_official 155:8435094ec241 209 RCC->CIR = 0x00000000;
mbed_official 155:8435094ec241 210
mbed_official 155:8435094ec241 211 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 155:8435094ec241 212 AHB/APBx prescalers and Flash settings */
mbed_official 155:8435094ec241 213 SetSysClock();
mbed_official 155:8435094ec241 214
mbed_official 155:8435094ec241 215 /* Configure the Vector Table location add offset address ------------------*/
mbed_official 155:8435094ec241 216 #ifdef VECT_TAB_SRAM
mbed_official 155:8435094ec241 217 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official 155:8435094ec241 218 #else
mbed_official 155:8435094ec241 219 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official 155:8435094ec241 220 #endif
mbed_official 155:8435094ec241 221 }
mbed_official 155:8435094ec241 222
mbed_official 155:8435094ec241 223 /**
mbed_official 155:8435094ec241 224 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 155:8435094ec241 225 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 155:8435094ec241 226 * be used by the user application to setup the SysTick timer or configure
mbed_official 155:8435094ec241 227 * other parameters.
mbed_official 155:8435094ec241 228 *
mbed_official 155:8435094ec241 229 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 155:8435094ec241 230 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 155:8435094ec241 231 * based on this variable will be incorrect.
mbed_official 155:8435094ec241 232 *
mbed_official 155:8435094ec241 233 * @note - The system frequency computed by this function is not the real
mbed_official 155:8435094ec241 234 * frequency in the chip. It is calculated based on the predefined
mbed_official 155:8435094ec241 235 * constant and the selected clock source:
mbed_official 155:8435094ec241 236 *
mbed_official 155:8435094ec241 237 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 155:8435094ec241 238 *
mbed_official 155:8435094ec241 239 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 155:8435094ec241 240 *
mbed_official 155:8435094ec241 241 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 155:8435094ec241 242 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 155:8435094ec241 243 *
mbed_official 155:8435094ec241 244 * (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
mbed_official 155:8435094ec241 245 * 8 MHz) but the real value may vary depending on the variations
mbed_official 155:8435094ec241 246 * in voltage and temperature.
mbed_official 155:8435094ec241 247 *
mbed_official 155:8435094ec241 248 * (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
mbed_official 155:8435094ec241 249 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 155:8435094ec241 250 * frequency of the crystal used. Otherwise, this function may
mbed_official 155:8435094ec241 251 * have wrong result.
mbed_official 155:8435094ec241 252 *
mbed_official 155:8435094ec241 253 * - The result of this function could be not correct when using fractional
mbed_official 155:8435094ec241 254 * value for HSE crystal.
mbed_official 155:8435094ec241 255 *
mbed_official 155:8435094ec241 256 * @param None
mbed_official 155:8435094ec241 257 * @retval None
mbed_official 155:8435094ec241 258 */
mbed_official 155:8435094ec241 259 void SystemCoreClockUpdate (void)
mbed_official 155:8435094ec241 260 {
mbed_official 155:8435094ec241 261 uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
mbed_official 155:8435094ec241 262
mbed_official 155:8435094ec241 263 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 155:8435094ec241 264 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 155:8435094ec241 265
mbed_official 155:8435094ec241 266 switch (tmp)
mbed_official 155:8435094ec241 267 {
mbed_official 155:8435094ec241 268 case 0x00: /* HSI used as system clock */
mbed_official 155:8435094ec241 269 SystemCoreClock = HSI_VALUE;
mbed_official 155:8435094ec241 270 break;
mbed_official 155:8435094ec241 271 case 0x04: /* HSE used as system clock */
mbed_official 155:8435094ec241 272 SystemCoreClock = HSE_VALUE;
mbed_official 155:8435094ec241 273 break;
mbed_official 155:8435094ec241 274 case 0x08: /* PLL used as system clock */
mbed_official 155:8435094ec241 275 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 155:8435094ec241 276 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
mbed_official 155:8435094ec241 277 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 155:8435094ec241 278 pllmull = ( pllmull >> 18) + 2;
mbed_official 155:8435094ec241 279
mbed_official 155:8435094ec241 280 if (pllsource == 0x00)
mbed_official 155:8435094ec241 281 {
mbed_official 155:8435094ec241 282 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
mbed_official 155:8435094ec241 283 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
mbed_official 155:8435094ec241 284 }
mbed_official 155:8435094ec241 285 else
mbed_official 155:8435094ec241 286 {
mbed_official 155:8435094ec241 287 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
mbed_official 155:8435094ec241 288 /* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official 155:8435094ec241 289 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
mbed_official 155:8435094ec241 290 }
mbed_official 155:8435094ec241 291 break;
mbed_official 155:8435094ec241 292 default: /* HSI used as system clock */
mbed_official 155:8435094ec241 293 SystemCoreClock = HSI_VALUE;
mbed_official 155:8435094ec241 294 break;
mbed_official 155:8435094ec241 295 }
mbed_official 155:8435094ec241 296 /* Compute HCLK clock frequency ----------------*/
mbed_official 155:8435094ec241 297 /* Get HCLK prescaler */
mbed_official 155:8435094ec241 298 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 155:8435094ec241 299 /* HCLK clock frequency */
mbed_official 155:8435094ec241 300 SystemCoreClock >>= tmp;
mbed_official 155:8435094ec241 301 }
mbed_official 155:8435094ec241 302
mbed_official 155:8435094ec241 303 /**
mbed_official 155:8435094ec241 304 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 155:8435094ec241 305 * AHB/APBx prescalers and Flash settings
mbed_official 155:8435094ec241 306 * @note This function should be called only once the RCC clock configuration
mbed_official 155:8435094ec241 307 * is reset to the default reset state (done in SystemInit() function).
mbed_official 155:8435094ec241 308 * @param None
mbed_official 155:8435094ec241 309 * @retval None
mbed_official 155:8435094ec241 310 */
mbed_official 155:8435094ec241 311 void SetSysClock(void)
mbed_official 155:8435094ec241 312 {
mbed_official 155:8435094ec241 313 /* 1- Try to start with HSE and external clock */
mbed_official 155:8435094ec241 314 #if USE_PLL_HSE_EXTC != 0
mbed_official 155:8435094ec241 315 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 155:8435094ec241 316 #endif
mbed_official 155:8435094ec241 317 {
mbed_official 155:8435094ec241 318 /* 2- If fail try to start with HSE and external xtal */
mbed_official 155:8435094ec241 319 #if USE_PLL_HSE_XTAL != 0
mbed_official 155:8435094ec241 320 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 155:8435094ec241 321 #endif
mbed_official 155:8435094ec241 322 {
mbed_official 155:8435094ec241 323 /* 3- If fail start with HSI clock */
mbed_official 155:8435094ec241 324 if (SetSysClock_PLL_HSI() == 0)
mbed_official 155:8435094ec241 325 {
mbed_official 155:8435094ec241 326 while(1)
mbed_official 155:8435094ec241 327 {
mbed_official 155:8435094ec241 328 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 155:8435094ec241 329 }
mbed_official 155:8435094ec241 330 }
mbed_official 155:8435094ec241 331 }
mbed_official 155:8435094ec241 332 }
mbed_official 155:8435094ec241 333
mbed_official 155:8435094ec241 334 /* Output SYSCLK on MCO pin(PA8) for debugging purpose */
mbed_official 155:8435094ec241 335 /*
mbed_official 155:8435094ec241 336 // Enable GPIOA clock
mbed_official 155:8435094ec241 337 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
mbed_official 155:8435094ec241 338 // Configure MCO pin (PA8)
mbed_official 155:8435094ec241 339 GPIO_InitTypeDef GPIO_InitStructure;
mbed_official 155:8435094ec241 340 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
mbed_official 155:8435094ec241 341 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
mbed_official 155:8435094ec241 342 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
mbed_official 155:8435094ec241 343 GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
mbed_official 155:8435094ec241 344 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
mbed_official 155:8435094ec241 345 GPIO_Init(GPIOA, &GPIO_InitStructure);
mbed_official 155:8435094ec241 346 // Select the clock to output
mbed_official 155:8435094ec241 347 RCC_MCOConfig(RCC_MCOSource_SYSCLK, RCC_MCOPrescaler_1);
mbed_official 155:8435094ec241 348 */
mbed_official 155:8435094ec241 349 }
mbed_official 155:8435094ec241 350
mbed_official 155:8435094ec241 351 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 155:8435094ec241 352 /******************************************************************************/
mbed_official 155:8435094ec241 353 /* PLL (clocked by HSE) used as System clock source */
mbed_official 155:8435094ec241 354 /******************************************************************************/
mbed_official 155:8435094ec241 355 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 155:8435094ec241 356 {
mbed_official 155:8435094ec241 357 __IO uint32_t StartUpCounter = 0;
mbed_official 155:8435094ec241 358 __IO uint32_t HSEStatus = 0;
mbed_official 155:8435094ec241 359
mbed_official 155:8435094ec241 360 /* Bypass HSE: can be done only if HSE is OFF */
mbed_official 155:8435094ec241 361 RCC->CR &= ((uint32_t)~RCC_CR_HSEON); /* To be sure HSE is OFF */
mbed_official 155:8435094ec241 362 if (bypass != 0)
mbed_official 155:8435094ec241 363 {
mbed_official 155:8435094ec241 364 RCC->CR |= ((uint32_t)RCC_CR_HSEBYP);
mbed_official 155:8435094ec241 365 }
mbed_official 155:8435094ec241 366 else
mbed_official 155:8435094ec241 367 {
mbed_official 155:8435094ec241 368 RCC->CR &= ((uint32_t)~RCC_CR_HSEBYP);
mbed_official 155:8435094ec241 369 }
mbed_official 155:8435094ec241 370
mbed_official 155:8435094ec241 371 /* Enable HSE */
mbed_official 155:8435094ec241 372 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
mbed_official 155:8435094ec241 373
mbed_official 155:8435094ec241 374 /* Wait till HSE is ready */
mbed_official 155:8435094ec241 375 do
mbed_official 155:8435094ec241 376 {
mbed_official 155:8435094ec241 377 HSEStatus = RCC->CR & RCC_CR_HSERDY;
mbed_official 155:8435094ec241 378 StartUpCounter++;
mbed_official 155:8435094ec241 379 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
mbed_official 155:8435094ec241 380
mbed_official 155:8435094ec241 381 /* Check if HSE has started correctly */
mbed_official 155:8435094ec241 382 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
mbed_official 155:8435094ec241 383 {
mbed_official 155:8435094ec241 384 /* Enable prefetch buffer and set flash latency
mbed_official 155:8435094ec241 385 0WS for 0 < SYSCLK <= 24 MHz
mbed_official 155:8435094ec241 386 1WS for 24 < SYSCLK <= 48 MHz
mbed_official 155:8435094ec241 387 2WS for 48 < SYSCLK <= 72 MHz */
mbed_official 155:8435094ec241 388 FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; /* 2 WS */
mbed_official 155:8435094ec241 389
mbed_official 155:8435094ec241 390 /* Warning: values are obtained with external xtal or clock = 8 MHz */
mbed_official 155:8435094ec241 391 /* SYSCLK = 72 MHz (8 MHz * 9) */
mbed_official 155:8435094ec241 392 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
mbed_official 155:8435094ec241 393 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9
mbed_official 155:8435094ec241 394 | RCC_CFGR_HPRE_DIV1 /* HCLK = 72 MHz */
mbed_official 155:8435094ec241 395 | RCC_CFGR_PPRE2_DIV1 /* PCLK2 = 72 MHz */
mbed_official 155:8435094ec241 396 | RCC_CFGR_PPRE1_DIV2); /* PCLK1 = 36 MHz */
mbed_official 155:8435094ec241 397 /* USBCLK = 48 MHz (72 MHz / 1.5) --> USB OK */
mbed_official 155:8435094ec241 398
mbed_official 155:8435094ec241 399 /* Enable PLL */
mbed_official 155:8435094ec241 400 RCC->CR |= RCC_CR_PLLON;
mbed_official 155:8435094ec241 401
mbed_official 155:8435094ec241 402 /* Wait till PLL is ready */
mbed_official 155:8435094ec241 403 while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official 155:8435094ec241 404 {
mbed_official 155:8435094ec241 405 }
mbed_official 155:8435094ec241 406
mbed_official 155:8435094ec241 407 /* Select PLL as system clock source */
mbed_official 155:8435094ec241 408 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 155:8435094ec241 409 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official 155:8435094ec241 410
mbed_official 155:8435094ec241 411 /* Wait till PLL is used as system clock source */
mbed_official 155:8435094ec241 412 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
mbed_official 155:8435094ec241 413 {
mbed_official 155:8435094ec241 414 }
mbed_official 155:8435094ec241 415
mbed_official 155:8435094ec241 416 return 1; // OK
mbed_official 155:8435094ec241 417 }
mbed_official 155:8435094ec241 418 else
mbed_official 155:8435094ec241 419 {
mbed_official 155:8435094ec241 420 return 0; // FAIL
mbed_official 155:8435094ec241 421 }
mbed_official 155:8435094ec241 422 }
mbed_official 155:8435094ec241 423 #endif
mbed_official 155:8435094ec241 424
mbed_official 155:8435094ec241 425 /******************************************************************************/
mbed_official 155:8435094ec241 426 /* PLL (clocked by HSI) used as System clock source */
mbed_official 155:8435094ec241 427 /******************************************************************************/
mbed_official 155:8435094ec241 428 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 155:8435094ec241 429 {
mbed_official 155:8435094ec241 430 /* At this stage the HSI is already enabled and used as System clock source */
mbed_official 155:8435094ec241 431
mbed_official 155:8435094ec241 432 /* Enable prefetch buffer and set flash latency
mbed_official 155:8435094ec241 433 0WS for 0 < SYSCLK <= 24 MHz
mbed_official 155:8435094ec241 434 1WS for 24 < SYSCLK <= 48 MHz
mbed_official 155:8435094ec241 435 2WS for 48 < SYSCLK <= 72 MHz */
mbed_official 155:8435094ec241 436 FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1; /* 2 WS */
mbed_official 155:8435094ec241 437
mbed_official 155:8435094ec241 438 /* SYSCLK = 64 MHz (8 MHz / 2 * 16) */
mbed_official 155:8435094ec241 439 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
mbed_official 155:8435094ec241 440 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL16
mbed_official 155:8435094ec241 441 | RCC_CFGR_HPRE_DIV1 /* HCLK = 64 MHz */
mbed_official 155:8435094ec241 442 | RCC_CFGR_PPRE2_DIV1 /* PCLK2 = 64 MHz */
mbed_official 155:8435094ec241 443 | RCC_CFGR_PPRE1_DIV2); /* PCLK1 = 32 MHz */
mbed_official 155:8435094ec241 444 /* USBCLK = 42.667 MHz (64 MHz / 1.5) --> USB NOT POSSIBLE */
mbed_official 155:8435094ec241 445
mbed_official 155:8435094ec241 446 /* Enable PLL */
mbed_official 155:8435094ec241 447 RCC->CR |= RCC_CR_PLLON;
mbed_official 155:8435094ec241 448
mbed_official 155:8435094ec241 449 /* Wait till PLL is ready */
mbed_official 155:8435094ec241 450 while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official 155:8435094ec241 451 {
mbed_official 155:8435094ec241 452 }
mbed_official 155:8435094ec241 453
mbed_official 155:8435094ec241 454 /* Select PLL as system clock source */
mbed_official 155:8435094ec241 455 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 155:8435094ec241 456 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official 155:8435094ec241 457
mbed_official 155:8435094ec241 458 /* Wait till PLL is used as system clock source */
mbed_official 155:8435094ec241 459 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
mbed_official 155:8435094ec241 460 {
mbed_official 155:8435094ec241 461 }
mbed_official 155:8435094ec241 462
mbed_official 155:8435094ec241 463 return 1; // OK
mbed_official 155:8435094ec241 464 }
mbed_official 155:8435094ec241 465
mbed_official 155:8435094ec241 466 /**
mbed_official 155:8435094ec241 467 * @}
mbed_official 155:8435094ec241 468 */
mbed_official 155:8435094ec241 469
mbed_official 155:8435094ec241 470 /**
mbed_official 155:8435094ec241 471 * @}
mbed_official 155:8435094ec241 472 */
mbed_official 155:8435094ec241 473
mbed_official 155:8435094ec241 474 /**
mbed_official 155:8435094ec241 475 * @}
mbed_official 155:8435094ec241 476 */
mbed_official 155:8435094ec241 477
mbed_official 155:8435094ec241 478 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/