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targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51.h@637:ed69428d4850, 2015-12-22 (annotated)

Committer:
jaerts
Date:
Tue Dec 22 13:22:16 2015 +0000
Revision:
637:ed69428d4850
Parent:
501:36015dec7d16 
Add very shady LPC1768 CAN Filter implementation

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 501:36015dec7d16 1
mbed_official 501:36015dec7d16 2 /****************************************************************************************************//**
mbed_official 501:36015dec7d16 3 * @file nRF51.h
mbed_official 501:36015dec7d16 4 *
mbed_official 501:36015dec7d16 5 * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
mbed_official 501:36015dec7d16 6 * nRF51 from Nordic Semiconductor.
mbed_official 501:36015dec7d16 7 *
mbed_official 501:36015dec7d16 8 * @version V522
mbed_official 501:36015dec7d16 9 * @date 31. October 2014
mbed_official 85:e1a8e879a6a9 10 *
mbed_official 501:36015dec7d16 11 * @note Generated with SVDConv V2.81d
mbed_official 501:36015dec7d16 12 * from CMSIS SVD File 'nRF51.xml' Version 522,
mbed_official 501:36015dec7d16 13 *
mbed_official 501:36015dec7d16 14 * @par Copyright (c) 2013, Nordic Semiconductor ASA
mbed_official 501:36015dec7d16 15 * All rights reserved.
mbed_official 501:36015dec7d16 16 *
mbed_official 501:36015dec7d16 17 * Redistribution and use in source and binary forms, with or without
mbed_official 501:36015dec7d16 18 * modification, are permitted provided that the following conditions are met:
mbed_official 501:36015dec7d16 19 *
mbed_official 501:36015dec7d16 20 * * Redistributions of source code must retain the above copyright notice, this
mbed_official 501:36015dec7d16 21 * list of conditions and the following disclaimer.
mbed_official 85:e1a8e879a6a9 22 *
mbed_official 501:36015dec7d16 23 * * Redistributions in binary form must reproduce the above copyright notice,
mbed_official 501:36015dec7d16 24 * this list of conditions and the following disclaimer in the documentation
mbed_official 501:36015dec7d16 25 * and/or other materials provided with the distribution.
mbed_official 501:36015dec7d16 26 *
mbed_official 501:36015dec7d16 27 * * Neither the name of Nordic Semiconductor ASA nor the names of its
mbed_official 501:36015dec7d16 28 * contributors may be used to endorse or promote products derived from
mbed_official 501:36015dec7d16 29 * this software without specific prior written permission.
mbed_official 104:a6a92e2e5a92 30 *
mbed_official 501:36015dec7d16 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 501:36015dec7d16 32 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 501:36015dec7d16 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 501:36015dec7d16 34 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 501:36015dec7d16 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 501:36015dec7d16 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 501:36015dec7d16 37 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 501:36015dec7d16 38 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 501:36015dec7d16 39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 501:36015dec7d16 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 501:36015dec7d16 41 *
mbed_official 501:36015dec7d16 42 *
mbed_official 501:36015dec7d16 43 *******************************************************************************************************/
mbed_official 85:e1a8e879a6a9 44
mbed_official 85:e1a8e879a6a9 45
mbed_official 85:e1a8e879a6a9 46
mbed_official 85:e1a8e879a6a9 47 /** @addtogroup Nordic Semiconductor
mbed_official 85:e1a8e879a6a9 48 * @{
mbed_official 85:e1a8e879a6a9 49 */
mbed_official 85:e1a8e879a6a9 50
mbed_official 85:e1a8e879a6a9 51 /** @addtogroup nRF51
mbed_official 85:e1a8e879a6a9 52 * @{
mbed_official 85:e1a8e879a6a9 53 */
mbed_official 85:e1a8e879a6a9 54
mbed_official 85:e1a8e879a6a9 55 #ifndef NRF51_H
mbed_official 85:e1a8e879a6a9 56 #define NRF51_H
mbed_official 85:e1a8e879a6a9 57
mbed_official 85:e1a8e879a6a9 58 #ifdef __cplusplus
mbed_official 85:e1a8e879a6a9 59 extern "C" {
mbed_official 85:e1a8e879a6a9 60 #endif
mbed_official 85:e1a8e879a6a9 61
mbed_official 85:e1a8e879a6a9 62
mbed_official 85:e1a8e879a6a9 63 /* ------------------------- Interrupt Number Definition ------------------------ */
mbed_official 85:e1a8e879a6a9 64
mbed_official 85:e1a8e879a6a9 65 typedef enum {
mbed_official 85:e1a8e879a6a9 66 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
mbed_official 85:e1a8e879a6a9 67 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
mbed_official 85:e1a8e879a6a9 68 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
mbed_official 85:e1a8e879a6a9 69 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
mbed_official 85:e1a8e879a6a9 70 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
mbed_official 85:e1a8e879a6a9 71 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
mbed_official 85:e1a8e879a6a9 72 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
mbed_official 85:e1a8e879a6a9 73 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
mbed_official 85:e1a8e879a6a9 74 /* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
mbed_official 85:e1a8e879a6a9 75 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
mbed_official 85:e1a8e879a6a9 76 RADIO_IRQn = 1, /*!< 1 RADIO */
mbed_official 85:e1a8e879a6a9 77 UART0_IRQn = 2, /*!< 2 UART0 */
mbed_official 85:e1a8e879a6a9 78 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
mbed_official 85:e1a8e879a6a9 79 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
mbed_official 85:e1a8e879a6a9 80 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
mbed_official 85:e1a8e879a6a9 81 ADC_IRQn = 7, /*!< 7 ADC */
mbed_official 85:e1a8e879a6a9 82 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
mbed_official 85:e1a8e879a6a9 83 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
mbed_official 85:e1a8e879a6a9 84 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
mbed_official 85:e1a8e879a6a9 85 RTC0_IRQn = 11, /*!< 11 RTC0 */
mbed_official 85:e1a8e879a6a9 86 TEMP_IRQn = 12, /*!< 12 TEMP */
mbed_official 85:e1a8e879a6a9 87 RNG_IRQn = 13, /*!< 13 RNG */
mbed_official 85:e1a8e879a6a9 88 ECB_IRQn = 14, /*!< 14 ECB */
mbed_official 85:e1a8e879a6a9 89 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
mbed_official 85:e1a8e879a6a9 90 WDT_IRQn = 16, /*!< 16 WDT */
mbed_official 85:e1a8e879a6a9 91 RTC1_IRQn = 17, /*!< 17 RTC1 */
mbed_official 85:e1a8e879a6a9 92 QDEC_IRQn = 18, /*!< 18 QDEC */
mbed_official 501:36015dec7d16 93 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
mbed_official 85:e1a8e879a6a9 94 SWI0_IRQn = 20, /*!< 20 SWI0 */
mbed_official 85:e1a8e879a6a9 95 SWI1_IRQn = 21, /*!< 21 SWI1 */
mbed_official 85:e1a8e879a6a9 96 SWI2_IRQn = 22, /*!< 22 SWI2 */
mbed_official 85:e1a8e879a6a9 97 SWI3_IRQn = 23, /*!< 23 SWI3 */
mbed_official 85:e1a8e879a6a9 98 SWI4_IRQn = 24, /*!< 24 SWI4 */
mbed_official 85:e1a8e879a6a9 99 SWI5_IRQn = 25 /*!< 25 SWI5 */
mbed_official 85:e1a8e879a6a9 100 } IRQn_Type;
mbed_official 85:e1a8e879a6a9 101
mbed_official 85:e1a8e879a6a9 102
mbed_official 85:e1a8e879a6a9 103 /** @addtogroup Configuration_of_CMSIS
mbed_official 85:e1a8e879a6a9 104 * @{
mbed_official 85:e1a8e879a6a9 105 */
mbed_official 85:e1a8e879a6a9 106
mbed_official 85:e1a8e879a6a9 107
mbed_official 85:e1a8e879a6a9 108 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 109 /* ================ Processor and Core Peripheral Section ================ */
mbed_official 85:e1a8e879a6a9 110 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 111
mbed_official 501:36015dec7d16 112 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
mbed_official 85:e1a8e879a6a9 113 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
mbed_official 85:e1a8e879a6a9 114 #define __MPU_PRESENT 0 /*!< MPU present or not */
mbed_official 85:e1a8e879a6a9 115 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
mbed_official 85:e1a8e879a6a9 116 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 85:e1a8e879a6a9 117 /** @} */ /* End of group Configuration_of_CMSIS */
mbed_official 85:e1a8e879a6a9 118
mbed_official 501:36015dec7d16 119 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
mbed_official 501:36015dec7d16 120 #include "system_nrf51.h" /*!< nRF51 System */
mbed_official 85:e1a8e879a6a9 121
mbed_official 85:e1a8e879a6a9 122 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 123 /* ================ Device Specific Peripheral Section ================ */
mbed_official 85:e1a8e879a6a9 124 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 125
mbed_official 85:e1a8e879a6a9 126
mbed_official 85:e1a8e879a6a9 127 /** @addtogroup Device_Peripheral_Registers
mbed_official 85:e1a8e879a6a9 128 * @{
mbed_official 85:e1a8e879a6a9 129 */
mbed_official 85:e1a8e879a6a9 130
mbed_official 85:e1a8e879a6a9 131
mbed_official 85:e1a8e879a6a9 132 /* ------------------- Start of section using anonymous unions ------------------ */
mbed_official 85:e1a8e879a6a9 133 #if defined(__CC_ARM)
mbed_official 85:e1a8e879a6a9 134 #pragma push
mbed_official 85:e1a8e879a6a9 135 #pragma anon_unions
mbed_official 85:e1a8e879a6a9 136 #elif defined(__ICCARM__)
mbed_official 85:e1a8e879a6a9 137 #pragma language=extended
mbed_official 85:e1a8e879a6a9 138 #elif defined(__GNUC__)
mbed_official 85:e1a8e879a6a9 139 /* anonymous unions are enabled by default */
mbed_official 85:e1a8e879a6a9 140 #elif defined(__TMS470__)
mbed_official 85:e1a8e879a6a9 141 /* anonymous unions are enabled by default */
mbed_official 85:e1a8e879a6a9 142 #elif defined(__TASKING__)
mbed_official 85:e1a8e879a6a9 143 #pragma warning 586
mbed_official 85:e1a8e879a6a9 144 #else
mbed_official 85:e1a8e879a6a9 145 #warning Not supported compiler type
mbed_official 85:e1a8e879a6a9 146 #endif
mbed_official 85:e1a8e879a6a9 147
mbed_official 85:e1a8e879a6a9 148
mbed_official 85:e1a8e879a6a9 149 typedef struct {
mbed_official 85:e1a8e879a6a9 150 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
mbed_official 85:e1a8e879a6a9 151 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
mbed_official 85:e1a8e879a6a9 152 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
mbed_official 85:e1a8e879a6a9 153 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
mbed_official 85:e1a8e879a6a9 154 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
mbed_official 85:e1a8e879a6a9 155 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
mbed_official 85:e1a8e879a6a9 156 } AMLI_RAMPRI_Type;
mbed_official 85:e1a8e879a6a9 157
mbed_official 85:e1a8e879a6a9 158 typedef struct {
mbed_official 501:36015dec7d16 159 __IO uint32_t SCK; /*!< Pin select for SCK. */
mbed_official 501:36015dec7d16 160 __IO uint32_t MOSI; /*!< Pin select for MOSI. */
mbed_official 501:36015dec7d16 161 __IO uint32_t MISO; /*!< Pin select for MISO. */
mbed_official 501:36015dec7d16 162 } SPIM_PSEL_Type;
mbed_official 501:36015dec7d16 163
mbed_official 501:36015dec7d16 164 typedef struct {
mbed_official 501:36015dec7d16 165 __IO uint32_t PTR; /*!< Data pointer. */
mbed_official 501:36015dec7d16 166 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */
mbed_official 501:36015dec7d16 167 __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */
mbed_official 501:36015dec7d16 168 } SPIM_RXD_Type;
mbed_official 501:36015dec7d16 169
mbed_official 501:36015dec7d16 170 typedef struct {
mbed_official 501:36015dec7d16 171 __IO uint32_t PTR; /*!< Data pointer. */
mbed_official 501:36015dec7d16 172 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */
mbed_official 501:36015dec7d16 173 __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */
mbed_official 501:36015dec7d16 174 } SPIM_TXD_Type;
mbed_official 501:36015dec7d16 175
mbed_official 501:36015dec7d16 176 typedef struct {
mbed_official 85:e1a8e879a6a9 177 __O uint32_t EN; /*!< Enable channel group. */
mbed_official 85:e1a8e879a6a9 178 __O uint32_t DIS; /*!< Disable channel group. */
mbed_official 85:e1a8e879a6a9 179 } PPI_TASKS_CHG_Type;
mbed_official 85:e1a8e879a6a9 180
mbed_official 85:e1a8e879a6a9 181 typedef struct {
mbed_official 85:e1a8e879a6a9 182 __IO uint32_t EEP; /*!< Channel event end-point. */
mbed_official 85:e1a8e879a6a9 183 __IO uint32_t TEP; /*!< Channel task end-point. */
mbed_official 85:e1a8e879a6a9 184 } PPI_CH_Type;
mbed_official 85:e1a8e879a6a9 185
mbed_official 501:36015dec7d16 186 typedef struct {
mbed_official 501:36015dec7d16 187 __I uint32_t PART; /*!< Part code */
mbed_official 501:36015dec7d16 188 __I uint32_t VARIANT; /*!< Part variant */
mbed_official 501:36015dec7d16 189 __I uint32_t PACKAGE; /*!< Package option */
mbed_official 501:36015dec7d16 190 __I uint32_t RAM; /*!< RAM variant */
mbed_official 501:36015dec7d16 191 __I uint32_t FLASH; /*!< Flash variant */
mbed_official 501:36015dec7d16 192 __I uint32_t RESERVED[3]; /*!< Reserved */
mbed_official 501:36015dec7d16 193 } FICR_INFO_Type;
mbed_official 501:36015dec7d16 194
mbed_official 85:e1a8e879a6a9 195
mbed_official 85:e1a8e879a6a9 196 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 197 /* ================ POWER ================ */
mbed_official 85:e1a8e879a6a9 198 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 199
mbed_official 85:e1a8e879a6a9 200
mbed_official 85:e1a8e879a6a9 201 /**
mbed_official 85:e1a8e879a6a9 202 * @brief Power Control. (POWER)
mbed_official 85:e1a8e879a6a9 203 */
mbed_official 85:e1a8e879a6a9 204
mbed_official 85:e1a8e879a6a9 205 typedef struct { /*!< POWER Structure */
mbed_official 85:e1a8e879a6a9 206 __I uint32_t RESERVED0[30];
mbed_official 85:e1a8e879a6a9 207 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
mbed_official 85:e1a8e879a6a9 208 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
mbed_official 85:e1a8e879a6a9 209 __I uint32_t RESERVED1[34];
mbed_official 85:e1a8e879a6a9 210 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
mbed_official 85:e1a8e879a6a9 211 __I uint32_t RESERVED2[126];
mbed_official 85:e1a8e879a6a9 212 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 213 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 214 __I uint32_t RESERVED3[61];
mbed_official 85:e1a8e879a6a9 215 __IO uint32_t RESETREAS; /*!< Reset reason. */
mbed_official 501:36015dec7d16 216 __I uint32_t RESERVED4[9];
mbed_official 501:36015dec7d16 217 __I uint32_t RAMSTATUS; /*!< Ram status register. */
mbed_official 501:36015dec7d16 218 __I uint32_t RESERVED5[53];
mbed_official 85:e1a8e879a6a9 219 __O uint32_t SYSTEMOFF; /*!< System off register. */
mbed_official 501:36015dec7d16 220 __I uint32_t RESERVED6[3];
mbed_official 85:e1a8e879a6a9 221 __IO uint32_t POFCON; /*!< Power failure configuration. */
mbed_official 501:36015dec7d16 222 __I uint32_t RESERVED7[2];
mbed_official 85:e1a8e879a6a9 223 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
mbed_official 85:e1a8e879a6a9 224 register. */
mbed_official 501:36015dec7d16 225 __I uint32_t RESERVED8;
mbed_official 85:e1a8e879a6a9 226 __IO uint32_t RAMON; /*!< Ram on/off. */
mbed_official 501:36015dec7d16 227 __I uint32_t RESERVED9[7];
mbed_official 85:e1a8e879a6a9 228 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
mbed_official 85:e1a8e879a6a9 229 is a retained register. */
mbed_official 501:36015dec7d16 230 __I uint32_t RESERVED10[3];
mbed_official 501:36015dec7d16 231 __IO uint32_t RAMONB; /*!< Ram on/off. */
mbed_official 501:36015dec7d16 232 __I uint32_t RESERVED11[8];
mbed_official 85:e1a8e879a6a9 233 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
mbed_official 501:36015dec7d16 234 __I uint32_t RESERVED12[291];
mbed_official 501:36015dec7d16 235 __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
mbed_official 85:e1a8e879a6a9 236 } NRF_POWER_Type;
mbed_official 85:e1a8e879a6a9 237
mbed_official 85:e1a8e879a6a9 238
mbed_official 85:e1a8e879a6a9 239 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 240 /* ================ CLOCK ================ */
mbed_official 85:e1a8e879a6a9 241 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 242
mbed_official 85:e1a8e879a6a9 243
mbed_official 85:e1a8e879a6a9 244 /**
mbed_official 85:e1a8e879a6a9 245 * @brief Clock control. (CLOCK)
mbed_official 85:e1a8e879a6a9 246 */
mbed_official 85:e1a8e879a6a9 247
mbed_official 85:e1a8e879a6a9 248 typedef struct { /*!< CLOCK Structure */
mbed_official 85:e1a8e879a6a9 249 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
mbed_official 85:e1a8e879a6a9 250 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
mbed_official 85:e1a8e879a6a9 251 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
mbed_official 85:e1a8e879a6a9 252 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
mbed_official 85:e1a8e879a6a9 253 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
mbed_official 85:e1a8e879a6a9 254 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
mbed_official 85:e1a8e879a6a9 255 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
mbed_official 85:e1a8e879a6a9 256 __I uint32_t RESERVED0[57];
mbed_official 85:e1a8e879a6a9 257 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
mbed_official 85:e1a8e879a6a9 258 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
mbed_official 85:e1a8e879a6a9 259 __I uint32_t RESERVED1;
mbed_official 501:36015dec7d16 260 __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
mbed_official 501:36015dec7d16 261 __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
mbed_official 85:e1a8e879a6a9 262 __I uint32_t RESERVED2[124];
mbed_official 85:e1a8e879a6a9 263 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 264 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 501:36015dec7d16 265 __I uint32_t RESERVED3[63];
mbed_official 501:36015dec7d16 266 __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
mbed_official 85:e1a8e879a6a9 267 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
mbed_official 501:36015dec7d16 268 __I uint32_t RESERVED4;
mbed_official 501:36015dec7d16 269 __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
mbed_official 85:e1a8e879a6a9 270 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
mbed_official 501:36015dec7d16 271 __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
mbed_official 501:36015dec7d16 272 triggered. */
mbed_official 501:36015dec7d16 273 __I uint32_t RESERVED5[62];
mbed_official 85:e1a8e879a6a9 274 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
mbed_official 85:e1a8e879a6a9 275 __I uint32_t RESERVED6[7];
mbed_official 85:e1a8e879a6a9 276 __IO uint32_t CTIV; /*!< Calibration timer interval. */
mbed_official 85:e1a8e879a6a9 277 __I uint32_t RESERVED7[5];
mbed_official 85:e1a8e879a6a9 278 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
mbed_official 85:e1a8e879a6a9 279 } NRF_CLOCK_Type;
mbed_official 85:e1a8e879a6a9 280
mbed_official 85:e1a8e879a6a9 281
mbed_official 85:e1a8e879a6a9 282 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 283 /* ================ MPU ================ */
mbed_official 85:e1a8e879a6a9 284 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 285
mbed_official 85:e1a8e879a6a9 286
mbed_official 85:e1a8e879a6a9 287 /**
mbed_official 85:e1a8e879a6a9 288 * @brief Memory Protection Unit. (MPU)
mbed_official 85:e1a8e879a6a9 289 */
mbed_official 85:e1a8e879a6a9 290
mbed_official 85:e1a8e879a6a9 291 typedef struct { /*!< MPU Structure */
mbed_official 85:e1a8e879a6a9 292 __I uint32_t RESERVED0[330];
mbed_official 85:e1a8e879a6a9 293 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
mbed_official 85:e1a8e879a6a9 294 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
mbed_official 85:e1a8e879a6a9 295 __I uint32_t RESERVED1[52];
mbed_official 501:36015dec7d16 296 __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
mbed_official 501:36015dec7d16 297 __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
mbed_official 501:36015dec7d16 298 __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
mbed_official 501:36015dec7d16 299 __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
mbed_official 85:e1a8e879a6a9 300 } NRF_MPU_Type;
mbed_official 85:e1a8e879a6a9 301
mbed_official 85:e1a8e879a6a9 302
mbed_official 85:e1a8e879a6a9 303 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 304 /* ================ PU ================ */
mbed_official 85:e1a8e879a6a9 305 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 306
mbed_official 85:e1a8e879a6a9 307
mbed_official 85:e1a8e879a6a9 308 /**
mbed_official 85:e1a8e879a6a9 309 * @brief Patch unit. (PU)
mbed_official 85:e1a8e879a6a9 310 */
mbed_official 85:e1a8e879a6a9 311
mbed_official 85:e1a8e879a6a9 312 typedef struct { /*!< PU Structure */
mbed_official 85:e1a8e879a6a9 313 __I uint32_t RESERVED0[448];
mbed_official 85:e1a8e879a6a9 314 __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
mbed_official 85:e1a8e879a6a9 315 __I uint32_t RESERVED1[24];
mbed_official 85:e1a8e879a6a9 316 __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
mbed_official 85:e1a8e879a6a9 317 __I uint32_t RESERVED2[24];
mbed_official 85:e1a8e879a6a9 318 __IO uint32_t PATCHEN; /*!< Patch enable register. */
mbed_official 85:e1a8e879a6a9 319 __IO uint32_t PATCHENSET; /*!< Patch enable register. */
mbed_official 85:e1a8e879a6a9 320 __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
mbed_official 85:e1a8e879a6a9 321 } NRF_PU_Type;
mbed_official 85:e1a8e879a6a9 322
mbed_official 85:e1a8e879a6a9 323
mbed_official 85:e1a8e879a6a9 324 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 325 /* ================ AMLI ================ */
mbed_official 85:e1a8e879a6a9 326 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 327
mbed_official 85:e1a8e879a6a9 328
mbed_official 85:e1a8e879a6a9 329 /**
mbed_official 85:e1a8e879a6a9 330 * @brief AHB Multi-Layer Interface. (AMLI)
mbed_official 85:e1a8e879a6a9 331 */
mbed_official 85:e1a8e879a6a9 332
mbed_official 85:e1a8e879a6a9 333 typedef struct { /*!< AMLI Structure */
mbed_official 85:e1a8e879a6a9 334 __I uint32_t RESERVED0[896];
mbed_official 85:e1a8e879a6a9 335 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
mbed_official 85:e1a8e879a6a9 336 } NRF_AMLI_Type;
mbed_official 85:e1a8e879a6a9 337
mbed_official 85:e1a8e879a6a9 338
mbed_official 85:e1a8e879a6a9 339 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 340 /* ================ RADIO ================ */
mbed_official 85:e1a8e879a6a9 341 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 342
mbed_official 85:e1a8e879a6a9 343
mbed_official 85:e1a8e879a6a9 344 /**
mbed_official 85:e1a8e879a6a9 345 * @brief The radio. (RADIO)
mbed_official 85:e1a8e879a6a9 346 */
mbed_official 85:e1a8e879a6a9 347
mbed_official 85:e1a8e879a6a9 348 typedef struct { /*!< RADIO Structure */
mbed_official 85:e1a8e879a6a9 349 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
mbed_official 85:e1a8e879a6a9 350 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
mbed_official 85:e1a8e879a6a9 351 __O uint32_t TASKS_START; /*!< Start radio. */
mbed_official 85:e1a8e879a6a9 352 __O uint32_t TASKS_STOP; /*!< Stop radio. */
mbed_official 85:e1a8e879a6a9 353 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
mbed_official 85:e1a8e879a6a9 354 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
mbed_official 85:e1a8e879a6a9 355 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
mbed_official 85:e1a8e879a6a9 356 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
mbed_official 85:e1a8e879a6a9 357 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
mbed_official 85:e1a8e879a6a9 358 __I uint32_t RESERVED0[55];
mbed_official 85:e1a8e879a6a9 359 __IO uint32_t EVENTS_READY; /*!< Ready event. */
mbed_official 85:e1a8e879a6a9 360 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
mbed_official 85:e1a8e879a6a9 361 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
mbed_official 85:e1a8e879a6a9 362 __IO uint32_t EVENTS_END; /*!< End event. */
mbed_official 85:e1a8e879a6a9 363 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
mbed_official 85:e1a8e879a6a9 364 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
mbed_official 85:e1a8e879a6a9 365 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
mbed_official 85:e1a8e879a6a9 366 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
mbed_official 85:e1a8e879a6a9 367 sample is ready for readout at the RSSISAMPLE register. */
mbed_official 85:e1a8e879a6a9 368 __I uint32_t RESERVED1[2];
mbed_official 85:e1a8e879a6a9 369 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */
mbed_official 85:e1a8e879a6a9 370 __I uint32_t RESERVED2[53];
mbed_official 501:36015dec7d16 371 __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
mbed_official 85:e1a8e879a6a9 372 __I uint32_t RESERVED3[64];
mbed_official 85:e1a8e879a6a9 373 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 374 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 375 __I uint32_t RESERVED4[61];
mbed_official 85:e1a8e879a6a9 376 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
mbed_official 501:36015dec7d16 377 __I uint32_t CD; /*!< Carrier detect. */
mbed_official 85:e1a8e879a6a9 378 __I uint32_t RXMATCH; /*!< Received address. */
mbed_official 85:e1a8e879a6a9 379 __I uint32_t RXCRC; /*!< Received CRC. */
mbed_official 501:36015dec7d16 380 __I uint32_t DAI; /*!< Device address match index. */
mbed_official 501:36015dec7d16 381 __I uint32_t RESERVED5[60];
mbed_official 85:e1a8e879a6a9 382 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 383 __IO uint32_t FREQUENCY; /*!< Frequency. */
mbed_official 85:e1a8e879a6a9 384 __IO uint32_t TXPOWER; /*!< Output power. */
mbed_official 85:e1a8e879a6a9 385 __IO uint32_t MODE; /*!< Data rate and modulation. */
mbed_official 85:e1a8e879a6a9 386 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
mbed_official 85:e1a8e879a6a9 387 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
mbed_official 85:e1a8e879a6a9 388 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 389 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
mbed_official 85:e1a8e879a6a9 390 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
mbed_official 85:e1a8e879a6a9 391 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
mbed_official 85:e1a8e879a6a9 392 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
mbed_official 85:e1a8e879a6a9 393 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
mbed_official 85:e1a8e879a6a9 394 __IO uint32_t CRCCNF; /*!< CRC configuration. */
mbed_official 85:e1a8e879a6a9 395 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
mbed_official 85:e1a8e879a6a9 396 __IO uint32_t CRCINIT; /*!< CRC initial value. */
mbed_official 85:e1a8e879a6a9 397 __IO uint32_t TEST; /*!< Test features enable register. */
mbed_official 85:e1a8e879a6a9 398 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
mbed_official 501:36015dec7d16 399 __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
mbed_official 501:36015dec7d16 400 __I uint32_t RESERVED6;
mbed_official 85:e1a8e879a6a9 401 __I uint32_t STATE; /*!< Current radio state. */
mbed_official 85:e1a8e879a6a9 402 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
mbed_official 501:36015dec7d16 403 __I uint32_t RESERVED7[2];
mbed_official 85:e1a8e879a6a9 404 __IO uint32_t BCC; /*!< Bit counter compare. */
mbed_official 501:36015dec7d16 405 __I uint32_t RESERVED8[39];
mbed_official 85:e1a8e879a6a9 406 __IO uint32_t DAB[8]; /*!< Device address base segment. */
mbed_official 85:e1a8e879a6a9 407 __IO uint32_t DAP[8]; /*!< Device address prefix. */
mbed_official 85:e1a8e879a6a9 408 __IO uint32_t DACNF; /*!< Device address match configuration. */
mbed_official 501:36015dec7d16 409 __I uint32_t RESERVED9[56];
mbed_official 85:e1a8e879a6a9 410 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
mbed_official 85:e1a8e879a6a9 411 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
mbed_official 85:e1a8e879a6a9 412 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
mbed_official 85:e1a8e879a6a9 413 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
mbed_official 85:e1a8e879a6a9 414 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
mbed_official 501:36015dec7d16 415 __I uint32_t RESERVED10[561];
mbed_official 85:e1a8e879a6a9 416 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 417 } NRF_RADIO_Type;
mbed_official 85:e1a8e879a6a9 418
mbed_official 85:e1a8e879a6a9 419
mbed_official 85:e1a8e879a6a9 420 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 421 /* ================ UART ================ */
mbed_official 85:e1a8e879a6a9 422 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 423
mbed_official 85:e1a8e879a6a9 424
mbed_official 85:e1a8e879a6a9 425 /**
mbed_official 85:e1a8e879a6a9 426 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
mbed_official 85:e1a8e879a6a9 427 */
mbed_official 85:e1a8e879a6a9 428
mbed_official 85:e1a8e879a6a9 429 typedef struct { /*!< UART Structure */
mbed_official 85:e1a8e879a6a9 430 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
mbed_official 85:e1a8e879a6a9 431 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
mbed_official 85:e1a8e879a6a9 432 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
mbed_official 85:e1a8e879a6a9 433 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
mbed_official 85:e1a8e879a6a9 434 __I uint32_t RESERVED0[3];
mbed_official 85:e1a8e879a6a9 435 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
mbed_official 85:e1a8e879a6a9 436 __I uint32_t RESERVED1[56];
mbed_official 85:e1a8e879a6a9 437 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
mbed_official 85:e1a8e879a6a9 438 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
mbed_official 85:e1a8e879a6a9 439 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
mbed_official 85:e1a8e879a6a9 440 __I uint32_t RESERVED2[4];
mbed_official 85:e1a8e879a6a9 441 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
mbed_official 85:e1a8e879a6a9 442 __I uint32_t RESERVED3;
mbed_official 85:e1a8e879a6a9 443 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
mbed_official 85:e1a8e879a6a9 444 __I uint32_t RESERVED4[7];
mbed_official 85:e1a8e879a6a9 445 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
mbed_official 85:e1a8e879a6a9 446 __I uint32_t RESERVED5[46];
mbed_official 501:36015dec7d16 447 __IO uint32_t SHORTS; /*!< Shortcuts for UART. */
mbed_official 501:36015dec7d16 448 __I uint32_t RESERVED6[64];
mbed_official 85:e1a8e879a6a9 449 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 450 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 451 __I uint32_t RESERVED7[93];
mbed_official 85:e1a8e879a6a9 452 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
mbed_official 85:e1a8e879a6a9 453 __I uint32_t RESERVED8[31];
mbed_official 85:e1a8e879a6a9 454 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
mbed_official 85:e1a8e879a6a9 455 __I uint32_t RESERVED9;
mbed_official 85:e1a8e879a6a9 456 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
mbed_official 85:e1a8e879a6a9 457 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
mbed_official 85:e1a8e879a6a9 458 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
mbed_official 85:e1a8e879a6a9 459 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
mbed_official 85:e1a8e879a6a9 460 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
mbed_official 501:36015dec7d16 461 Once read the character is consumed. If read when no character
mbed_official 85:e1a8e879a6a9 462 available, the UART will stop working. */
mbed_official 85:e1a8e879a6a9 463 __O uint32_t TXD; /*!< TXD register. */
mbed_official 85:e1a8e879a6a9 464 __I uint32_t RESERVED10;
mbed_official 85:e1a8e879a6a9 465 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
mbed_official 85:e1a8e879a6a9 466 __I uint32_t RESERVED11[17];
mbed_official 85:e1a8e879a6a9 467 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
mbed_official 85:e1a8e879a6a9 468 __I uint32_t RESERVED12[675];
mbed_official 85:e1a8e879a6a9 469 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 470 } NRF_UART_Type;
mbed_official 85:e1a8e879a6a9 471
mbed_official 85:e1a8e879a6a9 472
mbed_official 85:e1a8e879a6a9 473 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 474 /* ================ SPI ================ */
mbed_official 85:e1a8e879a6a9 475 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 476
mbed_official 85:e1a8e879a6a9 477
mbed_official 85:e1a8e879a6a9 478 /**
mbed_official 85:e1a8e879a6a9 479 * @brief SPI master 0. (SPI)
mbed_official 85:e1a8e879a6a9 480 */
mbed_official 85:e1a8e879a6a9 481
mbed_official 85:e1a8e879a6a9 482 typedef struct { /*!< SPI Structure */
mbed_official 85:e1a8e879a6a9 483 __I uint32_t RESERVED0[66];
mbed_official 85:e1a8e879a6a9 484 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
mbed_official 85:e1a8e879a6a9 485 __I uint32_t RESERVED1[126];
mbed_official 85:e1a8e879a6a9 486 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 487 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 488 __I uint32_t RESERVED2[125];
mbed_official 85:e1a8e879a6a9 489 __IO uint32_t ENABLE; /*!< Enable SPI. */
mbed_official 85:e1a8e879a6a9 490 __I uint32_t RESERVED3;
mbed_official 85:e1a8e879a6a9 491 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
mbed_official 85:e1a8e879a6a9 492 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
mbed_official 85:e1a8e879a6a9 493 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
mbed_official 85:e1a8e879a6a9 494 __I uint32_t RESERVED4;
mbed_official 501:36015dec7d16 495 __I uint32_t RXD; /*!< RX data. */
mbed_official 85:e1a8e879a6a9 496 __IO uint32_t TXD; /*!< TX data. */
mbed_official 85:e1a8e879a6a9 497 __I uint32_t RESERVED5;
mbed_official 85:e1a8e879a6a9 498 __IO uint32_t FREQUENCY; /*!< SPI frequency */
mbed_official 85:e1a8e879a6a9 499 __I uint32_t RESERVED6[11];
mbed_official 85:e1a8e879a6a9 500 __IO uint32_t CONFIG; /*!< Configuration register. */
mbed_official 85:e1a8e879a6a9 501 __I uint32_t RESERVED7[681];
mbed_official 85:e1a8e879a6a9 502 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 503 } NRF_SPI_Type;
mbed_official 85:e1a8e879a6a9 504
mbed_official 85:e1a8e879a6a9 505
mbed_official 85:e1a8e879a6a9 506 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 507 /* ================ TWI ================ */
mbed_official 85:e1a8e879a6a9 508 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 509
mbed_official 85:e1a8e879a6a9 510
mbed_official 85:e1a8e879a6a9 511 /**
mbed_official 85:e1a8e879a6a9 512 * @brief Two-wire interface master 0. (TWI)
mbed_official 85:e1a8e879a6a9 513 */
mbed_official 85:e1a8e879a6a9 514
mbed_official 85:e1a8e879a6a9 515 typedef struct { /*!< TWI Structure */
mbed_official 85:e1a8e879a6a9 516 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
mbed_official 85:e1a8e879a6a9 517 __I uint32_t RESERVED0;
mbed_official 85:e1a8e879a6a9 518 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
mbed_official 85:e1a8e879a6a9 519 __I uint32_t RESERVED1[2];
mbed_official 85:e1a8e879a6a9 520 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
mbed_official 85:e1a8e879a6a9 521 __I uint32_t RESERVED2;
mbed_official 85:e1a8e879a6a9 522 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
mbed_official 85:e1a8e879a6a9 523 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
mbed_official 85:e1a8e879a6a9 524 __I uint32_t RESERVED3[56];
mbed_official 85:e1a8e879a6a9 525 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
mbed_official 85:e1a8e879a6a9 526 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
mbed_official 85:e1a8e879a6a9 527 __I uint32_t RESERVED4[4];
mbed_official 85:e1a8e879a6a9 528 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
mbed_official 85:e1a8e879a6a9 529 __I uint32_t RESERVED5;
mbed_official 85:e1a8e879a6a9 530 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
mbed_official 85:e1a8e879a6a9 531 __I uint32_t RESERVED6[4];
mbed_official 85:e1a8e879a6a9 532 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
mbed_official 501:36015dec7d16 533 __I uint32_t RESERVED7[3];
mbed_official 501:36015dec7d16 534 __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
mbed_official 501:36015dec7d16 535 __I uint32_t RESERVED8[45];
mbed_official 85:e1a8e879a6a9 536 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
mbed_official 501:36015dec7d16 537 __I uint32_t RESERVED9[64];
mbed_official 85:e1a8e879a6a9 538 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 539 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 501:36015dec7d16 540 __I uint32_t RESERVED10[110];
mbed_official 85:e1a8e879a6a9 541 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
mbed_official 501:36015dec7d16 542 __I uint32_t RESERVED11[14];
mbed_official 85:e1a8e879a6a9 543 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
mbed_official 501:36015dec7d16 544 __I uint32_t RESERVED12;
mbed_official 85:e1a8e879a6a9 545 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
mbed_official 85:e1a8e879a6a9 546 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
mbed_official 501:36015dec7d16 547 __I uint32_t RESERVED13[2];
mbed_official 501:36015dec7d16 548 __I uint32_t RXD; /*!< RX data register. */
mbed_official 85:e1a8e879a6a9 549 __IO uint32_t TXD; /*!< TX data register. */
mbed_official 501:36015dec7d16 550 __I uint32_t RESERVED14;
mbed_official 85:e1a8e879a6a9 551 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
mbed_official 501:36015dec7d16 552 __I uint32_t RESERVED15[24];
mbed_official 85:e1a8e879a6a9 553 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
mbed_official 501:36015dec7d16 554 __I uint32_t RESERVED16[668];
mbed_official 85:e1a8e879a6a9 555 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 556 } NRF_TWI_Type;
mbed_official 85:e1a8e879a6a9 557
mbed_official 85:e1a8e879a6a9 558
mbed_official 85:e1a8e879a6a9 559 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 560 /* ================ SPIS ================ */
mbed_official 85:e1a8e879a6a9 561 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 562
mbed_official 85:e1a8e879a6a9 563
mbed_official 85:e1a8e879a6a9 564 /**
mbed_official 85:e1a8e879a6a9 565 * @brief SPI slave 1. (SPIS)
mbed_official 85:e1a8e879a6a9 566 */
mbed_official 85:e1a8e879a6a9 567
mbed_official 85:e1a8e879a6a9 568 typedef struct { /*!< SPIS Structure */
mbed_official 85:e1a8e879a6a9 569 __I uint32_t RESERVED0[9];
mbed_official 85:e1a8e879a6a9 570 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
mbed_official 85:e1a8e879a6a9 571 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
mbed_official 85:e1a8e879a6a9 572 __I uint32_t RESERVED1[54];
mbed_official 85:e1a8e879a6a9 573 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
mbed_official 85:e1a8e879a6a9 574 __I uint32_t RESERVED2[8];
mbed_official 85:e1a8e879a6a9 575 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
mbed_official 85:e1a8e879a6a9 576 __I uint32_t RESERVED3[53];
mbed_official 85:e1a8e879a6a9 577 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
mbed_official 85:e1a8e879a6a9 578 __I uint32_t RESERVED4[64];
mbed_official 85:e1a8e879a6a9 579 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 580 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 581 __I uint32_t RESERVED5[61];
mbed_official 85:e1a8e879a6a9 582 __I uint32_t SEMSTAT; /*!< Semaphore status. */
mbed_official 85:e1a8e879a6a9 583 __I uint32_t RESERVED6[15];
mbed_official 85:e1a8e879a6a9 584 __IO uint32_t STATUS; /*!< Status from last transaction. */
mbed_official 85:e1a8e879a6a9 585 __I uint32_t RESERVED7[47];
mbed_official 85:e1a8e879a6a9 586 __IO uint32_t ENABLE; /*!< Enable SPIS. */
mbed_official 85:e1a8e879a6a9 587 __I uint32_t RESERVED8;
mbed_official 85:e1a8e879a6a9 588 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
mbed_official 85:e1a8e879a6a9 589 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
mbed_official 85:e1a8e879a6a9 590 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
mbed_official 85:e1a8e879a6a9 591 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
mbed_official 85:e1a8e879a6a9 592 __I uint32_t RESERVED9[7];
mbed_official 85:e1a8e879a6a9 593 __IO uint32_t RXDPTR; /*!< RX data pointer. */
mbed_official 85:e1a8e879a6a9 594 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
mbed_official 501:36015dec7d16 595 __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
mbed_official 85:e1a8e879a6a9 596 __I uint32_t RESERVED10;
mbed_official 85:e1a8e879a6a9 597 __IO uint32_t TXDPTR; /*!< TX data pointer. */
mbed_official 85:e1a8e879a6a9 598 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
mbed_official 501:36015dec7d16 599 __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
mbed_official 85:e1a8e879a6a9 600 __I uint32_t RESERVED11;
mbed_official 85:e1a8e879a6a9 601 __IO uint32_t CONFIG; /*!< Configuration register. */
mbed_official 85:e1a8e879a6a9 602 __I uint32_t RESERVED12;
mbed_official 85:e1a8e879a6a9 603 __IO uint32_t DEF; /*!< Default character. */
mbed_official 85:e1a8e879a6a9 604 __I uint32_t RESERVED13[24];
mbed_official 85:e1a8e879a6a9 605 __IO uint32_t ORC; /*!< Over-read character. */
mbed_official 85:e1a8e879a6a9 606 __I uint32_t RESERVED14[654];
mbed_official 85:e1a8e879a6a9 607 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 608 } NRF_SPIS_Type;
mbed_official 85:e1a8e879a6a9 609
mbed_official 85:e1a8e879a6a9 610
mbed_official 85:e1a8e879a6a9 611 /* ================================================================================ */
mbed_official 501:36015dec7d16 612 /* ================ SPIM ================ */
mbed_official 501:36015dec7d16 613 /* ================================================================================ */
mbed_official 501:36015dec7d16 614
mbed_official 501:36015dec7d16 615
mbed_official 501:36015dec7d16 616 /**
mbed_official 501:36015dec7d16 617 * @brief SPI master with easyDMA 1. (SPIM)
mbed_official 501:36015dec7d16 618 */
mbed_official 501:36015dec7d16 619
mbed_official 501:36015dec7d16 620 typedef struct { /*!< SPIM Structure */
mbed_official 501:36015dec7d16 621 __I uint32_t RESERVED0[4];
mbed_official 501:36015dec7d16 622 __O uint32_t TASKS_START; /*!< Start SPI transaction. */
mbed_official 501:36015dec7d16 623 __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */
mbed_official 501:36015dec7d16 624 __I uint32_t RESERVED1;
mbed_official 501:36015dec7d16 625 __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */
mbed_official 501:36015dec7d16 626 __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */
mbed_official 501:36015dec7d16 627 __I uint32_t RESERVED2[56];
mbed_official 501:36015dec7d16 628 __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
mbed_official 501:36015dec7d16 629 __I uint32_t RESERVED3[2];
mbed_official 501:36015dec7d16 630 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
mbed_official 501:36015dec7d16 631 __I uint32_t RESERVED4;
mbed_official 501:36015dec7d16 632 __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached. */
mbed_official 501:36015dec7d16 633 __I uint32_t RESERVED5;
mbed_official 501:36015dec7d16 634 __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
mbed_official 501:36015dec7d16 635 __I uint32_t RESERVED6[10];
mbed_official 501:36015dec7d16 636 __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
mbed_official 501:36015dec7d16 637 __I uint32_t RESERVED7[44];
mbed_official 501:36015dec7d16 638 __IO uint32_t SHORTS; /*!< Shortcuts for SPIM. */
mbed_official 501:36015dec7d16 639 __I uint32_t RESERVED8[64];
mbed_official 501:36015dec7d16 640 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 501:36015dec7d16 641 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 501:36015dec7d16 642 __I uint32_t RESERVED9[125];
mbed_official 501:36015dec7d16 643 __IO uint32_t ENABLE; /*!< Enable SPIM. */
mbed_official 501:36015dec7d16 644 __I uint32_t RESERVED10;
mbed_official 501:36015dec7d16 645 SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
mbed_official 501:36015dec7d16 646 __I uint32_t RESERVED11;
mbed_official 501:36015dec7d16 647 __I uint32_t RXDDATA; /*!< RXD register. */
mbed_official 501:36015dec7d16 648 __IO uint32_t TXDDATA; /*!< TXD register. */
mbed_official 501:36015dec7d16 649 __I uint32_t RESERVED12;
mbed_official 501:36015dec7d16 650 __IO uint32_t FREQUENCY; /*!< SPI frequency. */
mbed_official 501:36015dec7d16 651 __I uint32_t RESERVED13[3];
mbed_official 501:36015dec7d16 652 SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
mbed_official 501:36015dec7d16 653 __I uint32_t RESERVED14;
mbed_official 501:36015dec7d16 654 SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
mbed_official 501:36015dec7d16 655 __I uint32_t RESERVED15;
mbed_official 501:36015dec7d16 656 __IO uint32_t CONFIG; /*!< Configuration register. */
mbed_official 501:36015dec7d16 657 __I uint32_t RESERVED16[26];
mbed_official 501:36015dec7d16 658 __IO uint32_t ORC; /*!< Over-read character. */
mbed_official 501:36015dec7d16 659 __I uint32_t RESERVED17[654];
mbed_official 501:36015dec7d16 660 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 501:36015dec7d16 661 } NRF_SPIM_Type;
mbed_official 501:36015dec7d16 662
mbed_official 501:36015dec7d16 663
mbed_official 501:36015dec7d16 664 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 665 /* ================ GPIOTE ================ */
mbed_official 85:e1a8e879a6a9 666 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 667
mbed_official 85:e1a8e879a6a9 668
mbed_official 85:e1a8e879a6a9 669 /**
mbed_official 85:e1a8e879a6a9 670 * @brief GPIO tasks and events. (GPIOTE)
mbed_official 85:e1a8e879a6a9 671 */
mbed_official 85:e1a8e879a6a9 672
mbed_official 85:e1a8e879a6a9 673 typedef struct { /*!< GPIOTE Structure */
mbed_official 85:e1a8e879a6a9 674 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
mbed_official 85:e1a8e879a6a9 675 __I uint32_t RESERVED0[60];
mbed_official 85:e1a8e879a6a9 676 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
mbed_official 85:e1a8e879a6a9 677 __I uint32_t RESERVED1[27];
mbed_official 85:e1a8e879a6a9 678 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
mbed_official 85:e1a8e879a6a9 679 __I uint32_t RESERVED2[97];
mbed_official 85:e1a8e879a6a9 680 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 681 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 682 __I uint32_t RESERVED3[129];
mbed_official 85:e1a8e879a6a9 683 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
mbed_official 85:e1a8e879a6a9 684 __I uint32_t RESERVED4[695];
mbed_official 85:e1a8e879a6a9 685 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 686 } NRF_GPIOTE_Type;
mbed_official 85:e1a8e879a6a9 687
mbed_official 85:e1a8e879a6a9 688
mbed_official 85:e1a8e879a6a9 689 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 690 /* ================ ADC ================ */
mbed_official 85:e1a8e879a6a9 691 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 692
mbed_official 85:e1a8e879a6a9 693
mbed_official 85:e1a8e879a6a9 694 /**
mbed_official 85:e1a8e879a6a9 695 * @brief Analog to digital converter. (ADC)
mbed_official 85:e1a8e879a6a9 696 */
mbed_official 85:e1a8e879a6a9 697
mbed_official 85:e1a8e879a6a9 698 typedef struct { /*!< ADC Structure */
mbed_official 85:e1a8e879a6a9 699 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
mbed_official 85:e1a8e879a6a9 700 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
mbed_official 85:e1a8e879a6a9 701 __I uint32_t RESERVED0[62];
mbed_official 85:e1a8e879a6a9 702 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
mbed_official 85:e1a8e879a6a9 703 __I uint32_t RESERVED1[128];
mbed_official 85:e1a8e879a6a9 704 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 705 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 706 __I uint32_t RESERVED2[61];
mbed_official 85:e1a8e879a6a9 707 __I uint32_t BUSY; /*!< ADC busy register. */
mbed_official 85:e1a8e879a6a9 708 __I uint32_t RESERVED3[63];
mbed_official 85:e1a8e879a6a9 709 __IO uint32_t ENABLE; /*!< ADC enable. */
mbed_official 85:e1a8e879a6a9 710 __IO uint32_t CONFIG; /*!< ADC configuration register. */
mbed_official 85:e1a8e879a6a9 711 __I uint32_t RESULT; /*!< Result of ADC conversion. */
mbed_official 85:e1a8e879a6a9 712 __I uint32_t RESERVED4[700];
mbed_official 85:e1a8e879a6a9 713 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 714 } NRF_ADC_Type;
mbed_official 85:e1a8e879a6a9 715
mbed_official 85:e1a8e879a6a9 716
mbed_official 85:e1a8e879a6a9 717 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 718 /* ================ TIMER ================ */
mbed_official 85:e1a8e879a6a9 719 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 720
mbed_official 85:e1a8e879a6a9 721
mbed_official 85:e1a8e879a6a9 722 /**
mbed_official 85:e1a8e879a6a9 723 * @brief Timer 0. (TIMER)
mbed_official 85:e1a8e879a6a9 724 */
mbed_official 85:e1a8e879a6a9 725
mbed_official 85:e1a8e879a6a9 726 typedef struct { /*!< TIMER Structure */
mbed_official 85:e1a8e879a6a9 727 __O uint32_t TASKS_START; /*!< Start Timer. */
mbed_official 85:e1a8e879a6a9 728 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
mbed_official 85:e1a8e879a6a9 729 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
mbed_official 85:e1a8e879a6a9 730 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
mbed_official 501:36015dec7d16 731 __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
mbed_official 501:36015dec7d16 732 __I uint32_t RESERVED0[11];
mbed_official 85:e1a8e879a6a9 733 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
mbed_official 85:e1a8e879a6a9 734 __I uint32_t RESERVED1[60];
mbed_official 85:e1a8e879a6a9 735 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
mbed_official 85:e1a8e879a6a9 736 __I uint32_t RESERVED2[44];
mbed_official 85:e1a8e879a6a9 737 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
mbed_official 85:e1a8e879a6a9 738 __I uint32_t RESERVED3[64];
mbed_official 85:e1a8e879a6a9 739 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 740 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 741 __I uint32_t RESERVED4[126];
mbed_official 85:e1a8e879a6a9 742 __IO uint32_t MODE; /*!< Timer Mode selection. */
mbed_official 85:e1a8e879a6a9 743 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
mbed_official 85:e1a8e879a6a9 744 __I uint32_t RESERVED5;
mbed_official 85:e1a8e879a6a9 745 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
mbed_official 85:e1a8e879a6a9 746 clock frequency is divided by 2^SCALE. */
mbed_official 85:e1a8e879a6a9 747 __I uint32_t RESERVED6[11];
mbed_official 85:e1a8e879a6a9 748 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
mbed_official 85:e1a8e879a6a9 749 __I uint32_t RESERVED7[683];
mbed_official 85:e1a8e879a6a9 750 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 751 } NRF_TIMER_Type;
mbed_official 85:e1a8e879a6a9 752
mbed_official 85:e1a8e879a6a9 753
mbed_official 85:e1a8e879a6a9 754 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 755 /* ================ RTC ================ */
mbed_official 85:e1a8e879a6a9 756 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 757
mbed_official 85:e1a8e879a6a9 758
mbed_official 85:e1a8e879a6a9 759 /**
mbed_official 85:e1a8e879a6a9 760 * @brief Real time counter 0. (RTC)
mbed_official 85:e1a8e879a6a9 761 */
mbed_official 85:e1a8e879a6a9 762
mbed_official 85:e1a8e879a6a9 763 typedef struct { /*!< RTC Structure */
mbed_official 85:e1a8e879a6a9 764 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
mbed_official 85:e1a8e879a6a9 765 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
mbed_official 85:e1a8e879a6a9 766 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
mbed_official 85:e1a8e879a6a9 767 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
mbed_official 85:e1a8e879a6a9 768 __I uint32_t RESERVED0[60];
mbed_official 85:e1a8e879a6a9 769 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
mbed_official 85:e1a8e879a6a9 770 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
mbed_official 85:e1a8e879a6a9 771 __I uint32_t RESERVED1[14];
mbed_official 85:e1a8e879a6a9 772 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
mbed_official 85:e1a8e879a6a9 773 __I uint32_t RESERVED2[109];
mbed_official 85:e1a8e879a6a9 774 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 775 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 776 __I uint32_t RESERVED3[13];
mbed_official 85:e1a8e879a6a9 777 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
mbed_official 85:e1a8e879a6a9 778 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
mbed_official 85:e1a8e879a6a9 779 the value of EVTEN. */
mbed_official 85:e1a8e879a6a9 780 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
mbed_official 85:e1a8e879a6a9 781 gives the value of EVTEN. */
mbed_official 85:e1a8e879a6a9 782 __I uint32_t RESERVED4[110];
mbed_official 501:36015dec7d16 783 __I uint32_t COUNTER; /*!< Current COUNTER value. */
mbed_official 85:e1a8e879a6a9 784 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
mbed_official 85:e1a8e879a6a9 785 Must be written when RTC is STOPed. */
mbed_official 85:e1a8e879a6a9 786 __I uint32_t RESERVED5[13];
mbed_official 85:e1a8e879a6a9 787 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
mbed_official 85:e1a8e879a6a9 788 __I uint32_t RESERVED6[683];
mbed_official 85:e1a8e879a6a9 789 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 790 } NRF_RTC_Type;
mbed_official 85:e1a8e879a6a9 791
mbed_official 85:e1a8e879a6a9 792
mbed_official 85:e1a8e879a6a9 793 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 794 /* ================ TEMP ================ */
mbed_official 85:e1a8e879a6a9 795 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 796
mbed_official 85:e1a8e879a6a9 797
mbed_official 85:e1a8e879a6a9 798 /**
mbed_official 85:e1a8e879a6a9 799 * @brief Temperature Sensor. (TEMP)
mbed_official 85:e1a8e879a6a9 800 */
mbed_official 85:e1a8e879a6a9 801
mbed_official 85:e1a8e879a6a9 802 typedef struct { /*!< TEMP Structure */
mbed_official 85:e1a8e879a6a9 803 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
mbed_official 85:e1a8e879a6a9 804 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
mbed_official 85:e1a8e879a6a9 805 __I uint32_t RESERVED0[62];
mbed_official 85:e1a8e879a6a9 806 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
mbed_official 85:e1a8e879a6a9 807 __I uint32_t RESERVED1[128];
mbed_official 85:e1a8e879a6a9 808 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 809 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 810 __I uint32_t RESERVED2[127];
mbed_official 85:e1a8e879a6a9 811 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
mbed_official 85:e1a8e879a6a9 812 __I uint32_t RESERVED3[700];
mbed_official 85:e1a8e879a6a9 813 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 814 } NRF_TEMP_Type;
mbed_official 85:e1a8e879a6a9 815
mbed_official 85:e1a8e879a6a9 816
mbed_official 85:e1a8e879a6a9 817 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 818 /* ================ RNG ================ */
mbed_official 85:e1a8e879a6a9 819 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 820
mbed_official 85:e1a8e879a6a9 821
mbed_official 85:e1a8e879a6a9 822 /**
mbed_official 85:e1a8e879a6a9 823 * @brief Random Number Generator. (RNG)
mbed_official 85:e1a8e879a6a9 824 */
mbed_official 85:e1a8e879a6a9 825
mbed_official 85:e1a8e879a6a9 826 typedef struct { /*!< RNG Structure */
mbed_official 85:e1a8e879a6a9 827 __O uint32_t TASKS_START; /*!< Start the random number generator. */
mbed_official 85:e1a8e879a6a9 828 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
mbed_official 85:e1a8e879a6a9 829 __I uint32_t RESERVED0[62];
mbed_official 85:e1a8e879a6a9 830 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
mbed_official 85:e1a8e879a6a9 831 __I uint32_t RESERVED1[63];
mbed_official 501:36015dec7d16 832 __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
mbed_official 85:e1a8e879a6a9 833 __I uint32_t RESERVED2[64];
mbed_official 85:e1a8e879a6a9 834 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
mbed_official 85:e1a8e879a6a9 835 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
mbed_official 85:e1a8e879a6a9 836 __I uint32_t RESERVED3[126];
mbed_official 85:e1a8e879a6a9 837 __IO uint32_t CONFIG; /*!< Configuration register. */
mbed_official 85:e1a8e879a6a9 838 __I uint32_t VALUE; /*!< RNG random number. */
mbed_official 85:e1a8e879a6a9 839 __I uint32_t RESERVED4[700];
mbed_official 85:e1a8e879a6a9 840 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 841 } NRF_RNG_Type;
mbed_official 85:e1a8e879a6a9 842
mbed_official 85:e1a8e879a6a9 843
mbed_official 85:e1a8e879a6a9 844 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 845 /* ================ ECB ================ */
mbed_official 85:e1a8e879a6a9 846 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 847
mbed_official 85:e1a8e879a6a9 848
mbed_official 85:e1a8e879a6a9 849 /**
mbed_official 85:e1a8e879a6a9 850 * @brief AES ECB Mode Encryption. (ECB)
mbed_official 85:e1a8e879a6a9 851 */
mbed_official 85:e1a8e879a6a9 852
mbed_official 85:e1a8e879a6a9 853 typedef struct { /*!< ECB Structure */
mbed_official 85:e1a8e879a6a9 854 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
mbed_official 85:e1a8e879a6a9 855 will not initiate a new encryption and the ERRORECB event will
mbed_official 85:e1a8e879a6a9 856 be triggered. */
mbed_official 85:e1a8e879a6a9 857 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
mbed_official 85:e1a8e879a6a9 858 this will will trigger the ERRORECB event. */
mbed_official 85:e1a8e879a6a9 859 __I uint32_t RESERVED0[62];
mbed_official 85:e1a8e879a6a9 860 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
mbed_official 85:e1a8e879a6a9 861 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
mbed_official 85:e1a8e879a6a9 862 error. */
mbed_official 85:e1a8e879a6a9 863 __I uint32_t RESERVED1[127];
mbed_official 85:e1a8e879a6a9 864 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 865 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 866 __I uint32_t RESERVED2[126];
mbed_official 85:e1a8e879a6a9 867 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
mbed_official 85:e1a8e879a6a9 868 __I uint32_t RESERVED3[701];
mbed_official 85:e1a8e879a6a9 869 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 870 } NRF_ECB_Type;
mbed_official 85:e1a8e879a6a9 871
mbed_official 85:e1a8e879a6a9 872
mbed_official 85:e1a8e879a6a9 873 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 874 /* ================ AAR ================ */
mbed_official 85:e1a8e879a6a9 875 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 876
mbed_official 85:e1a8e879a6a9 877
mbed_official 85:e1a8e879a6a9 878 /**
mbed_official 85:e1a8e879a6a9 879 * @brief Accelerated Address Resolver. (AAR)
mbed_official 85:e1a8e879a6a9 880 */
mbed_official 85:e1a8e879a6a9 881
mbed_official 85:e1a8e879a6a9 882 typedef struct { /*!< AAR Structure */
mbed_official 85:e1a8e879a6a9 883 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
mbed_official 85:e1a8e879a6a9 884 data structure. */
mbed_official 85:e1a8e879a6a9 885 __I uint32_t RESERVED0;
mbed_official 85:e1a8e879a6a9 886 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
mbed_official 85:e1a8e879a6a9 887 __I uint32_t RESERVED1[61];
mbed_official 85:e1a8e879a6a9 888 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
mbed_official 85:e1a8e879a6a9 889 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
mbed_official 85:e1a8e879a6a9 890 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
mbed_official 85:e1a8e879a6a9 891 __I uint32_t RESERVED2[126];
mbed_official 85:e1a8e879a6a9 892 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 893 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 894 __I uint32_t RESERVED3[61];
mbed_official 85:e1a8e879a6a9 895 __I uint32_t STATUS; /*!< Resolution status. */
mbed_official 85:e1a8e879a6a9 896 __I uint32_t RESERVED4[63];
mbed_official 85:e1a8e879a6a9 897 __IO uint32_t ENABLE; /*!< Enable AAR. */
mbed_official 85:e1a8e879a6a9 898 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
mbed_official 85:e1a8e879a6a9 899 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
mbed_official 85:e1a8e879a6a9 900 __I uint32_t RESERVED5;
mbed_official 85:e1a8e879a6a9 901 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
mbed_official 501:36015dec7d16 902 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
mbed_official 501:36015dec7d16 903 during resolution. A minimum of 3 bytes must be reserved. */
mbed_official 85:e1a8e879a6a9 904 __I uint32_t RESERVED6[697];
mbed_official 85:e1a8e879a6a9 905 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 906 } NRF_AAR_Type;
mbed_official 85:e1a8e879a6a9 907
mbed_official 85:e1a8e879a6a9 908
mbed_official 85:e1a8e879a6a9 909 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 910 /* ================ CCM ================ */
mbed_official 85:e1a8e879a6a9 911 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 912
mbed_official 85:e1a8e879a6a9 913
mbed_official 85:e1a8e879a6a9 914 /**
mbed_official 85:e1a8e879a6a9 915 * @brief AES CCM Mode Encryption. (CCM)
mbed_official 85:e1a8e879a6a9 916 */
mbed_official 85:e1a8e879a6a9 917
mbed_official 85:e1a8e879a6a9 918 typedef struct { /*!< CCM Structure */
mbed_official 85:e1a8e879a6a9 919 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
mbed_official 85:e1a8e879a6a9 920 itself when completed. */
mbed_official 85:e1a8e879a6a9 921 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
mbed_official 85:e1a8e879a6a9 922 completed. */
mbed_official 85:e1a8e879a6a9 923 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
mbed_official 85:e1a8e879a6a9 924 __I uint32_t RESERVED0[61];
mbed_official 85:e1a8e879a6a9 925 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
mbed_official 85:e1a8e879a6a9 926 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
mbed_official 85:e1a8e879a6a9 927 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
mbed_official 85:e1a8e879a6a9 928 __I uint32_t RESERVED1[61];
mbed_official 501:36015dec7d16 929 __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
mbed_official 85:e1a8e879a6a9 930 __I uint32_t RESERVED2[64];
mbed_official 85:e1a8e879a6a9 931 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 932 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 933 __I uint32_t RESERVED3[61];
mbed_official 85:e1a8e879a6a9 934 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
mbed_official 85:e1a8e879a6a9 935 __I uint32_t RESERVED4[63];
mbed_official 85:e1a8e879a6a9 936 __IO uint32_t ENABLE; /*!< CCM enable. */
mbed_official 85:e1a8e879a6a9 937 __IO uint32_t MODE; /*!< Operation mode. */
mbed_official 501:36015dec7d16 938 __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
mbed_official 501:36015dec7d16 939 __IO uint32_t INPTR; /*!< Pointer to the input packet. */
mbed_official 501:36015dec7d16 940 __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
mbed_official 501:36015dec7d16 941 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
mbed_official 501:36015dec7d16 942 during resolution. A minimum of 43 bytes must be reserved. */
mbed_official 85:e1a8e879a6a9 943 __I uint32_t RESERVED5[697];
mbed_official 85:e1a8e879a6a9 944 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 945 } NRF_CCM_Type;
mbed_official 85:e1a8e879a6a9 946
mbed_official 85:e1a8e879a6a9 947
mbed_official 85:e1a8e879a6a9 948 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 949 /* ================ WDT ================ */
mbed_official 85:e1a8e879a6a9 950 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 951
mbed_official 85:e1a8e879a6a9 952
mbed_official 85:e1a8e879a6a9 953 /**
mbed_official 85:e1a8e879a6a9 954 * @brief Watchdog Timer. (WDT)
mbed_official 85:e1a8e879a6a9 955 */
mbed_official 85:e1a8e879a6a9 956
mbed_official 85:e1a8e879a6a9 957 typedef struct { /*!< WDT Structure */
mbed_official 85:e1a8e879a6a9 958 __O uint32_t TASKS_START; /*!< Start the watchdog. */
mbed_official 85:e1a8e879a6a9 959 __I uint32_t RESERVED0[63];
mbed_official 85:e1a8e879a6a9 960 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
mbed_official 85:e1a8e879a6a9 961 __I uint32_t RESERVED1[128];
mbed_official 85:e1a8e879a6a9 962 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 963 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 964 __I uint32_t RESERVED2[61];
mbed_official 85:e1a8e879a6a9 965 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
mbed_official 85:e1a8e879a6a9 966 __I uint32_t REQSTATUS; /*!< Request status. */
mbed_official 85:e1a8e879a6a9 967 __I uint32_t RESERVED3[63];
mbed_official 85:e1a8e879a6a9 968 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
mbed_official 85:e1a8e879a6a9 969 __IO uint32_t RREN; /*!< Reload request enable. */
mbed_official 85:e1a8e879a6a9 970 __IO uint32_t CONFIG; /*!< Configuration register. */
mbed_official 85:e1a8e879a6a9 971 __I uint32_t RESERVED4[60];
mbed_official 85:e1a8e879a6a9 972 __O uint32_t RR[8]; /*!< Reload requests registers. */
mbed_official 85:e1a8e879a6a9 973 __I uint32_t RESERVED5[631];
mbed_official 85:e1a8e879a6a9 974 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 975 } NRF_WDT_Type;
mbed_official 85:e1a8e879a6a9 976
mbed_official 85:e1a8e879a6a9 977
mbed_official 85:e1a8e879a6a9 978 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 979 /* ================ QDEC ================ */
mbed_official 85:e1a8e879a6a9 980 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 981
mbed_official 85:e1a8e879a6a9 982
mbed_official 85:e1a8e879a6a9 983 /**
mbed_official 85:e1a8e879a6a9 984 * @brief Rotary decoder. (QDEC)
mbed_official 85:e1a8e879a6a9 985 */
mbed_official 85:e1a8e879a6a9 986
mbed_official 85:e1a8e879a6a9 987 typedef struct { /*!< QDEC Structure */
mbed_official 85:e1a8e879a6a9 988 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
mbed_official 85:e1a8e879a6a9 989 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
mbed_official 85:e1a8e879a6a9 990 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
mbed_official 85:e1a8e879a6a9 991 and clears the ACC registers. */
mbed_official 85:e1a8e879a6a9 992 __I uint32_t RESERVED0[61];
mbed_official 85:e1a8e879a6a9 993 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
mbed_official 85:e1a8e879a6a9 994 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
mbed_official 85:e1a8e879a6a9 995 ACC register different than zero. */
mbed_official 85:e1a8e879a6a9 996 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
mbed_official 85:e1a8e879a6a9 997 __I uint32_t RESERVED1[61];
mbed_official 501:36015dec7d16 998 __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
mbed_official 85:e1a8e879a6a9 999 __I uint32_t RESERVED2[64];
mbed_official 85:e1a8e879a6a9 1000 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 1001 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 1002 __I uint32_t RESERVED3[125];
mbed_official 85:e1a8e879a6a9 1003 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
mbed_official 85:e1a8e879a6a9 1004 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
mbed_official 85:e1a8e879a6a9 1005 __IO uint32_t SAMPLEPER; /*!< Sample period. */
mbed_official 85:e1a8e879a6a9 1006 __I int32_t SAMPLE; /*!< Motion sample value. */
mbed_official 85:e1a8e879a6a9 1007 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
mbed_official 85:e1a8e879a6a9 1008 __I int32_t ACC; /*!< Accumulated valid transitions register. */
mbed_official 85:e1a8e879a6a9 1009 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
mbed_official 85:e1a8e879a6a9 1010 task. */
mbed_official 85:e1a8e879a6a9 1011 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
mbed_official 85:e1a8e879a6a9 1012 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
mbed_official 85:e1a8e879a6a9 1013 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
mbed_official 85:e1a8e879a6a9 1014 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
mbed_official 85:e1a8e879a6a9 1015 __I uint32_t RESERVED4[5];
mbed_official 85:e1a8e879a6a9 1016 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
mbed_official 85:e1a8e879a6a9 1017 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
mbed_official 85:e1a8e879a6a9 1018 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
mbed_official 85:e1a8e879a6a9 1019 task. */
mbed_official 85:e1a8e879a6a9 1020 __I uint32_t RESERVED5[684];
mbed_official 85:e1a8e879a6a9 1021 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 1022 } NRF_QDEC_Type;
mbed_official 85:e1a8e879a6a9 1023
mbed_official 85:e1a8e879a6a9 1024
mbed_official 85:e1a8e879a6a9 1025 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1026 /* ================ LPCOMP ================ */
mbed_official 85:e1a8e879a6a9 1027 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1028
mbed_official 85:e1a8e879a6a9 1029
mbed_official 85:e1a8e879a6a9 1030 /**
mbed_official 501:36015dec7d16 1031 * @brief Low power comparator. (LPCOMP)
mbed_official 85:e1a8e879a6a9 1032 */
mbed_official 85:e1a8e879a6a9 1033
mbed_official 85:e1a8e879a6a9 1034 typedef struct { /*!< LPCOMP Structure */
mbed_official 85:e1a8e879a6a9 1035 __O uint32_t TASKS_START; /*!< Start the comparator. */
mbed_official 85:e1a8e879a6a9 1036 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
mbed_official 85:e1a8e879a6a9 1037 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
mbed_official 85:e1a8e879a6a9 1038 __I uint32_t RESERVED0[61];
mbed_official 85:e1a8e879a6a9 1039 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
mbed_official 85:e1a8e879a6a9 1040 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
mbed_official 85:e1a8e879a6a9 1041 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
mbed_official 85:e1a8e879a6a9 1042 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
mbed_official 85:e1a8e879a6a9 1043 __I uint32_t RESERVED1[60];
mbed_official 501:36015dec7d16 1044 __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
mbed_official 85:e1a8e879a6a9 1045 __I uint32_t RESERVED2[64];
mbed_official 85:e1a8e879a6a9 1046 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
mbed_official 85:e1a8e879a6a9 1047 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
mbed_official 85:e1a8e879a6a9 1048 __I uint32_t RESERVED3[61];
mbed_official 85:e1a8e879a6a9 1049 __I uint32_t RESULT; /*!< Result of last compare. */
mbed_official 85:e1a8e879a6a9 1050 __I uint32_t RESERVED4[63];
mbed_official 85:e1a8e879a6a9 1051 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
mbed_official 85:e1a8e879a6a9 1052 __IO uint32_t PSEL; /*!< Input pin select. */
mbed_official 85:e1a8e879a6a9 1053 __IO uint32_t REFSEL; /*!< Reference select. */
mbed_official 85:e1a8e879a6a9 1054 __IO uint32_t EXTREFSEL; /*!< External reference select. */
mbed_official 85:e1a8e879a6a9 1055 __I uint32_t RESERVED5[4];
mbed_official 85:e1a8e879a6a9 1056 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
mbed_official 85:e1a8e879a6a9 1057 __I uint32_t RESERVED6[694];
mbed_official 85:e1a8e879a6a9 1058 __IO uint32_t POWER; /*!< Peripheral power control. */
mbed_official 85:e1a8e879a6a9 1059 } NRF_LPCOMP_Type;
mbed_official 85:e1a8e879a6a9 1060
mbed_official 85:e1a8e879a6a9 1061
mbed_official 85:e1a8e879a6a9 1062 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1063 /* ================ SWI ================ */
mbed_official 85:e1a8e879a6a9 1064 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1065
mbed_official 85:e1a8e879a6a9 1066
mbed_official 85:e1a8e879a6a9 1067 /**
mbed_official 85:e1a8e879a6a9 1068 * @brief SW Interrupts. (SWI)
mbed_official 85:e1a8e879a6a9 1069 */
mbed_official 85:e1a8e879a6a9 1070
mbed_official 85:e1a8e879a6a9 1071 typedef struct { /*!< SWI Structure */
mbed_official 85:e1a8e879a6a9 1072 __I uint32_t UNUSED; /*!< Unused. */
mbed_official 85:e1a8e879a6a9 1073 } NRF_SWI_Type;
mbed_official 85:e1a8e879a6a9 1074
mbed_official 85:e1a8e879a6a9 1075
mbed_official 85:e1a8e879a6a9 1076 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1077 /* ================ NVMC ================ */
mbed_official 85:e1a8e879a6a9 1078 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1079
mbed_official 85:e1a8e879a6a9 1080
mbed_official 85:e1a8e879a6a9 1081 /**
mbed_official 85:e1a8e879a6a9 1082 * @brief Non Volatile Memory Controller. (NVMC)
mbed_official 85:e1a8e879a6a9 1083 */
mbed_official 85:e1a8e879a6a9 1084
mbed_official 85:e1a8e879a6a9 1085 typedef struct { /*!< NVMC Structure */
mbed_official 85:e1a8e879a6a9 1086 __I uint32_t RESERVED0[256];
mbed_official 85:e1a8e879a6a9 1087 __I uint32_t READY; /*!< Ready flag. */
mbed_official 85:e1a8e879a6a9 1088 __I uint32_t RESERVED1[64];
mbed_official 85:e1a8e879a6a9 1089 __IO uint32_t CONFIG; /*!< Configuration register. */
mbed_official 85:e1a8e879a6a9 1090 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
mbed_official 85:e1a8e879a6a9 1091 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
mbed_official 85:e1a8e879a6a9 1092 __IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
mbed_official 85:e1a8e879a6a9 1093 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
mbed_official 85:e1a8e879a6a9 1094 } NRF_NVMC_Type;
mbed_official 85:e1a8e879a6a9 1095
mbed_official 85:e1a8e879a6a9 1096
mbed_official 85:e1a8e879a6a9 1097 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1098 /* ================ PPI ================ */
mbed_official 85:e1a8e879a6a9 1099 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1100
mbed_official 85:e1a8e879a6a9 1101
mbed_official 85:e1a8e879a6a9 1102 /**
mbed_official 85:e1a8e879a6a9 1103 * @brief PPI controller. (PPI)
mbed_official 85:e1a8e879a6a9 1104 */
mbed_official 85:e1a8e879a6a9 1105
mbed_official 85:e1a8e879a6a9 1106 typedef struct { /*!< PPI Structure */
mbed_official 85:e1a8e879a6a9 1107 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
mbed_official 85:e1a8e879a6a9 1108 __I uint32_t RESERVED0[312];
mbed_official 85:e1a8e879a6a9 1109 __IO uint32_t CHEN; /*!< Channel enable. */
mbed_official 85:e1a8e879a6a9 1110 __IO uint32_t CHENSET; /*!< Channel enable set. */
mbed_official 85:e1a8e879a6a9 1111 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
mbed_official 85:e1a8e879a6a9 1112 __I uint32_t RESERVED1;
mbed_official 85:e1a8e879a6a9 1113 PPI_CH_Type CH[16]; /*!< PPI Channel. */
mbed_official 85:e1a8e879a6a9 1114 __I uint32_t RESERVED2[156];
mbed_official 85:e1a8e879a6a9 1115 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
mbed_official 85:e1a8e879a6a9 1116 } NRF_PPI_Type;
mbed_official 85:e1a8e879a6a9 1117
mbed_official 85:e1a8e879a6a9 1118
mbed_official 85:e1a8e879a6a9 1119 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1120 /* ================ FICR ================ */
mbed_official 85:e1a8e879a6a9 1121 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1122
mbed_official 85:e1a8e879a6a9 1123
mbed_official 85:e1a8e879a6a9 1124 /**
mbed_official 85:e1a8e879a6a9 1125 * @brief Factory Information Configuration. (FICR)
mbed_official 85:e1a8e879a6a9 1126 */
mbed_official 85:e1a8e879a6a9 1127
mbed_official 85:e1a8e879a6a9 1128 typedef struct { /*!< FICR Structure */
mbed_official 85:e1a8e879a6a9 1129 __I uint32_t RESERVED0[4];
mbed_official 85:e1a8e879a6a9 1130 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
mbed_official 85:e1a8e879a6a9 1131 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
mbed_official 85:e1a8e879a6a9 1132 __I uint32_t RESERVED1[4];
mbed_official 85:e1a8e879a6a9 1133 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
mbed_official 85:e1a8e879a6a9 1134 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
mbed_official 85:e1a8e879a6a9 1135 __I uint32_t RESERVED2;
mbed_official 85:e1a8e879a6a9 1136 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
mbed_official 501:36015dec7d16 1137
mbed_official 501:36015dec7d16 1138 union {
mbed_official 501:36015dec7d16 1139 __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
mbed_official 501:36015dec7d16 1140 kept for backward compatinility purposes. Use SIZERAMBLOCKS
mbed_official 501:36015dec7d16 1141 instead. */
mbed_official 501:36015dec7d16 1142 __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
mbed_official 501:36015dec7d16 1143 };
mbed_official 85:e1a8e879a6a9 1144 __I uint32_t RESERVED3[5];
mbed_official 85:e1a8e879a6a9 1145 __I uint32_t CONFIGID; /*!< Configuration identifier. */
mbed_official 85:e1a8e879a6a9 1146 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
mbed_official 85:e1a8e879a6a9 1147 __I uint32_t RESERVED4[6];
mbed_official 85:e1a8e879a6a9 1148 __I uint32_t ER[4]; /*!< Encryption root. */
mbed_official 85:e1a8e879a6a9 1149 __I uint32_t IR[4]; /*!< Identity root. */
mbed_official 85:e1a8e879a6a9 1150 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
mbed_official 85:e1a8e879a6a9 1151 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
mbed_official 85:e1a8e879a6a9 1152 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
mbed_official 501:36015dec7d16 1153 __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
mbed_official 501:36015dec7d16 1154 mode. */
mbed_official 501:36015dec7d16 1155 __I uint32_t RESERVED5[10];
mbed_official 85:e1a8e879a6a9 1156 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
mbed_official 85:e1a8e879a6a9 1157 mode. */
mbed_official 501:36015dec7d16 1158 FICR_INFO_Type INFO; /*!< Device info */
mbed_official 85:e1a8e879a6a9 1159 } NRF_FICR_Type;
mbed_official 85:e1a8e879a6a9 1160
mbed_official 85:e1a8e879a6a9 1161
mbed_official 85:e1a8e879a6a9 1162 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1163 /* ================ UICR ================ */
mbed_official 85:e1a8e879a6a9 1164 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1165
mbed_official 85:e1a8e879a6a9 1166
mbed_official 85:e1a8e879a6a9 1167 /**
mbed_official 85:e1a8e879a6a9 1168 * @brief User Information Configuration. (UICR)
mbed_official 85:e1a8e879a6a9 1169 */
mbed_official 85:e1a8e879a6a9 1170
mbed_official 85:e1a8e879a6a9 1171 typedef struct { /*!< UICR Structure */
mbed_official 85:e1a8e879a6a9 1172 __IO uint32_t CLENR0; /*!< Length of code region 0. */
mbed_official 85:e1a8e879a6a9 1173 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
mbed_official 85:e1a8e879a6a9 1174 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
mbed_official 85:e1a8e879a6a9 1175 __I uint32_t RESERVED0;
mbed_official 85:e1a8e879a6a9 1176 __I uint32_t FWID; /*!< Firmware ID. */
mbed_official 85:e1a8e879a6a9 1177 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
mbed_official 85:e1a8e879a6a9 1178 } NRF_UICR_Type;
mbed_official 85:e1a8e879a6a9 1179
mbed_official 85:e1a8e879a6a9 1180
mbed_official 85:e1a8e879a6a9 1181 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1182 /* ================ GPIO ================ */
mbed_official 85:e1a8e879a6a9 1183 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1184
mbed_official 85:e1a8e879a6a9 1185
mbed_official 85:e1a8e879a6a9 1186 /**
mbed_official 85:e1a8e879a6a9 1187 * @brief General purpose input and output. (GPIO)
mbed_official 85:e1a8e879a6a9 1188 */
mbed_official 85:e1a8e879a6a9 1189
mbed_official 85:e1a8e879a6a9 1190 typedef struct { /*!< GPIO Structure */
mbed_official 85:e1a8e879a6a9 1191 __I uint32_t RESERVED0[321];
mbed_official 85:e1a8e879a6a9 1192 __IO uint32_t OUT; /*!< Write GPIO port. */
mbed_official 85:e1a8e879a6a9 1193 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
mbed_official 85:e1a8e879a6a9 1194 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
mbed_official 85:e1a8e879a6a9 1195 __I uint32_t IN; /*!< Read GPIO port. */
mbed_official 85:e1a8e879a6a9 1196 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
mbed_official 85:e1a8e879a6a9 1197 __IO uint32_t DIRSET; /*!< DIR set register. */
mbed_official 85:e1a8e879a6a9 1198 __IO uint32_t DIRCLR; /*!< DIR clear register. */
mbed_official 85:e1a8e879a6a9 1199 __I uint32_t RESERVED1[120];
mbed_official 85:e1a8e879a6a9 1200 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
mbed_official 85:e1a8e879a6a9 1201 } NRF_GPIO_Type;
mbed_official 85:e1a8e879a6a9 1202
mbed_official 85:e1a8e879a6a9 1203
mbed_official 85:e1a8e879a6a9 1204 /* -------------------- End of section using anonymous unions ------------------- */
mbed_official 85:e1a8e879a6a9 1205 #if defined(__CC_ARM)
mbed_official 85:e1a8e879a6a9 1206 #pragma pop
mbed_official 85:e1a8e879a6a9 1207 #elif defined(__ICCARM__)
mbed_official 85:e1a8e879a6a9 1208 /* leave anonymous unions enabled */
mbed_official 85:e1a8e879a6a9 1209 #elif defined(__GNUC__)
mbed_official 85:e1a8e879a6a9 1210 /* anonymous unions are enabled by default */
mbed_official 85:e1a8e879a6a9 1211 #elif defined(__TMS470__)
mbed_official 85:e1a8e879a6a9 1212 /* anonymous unions are enabled by default */
mbed_official 85:e1a8e879a6a9 1213 #elif defined(__TASKING__)
mbed_official 85:e1a8e879a6a9 1214 #pragma warning restore
mbed_official 85:e1a8e879a6a9 1215 #else
mbed_official 85:e1a8e879a6a9 1216 #warning Not supported compiler type
mbed_official 85:e1a8e879a6a9 1217 #endif
mbed_official 85:e1a8e879a6a9 1218
mbed_official 85:e1a8e879a6a9 1219
mbed_official 85:e1a8e879a6a9 1220
mbed_official 85:e1a8e879a6a9 1221
mbed_official 85:e1a8e879a6a9 1222 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1223 /* ================ Peripheral memory map ================ */
mbed_official 85:e1a8e879a6a9 1224 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1225
mbed_official 85:e1a8e879a6a9 1226 #define NRF_POWER_BASE 0x40000000UL
mbed_official 85:e1a8e879a6a9 1227 #define NRF_CLOCK_BASE 0x40000000UL
mbed_official 85:e1a8e879a6a9 1228 #define NRF_MPU_BASE 0x40000000UL
mbed_official 85:e1a8e879a6a9 1229 #define NRF_PU_BASE 0x40000000UL
mbed_official 85:e1a8e879a6a9 1230 #define NRF_AMLI_BASE 0x40000000UL
mbed_official 85:e1a8e879a6a9 1231 #define NRF_RADIO_BASE 0x40001000UL
mbed_official 85:e1a8e879a6a9 1232 #define NRF_UART0_BASE 0x40002000UL
mbed_official 85:e1a8e879a6a9 1233 #define NRF_SPI0_BASE 0x40003000UL
mbed_official 85:e1a8e879a6a9 1234 #define NRF_TWI0_BASE 0x40003000UL
mbed_official 85:e1a8e879a6a9 1235 #define NRF_SPI1_BASE 0x40004000UL
mbed_official 85:e1a8e879a6a9 1236 #define NRF_TWI1_BASE 0x40004000UL
mbed_official 85:e1a8e879a6a9 1237 #define NRF_SPIS1_BASE 0x40004000UL
mbed_official 501:36015dec7d16 1238 #define NRF_SPIM1_BASE 0x40004000UL
mbed_official 85:e1a8e879a6a9 1239 #define NRF_GPIOTE_BASE 0x40006000UL
mbed_official 85:e1a8e879a6a9 1240 #define NRF_ADC_BASE 0x40007000UL
mbed_official 85:e1a8e879a6a9 1241 #define NRF_TIMER0_BASE 0x40008000UL
mbed_official 85:e1a8e879a6a9 1242 #define NRF_TIMER1_BASE 0x40009000UL
mbed_official 85:e1a8e879a6a9 1243 #define NRF_TIMER2_BASE 0x4000A000UL
mbed_official 85:e1a8e879a6a9 1244 #define NRF_RTC0_BASE 0x4000B000UL
mbed_official 85:e1a8e879a6a9 1245 #define NRF_TEMP_BASE 0x4000C000UL
mbed_official 85:e1a8e879a6a9 1246 #define NRF_RNG_BASE 0x4000D000UL
mbed_official 85:e1a8e879a6a9 1247 #define NRF_ECB_BASE 0x4000E000UL
mbed_official 85:e1a8e879a6a9 1248 #define NRF_AAR_BASE 0x4000F000UL
mbed_official 85:e1a8e879a6a9 1249 #define NRF_CCM_BASE 0x4000F000UL
mbed_official 85:e1a8e879a6a9 1250 #define NRF_WDT_BASE 0x40010000UL
mbed_official 85:e1a8e879a6a9 1251 #define NRF_RTC1_BASE 0x40011000UL
mbed_official 85:e1a8e879a6a9 1252 #define NRF_QDEC_BASE 0x40012000UL
mbed_official 85:e1a8e879a6a9 1253 #define NRF_LPCOMP_BASE 0x40013000UL
mbed_official 85:e1a8e879a6a9 1254 #define NRF_SWI_BASE 0x40014000UL
mbed_official 85:e1a8e879a6a9 1255 #define NRF_NVMC_BASE 0x4001E000UL
mbed_official 85:e1a8e879a6a9 1256 #define NRF_PPI_BASE 0x4001F000UL
mbed_official 85:e1a8e879a6a9 1257 #define NRF_FICR_BASE 0x10000000UL
mbed_official 85:e1a8e879a6a9 1258 #define NRF_UICR_BASE 0x10001000UL
mbed_official 85:e1a8e879a6a9 1259 #define NRF_GPIO_BASE 0x50000000UL
mbed_official 85:e1a8e879a6a9 1260
mbed_official 85:e1a8e879a6a9 1261
mbed_official 85:e1a8e879a6a9 1262 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1263 /* ================ Peripheral declaration ================ */
mbed_official 85:e1a8e879a6a9 1264 /* ================================================================================ */
mbed_official 85:e1a8e879a6a9 1265
mbed_official 85:e1a8e879a6a9 1266 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
mbed_official 85:e1a8e879a6a9 1267 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
mbed_official 85:e1a8e879a6a9 1268 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
mbed_official 85:e1a8e879a6a9 1269 #define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
mbed_official 85:e1a8e879a6a9 1270 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
mbed_official 85:e1a8e879a6a9 1271 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
mbed_official 85:e1a8e879a6a9 1272 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
mbed_official 85:e1a8e879a6a9 1273 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
mbed_official 85:e1a8e879a6a9 1274 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
mbed_official 85:e1a8e879a6a9 1275 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
mbed_official 85:e1a8e879a6a9 1276 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
mbed_official 85:e1a8e879a6a9 1277 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
mbed_official 501:36015dec7d16 1278 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
mbed_official 85:e1a8e879a6a9 1279 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
mbed_official 85:e1a8e879a6a9 1280 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
mbed_official 85:e1a8e879a6a9 1281 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
mbed_official 85:e1a8e879a6a9 1282 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
mbed_official 85:e1a8e879a6a9 1283 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
mbed_official 85:e1a8e879a6a9 1284 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
mbed_official 85:e1a8e879a6a9 1285 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
mbed_official 85:e1a8e879a6a9 1286 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
mbed_official 85:e1a8e879a6a9 1287 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
mbed_official 85:e1a8e879a6a9 1288 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
mbed_official 85:e1a8e879a6a9 1289 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
mbed_official 85:e1a8e879a6a9 1290 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
mbed_official 85:e1a8e879a6a9 1291 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
mbed_official 85:e1a8e879a6a9 1292 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
mbed_official 85:e1a8e879a6a9 1293 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
mbed_official 85:e1a8e879a6a9 1294 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
mbed_official 85:e1a8e879a6a9 1295 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
mbed_official 85:e1a8e879a6a9 1296 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
mbed_official 85:e1a8e879a6a9 1297 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
mbed_official 85:e1a8e879a6a9 1298 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
mbed_official 85:e1a8e879a6a9 1299 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
mbed_official 85:e1a8e879a6a9 1300
mbed_official 85:e1a8e879a6a9 1301
mbed_official 85:e1a8e879a6a9 1302 /** @} */ /* End of group Device_Peripheral_Registers */
mbed_official 85:e1a8e879a6a9 1303 /** @} */ /* End of group nRF51 */
mbed_official 85:e1a8e879a6a9 1304 /** @} */ /* End of group Nordic Semiconductor */
mbed_official 85:e1a8e879a6a9 1305
mbed_official 85:e1a8e879a6a9 1306 #ifdef __cplusplus
mbed_official 85:e1a8e879a6a9 1307 }
mbed_official 85:e1a8e879a6a9 1308 #endif
mbed_official 85:e1a8e879a6a9 1309
mbed_official 85:e1a8e879a6a9 1310
mbed_official 85:e1a8e879a6a9 1311 #endif /* nRF51_H */
mbed_official 501:36015dec7d16 1312