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targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51.h@433:73d4f6083dd2, 2014-12-10 (annotated)

Committer:: mbed_official
Date:: Wed Dec 10 08:15:06 2014 +0000
Revision:: 433:73d4f6083dd2
Parent:: 270:e2babe29baf8
Child:: 501:36015dec7d16

Synchronized with git revision 87c17ed748337226aaa7b4a335fb700e7af21c96

Full URL: https://github.com/mbedmicro/mbed/commit/87c17ed748337226aaa7b4a335fb700e7af21c96/

Targets: NRF51822 - With the old logic if Serial::writeable() was called before and/or used ...

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	104:a6a92e2e5a92	1	/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
mbed_official	85:e1a8e879a6a9	2	*
mbed_official	104:a6a92e2e5a92	3	* The information contained herein is property of Nordic Semiconductor ASA.
mbed_official	104:a6a92e2e5a92	4	* Terms and conditions of usage are described in detail in NORDIC
mbed_official	104:a6a92e2e5a92	5	* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
mbed_official	85:e1a8e879a6a9	6	*
mbed_official	104:a6a92e2e5a92	7	* Licensees are granted free, non-transferable use of the information. NO
mbed_official	104:a6a92e2e5a92	8	* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
mbed_official	104:a6a92e2e5a92	9	* the file.
mbed_official	104:a6a92e2e5a92	10	*
mbed_official	85:e1a8e879a6a9	11	*/
mbed_official	85:e1a8e879a6a9	12
mbed_official	85:e1a8e879a6a9	13
mbed_official	85:e1a8e879a6a9	14
mbed_official	85:e1a8e879a6a9	15	/** @addtogroup Nordic Semiconductor
mbed_official	85:e1a8e879a6a9	16	* @{
mbed_official	85:e1a8e879a6a9	17	*/
mbed_official	85:e1a8e879a6a9	18
mbed_official	85:e1a8e879a6a9	19	/** @addtogroup nRF51
mbed_official	85:e1a8e879a6a9	20	* @{
mbed_official	85:e1a8e879a6a9	21	*/
mbed_official	85:e1a8e879a6a9	22
mbed_official	85:e1a8e879a6a9	23	#ifndef NRF51_H
mbed_official	85:e1a8e879a6a9	24	#define NRF51_H
mbed_official	85:e1a8e879a6a9	25
mbed_official	85:e1a8e879a6a9	26	#ifdef __cplusplus
mbed_official	85:e1a8e879a6a9	27	extern "C" {
mbed_official	85:e1a8e879a6a9	28	#endif
mbed_official	85:e1a8e879a6a9	29
mbed_official	85:e1a8e879a6a9	30
mbed_official	85:e1a8e879a6a9	31	/* ------------------------- Interrupt Number Definition ------------------------ */
mbed_official	85:e1a8e879a6a9	32
mbed_official	85:e1a8e879a6a9	33	typedef enum {
mbed_official	85:e1a8e879a6a9	34	/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
mbed_official	85:e1a8e879a6a9	35	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
mbed_official	85:e1a8e879a6a9	36	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
mbed_official	85:e1a8e879a6a9	37	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
mbed_official	85:e1a8e879a6a9	38	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
mbed_official	85:e1a8e879a6a9	39	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
mbed_official	85:e1a8e879a6a9	40	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
mbed_official	85:e1a8e879a6a9	41	SysTick_IRQn = -1, /!< 15 System Tick Timer /
mbed_official	85:e1a8e879a6a9	42	/* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
mbed_official	85:e1a8e879a6a9	43	POWER_CLOCK_IRQn = 0, /!< 0 POWER_CLOCK /
mbed_official	85:e1a8e879a6a9	44	RADIO_IRQn = 1, /!< 1 RADIO /
mbed_official	85:e1a8e879a6a9	45	UART0_IRQn = 2, /!< 2 UART0 /
mbed_official	85:e1a8e879a6a9	46	SPI0_TWI0_IRQn = 3, /!< 3 SPI0_TWI0 /
mbed_official	85:e1a8e879a6a9	47	SPI1_TWI1_IRQn = 4, /!< 4 SPI1_TWI1 /
mbed_official	85:e1a8e879a6a9	48	GPIOTE_IRQn = 6, /!< 6 GPIOTE /
mbed_official	85:e1a8e879a6a9	49	ADC_IRQn = 7, /!< 7 ADC /
mbed_official	85:e1a8e879a6a9	50	TIMER0_IRQn = 8, /!< 8 TIMER0 /
mbed_official	85:e1a8e879a6a9	51	TIMER1_IRQn = 9, /!< 9 TIMER1 /
mbed_official	85:e1a8e879a6a9	52	TIMER2_IRQn = 10, /!< 10 TIMER2 /
mbed_official	85:e1a8e879a6a9	53	RTC0_IRQn = 11, /!< 11 RTC0 /
mbed_official	85:e1a8e879a6a9	54	TEMP_IRQn = 12, /!< 12 TEMP /
mbed_official	85:e1a8e879a6a9	55	RNG_IRQn = 13, /!< 13 RNG /
mbed_official	85:e1a8e879a6a9	56	ECB_IRQn = 14, /!< 14 ECB /
mbed_official	85:e1a8e879a6a9	57	CCM_AAR_IRQn = 15, /!< 15 CCM_AAR /
mbed_official	85:e1a8e879a6a9	58	WDT_IRQn = 16, /!< 16 WDT /
mbed_official	85:e1a8e879a6a9	59	RTC1_IRQn = 17, /!< 17 RTC1 /
mbed_official	85:e1a8e879a6a9	60	QDEC_IRQn = 18, /!< 18 QDEC /
mbed_official	85:e1a8e879a6a9	61	LPCOMP_COMP_IRQn = 19, /!< 19 LPCOMP_COMP /
mbed_official	85:e1a8e879a6a9	62	SWI0_IRQn = 20, /!< 20 SWI0 /
mbed_official	85:e1a8e879a6a9	63	SWI1_IRQn = 21, /!< 21 SWI1 /
mbed_official	85:e1a8e879a6a9	64	SWI2_IRQn = 22, /!< 22 SWI2 /
mbed_official	85:e1a8e879a6a9	65	SWI3_IRQn = 23, /!< 23 SWI3 /
mbed_official	85:e1a8e879a6a9	66	SWI4_IRQn = 24, /!< 24 SWI4 /
mbed_official	85:e1a8e879a6a9	67	SWI5_IRQn = 25 /!< 25 SWI5 /
mbed_official	85:e1a8e879a6a9	68	} IRQn_Type;
mbed_official	85:e1a8e879a6a9	69
mbed_official	85:e1a8e879a6a9	70
mbed_official	85:e1a8e879a6a9	71	/** @addtogroup Configuration_of_CMSIS
mbed_official	85:e1a8e879a6a9	72	* @{
mbed_official	85:e1a8e879a6a9	73	*/
mbed_official	85:e1a8e879a6a9	74
mbed_official	85:e1a8e879a6a9	75
mbed_official	85:e1a8e879a6a9	76	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	77	/* ================ Processor and Core Peripheral Section ================ */
mbed_official	85:e1a8e879a6a9	78	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	79
mbed_official	85:e1a8e879a6a9	80	/* ----------------Configuration of the cm0 Processor and Core Peripherals---------------- */
mbed_official	85:e1a8e879a6a9	81	#define __CM0_REV 0x0301 /!< Cortex-M0 Core Revision /
mbed_official	85:e1a8e879a6a9	82	#define __MPU_PRESENT 0 /!< MPU present or not /
mbed_official	85:e1a8e879a6a9	83	#define __NVIC_PRIO_BITS 2 /!< Number of Bits used for Priority Levels /
mbed_official	85:e1a8e879a6a9	84	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
mbed_official	85:e1a8e879a6a9	85	/** @} / / End of group Configuration_of_CMSIS */
mbed_official	85:e1a8e879a6a9	86
mbed_official	85:e1a8e879a6a9	87	#include <core_cm0.h> /!< Cortex-M0 processor and core peripherals /
mbed_official	85:e1a8e879a6a9	88	#include "system_nrf51822.h" /!< nRF51 System /
mbed_official	85:e1a8e879a6a9	89
mbed_official	85:e1a8e879a6a9	90
mbed_official	85:e1a8e879a6a9	91	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	92	/* ================ Device Specific Peripheral Section ================ */
mbed_official	85:e1a8e879a6a9	93	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	94
mbed_official	85:e1a8e879a6a9	95
mbed_official	85:e1a8e879a6a9	96	/** @addtogroup Device_Peripheral_Registers
mbed_official	85:e1a8e879a6a9	97	* @{
mbed_official	85:e1a8e879a6a9	98	*/
mbed_official	85:e1a8e879a6a9	99
mbed_official	85:e1a8e879a6a9	100
mbed_official	85:e1a8e879a6a9	101	/* ------------------- Start of section using anonymous unions ------------------ */
mbed_official	85:e1a8e879a6a9	102	#if defined(__CC_ARM)
mbed_official	85:e1a8e879a6a9	103	#pragma push
mbed_official	85:e1a8e879a6a9	104	#pragma anon_unions
mbed_official	85:e1a8e879a6a9	105	#elif defined(__ICCARM__)
mbed_official	85:e1a8e879a6a9	106	#pragma language=extended
mbed_official	85:e1a8e879a6a9	107	#elif defined(__GNUC__)
mbed_official	85:e1a8e879a6a9	108	/* anonymous unions are enabled by default */
mbed_official	85:e1a8e879a6a9	109	#elif defined(__TMS470__)
mbed_official	85:e1a8e879a6a9	110	/* anonymous unions are enabled by default */
mbed_official	85:e1a8e879a6a9	111	#elif defined(__TASKING__)
mbed_official	85:e1a8e879a6a9	112	#pragma warning 586
mbed_official	85:e1a8e879a6a9	113	#else
mbed_official	85:e1a8e879a6a9	114	#warning Not supported compiler type
mbed_official	85:e1a8e879a6a9	115	#endif
mbed_official	85:e1a8e879a6a9	116
mbed_official	85:e1a8e879a6a9	117
mbed_official	85:e1a8e879a6a9	118	typedef struct {
mbed_official	85:e1a8e879a6a9	119	__IO uint32_t CPU0; /!< Configurable priority configuration register for CPU0. /
mbed_official	85:e1a8e879a6a9	120	__IO uint32_t SPIS1; /!< Configurable priority configuration register for SPIS1. /
mbed_official	85:e1a8e879a6a9	121	__IO uint32_t RADIO; /!< Configurable priority configuration register for RADIO. /
mbed_official	85:e1a8e879a6a9	122	__IO uint32_t ECB; /!< Configurable priority configuration register for ECB. /
mbed_official	85:e1a8e879a6a9	123	__IO uint32_t CCM; /!< Configurable priority configuration register for CCM. /
mbed_official	85:e1a8e879a6a9	124	__IO uint32_t AAR; /!< Configurable priority configuration register for AAR. /
mbed_official	85:e1a8e879a6a9	125	} AMLI_RAMPRI_Type;
mbed_official	85:e1a8e879a6a9	126
mbed_official	85:e1a8e879a6a9	127	typedef struct {
mbed_official	85:e1a8e879a6a9	128	__O uint32_t EN; /!< Enable channel group. /
mbed_official	85:e1a8e879a6a9	129	__O uint32_t DIS; /!< Disable channel group. /
mbed_official	85:e1a8e879a6a9	130	} PPI_TASKS_CHG_Type;
mbed_official	85:e1a8e879a6a9	131
mbed_official	85:e1a8e879a6a9	132	typedef struct {
mbed_official	85:e1a8e879a6a9	133	__IO uint32_t EEP; /!< Channel event end-point. /
mbed_official	85:e1a8e879a6a9	134	__IO uint32_t TEP; /!< Channel task end-point. /
mbed_official	85:e1a8e879a6a9	135	} PPI_CH_Type;
mbed_official	85:e1a8e879a6a9	136
mbed_official	85:e1a8e879a6a9	137
mbed_official	85:e1a8e879a6a9	138	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	139	/* ================ POWER ================ */
mbed_official	85:e1a8e879a6a9	140	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	141
mbed_official	85:e1a8e879a6a9	142
mbed_official	85:e1a8e879a6a9	143	/**
mbed_official	85:e1a8e879a6a9	144	* @brief Power Control. (POWER)
mbed_official	85:e1a8e879a6a9	145	*/
mbed_official	85:e1a8e879a6a9	146
mbed_official	85:e1a8e879a6a9	147	typedef struct { /!< POWER Structure /
mbed_official	85:e1a8e879a6a9	148	__I uint32_t RESERVED0[30];
mbed_official	85:e1a8e879a6a9	149	__O uint32_t TASKS_CONSTLAT; /!< Enable constant latency mode. /
mbed_official	85:e1a8e879a6a9	150	__O uint32_t TASKS_LOWPWR; /!< Enable low power mode (variable latency). /
mbed_official	85:e1a8e879a6a9	151	__I uint32_t RESERVED1[34];
mbed_official	85:e1a8e879a6a9	152	__IO uint32_t EVENTS_POFWARN; /!< Power failure warning. /
mbed_official	85:e1a8e879a6a9	153	__I uint32_t RESERVED2[126];
mbed_official	85:e1a8e879a6a9	154	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
mbed_official	85:e1a8e879a6a9	155	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
mbed_official	85:e1a8e879a6a9	156	__I uint32_t RESERVED3[61];
mbed_official	85:e1a8e879a6a9	157	__IO uint32_t RESETREAS; /!< Reset reason. /
mbed_official	85:e1a8e879a6a9	158	__I uint32_t RESERVED4[63];
mbed_official	85:e1a8e879a6a9	159	__O uint32_t SYSTEMOFF; /!< System off register. /
mbed_official	85:e1a8e879a6a9	160	__I uint32_t RESERVED5[3];
mbed_official	85:e1a8e879a6a9	161	__IO uint32_t POFCON; /!< Power failure configuration. /
mbed_official	85:e1a8e879a6a9	162	__I uint32_t RESERVED6[2];
mbed_official	85:e1a8e879a6a9	163	__IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
mbed_official	85:e1a8e879a6a9	164	register. */
mbed_official	85:e1a8e879a6a9	165	__I uint32_t RESERVED7;
mbed_official	85:e1a8e879a6a9	166	__IO uint32_t RAMON; /!< Ram on/off. /
mbed_official	85:e1a8e879a6a9	167	__I uint32_t RESERVED8[7];
mbed_official	85:e1a8e879a6a9	168	__IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
mbed_official	85:e1a8e879a6a9	169	is a retained register. */
mbed_official	85:e1a8e879a6a9	170	__I uint32_t RESERVED9[12];
mbed_official	85:e1a8e879a6a9	171	__IO uint32_t DCDCEN; /!< DCDC converter enable configuration register. /
mbed_official	85:e1a8e879a6a9	172	} NRF_POWER_Type;
mbed_official	85:e1a8e879a6a9	173
mbed_official	85:e1a8e879a6a9	174
mbed_official	85:e1a8e879a6a9	175	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	176	/* ================ CLOCK ================ */
mbed_official	85:e1a8e879a6a9	177	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	178
mbed_official	85:e1a8e879a6a9	179
mbed_official	85:e1a8e879a6a9	180	/**
mbed_official	85:e1a8e879a6a9	181	* @brief Clock control. (CLOCK)
mbed_official	85:e1a8e879a6a9	182	*/
mbed_official	85:e1a8e879a6a9	183
mbed_official	85:e1a8e879a6a9	184	typedef struct { /!< CLOCK Structure /
mbed_official	85:e1a8e879a6a9	185	__O uint32_t TASKS_HFCLKSTART; /!< Start HFCLK clock source. /
mbed_official	85:e1a8e879a6a9	186	__O uint32_t TASKS_HFCLKSTOP; /!< Stop HFCLK clock source. /
mbed_official	85:e1a8e879a6a9	187	__O uint32_t TASKS_LFCLKSTART; /!< Start LFCLK clock source. /
mbed_official	85:e1a8e879a6a9	188	__O uint32_t TASKS_LFCLKSTOP; /!< Stop LFCLK clock source. /
mbed_official	85:e1a8e879a6a9	189	__O uint32_t TASKS_CAL; /!< Start calibration of LFCLK RC oscillator. /
mbed_official	85:e1a8e879a6a9	190	__O uint32_t TASKS_CTSTART; /!< Start calibration timer. /
mbed_official	85:e1a8e879a6a9	191	__O uint32_t TASKS_CTSTOP; /!< Stop calibration timer. /
mbed_official	85:e1a8e879a6a9	192	__I uint32_t RESERVED0[57];
mbed_official	85:e1a8e879a6a9	193	__IO uint32_t EVENTS_HFCLKSTARTED; /!< HFCLK oscillator started. /
mbed_official	85:e1a8e879a6a9	194	__IO uint32_t EVENTS_LFCLKSTARTED; /!< LFCLK oscillator started. /
mbed_official	85:e1a8e879a6a9	195	__I uint32_t RESERVED1;
mbed_official	85:e1a8e879a6a9	196	__IO uint32_t EVENTS_DONE; /!< Callibration of LFCLK RC oscillator completed. /
mbed_official	85:e1a8e879a6a9	197	__IO uint32_t EVENTS_CTTO; /!< Callibration timer timeout. /
mbed_official	85:e1a8e879a6a9	198	__I uint32_t RESERVED2[124];
mbed_official	85:e1a8e879a6a9	199	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
mbed_official	85:e1a8e879a6a9	200	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
mbed_official	85:e1a8e879a6a9	201	__I uint32_t RESERVED3[64];
mbed_official	85:e1a8e879a6a9	202	__I uint32_t HFCLKSTAT; /!< High frequency clock status. /
mbed_official	85:e1a8e879a6a9	203	__I uint32_t RESERVED4[2];
mbed_official	85:e1a8e879a6a9	204	__I uint32_t LFCLKSTAT; /!< Low frequency clock status. /
mbed_official	85:e1a8e879a6a9	205	__I uint32_t RESERVED5[63];
mbed_official	85:e1a8e879a6a9	206	__IO uint32_t LFCLKSRC; /!< Clock source for the LFCLK clock. /
mbed_official	85:e1a8e879a6a9	207	__I uint32_t RESERVED6[7];
mbed_official	85:e1a8e879a6a9	208	__IO uint32_t CTIV; /!< Calibration timer interval. /
mbed_official	85:e1a8e879a6a9	209	__I uint32_t RESERVED7[5];
mbed_official	85:e1a8e879a6a9	210	__IO uint32_t XTALFREQ; /!< Crystal frequency. /
mbed_official	85:e1a8e879a6a9	211	} NRF_CLOCK_Type;
mbed_official	85:e1a8e879a6a9	212
mbed_official	85:e1a8e879a6a9	213
mbed_official	85:e1a8e879a6a9	214	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	215	/* ================ MPU ================ */
mbed_official	85:e1a8e879a6a9	216	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	217
mbed_official	85:e1a8e879a6a9	218
mbed_official	85:e1a8e879a6a9	219	/**
mbed_official	85:e1a8e879a6a9	220	* @brief Memory Protection Unit. (MPU)
mbed_official	85:e1a8e879a6a9	221	*/
mbed_official	85:e1a8e879a6a9	222
mbed_official	85:e1a8e879a6a9	223	typedef struct { /!< MPU Structure /
mbed_official	85:e1a8e879a6a9	224	__I uint32_t RESERVED0[330];
mbed_official	85:e1a8e879a6a9	225	__IO uint32_t PERR0; /!< Configuration of peripherals in mpu regions. /
mbed_official	85:e1a8e879a6a9	226	__IO uint32_t RLENR0; /!< Length of RAM region 0. /
mbed_official	85:e1a8e879a6a9	227	__I uint32_t RESERVED1[52];
mbed_official	85:e1a8e879a6a9	228	__IO uint32_t PROTENSET0; /!< Protection bit enable set register for low addresses. /
mbed_official	85:e1a8e879a6a9	229	__IO uint32_t PROTENSET1; /!< Protection bit enable set register for high addresses. /
mbed_official	85:e1a8e879a6a9	230	__IO uint32_t DISABLEINDEBUG; /!< Disable protection mechanism in debug mode. /
mbed_official	85:e1a8e879a6a9	231	} NRF_MPU_Type;
mbed_official	85:e1a8e879a6a9	232
mbed_official	85:e1a8e879a6a9	233
mbed_official	85:e1a8e879a6a9	234	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	235	/* ================ PU ================ */
mbed_official	85:e1a8e879a6a9	236	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	237
mbed_official	85:e1a8e879a6a9	238
mbed_official	85:e1a8e879a6a9	239	/**
mbed_official	85:e1a8e879a6a9	240	* @brief Patch unit. (PU)
mbed_official	85:e1a8e879a6a9	241	*/
mbed_official	85:e1a8e879a6a9	242
mbed_official	85:e1a8e879a6a9	243	typedef struct { /!< PU Structure /
mbed_official	85:e1a8e879a6a9	244	__I uint32_t RESERVED0[448];
mbed_official	85:e1a8e879a6a9	245	__IO uint32_t REPLACEADDR[8]; /!< Address of first instruction to replace. /
mbed_official	85:e1a8e879a6a9	246	__I uint32_t RESERVED1[24];
mbed_official	85:e1a8e879a6a9	247	__IO uint32_t PATCHADDR[8]; /!< Relative address of patch instructions. /
mbed_official	85:e1a8e879a6a9	248	__I uint32_t RESERVED2[24];
mbed_official	85:e1a8e879a6a9	249	__IO uint32_t PATCHEN; /!< Patch enable register. /
mbed_official	85:e1a8e879a6a9	250	__IO uint32_t PATCHENSET; /!< Patch enable register. /
mbed_official	85:e1a8e879a6a9	251	__IO uint32_t PATCHENCLR; /!< Patch disable register. /
mbed_official	85:e1a8e879a6a9	252	} NRF_PU_Type;
mbed_official	85:e1a8e879a6a9	253
mbed_official	85:e1a8e879a6a9	254
mbed_official	85:e1a8e879a6a9	255	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	256	/* ================ AMLI ================ */
mbed_official	85:e1a8e879a6a9	257	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	258
mbed_official	85:e1a8e879a6a9	259
mbed_official	85:e1a8e879a6a9	260	/**
mbed_official	85:e1a8e879a6a9	261	* @brief AHB Multi-Layer Interface. (AMLI)
mbed_official	85:e1a8e879a6a9	262	*/
mbed_official	85:e1a8e879a6a9	263
mbed_official	85:e1a8e879a6a9	264	typedef struct { /!< AMLI Structure /
mbed_official	85:e1a8e879a6a9	265	__I uint32_t RESERVED0[896];
mbed_official	85:e1a8e879a6a9	266	AMLI_RAMPRI_Type RAMPRI; /!< RAM configurable priority configuration structure. /
mbed_official	85:e1a8e879a6a9	267	} NRF_AMLI_Type;
mbed_official	85:e1a8e879a6a9	268
mbed_official	85:e1a8e879a6a9	269
mbed_official	85:e1a8e879a6a9	270	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	271	/* ================ RADIO ================ */
mbed_official	85:e1a8e879a6a9	272	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	273
mbed_official	85:e1a8e879a6a9	274
mbed_official	85:e1a8e879a6a9	275	/**
mbed_official	85:e1a8e879a6a9	276	* @brief The radio. (RADIO)
mbed_official	85:e1a8e879a6a9	277	*/
mbed_official	85:e1a8e879a6a9	278
mbed_official	85:e1a8e879a6a9	279	typedef struct { /!< RADIO Structure /
mbed_official	85:e1a8e879a6a9	280	__O uint32_t TASKS_TXEN; /!< Enable radio in TX mode. /
mbed_official	85:e1a8e879a6a9	281	__O uint32_t TASKS_RXEN; /!< Enable radio in RX mode. /
mbed_official	85:e1a8e879a6a9	282	__O uint32_t TASKS_START; /!< Start radio. /
mbed_official	85:e1a8e879a6a9	283	__O uint32_t TASKS_STOP; /!< Stop radio. /
mbed_official	85:e1a8e879a6a9	284	__O uint32_t TASKS_DISABLE; /!< Disable radio. /
mbed_official	85:e1a8e879a6a9	285	__O uint32_t TASKS_RSSISTART; /!< Start the RSSI and take one sample of the receive signal strength. /
mbed_official	85:e1a8e879a6a9	286	__O uint32_t TASKS_RSSISTOP; /!< Stop the RSSI measurement. /
mbed_official	85:e1a8e879a6a9	287	__O uint32_t TASKS_BCSTART; /!< Start the bit counter. /
mbed_official	85:e1a8e879a6a9	288	__O uint32_t TASKS_BCSTOP; /!< Stop the bit counter. /
mbed_official	85:e1a8e879a6a9	289	__I uint32_t RESERVED0[55];
mbed_official	85:e1a8e879a6a9	290	__IO uint32_t EVENTS_READY; /!< Ready event. /
mbed_official	85:e1a8e879a6a9	291	__IO uint32_t EVENTS_ADDRESS; /!< Address event. /
mbed_official	85:e1a8e879a6a9	292	__IO uint32_t EVENTS_PAYLOAD; /!< Payload event. /
mbed_official	85:e1a8e879a6a9	293	__IO uint32_t EVENTS_END; /!< End event. /
mbed_official	85:e1a8e879a6a9	294	__IO uint32_t EVENTS_DISABLED; /!< Disable event. /
mbed_official	85:e1a8e879a6a9	295	__IO uint32_t EVENTS_DEVMATCH; /!< A device address match occurred on the last received packet. /
mbed_official	85:e1a8e879a6a9	296	__IO uint32_t EVENTS_DEVMISS; /!< No device address match occurred on the last received packet. /
mbed_official	85:e1a8e879a6a9	297	__IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
mbed_official	85:e1a8e879a6a9	298	sample is ready for readout at the RSSISAMPLE register. */
mbed_official	85:e1a8e879a6a9	299	__I uint32_t RESERVED1[2];
mbed_official	85:e1a8e879a6a9	300	__IO uint32_t EVENTS_BCMATCH; /!< Bit counter reached bit count value specified in BC register. /
mbed_official	85:e1a8e879a6a9	301	__I uint32_t RESERVED2[53];
mbed_official	85:e1a8e879a6a9	302	__IO uint32_t SHORTS; /!< Shortcut for the radio. /
mbed_official	85:e1a8e879a6a9	303	__I uint32_t RESERVED3[64];
mbed_official	85:e1a8e879a6a9	304	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
mbed_official	85:e1a8e879a6a9	305	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
mbed_official	85:e1a8e879a6a9	306	__I uint32_t RESERVED4[61];
mbed_official	85:e1a8e879a6a9	307	__I uint32_t CRCSTATUS; /!< CRC status of received packet. /
mbed_official	85:e1a8e879a6a9	308	__I uint32_t RESERVED5;
mbed_official	85:e1a8e879a6a9	309	__I uint32_t RXMATCH; /!< Received address. /
mbed_official	85:e1a8e879a6a9	310	__I uint32_t RXCRC; /!< Received CRC. /
mbed_official	85:e1a8e879a6a9	311	__IO uint32_t DAI; /!< Device address match index. /
mbed_official	85:e1a8e879a6a9	312	__I uint32_t RESERVED6[60];
mbed_official	85:e1a8e879a6a9	313	__IO uint32_t PACKETPTR; /!< Packet pointer. Decision point: START task. /
mbed_official	85:e1a8e879a6a9	314	__IO uint32_t FREQUENCY; /!< Frequency. /
mbed_official	85:e1a8e879a6a9	315	__IO uint32_t TXPOWER; /!< Output power. /
mbed_official	85:e1a8e879a6a9	316	__IO uint32_t MODE; /!< Data rate and modulation. /
mbed_official	85:e1a8e879a6a9	317	__IO uint32_t PCNF0; /!< Packet configuration 0. /
mbed_official	85:e1a8e879a6a9	318	__IO uint32_t PCNF1; /!< Packet configuration 1. /
mbed_official	85:e1a8e879a6a9	319	__IO uint32_t BASE0; /!< Radio base address 0. Decision point: START task. /
mbed_official	85:e1a8e879a6a9	320	__IO uint32_t BASE1; /!< Radio base address 1. Decision point: START task. /
mbed_official	85:e1a8e879a6a9	321	__IO uint32_t PREFIX0; /!< Prefixes bytes for logical addresses 0 to 3. /
mbed_official	85:e1a8e879a6a9	322	__IO uint32_t PREFIX1; /!< Prefixes bytes for logical addresses 4 to 7. /
mbed_official	85:e1a8e879a6a9	323	__IO uint32_t TXADDRESS; /!< Transmit address select. /
mbed_official	85:e1a8e879a6a9	324	__IO uint32_t RXADDRESSES; /!< Receive address select. /
mbed_official	85:e1a8e879a6a9	325	__IO uint32_t CRCCNF; /!< CRC configuration. /
mbed_official	85:e1a8e879a6a9	326	__IO uint32_t CRCPOLY; /!< CRC polynomial. /
mbed_official	85:e1a8e879a6a9	327	__IO uint32_t CRCINIT; /!< CRC initial value. /
mbed_official	85:e1a8e879a6a9	328	__IO uint32_t TEST; /!< Test features enable register. /
mbed_official	85:e1a8e879a6a9	329	__IO uint32_t TIFS; /!< Inter Frame Spacing in microseconds. /
mbed_official	85:e1a8e879a6a9	330	__IO uint32_t RSSISAMPLE; /!< RSSI sample. /
mbed_official	85:e1a8e879a6a9	331	__I uint32_t RESERVED7;
mbed_official	85:e1a8e879a6a9	332	__I uint32_t STATE; /!< Current radio state. /
mbed_official	85:e1a8e879a6a9	333	__IO uint32_t DATAWHITEIV; /!< Data whitening initial value. /
mbed_official	85:e1a8e879a6a9	334	__I uint32_t RESERVED8[2];
mbed_official	85:e1a8e879a6a9	335	__IO uint32_t BCC; /!< Bit counter compare. /
mbed_official	85:e1a8e879a6a9	336	__I uint32_t RESERVED9[39];
mbed_official	85:e1a8e879a6a9	337	__IO uint32_t DAB[8]; /!< Device address base segment. /
mbed_official	85:e1a8e879a6a9	338	__IO uint32_t DAP[8]; /!< Device address prefix. /
mbed_official	85:e1a8e879a6a9	339	__IO uint32_t DACNF; /!< Device address match configuration. /
mbed_official	85:e1a8e879a6a9	340	__I uint32_t RESERVED10[56];
mbed_official	85:e1a8e879a6a9	341	__IO uint32_t OVERRIDE0; /!< Trim value override register 0. /
mbed_official	85:e1a8e879a6a9	342	__IO uint32_t OVERRIDE1; /!< Trim value override register 1. /
mbed_official	85:e1a8e879a6a9	343	__IO uint32_t OVERRIDE2; /!< Trim value override register 2. /
mbed_official	85:e1a8e879a6a9	344	__IO uint32_t OVERRIDE3; /!< Trim value override register 3. /
mbed_official	85:e1a8e879a6a9	345	__IO uint32_t OVERRIDE4; /!< Trim value override register 4. /
mbed_official	85:e1a8e879a6a9	346	__I uint32_t RESERVED11[561];
mbed_official	85:e1a8e879a6a9	347	__IO uint32_t POWER; /!< Peripheral power control. /
mbed_official	85:e1a8e879a6a9	348	} NRF_RADIO_Type;
mbed_official	85:e1a8e879a6a9	349
mbed_official	85:e1a8e879a6a9	350
mbed_official	85:e1a8e879a6a9	351	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	352	/* ================ UART ================ */
mbed_official	85:e1a8e879a6a9	353	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	354
mbed_official	85:e1a8e879a6a9	355
mbed_official	85:e1a8e879a6a9	356	/**
mbed_official	85:e1a8e879a6a9	357	* @brief Universal Asynchronous Receiver/Transmitter. (UART)
mbed_official	85:e1a8e879a6a9	358	*/
mbed_official	85:e1a8e879a6a9	359
mbed_official	85:e1a8e879a6a9	360	typedef struct { /!< UART Structure /
mbed_official	85:e1a8e879a6a9	361	__O uint32_t TASKS_STARTRX; /!< Start UART receiver. /
mbed_official	85:e1a8e879a6a9	362	__O uint32_t TASKS_STOPRX; /!< Stop UART receiver. /
mbed_official	85:e1a8e879a6a9	363	__O uint32_t TASKS_STARTTX; /!< Start UART transmitter. /
mbed_official	85:e1a8e879a6a9	364	__O uint32_t TASKS_STOPTX; /!< Stop UART transmitter. /
mbed_official	85:e1a8e879a6a9	365	__I uint32_t RESERVED0[3];
mbed_official	85:e1a8e879a6a9	366	__O uint32_t TASKS_SUSPEND; /!< Suspend UART. /
mbed_official	85:e1a8e879a6a9	367	__I uint32_t RESERVED1[56];
mbed_official	85:e1a8e879a6a9	368	__IO uint32_t EVENTS_CTS; /!< CTS activated. /
mbed_official	85:e1a8e879a6a9	369	__IO uint32_t EVENTS_NCTS; /!< CTS deactivated. /
mbed_official	85:e1a8e879a6a9	370	__IO uint32_t EVENTS_RXDRDY; /!< Data received in RXD. /
mbed_official	85:e1a8e879a6a9	371	__I uint32_t RESERVED2[4];
mbed_official	85:e1a8e879a6a9	372	__IO uint32_t EVENTS_TXDRDY; /!< Data sent from TXD. /
mbed_official	85:e1a8e879a6a9	373	__I uint32_t RESERVED3;
mbed_official	85:e1a8e879a6a9	374	__IO uint32_t EVENTS_ERROR; /!< Error detected. /
mbed_official	85:e1a8e879a6a9	375	__I uint32_t RESERVED4[7];
mbed_official	85:e1a8e879a6a9	376	__IO uint32_t EVENTS_RXTO; /!< Receiver timeout. /
mbed_official	85:e1a8e879a6a9	377	__I uint32_t RESERVED5[46];
mbed_official	85:e1a8e879a6a9	378	__IO uint32_t SHORTS; /!< Shortcuts for TWI. /
mbed_official	433:73d4f6083dd2	379	__I uint32_t RESERVED6[63];
mbed_official	433:73d4f6083dd2	380	__IO uint32_t INTEN; /!< Interrupt enable register. /
mbed_official	85:e1a8e879a6a9	381	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
mbed_official	85:e1a8e879a6a9	382	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
mbed_official	85:e1a8e879a6a9	383	__I uint32_t RESERVED7[93];
mbed_official	85:e1a8e879a6a9	384	__IO uint32_t ERRORSRC; /!< Error source. Write error field to 1 to clear error. /
mbed_official	85:e1a8e879a6a9	385	__I uint32_t RESERVED8[31];
mbed_official	85:e1a8e879a6a9	386	__IO uint32_t ENABLE; /!< Enable UART and acquire IOs. /
mbed_official	85:e1a8e879a6a9	387	__I uint32_t RESERVED9;
mbed_official	85:e1a8e879a6a9	388	__IO uint32_t PSELRTS; /!< Pin select for RTS. /
mbed_official	85:e1a8e879a6a9	389	__IO uint32_t PSELTXD; /!< Pin select for TXD. /
mbed_official	85:e1a8e879a6a9	390	__IO uint32_t PSELCTS; /!< Pin select for CTS. /
mbed_official	85:e1a8e879a6a9	391	__IO uint32_t PSELRXD; /!< Pin select for RXD. /
mbed_official	85:e1a8e879a6a9	392	__I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
mbed_official	85:e1a8e879a6a9	393	Once read the character is consummed. If read when no character
mbed_official	85:e1a8e879a6a9	394	available, the UART will stop working. */
mbed_official	85:e1a8e879a6a9	395	__O uint32_t TXD; /!< TXD register. /
mbed_official	85:e1a8e879a6a9	396	__I uint32_t RESERVED10;
mbed_official	85:e1a8e879a6a9	397	__IO uint32_t BAUDRATE; /!< UART Baudrate. /
mbed_official	85:e1a8e879a6a9	398	__I uint32_t RESERVED11[17];
mbed_official	85:e1a8e879a6a9	399	__IO uint32_t CONFIG; /!< Configuration of parity and hardware flow control register. /
mbed_official	85:e1a8e879a6a9	400	__I uint32_t RESERVED12[675];
mbed_official	85:e1a8e879a6a9	401	__IO uint32_t POWER; /!< Peripheral power control. /
mbed_official	85:e1a8e879a6a9	402	} NRF_UART_Type;
mbed_official	85:e1a8e879a6a9	403
mbed_official	85:e1a8e879a6a9	404
mbed_official	85:e1a8e879a6a9	405	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	406	/* ================ SPI ================ */
mbed_official	85:e1a8e879a6a9	407	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	408
mbed_official	85:e1a8e879a6a9	409
mbed_official	85:e1a8e879a6a9	410	/**
mbed_official	85:e1a8e879a6a9	411	* @brief SPI master 0. (SPI)
mbed_official	85:e1a8e879a6a9	412	*/
mbed_official	85:e1a8e879a6a9	413
mbed_official	85:e1a8e879a6a9	414	typedef struct { /!< SPI Structure /
mbed_official	85:e1a8e879a6a9	415	__I uint32_t RESERVED0[66];
mbed_official	85:e1a8e879a6a9	416	__IO uint32_t EVENTS_READY; /!< TXD byte sent and RXD byte received. /
mbed_official	85:e1a8e879a6a9	417	__I uint32_t RESERVED1[126];
mbed_official	85:e1a8e879a6a9	418	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
mbed_official	85:e1a8e879a6a9	419	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
mbed_official	85:e1a8e879a6a9	420	__I uint32_t RESERVED2[125];
mbed_official	85:e1a8e879a6a9	421	__IO uint32_t ENABLE; /!< Enable SPI. /
mbed_official	85:e1a8e879a6a9	422	__I uint32_t RESERVED3;
mbed_official	85:e1a8e879a6a9	423	__IO uint32_t PSELSCK; /!< Pin select for SCK. /
mbed_official	85:e1a8e879a6a9	424	__IO uint32_t PSELMOSI; /!< Pin select for MOSI. /
mbed_official	85:e1a8e879a6a9	425	__IO uint32_t PSELMISO; /!< Pin select for MISO. /
mbed_official	85:e1a8e879a6a9	426	__I uint32_t RESERVED4;
mbed_official	85:e1a8e879a6a9	427	__IO uint32_t RXD; /!< RX data. /
mbed_official	85:e1a8e879a6a9	428	__IO uint32_t TXD; /!< TX data. /
mbed_official	85:e1a8e879a6a9	429	__I uint32_t RESERVED5;
mbed_official	85:e1a8e879a6a9	430	__IO uint32_t FREQUENCY; /!< SPI frequency /
mbed_official	85:e1a8e879a6a9	431	__I uint32_t RESERVED6[11];
mbed_official	85:e1a8e879a6a9	432	__IO uint32_t CONFIG; /!< Configuration register. /
mbed_official	85:e1a8e879a6a9	433	__I uint32_t RESERVED7[681];
mbed_official	85:e1a8e879a6a9	434	__IO uint32_t POWER; /!< Peripheral power control. /
mbed_official	85:e1a8e879a6a9	435	} NRF_SPI_Type;
mbed_official	85:e1a8e879a6a9	436
mbed_official	85:e1a8e879a6a9	437
mbed_official	85:e1a8e879a6a9	438	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	439	/* ================ TWI ================ */
mbed_official	85:e1a8e879a6a9	440	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	441
mbed_official	85:e1a8e879a6a9	442
mbed_official	85:e1a8e879a6a9	443	/**
mbed_official	85:e1a8e879a6a9	444	* @brief Two-wire interface master 0. (TWI)
mbed_official	85:e1a8e879a6a9	445	*/
mbed_official	85:e1a8e879a6a9	446
mbed_official	85:e1a8e879a6a9	447	typedef struct { /!< TWI Structure /
mbed_official	85:e1a8e879a6a9	448	__O uint32_t TASKS_STARTRX; /!< Start 2-Wire master receive sequence. /
mbed_official	85:e1a8e879a6a9	449	__I uint32_t RESERVED0;
mbed_official	85:e1a8e879a6a9	450	__O uint32_t TASKS_STARTTX; /!< Start 2-Wire master transmit sequence. /
mbed_official	85:e1a8e879a6a9	451	__I uint32_t RESERVED1[2];
mbed_official	85:e1a8e879a6a9	452	__O uint32_t TASKS_STOP; /!< Stop 2-Wire transaction. /
mbed_official	85:e1a8e879a6a9	453	__I uint32_t RESERVED2;
mbed_official	85:e1a8e879a6a9	454	__O uint32_t TASKS_SUSPEND; /!< Suspend 2-Wire transaction. /
mbed_official	85:e1a8e879a6a9	455	__O uint32_t TASKS_RESUME; /!< Resume 2-Wire transaction. /
mbed_official	85:e1a8e879a6a9	456	__I uint32_t RESERVED3[56];
mbed_official	85:e1a8e879a6a9	457	__IO uint32_t EVENTS_STOPPED; /!< Two-wire stopped. /
mbed_official	85:e1a8e879a6a9	458	__IO uint32_t EVENTS_RXDREADY; /!< Two-wire ready to deliver new RXD byte received. /
mbed_official	85:e1a8e879a6a9	459	__I uint32_t RESERVED4[4];
mbed_official	85:e1a8e879a6a9	460	__IO uint32_t EVENTS_TXDSENT; /!< Two-wire finished sending last TXD byte. /
mbed_official	85:e1a8e879a6a9	461	__I uint32_t RESERVED5;
mbed_official	85:e1a8e879a6a9	462	__IO uint32_t EVENTS_ERROR; /!< Two-wire error detected. /
mbed_official	85:e1a8e879a6a9	463	__I uint32_t RESERVED6[4];
mbed_official	85:e1a8e879a6a9	464	__IO uint32_t EVENTS_BB; /!< Two-wire byte boundary. /
mbed_official	85:e1a8e879a6a9	465	__I uint32_t RESERVED7[49];
mbed_official	85:e1a8e879a6a9	466	__IO uint32_t SHORTS; /!< Shortcuts for TWI. /
mbed_official	85:e1a8e879a6a9	467	__I uint32_t RESERVED8[64];
mbed_official	85:e1a8e879a6a9	468	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
mbed_official	85:e1a8e879a6a9	469	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
mbed_official	85:e1a8e879a6a9	470	__I uint32_t RESERVED9[110];
mbed_official	85:e1a8e879a6a9	471	__IO uint32_t ERRORSRC; /!< Two-wire error source. Write error field to 1 to clear error. /
mbed_official	85:e1a8e879a6a9	472	__I uint32_t RESERVED10[14];
mbed_official	85:e1a8e879a6a9	473	__IO uint32_t ENABLE; /!< Enable two-wire master. /
mbed_official	85:e1a8e879a6a9	474	__I uint32_t RESERVED11;
mbed_official	85:e1a8e879a6a9	475	__IO uint32_t PSELSCL; /!< Pin select for SCL. /
mbed_official	85:e1a8e879a6a9	476	__IO uint32_t PSELSDA; /!< Pin select for SDA. /
mbed_official	85:e1a8e879a6a9	477	__I uint32_t RESERVED12[2];
mbed_official	85:e1a8e879a6a9	478	__IO uint32_t RXD; /!< RX data register. /
mbed_official	85:e1a8e879a6a9	479	__IO uint32_t TXD; /!< TX data register. /
mbed_official	85:e1a8e879a6a9	480	__I uint32_t RESERVED13;
mbed_official	85:e1a8e879a6a9	481	__IO uint32_t FREQUENCY; /!< Two-wire frequency. /
mbed_official	85:e1a8e879a6a9	482	__I uint32_t RESERVED14[24];
mbed_official	85:e1a8e879a6a9	483	__IO uint32_t ADDRESS; /!< Address used in the two-wire transfer. /
mbed_official	85:e1a8e879a6a9	484	__I uint32_t RESERVED15[668];
mbed_official	85:e1a8e879a6a9	485	__IO uint32_t POWER; /!< Peripheral power control. /
mbed_official	85:e1a8e879a6a9	486	} NRF_TWI_Type;
mbed_official	85:e1a8e879a6a9	487
mbed_official	85:e1a8e879a6a9	488
mbed_official	85:e1a8e879a6a9	489	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	490	/* ================ SPIS ================ */
mbed_official	85:e1a8e879a6a9	491	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	492
mbed_official	85:e1a8e879a6a9	493
mbed_official	85:e1a8e879a6a9	494	/**
mbed_official	85:e1a8e879a6a9	495	* @brief SPI slave 1. (SPIS)
mbed_official	85:e1a8e879a6a9	496	*/
mbed_official	85:e1a8e879a6a9	497
mbed_official	85:e1a8e879a6a9	498	typedef struct { /!< SPIS Structure /
mbed_official	85:e1a8e879a6a9	499	__I uint32_t RESERVED0[9];
mbed_official	85:e1a8e879a6a9	500	__O uint32_t TASKS_ACQUIRE; /!< Acquire SPI semaphore. /
mbed_official	85:e1a8e879a6a9	501	__O uint32_t TASKS_RELEASE; /!< Release SPI semaphore. /
mbed_official	85:e1a8e879a6a9	502	__I uint32_t RESERVED1[54];
mbed_official	85:e1a8e879a6a9	503	__IO uint32_t EVENTS_END; /!< Granted transaction completed. /
mbed_official	85:e1a8e879a6a9	504	__I uint32_t RESERVED2[8];
mbed_official	85:e1a8e879a6a9	505	__IO uint32_t EVENTS_ACQUIRED; /!< Semaphore acquired. /
mbed_official	85:e1a8e879a6a9	506	__I uint32_t RESERVED3[53];
mbed_official	85:e1a8e879a6a9	507	__IO uint32_t SHORTS; /!< Shortcuts for SPIS. /
mbed_official	85:e1a8e879a6a9	508	__I uint32_t RESERVED4[64];
mbed_official	85:e1a8e879a6a9	509	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
mbed_official	85:e1a8e879a6a9	510	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
mbed_official	85:e1a8e879a6a9	511	__I uint32_t RESERVED5[61];
mbed_official	85:e1a8e879a6a9	512	__I uint32_t SEMSTAT; /!< Semaphore status. /
mbed_official	85:e1a8e879a6a9	513	__I uint32_t RESERVED6[15];
mbed_official	85:e1a8e879a6a9	514	__IO uint32_t STATUS; /!< Status from last transaction. /
mbed_official	85:e1a8e879a6a9	515	__I uint32_t RESERVED7[47];
mbed_official	85:e1a8e879a6a9	516	__IO uint32_t ENABLE; /!< Enable SPIS. /
mbed_official	85:e1a8e879a6a9	517	__I uint32_t RESERVED8;
mbed_official	85:e1a8e879a6a9	518	__IO uint32_t PSELSCK; /!< Pin select for SCK. /
mbed_official	85:e1a8e879a6a9	519	__IO uint32_t PSELMISO; /!< Pin select for MISO. /
mbed_official	85:e1a8e879a6a9	520	__IO uint32_t PSELMOSI; /!< Pin select for MOSI. /
mbed_official	85:e1a8e879a6a9	521	__IO uint32_t PSELCSN; /!< Pin select for CSN. /
mbed_official	85:e1a8e879a6a9	522	__I uint32_t RESERVED9[7];
mbed_official	85:e1a8e879a6a9	523	__IO uint32_t RXDPTR; /!< RX data pointer. /
mbed_official	85:e1a8e879a6a9	524	__IO uint32_t MAXRX; /!< Maximum number of bytes in the receive buffer. /
mbed_official	85:e1a8e879a6a9	525	__IO uint32_t AMOUNTRX; /!< Number of bytes received in last granted transaction. /
mbed_official	85:e1a8e879a6a9	526	__I uint32_t RESERVED10;
mbed_official	85:e1a8e879a6a9	527	__IO uint32_t TXDPTR; /!< TX data pointer. /
mbed_official	85:e1a8e879a6a9	528	__IO uint32_t MAXTX; /!< Maximum number of bytes in the transmit buffer. /
mbed_official	85:e1a8e879a6a9	529	__IO uint32_t AMOUNTTX; /!< Number of bytes transmitted in last granted transaction. /
mbed_official	85:e1a8e879a6a9	530	__I uint32_t RESERVED11;
mbed_official	85:e1a8e879a6a9	531	__IO uint32_t CONFIG; /!< Configuration register. /
mbed_official	85:e1a8e879a6a9	532	__I uint32_t RESERVED12;
mbed_official	85:e1a8e879a6a9	533	__IO uint32_t DEF; /!< Default character. /
mbed_official	85:e1a8e879a6a9	534	__I uint32_t RESERVED13[24];
mbed_official	85:e1a8e879a6a9	535	__IO uint32_t ORC; /!< Over-read character. /
mbed_official	85:e1a8e879a6a9	536	__I uint32_t RESERVED14[654];
mbed_official	85:e1a8e879a6a9	537	__IO uint32_t POWER; /!< Peripheral power control. /
mbed_official	85:e1a8e879a6a9	538	} NRF_SPIS_Type;
mbed_official	85:e1a8e879a6a9	539
mbed_official	85:e1a8e879a6a9	540
mbed_official	85:e1a8e879a6a9	541	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	542	/* ================ GPIOTE ================ */
mbed_official	85:e1a8e879a6a9	543	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	544
mbed_official	85:e1a8e879a6a9	545
mbed_official	85:e1a8e879a6a9	546	/**
mbed_official	85:e1a8e879a6a9	547	* @brief GPIO tasks and events. (GPIOTE)
mbed_official	85:e1a8e879a6a9	548	*/
mbed_official	85:e1a8e879a6a9	549
mbed_official	85:e1a8e879a6a9	550	typedef struct { /!< GPIOTE Structure /
mbed_official	85:e1a8e879a6a9	551	__O uint32_t TASKS_OUT[4]; /!< Tasks asssociated with GPIOTE channels. /
mbed_official	85:e1a8e879a6a9	552	__I uint32_t RESERVED0[60];
mbed_official	85:e1a8e879a6a9	553	__IO uint32_t EVENTS_IN[4]; /!< Tasks asssociated with GPIOTE channels. /
mbed_official	85:e1a8e879a6a9	554	__I uint32_t RESERVED1[27];
mbed_official	85:e1a8e879a6a9	555	__IO uint32_t EVENTS_PORT; /!< Event generated from multiple pins. /
mbed_official	85:e1a8e879a6a9	556	__I uint32_t RESERVED2[97];
mbed_official	85:e1a8e879a6a9	557	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
mbed_official	85:e1a8e879a6a9	558	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
mbed_official	85:e1a8e879a6a9	559	__I uint32_t RESERVED3[129];
mbed_official	85:e1a8e879a6a9	560	__IO uint32_t CONFIG[4]; /!< Channel configuration registers. /
mbed_official	85:e1a8e879a6a9	561	__I uint32_t RESERVED4[695];
mbed_official	85:e1a8e879a6a9	562	__IO uint32_t POWER; /!< Peripheral power control. /
mbed_official	85:e1a8e879a6a9	563	} NRF_GPIOTE_Type;
mbed_official	85:e1a8e879a6a9	564
mbed_official	85:e1a8e879a6a9	565
mbed_official	85:e1a8e879a6a9	566	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	567	/* ================ ADC ================ */
mbed_official	85:e1a8e879a6a9	568	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	569
mbed_official	85:e1a8e879a6a9	570
mbed_official	85:e1a8e879a6a9	571	/**
mbed_official	85:e1a8e879a6a9	572	* @brief Analog to digital converter. (ADC)
mbed_official	85:e1a8e879a6a9	573	*/
mbed_official	85:e1a8e879a6a9	574
mbed_official	85:e1a8e879a6a9	575	typedef struct { /!< ADC Structure /
mbed_official	85:e1a8e879a6a9	576	__O uint32_t TASKS_START; /!< Start an ADC conversion. /
mbed_official	85:e1a8e879a6a9	577	__O uint32_t TASKS_STOP; /!< Stop ADC. /
mbed_official	85:e1a8e879a6a9	578	__I uint32_t RESERVED0[62];
mbed_official	85:e1a8e879a6a9	579	__IO uint32_t EVENTS_END; /!< ADC conversion complete. /
mbed_official	85:e1a8e879a6a9	580	__I uint32_t RESERVED1[128];
mbed_official	85:e1a8e879a6a9	581	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
mbed_official	85:e1a8e879a6a9	582	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
mbed_official	85:e1a8e879a6a9	583	__I uint32_t RESERVED2[61];
mbed_official	85:e1a8e879a6a9	584	__I uint32_t BUSY; /!< ADC busy register. /
mbed_official	85:e1a8e879a6a9	585	__I uint32_t RESERVED3[63];
mbed_official	85:e1a8e879a6a9	586	__IO uint32_t ENABLE; /!< ADC enable. /
mbed_official	85:e1a8e879a6a9	587	__IO uint32_t CONFIG; /!< ADC configuration register. /
mbed_official	85:e1a8e879a6a9	588	__I uint32_t RESULT; /!< Result of ADC conversion. /
mbed_official	85:e1a8e879a6a9	589	__I uint32_t RESERVED4[700];
mbed_official	85:e1a8e879a6a9	590	__IO uint32_t POWER; /!< Peripheral power control. /
mbed_official	85:e1a8e879a6a9	591	} NRF_ADC_Type;
mbed_official	85:e1a8e879a6a9	592
mbed_official	85:e1a8e879a6a9	593
mbed_official	85:e1a8e879a6a9	594	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	595	/* ================ TIMER ================ */
mbed_official	85:e1a8e879a6a9	596	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	597
mbed_official	85:e1a8e879a6a9	598
mbed_official	85:e1a8e879a6a9	599	/**
mbed_official	85:e1a8e879a6a9	600	* @brief Timer 0. (TIMER)
mbed_official	85:e1a8e879a6a9	601	*/
mbed_official	85:e1a8e879a6a9	602
mbed_official	85:e1a8e879a6a9	603	typedef struct { /!< TIMER Structure /
mbed_official	85:e1a8e879a6a9	604	__O uint32_t TASKS_START; /!< Start Timer. /
mbed_official	85:e1a8e879a6a9	605	__O uint32_t TASKS_STOP; /!< Stop Timer. /
mbed_official	85:e1a8e879a6a9	606	__O uint32_t TASKS_COUNT; /!< Increment Timer (In counter mode). /
mbed_official	85:e1a8e879a6a9	607	__O uint32_t TASKS_CLEAR; /!< Clear timer. /
mbed_official	85:e1a8e879a6a9	608	__I uint32_t RESERVED0[12];
mbed_official	85:e1a8e879a6a9	609	__O uint32_t TASKS_CAPTURE[4]; /!< Capture Timer value to CC[n] registers. /
mbed_official	85:e1a8e879a6a9	610	__I uint32_t RESERVED1[60];
mbed_official	85:e1a8e879a6a9	611	__IO uint32_t EVENTS_COMPARE[4]; /!< Compare event on CC[n] match. /
mbed_official	85:e1a8e879a6a9	612	__I uint32_t RESERVED2[44];
mbed_official	85:e1a8e879a6a9	613	__IO uint32_t SHORTS; /!< Shortcuts for Timer. /
mbed_official	85:e1a8e879a6a9	614	__I uint32_t RESERVED3[64];
mbed_official	85:e1a8e879a6a9	615	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
mbed_official	85:e1a8e879a6a9	616	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
mbed_official	85:e1a8e879a6a9	617	__I uint32_t RESERVED4[126];
mbed_official	85:e1a8e879a6a9	618	__IO uint32_t MODE; /!< Timer Mode selection. /
mbed_official	85:e1a8e879a6a9	619	__IO uint32_t BITMODE; /!< Sets timer behaviour. /
mbed_official	85:e1a8e879a6a9	620	__I uint32_t RESERVED5;
mbed_official	85:e1a8e879a6a9	621	__IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
mbed_official	85:e1a8e879a6a9	622	clock frequency is divided by 2^SCALE. */
mbed_official	85:e1a8e879a6a9	623	__I uint32_t RESERVED6[11];
mbed_official	85:e1a8e879a6a9	624	__IO uint32_t CC[4]; /!< Capture/compare registers. /
mbed_official	85:e1a8e879a6a9	625	__I uint32_t RESERVED7[683];
mbed_official	85:e1a8e879a6a9	626	__IO uint32_t POWER; /!< Peripheral power control. /
mbed_official	85:e1a8e879a6a9	627	} NRF_TIMER_Type;
mbed_official	85:e1a8e879a6a9	628
mbed_official	85:e1a8e879a6a9	629
mbed_official	85:e1a8e879a6a9	630	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	631	/* ================ RTC ================ */
mbed_official	85:e1a8e879a6a9	632	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	633
mbed_official	85:e1a8e879a6a9	634
mbed_official	85:e1a8e879a6a9	635	/**
mbed_official	85:e1a8e879a6a9	636	* @brief Real time counter 0. (RTC)
mbed_official	85:e1a8e879a6a9	637	*/
mbed_official	85:e1a8e879a6a9	638
mbed_official	85:e1a8e879a6a9	639	typedef struct { /!< RTC Structure /
mbed_official	85:e1a8e879a6a9	640	__O uint32_t TASKS_START; /!< Start RTC Counter. /
mbed_official	85:e1a8e879a6a9	641	__O uint32_t TASKS_STOP; /!< Stop RTC Counter. /
mbed_official	85:e1a8e879a6a9	642	__O uint32_t TASKS_CLEAR; /!< Clear RTC Counter. /
mbed_official	85:e1a8e879a6a9	643	__O uint32_t TASKS_TRIGOVRFLW; /!< Set COUNTER to 0xFFFFFFF0. /
mbed_official	85:e1a8e879a6a9	644	__I uint32_t RESERVED0[60];
mbed_official	85:e1a8e879a6a9	645	__IO uint32_t EVENTS_TICK; /!< Event on COUNTER increment. /
mbed_official	85:e1a8e879a6a9	646	__IO uint32_t EVENTS_OVRFLW; /!< Event on COUNTER overflow. /
mbed_official	85:e1a8e879a6a9	647	__I uint32_t RESERVED1[14];
mbed_official	85:e1a8e879a6a9	648	__IO uint32_t EVENTS_COMPARE[4]; /!< Compare event on CC[n] match. /
mbed_official	85:e1a8e879a6a9	649	__I uint32_t RESERVED2[109];
mbed_official	85:e1a8e879a6a9	650	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
mbed_official	85:e1a8e879a6a9	651	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
mbed_official	85:e1a8e879a6a9	652	__I uint32_t RESERVED3[13];
mbed_official	85:e1a8e879a6a9	653	__IO uint32_t EVTEN; /!< Configures event enable routing to PPI for each RTC event. /
mbed_official	85:e1a8e879a6a9	654	__IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
mbed_official	85:e1a8e879a6a9	655	the value of EVTEN. */
mbed_official	85:e1a8e879a6a9	656	__IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
mbed_official	85:e1a8e879a6a9	657	gives the value of EVTEN. */
mbed_official	85:e1a8e879a6a9	658	__I uint32_t RESERVED4[110];
mbed_official	85:e1a8e879a6a9	659	__IO uint32_t COUNTER; /!< Current COUNTER value. /
mbed_official	85:e1a8e879a6a9	660	__IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
mbed_official	85:e1a8e879a6a9	661	Must be written when RTC is STOPed. */
mbed_official	85:e1a8e879a6a9	662	__I uint32_t RESERVED5[13];
mbed_official	85:e1a8e879a6a9	663	__IO uint32_t CC[4]; /!< Capture/compare registers. /
mbed_official	85:e1a8e879a6a9	664	__I uint32_t RESERVED6[683];
mbed_official	85:e1a8e879a6a9	665	__IO uint32_t POWER; /!< Peripheral power control. /
mbed_official	85:e1a8e879a6a9	666	} NRF_RTC_Type;
mbed_official	85:e1a8e879a6a9	667
mbed_official	85:e1a8e879a6a9	668
mbed_official	85:e1a8e879a6a9	669	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	670	/* ================ TEMP ================ */
mbed_official	85:e1a8e879a6a9	671	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	672
mbed_official	85:e1a8e879a6a9	673
mbed_official	85:e1a8e879a6a9	674	/**
mbed_official	85:e1a8e879a6a9	675	* @brief Temperature Sensor. (TEMP)
mbed_official	85:e1a8e879a6a9	676	*/
mbed_official	85:e1a8e879a6a9	677
mbed_official	85:e1a8e879a6a9	678	typedef struct { /!< TEMP Structure /
mbed_official	85:e1a8e879a6a9	679	__O uint32_t TASKS_START; /!< Start temperature measurement. /
mbed_official	85:e1a8e879a6a9	680	__O uint32_t TASKS_STOP; /!< Stop temperature measurement. /
mbed_official	85:e1a8e879a6a9	681	__I uint32_t RESERVED0[62];
mbed_official	85:e1a8e879a6a9	682	__IO uint32_t EVENTS_DATARDY; /!< Temperature measurement complete, data ready event. /
mbed_official	85:e1a8e879a6a9	683	__I uint32_t RESERVED1[128];
mbed_official	85:e1a8e879a6a9	684	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
mbed_official	85:e1a8e879a6a9	685	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
mbed_official	85:e1a8e879a6a9	686	__I uint32_t RESERVED2[127];
mbed_official	85:e1a8e879a6a9	687	__I int32_t TEMP; /!< Die temperature in degC, 2's complement format, 0.25 degC pecision. /
mbed_official	85:e1a8e879a6a9	688	__I uint32_t RESERVED3[700];
mbed_official	85:e1a8e879a6a9	689	__IO uint32_t POWER; /!< Peripheral power control. /
mbed_official	85:e1a8e879a6a9	690	} NRF_TEMP_Type;
mbed_official	85:e1a8e879a6a9	691
mbed_official	85:e1a8e879a6a9	692
mbed_official	85:e1a8e879a6a9	693	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	694	/* ================ RNG ================ */
mbed_official	85:e1a8e879a6a9	695	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	696
mbed_official	85:e1a8e879a6a9	697
mbed_official	85:e1a8e879a6a9	698	/**
mbed_official	85:e1a8e879a6a9	699	* @brief Random Number Generator. (RNG)
mbed_official	85:e1a8e879a6a9	700	*/
mbed_official	85:e1a8e879a6a9	701
mbed_official	85:e1a8e879a6a9	702	typedef struct { /!< RNG Structure /
mbed_official	85:e1a8e879a6a9	703	__O uint32_t TASKS_START; /!< Start the random number generator. /
mbed_official	85:e1a8e879a6a9	704	__O uint32_t TASKS_STOP; /!< Stop the random number generator. /
mbed_official	85:e1a8e879a6a9	705	__I uint32_t RESERVED0[62];
mbed_official	85:e1a8e879a6a9	706	__IO uint32_t EVENTS_VALRDY; /!< New random number generated and written to VALUE register. /
mbed_official	85:e1a8e879a6a9	707	__I uint32_t RESERVED1[63];
mbed_official	85:e1a8e879a6a9	708	__IO uint32_t SHORTS; /!< Shortcut for the RNG. /
mbed_official	85:e1a8e879a6a9	709	__I uint32_t RESERVED2[64];
mbed_official	85:e1a8e879a6a9	710	__IO uint32_t INTENSET; /!< Interrupt enable set register /
mbed_official	85:e1a8e879a6a9	711	__IO uint32_t INTENCLR; /!< Interrupt enable clear register /
mbed_official	85:e1a8e879a6a9	712	__I uint32_t RESERVED3[126];
mbed_official	85:e1a8e879a6a9	713	__IO uint32_t CONFIG; /!< Configuration register. /
mbed_official	85:e1a8e879a6a9	714	__I uint32_t VALUE; /!< RNG random number. /
mbed_official	85:e1a8e879a6a9	715	__I uint32_t RESERVED4[700];
mbed_official	85:e1a8e879a6a9	716	__IO uint32_t POWER; /!< Peripheral power control. /
mbed_official	85:e1a8e879a6a9	717	} NRF_RNG_Type;
mbed_official	85:e1a8e879a6a9	718
mbed_official	85:e1a8e879a6a9	719
mbed_official	85:e1a8e879a6a9	720	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	721	/* ================ ECB ================ */
mbed_official	85:e1a8e879a6a9	722	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	723
mbed_official	85:e1a8e879a6a9	724
mbed_official	85:e1a8e879a6a9	725	/**
mbed_official	85:e1a8e879a6a9	726	* @brief AES ECB Mode Encryption. (ECB)
mbed_official	85:e1a8e879a6a9	727	*/
mbed_official	85:e1a8e879a6a9	728
mbed_official	85:e1a8e879a6a9	729	typedef struct { /!< ECB Structure /
mbed_official	85:e1a8e879a6a9	730	__O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
mbed_official	85:e1a8e879a6a9	731	will not initiate a new encryption and the ERRORECB event will
mbed_official	85:e1a8e879a6a9	732	be triggered. */
mbed_official	85:e1a8e879a6a9	733	__O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
mbed_official	85:e1a8e879a6a9	734	this will will trigger the ERRORECB event. */
mbed_official	85:e1a8e879a6a9	735	__I uint32_t RESERVED0[62];
mbed_official	85:e1a8e879a6a9	736	__IO uint32_t EVENTS_ENDECB; /!< ECB block encrypt complete. /
mbed_official	85:e1a8e879a6a9	737	__IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
mbed_official	85:e1a8e879a6a9	738	error. */
mbed_official	85:e1a8e879a6a9	739	__I uint32_t RESERVED1[127];
mbed_official	85:e1a8e879a6a9	740	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
mbed_official	85:e1a8e879a6a9	741	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
mbed_official	85:e1a8e879a6a9	742	__I uint32_t RESERVED2[126];
mbed_official	85:e1a8e879a6a9	743	__IO uint32_t ECBDATAPTR; /!< ECB block encrypt memory pointer. /
mbed_official	85:e1a8e879a6a9	744	__I uint32_t RESERVED3[701];
mbed_official	85:e1a8e879a6a9	745	__IO uint32_t POWER; /!< Peripheral power control. /
mbed_official	85:e1a8e879a6a9	746	} NRF_ECB_Type;
mbed_official	85:e1a8e879a6a9	747
mbed_official	85:e1a8e879a6a9	748
mbed_official	85:e1a8e879a6a9	749	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	750	/* ================ AAR ================ */
mbed_official	85:e1a8e879a6a9	751	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	752
mbed_official	85:e1a8e879a6a9	753
mbed_official	85:e1a8e879a6a9	754	/**
mbed_official	85:e1a8e879a6a9	755	* @brief Accelerated Address Resolver. (AAR)
mbed_official	85:e1a8e879a6a9	756	*/
mbed_official	85:e1a8e879a6a9	757
mbed_official	85:e1a8e879a6a9	758	typedef struct { /!< AAR Structure /
mbed_official	85:e1a8e879a6a9	759	__O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
mbed_official	85:e1a8e879a6a9	760	data structure. */
mbed_official	85:e1a8e879a6a9	761	__I uint32_t RESERVED0;
mbed_official	85:e1a8e879a6a9	762	__O uint32_t TASKS_STOP; /!< Stop resolving addresses. /
mbed_official	85:e1a8e879a6a9	763	__I uint32_t RESERVED1[61];
mbed_official	85:e1a8e879a6a9	764	__IO uint32_t EVENTS_END; /!< Address resolution procedure completed. /
mbed_official	85:e1a8e879a6a9	765	__IO uint32_t EVENTS_RESOLVED; /!< Address resolved. /
mbed_official	85:e1a8e879a6a9	766	__IO uint32_t EVENTS_NOTRESOLVED; /!< Address not resolved. /
mbed_official	85:e1a8e879a6a9	767	__I uint32_t RESERVED2[126];
mbed_official	85:e1a8e879a6a9	768	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
mbed_official	85:e1a8e879a6a9	769	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
mbed_official	85:e1a8e879a6a9	770	__I uint32_t RESERVED3[61];
mbed_official	85:e1a8e879a6a9	771	__I uint32_t STATUS; /!< Resolution status. /
mbed_official	85:e1a8e879a6a9	772	__I uint32_t RESERVED4[63];
mbed_official	85:e1a8e879a6a9	773	__IO uint32_t ENABLE; /!< Enable AAR. /
mbed_official	85:e1a8e879a6a9	774	__IO uint32_t NIRK; /!< Number of Identity root Keys in the IRK data structure. /
mbed_official	85:e1a8e879a6a9	775	__IO uint32_t IRKPTR; /!< Pointer to the IRK data structure. /
mbed_official	85:e1a8e879a6a9	776	__I uint32_t RESERVED5;
mbed_official	85:e1a8e879a6a9	777	__IO uint32_t ADDRPTR; /!< Pointer to the resolvable address (6 bytes). /
mbed_official	85:e1a8e879a6a9	778	__IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
mbed_official	85:e1a8e879a6a9	779	resolution. A minimum of 3 bytes must be reserved. */
mbed_official	85:e1a8e879a6a9	780	__I uint32_t RESERVED6[697];
mbed_official	85:e1a8e879a6a9	781	__IO uint32_t POWER; /!< Peripheral power control. /
mbed_official	85:e1a8e879a6a9	782	} NRF_AAR_Type;
mbed_official	85:e1a8e879a6a9	783
mbed_official	85:e1a8e879a6a9	784
mbed_official	85:e1a8e879a6a9	785	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	786	/* ================ CCM ================ */
mbed_official	85:e1a8e879a6a9	787	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	788
mbed_official	85:e1a8e879a6a9	789
mbed_official	85:e1a8e879a6a9	790	/**
mbed_official	85:e1a8e879a6a9	791	* @brief AES CCM Mode Encryption. (CCM)
mbed_official	85:e1a8e879a6a9	792	*/
mbed_official	85:e1a8e879a6a9	793
mbed_official	85:e1a8e879a6a9	794	typedef struct { /!< CCM Structure /
mbed_official	85:e1a8e879a6a9	795	__O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
mbed_official	85:e1a8e879a6a9	796	itself when completed. */
mbed_official	85:e1a8e879a6a9	797	__O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
mbed_official	85:e1a8e879a6a9	798	completed. */
mbed_official	85:e1a8e879a6a9	799	__O uint32_t TASKS_STOP; /!< Stop encrypt/decrypt. /
mbed_official	85:e1a8e879a6a9	800	__I uint32_t RESERVED0[61];
mbed_official	85:e1a8e879a6a9	801	__IO uint32_t EVENTS_ENDKSGEN; /!< Keystream generation completed. /
mbed_official	85:e1a8e879a6a9	802	__IO uint32_t EVENTS_ENDCRYPT; /!< Encrypt/decrypt completed. /
mbed_official	85:e1a8e879a6a9	803	__IO uint32_t EVENTS_ERROR; /!< Error happened. /
mbed_official	85:e1a8e879a6a9	804	__I uint32_t RESERVED1[61];
mbed_official	85:e1a8e879a6a9	805	__IO uint32_t SHORTS; /!< Shortcut for the CCM. /
mbed_official	85:e1a8e879a6a9	806	__I uint32_t RESERVED2[64];
mbed_official	85:e1a8e879a6a9	807	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
mbed_official	85:e1a8e879a6a9	808	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
mbed_official	85:e1a8e879a6a9	809	__I uint32_t RESERVED3[61];
mbed_official	85:e1a8e879a6a9	810	__I uint32_t MICSTATUS; /!< CCM RX MIC check result. /
mbed_official	85:e1a8e879a6a9	811	__I uint32_t RESERVED4[63];
mbed_official	85:e1a8e879a6a9	812	__IO uint32_t ENABLE; /!< CCM enable. /
mbed_official	85:e1a8e879a6a9	813	__IO uint32_t MODE; /!< Operation mode. /
mbed_official	85:e1a8e879a6a9	814	__IO uint32_t CNFPTR; /!< Pointer to data structure holding AES key and NONCE vector. /
mbed_official	85:e1a8e879a6a9	815	__IO uint32_t INPTR; /!< Pointer to input packet. /
mbed_official	85:e1a8e879a6a9	816	__IO uint32_t OUTPTR; /!< Pointer to output packet. /
mbed_official	85:e1a8e879a6a9	817	__IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
mbed_official	85:e1a8e879a6a9	818	resolution. A minimum of 43 bytes must be reserved. */
mbed_official	85:e1a8e879a6a9	819	__I uint32_t RESERVED5[697];
mbed_official	85:e1a8e879a6a9	820	__IO uint32_t POWER; /!< Peripheral power control. /
mbed_official	85:e1a8e879a6a9	821	} NRF_CCM_Type;
mbed_official	85:e1a8e879a6a9	822
mbed_official	85:e1a8e879a6a9	823
mbed_official	85:e1a8e879a6a9	824	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	825	/* ================ WDT ================ */
mbed_official	85:e1a8e879a6a9	826	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	827
mbed_official	85:e1a8e879a6a9	828
mbed_official	85:e1a8e879a6a9	829	/**
mbed_official	85:e1a8e879a6a9	830	* @brief Watchdog Timer. (WDT)
mbed_official	85:e1a8e879a6a9	831	*/
mbed_official	85:e1a8e879a6a9	832
mbed_official	85:e1a8e879a6a9	833	typedef struct { /!< WDT Structure /
mbed_official	85:e1a8e879a6a9	834	__O uint32_t TASKS_START; /!< Start the watchdog. /
mbed_official	85:e1a8e879a6a9	835	__I uint32_t RESERVED0[63];
mbed_official	85:e1a8e879a6a9	836	__IO uint32_t EVENTS_TIMEOUT; /!< Watchdog timeout. /
mbed_official	85:e1a8e879a6a9	837	__I uint32_t RESERVED1[128];
mbed_official	85:e1a8e879a6a9	838	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
mbed_official	85:e1a8e879a6a9	839	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
mbed_official	85:e1a8e879a6a9	840	__I uint32_t RESERVED2[61];
mbed_official	85:e1a8e879a6a9	841	__I uint32_t RUNSTATUS; /!< Watchdog running status. /
mbed_official	85:e1a8e879a6a9	842	__I uint32_t REQSTATUS; /!< Request status. /
mbed_official	85:e1a8e879a6a9	843	__I uint32_t RESERVED3[63];
mbed_official	85:e1a8e879a6a9	844	__IO uint32_t CRV; /!< Counter reload value in number of 32kiHz clock cycles. /
mbed_official	85:e1a8e879a6a9	845	__IO uint32_t RREN; /!< Reload request enable. /
mbed_official	85:e1a8e879a6a9	846	__IO uint32_t CONFIG; /!< Configuration register. /
mbed_official	85:e1a8e879a6a9	847	__I uint32_t RESERVED4[60];
mbed_official	85:e1a8e879a6a9	848	__O uint32_t RR[8]; /!< Reload requests registers. /
mbed_official	85:e1a8e879a6a9	849	__I uint32_t RESERVED5[631];
mbed_official	85:e1a8e879a6a9	850	__IO uint32_t POWER; /!< Peripheral power control. /
mbed_official	85:e1a8e879a6a9	851	} NRF_WDT_Type;
mbed_official	85:e1a8e879a6a9	852
mbed_official	85:e1a8e879a6a9	853
mbed_official	85:e1a8e879a6a9	854	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	855	/* ================ QDEC ================ */
mbed_official	85:e1a8e879a6a9	856	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	857
mbed_official	85:e1a8e879a6a9	858
mbed_official	85:e1a8e879a6a9	859	/**
mbed_official	85:e1a8e879a6a9	860	* @brief Rotary decoder. (QDEC)
mbed_official	85:e1a8e879a6a9	861	*/
mbed_official	85:e1a8e879a6a9	862
mbed_official	85:e1a8e879a6a9	863	typedef struct { /!< QDEC Structure /
mbed_official	85:e1a8e879a6a9	864	__O uint32_t TASKS_START; /!< Start the quadrature decoder. /
mbed_official	85:e1a8e879a6a9	865	__O uint32_t TASKS_STOP; /!< Stop the quadrature decoder. /
mbed_official	85:e1a8e879a6a9	866	__O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
mbed_official	85:e1a8e879a6a9	867	and clears the ACC registers. */
mbed_official	85:e1a8e879a6a9	868	__I uint32_t RESERVED0[61];
mbed_official	85:e1a8e879a6a9	869	__IO uint32_t EVENTS_SAMPLERDY; /!< A new sample is written to the sample register. /
mbed_official	85:e1a8e879a6a9	870	__IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
mbed_official	85:e1a8e879a6a9	871	ACC register different than zero. */
mbed_official	85:e1a8e879a6a9	872	__IO uint32_t EVENTS_ACCOF; /!< ACC or ACCDBL register overflow. /
mbed_official	85:e1a8e879a6a9	873	__I uint32_t RESERVED1[61];
mbed_official	85:e1a8e879a6a9	874	__IO uint32_t SHORTS; /!< Shortcut for the QDEC. /
mbed_official	85:e1a8e879a6a9	875	__I uint32_t RESERVED2[64];
mbed_official	85:e1a8e879a6a9	876	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
mbed_official	85:e1a8e879a6a9	877	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
mbed_official	85:e1a8e879a6a9	878	__I uint32_t RESERVED3[125];
mbed_official	85:e1a8e879a6a9	879	__IO uint32_t ENABLE; /!< Enable the QDEC. /
mbed_official	85:e1a8e879a6a9	880	__IO uint32_t LEDPOL; /!< LED output pin polarity. /
mbed_official	85:e1a8e879a6a9	881	__IO uint32_t SAMPLEPER; /!< Sample period. /
mbed_official	85:e1a8e879a6a9	882	__I int32_t SAMPLE; /!< Motion sample value. /
mbed_official	85:e1a8e879a6a9	883	__IO uint32_t REPORTPER; /!< Number of samples to generate an EVENT_REPORTRDY. /
mbed_official	85:e1a8e879a6a9	884	__I int32_t ACC; /!< Accumulated valid transitions register. /
mbed_official	85:e1a8e879a6a9	885	__I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
mbed_official	85:e1a8e879a6a9	886	task. */
mbed_official	85:e1a8e879a6a9	887	__IO uint32_t PSELLED; /!< Pin select for LED output. /
mbed_official	85:e1a8e879a6a9	888	__IO uint32_t PSELA; /!< Pin select for phase A input. /
mbed_official	85:e1a8e879a6a9	889	__IO uint32_t PSELB; /!< Pin select for phase B input. /
mbed_official	85:e1a8e879a6a9	890	__IO uint32_t DBFEN; /!< Enable debouncer input filters. /
mbed_official	85:e1a8e879a6a9	891	__I uint32_t RESERVED4[5];
mbed_official	85:e1a8e879a6a9	892	__IO uint32_t LEDPRE; /!< Time LED is switched ON before the sample. /
mbed_official	85:e1a8e879a6a9	893	__I uint32_t ACCDBL; /!< Accumulated double (error) transitions register. /
mbed_official	85:e1a8e879a6a9	894	__I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
mbed_official	85:e1a8e879a6a9	895	task. */
mbed_official	85:e1a8e879a6a9	896	__I uint32_t RESERVED5[684];
mbed_official	85:e1a8e879a6a9	897	__IO uint32_t POWER; /!< Peripheral power control. /
mbed_official	85:e1a8e879a6a9	898	} NRF_QDEC_Type;
mbed_official	85:e1a8e879a6a9	899
mbed_official	85:e1a8e879a6a9	900
mbed_official	85:e1a8e879a6a9	901	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	902	/* ================ LPCOMP ================ */
mbed_official	85:e1a8e879a6a9	903	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	904
mbed_official	85:e1a8e879a6a9	905
mbed_official	85:e1a8e879a6a9	906	/**
mbed_official	85:e1a8e879a6a9	907	* @brief Wakeup Comparator. (LPCOMP)
mbed_official	85:e1a8e879a6a9	908	*/
mbed_official	85:e1a8e879a6a9	909
mbed_official	85:e1a8e879a6a9	910	typedef struct { /!< LPCOMP Structure /
mbed_official	85:e1a8e879a6a9	911	__O uint32_t TASKS_START; /!< Start the comparator. /
mbed_official	85:e1a8e879a6a9	912	__O uint32_t TASKS_STOP; /!< Stop the comparator. /
mbed_official	85:e1a8e879a6a9	913	__O uint32_t TASKS_SAMPLE; /!< Sample comparator value. /
mbed_official	85:e1a8e879a6a9	914	__I uint32_t RESERVED0[61];
mbed_official	85:e1a8e879a6a9	915	__IO uint32_t EVENTS_READY; /!< LPCOMP is ready and output is valid. /
mbed_official	85:e1a8e879a6a9	916	__IO uint32_t EVENTS_DOWN; /!< Input voltage crossed the threshold going down. /
mbed_official	85:e1a8e879a6a9	917	__IO uint32_t EVENTS_UP; /!< Input voltage crossed the threshold going up. /
mbed_official	85:e1a8e879a6a9	918	__IO uint32_t EVENTS_CROSS; /!< Input voltage crossed the threshold in any direction. /
mbed_official	85:e1a8e879a6a9	919	__I uint32_t RESERVED1[60];
mbed_official	85:e1a8e879a6a9	920	__IO uint32_t SHORTS; /!< Shortcut for the LPCOMP. /
mbed_official	85:e1a8e879a6a9	921	__I uint32_t RESERVED2[64];
mbed_official	85:e1a8e879a6a9	922	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
mbed_official	85:e1a8e879a6a9	923	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
mbed_official	85:e1a8e879a6a9	924	__I uint32_t RESERVED3[61];
mbed_official	85:e1a8e879a6a9	925	__I uint32_t RESULT; /!< Result of last compare. /
mbed_official	85:e1a8e879a6a9	926	__I uint32_t RESERVED4[63];
mbed_official	85:e1a8e879a6a9	927	__IO uint32_t ENABLE; /!< Enable the LPCOMP. /
mbed_official	85:e1a8e879a6a9	928	__IO uint32_t PSEL; /!< Input pin select. /
mbed_official	85:e1a8e879a6a9	929	__IO uint32_t REFSEL; /!< Reference select. /
mbed_official	85:e1a8e879a6a9	930	__IO uint32_t EXTREFSEL; /!< External reference select. /
mbed_official	85:e1a8e879a6a9	931	__I uint32_t RESERVED5[4];
mbed_official	85:e1a8e879a6a9	932	__IO uint32_t ANADETECT; /!< Analog detect configuration. /
mbed_official	85:e1a8e879a6a9	933	__I uint32_t RESERVED6[694];
mbed_official	85:e1a8e879a6a9	934	__IO uint32_t POWER; /!< Peripheral power control. /
mbed_official	85:e1a8e879a6a9	935	} NRF_LPCOMP_Type;
mbed_official	85:e1a8e879a6a9	936
mbed_official	85:e1a8e879a6a9	937
mbed_official	85:e1a8e879a6a9	938	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	939	/* ================ COMP ================ */
mbed_official	85:e1a8e879a6a9	940	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	941
mbed_official	85:e1a8e879a6a9	942
mbed_official	85:e1a8e879a6a9	943	/**
mbed_official	85:e1a8e879a6a9	944	* @brief Comparator. (COMP)
mbed_official	85:e1a8e879a6a9	945	*/
mbed_official	85:e1a8e879a6a9	946
mbed_official	85:e1a8e879a6a9	947	typedef struct { /!< COMP Structure /
mbed_official	85:e1a8e879a6a9	948	__O uint32_t TASKS_START; /!< Start the comparator. /
mbed_official	85:e1a8e879a6a9	949	__O uint32_t TASKS_STOP; /!< Stop the comparator. /
mbed_official	85:e1a8e879a6a9	950	__O uint32_t TASKS_SAMPLE; /!< Sample comparator value. /
mbed_official	85:e1a8e879a6a9	951	__I uint32_t RESERVED0[61];
mbed_official	85:e1a8e879a6a9	952	__IO uint32_t EVENTS_READY; /!< COMP is ready and output is valid. /
mbed_official	85:e1a8e879a6a9	953	__IO uint32_t EVENTS_DOWN; /!< Input voltage crossed the threshold going down. /
mbed_official	85:e1a8e879a6a9	954	__IO uint32_t EVENTS_UP; /!< Input voltage crossed the threshold going up. /
mbed_official	85:e1a8e879a6a9	955	__IO uint32_t EVENTS_CROSS; /!< Input voltage crossed the threshold in any direction. /
mbed_official	85:e1a8e879a6a9	956	__I uint32_t RESERVED1[60];
mbed_official	85:e1a8e879a6a9	957	__IO uint32_t SHORTS; /!< Shortcut for the COMP. /
mbed_official	85:e1a8e879a6a9	958	__I uint32_t RESERVED2[64];
mbed_official	85:e1a8e879a6a9	959	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
mbed_official	85:e1a8e879a6a9	960	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
mbed_official	85:e1a8e879a6a9	961	__I uint32_t RESERVED3[61];
mbed_official	85:e1a8e879a6a9	962	__I uint32_t RESULT; /!< Compare result. /
mbed_official	85:e1a8e879a6a9	963	__I uint32_t RESERVED4[63];
mbed_official	85:e1a8e879a6a9	964	__IO uint32_t ENABLE; /!< Enable the COMP. /
mbed_official	85:e1a8e879a6a9	965	__IO uint32_t PSEL; /!< Input pin select. /
mbed_official	85:e1a8e879a6a9	966	__IO uint32_t REFSEL; /!< Reference select. /
mbed_official	85:e1a8e879a6a9	967	__IO uint32_t EXTREFSEL; /!< External reference select. /
mbed_official	85:e1a8e879a6a9	968	__I uint32_t RESERVED5[8];
mbed_official	85:e1a8e879a6a9	969	__IO uint32_t TH; /!< Threshold configuration for hysteresis unit. /
mbed_official	85:e1a8e879a6a9	970	__IO uint32_t MODE; /!< Mode configuration. /
mbed_official	85:e1a8e879a6a9	971	__I uint32_t RESERVED6[689];
mbed_official	85:e1a8e879a6a9	972	__IO uint32_t POWER; /!< Peripheral power control. /
mbed_official	85:e1a8e879a6a9	973	} NRF_COMP_Type;
mbed_official	85:e1a8e879a6a9	974
mbed_official	85:e1a8e879a6a9	975
mbed_official	85:e1a8e879a6a9	976	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	977	/* ================ SWI ================ */
mbed_official	85:e1a8e879a6a9	978	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	979
mbed_official	85:e1a8e879a6a9	980
mbed_official	85:e1a8e879a6a9	981	/**
mbed_official	85:e1a8e879a6a9	982	* @brief SW Interrupts. (SWI)
mbed_official	85:e1a8e879a6a9	983	*/
mbed_official	85:e1a8e879a6a9	984
mbed_official	85:e1a8e879a6a9	985	typedef struct { /!< SWI Structure /
mbed_official	85:e1a8e879a6a9	986	__I uint32_t UNUSED; /!< Unused. /
mbed_official	85:e1a8e879a6a9	987	} NRF_SWI_Type;
mbed_official	85:e1a8e879a6a9	988
mbed_official	85:e1a8e879a6a9	989
mbed_official	85:e1a8e879a6a9	990	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	991	/* ================ NVMC ================ */
mbed_official	85:e1a8e879a6a9	992	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	993
mbed_official	85:e1a8e879a6a9	994
mbed_official	85:e1a8e879a6a9	995	/**
mbed_official	85:e1a8e879a6a9	996	* @brief Non Volatile Memory Controller. (NVMC)
mbed_official	85:e1a8e879a6a9	997	*/
mbed_official	85:e1a8e879a6a9	998
mbed_official	85:e1a8e879a6a9	999	typedef struct { /!< NVMC Structure /
mbed_official	85:e1a8e879a6a9	1000	__I uint32_t RESERVED0[256];
mbed_official	85:e1a8e879a6a9	1001	__I uint32_t READY; /!< Ready flag. /
mbed_official	85:e1a8e879a6a9	1002	__I uint32_t RESERVED1[64];
mbed_official	85:e1a8e879a6a9	1003	__IO uint32_t CONFIG; /!< Configuration register. /
mbed_official	85:e1a8e879a6a9	1004	__IO uint32_t ERASEPAGE; /!< Register for erasing a non-protected non-volatile memory page. /
mbed_official	85:e1a8e879a6a9	1005	__IO uint32_t ERASEALL; /!< Register for erasing all non-volatile user memory. /
mbed_official	85:e1a8e879a6a9	1006	__IO uint32_t ERASEPROTECTEDPAGE; /!< Register for erasing a protected non-volatile memory page. /
mbed_official	85:e1a8e879a6a9	1007	__IO uint32_t ERASEUICR; /!< Register for start erasing User Information Congfiguration Registers. /
mbed_official	85:e1a8e879a6a9	1008	} NRF_NVMC_Type;
mbed_official	85:e1a8e879a6a9	1009
mbed_official	85:e1a8e879a6a9	1010
mbed_official	85:e1a8e879a6a9	1011	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	1012	/* ================ PPI ================ */
mbed_official	85:e1a8e879a6a9	1013	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	1014
mbed_official	85:e1a8e879a6a9	1015
mbed_official	85:e1a8e879a6a9	1016	/**
mbed_official	85:e1a8e879a6a9	1017	* @brief PPI controller. (PPI)
mbed_official	85:e1a8e879a6a9	1018	*/
mbed_official	85:e1a8e879a6a9	1019
mbed_official	85:e1a8e879a6a9	1020	typedef struct { /!< PPI Structure /
mbed_official	85:e1a8e879a6a9	1021	PPI_TASKS_CHG_Type TASKS_CHG[4]; /!< Channel group tasks. /
mbed_official	85:e1a8e879a6a9	1022	__I uint32_t RESERVED0[312];
mbed_official	85:e1a8e879a6a9	1023	__IO uint32_t CHEN; /!< Channel enable. /
mbed_official	85:e1a8e879a6a9	1024	__IO uint32_t CHENSET; /!< Channel enable set. /
mbed_official	85:e1a8e879a6a9	1025	__IO uint32_t CHENCLR; /!< Channel enable clear. /
mbed_official	85:e1a8e879a6a9	1026	__I uint32_t RESERVED1;
mbed_official	85:e1a8e879a6a9	1027	PPI_CH_Type CH[16]; /!< PPI Channel. /
mbed_official	85:e1a8e879a6a9	1028	__I uint32_t RESERVED2[156];
mbed_official	85:e1a8e879a6a9	1029	__IO uint32_t CHG[4]; /!< Channel group configuration. /
mbed_official	85:e1a8e879a6a9	1030	} NRF_PPI_Type;
mbed_official	85:e1a8e879a6a9	1031
mbed_official	85:e1a8e879a6a9	1032
mbed_official	85:e1a8e879a6a9	1033	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	1034	/* ================ FICR ================ */
mbed_official	85:e1a8e879a6a9	1035	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	1036
mbed_official	85:e1a8e879a6a9	1037
mbed_official	85:e1a8e879a6a9	1038	/**
mbed_official	85:e1a8e879a6a9	1039	* @brief Factory Information Configuration. (FICR)
mbed_official	85:e1a8e879a6a9	1040	*/
mbed_official	85:e1a8e879a6a9	1041
mbed_official	85:e1a8e879a6a9	1042	typedef struct { /!< FICR Structure /
mbed_official	85:e1a8e879a6a9	1043	__I uint32_t RESERVED0[4];
mbed_official	85:e1a8e879a6a9	1044	__I uint32_t CODEPAGESIZE; /!< Code memory page size in bytes. /
mbed_official	85:e1a8e879a6a9	1045	__I uint32_t CODESIZE; /!< Code memory size in pages. /
mbed_official	85:e1a8e879a6a9	1046	__I uint32_t RESERVED1[4];
mbed_official	85:e1a8e879a6a9	1047	__I uint32_t CLENR0; /!< Length of code region 0 in bytes. /
mbed_official	85:e1a8e879a6a9	1048	__I uint32_t PPFC; /!< Pre-programmed factory code present. /
mbed_official	85:e1a8e879a6a9	1049	__I uint32_t RESERVED2;
mbed_official	85:e1a8e879a6a9	1050	__I uint32_t NUMRAMBLOCK; /!< Number of individualy controllable RAM blocks. /
mbed_official	85:e1a8e879a6a9	1051	__I uint32_t SIZERAMBLOCK[4]; /!< Size of RAM block in bytes. /
mbed_official	85:e1a8e879a6a9	1052	__I uint32_t RESERVED3[5];
mbed_official	85:e1a8e879a6a9	1053	__I uint32_t CONFIGID; /!< Configuration identifier. /
mbed_official	85:e1a8e879a6a9	1054	__I uint32_t DEVICEID[2]; /!< Device identifier. /
mbed_official	85:e1a8e879a6a9	1055	__I uint32_t RESERVED4[6];
mbed_official	85:e1a8e879a6a9	1056	__I uint32_t ER[4]; /!< Encryption root. /
mbed_official	85:e1a8e879a6a9	1057	__I uint32_t IR[4]; /!< Identity root. /
mbed_official	85:e1a8e879a6a9	1058	__I uint32_t DEVICEADDRTYPE; /!< Device address type. /
mbed_official	85:e1a8e879a6a9	1059	__I uint32_t DEVICEADDR[2]; /!< Device address. /
mbed_official	85:e1a8e879a6a9	1060	__I uint32_t OVERRIDEEN; /!< Radio calibration override enable. /
mbed_official	85:e1a8e879a6a9	1061	__I uint32_t RESERVED5[15];
mbed_official	85:e1a8e879a6a9	1062	__I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
mbed_official	85:e1a8e879a6a9	1063	mode. */
mbed_official	85:e1a8e879a6a9	1064	} NRF_FICR_Type;
mbed_official	85:e1a8e879a6a9	1065
mbed_official	85:e1a8e879a6a9	1066
mbed_official	85:e1a8e879a6a9	1067	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	1068	/* ================ UICR ================ */
mbed_official	85:e1a8e879a6a9	1069	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	1070
mbed_official	85:e1a8e879a6a9	1071
mbed_official	85:e1a8e879a6a9	1072	/**
mbed_official	85:e1a8e879a6a9	1073	* @brief User Information Configuration. (UICR)
mbed_official	85:e1a8e879a6a9	1074	*/
mbed_official	85:e1a8e879a6a9	1075
mbed_official	85:e1a8e879a6a9	1076	typedef struct { /!< UICR Structure /
mbed_official	85:e1a8e879a6a9	1077	__IO uint32_t CLENR0; /!< Length of code region 0. /
mbed_official	85:e1a8e879a6a9	1078	__IO uint32_t RBPCONF; /!< Readback protection configuration. /
mbed_official	85:e1a8e879a6a9	1079	__IO uint32_t XTALFREQ; /!< Reset value for CLOCK XTALFREQ register. /
mbed_official	85:e1a8e879a6a9	1080	__I uint32_t RESERVED0;
mbed_official	85:e1a8e879a6a9	1081	__I uint32_t FWID; /!< Firmware ID. /
mbed_official	85:e1a8e879a6a9	1082	__IO uint32_t BOOTLOADERADDR; /!< Bootloader start address. /
mbed_official	85:e1a8e879a6a9	1083	} NRF_UICR_Type;
mbed_official	85:e1a8e879a6a9	1084
mbed_official	85:e1a8e879a6a9	1085
mbed_official	85:e1a8e879a6a9	1086	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	1087	/* ================ GPIO ================ */
mbed_official	85:e1a8e879a6a9	1088	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	1089
mbed_official	85:e1a8e879a6a9	1090
mbed_official	85:e1a8e879a6a9	1091	/**
mbed_official	85:e1a8e879a6a9	1092	* @brief General purpose input and output. (GPIO)
mbed_official	85:e1a8e879a6a9	1093	*/
mbed_official	85:e1a8e879a6a9	1094
mbed_official	85:e1a8e879a6a9	1095	typedef struct { /!< GPIO Structure /
mbed_official	85:e1a8e879a6a9	1096	__I uint32_t RESERVED0[321];
mbed_official	85:e1a8e879a6a9	1097	__IO uint32_t OUT; /!< Write GPIO port. /
mbed_official	85:e1a8e879a6a9	1098	__IO uint32_t OUTSET; /!< Set individual bits in GPIO port. /
mbed_official	85:e1a8e879a6a9	1099	__IO uint32_t OUTCLR; /!< Clear individual bits in GPIO port. /
mbed_official	85:e1a8e879a6a9	1100	__I uint32_t IN; /!< Read GPIO port. /
mbed_official	85:e1a8e879a6a9	1101	__IO uint32_t DIR; /!< Direction of GPIO pins. /
mbed_official	85:e1a8e879a6a9	1102	__IO uint32_t DIRSET; /!< DIR set register. /
mbed_official	85:e1a8e879a6a9	1103	__IO uint32_t DIRCLR; /!< DIR clear register. /
mbed_official	85:e1a8e879a6a9	1104	__I uint32_t RESERVED1[120];
mbed_official	85:e1a8e879a6a9	1105	__IO uint32_t PIN_CNF[32]; /!< Configuration of GPIO pins. /
mbed_official	85:e1a8e879a6a9	1106	} NRF_GPIO_Type;
mbed_official	85:e1a8e879a6a9	1107
mbed_official	85:e1a8e879a6a9	1108
mbed_official	85:e1a8e879a6a9	1109	/* -------------------- End of section using anonymous unions ------------------- */
mbed_official	85:e1a8e879a6a9	1110	#if defined(__CC_ARM)
mbed_official	85:e1a8e879a6a9	1111	#pragma pop
mbed_official	85:e1a8e879a6a9	1112	#elif defined(__ICCARM__)
mbed_official	85:e1a8e879a6a9	1113	/* leave anonymous unions enabled */
mbed_official	85:e1a8e879a6a9	1114	#elif defined(__GNUC__)
mbed_official	85:e1a8e879a6a9	1115	/* anonymous unions are enabled by default */
mbed_official	85:e1a8e879a6a9	1116	#elif defined(__TMS470__)
mbed_official	85:e1a8e879a6a9	1117	/* anonymous unions are enabled by default */
mbed_official	85:e1a8e879a6a9	1118	#elif defined(__TASKING__)
mbed_official	85:e1a8e879a6a9	1119	#pragma warning restore
mbed_official	85:e1a8e879a6a9	1120	#else
mbed_official	85:e1a8e879a6a9	1121	#warning Not supported compiler type
mbed_official	85:e1a8e879a6a9	1122	#endif
mbed_official	85:e1a8e879a6a9	1123
mbed_official	85:e1a8e879a6a9	1124
mbed_official	85:e1a8e879a6a9	1125
mbed_official	85:e1a8e879a6a9	1126
mbed_official	85:e1a8e879a6a9	1127	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	1128	/* ================ Peripheral memory map ================ */
mbed_official	85:e1a8e879a6a9	1129	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	1130
mbed_official	85:e1a8e879a6a9	1131	#define NRF_POWER_BASE 0x40000000UL
mbed_official	85:e1a8e879a6a9	1132	#define NRF_CLOCK_BASE 0x40000000UL
mbed_official	85:e1a8e879a6a9	1133	#define NRF_MPU_BASE 0x40000000UL
mbed_official	85:e1a8e879a6a9	1134	#define NRF_PU_BASE 0x40000000UL
mbed_official	85:e1a8e879a6a9	1135	#define NRF_AMLI_BASE 0x40000000UL
mbed_official	85:e1a8e879a6a9	1136	#define NRF_RADIO_BASE 0x40001000UL
mbed_official	85:e1a8e879a6a9	1137	#define NRF_UART0_BASE 0x40002000UL
mbed_official	85:e1a8e879a6a9	1138	#define NRF_SPI0_BASE 0x40003000UL
mbed_official	85:e1a8e879a6a9	1139	#define NRF_TWI0_BASE 0x40003000UL
mbed_official	85:e1a8e879a6a9	1140	#define NRF_SPI1_BASE 0x40004000UL
mbed_official	85:e1a8e879a6a9	1141	#define NRF_TWI1_BASE 0x40004000UL
mbed_official	85:e1a8e879a6a9	1142	#define NRF_SPIS1_BASE 0x40004000UL
mbed_official	85:e1a8e879a6a9	1143	#define NRF_GPIOTE_BASE 0x40006000UL
mbed_official	85:e1a8e879a6a9	1144	#define NRF_ADC_BASE 0x40007000UL
mbed_official	85:e1a8e879a6a9	1145	#define NRF_TIMER0_BASE 0x40008000UL
mbed_official	85:e1a8e879a6a9	1146	#define NRF_TIMER1_BASE 0x40009000UL
mbed_official	85:e1a8e879a6a9	1147	#define NRF_TIMER2_BASE 0x4000A000UL
mbed_official	85:e1a8e879a6a9	1148	#define NRF_RTC0_BASE 0x4000B000UL
mbed_official	85:e1a8e879a6a9	1149	#define NRF_TEMP_BASE 0x4000C000UL
mbed_official	85:e1a8e879a6a9	1150	#define NRF_RNG_BASE 0x4000D000UL
mbed_official	85:e1a8e879a6a9	1151	#define NRF_ECB_BASE 0x4000E000UL
mbed_official	85:e1a8e879a6a9	1152	#define NRF_AAR_BASE 0x4000F000UL
mbed_official	85:e1a8e879a6a9	1153	#define NRF_CCM_BASE 0x4000F000UL
mbed_official	85:e1a8e879a6a9	1154	#define NRF_WDT_BASE 0x40010000UL
mbed_official	85:e1a8e879a6a9	1155	#define NRF_RTC1_BASE 0x40011000UL
mbed_official	85:e1a8e879a6a9	1156	#define NRF_QDEC_BASE 0x40012000UL
mbed_official	85:e1a8e879a6a9	1157	#define NRF_LPCOMP_BASE 0x40013000UL
mbed_official	85:e1a8e879a6a9	1158	#define NRF_COMP_BASE 0x40013000UL
mbed_official	85:e1a8e879a6a9	1159	#define NRF_SWI_BASE 0x40014000UL
mbed_official	85:e1a8e879a6a9	1160	#define NRF_NVMC_BASE 0x4001E000UL
mbed_official	85:e1a8e879a6a9	1161	#define NRF_PPI_BASE 0x4001F000UL
mbed_official	85:e1a8e879a6a9	1162	#define NRF_FICR_BASE 0x10000000UL
mbed_official	85:e1a8e879a6a9	1163	#define NRF_UICR_BASE 0x10001000UL
mbed_official	85:e1a8e879a6a9	1164	#define NRF_GPIO_BASE 0x50000000UL
mbed_official	85:e1a8e879a6a9	1165
mbed_official	85:e1a8e879a6a9	1166
mbed_official	85:e1a8e879a6a9	1167	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	1168	/* ================ Peripheral declaration ================ */
mbed_official	85:e1a8e879a6a9	1169	/* ================================================================================ */
mbed_official	85:e1a8e879a6a9	1170
mbed_official	85:e1a8e879a6a9	1171	#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
mbed_official	85:e1a8e879a6a9	1172	#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
mbed_official	85:e1a8e879a6a9	1173	#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
mbed_official	85:e1a8e879a6a9	1174	#define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
mbed_official	85:e1a8e879a6a9	1175	#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
mbed_official	85:e1a8e879a6a9	1176	#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
mbed_official	85:e1a8e879a6a9	1177	#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
mbed_official	85:e1a8e879a6a9	1178	#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
mbed_official	85:e1a8e879a6a9	1179	#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
mbed_official	85:e1a8e879a6a9	1180	#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
mbed_official	85:e1a8e879a6a9	1181	#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
mbed_official	85:e1a8e879a6a9	1182	#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
mbed_official	85:e1a8e879a6a9	1183	#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
mbed_official	85:e1a8e879a6a9	1184	#define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
mbed_official	85:e1a8e879a6a9	1185	#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
mbed_official	85:e1a8e879a6a9	1186	#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
mbed_official	85:e1a8e879a6a9	1187	#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
mbed_official	85:e1a8e879a6a9	1188	#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
mbed_official	85:e1a8e879a6a9	1189	#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
mbed_official	85:e1a8e879a6a9	1190	#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
mbed_official	85:e1a8e879a6a9	1191	#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
mbed_official	85:e1a8e879a6a9	1192	#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
mbed_official	85:e1a8e879a6a9	1193	#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
mbed_official	85:e1a8e879a6a9	1194	#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
mbed_official	85:e1a8e879a6a9	1195	#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
mbed_official	85:e1a8e879a6a9	1196	#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
mbed_official	85:e1a8e879a6a9	1197	#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
mbed_official	85:e1a8e879a6a9	1198	#define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE)
mbed_official	85:e1a8e879a6a9	1199	#define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
mbed_official	85:e1a8e879a6a9	1200	#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
mbed_official	85:e1a8e879a6a9	1201	#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
mbed_official	85:e1a8e879a6a9	1202	#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
mbed_official	85:e1a8e879a6a9	1203	#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
mbed_official	85:e1a8e879a6a9	1204	#define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
mbed_official	85:e1a8e879a6a9	1205
mbed_official	85:e1a8e879a6a9	1206
mbed_official	85:e1a8e879a6a9	1207	/** @} / / End of group Device_Peripheral_Registers */
mbed_official	85:e1a8e879a6a9	1208	/** @} / / End of group nRF51 */
mbed_official	85:e1a8e879a6a9	1209	/** @} / / End of group Nordic Semiconductor */
mbed_official	85:e1a8e879a6a9	1210
mbed_official	85:e1a8e879a6a9	1211	#ifdef __cplusplus
mbed_official	85:e1a8e879a6a9	1212	}
mbed_official	85:e1a8e879a6a9	1213	#endif
mbed_official	85:e1a8e879a6a9	1214
mbed_official	85:e1a8e879a6a9	1215
mbed_official	85:e1a8e879a6a9	1216	#endif /* nRF51_H */

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Type:	Library
Created:	26 Nov 2015
Imports:	17
Forks:	0
Commits:	638
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51.h@433:73d4f6083dd2, 2014-12-10 (annotated)

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