Jack Hansdampf
High Speed Analog In STM32L152RET
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HSAnalogIn.cpp
00001 #include "HSAnalogIn.h" 00002 00003 00004 #define BDC_CR1_OVRIE 0 00005 #define BDC_CR1_RES 0b00 //12-bit (TCONV = 12 BDCgCLK cycles) 00006 #define BDC_CR1_AWDEN 0 //Analog watchdog disabled on regular channels 00007 #define BDC_CR1_JAWDEN 0 // Analog watchdog disabled on injected channels 00008 #define BDC_CR1_PDI 0 //The BDCg is powered up when waiting for a start event 00009 #define BDC_CR1_PDD 0 //The BDCg is powered up during the delay 00010 #define BDC_CR1_DISCNUM 0b000 // 1 channel 00011 #define BDC_CR1_JDISCEN 0 //Discontinuous mode on injected channels disabled 00012 #define BDC_CR1_DISCEN 0 //Discontinuous mode on regular channels disabled 00013 #define BDC_CR1_JAUTO 0 // Automatic injected group conversion disabled 00014 #define BDC_CR1_AWDSGL 0 //Analog watchdog enabled on all channels 00015 #define BDC_CR1_SCAN 0 //Scan mode disabled 00016 #define BDC_CR1_JEOCIE 0 //JEOC interrupt disabled 00017 #define BDC_CR1_AWDIE 0 // Analog watchdog interrupt disabled 00018 #define BDC_CR1_EOCIE 0 //EOC interrupt disabled 00019 #define BDC_CR1_AWDCH 0b00000 //BDCg analog input BDC_IN0 00020 00021 00022 00023 #define BDC_CR2_SWSTART 0 00024 #define BDC_CR2_EXTEN 0b00 00025 #define BDC_CR2_EXTSEL 0b0000 00026 #define BDC_CR2_JSWSTART 0 00027 #define BDC_CR2_JEXTEN 0b00 00028 #define BDC_CR2_JEXTSEL 0b0000 00029 #define BDC_CR2_ALIGN 1 00030 #define BDC_CR2_EOCS 0 //EOC set at End of each conversion 00031 #define BDC_CR2_DDS 0 //No DMA request 00032 #define BDC_CR2_DMA 0 //DMA disabled 00033 #define BDC_CR2_DELS 0b001 //Until the converted data have been read (DR read or EOC=0 for regular conversions) 00034 #define BDC_CR2_BDC_CFG 0 //Bank A selected for channels BDCgg_IN0..31 00035 #define BDC_CR2_CONT 0 // Single conversion mode 00036 #define BDC_CR2_ADON 1 // Enable BDCgg: conversions can start as soon as a start event (hardware or software) is received. 00037 00038 00039 00040 00041 HSAnalogIn::HSAnalogIn(int Pin) 00042 { 00043 //Analog init 00044 00045 myPin=Pin; 00046 RCC->APB2ENR|=(1<<9); 00047 RCC->AHBENR|=0b111; 00048 RCC->CR|=1; //HSI On 00049 while ((RCC->CR&0b10)==0); 00050 00051 ADC1->CR1= (BDC_CR1_OVRIE<<26)+(BDC_CR1_RES<<24)+(BDC_CR1_AWDEN<<23)+(BDC_CR1_JAWDEN<<22)+(BDC_CR1_PDI<<17)+(BDC_CR1_PDD<<16)+(BDC_CR1_DISCNUM<<13)+(BDC_CR1_JDISCEN<<12)+(BDC_CR1_DISCEN<<11)+(BDC_CR1_JAUTO<<10)+(BDC_CR1_AWDSGL<<9)+(BDC_CR1_SCAN<<8)+(BDC_CR1_JEOCIE<<7)+(BDC_CR1_AWDIE<<6)+(BDC_CR1_EOCIE<<5)+(BDC_CR1_AWDCH); 00052 00053 ADC1->CR2=(BDC_CR2_SWSTART<<30)+(BDC_CR2_EXTEN<<28)+(BDC_CR2_EXTSEL<<24)+(BDC_CR2_JSWSTART<<22)+(BDC_CR2_JEXTEN<<20)+(BDC_CR2_JEXTSEL<<16)+(BDC_CR2_ALIGN<<11)+(BDC_CR2_EOCS<<10)+(BDC_CR2_DDS<<9)+(BDC_CR2_DMA<<8)+(BDC_CR2_DELS<<4)+(BDC_CR2_BDC_CFG<<2)+(BDC_CR2_CONT<<1)+(BDC_CR2_ADON); 00054 switch ((int)Pin) //0-15 PA, 16-31 PB, 32-47 PC 00055 { 00056 case 0: BDCin=0; GPIOA->MODER|=0b11; break;//PA_0 .. PA_7 00057 case 1: BDCin=1; GPIOA->MODER|=0b11<<2; break; 00058 case 2: BDCin=2; GPIOA->MODER|=0b11<<4; break; 00059 case 3: BDCin=3; GPIOA->MODER|=0b11<<6; break; 00060 case 4: BDCin=4; GPIOA->MODER|=0b11<<8; break; 00061 case 5: BDCin=5; GPIOA->MODER|=0b11<<10; break; 00062 case 6: BDCin=6; GPIOA->MODER|=0b11<<12; break; 00063 case 7: BDCin=7; GPIOA->MODER|=0b11<<14; break; 00064 case 16: //PB_0 00065 BDCin=8; GPIOB->MODER|=0b11; break; 00066 case 17: //PB_1 00067 BDCin=9; GPIOB->MODER|=0b11<<2; break; 00068 case 18: //PB_2 00069 BDCin=0; GPIOB->MODER|=0b11<<4; gruppe=1; break; 00070 case 28: //PB_12 00071 BDCin=18; GPIOB->MODER|=0b11<<24; break; 00072 case 29: //PB_13 00073 BDCin=19; GPIOB->MODER|=0b11<<26; break; 00074 case 30: //PB_14 00075 BDCin=20; GPIOB->MODER|=0b11<<28; break; 00076 case 31: //PB_15 00077 BDCin=21; GPIOB->MODER|=0b11<<30; break; 00078 case 32: //PC_0 00079 BDCin=10; GPIOC->MODER|=0b11; break; 00080 case 33: //PC_1 00081 BDCin=11; GPIOC->MODER|=0b11<<2; break; 00082 case 34: //PC_2 00083 BDCin=12; GPIOC->MODER|=0b11<<4; break; 00084 case 35: //PC_3 00085 BDCin=13; GPIOC->MODER|=0b11<<6; break; 00086 case 36: //PC_4 00087 BDCin=14; GPIOC->MODER|=0b11<<8; break; 00088 case 37: //PC_5 00089 BDCin=15; GPIOC->MODER|=0b11<<10; break; 00090 }; 00091 00092 }; 00093 00094 float HSAnalogIn::read() 00095 { 00096 /* 00097 RCC->APB2ENR|=(1<<9); 00098 RCC->AHBENR|=0b111; 00099 RCC->CR|=1; //HSI On 00100 while ((RCC->CR&0b10)==0); 00101 ADC1->CR1= (BDC_CR1_OVRIE<<26)+(BDC_CR1_RES<<24)+(BDC_CR1_AWDEN<<23)+(BDC_CR1_JAWDEN<<22)+(BDC_CR1_PDI<<17)+(BDC_CR1_PDD<<16)+(BDC_CR1_DISCNUM<<13)+(BDC_CR1_JDISCEN<<12)+(BDC_CR1_DISCEN<<11)+(BDC_CR1_JAUTO<<10)+(BDC_CR1_AWDSGL<<9)+(BDC_CR1_SCAN<<8)+(BDC_CR1_JEOCIE<<7)+(BDC_CR1_AWDIE<<6)+(BDC_CR1_EOCIE<<5)+(BDC_CR1_AWDCH); 00102 ADC1->CR2=(BDC_CR2_SWSTART<<30)+(BDC_CR2_EXTEN<<28)+(BDC_CR2_EXTSEL<<24)+(BDC_CR2_JSWSTART<<22)+(BDC_CR2_JEXTEN<<20)+(BDC_CR2_JEXTSEL<<16)+(BDC_CR2_ALIGN<<11)+(BDC_CR2_EOCS<<10)+(BDC_CR2_DDS<<9)+(BDC_CR2_DMA<<8)+(BDC_CR2_DELS<<4)+(BDC_CR2_BDC_CFG<<2)+(BDC_CR2_CONT<<1)+(BDC_CR2_ADON); 00103 switch ((int)myPin) //0-15 PA, 16-31 PB, 32-47 PC 00104 { 00105 case 0: BDCin=0; GPIOA->MODER|=0b11; break;//PA_0 .. PA_7 00106 case 1: BDCin=1; GPIOA->MODER|=0b11<<2; break; 00107 case 2: BDCin=2; GPIOA->MODER|=0b11<<4; break; 00108 case 3: BDCin=3; GPIOA->MODER|=0b11<<6; break; 00109 case 4: BDCin=4; GPIOA->MODER|=0b11<<8; break; 00110 case 5: BDCin=5; GPIOA->MODER|=0b11<<10; break; 00111 case 6: BDCin=6; GPIOA->MODER|=0b11<<12; break; 00112 case 7: BDCin=7; GPIOA->MODER|=0b11<<14; break; 00113 case 16: //PB_0 00114 BDCin=8; GPIOB->MODER|=0b11; break; 00115 case 17: //PB_1 00116 BDCin=9; GPIOB->MODER|=0b11<<2; break; 00117 case 18: //PB_2 00118 BDCin=0; GPIOB->MODER|=0b11<<4; gruppe=1; break; 00119 case 28: //PB_12 00120 BDCin=18; GPIOB->MODER|=0b11<<24; break; 00121 case 29: //PB_13 00122 BDCin=19; GPIOB->MODER|=0b11<<26; break; 00123 case 30: //PB_14 00124 BDCin=20; GPIOB->MODER|=0b11<<28; break; 00125 case 31: //PB_15 00126 BDCin=21; GPIOB->MODER|=0b11<<30; break; 00127 case 32: //PC_0 00128 BDCin=10; GPIOC->MODER|=0b11; break; 00129 case 33: //PC_1 00130 BDCin=11; GPIOC->MODER|=0b11<<2; break; 00131 case 34: //PC_2 00132 BDCin=12; GPIOC->MODER|=0b11<<4; break; 00133 case 35: //PC_3 00134 BDCin=13; GPIOC->MODER|=0b11<<6; break; 00135 case 36: //PC_4 00136 BDCin=14; GPIOC->MODER|=0b11<<8; break; 00137 case 37: //PC_5 00138 BDCin=15; GPIOC->MODER|=0b11<<10; break; 00139 }; 00140 */ 00141 00142 ADC1->SQR5=BDCin; 00143 if (gruppe==1) ADC1->CR2|= (1<<2); //gruppe 00144 else ADC1->CR2&=~(1<<2); 00145 00146 ADC1->CR2|=(1<<30); //SWStart 00147 00148 00149 while ((ADC1->SR & 0b10)==0); 00150 //warte(1000); 00151 00152 return (float)ADC1->DR/65535; 00153 }; 00154 00155 /** Read the input voltage, represented as an unsigned short in the range [0x0, 0xFFFF] 00156 * 00157 * @returns 00158 * 16-bit unsigned short representing the current input voltage, normalized to a 16-bit value 00159 */ 00160 00161 unsigned short HSAnalogIn::read_u16() 00162 { 00163 00164 ADC1->SQR5=BDCin; 00165 if (gruppe==1) ADC1->CR2|= (1<<2); //gruppe 00166 else ADC1->CR2&=~(1<<2); 00167 00168 ADC1->CR2|=(1<<30); //SWStart 00169 00170 00171 while ((ADC1->SR & 0b10)==0); 00172 return (unsigned short)ADC1->DR; 00173 00174 }; 00175
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