ard2pmod.cpp

00001 /******************************************************************//**
00002 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
00003 *
00004 * Permission is hereby granted, free of charge, to any person obtaining a
00005 * copy of this software and associated documentation files (the "Software"),
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00009 * Software is furnished to do so, subject to the following conditions:
00010 *
00011 * The above copyright notice and this permission notice shall be included
00012 * in all copies or substantial portions of the Software.
00013 *
00014 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
00015 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
00016 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
00017 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
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00019 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
00020 * OTHER DEALINGS IN THE SOFTWARE.
00021 *
00022 * Except as contained in this notice, the name of Maxim Integrated
00023 * Products, Inc. shall not be used except as stated in the Maxim Integrated
00024 * Products, Inc. Branding Policy.
00025 *
00026 * The mere transfer of this software does not imply any licenses
00027 * of trade secrets, proprietary technology, copyrights, patents,
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00031 **********************************************************************/
00032 
00033 
00034 #include "ard2pmod.h"
00035 
00036 
00037 //*********************************************************************
00038 Ard2Pmod::Ard2Pmod(PmodType pmod_type, PinName ow_pin): 
00039 _mux(D14, D15, Max14661::MAX14661_I2C_ADRS0)
00040 {
00041     switch(pmod_type)
00042     {
00043         case PMOD_TYPE_I2C_A:
00044             _mux.set_switches((Max14661::SW12 | Max14661::SW09), (Max14661::SW11 | Max14661::SW10));
00045         break;
00046             
00047         case PMOD_TYPE_I2C_B:
00048             _mux.set_switches((Max14661::SW09 | Max14661::SW07), (Max14661::SW10 | Max14661::SW08));
00049         break;
00050             
00051         case PMOD_TYPE_I2C_AB:
00052             _mux.set_switches((Max14661::SW12 | Max14661::SW09 | Max14661::SW07), (Max14661::SW11 | Max14661::SW10 | Max14661::SW08));
00053         break;
00054             
00055         case PMOD_TYPE_1_GPIO:
00056             _mux.wrt_cmd_registers(Max14661::DISABLE_BANK, Max14661::DISABLE_BANK);
00057         break;
00058             
00059         case PMOD_TYPE_2_SPI:
00060             _mux.wrt_cmd_registers(Max14661::DISABLE_BANK, Max14661::DISABLE_BANK);
00061         break;
00062             
00063         case PMOD_TYPE_3_UART:
00064             _mux.set_switches((Max14661::SW12 | Max14661::SW01), (Max14661::SW11 | Max14661::SW02));
00065         break;
00066             
00067         case PMOD_TYPE_4_UART:
00068             _mux.set_switches((Max14661::SW13 | Max14661::SW02), (Max14661::SW12 | Max14661::SW01));
00069             break;
00070             
00071         case PMOD_TYPE_5_HBRIDGE:
00072             _mux.wrt_cmd_registers(Max14661::DISABLE_BANK, Max14661::DISABLE_BANK);
00073         break;
00074             
00075         case PMOD_TYPE_6_HBRIDGE:
00076             _mux.wrt_cmd_registers(Max14661::DISABLE_BANK, Max14661::DISABLE_BANK);
00077         break;
00078             
00079         case PMOD_TYPE_7_ONEWIRE_A:
00080         
00081             //set switches for owm_A
00082             switch(ow_pin)
00083             {
00084                 case D0:
00085                     _mux.set_switches((Max14661::SW01 | Max14661::SW11), 0);
00086                 break;
00087                 
00088                 case D1:
00089                     _mux.set_switches((Max14661::SW02 | Max14661::SW11), 0);
00090                 break;
00091                 
00092                 case D2:
00093                     _mux.set_switches((Max14661::SW03 | Max14661::SW11), 0);
00094                 break;
00095                 
00096                 case D3:
00097                     _mux.set_switches((Max14661::SW04 | Max14661::SW11), 0);
00098                 break;
00099                 
00100                 case D4:
00101                     _mux.set_switches((Max14661::SW05 | Max14661::SW11), 0);
00102                 break;
00103                 
00104                 case D5:
00105                     _mux.set_switches((Max14661::SW06 | Max14661::SW11), 0);
00106                 break;
00107                 
00108                 case D6:
00109                     _mux.set_switches((Max14661::SW07 | Max14661::SW11), 0);
00110                 break;
00111                 
00112                 case D7:
00113                     _mux.set_switches((Max14661::SW08 | Max14661::SW11), 0);
00114                 break;
00115                 
00116                 case D8:
00117                     _mux.set_switches((Max14661::SW16 | Max14661::SW11), 0);
00118                 break;
00119                 
00120                 case D9:
00121                     _mux.set_switches((Max14661::SW15 | Max14661::SW11), 0);
00122                 break;
00123                 
00124                 case D10:
00125                     _mux.set_switches((Max14661::SW14 | Max14661::SW11), 0);
00126                 break;
00127                 
00128                 case D11:
00129                     _mux.set_switches((Max14661::SW13 | Max14661::SW11), 0);
00130                 break;
00131                 
00132                 case D12:
00133                     _mux.set_switches((Max14661::SW12 | Max14661::SW11), 0);
00134                 break;
00135                 
00136                 default:
00137                     _mux.wrt_cmd_registers(Max14661::DISABLE_BANK, Max14661::DISABLE_BANK);
00138                 break;
00139             }  
00140             
00141         break;
00142             
00143         case PMOD_TYPE_8_ONEWIRE_B:
00144             
00145             //set switches for owm_B
00146             switch(ow_pin)
00147             {
00148                 case D0:
00149                     _mux.set_switches(0, (Max14661::SW01 | Max14661::SW08));
00150                 break;
00151                 
00152                 case D1:
00153                     _mux.set_switches(0, (Max14661::SW02 | Max14661::SW08));
00154                 break;
00155                 
00156                 case D2:
00157                     _mux.set_switches(0, (Max14661::SW03 | Max14661::SW08));
00158                 break;
00159                 
00160                 case D3:
00161                     _mux.set_switches(0, (Max14661::SW04 | Max14661::SW08));
00162                 break;
00163                 
00164                 case D4:
00165                     _mux.set_switches(0, (Max14661::SW05 | Max14661::SW08));
00166                 break;
00167                 
00168                 case D5:
00169                     _mux.set_switches(0, (Max14661::SW06 | Max14661::SW08));
00170                 break;
00171                 
00172                 case D6:
00173                     _mux.set_switches(0, (Max14661::SW07 | Max14661::SW08));
00174                 break;
00175                 
00176                 case D7:
00177                     _mux.wrt_cmd_registers(Max14661::DISABLE_BANK, Max14661::DISABLE_BANK);
00178                 break;
00179                 
00180                 case D8:
00181                     _mux.set_switches(0, (Max14661::SW16 | Max14661::SW08));
00182                 break;
00183                 
00184                 case D9:
00185                     _mux.set_switches(0, (Max14661::SW15 | Max14661::SW08));
00186                 break;
00187                 
00188                 case D10:
00189                     _mux.set_switches(0, (Max14661::SW14 | Max14661::SW08));
00190                 break;
00191                 
00192                 case D11:
00193                     _mux.set_switches(0, (Max14661::SW13 | Max14661::SW08));
00194                 break;
00195                 
00196                 case D12:
00197                     _mux.set_switches(0, (Max14661::SW12 | Max14661::SW08));
00198                 break;
00199                 
00200                 case D13:
00201                     _mux.set_switches(0, (Max14661::SW11 | Max14661::SW08));
00202                 break;
00203                 
00204                 default:
00205                     _mux.wrt_cmd_registers(Max14661::DISABLE_BANK, Max14661::DISABLE_BANK);
00206                 break;
00207             } 
00208             
00209         break;
00210             
00211         default:
00212             _mux.wrt_cmd_registers(Max14661::DISABLE_BANK, Max14661::DISABLE_BANK);
00213         break;
00214     } 
00215 }
00216 
00217