Ivo Noorhoff / UIPEthernet

Fork for fixes

utility/Enc28j60Eth.cpp@22:a0b1d0e6d237, 2020-09-26 (annotated)

Committer:
ivo_n
Date:
Sat Sep 26 08:31:41 2020 +0000
Revision:
22:a0b1d0e6d237
Parent:
19:58e840279555 
Everything seems to work

Who changed what in which revision?

UserRevisionLine numberNew contents of line
hudakz 9:a156d3de5647 1 /*
hudakz 9:a156d3de5647 2 Enc28J60Network.cpp
hudakz 9:a156d3de5647 3 UIPEthernet network driver for Microchip ENC28J60 Ethernet Interface.
hudakz 9:a156d3de5647 4
hudakz 9:a156d3de5647 5 Copyright (c) 2013 Norbert Truchsess <norbert.truchsess@t-online.de>
hudakz 9:a156d3de5647 6 All rights reserved.
hudakz 9:a156d3de5647 7
hudakz 9:a156d3de5647 8 based on enc28j60.c file from the AVRlib library by Pascal Stang.
hudakz 9:a156d3de5647 9 For AVRlib See http://www.procyonengineering.com/
hudakz 9:a156d3de5647 10
hudakz 9:a156d3de5647 11 Modified (ported to mbed) by Zoltan Hudak <hudakz@inbox.com>
hudakz 9:a156d3de5647 12
hudakz 9:a156d3de5647 13 This program is free software: you can redistribute it and/or modify
hudakz 9:a156d3de5647 14 it under the terms of the GNU General Public License as published by
hudakz 9:a156d3de5647 15 the Free Software Foundation, either version 3 of the License, or
hudakz 9:a156d3de5647 16 (at your option) any later version.
hudakz 9:a156d3de5647 17
hudakz 9:a156d3de5647 18 This program is distributed in the hope that it will be useful,
hudakz 9:a156d3de5647 19 but WITHOUT ANY WARRANTY; without even the implied warranty of
hudakz 9:a156d3de5647 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
hudakz 9:a156d3de5647 21 GNU General Public License for more details.
hudakz 9:a156d3de5647 22
hudakz 9:a156d3de5647 23 You should have received a copy of the GNU General Public License
hudakz 9:a156d3de5647 24 along with this program. If not, see <http://www.gnu.org/licenses/>.
hudakz 9:a156d3de5647 25 */
hudakz 11:647d53d146f1 26 #include "Enc28j60Eth.h"
hudakz 9:a156d3de5647 27 #include "mbed.h"
hudakz 16:269f652b4d0b 28 #include "mbed_version.h"
hudakz 9:a156d3de5647 29
hudakz 9:a156d3de5647 30 extern "C"
hudakz 9:a156d3de5647 31 {
hudakz 9:a156d3de5647 32 #include "enc28j60.h"
hudakz 9:a156d3de5647 33 #include "uip.h"
hudakz 9:a156d3de5647 34 }
hudakz 9:a156d3de5647 35
hudakz 9:a156d3de5647 36 // Static member initialization
hudakz 11:647d53d146f1 37 uint16_t Enc28j60Eth::nextPacketPtr;
hudakz 11:647d53d146f1 38 uint8_t Enc28j60Eth::bank = 0xff;
hudakz 11:647d53d146f1 39 struct memblock Enc28j60Eth::receivePkt;
hudakz 9:a156d3de5647 40
hudakz 9:a156d3de5647 41 /**
hudakz 9:a156d3de5647 42 * @brief
hudakz 9:a156d3de5647 43 * @note
hudakz 9:a156d3de5647 44 * @param
hudakz 9:a156d3de5647 45 * @retval
hudakz 9:a156d3de5647 46 */
hudakz 11:647d53d146f1 47 Enc28j60Eth::Enc28j60Eth(PinName mosi, PinName miso, PinName sclk, PinName cs) :
hudakz 9:a156d3de5647 48 MemPool(),
hudakz 9:a156d3de5647 49 _spi(mosi, miso, sclk),
hudakz 9:a156d3de5647 50 _cs(cs)
hudakz 9:a156d3de5647 51 { }
hudakz 9:a156d3de5647 52
hudakz 9:a156d3de5647 53 /**
hudakz 9:a156d3de5647 54 * @brief
hudakz 9:a156d3de5647 55 * @note
hudakz 9:a156d3de5647 56 * @param
hudakz 9:a156d3de5647 57 * @retval
hudakz 9:a156d3de5647 58 */
hudakz 11:647d53d146f1 59 void Enc28j60Eth::init(uint8_t* macaddr)
hudakz 9:a156d3de5647 60 {
hudakz 15:53715cc81c63 61 MemPool::init(); // 1 byte in between RX_STOP_INIT and pool to allow prepending of controlbyte
hudakz 15:53715cc81c63 62
hudakz 9:a156d3de5647 63 // initialize SPI interface
hudakz 15:53715cc81c63 64 _cs = 1;
hudakz 9:a156d3de5647 65 _spi.format(8, 0); // 8-bit, mode 0
hudakz 15:53715cc81c63 66 _spi.frequency(10000000); // 10 Mbit/s
hudakz 16:269f652b4d0b 67 #if MBED_MAJOR_VERSION == 2
hudakz 16:269f652b4d0b 68 wait_ms(100);
hudakz 16:269f652b4d0b 69 #else
hudakz 16:269f652b4d0b 70 thread_sleep_for(100);
hudakz 16:269f652b4d0b 71 #endif
hudakz 9:a156d3de5647 72
hudakz 9:a156d3de5647 73 // perform system reset
hudakz 9:a156d3de5647 74 writeOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
hudakz 9:a156d3de5647 75
hudakz 9:a156d3de5647 76 // check CLKRDY bit to see if reset is complete
hudakz 15:53715cc81c63 77 // while(!(readReg(ESTAT) & ESTAT_CLKRDY));
hudakz 15:53715cc81c63 78 // The CLKRDY does not work. See Rev. B4 Silicon Errata point.
hudakz 15:53715cc81c63 79 // Just wait.
hudakz 16:269f652b4d0b 80 #if MBED_MAJOR_VERSION == 2
hudakz 9:a156d3de5647 81 wait_ms(50);
hudakz 16:269f652b4d0b 82 #else
hudakz 16:269f652b4d0b 83 thread_sleep_for(50);
hudakz 16:269f652b4d0b 84 #endif
hudakz 9:a156d3de5647 85
hudakz 9:a156d3de5647 86 // do bank 0 stuff
hudakz 9:a156d3de5647 87 // initialize receive buffer
hudakz 9:a156d3de5647 88 // 16-bit transfers, must write low byte first
hudakz 9:a156d3de5647 89 // set receive buffer start address
hudakz 9:a156d3de5647 90 nextPacketPtr = RXSTART_INIT;
hudakz 9:a156d3de5647 91
hudakz 9:a156d3de5647 92 // Rx start
hudakz 9:a156d3de5647 93 writeRegPair(ERXSTL, RXSTART_INIT);
hudakz 9:a156d3de5647 94
hudakz 9:a156d3de5647 95 // set receive pointer address
hudakz 9:a156d3de5647 96 writeRegPair(ERXRDPTL, RXSTART_INIT);
hudakz 9:a156d3de5647 97
hudakz 9:a156d3de5647 98 // RX end
hudakz 11:647d53d146f1 99 writeRegPair(ERXNDL, RXEND_INIT);
hudakz 9:a156d3de5647 100
hudakz 11:647d53d146f1 101 //All memory which is not used by the receive buffer is considered the transmission buffer.
hudakz 11:647d53d146f1 102 // No explicit action is required to initialize the transmission buffer.
hudakz 9:a156d3de5647 103 // TX start
hudakz 9:a156d3de5647 104 //writeRegPair(ETXSTL, TXSTART_INIT);
hudakz 9:a156d3de5647 105 // TX end
hudakz 11:647d53d146f1 106 //writeRegPair(ETXNDL, TXEND_INIT);
hudakz 15:53715cc81c63 107 // However, he host controller should leave at least seven bytes between each
hudakz 15:53715cc81c63 108 // packet and the beginning of the receive buffer.
hudakz 11:647d53d146f1 109
hudakz 9:a156d3de5647 110 // do bank 1 stuff, packet filter:
hudakz 9:a156d3de5647 111 // For broadcast packets we allow only ARP packtets
hudakz 9:a156d3de5647 112 // All other packets should be unicast only for our mac (MAADR)
hudakz 9:a156d3de5647 113 //
hudakz 15:53715cc81c63 114 // The pattern to match is therefore
hudakz 9:a156d3de5647 115 // Type ETH.DST
hudakz 9:a156d3de5647 116 // ARP BROADCAST
hudakz 9:a156d3de5647 117 // 06 08 -- ff ff ff ff ff ff -> ip checksum for theses bytes=f7f9
hudakz 9:a156d3de5647 118 // in binary these poitions are:11 0000 0011 1111
hudakz 9:a156d3de5647 119 // This is hex 303F->EPMM0=0x3f,EPMM1=0x30
hudakz 9:a156d3de5647 120 //TODO define specific pattern to receive dhcp-broadcast packages instead of setting ERFCON_BCEN!
hudakz 9:a156d3de5647 121 writeReg(ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_PMEN | ERXFCON_BCEN);
hudakz 9:a156d3de5647 122 writeRegPair(EPMM0, 0x303f);
hudakz 9:a156d3de5647 123 writeRegPair(EPMCSL, 0xf7f9);
hudakz 9:a156d3de5647 124
hudakz 9:a156d3de5647 125 //
hudakz 9:a156d3de5647 126 //
hudakz 11:647d53d146f1 127 // do bank 2 stuff,
hudakz 9:a156d3de5647 128 // enable MAC receive
hudakz 9:a156d3de5647 129 // and bring MAC out of reset (writes 0x00 to MACON2)
hudakz 9:a156d3de5647 130 writeRegPair(MACON1, MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
hudakz 9:a156d3de5647 131
hudakz 9:a156d3de5647 132 // enable automatic padding to 60bytes and CRC operations
hudakz 9:a156d3de5647 133 writeOp(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN);
hudakz 9:a156d3de5647 134
hudakz 9:a156d3de5647 135 // set inter-frame gap (non-back-to-back)
hudakz 9:a156d3de5647 136 writeRegPair(MAIPGL, 0x0C12);
hudakz 9:a156d3de5647 137
hudakz 9:a156d3de5647 138 // set inter-frame gap (back-to-back)
hudakz 9:a156d3de5647 139 writeReg(MABBIPG, 0x12);
hudakz 9:a156d3de5647 140
hudakz 9:a156d3de5647 141 // Set the maximum packet size which the controller will accept
hudakz 9:a156d3de5647 142 // Do not send packets longer than MAX_FRAMELEN:
hudakz 9:a156d3de5647 143 writeRegPair(MAMXFLL, MAX_FRAMELEN);
hudakz 9:a156d3de5647 144
hudakz 9:a156d3de5647 145 // do bank 3 stuff
hudakz 9:a156d3de5647 146 // write MAC address
hudakz 9:a156d3de5647 147 // NOTE: MAC address in ENC28J60 is byte-backward
hudakz 9:a156d3de5647 148 writeReg(MAADR5, macaddr[0]);
hudakz 9:a156d3de5647 149 writeReg(MAADR4, macaddr[1]);
hudakz 9:a156d3de5647 150 writeReg(MAADR3, macaddr[2]);
hudakz 9:a156d3de5647 151 writeReg(MAADR2, macaddr[3]);
hudakz 9:a156d3de5647 152 writeReg(MAADR1, macaddr[4]);
hudakz 9:a156d3de5647 153 writeReg(MAADR0, macaddr[5]);
hudakz 9:a156d3de5647 154
hudakz 9:a156d3de5647 155 // no loopback of transmitted frames
hudakz 9:a156d3de5647 156 phyWrite(PHCON2, PHCON2_HDLDIS);
hudakz 9:a156d3de5647 157
hudakz 9:a156d3de5647 158 // switch to bank 0
hudakz 9:a156d3de5647 159 setBank(ECON1);
hudakz 9:a156d3de5647 160
hudakz 9:a156d3de5647 161 // enable interrutps
hudakz 9:a156d3de5647 162 writeOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE | EIE_PKTIE);
hudakz 9:a156d3de5647 163
hudakz 9:a156d3de5647 164 // enable packet reception
hudakz 9:a156d3de5647 165 writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
hudakz 9:a156d3de5647 166
hudakz 9:a156d3de5647 167 //Configure leds
hudakz 9:a156d3de5647 168 phyWrite(PHLCON, 0x476);
hudakz 9:a156d3de5647 169 }
hudakz 9:a156d3de5647 170
hudakz 9:a156d3de5647 171 /**
hudakz 9:a156d3de5647 172 * @brief
hudakz 9:a156d3de5647 173 * @note
hudakz 9:a156d3de5647 174 * @param
hudakz 9:a156d3de5647 175 * @retval
hudakz 9:a156d3de5647 176 */
hudakz 11:647d53d146f1 177 memhandle Enc28j60Eth::receivePacket()
hudakz 9:a156d3de5647 178 {
hudakz 9:a156d3de5647 179 uint8_t rxstat;
hudakz 9:a156d3de5647 180 uint16_t len;
hudakz 9:a156d3de5647 181 // check if a packet has been received and buffered
hudakz 9:a156d3de5647 182 //if( !(readReg(EIR) & EIR_PKTIF) ){
hudakz 9:a156d3de5647 183 // The above does not work. See Rev. B4 Silicon Errata point 6.
hudakz 9:a156d3de5647 184 if (readReg(EPKTCNT) != 0) {
ivo_n 19:58e840279555 185 uint16_t readPtr = (nextPacketPtr +
ivo_n 19:58e840279555 186 6 > RXEND_INIT) ? (nextPacketPtr +
hudakz 9:a156d3de5647 187 6 -
hudakz 11:647d53d146f1 188 RXEND_INIT +
ivo_n 19:58e840279555 189 RXSTART_INIT) : (nextPacketPtr +
ivo_n 19:58e840279555 190 6);
hudakz 9:a156d3de5647 191 // Set the read pointer to the start of the received packet
hudakz 9:a156d3de5647 192 writeRegPair(ERDPTL, nextPacketPtr);
hudakz 9:a156d3de5647 193
hudakz 9:a156d3de5647 194 // read the next packet pointer
hudakz 9:a156d3de5647 195 nextPacketPtr = readOp(ENC28J60_READ_BUF_MEM, 0);
hudakz 9:a156d3de5647 196 nextPacketPtr |= readOp(ENC28J60_READ_BUF_MEM, 0) << 8;
hudakz 9:a156d3de5647 197
hudakz 9:a156d3de5647 198 // read the packet length (see datasheet page 43)
hudakz 9:a156d3de5647 199 len = readOp(ENC28J60_READ_BUF_MEM, 0);
hudakz 9:a156d3de5647 200 len |= readOp(ENC28J60_READ_BUF_MEM, 0) << 8;
hudakz 9:a156d3de5647 201 len -= 4; //remove the CRC count
hudakz 9:a156d3de5647 202 // read the receive status (see datasheet page 43)
hudakz 9:a156d3de5647 203 rxstat = readOp(ENC28J60_READ_BUF_MEM, 0);
hudakz 9:a156d3de5647 204
hudakz 9:a156d3de5647 205 //rxstat |= readOp(ENC28J60_READ_BUF_MEM, 0) << 8;
hudakz 9:a156d3de5647 206 #ifdef ENC28J60DEBUG
ivo_n 19:58e840279555 207 uint16_t start = readPtr;
ivo_n 19:58e840279555 208 uint16_t end = start + len -1; //todo: why -1 ?
ivo_n 19:58e840279555 209
hudakz 9:a156d3de5647 210 printf
hudakz 9:a156d3de5647 211 (
ivo_n 19:58e840279555 212 "receivePacket [%d-%d] (%d) (%d), next: %d, stat: %d, count: %d -> ",
hudakz 9:a156d3de5647 213 readPtr,
ivo_n 19:58e840279555 214 (readPtr + len),
ivo_n 19:58e840279555 215 len,
ivo_n 19:58e840279555 216 (readPtr + len) % (RXEND_INIT + 1), // todo: what is RXEND_INIT ?
hudakz 9:a156d3de5647 217 nextPacketPtr,
hudakz 9:a156d3de5647 218 rxstat,
hudakz 9:a156d3de5647 219 readReg(EPKTCNT)
hudakz 9:a156d3de5647 220 );
hudakz 9:a156d3de5647 221 (rxstat & 0x80) != 0 ? printf("OK") : printf("failed");
ivo_n 19:58e840279555 222
ivo_n 19:58e840279555 223 printf("\r\n");
ivo_n 19:58e840279555 224
ivo_n 19:58e840279555 225 int j = 1;
ivo_n 19:58e840279555 226 for (uint16_t i = start; i < end; i++) {
ivo_n 19:58e840279555 227 printf("%02x ", readByte(i));
ivo_n 19:58e840279555 228 if (j%8==0) printf(" ");
ivo_n 19:58e840279555 229 if (j%16==0) printf("\r\n");
ivo_n 19:58e840279555 230 j++;
ivo_n 19:58e840279555 231 }
ivo_n 19:58e840279555 232
hudakz 9:a156d3de5647 233 printf("\r\n");
hudakz 9:a156d3de5647 234 #endif
hudakz 9:a156d3de5647 235 // decrement the packet counter indicate we are done with this packet
hudakz 9:a156d3de5647 236
hudakz 9:a156d3de5647 237 writeOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC);
hudakz 9:a156d3de5647 238
hudakz 9:a156d3de5647 239 // check CRC and symbol errors (see datasheet page 44, table 7-3):
hudakz 9:a156d3de5647 240 // The ERXFCON.CRCEN is set by default. Normally we should not
hudakz 9:a156d3de5647 241 // need to check this.
hudakz 9:a156d3de5647 242 if ((rxstat & 0x80) != 0) {
hudakz 9:a156d3de5647 243 receivePkt.begin = readPtr;
hudakz 9:a156d3de5647 244 receivePkt.size = len;
hudakz 9:a156d3de5647 245 return UIP_RECEIVEBUFFERHANDLE;
hudakz 9:a156d3de5647 246 }
hudakz 9:a156d3de5647 247
hudakz 9:a156d3de5647 248 // Move the RX read pointer to the start of the next received packet
hudakz 9:a156d3de5647 249 // This frees the memory we just read out
hudakz 9:a156d3de5647 250 setERXRDPT();
hudakz 9:a156d3de5647 251 }
hudakz 9:a156d3de5647 252
hudakz 9:a156d3de5647 253 return(NOBLOCK);
hudakz 9:a156d3de5647 254 }
hudakz 9:a156d3de5647 255
hudakz 9:a156d3de5647 256 /**
hudakz 9:a156d3de5647 257 * @brief
hudakz 9:a156d3de5647 258 * @note
hudakz 9:a156d3de5647 259 * @param
hudakz 9:a156d3de5647 260 * @retval
hudakz 9:a156d3de5647 261 */
hudakz 11:647d53d146f1 262 void Enc28j60Eth::setERXRDPT()
hudakz 9:a156d3de5647 263 {
ivo_n 19:58e840279555 264 uint16_t tmp = (nextPacketPtr == RXSTART_INIT) ? RXEND_INIT : nextPacketPtr - 1;
ivo_n 19:58e840279555 265
ivo_n 19:58e840279555 266 #ifdef ENC28J60DEBUG
ivo_n 19:58e840279555 267 printf("setERXRDPT set %d start %d end %d \r\n",tmp,RXSTART_INIT,RXEND_INIT);
ivo_n 19:58e840279555 268 #endif
ivo_n 19:58e840279555 269
ivo_n 19:58e840279555 270 writeRegPair(ERXRDPTL, tmp);
hudakz 9:a156d3de5647 271 }
hudakz 9:a156d3de5647 272
hudakz 9:a156d3de5647 273 /**
hudakz 9:a156d3de5647 274 * @brief
hudakz 9:a156d3de5647 275 * @note
hudakz 9:a156d3de5647 276 * @param
hudakz 9:a156d3de5647 277 * @retval
hudakz 9:a156d3de5647 278 */
hudakz 14:7648334eb41b 279 size_t Enc28j60Eth::blockSize(memhandle handle)
hudakz 9:a156d3de5647 280 {
hudakz 9:a156d3de5647 281 return handle == NOBLOCK ? 0 : handle == UIP_RECEIVEBUFFERHANDLE ? receivePkt.size : blocks[handle].size;
hudakz 9:a156d3de5647 282 }
hudakz 9:a156d3de5647 283
hudakz 9:a156d3de5647 284 /**
hudakz 9:a156d3de5647 285 * @brief
hudakz 9:a156d3de5647 286 * @note
hudakz 9:a156d3de5647 287 * @param
hudakz 9:a156d3de5647 288 * @retval
hudakz 9:a156d3de5647 289 */
hudakz 11:647d53d146f1 290 void Enc28j60Eth::sendPacket(memhandle handle)
hudakz 9:a156d3de5647 291 {
hudakz 9:a156d3de5647 292 memblock* packet = &blocks[handle];
hudakz 9:a156d3de5647 293 uint16_t start = packet->begin - 1;
hudakz 9:a156d3de5647 294 uint16_t end = start + packet->size;
hudakz 9:a156d3de5647 295
hudakz 9:a156d3de5647 296 // backup data at control-byte position
hudakz 9:a156d3de5647 297 uint8_t data = readByte(start);
hudakz 9:a156d3de5647 298 // write control-byte (if not 0 anyway)
hudakz 9:a156d3de5647 299 if (data)
hudakz 9:a156d3de5647 300 writeByte(start, 0);
hudakz 9:a156d3de5647 301
hudakz 9:a156d3de5647 302 #ifdef ENC28J60DEBUG
ivo_n 19:58e840279555 303 printf("sendPacket(%d) [%d-%d]\r\n", handle, start, end);
ivo_n 19:58e840279555 304 int j = 1;
ivo_n 19:58e840279555 305 for (uint16_t i = start+1; i <= end; i++) {
ivo_n 19:58e840279555 306 printf("%02x ", readByte(i));
ivo_n 19:58e840279555 307 if (j%8==0) printf(" ");
ivo_n 19:58e840279555 308 if (j%16==0) printf("\r\n");
ivo_n 19:58e840279555 309 j++;
hudakz 9:a156d3de5647 310 }
hudakz 9:a156d3de5647 311
hudakz 9:a156d3de5647 312 printf("\r\n");
hudakz 9:a156d3de5647 313 #endif
hudakz 9:a156d3de5647 314 // TX start
hudakz 9:a156d3de5647 315
hudakz 9:a156d3de5647 316 writeRegPair(ETXSTL, start);
hudakz 9:a156d3de5647 317
hudakz 9:a156d3de5647 318 // Set the TXND pointer to correspond to the packet size given
hudakz 9:a156d3de5647 319 writeRegPair(ETXNDL, end);
hudakz 9:a156d3de5647 320
hudakz 9:a156d3de5647 321 // send the contents of the transmit buffer onto the network
hudakz 9:a156d3de5647 322 writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
hudakz 9:a156d3de5647 323
hudakz 9:a156d3de5647 324 // Reset the transmit logic problem. See Rev. B4 Silicon Errata point 12.
hudakz 9:a156d3de5647 325 if ((readReg(EIR) & EIR_TXERIF)) {
hudakz 9:a156d3de5647 326 writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRTS);
hudakz 9:a156d3de5647 327 }
hudakz 9:a156d3de5647 328
hudakz 9:a156d3de5647 329 //restore data on control-byte position
hudakz 9:a156d3de5647 330 if (data)
hudakz 9:a156d3de5647 331 writeByte(start, data);
hudakz 9:a156d3de5647 332 }
hudakz 9:a156d3de5647 333
hudakz 9:a156d3de5647 334 /**
hudakz 9:a156d3de5647 335 * @brief
hudakz 9:a156d3de5647 336 * @note
hudakz 9:a156d3de5647 337 * @param
hudakz 9:a156d3de5647 338 * @retval
hudakz 9:a156d3de5647 339 */
hudakz 11:647d53d146f1 340 uint16_t Enc28j60Eth::setReadPtr(memhandle handle, memaddress position, uint16_t len)
hudakz 9:a156d3de5647 341 {
hudakz 9:a156d3de5647 342 memblock* packet = handle == UIP_RECEIVEBUFFERHANDLE ? &receivePkt : &blocks[handle];
hudakz 9:a156d3de5647 343 memaddress start = handle == UIP_RECEIVEBUFFERHANDLE &&
hudakz 9:a156d3de5647 344 packet->begin +
hudakz 11:647d53d146f1 345 position > RXEND_INIT ? packet->begin +
hudakz 9:a156d3de5647 346 position -
hudakz 11:647d53d146f1 347 RXEND_INIT +
hudakz 9:a156d3de5647 348 RXSTART_INIT : packet->begin +
hudakz 9:a156d3de5647 349 position;
hudakz 9:a156d3de5647 350
hudakz 9:a156d3de5647 351 writeRegPair(ERDPTL, start);
hudakz 9:a156d3de5647 352
hudakz 9:a156d3de5647 353 if (len > packet->size - position)
hudakz 9:a156d3de5647 354 len = packet->size - position;
hudakz 9:a156d3de5647 355 return len;
hudakz 9:a156d3de5647 356 }
hudakz 9:a156d3de5647 357
hudakz 9:a156d3de5647 358 /**
hudakz 9:a156d3de5647 359 * @brief
hudakz 9:a156d3de5647 360 * @note
hudakz 9:a156d3de5647 361 * @param
hudakz 9:a156d3de5647 362 * @retval
hudakz 9:a156d3de5647 363 */
hudakz 11:647d53d146f1 364 uint16_t Enc28j60Eth::readPacket(memhandle handle, memaddress position, uint8_t* buffer, uint16_t len)
hudakz 9:a156d3de5647 365 {
hudakz 9:a156d3de5647 366 len = setReadPtr(handle, position, len);
hudakz 9:a156d3de5647 367 readBuffer(len, buffer);
hudakz 9:a156d3de5647 368 return len;
hudakz 9:a156d3de5647 369 }
hudakz 9:a156d3de5647 370
hudakz 9:a156d3de5647 371 /**
hudakz 9:a156d3de5647 372 * @brief
hudakz 9:a156d3de5647 373 * @note
hudakz 9:a156d3de5647 374 * @param
hudakz 9:a156d3de5647 375 * @retval
hudakz 9:a156d3de5647 376 */
hudakz 11:647d53d146f1 377 uint16_t Enc28j60Eth::writePacket(memhandle handle, memaddress position, uint8_t* buffer, uint16_t len)
hudakz 9:a156d3de5647 378 {
hudakz 9:a156d3de5647 379 memblock* packet = &blocks[handle];
hudakz 9:a156d3de5647 380 uint16_t start = packet->begin + position;
hudakz 9:a156d3de5647 381
hudakz 9:a156d3de5647 382 writeRegPair(EWRPTL, start);
hudakz 9:a156d3de5647 383
hudakz 9:a156d3de5647 384 if (len > packet->size - position)
hudakz 9:a156d3de5647 385 len = packet->size - position;
hudakz 9:a156d3de5647 386 writeBuffer(len, buffer);
hudakz 9:a156d3de5647 387 return len;
hudakz 9:a156d3de5647 388 }
hudakz 9:a156d3de5647 389
hudakz 9:a156d3de5647 390 /**
hudakz 9:a156d3de5647 391 * @brief
hudakz 9:a156d3de5647 392 * @note
hudakz 9:a156d3de5647 393 * @param
hudakz 9:a156d3de5647 394 * @retval
hudakz 9:a156d3de5647 395 */
hudakz 11:647d53d146f1 396 uint8_t Enc28j60Eth::readByte(uint16_t addr)
hudakz 9:a156d3de5647 397 {
hudakz 9:a156d3de5647 398 uint8_t result;
hudakz 9:a156d3de5647 399
hudakz 9:a156d3de5647 400 writeRegPair(ERDPTL, addr);
hudakz 9:a156d3de5647 401
hudakz 9:a156d3de5647 402 _cs = 0;
hudakz 9:a156d3de5647 403
hudakz 9:a156d3de5647 404 // issue read command
hudakz 9:a156d3de5647 405 _spi.write(ENC28J60_READ_BUF_MEM);
hudakz 9:a156d3de5647 406
hudakz 9:a156d3de5647 407 // read data
hudakz 9:a156d3de5647 408 result = _spi.write(0x00);
hudakz 15:53715cc81c63 409
hudakz 9:a156d3de5647 410 _cs = 1;
hudakz 15:53715cc81c63 411
hudakz 9:a156d3de5647 412 return(result);
hudakz 9:a156d3de5647 413 }
hudakz 9:a156d3de5647 414
hudakz 9:a156d3de5647 415 /**
hudakz 9:a156d3de5647 416 * @brief
hudakz 9:a156d3de5647 417 * @note
hudakz 9:a156d3de5647 418 * @param
hudakz 9:a156d3de5647 419 * @retval
hudakz 9:a156d3de5647 420 */
hudakz 11:647d53d146f1 421 void Enc28j60Eth::writeByte(uint16_t addr, uint8_t data)
hudakz 9:a156d3de5647 422 {
hudakz 9:a156d3de5647 423 writeRegPair(EWRPTL, addr);
hudakz 9:a156d3de5647 424
hudakz 9:a156d3de5647 425 _cs = 0;
hudakz 9:a156d3de5647 426
hudakz 9:a156d3de5647 427 // issue write command
hudakz 9:a156d3de5647 428 _spi.write(ENC28J60_WRITE_BUF_MEM);
hudakz 9:a156d3de5647 429
hudakz 9:a156d3de5647 430 // write data
hudakz 9:a156d3de5647 431 _spi.write(data);
hudakz 15:53715cc81c63 432
hudakz 9:a156d3de5647 433 _cs = 1;
hudakz 9:a156d3de5647 434 }
hudakz 9:a156d3de5647 435
hudakz 9:a156d3de5647 436 /**
hudakz 9:a156d3de5647 437 * @brief
hudakz 9:a156d3de5647 438 * @note
hudakz 9:a156d3de5647 439 * @param
hudakz 9:a156d3de5647 440 * @retval
hudakz 9:a156d3de5647 441 */
hudakz 11:647d53d146f1 442 void Enc28j60Eth::copyPacket
hudakz 9:a156d3de5647 443 (
hudakz 9:a156d3de5647 444 memhandle dest_pkt,
hudakz 9:a156d3de5647 445 memaddress dest_pos,
hudakz 9:a156d3de5647 446 memhandle src_pkt,
hudakz 9:a156d3de5647 447 memaddress src_pos,
hudakz 9:a156d3de5647 448 uint16_t len
hudakz 9:a156d3de5647 449 )
hudakz 9:a156d3de5647 450 {
hudakz 9:a156d3de5647 451 memblock* dest = &blocks[dest_pkt];
hudakz 9:a156d3de5647 452 memblock* src = src_pkt == UIP_RECEIVEBUFFERHANDLE ? &receivePkt : &blocks[src_pkt];
hudakz 9:a156d3de5647 453 memaddress start = src_pkt == UIP_RECEIVEBUFFERHANDLE &&
hudakz 9:a156d3de5647 454 src->begin +
hudakz 11:647d53d146f1 455 src_pos > RXEND_INIT ? src->begin +
hudakz 9:a156d3de5647 456 src_pos -
hudakz 11:647d53d146f1 457 RXEND_INIT +
hudakz 9:a156d3de5647 458 RXSTART_INIT : src->begin +
hudakz 9:a156d3de5647 459 src_pos;
hudakz 9:a156d3de5647 460 enc28j60_mempool_block_move_callback(dest->begin + dest_pos, start, len);
hudakz 9:a156d3de5647 461
hudakz 9:a156d3de5647 462 // Move the RX read pointer to the start of the next received packet
hudakz 9:a156d3de5647 463 // This frees the memory we just read out
hudakz 11:647d53d146f1 464 //setERXRDPT();
hudakz 9:a156d3de5647 465 }
hudakz 9:a156d3de5647 466
hudakz 9:a156d3de5647 467 /**
hudakz 9:a156d3de5647 468 * @brief
hudakz 9:a156d3de5647 469 * @note
hudakz 9:a156d3de5647 470 * @param
hudakz 9:a156d3de5647 471 * @retval
hudakz 9:a156d3de5647 472 */
hudakz 11:647d53d146f1 473 void Enc28j60Eth::freePacket()
hudakz 9:a156d3de5647 474 {
hudakz 9:a156d3de5647 475 setERXRDPT();
hudakz 9:a156d3de5647 476 }
hudakz 9:a156d3de5647 477
hudakz 9:a156d3de5647 478 /**
hudakz 9:a156d3de5647 479 * @brief
hudakz 9:a156d3de5647 480 * @note
hudakz 9:a156d3de5647 481 * @param
hudakz 9:a156d3de5647 482 * @retval
hudakz 9:a156d3de5647 483 */
hudakz 11:647d53d146f1 484 uint8_t Enc28j60Eth::readOp(uint8_t op, uint8_t address)
hudakz 9:a156d3de5647 485 {
hudakz 9:a156d3de5647 486 uint8_t result;
hudakz 9:a156d3de5647 487
hudakz 9:a156d3de5647 488 _cs = 0;
hudakz 9:a156d3de5647 489
hudakz 9:a156d3de5647 490 // issue read command
hudakz 9:a156d3de5647 491 _spi.write(op | (address & ADDR_MASK));
hudakz 9:a156d3de5647 492
hudakz 9:a156d3de5647 493 // read data
hudakz 9:a156d3de5647 494 result = _spi.write(0x00);
hudakz 9:a156d3de5647 495
hudakz 9:a156d3de5647 496 // do dummy read if needed (for mac and mii, see datasheet page 29)
hudakz 9:a156d3de5647 497 if (address & 0x80)
hudakz 9:a156d3de5647 498 result = _spi.write(0x00);
hudakz 9:a156d3de5647 499
hudakz 9:a156d3de5647 500 _cs = 1;
hudakz 9:a156d3de5647 501 return(result);
hudakz 9:a156d3de5647 502 }
hudakz 9:a156d3de5647 503
hudakz 9:a156d3de5647 504 /**
hudakz 9:a156d3de5647 505 * @brief
hudakz 9:a156d3de5647 506 * @note
hudakz 9:a156d3de5647 507 * @param
hudakz 9:a156d3de5647 508 * @retval
hudakz 9:a156d3de5647 509 */
hudakz 11:647d53d146f1 510 void Enc28j60Eth::writeOp(uint8_t op, uint8_t address, uint8_t data)
hudakz 9:a156d3de5647 511 {
hudakz 9:a156d3de5647 512 _cs = 0;
hudakz 9:a156d3de5647 513
hudakz 9:a156d3de5647 514 // issue write command
hudakz 9:a156d3de5647 515 _spi.write(op | (address & ADDR_MASK));
hudakz 9:a156d3de5647 516
hudakz 9:a156d3de5647 517 // write data
hudakz 9:a156d3de5647 518 _spi.write(data);
hudakz 15:53715cc81c63 519
hudakz 9:a156d3de5647 520 _cs = 1;
hudakz 9:a156d3de5647 521 }
hudakz 9:a156d3de5647 522
hudakz 9:a156d3de5647 523 /**
hudakz 9:a156d3de5647 524 * @brief
hudakz 9:a156d3de5647 525 * @note
hudakz 9:a156d3de5647 526 * @param
hudakz 9:a156d3de5647 527 * @retval
hudakz 9:a156d3de5647 528 */
hudakz 11:647d53d146f1 529 void Enc28j60Eth::readBuffer(uint16_t len, uint8_t* data)
hudakz 9:a156d3de5647 530 {
hudakz 9:a156d3de5647 531 _cs = 0;
hudakz 9:a156d3de5647 532
hudakz 9:a156d3de5647 533 // issue read command
hudakz 9:a156d3de5647 534 _spi.write(ENC28J60_READ_BUF_MEM);
hudakz 15:53715cc81c63 535
hudakz 15:53715cc81c63 536 // read data
hudakz 9:a156d3de5647 537 while (len) {
hudakz 9:a156d3de5647 538 len--;
hudakz 9:a156d3de5647 539 *data = _spi.write(0x00);
hudakz 9:a156d3de5647 540 data++;
hudakz 9:a156d3de5647 541 }
hudakz 9:a156d3de5647 542
hudakz 9:a156d3de5647 543 *data = '\0';
hudakz 15:53715cc81c63 544
hudakz 9:a156d3de5647 545 _cs = 1;
hudakz 9:a156d3de5647 546 }
hudakz 9:a156d3de5647 547
hudakz 9:a156d3de5647 548 /**
hudakz 9:a156d3de5647 549 * @brief
hudakz 9:a156d3de5647 550 * @note
hudakz 9:a156d3de5647 551 * @param
hudakz 9:a156d3de5647 552 * @retval
hudakz 9:a156d3de5647 553 */
hudakz 11:647d53d146f1 554 void Enc28j60Eth::writeBuffer(uint16_t len, uint8_t* data)
hudakz 9:a156d3de5647 555 {
hudakz 9:a156d3de5647 556 _cs = 0;
hudakz 9:a156d3de5647 557
hudakz 9:a156d3de5647 558 // issue write command
hudakz 9:a156d3de5647 559 _spi.write(ENC28J60_WRITE_BUF_MEM);
hudakz 15:53715cc81c63 560
hudakz 15:53715cc81c63 561 // write data
hudakz 9:a156d3de5647 562 while (len) {
hudakz 9:a156d3de5647 563 len--;
hudakz 9:a156d3de5647 564 _spi.write(*data);
hudakz 9:a156d3de5647 565 data++;
hudakz 9:a156d3de5647 566 }
hudakz 9:a156d3de5647 567
hudakz 9:a156d3de5647 568 _cs = 1;
hudakz 9:a156d3de5647 569 }
hudakz 9:a156d3de5647 570
hudakz 9:a156d3de5647 571 /**
hudakz 9:a156d3de5647 572 * @brief
hudakz 9:a156d3de5647 573 * @note
hudakz 9:a156d3de5647 574 * @param
hudakz 9:a156d3de5647 575 * @retval
hudakz 9:a156d3de5647 576 */
hudakz 11:647d53d146f1 577 void Enc28j60Eth::setBank(uint8_t address)
hudakz 9:a156d3de5647 578 {
hudakz 9:a156d3de5647 579 // set the bank (if needed)
hudakz 9:a156d3de5647 580 if ((address & BANK_MASK) != bank) {
hudakz 9:a156d3de5647 581 // set the bank
hudakz 9:a156d3de5647 582 writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, (ECON1_BSEL1 | ECON1_BSEL0));
hudakz 9:a156d3de5647 583 writeOp(ENC28J60_BIT_FIELD_SET, ECON1, (address & BANK_MASK) >> 5);
hudakz 9:a156d3de5647 584 bank = (address & BANK_MASK);
hudakz 9:a156d3de5647 585 }
hudakz 9:a156d3de5647 586 }
hudakz 9:a156d3de5647 587
hudakz 9:a156d3de5647 588 /**
hudakz 9:a156d3de5647 589 * @brief
hudakz 9:a156d3de5647 590 * @note
hudakz 9:a156d3de5647 591 * @param
hudakz 9:a156d3de5647 592 * @retval
hudakz 9:a156d3de5647 593 */
hudakz 11:647d53d146f1 594 uint8_t Enc28j60Eth::readReg(uint8_t address)
hudakz 9:a156d3de5647 595 {
hudakz 9:a156d3de5647 596 // set the bank
hudakz 9:a156d3de5647 597 setBank(address);
hudakz 9:a156d3de5647 598
hudakz 9:a156d3de5647 599 // do the read
hudakz 9:a156d3de5647 600 return readOp(ENC28J60_READ_CTRL_REG, address);
hudakz 9:a156d3de5647 601 }
hudakz 9:a156d3de5647 602
hudakz 9:a156d3de5647 603 /**
hudakz 9:a156d3de5647 604 * @brief
hudakz 9:a156d3de5647 605 * @note
hudakz 9:a156d3de5647 606 * @param
hudakz 9:a156d3de5647 607 * @retval
hudakz 9:a156d3de5647 608 */
hudakz 11:647d53d146f1 609 void Enc28j60Eth::writeReg(uint8_t address, uint8_t data)
hudakz 9:a156d3de5647 610 {
hudakz 9:a156d3de5647 611 // set the bank
hudakz 9:a156d3de5647 612 setBank(address);
hudakz 9:a156d3de5647 613
hudakz 9:a156d3de5647 614 // do the write
hudakz 9:a156d3de5647 615 writeOp(ENC28J60_WRITE_CTRL_REG, address, data);
hudakz 9:a156d3de5647 616 }
hudakz 9:a156d3de5647 617
hudakz 9:a156d3de5647 618 /**
hudakz 9:a156d3de5647 619 * @brief
hudakz 9:a156d3de5647 620 * @note
hudakz 9:a156d3de5647 621 * @param
hudakz 9:a156d3de5647 622 * @retval
hudakz 9:a156d3de5647 623 */
hudakz 11:647d53d146f1 624 void Enc28j60Eth::writeRegPair(uint8_t address, uint16_t data)
hudakz 9:a156d3de5647 625 {
hudakz 9:a156d3de5647 626 // set the bank
hudakz 9:a156d3de5647 627 setBank(address);
hudakz 9:a156d3de5647 628
hudakz 9:a156d3de5647 629 // do the write
hudakz 9:a156d3de5647 630 writeOp(ENC28J60_WRITE_CTRL_REG, address, (data & 0xFF));
hudakz 9:a156d3de5647 631 writeOp(ENC28J60_WRITE_CTRL_REG, address + 1, (data) >> 8);
hudakz 9:a156d3de5647 632 }
hudakz 9:a156d3de5647 633
hudakz 9:a156d3de5647 634 /**
hudakz 9:a156d3de5647 635 * @brief
hudakz 9:a156d3de5647 636 * @note
hudakz 9:a156d3de5647 637 * @param
hudakz 9:a156d3de5647 638 * @retval
hudakz 9:a156d3de5647 639 */
hudakz 11:647d53d146f1 640 void Enc28j60Eth::phyWrite(uint8_t address, uint16_t data)
hudakz 9:a156d3de5647 641 {
hudakz 9:a156d3de5647 642 // set the PHY register address
hudakz 9:a156d3de5647 643 writeReg(MIREGADR, address);
hudakz 9:a156d3de5647 644
hudakz 9:a156d3de5647 645 // write the PHY data
hudakz 9:a156d3de5647 646 writeRegPair(MIWRL, data);
hudakz 9:a156d3de5647 647
hudakz 9:a156d3de5647 648 // wait until the PHY write completes
hudakz 9:a156d3de5647 649 while (readReg(MISTAT) & MISTAT_BUSY) {
hudakz 9:a156d3de5647 650 wait_us(15);
hudakz 9:a156d3de5647 651 }
hudakz 9:a156d3de5647 652 }
hudakz 9:a156d3de5647 653
hudakz 9:a156d3de5647 654 /**
hudakz 9:a156d3de5647 655 * @brief
hudakz 9:a156d3de5647 656 * @note
hudakz 9:a156d3de5647 657 * @param
hudakz 9:a156d3de5647 658 * @retval
hudakz 9:a156d3de5647 659 */
hudakz 11:647d53d146f1 660 uint16_t Enc28j60Eth::phyRead(uint8_t address)
hudakz 9:a156d3de5647 661 {
hudakz 9:a156d3de5647 662 writeReg(MIREGADR, address);
hudakz 9:a156d3de5647 663 writeReg(MICMD, MICMD_MIIRD);
hudakz 9:a156d3de5647 664
hudakz 9:a156d3de5647 665 // wait until the PHY read completes
hudakz 9:a156d3de5647 666 while (readReg(MISTAT) & MISTAT_BUSY) {
hudakz 9:a156d3de5647 667 wait_us(15);
hudakz 9:a156d3de5647 668 } //and MIRDH
hudakz 9:a156d3de5647 669
hudakz 9:a156d3de5647 670 writeReg(MICMD, 0);
hudakz 9:a156d3de5647 671 return(readReg(MIRDL) | readReg(MIRDH) << 8);
hudakz 9:a156d3de5647 672 }
hudakz 9:a156d3de5647 673
hudakz 9:a156d3de5647 674 /**
hudakz 9:a156d3de5647 675 * @brief
hudakz 9:a156d3de5647 676 * @note
hudakz 9:a156d3de5647 677 * @param
hudakz 9:a156d3de5647 678 * @retval
hudakz 9:a156d3de5647 679 */
hudakz 11:647d53d146f1 680 void Enc28j60Eth::clkout(uint8_t clk)
hudakz 9:a156d3de5647 681 {
hudakz 9:a156d3de5647 682 //setup clkout: 2 is 12.5MHz:
hudakz 9:a156d3de5647 683 writeReg(ECOCON, clk & 0x7);
hudakz 9:a156d3de5647 684 }
hudakz 9:a156d3de5647 685
hudakz 9:a156d3de5647 686 // read the revision of the chip:
hudakz 11:647d53d146f1 687 uint8_t Enc28j60Eth::getrev()
hudakz 9:a156d3de5647 688 {
hudakz 9:a156d3de5647 689 return(readReg(EREVID));
hudakz 9:a156d3de5647 690 }
hudakz 9:a156d3de5647 691
hudakz 9:a156d3de5647 692 /**
hudakz 9:a156d3de5647 693 * @brief
hudakz 9:a156d3de5647 694 * @note
hudakz 9:a156d3de5647 695 * @param
hudakz 9:a156d3de5647 696 * @retval
hudakz 9:a156d3de5647 697 */
hudakz 11:647d53d146f1 698 uint16_t Enc28j60Eth::chksum(uint16_t sum, memhandle handle, memaddress pos, uint16_t len)
hudakz 9:a156d3de5647 699 {
hudakz 9:a156d3de5647 700 uint8_t spdr;
hudakz 9:a156d3de5647 701 uint16_t t;
hudakz 9:a156d3de5647 702 uint16_t i;
hudakz 9:a156d3de5647 703
hudakz 9:a156d3de5647 704 len = setReadPtr(handle, pos, len) - 1;
hudakz 9:a156d3de5647 705 _cs = 0;
hudakz 9:a156d3de5647 706
hudakz 9:a156d3de5647 707 // issue read command
hudakz 9:a156d3de5647 708 spdr = _spi.write(ENC28J60_READ_BUF_MEM);
hudakz 9:a156d3de5647 709 for (i = 0; i < len; i += 2) {
hudakz 9:a156d3de5647 710 // read data
hudakz 9:a156d3de5647 711 spdr = _spi.write(0x00);
hudakz 9:a156d3de5647 712 t = spdr << 8;
hudakz 9:a156d3de5647 713 spdr = _spi.write(0x00);
hudakz 9:a156d3de5647 714 t += spdr;
hudakz 9:a156d3de5647 715 sum += t;
hudakz 9:a156d3de5647 716 if (sum < t) {
hudakz 9:a156d3de5647 717 sum++; /* carry */
hudakz 9:a156d3de5647 718 }
hudakz 9:a156d3de5647 719 }
hudakz 9:a156d3de5647 720
hudakz 9:a156d3de5647 721 if (i == len) {
hudakz 9:a156d3de5647 722 spdr = _spi.write(0x00);
hudakz 9:a156d3de5647 723 t = (spdr << 8) + 0;
hudakz 9:a156d3de5647 724 sum += t;
hudakz 9:a156d3de5647 725 if (sum < t) {
hudakz 9:a156d3de5647 726 sum++; /* carry */
hudakz 9:a156d3de5647 727 }
hudakz 9:a156d3de5647 728 }
hudakz 9:a156d3de5647 729
hudakz 9:a156d3de5647 730 _cs = 1;
hudakz 9:a156d3de5647 731
hudakz 9:a156d3de5647 732 /* Return sum in host byte order. */
hudakz 9:a156d3de5647 733 return sum;
hudakz 9:a156d3de5647 734 }
hudakz 9:a156d3de5647 735
hudakz 9:a156d3de5647 736 /**
hudakz 9:a156d3de5647 737 * @brief
hudakz 9:a156d3de5647 738 * @note
hudakz 9:a156d3de5647 739 * @param
hudakz 9:a156d3de5647 740 * @retval
hudakz 9:a156d3de5647 741 */
hudakz 11:647d53d146f1 742 void Enc28j60Eth::powerOff()
hudakz 9:a156d3de5647 743 {
hudakz 9:a156d3de5647 744 writeOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_RXEN);
hudakz 16:269f652b4d0b 745 #if MBED_MAJOR_VERSION == 2
hudakz 9:a156d3de5647 746 wait_ms(50);
hudakz 16:269f652b4d0b 747 #else
hudakz 16:269f652b4d0b 748 thread_sleep_for(50);
hudakz 16:269f652b4d0b 749 #endif
hudakz 9:a156d3de5647 750 writeOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_VRPS);
hudakz 16:269f652b4d0b 751 #if MBED_MAJOR_VERSION == 2
hudakz 9:a156d3de5647 752 wait_ms(50);
hudakz 16:269f652b4d0b 753 #else
hudakz 16:269f652b4d0b 754 thread_sleep_for(50);
hudakz 16:269f652b4d0b 755 #endif
hudakz 9:a156d3de5647 756 writeOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PWRSV);
hudakz 9:a156d3de5647 757 }
hudakz 9:a156d3de5647 758
hudakz 9:a156d3de5647 759 /**
hudakz 9:a156d3de5647 760 * @brief
hudakz 9:a156d3de5647 761 * @note
hudakz 9:a156d3de5647 762 * @param
hudakz 9:a156d3de5647 763 * @retval
hudakz 9:a156d3de5647 764 */
hudakz 11:647d53d146f1 765 void Enc28j60Eth::powerOn()
hudakz 9:a156d3de5647 766 {
hudakz 9:a156d3de5647 767 writeOp(ENC28J60_BIT_FIELD_CLR, ECON2, ECON2_PWRSV);
hudakz 16:269f652b4d0b 768 #if MBED_MAJOR_VERSION == 2
hudakz 9:a156d3de5647 769 wait_ms(50);
hudakz 16:269f652b4d0b 770 #else
hudakz 16:269f652b4d0b 771 thread_sleep_for(50);
hudakz 16:269f652b4d0b 772 #endif
hudakz 9:a156d3de5647 773 writeOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
hudakz 16:269f652b4d0b 774 #if MBED_MAJOR_VERSION == 2
hudakz 9:a156d3de5647 775 wait_ms(50);
hudakz 16:269f652b4d0b 776 #else
hudakz 16:269f652b4d0b 777 thread_sleep_for(50);
hudakz 16:269f652b4d0b 778 #endif
hudakz 9:a156d3de5647 779 }
hudakz 9:a156d3de5647 780
hudakz 9:a156d3de5647 781 /**
hudakz 9:a156d3de5647 782 * @brief
hudakz 9:a156d3de5647 783 * @note
hudakz 9:a156d3de5647 784 * @param
hudakz 9:a156d3de5647 785 * @retval
hudakz 9:a156d3de5647 786 */
hudakz 11:647d53d146f1 787 bool Enc28j60Eth::linkStatus()
hudakz 9:a156d3de5647 788 {
hudakz 9:a156d3de5647 789 return(phyRead(PHSTAT2) & 0x0400) > 0;
hudakz 9:a156d3de5647 790 }