Franco Patane / Mbed OS Si5351A_Clock_generator

Dependencies:   Si5351A

Fork of Check_Si5351A_Clock_generator by Kenji Arai

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main.cpp

00001 #include "mbed.h"
00002 #include "si5351a.h"
00003 
00004 Serial pc(USBTX, USBRX);
00005  
00006 I2C i2c(I2C_SDA, I2C_SCL);       // communication with Si5351A
00007 SI5351A clk(i2c, 24998410UL);     // Base clock = 25MHz
00008  
00009 int main() {
00010         uint32_t num=145000000;
00011     
00012       clk.set_frequency(SI5351_CLK0, 7000000);   // CLK0=7MHz
00013     
00014     clk.set_frequency(SI5351_CLK1,num);   // CLK0=145MHz
00015         
00016   while(true) {
00017  
00018      //wait(1);
00019       num = num + 10000;
00020       
00021      pc.printf("%d scrivo -\r\n", num);
00022 
00023    /* clk.set_frequency(SI5351_CLK1,num); 
00024     if (num>146000000) 
00025     {
00026          num=145000000;
00027          }*/
00028   } 
00029 }
00030  
00031 // ---------  CAUTION & RESTRICTION -----------------------------------------
00032 // 1) SETTING METHOD
00033 // 2.6KHz~100MHz: fixed PLL(around 900 or around 600MHz), fractional divider
00034 // 100~150MHz: fractional PLL 600-900MHz, fixed divider 6
00035 // 150~200MHz: fractional PLL 600-900MHz, fixed divider 4
00036 //
00037 // 2) RESOURCE USAGE
00038 // PLLA -> only for CLK0 (You can change freqency any time to any value.)
00039 // PLLB -> use for bothe CLK1 & CLK2
00040 // If you set a freq. less than 100MHz,
00041 //    You can change both CLK1 & CLK2 independently.
00042 // Over 100MHz, you may have a trouble becase need to change PLLB freq.
00043 //
00044 // 3) DISCONTINUITY
00045 // If you use multiple output, you will lose output signal when you change
00046 //   the output frequency even not specific CLKn during I2C acccess. 
00047 // --------------------------------------------------------------------------
00048